WO2022104505A1

WO2022104505A1 - A novel gap fill and cell structure for improved selector thermal reliability for 3d pcm

Info

Publication number: WO2022104505A1
Application number: PCT/CN2020/129307
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2022-05-27
Also published as: CN112585758B; CN112585758A

Abstract

A three-dimensional memory cell structure includes a plurality of parallel, vertically extending memory cells (304) in a mutually spaced planar arrangement including gaps between the memory cells (304). The structure further includes two layers of filler filling the gaps including a lower layer of filler (326) and an upper layer of filler (320), the lower layer (326) having greater thermal conductivity than the upper layer (320). The lower layer of filler (326) may be oxide. The greater thermal conductivity of the lower layer of filler (326) enables heat dissipation from selectors (316) in the memory cells (304) while the upper layer of filler (320) prevents cross talk between phase change elements (314) of the memory cells (304).

Description

A NOVEL GAP FILL AND CELL STRUCTURE FOR IMPROVED SELECTOR THERMAL RELIABILITY FOR 3D PCM

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to reducing programming current and thermal cross talk in adjacent memory cells.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. Three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.

Phase-change memory (PCM) is a non-volatile solid-state memory technology that exploits reversible, thermally-assisted switching of phase-change materials like chalcogenide compounds such as GST (Germanium-Antimony-Tellurium) , between states with different electrical resistance. The fundamental storage unit (the “cell” ) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. Programmable cell-states can be used to represent different data values, permitting storage of information.

PCM cells are programmed or erased by thermal self heating to induce an amorphous or crystalline state to denote 1 and 0. Programming current is directly proportional to the size and cross-sectional area of the PCM cell. In single-level PCM devices, each cell can be set to one of two states, a “SET” state and a “RESET” state, permitting storage of one bit per cell. In the RESET state, which corresponds to a wholly amorphous state of the phase-change material, the electrical resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase-change material can be transformed into a low-resistance, fully-crystalline state. This low-resistance state provides the SET state of the cell. If the cell is then heated to a high temperature, above the melting point of the phase-change material, the material reverts to the fully-amorphous RESET state on rapid cooling.

Due to the nature of thermal self heating, cross talk occurs when an adjacent cell is programmed. Cross talk is interference between signals. Due to process-technology scaling, the spacing between adjacent interconnects shrinks. Switching on one signal, can influence another signal. This may, in the worst cases cause a change in value of another cell, or it could delay a signal transition affecting timing. This is classified as a signal integrity issue.

In addition, large programming current requirements also lend to large program voltage requirements due to IR drop (IR =voltage=current x resistance) . Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase-change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes Joule heating of the phase-change material to an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. An applied read voltage causes current to flow through the cell, this current being dependent on resistance of the cell. Measurement of the cell current therefore provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing the resistance metric with predefined reference levels. Programming current (I) is typically in the order of 100-200μA. The voltage drop may be significant if the write line or word line (WL) and bit line (BL) in the cell encounters large resistance and the current is too large.

A 3D X-point memory is formed when the WL and the BL are formed perpendicular to each other. The memory cell is formed self-aligned at the cross point of the WL and BL. The memory cell is of a vertical square pillar shape with single material composition.

Thus, there is still a need for such a memory cell that provides reduced programming current and reduced thermal cross talk.

SUMMARY

The following summary is included in order to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview and as such it is not intended to particularly identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a summarized format.

According to an arrangement, a three-dimensional memory cell structure includes a plurality of parallel, vertically extending memory cells in a mutually spaced planar arrangement including gaps between the memory cells. The structure further includes two layers of filler filling the gaps including a lower layer of filler and an upper layer of filler, the lower layer having greater thermal conductivity than the upper layer.

According to an aspect, the lower layer of filler is oxide.

According to an aspect, the memory cells each include a phase change material layer located above a selector layer, and the upper layer of filler extends below the phase change layers.

According to an aspect, the selector layer is an ovonic threshold switch layer.

According to an aspect, the plurality of memory cells is a first plurality of memory cells, and the structure further includes a second plurality of parallel, vertically extending second row memory cells in a mutually spaced planar arrangement including second gaps between the second row memory cells, the second plurality of memory cells extending along a plane parallel to and located above a plane along which the first plurality of memory cells extends. The two layers of filler filling the second gaps including a second lower layer of filler and a second upper layer of filler, the second lower layer having greater thermal conductivity than the second upper layer.

According to an arrangement, a method for forming a three-dimensional cross point memory array includes forming a plurality of parallel, vertically extending memory cells in a mutually spaced planar arrangement including gaps between the memory cells. The method also includes creating a first filler layer by filling the gaps with a first filler material, removing an upper portion of the first filler layer from the gaps, and creating a second filler layer by backfilling the gaps with a second filler material on top of the first filler layer.

According to an aspect, the first filler material has a greater thermal conductivity than the second filler layer.

According to an aspect, each memory cell includes a phase change material layer and a selector layer, and the removing step includes removing all first filler material above a boundary plane, the boundary plane being parallel to the planar arrangement and being located below the phase change material layer.

According to an aspect, the selector layer is an ovonic threshold switch layer.

According to an aspect, the forming step includes depositing a stack of materials on a planar surface, cutting a first plurality of parallel grooves through the stack, cutting a second plurality of parallel grooves through the stack, the second plurality of parallel grooves extending perpendicular to the first plurality of parallel grooves.

According to an aspect, the steps of creating the first filler layer, removing an upper portion of the first filler layer, and creating the second filler layer are performed after the step of cutting the first plurality of parallel grooves and before the step of cutting a second plurality of parallel grooves.

According to an aspect, the steps of creating the first filler layer, removing an upper portion of the first filler layer, and creating the second filler layer are repeated after the step of cutting the second plurality of parallel grooves.

According to an aspect, the method includes creating a planar surface on top of the memory cells and second filler layer, and forming a second row of memory cells on the planar surface.

According to an aspect, the method includes creating a third filler layer within gaps in the second row of memory cells, and creating a fourth filler layer on top of the third filler layer, the fourth filler layer having a third filler layer having a greater thermal conductivity than the fourth filler layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity.

However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

Figs. 1A and 1B are isometric views of a prior multi-section and a single section of three-dimensional cross point memory, respectively.

Fig. 2 is a plan view of a section of a three-dimensional cross point memory architecture.

Fig. 3 is a plan view of a section of a three-dimensional cross point memory architecture including a layer of low thermal resistance filler.

Fig. 4 is a plan view of the three-dimensional cross point memory in accordance with the embodiment of Fig. 3 showing deposition of a plurality of layers of material.

Fig. 5 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing etching of material stacks.

Fig. 6 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing deposition of a nitride layer and an oxide layer.

Fig. 7 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing deposition of filler material.

Fig. 8 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing etching of the filler material and backfilling with another filler material.

Fig. 9 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing polishing of a planar surface on top of the material stacks.

Figs. 10A and 10B are plan views of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing deposition of word line metal.

Fig. 11 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing etching of cell precursor stacks.

Fig. 12 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing deposition of filler material.

Fig. 13 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing etching of the filler material and backfilling with another filler material.

Fig. 14 is a plan view of the three dimensional cross point memory in accordance with the embodiment of FIG. 3 showing polishing of a planar surface on top of the word lines.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” and the like, merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer there between, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer there between (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substrate” as used herein may refer to any workpiece on which formation or treatment of material layers is desired. Non-limiting examples include silicon, germanium, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, aluminum nitride, glasses, combinations or alloys thereof, and other solid materials. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpattern. Furthermore, the substrate can include a wide array of semiconductor materials, including but not limited to silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term “horizontal” as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term “vertical” will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above” , “below” , “bottom” , “top” , “side” (e.g. sidewall) , “higher” , “lower” , “upper” , “over” , and “under” , are defined with respect to the horizontal plane. The term “on” means there is direct contact between the elements. The term “above” will allow for intervening elements.

As used herein, a material (e.g. a dielectric material or an electrode material) will be considered to be “crystalline” if it exhibits greater than or equal to 30%crystallinity as measured by a technique such as x-ray diffraction (XRD) . Amorphous material is considered non-crystalline.

As used herein, the terms “first, ” “second, ” and other ordinals will be understood to provide differentiation only, rather than imposing any specific spatial or temporal order.

As used herein, the term “oxide” (of an element) will be understood to include additional components besides the element and oxygen, including but not limited to a dopant or alloy. As used herein, the term “nitride” (of an element) will be understood to include additional components besides the element and nitrogen, including but not limited to a dopant or alloy.

The present technology is applied in the field of three-dimensional memory. A generalized prior example of a three-dimensional (3D) memory is shown in FIG. 1A. In particular, FIG. 1A is an isometric view of a section of three-dimensional cross point memory. The memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and second layer of memory cells is a number of word lines 15 extending in the X direction. Above the first layer of memory cells 5 are a number of first bit lines 20 extending along the Y direction, and below the second layer of memory cells is a number of second bit lines 25 extending along the Y direction. Further, as can be seen from the figure, the sequential structure of bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration. In any event, an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell.

In FIG. 1B, shown is a single section 100 of the cell structure in FIG. 1A. Shown is a top cell bit line 110 connected to a top cell stack 150. Stack 150 is composed of several layers that will be described herein in the improvement of this standard stack 150. Perpendicular to the top cell bit line 110 is top cell write line or word line 130 and bottom cell write line or word line 140. Connected to bottom cell write line or word line 140 is a bottom cell stack 160. Parallel to top cell bit line 110 is bottom cell bit line 120. Bottom cell bit line 120 is coupled to the bottom cell stack 160. Like cell stack 150, cell stack 160 is also made of several layers. FIGS. 1A and 1B illustrate the general structure of a 3D X-Point Memory cell that terminology is used herein to describe the improvement. The section includes a number of word lines, e.g. word lines 130, 140, extending in the X (horizontal) direction, a number of top cell bit lines, e.g.,

bit lines

110, 120, extending along the Y (vertical) direction and corresponding to a top cell array of memory cells 150, and a number of bottom cell bit lines extending along the vertical direction and corresponding to a bottom cell array of memory cells 150. The word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.

As recognized with the present technology described herein, the prior configuration as exemplified in FIGS. 1A and 1B is susceptible to cross talk from adjacent cells causing interference with the memory cells. The disclosed new configurations and material provide reduced cross talk and power required for the memory cell. The new configuration includes a reduced sized PCM layer in relation to the selector layer and/or electrode layers in its respective cell.

FIG. 2 is a plan view corresponding to the Y direction in FIG. 1A of a block 200 of two rows 202 of memory cells 204 with exemplary features for reducing cross-talk. Three cells 204 are illustrated per row 202, but it should be understood that the FIG. 2 represents a portion of a memory device, and quantities of cells 204 per row 202 greater than three are contemplated. The two rows 202 are separated by word lines 206 extending laterally, meaning horizontally in the plane of FIG. 2, and each cell 204 in the plane of FIG. 2 contacts a different bit line 208 at the vertically opposite end of each cell 204 from the bit line 208. In alternative arrangements, the two rows 202 may be separated by a single, shared word line 206. It should also be noted that the locations of the word lines 206 and bit lines 208 as illustrated throughout this application are merely exemplary, and could be reversed. The word lines 206 and bit lines 208 may be a tungsten based compound, or cobalt based compound and functions as a conductor among other things. Depending on the embodiment, the word lines 206 and bit lines 208 may be made of other materials that have conductive properties.

Each cell 204 includes a stack of layers of various materials. The cell stacks are similar in function and composition. The layers, listed from top to bottom, include a first electrode layer 212a, a phase change material (PCM) layer 214, a second electrode layer 212b, an selector layer 216 which may be, for example, an ovonic threshold switch (OTS) , and a third electrode layer 212c. Depending on the embodiment the

electrode layers

212a, 212b, 212c may be a carbon electrode or any other electrode known to one skilled in the art. The

electrode layers

212a, 212b, 212c can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon. Moreover, while the features described are particularly advantageous for multi-level cells, these features can also be applied to advantage in single-level cells in some embodiments. The PCM layer 214 may be a PCM cell made from any suitable PCM. First electrode layer 212a and PCM layer 214 are laterally narrower than second electrode layer 212b, selector layer 216, and third electrode layer 212c. Each bit line 208 has a lateral width equal to the adjacent electrode layer, 212a or 212c. In the illustrated arrangement, the bit lines 208 of the upper row 202 are laterally narrower than the bit lines 208 of the lower row 202. Block 200 rests on a substrate 210.

Insulating features for reducing cross talk include a nitride coat 218, a gap fill 220, a nitride barrier 222, and oxide 224. The nitride coats 218 in each row 202 extend along an entire height of the row 202 on either lateral side of each cell 204. The nitride of the nitride coat 218 and nitride barrier 222 may be any one of or any combination of TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials. The vertical portions of the nitride coats 218 are planar and extend along the lateral sides of the second electrode layer 212b, selector layer 216, and third electrode layer 212c, leaving space between each vertical portion of each nitride coat 218 and the first electrode layer 212a and PCM layer 214 of the corresponding cells 204. Similarly, space exists between each vertical portion of each nitride coat 218 in the upper row 202 and the bit line 208 of the corresponding cells 204 in the upper row 202, but not between the vertical portions of the nitride coats 218 in the lower row 202 and the bit line 208 of the corresponding cells 204 in the lower row 202. Low thermal conductivity gap fill 220 or upper level gap fill fills the space between the lateral portions of each nitride coat 218. Examples of gap fill 220 materials include, but are not limited to, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) and lead selenide (PbSe) and Cobalt based compounds and any combination thereof. Nitride barriers 222 extend vertically from the upper side of each second electrode layer 212b along both lateral sides of each PCM layer 214 and first electrode layer 212a and along both lateral sides of each bit line 208 in the upper row 202. Oxide 222 fills the lateral spaces between the nitride barriers 222 and the vertical portions of the nitride coats 218.

Gap fill 220 extending along the entire height of the nitride coats 218 as illustrated in FIG. 2 insulates the memory cells 204, and thereby limits thermal cross talk, but limits heat dissipation from the selector layer 216. FIG. 3 illustrates a block 300 according to another arrangement generally similar to block 200, and with like elements indicated by like numerals (i.e., numeral 206 indicates a word line in block 200 and numeral 306 indicates word lines in block 300) . Block 300 differs from block 200 at least by inclusion of additional oxide layer 326 or lower level gap fill between adjacent vertically extending portions of the nitride coats 318. The additional oxide 326 extends vertically from a horizontal portion at the bottom of each nitride coat 318 past an upper edge of the selector layer 316 in the same row 302, but not past an upper edge of the second electrode layer 312b of the same row 302. In the illustrated arrangement, the additional oxide 326 does not extend to the upper edge of the second electrode layer 312b of the same row 302, but in some arrangements the additional oxide layer 326 extends to a height even with the second electrode layer 312b of the same row 302. Depending on the embodiment, additional oxide layer 326 is a higher thermal conductivity gap fill than the gap fill 320 that is a lower thermal conductivity gap fill in comparison. That is, the additional oxide layer 326 is composed of a material or mixture of materials that has greater thermal conductivity than the material or materials of which the gap fill 320 is composed. In such examples, the gap fill 320 is any of the materials described above with regard to gap fill 220, and the additional oxide layer is any oxide material or oxide containing mixture having a greater thermal conductivity than the material or materials in the gap fill 320. Thus, the cells 304 of the block 300 are separated by a lower layer of filler and an upper layer of filler, and the lower layer of filler has a greater thermal conductivity than the upper layer of filler. The materials for additional oxide layer 326 and the gap fill 320 may or may not be the same depending on the implementation. Gap fill 320 extends vertically from the top of the additional oxide 326 to the top of the row 302. The additional oxide 326 permits greater heat dissipation from the selector layers 316 than the full length gap fill 220 of the block 200 of FIG. 2 while mitigating cross talk between the PCM layers 314.

FIGS. 4 –14 illustrate an embodiment and steps of a process for forming the block 300 of FIG. 3. As shown in FIG. 4, a bit line precursor layer 326, the third electrode layer 312c, selector layer 316, second electrode layer 312b, PCM layer 314, first electrode layer 312a, and a first sacrificial nitride layer 328, listed from bottom to top, are deposited according to suitable processes upon the substrate 310 to provide raw material for the lower row 302. An exemplary suitable deposition process here and for other deposition steps below includes chemical vapor deposition (CVD) . In this CVD, a vacuum deposition method is used to produce high quality, high-performance, solid materials. In typical CVD, the wafer, substrate, or other underlying structure is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. In a first etching step, parallel grooves extending in the X direction are etched down to the upper surface of the second electrode layer 312b to separate the first sacrificial nitride layer 328, first electrode layer 312a, and PCM layer 314 into parallel Y-direction stacks 303 extending in the Y direction, as shown in FIG. 5. A nitride barrier precursor layer 330 and an oxide layer 332 are deposited over the Y-direction stacks 303 to cover the upper surfaces of the first sacrificial nitride layer 328 and second electrode layer 312b and the sides of the first sacrificial nitride layer 330, first electrode layer 312a, and PCM layer 314, as shown in FIG. 6.

In a second etching step, grooves extending in the Y direction are etched all the way to the substrate 310 to separate the bit line precursor layer 326 into bit lines 308, followed by deposition of the nitride coat 318 and additional oxide 324 to result in the arrangement shown in FIG. 7. The grooves of the second etching step are narrower than, but centered within, the grooves of the first etching step, which leaves the bit lines 308, third electrode layers 312c, selector layers 316, and second electrode layers 312b wider in the X direction than the first sacrificial nitride layers 328, PCM layers 314 and first electrode layers 312a in each Y-direction stack 303. The second step further removes the oxide layer 332 and, optionally, some or the entire nitride barrier precursor layer 330 from the top of the first sacrificial nitride layers 328. The second etching step therefore separates the nitride barrier precursor layer 330 into the nitride barriers 322 shown in FIG. 7. Similarly, the second etching step separates the oxide layer 322 into the oxide 324 that extends along the nitride barriers 322. The combined width of the nitride barriers 322 and oxide 324 in the Y direction extends from the each lateral side of each first sacrificial nitride layer 328, first electrode layer 312a, and PCM layer 316 to a plane of the corresponding lateral side of a bit lines 308, third electrode layer 312c, selector layer 314, and second electrode layer 312b. Vertical portions of the nitride coat 318 therefore extend on the planes of each lateral side of the oxide 322 and each second electrode layer 312b, selector layer 316, third electrode layer 312c, bit line 308, and the remaining oxide 324. Additional oxide 326 fills spaces between laterally adjacent vertical portions of the nitride coat 318.

To provide the arrangement shown in FIG. 8, the additional oxide 326 is removed from the top surfaces of the nitride coat 318 by, for example, chemical mechanical polishing. A third etching step removes the additional oxide 326 from an area between the vertically extending portions of the nitride coat 318 that extends from the top of the nitride coat 318 at least to a height of the upper surfaces of the second electrode layers 312b but not past the lower surfaces of the second electrode layers 312b. Gap fill 326 is then deposited to fill the spaces between the vertically extending portions of the oxide coat 320 as illustrated in FIG. 7. Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) or flowable chemical vapor deposition (CVD) oxide.

Top down chemical mechanical polishing treatment removes all material down to the upper surface of the first electrode layers 312a as illustrated in FIG. 9. FIG. 10a illustrates a word line precursor layer 334 and second sacrificial nitride layer 336 deposition step. As shown in FIG. 10b, the word line precursor layer 334 and second sacrificial nitride layer 336 extend in the Y direction, along with the bit lines 308,

electrode layers

312a, 312b, 312c, selector layer 316, and PCM layer 314. A fourth etching step cuts grooves extending in the X direction through the sacrificial nitride layer 336, word line precursor layer 334, first electrode layer 312a, and PCM layer 314 to provide the arrangement shown in FIG. 11. As shown in FIG. 11, the fourth etching step separates the Y-direction stacks 303 into cell precursor stacks 305, and separates the word line precursor layer 334 into word lines 306.

Through a series of steps generally similar to those described above with regard to FIGS. 6 and 8, the cell precursor stacks 305 are separated down to the bit lines 308 and encapsulated by nitride coats 318, nitride barriers 322, oxide 324 between the nitride coats 318 and nitride barriers 322, and additional oxide 324 along the sides of the cell precursor stacks 305 facing in the Y direction to provide the arrangement shown in FIG. 12. A nitride layer and an oxide layer are deposited over the cell precursor stacks 305. A fifth etching step cuts grooves extending in the X direction through the second electrode layer 312b, selector layer 316, and third electrode layer 312c down to the bit lines 308. The grooves of the fifth etching step are narrower than, but centered on, the grooves of the fourth etching step in the Y direction, which results in the combined width of the nitride barriers 322 and oxide 324 extending from the sides of the PCM layers 316 and first electrode layers 312a to a plane even with the sides of the second electrode layers 312b, selector layers 316, and third electrode layers 312c. The nitride coat 318 is deposited over the cell precursor stacks 305 to extend along the sides of the second electrode layers 312b, selector layers 316, third electrode layers 312c, and oxide 322. Additional oxide 326 is deposited to fill spaces between adjacent vertical portions of the oxide coat 318.

To provide the arrangement shown in FIG. 13, the additional oxide 326 is removed from the top of the cell precursor stacks 305 by etching or chemical mechanical polishing, and a sixth etching step removes the additional oxide from spaces between vertically extending portions of the nitride coat 318 extending from the tops of the cell precursor stacks 305 down to at least a plane corresponding to the upper surfaces of the second electrode layers 312b, but not past the lower surfaces of the second electrode layers 312b. Gap fill 320 is then deposited to fill the spaces between the vertically extending portions of the nitride coat 318 at least to the top of the cell precursor stacks 305.

Top down chemical mechanical polishing removes all material down to the word lines 306 to result in a bottom row 302 of partially insulated memory cells 304, as shown in FIG. 14. The block 300 of two rows 302 of partially insulated memory cells 304 as shown in FIG. 3 can be created by placement of a top row 302 of memory cells 304 on top of the bottom row 302 shown in FIG. 14. The top row 302 may be produced by a sequence of various deposition, etching, and polishing steps generally similar to the process described in regard to FIGS. 4-14 for creating the lower row 302. The top row 302 can be constructed directly on a surface provided by the tops of the word lines 306 and gap fill 320 of the bottom row 302 shown in FIG. 14 instead of a substrate 310, or the top row 302 may be constructed separately and placed atop the bottom row 302 shown in FIG. 14, to produce the structure shown and described above in FIG. 3.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A three-dimensional memory cell structure comprising:

a plurality of parallel, vertically extending memory cells in a mutually spaced planar arrangement including gaps between the memory cells; and

two layers of filler filling the gaps including a lower layer of filler and an upper layer of filler, the lower layer having greater thermal conductivity than the upper layer.
The three-dimensional memory cell structure of claim 1, wherein the lower layer of filler is oxide and the upper layer of filler comprises any one of or any combination of gallium arsenide, indium gallium arsenide, gallium nitride, aluminum nitride, cadmium sulfide, cadmium selenide, cadmium tellurite, zinc sulfide, lead sulfide, lead selenide, and Cobalt based compounds.
The three-dimensional memory cell structure of claim 1, wherein the memory cells each include a phase change material layer located above a selector layer, and the upper layer of filler extends below the phase change layers.
The three-dimensional memory cell structure of claim 3, wherein the selector layer is an ovonic threshold switch layer.
The three-dimensional memory cell structure of claim 3, wherein the phase change material layer is isolated from other phase change material layers by the upper layer.
The three-dimensional memory cell structure of claim 3, wherein the selector layer is isolated from other selector layers by the lower level.
The three-dimensional memory cell structure of claim 1, wherein the plurality of memory cells is a first plurality of memory cells, the structure further comprising:

second plurality of parallel, vertically extending second row memory cells in a mutually spaced planar arrangement including second gaps between the second row memory cells, the second plurality of memory cells extending along a plane parallel to and located above a plane along which the first plurality of memory cells extends; and

two layers of filler filling the second gaps including a second lower layer of filler and a second upper layer of filler, the second lower layer having greater thermal conductivity than the second upper layer.
A method for forming a three dimensional cross point memory array, the method comprising:

forming a plurality of parallel, vertically extending memory cells in a mutually spaced planar arrangement including gaps between the memory cells;

creating a first filler layer by filling the gaps with a first filler material;

removing an upper portion of the first filler layer from the gaps; and

creating a second filler layer by backfilling the gaps with a second filler material on top of the first filler layer.
The method of claim 8, wherein the first filler material has a greater thermal conductivity than the second filler layer.
The method of claim 8, wherein each memory cell includes a phase change material layer and a selector layer, and the removing step includes removing all first filler material above a boundary plane, the boundary plane being parallel to the planar arrangement and being located below the phase change material layer.
The method of claim 10, wherein the selector layer is an ovonic threshold switch layer.
The method of claim 8, wherein the forming step includes:

depositing a stack of materials on a planar surface;

cutting a first plurality of parallel grooves through the stack; and

cutting a second plurality of parallel grooves through the stack, the second plurality of parallel grooves extending perpendicular to the first plurality of parallel grooves.
The method of claim 12, wherein the steps of creating the first filler layer, removing an upper portion of the first filler layer, and creating the second filler layer are performed after the step of cutting the first plurality of parallel grooves and before the step of cutting a second plurality of parallel grooves.
The method of claim 13, wherein the steps of creating the first filler layer, removing an upper portion of the first filler layer, and creating the second filler layer are repeated after the step of cutting the second plurality of parallel grooves.
The method of claim 14, comprising:

creating a planar surface on top of the memory cells and second filler layer; and

forming a second row of memory cells on the planar surface.
The method of claim 15, comprising:

creating a third filler layer within gaps in the second row of memory cells; and

creating a fourth filler layer on top of the third filler layer, the fourth filler layer having a third filler layer having a greater thermal conductivity than the fourth filler layer.