WO2022111114A1 - 一种时序信息的配置方法以及相关装置 - Google Patents

一种时序信息的配置方法以及相关装置 Download PDF

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Publication number
WO2022111114A1
WO2022111114A1 PCT/CN2021/123972 CN2021123972W WO2022111114A1 WO 2022111114 A1 WO2022111114 A1 WO 2022111114A1 CN 2021123972 W CN2021123972 W CN 2021123972W WO 2022111114 A1 WO2022111114 A1 WO 2022111114A1
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WIPO (PCT)
Prior art keywords
olt
optical module
timing
timing information
optical
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PCT/CN2021/123972
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English (en)
French (fr)
Inventor
林华枫
李远谋
王韦华
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21896616.6A priority Critical patent/EP4240022A4/en
Publication of WO2022111114A1 publication Critical patent/WO2022111114A1/zh
Priority to US18/323,802 priority patent/US20230319448A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0803—Configuration setting
    • H04L41/0806—Configuration setting for initial configuration or provisioning, e.g. plug-and-play
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q11/0067—Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0803—Configuration setting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q2011/0064—Arbitration, scheduling or medium access control aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q2011/0088—Signalling aspects

Definitions

  • the present application relates to the field of communications, and in particular, to a method for configuring timing information and a related device.
  • the optical fiber access used in the home mainly uses the passive optical network (PON) method, and its main function is: the uplink is to transmit data by means of time division multiple access (TDMA).
  • TDMA time division multiple access
  • the optical line termination (OLT) will allocate a specific time slot to the ONU for data transmission according to the system configuration.
  • the ONU sends data in order according to the allocated time slot, avoiding upstream data conflict.
  • FIG. 1 In a scenario where multiple ONUs are paired with one OLT, ONU1 and ONU2 and ONU3 obtain time slots respectively.
  • ONU1 sends data 1 in time slot 1
  • ONU2 sends data 2 in time slot 2
  • ONU3 sends data 3 in time slot 3
  • OLT receives data 1 to data 3 according to the order of time slots.
  • the downstream direction adopts the broadcast mode, and all ONUs can receive the same data.
  • the downstream data flow is encapsulated into an Ethernet packet, and a corresponding identity (identity, ID) is attached.
  • ID identity
  • the signals are divided into three groups and broadcast to each branch.
  • the ONU judges whether to process or discard the data stream according to the ID. The specific process can be shown in Figure 2.
  • the OLT in order to solve the upstream burst problem, the OLT usually needs the ability of the OLT to recover the BCDR according to the burst data recovery function of the optical module, the media access control (Media Access Control, MAC) business continuity and the burst clock data recovery (BCDR). , Whether the burst reception needs to be reset (Reset), how many resets are required, etc. to determine the key timing information such as burst overhead data, preamble (Preamble) length, and the position of the Reset signal that meet the system specification requirements; OLT According to the timing configuration information, the realization of The orderly cooperation between the OLT/MAC and the optical module can efficiently complete the upstream burst data reception and recovery.
  • the timing configuration information such as burst overhead data, preamble (Preamble) length, and the position of the Reset signal that meet the system specification requirements
  • the adaptation of the timing information between the OLT and the optical module is very critical.
  • the current OLT can usually only store fixed timing information. Therefore, when the timing required by the optical module changes or the timing information of the optical module changes significantly in the subsequent development, the OLT cannot realize the appropriate timing information between the optical module and the optical module. match.
  • Embodiments of the present application provide a method for configuring timing information and a related device, which are used to solve the problem of adapting timing information between an OLT and an optical module.
  • an embodiment of the present application provides a method for configuring timing information, which is specifically as follows: the OLT performs interactive authentication with an optical module, and then determines timing parameters of the optical module; then the optical module stores the timing parameters in itself In the register; when the optical module is inserted into the OLT and is in working state, the OLT reads the timing parameters stored by the optical module; then the OLT determines the timing information of the ONU corresponding to the optical module according to the timing parameters; The OLT configures the timing information to the ONU.
  • the timing parameter may be timing information corresponding to the optical module; or may determine the timing information corresponding to the optical module with the timing coefficient stored by the OLT. That is, the timing information corresponding to the optical module can be determined during the mutual authentication between the optical module and the OLT, and then the timing information can be stored in the optical module as the timing parameter; At the same time, the OLT converts its own stored timing information into timing coefficients, and then determines the timing parameters of the optical module according to the timing coefficients and the timing information of the optical module. For example, the preamble in the timing information of the optical module is 100 nanoseconds, and the timing coefficient stored by the OLT is 5, then the timing parameter stored by the optical module is 20 nanoseconds.
  • the optical module and the OLT are mutually authenticated to determine the timing parameter corresponding to the optical module, and then the OLT determines the timing information corresponding to each optical module according to the timing parameter as a variable.
  • the OLT device does not need to modify the timing information stored by itself, and can flexibly implement the problem of adaptation of timing information between the OLT and the optical modules.
  • the timing parameter is stored in a register address agreed between the optical module and the OLT protocol. In this way, it is convenient for the OLT to read the timing parameter.
  • the OLT may read the timing parameters stored in the optical module through a management channel between the optical module and the OLT.
  • the timing information includes burst overhead data, preamble length of preamble, and position of reset signal.
  • the OLT may perform normal data interaction with the ONU according to the timing information.
  • an embodiment of the present application provides a method for configuring timing information, which specifically includes: an optical module and an OLT interactively authenticate and determine timing parameters, and then the optical module stores the timing parameters in its own register; when the optical module is inserted into the When the OLT is in a working state, the OLT reads the stored timing parameters of the optical module; then the OLT determines the timing information of the ONU corresponding to the optical module according to the timing parameters; finally, the OLT configures the timing information to the ONU .
  • the timing parameter may be timing information corresponding to the optical module; or may determine the timing information corresponding to the optical module with the timing coefficient stored by the OLT. That is, the timing information corresponding to the optical module can be determined during the mutual authentication between the optical module and the OLT, and then the timing information can be stored in the optical module as the timing parameter; At the same time, the OLT converts its own stored timing information into timing coefficients, and then determines the timing parameters of the optical module according to the timing coefficients and the timing information of the optical module. For example, the preamble in the timing information of the optical module is 100 nanoseconds, and the timing coefficient stored by the OLT is 5, then the timing parameter stored by the optical module is 20 nanoseconds.
  • the optical module and the OLT are mutually authenticated to determine the timing parameter corresponding to the optical module, and then the OLT determines the timing information corresponding to each optical module according to the timing parameter as a variable.
  • the OLT device does not need to modify the timing information stored by itself, and can flexibly implement the problem of adaptation of timing information between the OLT and the optical modules.
  • the timing information includes burst overhead data, preamble length of preamble, and position of reset signal.
  • the optical module responding to the read instruction of the OLT, and transmitting the timing parameter to the OLT specifically includes: the optical module responds to the read instruction of the OLT, and transmits to the OLT through a management channel. the timing parameters.
  • the present application provides an optical line termination device, the device having the function of implementing the behavior of the OLT in the above-mentioned first aspect.
  • This function can be implemented by hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the apparatus includes units or modules for performing the steps of the above first aspect.
  • the device includes: a reading unit for reading the timing parameters stored in the light unit;
  • a processing unit configured to determine timing information corresponding to the optical module according to the timing parameter
  • a configuration unit configured to configure the timing information for the ONU corresponding to the optical module.
  • the apparatus includes: a processor and a transceiver, where the processor is configured to support the OLT to perform corresponding functions in the method provided in the first aspect.
  • the transceiver is used to instruct the OLT, the optical module and the ONU and the communication between them, to send the interactive data involved in the above method to the ONU, and to send a read command to the optical module.
  • the apparatus may further include a memory, which is used for coupling with the processor, and which stores necessary program instructions and data of the OLT, such as storing fixed timing coefficients.
  • the chip when the device is a chip in the OLT, the chip includes: a processing unit and a transceiver unit.
  • the transceiver unit may be, for example, an input/output interface, a pin or a circuit on the chip, and transmits reading instructions or timing information to other chips or modules coupled to the chip.
  • the processing unit may be, for example, a processor, and the processor is configured to determine timing information corresponding to the optical module according to the timing parameter.
  • the processing unit can execute the computer-executed instructions stored in the storage unit, so as to support the OLT to perform the method provided in the first aspect.
  • the storage unit can be a storage unit in the chip, such as a register, a cache, etc., and the storage unit can also be a storage unit located outside the chip, such as a read-only memory (read-only memory, ROM) or a memory unit.
  • ROM read-only memory
  • RAM random access memory
  • the device includes a communication interface and a logic circuit
  • the communication interface is used to read the timing parameters stored in the optical unit; the logic circuit is used to determine the corresponding optical module according to the timing parameters.
  • the timing information; the communication interface is also used to configure the timing information for the ONU corresponding to the optical module.
  • the processor mentioned in any of the above may be a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more An integrated circuit for program execution of a configuration method for controlling timing information of the above aspects.
  • CPU Central Processing Unit
  • ASIC application-specific integrated circuit
  • an embodiment of the present application provides an optical module device, and the device has a function of implementing the behavior of the optical module in the above-mentioned second aspect.
  • This function can be implemented by hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the apparatus includes units or modules for performing the steps of the second aspect above.
  • the device includes: an interactive authentication unit, configured to interact with the optical line terminal OLT to authenticate and determine timing parameters; a storage unit, configured to store the timing parameters in its own register; and a receiving unit, configured to operate when the OLT is inserted In the state, the read instruction of the OLT is received; the response unit is used to respond to the read instruction of the OLT, so that the OLT reads the timing parameters and based on the timing parameters and the optical module corresponding to the The optical network unit ONU performs data exchange.
  • the apparatus includes: a processor, a transceiver, and a memory, where the processor is configured to support the optical module to perform corresponding functions in the method provided in the second aspect.
  • the transceiver is used to instruct the optical module to communicate with the OLT and the ONU, receive the read command sent by the OLT and respond to the read command.
  • the memory is used for coupling with the processor, and stores necessary program instructions and data of the optical module, such as storing timing parameters.
  • the chip when the device is a chip in an optical module, the chip includes: a processing unit, a transceiver unit, and a storage unit.
  • the transceiver unit may be, for example, an input/output interface, a pin or a circuit on the chip, receives a read command and transmits timing parameters to other chips or modules coupled to the chip in response to the read command.
  • the processing unit may be, for example, a processor, and the processor is configured to determine timing information corresponding to the optical module according to the timing parameter.
  • the processing unit can execute the computer-executed instructions stored in the storage unit, so as to support the optical module to perform the method provided in the second aspect.
  • the storage unit may be a storage unit within the chip, such as a register, a cache, etc., or a storage unit located outside the chip, such as a read-only memory (ROM) or a storage unit that can store static information and Other types of static storage devices for instructions, random access memory (RAM), etc.
  • ROM read-only memory
  • RAM random access memory
  • the device includes a communication interface and a logic circuit, the communication interface is used for mutual authentication and determination of timing parameters with the optical line terminal OLT; the logic circuit is used for storing the timing parameters in its own register; the The communication interface is further configured to receive a read instruction of the OLT when the inserted OLT is in a working state; and to transmit the timing parameter to the OLT in response to the read instruction of the OLT.
  • the processor mentioned in any of the above may be a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more An integrated circuit for program execution of a configuration method for controlling timing information of the above aspects.
  • CPU Central Processing Unit
  • ASIC application-specific integrated circuit
  • an embodiment of the present application provides a computer-readable storage medium, where computer instructions are stored in the computer storage medium, and the computer instructions are used to execute the method in any possible implementation manner of any one of the foregoing aspects.
  • the embodiments of the present application provide a computer program product including instructions, which, when executed on a computer, cause the computer to execute the method in any one of the foregoing aspects.
  • the present application provides a chip system
  • the chip system includes a processor for supporting a communication device to implement the functions involved in the above aspects, such as generating or processing the data and/or information involved in the above methods.
  • the chip system further includes a memory for storing necessary program instructions and data of the communication device, so as to realize the function of any one of the above aspects.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • the OLT when the chip system runs on the side of the OLT, the OLT can be supported to perform the method provided in the first aspect;
  • the optical module when the system-on-chip runs on the optical module, the optical module can be supported to perform the method provided in the second aspect.
  • an embodiment of the present application provides a communication system, where the system includes the optical module, the OLT, and the ONU described in the foregoing aspects.
  • Fig. 1 is a schematic diagram of upstream data transmission of a PON access system
  • Fig. 2 is a schematic diagram of downlink data transmission of the PON access system
  • Fig. 3 is the data format schematic diagram of the upstream data packet of ONU
  • FIG. 4 is a schematic structural diagram of an optical module in an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a timing configuration mode of an OLT
  • FIG. 6 is a schematic diagram of an embodiment of a method for configuring timing information in an embodiment of the present application
  • FIG. 7 is a schematic flowchart of timing information configuration in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an embodiment of an optical line termination device in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another embodiment of an optical line termination device in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of an embodiment of an optical module device in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of another embodiment of the optical module device in the embodiment of the present application.
  • the naming or numbering of the steps in this application does not mean that the steps in the method flow must be executed in the time/logical sequence indicated by the naming or numbering, and the named or numbered process steps can be implemented according to the The technical purpose is to change the execution order, as long as the same or similar technical effects can be achieved.
  • the division of units in this application is a logical division. In practical applications, there may be other division methods. For example, multiple units may be combined or integrated into another system, or some features may be ignored. , or not implemented, in addition, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, and the indirect coupling or communication connection between units may be electrical or other similar forms. There are no restrictions in the application.
  • the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed into multiple circuit units, and some or all of them may be selected according to actual needs. unit to achieve the purpose of the scheme of this application.
  • the terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to be limiting of the application.
  • the singular expressions "a,” “an,” “the,” “above,” “the,” and “the” are intended to also Expressions such as “one or more” are included unless the context clearly dictates otherwise.
  • one or more refers to one, two or more; "and/or”, which describes the association relationship of associated objects, indicates that there may be three kinds of relationships; for example, A and/or B can mean that A exists alone, A and B exist simultaneously, and B exists independently, wherein A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are an "or" relationship.
  • PON technology is a point-to-multipoint fiber access technology.
  • a PON system may include an OLT, an optical distribution network (ODN), and at least one ONU.
  • the OLT is connected to multiple ONUs through the ODN.
  • the structure of the PON access system consists of three parts, namely OLT, ODN and ONU.
  • the OLT is the aggregation device of the ON protocol placed at the central office;
  • the ODN is a passive device that connects the OLT and the ONU, and its function is to distribute the downstream data and concentrate the upstream data; in the PON access system, the ONU can be used for Providing a user-side interface can also directly provide user port functions.
  • the ONU directly provides the user port function, it is called an optical network terminal (ONT). Therefore, for ease of understanding, the ONUs mentioned below collectively refer to an ONT that can directly provide a user port function and an ONU that provides a user side interface.
  • the uplink is to transmit data by means of TDMA. That is, after the ONU is successfully registered, the OLT will allocate a specific time slot to the ONU for data transmission according to the system configuration. The ONU sends data in order according to the allocated time slot, avoiding upstream data conflict. The specific process can be shown in FIG. 1 . The OLT allocates corresponding time slots to ONU1 , ONU2 and ONU3 .
  • ONU1 sends data 1 in time slot 1
  • ONU2 sends data 2 in time slot 2
  • ONU3 sends data 3 in time slot 3
  • OLT receives data 1 to data 3 according to the order of time slots.
  • the OLT sends data by broadcasting, that is, all ONUs can receive the same data.
  • the downstream data flow is encapsulated into an Ethernet packet, and a corresponding ID is attached, and the ID is used to indicate the ONU to which the packet belongs.
  • the message is divided into three groups of signals and broadcast to each branch.
  • the ONU judges whether to process or discard the data stream according to the ID. The specific process can be shown in Figure 2.
  • the OLT needs to send data packets for three ONUs (such as ONU1 to ONU3), wherein the ID is used to indicate that the data packet 1 corresponds to ONU1, the data packet 2 corresponds to ONU2, and the data packet 3 corresponds to ONU3. Then, at the optical splitter, the data including the data packet 1 to the data packet 3 is divided into three groups of signals and broadcast to each branch, and then the ONU1 determines the corresponding data packet according to the ID, and then receives its corresponding data packet , other packets are dropped. For example, ONU1 receives data packet 1 and discards data packet 2 and data packet 3, and ONU2 receives data packet 2 and discards data packet 1 and data packet 3.
  • ONU1 receives data packet 1 and discards data packet 2 and data packet 3
  • ONU2 receives data packet 2 and discards data packet 1 and data packet 3.
  • the ONU is required to be in an off state when no signal is transmitted, and it is required to be turned on quickly when a signal is transmitted, which requires the ONU to support the working mode of burst transmission. Therefore, the format of the upstream data packet of the ONU can be as shown in Figure 3, that is, the total overhead of upstream burst reception includes a guard time (Guard time), a preamble (Preamble), a delimiter (Delimiter) and a payload.
  • the protection time includes the turn off time (Turn off), the turn on time (Turn on), the post stabilization of the previous burst light, the front stabilization of the current burst light, and the reset time.
  • the OLT optical module (for ease of understanding, the optical modules mentioned below all refer to the OLT optical module), as the core device for realizing burst reception, its main function is to realize optical-electrical or electrical-optical conversion. It mainly includes a receiving part and a transmitting part, the receiving part realizes the photo-electrical conversion, and the transmitting part realizes the electric-optical conversion.
  • the structure of the optical module can be shown in Figure 4, in which the functions of each functional unit are as follows:
  • Laser A device that converts electrical signals into optical signals.
  • Monitoring diode receives the optical power of the laser, is used to monitor the current of the laser, and completes the control of the laser output power with the automatic power control circuit.
  • Laser driver It is used to drive and control the laser. It mainly converts the input electrical signal into the laser driving signal, and controls the laser to work normally.
  • Detector used to receive optical signals and complete the conversion of optical signals to current signals.
  • a trans-impedance amplifier (TIA) is used to amplify the current signal output by the photodetector, and at the same time convert the current signal into a voltage signal for output.
  • Limiting amplifier mainly amplifies the voltage signal output by TIA, and converts the signal into a standard digital level signal.
  • the OLT needs to acquire various information related to the optical module to determine timing information that meets the system specification requirements.
  • the information related to the optical module includes but is not limited to one or more of data recovery performance, MAC BCDR capability, whether a reset is required for burst reception, and how many resets are required.
  • the timing information includes, but is not limited to, one or more of burst overhead data, preamble length, and position of the Reset signal.
  • the system specification refers to the parameters that the OLT needs to achieve in the PON access system, for example, it needs to meet a certain delay requirement. According to the timing information, the OLT realizes the orderly cooperation between the OLT and the optical module, so as to efficiently complete the reception and recovery of uplink burst data.
  • the timing mapping table is usually preconfigured for the OLT (the timing mapping table includes the timing sequence number, and the timing information corresponding to the timing sequence number. If the timing sequence number is 1, the corresponding The timing information is A; the timing sequence number is 2, and the corresponding timing information is B).
  • the timing sequence number corresponding to the optical module is pre-configured during the optical module processing.
  • the OLT reads the internal optical module. Timing sequence number, find the timing mapping table through the timing sequence number, and configure the single-board register corresponding to the optical module according to the timing information in the timing mapping table.
  • the configured timing mapping table includes timing information 1, the timing information 1 is adapted to the optical module A, and the system joint debugging test is completed. In order for the OLT device and the optical module to work normally, all other optical modules introduced later must exactly match the timing information1. If the subsequent optical module B adopts a different working mode and cannot be compatible with the timing information 1, the optical module B cannot be applied.
  • timing sequence number For ease of understanding, the following describes the relationship between the timing sequence number, timing information, timing parameters, and timing coefficients:
  • Timing information is the information used to realize the normal data interaction between the optical module, the OLT and the ONU, including but not limited to the burst overhead, the length of the preamble, and the position of the reset signal.
  • Timing sequence number There is a one-to-one correspondence with timing information in the timing mapping table preset by the OLT.
  • the relationship between the timing sequence number and timing information may be as shown in Table 1:
  • sequence number timing information 1 Burst total overhead A1, preamble length A1... 2 Burst total overhead B1, preamble length B1...
  • Timing coefficient In this application document, the timing coefficient is a fixed parameter preset in the OLT.
  • Timing parameter In this application document, the timing parameter is preset in the register of the optical module.
  • the timing parameter may be timing information corresponding to the optical module, or may be an intermediate value for obtaining timing information.
  • the OLT may determine timing information corresponding to the optical module according to the timing coefficient preset in the OLT and the timing parameter preset in the optical module. For example, the burst total overhead data in the timing information corresponding to the optical module is 100 nanometers, and the timing coefficient stored by the OLT is 4, then the parameter used to indicate the burst overhead data in the timing parameters may be 25 nanometers.
  • the embodiments of the present application provide a timing information configuration method and a related device.
  • FIG. 6 a method for configuring timing information in an embodiment of the present application is shown. The following embodiments will be described with an OLT and an optical module.
  • the optical module and the OLT are mutually authenticated to determine timing parameters corresponding to the optical module, and the timing parameters are preset in the optical module.
  • the optical module In the development stage of the optical module, the optical module is authenticated interactively with the OLT, so as to determine the timing parameters of the optical module when it is working, and then the optical module writes the timing parameters into the register address pre-agreed with the OLT.
  • the register address located in the optical module can be as shown in Table 2:
  • the counting unit of the information such as the total overhead of the burst reception, the length of the Preamble, and the position of the Reset signal can be set according to the actual situation, for example, set to nanoseconds or default to the unit, which is not specifically limited here.
  • the timing parameters of the optical module research and development stage may be directly used timing information, or may be timing parameters obtained according to the timing coefficients stored by the OLT, where the timing coefficients are fixed parameters that have been stored by the OLT .
  • the OLT can store a fixed timing coefficient in itself.
  • the OLT can determine the timing coefficient according to the timing coefficient stored in the OLT and the timing parameters stored in the optical module. Timing information when the optical module is working.
  • the timing coefficient stored by the OLT is A, and the timing parameters obtained by each optical module after mutual authentication with it (for example, the timing parameter of optical module 1 is B, and the timing parameter of optical module 2 is C), and then when each optical module is When the OLT is inserted to work, the OLT can obtain the timing information of each optical module according to the coefficient and the timing parameters of each optical module.
  • the timing information of the optical module 1 is A*B
  • the timing information of the optical module 2 is A*C.
  • the OLT reads the timing parameter.
  • the OLT When the optical module is inserted into the OLT to work, the OLT reads the timing parameters stored in the optical module from the register of the optical module through a management channel (eg, an integrated circuit (inter-integrated circuit, IIC)).
  • a management channel eg, an integrated circuit (inter-integrated circuit, IIC)
  • the OLT determines timing information corresponding to the optical module according to the timing parameter.
  • the OLT configures the timing information to the ONU corresponding to the optical module.
  • the OLT sends the timing information to the ONU corresponding to the optical module, thereby informing the ONU that data can be sent and received according to the timing information.
  • the OLT exchanges data with the ONU according to the timing information.
  • the OLT reads the timing information stored inside the optical module from the register of the optical module through the management channel, and then according to the timing information stored inside the optical module.
  • the information configures the timing configuration parameters of the optical module and the ONU corresponding to the optical module; finally, the OLT configures the timing configuration parameters to the MAC interface corresponding to the optical module and the ONU, and finally controls the optical module to perform data exchange with the ONU.
  • the optical line terminal device 800 includes: a reading unit 801, a processing unit 802, and a configuration unit 803, wherein the reading unit 801, the processing unit 802, and the configuration unit 803 are connected through a bus .
  • the optical line termination device 800 may be the OLT in the above method embodiments, or may be configured as one or more chips in the OLT.
  • the optical line termination device 800 may be used to perform part or all of the functions of the OLT in the above method embodiments. Meanwhile, FIG. 8 only shows some modules of the optical line termination device related to the embodiments of the present application.
  • the reading unit 801 is used to read the timing parameters stored in the optical unit; the processing unit 802 is used to determine the timing information corresponding to the optical module according to the timing parameters; the configuration unit 803 is used to The timing information is configured for the ONU corresponding to the optical module.
  • the optical line terminal device 800 further includes a storage unit, which can store execution instructions, and at this time, the storage unit is coupled with the processing unit 802, so that the processing unit 802 can execute the computer execution instructions stored in the storage unit to achieve.
  • the optional storage unit included in the optical line termination device 800 may be an in-chip storage unit, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip, such as a ROM or a storable storage unit. Other types of static storage devices for static information and instructions, RAM, etc.
  • FIG. 9 shows a schematic structural diagram of an optical line termination device 900 in the above embodiment, and the optical line termination device 900 may be configured as the aforementioned OLT.
  • the optical line termination apparatus 900 may include a processor 902 , a computer readable storage medium/memory 903 , a transceiver 904 , input devices 905 and output devices 906 , and a bus 901 . Wherein, processors, transceivers, computer-readable storage media, etc. are connected through a bus.
  • the embodiments of the present application do not limit the specific connection medium between the above components.
  • the transceiver 904 reads the timing parameters stored in the optical unit; the processor 904 determines timing information corresponding to the optical module according to the timing parameters; The network single ONU sends the timing information, thereby realizing the function of configuring the timing information for the ONU.
  • the transceiver 904 and the processor 902 can implement the corresponding steps in any of the foregoing embodiments in FIG. 6 to FIG. 7 , and details are not described here.
  • FIG. 9 only shows a simplified design of the optical line termination device.
  • the optical line termination device can include any number of transceivers, processors, memories, etc., and all of them can implement the requirements of the present application.
  • Optical line termination devices are all within the scope of protection of this application.
  • the processor 902 involved in the above-mentioned apparatus 900 may be a general-purpose processor, such as a CPU, a network processor (NP), a microprocessor, etc., or an ASIC, or one or more programs for controlling the solution of the present application. implemented integrated circuits. It can also be a digital signal processor (DSP), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.
  • DSP digital signal processor
  • FPGA field-programmable gate array
  • a controller/processor may also be a combination that implements computing functions, such as a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, and the like. Processors typically perform logical and arithmetic operations based on program instructions stored in memory.
  • the above-mentioned bus 901 may be a peripheral component interconnect (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of presentation, only one thick line is used in FIG. 9, but it does not mean that there is only one bus or one type of bus.
  • the above-mentioned computer-readable storage medium/memory 903 may also store an operating system and other application programs.
  • the program may include program code, and the program code includes computer operation instructions.
  • the above-mentioned memory may be ROM, other types of static storage devices that can store static information and instructions, RAM, other types of dynamic storage devices that can store information and instructions, disk storage, and the like.
  • Memory 903 may be a combination of the above-described storage types.
  • the above-mentioned computer-readable storage medium/memory may be in the processor, outside the processor, or distributed over multiple entities including the processor or processing circuit.
  • the computer-readable storage medium/memory described above may be embodied in a computer program product.
  • a computer program product may include a computer-readable medium in packaging materials.
  • the embodiments of the present application also provide a general-purpose processing system, for example, commonly referred to as a chip, and the general-purpose processing system includes: one or more microprocessors that provide processor functions; and an external memory that provides at least a part of a storage medium. , all of which are connected together with other support circuits through an external bus architecture.
  • the processor is caused to execute some or all of the steps in the method for configuring the timing information of the optical line termination device in the embodiment of FIGS. Other procedures of the described techniques.
  • the steps of the methods or algorithms described in conjunction with the disclosure of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • the software instructions can be composed of corresponding software modules, and the software modules can be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage known in the art in the medium.
  • An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and storage medium may reside in an ASIC. Alternatively, the ASIC may be located in the terminal.
  • the processor and storage medium may also exist in the optical line termination device as discrete components.
  • the optical module device 1000 includes: an interactive authentication unit 1001 , a storage unit 1002 , a receiving unit 1003 and a response unit 1004 , wherein the interactive authentication unit 1001 , the storage unit 1002 , and the receiving unit 1003 and the response unit 1004 are connected through a bus.
  • the optical module apparatus 1000 may be the optical module in the above method embodiments, or may be configured as one or more chips in the optical module.
  • the optical module apparatus 1000 may be used to perform part or all of the functions of the optical module in the foregoing method embodiments. Meanwhile, FIG. 10 only shows that the optical module device involves some modules of the embodiment of the present application.
  • the interactive authentication unit 1001 is used to interactively authenticate and determine timing parameters with the optical line terminal OLT; the storage unit 1002 is used to store the timing parameters in its own register; the receiving unit 1003 is used to insert the OLT in the In the working state, the read instruction of the OLT is received; the response unit 1004 is configured to transmit the timing parameter to the OLT in response to the read instruction of the OLT.
  • the storage unit 1002 may store execution instructions.
  • the storage unit 1002 is coupled to the processing unit, so that the processing unit can execute the computer execution instructions stored in the storage unit to implement the functions of the optical module in the above method embodiments.
  • the optional storage unit included in the optical module device 1000 may be an in-chip storage unit, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip, such as a ROM or a storage unit that can store static Other types of static storage devices for information and instructions, RAM, etc.
  • FIG. 11 shows a schematic structural diagram of an optical module apparatus 1100 in the above-mentioned embodiment, and the optical module apparatus 1100 may be configured as the aforementioned optical module.
  • the optical module apparatus 1100 may include a processor 1102 , a computer-readable storage medium/memory 1103 , a transceiver 1104 , an input device 1105 and an output device 1106 , and a bus 1101 . Wherein, processors, transceivers, computer-readable storage media, etc. are connected through a bus.
  • the embodiments of the present application do not limit the specific connection medium between the above components.
  • the transceiver 1104 interacts with the optical line terminal OLT for authentication; the processor 1104 determines timing parameters; the memory 1103 stores the timing parameters; A read command of the OLT; in response to the read command of the OLT, the timing parameter is transmitted to the OLT.
  • the transceiver 1104 , the processor 1102 and the memory 1103 can implement the corresponding steps in any of the foregoing embodiments in FIG. 6 to FIG. 7 , and details are not described here.
  • FIG. 11 only shows a simplified design of the optical module device.
  • the optical module device can include any number of transceivers, processors, memories, etc., and all the optical modules that can implement the application The devices are all within the scope of protection of the present application.
  • the processor 1102 involved in the above device 1100 may be a general-purpose processor, such as a CPU, a network processor (NP), a microprocessor, etc., or an ASIC, or one or more programs used to control the solution of the present application implemented integrated circuits. It can also be a digital signal processor (DSP), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.
  • DSP digital signal processor
  • FPGA field-programmable gate array
  • a controller/processor may also be a combination that implements computing functions, such as a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, and the like. Processors typically perform logical and arithmetic operations based on program instructions stored in memory.
  • the aforementioned bus 1101 may be a peripheral component interconnect (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of presentation, only one thick line is used in FIG. 11, but it does not mean that there is only one bus or one type of bus.
  • the computer-readable storage medium/memory 1103 mentioned above may also store an operating system and other application programs.
  • the program may include program code, and the program code includes computer operation instructions.
  • the above-mentioned memory may be ROM, other types of static storage devices that can store static information and instructions, RAM, other types of dynamic storage devices that can store information and instructions, disk storage, and the like.
  • the memory 1103 may be a combination of the above storage types.
  • the above-mentioned computer-readable storage medium/memory may be in the processor, outside the processor, or distributed over multiple entities including the processor or processing circuit.
  • the computer-readable storage medium/memory described above may be embodied in a computer program product.
  • a computer program product may include a computer-readable medium in packaging materials.
  • the embodiments of the present application also provide a general-purpose processing system, for example, commonly referred to as a chip, and the general-purpose processing system includes: one or more microprocessors that provide processor functions; and an external memory that provides at least a part of a storage medium. , all of which are connected together with other support circuits through an external bus architecture.
  • the processor is caused to execute some or all of the steps in the method for configuring the timing information of the optical line termination device in the embodiment of FIGS. Other procedures of the described techniques.
  • the steps of the methods or algorithms described in conjunction with the disclosure of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • the software instructions can be composed of corresponding software modules, and the software modules can be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage known in the art in the medium.
  • An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and storage medium may reside in an ASIC. Alternatively, the ASIC may be located in the terminal.
  • the processor and the storage medium may also exist in the optical module device as discrete components.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware, or can be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请实施例提供了一种时序信息的配置方法以及相关装置，用于解决OLT与光模块之间时序信息的适配问题。本申请实施例提供的技术方案具体如下：该OLT与光模块进行交互认证，然后确定该光模块的时序参数；然后该光模块将该时序参数存储在自身寄存器中；当该光模块***该OLT并处于工作状态时，该OLT读取该光模块已存储的时序参数；然后该OLT根据该时序参数确定并配置与该光模块对应的ONU的时序信息。

Description

一种时序信息的配置方法以及相关装置
本申请要求于2020年11月26日提交中国国家知识产权局、申请号为202011352945.1、申请名称为“一种时序信息的配置方法以及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种时序信息的配置方法以及相关装置。
背景技术
当前家庭使用的光纤接入，主流使用无源光纤网络(passive optical network，PON)的方式，其主要的功能是：上行是通过时分复用(time division multiple access，TDMA)的方式传输数据。当光网络单元(optical network unit，ONU)注册成功后，光线路终端(optical line termination，OLT)会根据***的配置给ONU分配特定的时隙以进行数据传输。ONU根据分配的时隙按次序发送数据，避免了上行数据冲突。其具体过程可以如图1所示，在多个ONU对一个OLT的场景下，ONU1和ONU2以及ONU3分别获取时隙。其中ONU1在时隙1里发送数据1，ONU2在时隙2里发送数据2，ONU3在时隙3里发送数据3，然后OLT根据时隙的先后顺序接收数据1至数据3。下行的方向采用广播的方式，所有的ONU都能收到相同的数据。在OLT上，下行数据流被封装成为以太网报文，附加相应的身份标识(identity，ID)。在分光器处，被分为三组信号广播到每个支路。ONU接收到OLT发送的数据后，根据ID对数据流进行判断是进行处理还是进行丢弃。其具体过程可以如图2所示。
在该PON***中，为了解决上行突发问题，通常需要OLT根据光模块的突发数据恢复功能、媒体接入控制(Media Access Control，MAC)业务连续性和突发时钟数据恢复BCDR)的能力、突发接收是否需要复位(Reset)、需要多少个复位等确定满足***规格要求的突发开销数据、前导码(Preamble)长度、Reset信号的位置等关键时序信息；OLT根据时序配置信息，实现OLT/MAC与光模块之间的有序配合，从而高效完成上行突发数据接收和恢复。
因此为了控制光模块在上行突发状态下进行***正常的数据交互，OLT与光模块之间的时序信息的适配是十分关键的。目前的OLT通常只可以存储固定的时序信息，因此在光模块所需要的时序产生变化或者后续的发展中光模块的时序信息发生重大变化时，该OLT无法实现和光模块之间的时序信息的适配。
发明内容
本申请实施例提供了一种时序信息的配置方法以及相关装置，用于解决OLT与光模块之间时序信息的适配问题。
第一方面，本申请实施例提供一种时序信息的配置方法，其具体如下：该OLT与光模块进行交互认证，然后确定该光模块的时序参数；然后该光模块将该时序参数存储在自身寄存器中；当该光模块***该OLT并处于工作状态时，该OLT读取该光模块已存储的时序参数；然后该OLT根据该时序参数确定与该光模块对应的ONU的时序信息；最后该OLT将该时序信息配置给该ONU。
本实施例中，该时序参数可以是该光模块对应的时序信息；也可以与该OLT存储的时序系数确定该光模块对应的时序信息。即该光模块与该OLT交互认证时可以确定该光模块对应的时序信息，然后将该时序信息作为该时序参数存储在该光模块中；或者该光模块与该OLT交互认证时确定了该光模块的时序信息，同时该OLT将自身已存储的时序信息转化为时序系数，然后根据该时序系数和该光模块的时序信息确定该光模块的时序参数。比如该光模块的时序信息中前导码的为100纳秒，而该OLT存储的时序系数为5，则该光模块存储的时序参数为20纳秒。
本实施例中，该光模块与该OLT交互认证确定该光模块对应的时序参数，然后OLT根据该时序参数作为变量来确定各个光模块对应的时序信息。这样对于各不同的光模块，该OLT设备不需要再修改自身存储的时序信息，就可以灵活实现OLT与光模块之间时序信息的适配问题。
可选的，该时序参数存储于该光模块与该OLT协议约定的寄存器地址。这样可以方便该OLT读取该时序参数。
可选的，该OLT读取该光模块中已存储的时序参数可以通过该光模块与该OLT之间的管理通道。
可选的，所述时序信息包括突发总开销数据、前导码Preamble长度、复位Reset信号位置。
可选的，该OLT在将该时序信息配置给该ONU之后，该OLT可以根据该时序信息与该ONU进行正常数据交互。
第二方面，本申请实施例提供一种时序信息的配置方法，其具体包括：光模块与OLT交互认证确定时序参数，然后该光模块将该时序参数存储在自身寄存器；当该光模块***该OLT并处于工作状态时，该OLT读取该光模块已存储的时序参数；然后该OLT根据该时序参数确定与该光模块对应的ONU的时序信息；最后该OLT将该时序信息配置给该ONU。
本实施例中，该时序参数可以是该光模块对应的时序信息；也可以与该OLT存储的时序系数确定该光模块对应的时序信息。即该光模块与该OLT交互认证时可以确定该光模块对应的时序信息，然后将该时序信息作为该时序参数存储在该光模块中；或者该光模块与该OLT交互认证时确定了该光模块的时序信息，同时该OLT将自身已存储的时序信息转化为时序系数，然后根据该时序系数和该光模块的时序信息确定该光模块的时序参数。比如该光模块的时序信息中前导码的为100纳秒，而该OLT存储的时序系数为5，则该光模块存储的时序参数为20纳秒。
本实施例中，该光模块与该OLT交互认证确定该光模块对应的时序参数，然后OLT根据该时序参数作为变量来确定各个光模块对应的时序信息。这样对于各不同的光模块，该OLT设备不需要再修改自身存储的时序信息，就可以灵活实现OLT与光模块之间时序信息的适配问题。
可选的，所述时序信息包括突发总开销数据、前导码Preamble长度、复位Reset信号位置。
可选的，该所述光模块响应所述OLT的读取指令，向所述OLT传送所述时序参数具体 包括：所述光模块响应所述OLT的读取指令，通过管理通道向该OLT传送所述时序参数。
第三方面，本申请提供一种光线路终端装置，该装置具有实现上述第一方面中OLT行为的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的实现方式中，该装置包括用于执行以上第一方面各个步骤的单元或模块。例如，该装置包括：读取单元，用于读取光单元中已存储的时序参数；
处理单元，用于根据所述时序参数确定所述光模块对应的时序信息；
配置单元，用于为与所述光模块对应的光网络单元ONU配置所述时序信息。
在一种可能的实现方式中，该装置包括：处理器和收发器，该处理器被配置为支持OLT执行上述第一方面提供的方法中相应的功能。收发器用于指示OLT和光模块以及ONU以及之间的通信，向ONU发送上述方法中所涉及的交互数据，以及向该光模块发送读取指令。可选的，此装置还可以包括存储器，该存储器用于与处理器耦合，其保存OLT必要的程序指令和数据，例如存储固定的时序系数。
在一种可能的实现方式中，当该装置为OLT内的芯片时，该芯片包括：处理单元和收发单元。该收发单元例如可以是该芯片上的输入/输出接口、管脚或电路等，将读取指令或时序信息传送给与此芯片耦合的其他芯片或模块中。该处理单元例如可以是处理器，此处理器用于根据所述时序参数确定所述光模块对应的时序信息。该处理单元可执行存储单元存储的计算机执行指令，以支持OLT执行上述第一方面提供的方法。可选地，该存储单元可以为该芯片内的存储单元，如寄存器、缓存等，该存储单元还可以是位于该芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
在一种可能实现方式中，该装置包括通信接口和逻辑电路，该通信接口用于读取光单元中已存储的时序参数；该逻辑电路，用于根据所述时序参数确定所述光模块对应的时序信息；该通信接口，还用于为与所述光模块对应的光网络单元ONU配置所述时序信息。
其中，上述任一处提到的处理器，可以是一个通用中央处理器(Central Processing Unit，CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制上述各方面时序信息的配置方法的程序执行的集成电路。
第四方面，本申请实施例提供一种光模块装置，该装置具有实现上述第二方面中光模块行为的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的实现方式中，该装置包括用于执行以上第二方面各个步骤的单元或模块。例如，该装置包括：交互认证单元，用于与光线路终端OLT交互认证确定时序参数；存储单元，用于将所述时序参数存储在自身寄存器；接收单元，用于在***所述OLT处于工作状态时，接收所述OLT的读取指令；响应单元，用于响应所述OLT的读取指令，以使得所述OLT读取所述时序参数并基于所述时序参数与所述光模块对应的光网络单元ONU进行数据交互。
在一种可能的实现方式中，该装置包括：处理器、收发器和存储器，该处理器被配置为支持光模块执行上述第二方面提供的方法中相应的功能。收发器用于指示光模块与OLT以及ONU以及之间的通信，接收该OLT发送的读取指令以及响应该读取指令。该存储器用于与处理器耦合，其保存光模块必要的程序指令和数据，例如存储时序参数。
在一种可能的实现方式中，当该装置为光模块内的芯片时，该芯片包括：处理单元、收发单元和存储单元。该收发单元例如可以是该芯片上的输入/输出接口、管脚或电路等，接收读取指令并响应该读取指令将时序参数传送给与此芯片耦合的其他芯片或模块中。该处理单元例如可以是处理器，此处理器用于根据所述时序参数确定所述光模块对应的时序信息。该处理单元可执行存储单元存储的计算机执行指令，以支持光模块执行上述第二方面提供的方法。该存储单元可以为该芯片内的存储单元，如寄存器、缓存等，该存储单元还可以是位于该芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
在一种可能实现方式中，该装置包括通信接口和逻辑电路，该通信接口用于与光线路终端OLT交互认证确定时序参数；该逻辑电路，用于将所述时序参数存储在自身寄存器；该通信接口，还用于在***所述OLT处于工作状态时，接收所述OLT的读取指令；响应所述OLT的读取指令，向所述OLT传送所述时序参数。
其中，上述任一处提到的处理器，可以是一个通用中央处理器(Central Processing Unit，CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制上述各方面时序信息的配置方法的程序执行的集成电路。
第五方面，本申请实施例提供一种计算机可读存储介质，该计算机存储介质存储有计算机指令，该计算机指令用于执行上述各方面中任意一方面任意可能的实施方式该的方法。
第六方面，本申请实施例提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面中任意一方面该的方法。
第七方面，本申请提供了一种芯片***，该芯片***包括处理器，用于支持通信装置实现上述方面中所涉及的功能，例如生成或处理上述方法中所涉及的数据和/或信息。在一种可能的设计中，该芯片***还包括存储器，该存储器，用于保存通信装置必要的程序指令和数据，以实现上述各方面中任意一方面的功能。该芯片***可以由芯片构成，也可以包含芯片和其他分立器件。
一种可能的实现方式中，在芯片***运行在该OLT侧时，可以支持该OLT执行上述第一方面提供的方法；
又一种可能的实现方式中，在芯片***运行在光模块时，可以支持该光模块执行上述第二方面提供的方法。
第八方面，本申请实施例提供一种通信***，该***包括上述方面所述的光模块、OLT以及ONU。
附图说明
图1为PON接入***的一个上行数据发送示意图；
图2为PON接入***的一个下行数据发送示意图；
图3为ONU的上行数据包的数据格式示意图；
图4为本申请实施例中光模块的结构示意图；
图5为一种OLT的时序配置方式流程示意图；
图6为本申请实施例中时序信息的配置方法的一个实施例示意图；
图7为本申请实施例中时序信息配置的一个流程示意图；
图8为本申请实施例中光线路终端装置的一个实施例示意图；
图9为本申请实施例中光线路终端装置的另一个实施例示意图；
图10为本申请实施例中光模块装置的一个实施例示意图；
图11为本申请实施例中光模块装置的另一个实施例示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着新应用场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块的过程、方法、***、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块。在本申请中出现的对步骤进行的命名或者编号，并不意味着必须按照命名或者编号所指示的时间/逻辑先后顺序执行方法流程中的步骤，已经命名或者编号的流程步骤可以根据要实现的技术目的变更执行次序，只要能达到相同或者相类似的技术效果即可。本申请中所出现的单元的划分，是一种逻辑上的划分，实际应用中实现时可以有另外的划分方式，例如多个单元可以结合成或集成在另一个***中，或一些特征可以忽略，或不执行，另外，所显示的或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元之间的间接耦合或通信连接可以是电性或其他类似的形式，本申请中均不作限定。并且，作为分离部件说明的单元或子单元可以是也可以不是物理上的分离，可以是也可以不是物理单元，或者可以分布到多个电路单元中，可以根据实际的需要选择其中的部分或全部单元来实现本申请方案的目的。本申请中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。还应当理解，在本申请实施例中，“一个或多个”是指一个、两个或两个以上；“和 /或”，描述关联对象的关联关系，表示可以存在三种关系；例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A、B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
为了便于理解，首先对于现有技术的PON接入***进行介绍。PON技术是一种点到多点的光纤接入技术。PON***可以包括OLT、光分配网络(optical distribution network，ODN)和至少一个ONU。OLT通过ODN与多个ONU连接。如图1和图2所示，PON接入***的结构由三部分组成，分别是OLT、ODN和ONU。其中OLT是放置在局端的ON协议的汇聚设备；ODN是一个连接OLT和ONU的无源设备，它的功能是分发下行数据，并集中上行数据；在PON接入***中，该ONU可以用于提供用户侧接口也可以直接提供用户端口功能。若ONU直接提供用户端口功能，则称为光网络终端(optical network terminal，ONT)。因此为了便于理解，下文所提到的ONU统指可以直接提供用户端口功能的ONT和提供用户侧接口的ONU。在当前的PON接入***中，上行是通过TDMA的方式传输数据。即当ONU注册成功之后，OLT会根据***的配置给ONU分配特定的时隙以进行数据传输。ONU根据分配的时隙按次序发送数据，避免了上行数据冲突。其具体过程可以如图1所示，OLT给ONU1、ONU2以及ONU3分配相应的时隙。其中ONU1在时隙1里发送数据1，ONU2在时隙2里发送数据2，ONU3在时隙3里发送数据3；然后OLT根据时隙的先后顺序接收数据1至数据3。下行的方向该OLT采用广播的方式发送数据，即所有的ONU都能收到相同的数据。在OLT上，下行数据流被封装成为以太网报文，附加相应的ID，该ID用于指示该报文所属的ONU。在分光器处，该报文被分为三组信号广播到每个支路。ONU接收到OLT发送的数据后，根据ID对数据流进行判断是进行处理还是进行丢弃。其具体过程可以如图2所示，该OLT需要针对三个ONU(如ONU1至ONU3)发送数据包，其中利用ID分别指示数据包1对应ONU1，数据包2对应ONU2，数据包3对应ONU3。然后在分光器处将包含该数据包1至该数据包3的数据分为三组信号广播至每个支路，然后该ONU1根据该ID确定各自对应的数据包，然后接收自己对应的数据包，丢弃其他数据包。比如，ONU1接收数据包1丢弃数据包2和数据包3，ONU2接收数据包2丢弃数据包1和数据包3。
通过上述方案可知，从整个***设计的角度而言，在下行方向只有OLT一个信号源，ONU接收广播帧。对于某一个特定的ONU来讲，接收路径不变，其接收信号电平和相位特性是相对稳定的，因此不会存在突发接收问题。但是在上行方向上，对于OLT来讲存在多个信号源(ONU)；ONU与OLT之间的不同距离以及链路特性上的差异，会造成各ONU的发送功率相同，OLT接收时却各不相同，这就需要OLT端的接收机支持突发接收。同时从整个***优化的角度而言，要求ONU在没有传送信号时处于关断状态，而在传送信号时要求很快打开，这就需要ONU支持突发发射的工作模式。因此ONU的上行数据包的格式可以如图3所示，即上行突发接收总开销包括防护时间(Guard time)、前导码(Preamble)、定界符(Delimiter)和有效净荷。其中防护时间包括关光时间(Turn off)、开光时间(Turn on)、前一个突发光的后防抖、当前突发光的前防抖和复位时间。而OLT为了支持突发接收，该OLT需要与突发接收机(即OLT光模块)进行配合使用。该OLT光模块(为便于理解，下文所提及的光模块均指代OLT光模块)作为实现突发接收的核心器件，其主要作用 是用于实现光-电或者电-光转换。其主要包括接收部分和发射部分，该接收部分实现光-电变换，该发射部分实现电-光变换。该光模块的结构可以如图4所示，其中，各功能单元的作用如下：
激光器：把电信号转换为光信号的器件。
监控二级管：接收激光器的光功率，用于监控激光器的电流，与自动功率控制电路完成激光器出光功率的控制。
激光驱动器：用于驱动和控制激光器的工作，主要完成把输入的电信号转换成激光器驱动信号，同时控制激光器工作正常。
探测器：用于接收光信号，完成光信号到电流信号的转换。
跨阻放大器(trans-impedance amplifier，TIA)用于放大光电探测器输出的电流信号，同时把电流信号转换成电压信号输出。
限幅放大器：主要是放大TIA输出的电压信号，并把信号转换成标准的数字电平信号。
基于该光模块的功能，该OLT需要获知与光模块相关的多种信息确定满足***规格要求的时序信息。其中与光模块相关的信息包括但不限于数据恢复性能、MAC BCDR的能力、突发接收是否需要Reset、需要多少个复位等一种或多种。时序信息包括但不限于突发开销数据、Preamble长度、Reset信号的位置等一种或多种。***规格指该OLT在PON接入***中需要达到的参数，比如需要满足一定的时延需求。OLT根据时序信息，实现OLT与光模块之间的有序配合，从而高效完成上行突发数据接收和恢复。而目前为了实现该OLT与光模块之间的有序配合，通常为OLT预配置时序映射表(该时序映射表包括时序序号，以及该时序序号对应的时序信息。如时序序号为1，对应的时序信息为A；时序序号为2，对应的时序信息为B)，光模块加工过程中预配置光模块相对应的时序序号，当光模块插在OLT上使用时，OLT读取光模块内部的时序序号，通过时序序号查找时序映射表，并根据时序映射表中的时序信息配置光模块对应的单板寄存器，如图5所示的一种示例性的实现方式中，在该OLT设备中预配置的时序映射表中包括了时序信息1，该时序信息1适配光模块A，并完成***联调测试。为了实现OLT设备与光模块可以正常工作，后续新引入的所有其他光模块都必须完全匹配该时序信息1。若后续的光模块B采用不同的工作模式而无法兼容时序信息1时，该光模块B则无法应用。
为便于理解，下面对于时序序号、时序信息、时序参数以及时序系数之间的关系进行说明：
时序信息：本申请文件中，该时序信息是用于实现光模块、OLT以及ONU正常数据交互的信息，其包括但不限于突发总开销、前导码长度、复位信号的位置。
时序序号：在OLT预置的时序映射表中与时序信息为一一对应的关系。一种示例性方案中，该时序序号与时序信息之间的关系可如表1所示：
表1
时序序号 时序信息
1 突发总开销A1，前导码长度A1……
2 突发总开销B1，前导码长度B1……
时序系数：本申请文件中，该时序系数为预置于OLT中的固定参数。
时序参数：本申请文件中，该时序参数预置于光模块的寄存器中。该时序参数可以是该光模块对应的时序信息，也可以是获取时序信息的中间值。当该时序参数为中间值时，该OLT可以根据预置于该OLT中的时序系数和该预置于该光模块的时序参数确定该光模块对应的时序信息。比如该光模块对应的时序信息中突发总开销数据为100纳米，OLT存储的时序系数为4，则该时序参数中用于指示突发总开销数据的参数可以为25纳米。
因此，为了解决上述方案中存在的问题，实现OLT可以灵活适配不同时序要求的光模块，本申请实施例提供一种时序信息的配置方法以及相关装置。
下面结合具体的实施例对本申请的时序信息的配置方法进行介绍。
参照图6所示，示出了本申请实施例中一种时序信息的配置方法。以下实施例将以OLT与光模块进行说明。
601、光模块与OLT交互认证确定与该光模块对应的时序参数，该时序参数预置于该光模块中。
在光模块研发阶段，将该光模块与OLT进行交互认证，从而确定该光模块工作时的时序参数，然后该光模块将该时序参数写入与该OLT预先约定好的寄存器地址，该寄存器地址位于该光模块中。其中，一种示例性方案中，该时序参数可以如表2所示：
表2
光模块 突发接收总开销 Preamble长度 Reset信号位置
A XX XX XX
可以理解的是，上述仅展示了该时序参数的部分信息，具体的内容可以根据实际情况进行配置。同时该突发接收总开销、Preamble长度以及Reset信号位置等信息的计数单位可以根据实际情况进行设置，比如设置为纳秒或者默认为单位，具体此处不做限定。
在本申请实施例中，该光模块研发阶段的时序参数可以是直接使用的时序信息，也可以是根据OLT存储的时序系数得到的时序参数，此处该时序系数为该OLT已存储的固定参数。若为后一种情况，则该OLT可以在自身存储一个固定的时序系数，当光模块***该OLT工作时，该OLT可以根据该OLT存储的该时序系数和该光模块存储的时序参数确定该光模块工作时的时序信息。比如，该OLT存储的时序系数为A，而各个光模块与其交互认证之后各自得到的时序参数(例如光模块1的时序参数为B，光模块2的时序参数为C)，然后当各个光模块***该OLT工作时，该OLT可以根据该系数和该各个光模块的时序参数得到各个光模块的时序信息。比如光模块1的时序信息为A*B，该光模块2的时序信息为A*C。
602、在该光模块***该OLT工作时，该OLT读取该时序参数。
在该光模块***该OLT工作时，该OLT通过管理通道(如集成电路总线(inter-integrated circuit，IIC))从该光模块的寄存器中读取该光模块存储的时序参数。
603、该OLT根据该时序参数确定该光模块对应的时序信息。
604、该OLT将该时序信息配置给与该光模块对应的ONU。
该OLT将该时序信息发送给与该光模块对应的ONU，从而通知该ONU可以按照该时序信息进行数据发送和接收。
605、该OLT根据该时序信息与该ONU进行数据交互。
其具体过程可以如图7所示：在该光模块***到该OLT之后，该OLT通过管理通道从该光模块的寄存器读取光模块内部存储的时序信息，然后根据该光模块内部存储的时序信息配置该光模块以及与该光模块对应的ONU的时序配置参数；最后OLT将该时序配置参数配置给该光模块对应的MAC接口以及该ONU，最后控制该光模块与该ONU进行数据交互。
具体请参阅图8所示，本申请实施例中该光线路终端装置800包括：读取单元801、处理单元802、配置单元803，其中读取单元801、处理单元802、配置单元803通过总线连接。光线路终端装置800可以是上述方法实施例中的OLT，也可以配置为OLT内的一个或多个芯片。光线路终端装置800可以用于执行上述方法实施例中的OLT的部分或全部功能。同时，图8仅示出了该光线路终端装置涉及到本申请实施例的部分模块。
例如，该读取单元801，用于读取光单元中已存储的时序参数；该处理单元802，用于根据所述时序参数确定所述光模块对应的时序信息；该配置单元803，用于为与所述光模块对应的光网络单元ONU配置所述时序信息。
可选的，该光线路终端装置800还包括存储单元，该存储单元可以存储执行指令，此时该存储单元与处理单元802耦合，使得处理单元802可执行存储单元中存储的计算机执行指令以实现上述方法实施例中OLT的功能。在一个示例中，光线路终端装置800中可选的包括的存储单元可以为芯片内的存储单元，如寄存器、缓存等，该存储单元还可以是位于芯片外部的存储单元，如ROM或可存储静态信息和指令的其他类型的静态存储设备，RAM等。
应理解，上述图8对应实施例中OLT的各模块之间所执行的流程与前述图6至图7中对应方法实施例中的OLT执行的流程类似，具体此处不再赘述。
图9示出了上述实施例中一种光线路终端装置900可能的结构示意图，该光线路终端装置900可以配置成是前述OLT。该光线路终端装置900可以包括：处理器902、计算机可读存储介质/存储器903、收发器904、输入设备905和输出设备906，以及总线901。其中，处理器，收发器，计算机可读存储介质等通过总线连接。本申请实施例不限定上述部件之间的具体连接介质。
一个示例中，该收发器904读取光单元中已存储的时序参数；该处理器904根据所述时序参数确定所述光模块对应的时序信息；该收发器904向与该光模块对应的光网络单ONU发送该时序信息，从而实现为ONU配置所述时序信息的功能。
该收发器904与该处理器902可以实现上述图6至图7中任一实施例中相应的步骤， 具体此处不做赘述。
可以理解的是，图9仅仅示出了光线路终端装置的简化设计，在实际应用中，光线路终端装置可以包含任意数量的收发器，处理器，存储器等，而所有的可以实现本申请的光线路终端装置都在本申请的保护范围之内。
上述装置900中涉及的处理器902可以是通用处理器，例如CPU、网络处理器(network processor，NP)、微处理器等，也可以是ASIC，或一个或多个用于控制本申请方案程序执行的集成电路。还可以是数字信号处理器(digital signal processor，DSP)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。控制器/处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。处理器通常是基于存储器内存储的程序指令来执行逻辑和算术运算。
上述涉及的总线901可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图9中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
上述涉及的计算机可读存储介质/存储器903还可以保存有操作***和其他应用程序。具体地，程序可以包括程序代码，程序代码包括计算机操作指令。更具体的，上述存储器可以是ROM、可存储静态信息和指令的其他类型的静态存储设备、RAM、可存储信息和指令的其他类型的动态存储设备、磁盘存储器等等。存储器903可以是上述存储类型的组合。并且上述计算机可读存储介质/存储器可以在处理器中，还可以在处理器的外部，或在包括处理器或处理电路的多个实体上分布。上述计算机可读存储介质/存储器可以具体体现在计算机程序产品中。举例而言，计算机程序产品可以包括封装材料中的计算机可读介质。
可以替换的，本申请实施例还提供一种通用处理***，例如通称为芯片，该通用处理***包括:提供处理器功能的一个或多个微处理器；以及提供存储介质的至少一部分的外部存储器，所有这些都通过外部总线体系结构与其它支持电路连接在一起。当存储器存储的指令被处理器执行时，使得处理器执行光线路终端装置在图6至图7该实施例中的时序信息的配置方法中的部分或全部步骤，和/或用于本申请所描述的技术的其它过程。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于终端中。当然，处理器和存储介质也可以作为分立组件存在于光线路终端装置中。
具体请参阅图10所示，本申请实施例中该光模块装置1000包括：交互认证单元 1001、存储单元1002、接收单元1003和响应单元1004，其中交互认证单元1001、存储单元1002、接收单元1003和响应单元1004通过总线连接。光模块装置1000可以是上述方法实施例中的光模块，也可以配置为光模块内的一个或多个芯片。光模块装置1000可以用于执行上述方法实施例中的光模块的部分或全部功能。同时，图10仅示出了该光模块装置涉及到本申请实施例的部分模块。
例如，该交互认证单元1001，用于与光线路终端OLT交互认证确定时序参数；该存储单元1002，用于将所述时序参数存储在自身寄存器；接收单元1003，用于在***所述OLT处于工作状态时，接收所述OLT的读取指令；响应单元1004，用于响应所述OLT的读取指令，向所述OLT传送所述时序参数。
可选的，该存储单元1002可以存储执行指令，此时该存储单元1002与处理单元耦合，使得处理单元可执行存储单元中存储的计算机执行指令以实现上述方法实施例中光模块的功能。在一个示例中，光模块装置1000中可选的包括的存储单元可以为芯片内的存储单元，如寄存器、缓存等，该存储单元还可以是位于芯片外部的存储单元，如ROM或可存储静态信息和指令的其他类型的静态存储设备，RAM等。
应理解，上述图10对应实施例中光模块的各模块之间所执行的流程与前述图6至图7中对应方法实施例中的光模块执行的流程类似，具体此处不再赘述。
图11示出了上述实施例中一种光模块装置1100可能的结构示意图，该光模块装置1100可以配置成是前述光模块。该光模块装置1100可以包括：处理器1102、计算机可读存储介质/存储器1103、收发器1104、输入设备1105和输出设备1106，以及总线1101。其中，处理器，收发器，计算机可读存储介质等通过总线连接。本申请实施例不限定上述部件之间的具体连接介质。
一个示例中，该收发器1104与光线路终端OLT交互认证；该处理器1104确定时序参数；该存储器1103存储所述时序参数；该收发器1104在***所述OLT处于工作状态时，接收所述OLT的读取指令；响应所述OLT的读取指令，向所述OLT传送所述时序参数。
该收发器1104、该处理器1102和该存储器1103可以实现上述图6至图7中任一实施例中相应的步骤，具体此处不做赘述。
可以理解的是，图11仅仅示出了光模块装置的简化设计，在实际应用中，光模块装置可以包含任意数量的收发器，处理器，存储器等，而所有的可以实现本申请的光模块装置都在本申请的保护范围之内。
上述装置1100中涉及的处理器1102可以是通用处理器，例如CPU、网络处理器(network processor，NP)、微处理器等，也可以是ASIC，或一个或多个用于控制本申请方案程序执行的集成电路。还可以是数字信号处理器(digital signal processor，DSP)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。控制器/处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。处理器通常是基于存储器内存储的程序指令来执行逻辑和算术运算。
上述涉及的总线1101可以是外设部件互连标准(peripheral component  interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图11中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
上述涉及的计算机可读存储介质/存储器1103还可以保存有操作***和其他应用程序。具体地，程序可以包括程序代码，程序代码包括计算机操作指令。更具体的，上述存储器可以是ROM、可存储静态信息和指令的其他类型的静态存储设备、RAM、可存储信息和指令的其他类型的动态存储设备、磁盘存储器等等。存储器1103可以是上述存储类型的组合。并且上述计算机可读存储介质/存储器可以在处理器中，还可以在处理器的外部，或在包括处理器或处理电路的多个实体上分布。上述计算机可读存储介质/存储器可以具体体现在计算机程序产品中。举例而言，计算机程序产品可以包括封装材料中的计算机可读介质。
可以替换的，本申请实施例还提供一种通用处理***，例如通称为芯片，该通用处理***包括:提供处理器功能的一个或多个微处理器；以及提供存储介质的至少一部分的外部存储器，所有这些都通过外部总线体系结构与其它支持电路连接在一起。当存储器存储的指令被处理器执行时，使得处理器执行光线路终端装置在图6至图7该实施例中的时序信息的配置方法中的部分或全部步骤，和/或用于本申请所描述的技术的其它过程。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于终端中。当然，处理器和存储介质也可以作为分立组件存在于光模块装置中。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的***，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既 可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (22)

  1. 一种时序信息的配置方法，其特征在于，包括：
    光线路终端OLT读取光模块中已存储的时序参数；
    所述OLT根据所述时序参数确定所述光模块对应的时序信息；
    所述OLT为与所述光模块对应的光网络单元ONU配置所述时序信息。
  2. 根据权利要求1所述的方法，其特征在于，所述时序参数由所述光模块与所述OLT交互认证确定。
  3. 根据权利要求1或2所述的方法，其特征在于，所述时序参数存储于所述光模块与所述OLT协议约定的寄存器地址。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，光线路终端OLT读取光模块中已存储的时序参数包括：
    所述OLT通过管理通道读取所述光模块中已存储的所述时序参数。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述时序信息包括突发总开销数据、前导码Preamble长度、复位Reset信号位置。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述方法还包括：
    所述OLT根据所述时序信息与所述ONU进行数据交互。
  7. 一种时序信息的配置方法，其特征在于，包括：
    光模块与光线路终端OLT交互认证确定时序参数；
    所述光模块将所述时序参数存储在自身寄存器；
    在所述光模块***所述OLT处于工作状态时，所述光模块接收所述OLT的读取指令；
    所述光模块响应所述OLT的读取指令，向所述OLT传送所述时序参数。
  8. 根据权利要求7所述的方法，其特征在于，所述时序信息包括突发总开销数据、前导码Preamble长度、复位Reset信号位置。
  9. 根据权利要求7至8中任一项所述的方法，其特征在于，所述光模块响应所述OLT的读取指令，向所述OLT传送所述时序参数包括：
    所述光模块响应所述OLT的读取指令，通过管理通道向所述OLT传送所述时序参数。
  10. 一种光线路终端装置，其特征在于，包括：
    读取单元，用于读取光单元中已存储的时序参数；
    处理单元，用于根据所述时序参数确定所述光模块对应的时序信息；
    配置单元，用于为与所述光模块对应的光网络单元ONU配置所述时序信息。
  11. 根据权利要求10所述的装置，其特征在于，所述时序参数由所述光模块与所述OLT交互认证确定。
  12. 根据权利要求10或11所述的装置，其特征在于，所述时序参数存储于所述光模块与所述OLT协议约定的寄存器地址。
  13. 根据权利要求11至12中任一项所述的装置，其特征在于，所述读取单元，具体用于通过管理通道读取所述光模块中已存储的所述时序参数。
  14. 根据权利要求11至13中任一项所述的装置，其特征在于，所述时序信息包括突 发总开销数据、前导码Preamble长度、复位Reset信号位置。
  15. 根据权利要求11至14中任一项所述的装置，其特征在于，所述装置还包括收发单元，用于根据所述时序信息与所述ONU进行数据交互。
  16. 一种光模块装置，其特征在于，包括：
    交互认证单元，用于与光线路终端OLT交互认证确定时序参数；
    存储单元，用于将所述时序参数存储在自身寄存器；
    接收单元，用于在***所述OLT处于工作状态时，接收所述OLT的读取指令；
    响应单元，用于响应所述OLT的读取指令，向所述OLT传送所述时序参数。
  17. 根据权利要求16所述的装置，其特征在于，所述时序信息包括突发总开销数据、前导码Preamble长度、复位Reset信号位置。
  18. 根据权利要求16或17所述的装置，其特征在于，所述响应单元，具体用于响应所述OLT的读取指令，向所述OLT传送所述时序参数。
  19. 一种光线路终端装置，其特征在于，包括至少一个处理器和存储器，所述处理器用于与所述存储器耦合，所述处理器调用所述存储器中存储的指令以控制所述光模块装置执行权利要求1至6中任一项所述的方法。
  20. 一种光模块装置，其特征在于，包括至少一个处理器和存储器，所述处理器用于与所述存储器耦合，所述处理器调用所述存储器中存储的指令以控制所述光模块装置执行权利要求7至9中任一项所述的方法。
  21. 一种光通信***，其特征在于，包括如权利要求10至15中任一项所述的光线路终端装置和如权利要求16至18中任一项所述的光模块装置以及ONU。
  22. 一种计算存储介质，其特征在于，所述计算机存储介质存储有计算机指令，所述计算机指令用于执行上述权利要求1至权利要求9中任意任一项所述的方法。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107529100A (zh) * 2016-06-21 2017-12-29 中兴通讯股份有限公司 无源光网络模式切换方法及装置、无源光网络设备及***
CN107547952A (zh) * 2017-09-22 2018-01-05 烽火通信科技股份有限公司 Onu适应10g/10g对称和10g/1g非对称的方法及***
CN108540231A (zh) * 2017-12-14 2018-09-14 武汉电信器件有限公司 一种自适应的olt光模块及其控制方法
US20200355881A1 (en) * 2019-05-10 2020-11-12 Lumentum Japan, Inc. Optical communication module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112492412A (zh) * 2020-09-30 2021-03-12 中兴通讯股份有限公司 Olt接收机参数配置方法、装置、存储介质及电子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107529100A (zh) * 2016-06-21 2017-12-29 中兴通讯股份有限公司 无源光网络模式切换方法及装置、无源光网络设备及***
CN107547952A (zh) * 2017-09-22 2018-01-05 烽火通信科技股份有限公司 Onu适应10g/10g对称和10g/1g非对称的方法及***
CN108540231A (zh) * 2017-12-14 2018-09-14 武汉电信器件有限公司 一种自适应的olt光模块及其控制方法
US20200355881A1 (en) * 2019-05-10 2020-11-12 Lumentum Japan, Inc. Optical communication module

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4240022A4

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