WO2022110736A9 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022110736A9
WO2022110736A9 PCT/CN2021/097268 CN2021097268W WO2022110736A9 WO 2022110736 A9 WO2022110736 A9 WO 2022110736A9 CN 2021097268 W CN2021097268 W CN 2021097268W WO 2022110736 A9 WO2022110736 A9 WO 2022110736A9
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WO
WIPO (PCT)
Prior art keywords
light
display area
emitting unit
pixel circuit
pattern
Prior art date
Application number
PCT/CN2021/097268
Other languages
English (en)
French (fr)
Other versions
WO2022110736A1 (zh
Inventor
杜丽丽
刘聪
黄炜赟
吴超
曾超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001352.7A priority Critical patent/CN114830220A/zh
Priority to US17/828,194 priority patent/US20220293715A1/en
Publication of WO2022110736A1 publication Critical patent/WO2022110736A1/zh
Publication of WO2022110736A9 publication Critical patent/WO2022110736A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED display panels have been widely used due to their advantages of self-luminescence, low driving voltage, and fast response.
  • the OLED display panel includes a plurality of pixel units, and each pixel unit includes a light-emitting unit and a pixel circuit connected to the light-emitting unit.
  • the present application provides a display panel and a display device, and the technical solutions are as follows:
  • a display panel comprising:
  • the base substrate has an adjacent first display area and a second display area;
  • the plurality of first light-emitting unit groups are located in the first display area;
  • the plurality of first pixel circuit groups are located in the first display area, and the first pixel circuit groups are connected to one of the first light-emitting unit groups;
  • a plurality of second light-emitting unit groups the plurality of second light-emitting unit groups are located in the second display area, and the plurality of second light-emitting unit groups include: at least one first-type second light-emitting unit group and at least one first light-emitting unit group Two-type second light-emitting unit groups, the at least one second-type second light-emitting unit group is close to the first display area relative to the at least one first-type second light-emitting unit group;
  • a plurality of second pixel circuit groups are located in the first display area, and the plurality of pixel circuit groups include: at least one first type of second pixel circuit group and at least one second type of pixel circuit group a second pixel circuit group, the at least one second type second pixel circuit group is close to the second display area relative to the at least one first type second pixel circuit group;
  • the plurality of dummy electrode pattern groups located in the first display area, the plurality of dummy electrode pattern groups including: at least one first pattern group and at least one second pattern group, the at least one second pattern group is opposite to the the at least one first pattern group is close to the second display area;
  • a plurality of first connection lines, the plurality of first connection lines and the plurality of dummy electrode pattern groups are located on different layers, and one end of the first connection lines is connected to one of the first type of second light-emitting units group connection, and the other end is connected with one of the first type of second pixel circuit groups through one of the first pattern groups;
  • the plurality of second connection wires and the plurality of first connection wires are located on different layers, and one end of the second connection wires is connected to one of the second type
  • the two light-emitting unit groups are connected, and the other end is connected to one of the second type of second pixel circuit groups through one of the second pattern groups.
  • the orthographic projection of the dummy electrode pattern group on the base substrate at least partially overlaps with the orthographic projection of the at least one second pixel circuit group on the base substrate, and the dummy electrode
  • the orthographic projection of the pattern group on the base substrate does not overlap with the orthographic projection of any one of the first light-emitting unit groups on the base substrate.
  • each of the first light-emitting unit group and each of the second light-emitting unit groups includes a plurality of light-emitting units, and the light-emitting units include first electrodes stacked in sequence along a direction away from the base substrate , the light-emitting layer and the second electrode;
  • the dummy electrode pattern group includes a plurality of dummy electrode patterns, and the number of the plurality of dummy electrode patterns included in one of the dummy electrode pattern groups is the same as the number of the plurality of light-emitting units included in one light-emitting unit group, And the dummy electrode pattern and the first electrode are located in the same layer.
  • the display panel further includes: a pixel defining layer located between the first electrode and the light-emitting layer;
  • the pixel defining layer has a plurality of openings, one of the openings is used to expose a first electrode of one of the light-emitting units, and the orthographic projections of the plurality of openings on the base substrate are in the same range as any of the dummy electrode patterns.
  • the orthographic projections on the base substrate do not overlap.
  • a plurality of the dummy electrode patterns in one of the dummy electrode pattern groups are in one-to-one correspondence with a plurality of first light-emitting units in one of the first light-emitting unit groups, and the dummy electrode patterns correspond to the corresponding ones.
  • the shape and area of the first electrodes in the first light-emitting unit are the same.
  • one of the first light-emitting unit groups includes: a first light-emitting unit of a first color, two first light-emitting units of a second color, and a first light-emitting unit of a third color;
  • One of the second light-emitting unit groups includes: a second light-emitting unit of a first color, two second light-emitting units of a second color, and a second light-emitting unit of a third color.
  • the distance between the centers of two first light-emitting units of the first color adjacent in the row direction in the first display area is the same as the distance between the centers of the two adjacent first light emitting units in the row direction in the second display area.
  • the distances between the centers of the second light-emitting units of the first color are equal;
  • the distance between the centers of the two adjacent first light-emitting units of the second color in the row direction in the first display area is the The distances between the centers of the second light-emitting units are equal;
  • the distance between the centers of the two adjacent first light-emitting units of the third color in the row direction in the first display area is the distance between the centers of the two adjacent third color first light-emitting units in the row direction in the second display area
  • the distances between the centers of the second light emitting units are equal.
  • the area of the orthographic projection of the opening of the first light-emitting unit of the first color exposed in the first display area on the base substrate is the same as the area of the orthographic projection of the opening of the first light-emitting unit of the first color exposed in the second display area.
  • the area of the orthographic projection of the opening on the base substrate is equal, and the area of the orthographic projection of the first electrode of the first light-emitting unit of the first color in the first display area on the base substrate is greater than that of the second the area of the orthographic projection of the first electrode of the second light-emitting unit of the first color in the display area on the base substrate;
  • the area of the orthographic projection of the opening of the first light-emitting unit exposing the second color in the first display area on the base substrate is aligned with the opening of the second light-emitting unit exposing the second color in the second display area.
  • the area of the orthographic projection on the base substrate is equal, and the area of the orthographic projection of the first electrode of the first light-emitting unit of the second color in the first display area on the base substrate is larger than that in the second display area.
  • the area of the orthographic projection of the opening of the first light-emitting unit exposing the third color in the first display area on the base substrate is in line with the opening of exposing the second light-emitting unit of the third color in the second display area.
  • the area of the orthographic projection on the base substrate is equal, and the area of the orthographic projection of the first electrode of the first light-emitting unit of the third color in the first display area on the base substrate is larger than that in the second display area.
  • the area of the orthographic projection of the first electrodes of the second light-emitting units of the three colors on the base substrate is equal, and the area of the orthographic projection of the first electrode of the first light-emitting unit of the third color in the first display area on the base substrate is larger than that in the second display area.
  • the first electrode of the first light-emitting unit in the first light-emitting unit group includes: a first body pattern, and a first connection pattern connected to the first body pattern, the first body At least part of the pattern is in contact with the light-emitting layer of the first light-emitting unit, and the first connection pattern is connected with the first pixel circuit group;
  • the dummy electrode pattern includes: a second main body pattern, and a second connection pattern and a third connection pattern respectively connected to the second main body pattern, the second main body pattern and the light emission of any one of the first light-emitting units
  • the layers are not in contact, and the second connection pattern is connected to the second pixel circuit group, and the third connection pattern is connected to the second light-emitting unit group through the first connection wire or the second connection wire .
  • the first electrode of the first light-emitting unit further includes: a fourth connection pattern connected to the first body pattern;
  • the orthographic projection of the first body pattern of the first electrode in the first light-emitting unit on the base substrate, and the second body pattern of the dummy electrode pattern corresponding to the first light-emitting unit on the base substrate The shape and area of the orthographic projection are the same;
  • the orthographic projection of the first connection pattern of the first electrode in the first light-emitting unit on the base substrate, and the second connection pattern of the dummy electrode pattern corresponding to the first light-emitting unit on the base substrate The shape and area of the orthographic projection on are the same;
  • the orthographic projection of the fourth connection pattern of the first electrode in the first light-emitting unit on the base substrate, and the third connection pattern of the dummy electrode pattern corresponding to the first light-emitting unit on the base substrate The shape and area of the orthographic projection on are the same.
  • the orthographic projection of the first connection pattern on the base substrate does not overlap with the orthographic projection of the plurality of first connection traces on the base substrate, and the fourth connection pattern The orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the plurality of first connection traces on the base substrate;
  • the orthographic projection of the second connection pattern on the base substrate does not overlap with the orthographic projection of the plurality of first connection traces on the base substrate, and the third connection pattern is on the substrate
  • the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the plurality of first connection traces on the base substrate.
  • the colors of the first light-emitting units corresponding to the two target dummy electrode patterns in the two adjacent first pattern groups in the row direction are the same, and the third target dummy electrode pattern of the two target dummy electrode patterns is the same color.
  • the connection patterns are respectively connected with the second light-emitting unit group through one of the first connection lines;
  • the first pixel circuit group includes a plurality of first pixel circuit units, each of the first pixel circuit units at least includes: a first pixel circuit and a second pixel circuit, and the first pixel circuit unit At least two pixel circuits in the first light-emitting unit group are configured to be electrically connected to the first electrodes of the same first light-emitting unit in the first light-emitting unit group.
  • the first connection pattern included in the first electrode of the first light-emitting unit includes: a first main body connection part extending along the target direction and two first end parts located at both ends of the first main body connection part;
  • the two first end portions are respectively electrically connected to the first pixel circuit and the second pixel circuit, and the target direction is substantially parallel to the row direction.
  • the second pixel circuit group includes a plurality of second pixel circuit units, each of the second pixel circuit units at least includes: a third pixel circuit and a fourth pixel circuit, and the second pixel circuit unit At least two pixel circuits in are configured to be electrically connected to the same dummy electrode pattern.
  • the second connection pattern included in the dummy electrode pattern includes: a second main body connection part extending along the target direction and two second end parts located at both ends of the second main body connection part;
  • the two second end portions are respectively electrically connected to the third pixel circuit and the fourth pixel circuit, and the target direction is substantially parallel to the row direction.
  • the plurality of second connection wires are located on the same layer as the dummy electrode pattern group.
  • connection lines of the other ends of the plurality of first connection lines are parallel to the edge of the first display area away from the second display area, and the other ends of the plurality of first connection lines The distance between the connecting line and the edge of the first display area away from the second display area is less than the distance threshold.
  • the connecting lines of the other ends of the plurality of first connecting lines and the edge of the first display area away from the second display area are both substantially parallel to the column direction.
  • the connecting lines of the other ends of the plurality of first connecting lines are collinear with the edge of the first display area away from the second display area.
  • the base substrate further includes: a third display area located on the same side of the first display area and the second display area, and the display panel further includes: multiple display areas located in the third display area a third light-emitting unit group and a plurality of third pixel circuit groups;
  • each of the third pixel circuit groups is connected to one of the third light-emitting unit groups, and the density of the third light-emitting unit groups is greater than the density of the first light-emitting unit groups and greater than the density of the plurality of first light-emitting unit groups. The density of the plurality of second light-emitting unit groups.
  • the base substrate includes: two of the first display areas and one of the second display areas, and the second display area is rectangular;
  • At least one edge of the rectangle extending in the row direction is connected to the third display area, and two edges of the rectangle extending in the column direction are respectively connected to the two first display areas.
  • the first display area is rectangular; the length of any edge of the first display area ranges from 0.1 mm to 20 mm;
  • the length of any edge of the second display area ranges from 0.2 mm to 10 mm.
  • the display panel further includes: a plurality of data lines;
  • Orthographic projections of at least part of at least one target data line located in the second display area on the base substrate among the plurality of data lines are all located in an area of the second display area close to the first display area .
  • a display device comprising: a power supply assembly and the display panel according to the above aspect;
  • the power supply assembly is used for supplying power to the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partial schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • FIG. 4 is a top view of a base substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a light-emitting unit provided by an embodiment of the present application.
  • FIG. 6 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • FIG. 7 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 8 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 9 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 10 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 11 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 12 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 13 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 14 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • 15 is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided by an embodiment of the present application.
  • Fig. 16 is the partial plane structure schematic diagram of the active semiconductor layer of the pixel circuit in the first display area provided by the embodiment of the present application;
  • FIG. 17 is a schematic diagram of a first conductive layer in a first display area provided by an embodiment of the present application.
  • FIG. 18 is a schematic diagram of an active semiconductor layer and a first conductive stack in the first display area provided by an embodiment of the present application;
  • FIG. 19 is a schematic partial plane structure diagram of the second conductive layer in the first display area provided by the embodiment of the present application.
  • 20 is a schematic diagram of stacking the active semiconductor layer, the first conductive layer and the second conductive layer in the first display area provided by the embodiment of the present application;
  • FIG. 21 is a schematic partial planar structure diagram of a source-drain metal layer of a first display area provided by an embodiment of the present application.
  • 22 is a schematic diagram of stacking an active semiconductor layer, a first conductive layer, a second conductive layer and a source-drain metal layer in the first display area provided by an embodiment of the present application;
  • FIG. 23 is a schematic diagram of the connection relationship between the first light-emitting unit group and the first pixel circuit group in the first display area provided by the embodiment of the present application;
  • FIG. 24 is a schematic diagram of a first electrode and a dummy electrode pattern provided by an embodiment of the present application.
  • 25 is a schematic diagram of stacking a first conductive layer, a second conductive layer, a source-drain metal layer, a first connection trace, a first electrode and a dummy electrode pattern in the first display area provided by an embodiment of the present application;
  • FIG. 26 shows the stacking of the active semiconductor layer, the first conductive layer, the second conductive layer, the source-drain metal layer, the first connection trace, the first electrode and the dummy electrode pattern in the first display area provided by the embodiment of the present application schematic diagram;
  • FIG. 27 shows an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer, a first connection trace, a first electrode, a dummy electrode pattern, and a pixel in the first display area provided by the embodiment of the present application
  • FIG. 28 is a schematic diagram showing the positional relationship between the first light-emitting unit group and the via hole in the first display area shown in FIG. 23;
  • 29 is a partial plan view of the first display area and the third display area in the display panel shown in FIG. 1;
  • FIG. 30 is a schematic structural diagram of a part of the pixel circuit at the junction of the third display area and the first display area provided by the embodiment of the present application;
  • FIG. 31 is a schematic diagram of the structure of the film layer where the data line connection portion at the position shown in FIG. 30 is located;
  • Figure 32 is a schematic diagram of the structure of the film layer where the data line at the position shown in Figure 30 is located;
  • 33 is a schematic structural diagram of a partial pixel circuit at the junction of the edge area of the third display area and the second display area provided by an embodiment of the present application;
  • 35 is a schematic diagram of a first electrode of a light-emitting unit group located in a third display area provided by an embodiment of the present application;
  • 36 is a schematic diagram of a first electrode of a light-emitting unit group located at a non-edge of the first display area provided by an embodiment of the present application;
  • FIG. 37 is a schematic diagram of a first electrode of a light-emitting unit group located in a second display area provided by an embodiment of the present application;
  • FIG. 38 is a schematic diagram of a first electrode of each light-emitting unit in a two-row light-emitting unit group of a first display area bordering a third display area provided in an embodiment of the present application;
  • 39 is a schematic diagram of the first electrode of each light-emitting unit in the two-column light-emitting unit group of the first display area bordering the third display area provided by the embodiment of the present application;
  • FIG. 40 is a cross-sectional view of FIG. 3 along the direction A1 to A2;
  • FIG. 41 is a cross-sectional view of FIG. 7 along the direction B1 to B2;
  • FIG. 42 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the camera of the display device may be arranged in the display area of the display panel.
  • the pixel circuits of each pixel unit in the area where the camera is located are usually arranged in the non-camera area.
  • the pixel circuit located in the non-camera area is connected to the light emitting unit located in the camera area through the connecting wires, so as to provide driving signals for the light emitting unit located in the camera area.
  • connection wires that can be arranged in the display area is limited, it is difficult to arrange a large number of light-emitting units in the camera area, which results in poor display effect of the camera area.
  • Words like “including” or “comprising” mean that the elements or items listed before “including” or “including” cover the elements or items listed after “including” or “including” and their equivalents, and do not exclude other component or object.
  • Words like “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “Down”, “Left”, “Right”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partial schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • the display panel 10 may include: a base substrate 101, a plurality of first light-emitting unit groups 102, a plurality of first pixel circuit groups 103, a plurality of second light-emitting unit groups 104, a plurality of A plurality of second pixel circuit groups 105 , a plurality of dummy electrode pattern groups 106 , a plurality of first connection wires 107 , and a plurality of second connection wires 108 .
  • FIG. 4 is a top view of a base substrate provided by an embodiment of the present application.
  • the base substrate 101 may have adjacent first display areas 101a and second display areas 101b. Two first display areas 101a and one second display area 101b are shown in FIG. 4 .
  • the second display area 101b may be an area provided with a camera.
  • a plurality of first light-emitting unit groups 102 are located in the first display area 101a, and a plurality of first pixel circuit groups 103 are located in the first display area 101a.
  • the first pixel circuit group 103 is connected to a first light-emitting unit group 102, and the first pixel circuit group 103 is used to provide a driving signal for the first light-emitting unit group 102 connected thereto, and the driving signal is used to drive the first light-emitting unit Group 102 glows.
  • a plurality of second light-emitting unit groups 104 are located in the second display area 101b, and a plurality of second pixel circuit groups 105 are located in the first display area 101a.
  • the plurality of second light-emitting unit groups 104 include: at least one first-type second light-emitting unit group 104a and at least one second-type second light-emitting unit group 104b.
  • the at least one second type second light emitting unit group 104b is closer to the first display area 101a than the at least one first type second light emitting unit group 104a.
  • the plurality of second pixel circuit groups 105 include: at least one first type second pixel circuit group 105a and at least one second type second pixel circuit group 105b.
  • the at least one second-type second pixel circuit group 105b is closer to the second display area 101b relative to the at least one first-type second pixel circuit group 105a.
  • a plurality of dummy electrode pattern groups 106 are located in the first display area 101a, and the plurality of dummy electrode pattern groups 106 include: at least one first pattern group 106a and at least one second pattern group 106b.
  • the at least one second pattern group 106b is close to the second display area 101b relative to the at least one first pattern group 106a.
  • the plurality of first connection wires 107 and the plurality of dummy electrode pattern groups 106 may be located in different layers, that is, the plurality of first connection wires 107 and the plurality of dummy electrode pattern groups 106 need to be separately prepared by two patterning processes.
  • One end of the first connecting wire 107 is connected to a first-type second light-emitting unit group 104a, and the other end is connected to a first-type second pixel circuit group 105a through a first pattern group 106a.
  • each first-type second pixel circuit group 105a located in the first display area 101a can communicate with the first-type second light-emitting unit located in the second display area 101b through the first connection traces 107 and the first pattern group 106a Group 104a is connected. Therefore, each first-type second pixel circuit group 105a can provide a driving signal for the first-type second light-emitting unit group 104a connected thereto, and the driving signal is used to drive the first-type second light-emitting unit group 104a to emit light.
  • the plurality of second connection traces 108 and the plurality of first connection traces 107 may be located in different layers, that is, the plurality of second connection traces 108 and the plurality of first connection traces 107 need to be separately prepared by two patterning processes .
  • One end of the second connecting wire 108 is connected to a second type second light emitting unit group 104b, and the other end is connected to a second type second pixel circuit group 105b through a second pattern group 106b. That is, the second type of second pixel circuit group 105b located in the first display area 101a can communicate with the second type of second light-emitting unit located in the second display area 101b through the second connection traces 108 and the second pattern group 106b.
  • Group 104b is connected.
  • each second-type second pixel circuit group 105b can provide a driving signal for the second-type second light-emitting unit group 104b connected thereto, and the driving signal is used to drive the second-type second light-emitting unit group 104b to emit light.
  • the second connecting wire 108 By arranging the second connecting wire 108, the second type of second pixel circuit group 105b in the first display area 101a close to the second display area 101b is made to be close to the second pixel circuit group 105b through the second connecting wire 108 and the second display area 101b.
  • the second-type second light-emitting unit group 104b of a display area 101a is connected, so that the second-type second light-emitting unit group 104b emits light.
  • the number of the second light-emitting unit groups 104 arranged in the second display area 101b can be increased, which not only ensures the second display area
  • the display effect of 101b can be improved, and a larger-sized camera can be allowed to be set, and the requirement on the manufacturing precision of the display panel 10 is lower.
  • the distance between the second type of second pixel circuit group 105b and the second type of second light-emitting unit group 104b connected by the second connection wire 108 is relatively small, it is not only convenient to manufacture, but also can avoid the second type of connection trace.
  • the line 108 affects the first type of second light-emitting unit group 104a in the first display area 101a to ensure the light-emitting effect of the first type of second light-emitting unit group 104a.
  • the embodiments of the present application provide a display panel, in which the plurality of second pixel circuit groups located in the first display area include the first type of second pixel circuit groups far away from the second display area, and A second type of second pixel circuit group close to the second display area.
  • the first type of second pixel circuit group is connected to the first type of second light-emitting unit group located in the second display area and far away from the first display area through the first connecting line, and the second type of second pixel circuit group is connected through the second
  • the connection wires are connected to the second type of second light-emitting unit group located in the second display area and close to the first display area.
  • the solution provided by the embodiment of the present application can also provide a driving signal for the second type of second light-emitting unit group through the second connection wire located on a different layer from the first connection wire, it can be used without adding the first connection wire.
  • the number of the second light-emitting unit groups that can be arranged in the second display area is increased, thereby ensuring the display effect of the second display area in the display panel.
  • the material of the first connection wire 107 may be a transparent material, so as to avoid the influence of the first connection wire 107 on the transmittance of the second display area 101b.
  • the material of the first connecting wire 107 may be indium tin oxide (ITO).
  • the extension direction of the plurality of first connection traces 107 may be the row direction X.
  • a maximum of 13 first connection lines 107 can be designed for each row of pixels (the number of the first connection lines 107 is limited by the width of the first connection lines 107 and the pixels of the first connection line 107 ) size). That is, the second display area 101b can be provided with a maximum of 26 pixels along the row direction X (the two first display areas 101a are respectively provided with 13 first connection lines 107, so that there are 26 first connection lines 107 and 26 pixels are connected one by one). However, if the second display area 101b needs a larger number of pixels along the row direction X, some pixels lack the corresponding first connection wires 107 to be connected to them.
  • the second type of second pixel circuit group 105b in the first display area 101a is close to the second display area 101b and the second type of second light-emitting unit group 104b in the second display area 101b is close to the first display area 101a by setting The second connection traces 108 of the second connection line 108 are connected, so as to realize the second type of the second light-emitting unit group 104b to emit light.
  • the remaining first-type second pixel circuit groups 105a are connected to the first-type second pixel circuit groups 105a in the first display area 101a through the first connecting wires 107 .
  • the second display area 101b may include a central area 101b1 and an edge area 101b2 surrounding the central area 101b1.
  • FIG. 4 schematically shows that the shape of the second display area 101b is a rectangle, the shape of the center area 101b1 of the second display area 101b is a circle, and the edge area 101b2 is an area located in the rectangle except for the center area of the circle.
  • the central area 101b1 and the edge area 101b2 of the second display area 101b may also be in other shapes, which may be set according to actual product requirements, which are not limited in the embodiments of the present application.
  • the central area 101b can be used as an under-screen camera area, the central area 101b1 is provided with a second light-emitting unit group 104, and the second pixel circuit group 105 that drives the second light-emitting unit group 104 to emit light is provided in the first display area 101a . Therefore, the central area 101b1 can be made to have a higher light transmittance to realize the imaging function, and can also be connected to the pixel circuit groups in other areas (the first display area 101a) to realize light emission, without affecting the display function of the screen .
  • the orthographic projection of each dummy electrode pattern group 106 on the base substrate 101 may at least partially overlap with the orthographic projection of at least one second pixel circuit group 105 on the base substrate 101 .
  • the same small square is used to represent the overlapping second pixel circuit group 105 and the dummy electrode pattern group 106, and are marked with 105/106.
  • the orthographic projection of each dummy electrode pattern group 106 on the base substrate 101 may at least partially overlap with the orthographic projection of a second pixel circuit group 105 on the base substrate 101 .
  • each dummy electrode pattern group 106 and any one of the first light emitting unit groups 102 on the base substrate 101 do not overlap.
  • the dummy electrode pattern group 106 does not overlap with the first light-emitting unit group 102 , which can prevent the dummy electrode pattern group 106 from affecting the first light-emitting unit 1021 in the first light-emitting unit group 102 and ensure the light emission of the first light-emitting unit 1021 Effect.
  • each of the first light-emitting unit group 102 and each of the second light-emitting unit groups 104 may include a plurality of light-emitting units, for example, the first light-emitting unit group 102 includes a plurality of first light-emitting units 1021, The second light-emitting unit group 104 includes a plurality of second light-emitting units 1041 .
  • FIG. 5 is a schematic structural diagram of a light-emitting unit provided by an embodiment of the present application. Referring to FIG.
  • the light-emitting unit may include a first electrode a1 , a light-emitting layer a2 and a second electrode a3 stacked in sequence along a direction away from the base substrate 101 .
  • the first electrode a1 may be an anode
  • the second electrode a3 may be a cathode.
  • each dummy electrode pattern group 106 may include a plurality of dummy electrode patterns 1061, the number of the plurality of dummy electrode patterns 1061 included in one dummy electrode pattern group 106, and a light-emitting unit group (the first light-emitting unit The number of the plurality of light-emitting units included in the group 102 or the second light-emitting unit group 104) is the same.
  • each dummy electrode pattern group 106 includes four dummy electrode patterns 1061
  • each light-emitting unit group includes four light-emitting units.
  • the dummy electrode pattern 1061 in the dummy electrode pattern group 106 may be located on the same layer as the first electrode a1 in the light emitting unit, and the second connecting wire 108 and the first electrode a1 are also located on the same layer. That is, the plurality of second connection wires 108 may be located on the same layer as the plurality of dummy electrode pattern groups 106 .
  • the plurality of second connection wires 108 and the plurality of dummy electrode pattern groups 106 are located on the same layer may mean that the plurality of second connection wires 108 and the dummy electrode patterns 1061 in the plurality of dummy electrode pattern groups 106 are positioned on the same layer .
  • the dummy electrode pattern 1061 may be a dummy anode pattern
  • the second connection trace 108 may be an anode trace.
  • the dummy electrode patterns 1061 in the dummy electrode pattern group 106 may be located in the same layer as the first electrodes a1 in the light emitting unit, and the plurality of second connection traces 108 may also be located in different layers with the plurality of dummy electrode pattern groups 106 . That is, the plurality of second connection wires 108 may not be located on the same layer as the first electrode a1.
  • the plurality of second connection traces 107 may be located in other metal layers, for example, the plurality of second connection traces 107 may be located in the second source and drain layers.
  • An insulating layer may be provided between the second source-drain metal layer and the plurality of second connection wires, and the second connection wires located in the second source-drain metal layer and the dummy electrode pattern 1061 are connected through via holes in the insulating layer. This embodiment of the present application does not limit the setting position of the dummy electrode pattern 1061 .
  • the dummy electrode pattern group 106 not only represents a dummy, but the dummy electrode pattern group 106 can also play a role of signal transmission.
  • the light emitting unit may further include: a pixel defining layer a4 located between the first electrode a1 and the light emitting layer a2.
  • the pixel defining layer a4 may have a plurality of openings a41, and each opening a41 may be used to expose the first electrode a1 of one light-emitting unit.
  • the orthographic projections of the plurality of openings a41 on the base substrate 101 do not overlap with the orthographic projections of any dummy electrode pattern 1061 on the base substrate 101 .
  • the first electrode a1 of the light emitting unit By exposing the first electrode a1 of the light emitting unit through the opening a41 of the pixel defining layer a4, the first electrode a1 of the light emitting unit can be brought into contact with the light emitting layer a2 to realize light emission. Since the orthographic projections of the openings a41 on the base substrate 101 do not overlap with the orthographic projections of any dummy electrode pattern 1061 on the base substrate 101 , the dummy electrode pattern 1061 does not emit light.
  • the light-emitting layer a2 and the cathode layer a3 are not shown in the top views provided in the embodiments of the present application, and only the opening a41 of the pixel defining layer a4 is used to distinguish the first electrode a1 and the dummy electrode pattern 1061 .
  • the pattern of the region with the opening a41 of the pixel definition layer a4 is the first electrode a1
  • the pattern of the region without the opening a41 of the pixel definition layer a4 is the dummy electrode pattern 1061 .
  • the plurality of dummy electrode patterns 1061 in the dummy electrode pattern group 106 are in one-to-one correspondence with the plurality of first light-emitting units 1021 in a first light-emitting unit group 102 , and the dummy electrode patterns 1061 correspond to the corresponding first light-emitting units 1021 .
  • the shape and area of the first electrode a1 in a light-emitting unit 1021 are the same.
  • the overlapping area of the first electrode a1 and the first connection trace 107 in the first display area 101a can be The overlapping area of the dummy electrode pattern 1061 and the first connection trace 107 is the same, so that the overlap capacitance of the first electrode a1 of the first display area 101 a and the dummy electrode pattern 1061 and the first connection trace 107 are consistent, ensuring the display panel 10 display effect.
  • the shape and area of the dummy electrode pattern 1061 and the first electrode a1 in the corresponding first light-emitting unit 1021 may also be different, which is not limited in the embodiment of the present application, and only the first electrode a1 of the first display area 101a needs to be
  • the overlapping area with the first connection trace 107 may be the same as the overlapping area of the dummy electrode pattern 1061 and the first connection trace 107 .
  • each light-emitting unit group may include: at least one light-emitting unit of a first color, at least one light-emitting unit of a second color, and At least one light-emitting unit of a third color.
  • the first color, the second color and the third color may be three primary colors.
  • the first color is red (red, R)
  • the second color is green (green, G)
  • the third color is blue (blue, B).
  • each first light-emitting unit group 102 includes: a first light-emitting unit b1 of a first color, two first light-emitting units (b21 and b22) of a second color, and a first light-emitting unit b1 of a third color The first light-emitting unit b3.
  • the two first light-emitting units (b21 and b22) of the second color may be collectively referred to as the pair of first light-emitting units of the second color b2.
  • each second light-emitting unit group 104 includes: a second light-emitting unit b1 of a first color, two second light-emitting units (b21 and b22) of a second color, and a second light-emitting unit b1 of a third color Two light-emitting units b3.
  • the two second light emitting units (b21 and b22) of the second color may be collectively referred to as the second light emitting unit pair b2 of the second color.
  • the plurality of dummy electrode patterns 1061 in each dummy electrode pattern group 106 are also in one-to-one correspondence with the plurality of second light-emitting units 1041 in a second light-emitting unit group 104 , and each dummy electrode pattern
  • the first light-emitting unit 1021 corresponding to 1061 and the corresponding second light-emitting unit 1041 have the same color.
  • the distance between the centers of the two first color first light-emitting units 1041 adjacent to each other along the row direction X in the first display area 101a is the same as the distance between the centers of the two adjacent first color first light emitting units 1041 along the row direction X in the second display area 101b.
  • the distances between the centers of the second light emitting units 1041 of one color are equal.
  • the distance between the centers of the two adjacent first light emitting units 1021 of the second color along the row direction X in the first display area 101a The distances between the centers of the two light-emitting units 1041 are equal.
  • the distance between the centers of the two first light emitting units 1021 of the third color adjacent to the row direction X in the first display area 101a The distance between the centers of the two light-emitting units 1041 .
  • the resolution of the part of the display panel 10 located in the first display area 101a may be equal to the resolution of the part located in the second display area 101b.
  • the area of the orthographic projection of the opening of the first light-emitting unit 1021 of the first color exposed in the first display area 101a on the base substrate 101 is the same as the area of the orthographic projection of the opening of the first light-emitting unit 1021 of the first color exposed in the second display area 101b.
  • the area of the orthographic projection of the opening 1041 on the base substrate 101 is equal.
  • the area of the light-emitting area of the first light-emitting unit 1021 of the first color located in the first display area 101a can be equal to the area of the light-emitting area of the second light-emitting unit 1041 of the first color located in the second display area 101b, The uniformity of the light-emitting effect of the light-emitting units of the first color in the first display area 101a and the second display area 101b is ensured.
  • the area of the orthographic projection of the opening of the first light-emitting unit 1021 of the second color exposed in the first display area 101a on the base substrate 101 is the same as that of the opening of the second light-emitting unit 1041 of the second color exposed in the second display area 101b.
  • the areas of the orthographic projections on the base substrate 101 are equal.
  • the area of the light-emitting area of the first light-emitting unit 1021 of the second color located in the first display area 101a can be equal to the area of the light-emitting area of the second light-emitting unit 1041 of the second color located in the second display area 101b, The uniformity of the light-emitting effect of the light-emitting units of the second color in the first display area 101a and the second display area 101b is ensured.
  • the area of the orthographic projection of the opening of the first light-emitting unit 1021 of the third color exposed in the first display area 101a on the base substrate 101 is the same as that of the opening of the second light-emitting unit 1041 of the third color exposed in the second display area 101b.
  • the areas of the orthographic projections on the base substrate 101 are equal.
  • the area of the light-emitting area of the first light-emitting unit 1021 of the third color located in the first display area 101a can be equal to the area of the light-emitting area of the second light-emitting unit 1041 of the third color located in the second display area 101b, The uniformity of the light-emitting effect of the light-emitting units of the third color in the first display area 101a and the second display area 101b is ensured.
  • the area of the orthographic projection of the first electrode a1 of the first light-emitting unit 1021 of the first color in the first display area 101a on the base substrate 101 is larger than that of the first electrode a1 in the second display area 101b
  • the area of the orthographic projection of the first electrode a1 of the second light emitting unit 1041 of the color on the base substrate 101 is larger than that of the second light-emitting unit 1041 of the second color in the second display area 101b.
  • the area of the orthographic projection of an electrode a1 on the base substrate 101 is larger than that of the first electrode a1 in the second display area 101b.
  • the area of the orthographic projection of the first electrode a1 of the first light-emitting unit 1021 of the third color in the first display area 101a on the base substrate 101 is larger than that of the second light-emitting unit 1041 of the third color in the second display area 101b.
  • the area of the orthographic projection of an electrode a1 on the base substrate 101 is larger than that of the second light-emitting unit 1041 of the third color in the second display area 101b.
  • FIG. 8 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • the second pattern group of the plurality of dummy electrode pattern groups 106 includes a first dummy electrode pattern 1061a, a second dummy electrode pattern 1061b, a third dummy electrode pattern 1061c and a fourth dummy electrode pattern 1061d.
  • the second type of second light-emitting unit group in the plurality of second light-emitting unit groups 104 includes a first second light-emitting unit 1041a, a second second light-emitting unit 1041b, a third second light-emitting unit 1041c, and a fourth second light-emitting unit 1041c. Two light-emitting units 1041d.
  • the first dummy electrode pattern 1061a corresponds to the first second light emitting unit 1041a
  • the second dummy electrode pattern 1061b corresponds to the second second light emitting unit 1041b
  • the third dummy electrode pattern 1061c corresponds to the third second light emitting unit 1041b.
  • the two light-emitting units 1041c correspond to each other
  • the fourth dummy electrode pattern 1061d corresponds to the fourth second light-emitting unit 1041d.
  • the first dummy electrode pattern 1061a is connected to the second second light emitting unit 1041b through the second second connecting wire 108b.
  • the second dummy electrode pattern 1061b is connected to the first second light emitting unit 1041a through the first second connecting wire 108a.
  • the third dummy electrode pattern 1061c and the fourth second light emitting unit 1041d pass through the fourth second connecting wire 108d.
  • the fourth dummy electrode pattern 1061d is connected to the third second light emitting unit 1041c through the third second connecting wire 108c. That is, each dummy electrode pattern 1061 in the second pattern group is not connected to the corresponding second light-emitting unit 1041 in the second-type second light-emitting unit group 104 .
  • each dummy electrode pattern 1061 in the second pattern group corresponds to the second type of the second light-emitting unit group 104 is connected to the second light-emitting unit 1041, which is not limited in this embodiment of the present application.
  • FIG. 9 is a partial schematic diagram of a display panel provided by an embodiment of the present application.
  • the first electrode a1 of the first light-emitting unit 1021 in the first light-emitting unit group 102 includes: a first body pattern 1021-1, and a first connection pattern 1021- connected to the first body pattern 1021-1 2.
  • the region where the first body pattern 1021-1 is located has the opening a41 of the pixel defining layer a4, so at least part of the first body pattern 1021-1 is in contact with the light emitting layer a2 of the first light emitting unit 1021, and the first connection pattern 1021-2 It can be connected to the first pixel circuit group 103 .
  • the dummy electrode pattern 1061 may include a second body pattern 1061-1, and a second connection pattern 1061-2 and a third connection pattern 1061-3 respectively connected to the second body pattern 1061-1.
  • the region where the second body pattern 1061-1 is located does not have the opening a41 of the pixel defining layer a4, so the second body pattern 1061-1 may not be in contact with the light emitting layer a2 of any first light emitting unit 1021.
  • the second connection pattern 1061-2 is connected to the second pixel circuit group 105
  • the third connection pattern 1061-3 is connected to the second light emitting unit group 104 through the first connection wire 107 or the second connection wire 108.
  • the third connection pattern 1061-3 of the dummy electrode pattern 1061 can be connected to the first type of second type through the first connection trace 107
  • the light emitting unit group 104a is connected.
  • the third connection pattern 1061-3 of the dummy electrode pattern 1061 can be connected to the second type of second light-emitting unit through the second connection trace 108 Group 104b is connected.
  • the first electrode a1 of the first light emitting unit 1021 may also include: a fourth connection pattern 1021-3 connected to the first body pattern 1021-1.
  • the first body pattern 1021-1 of the first electrode a1 may correspond to the second body pattern 1061-1 of the dummy electrode pattern 1061
  • the first connection pattern 1021-2 of the first electrode a1 may correspond to the second body pattern 1061-1 of the dummy electrode pattern 1061.
  • the two connection patterns 1061-2 correspond to each other
  • the fourth connection pattern 1021-3 of the first electrode a1 may correspond to the third connection pattern 1061-3 of the dummy electrode pattern 1061.
  • the shapes and areas of the corresponding two patterns are the same, and the overlapping areas of the corresponding two patterns and the first connection traces 107 are respectively the same.
  • the orthographic projection of the first body pattern 1021-1 of the first electrode a1 in the first light-emitting unit 1021 on the base substrate 101, the second body pattern 1061 of the dummy electrode pattern 1061 corresponding to the first light-emitting unit 1021 The shape and area of the orthographic projection of -1 on the base substrate 101 are the same.
  • the orthographic projection of the first connection pattern 1021-2 of the first electrode a1 in the first light-emitting unit 1021 on the base substrate 101, the second connection pattern 1061-2 of the dummy electrode pattern 1061 corresponding to the first light-emitting unit 1021 is in The shape and area of the orthographic projection on the base substrate 101 are the same.
  • the orthographic projection of the fourth connection pattern 1021-3 of the first electrode a1 in the first light-emitting unit 1021 on the base substrate 101, and the third connection pattern 1061-3 of the dummy electrode pattern 1061 corresponding to the first light-emitting unit 1021 is in The shape and area of the orthographic projection on the base substrate 101 are the same.
  • the dummy electrode pattern 1061 corresponding to the first light emitting unit 1021 includes the third connection pattern 1061-3 for connecting the first connection trace 107 or the second connection trace 108, in order to make the first connection trace 107 or the second connection trace 108 connected
  • the electrode a1 has the same shape and area as the dummy electrode pattern 1061, and the first electrode a1 may also include a fourth connection pattern 1021-3 having the same shape and area as the third connection pattern 1061-3.
  • the fourth connection pattern 1021 - 3 does not need to be connected to the first connection trace 107 or the second connection trace 108 .
  • the orthographic projection of the first connection pattern 1021 - 2 on the base substrate 101 is different from the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 . overlapping. Therefore, the connection between the first connection pattern 1021-2 of the first electrode a1 and the first pixel circuit group 103 can be prevented from being affected by the first connection wiring 107, and the connection with the first pixel circuit group 103 can be ensured.
  • the first light emitting units 1021 in the connected first light emitting unit group 102 emit light normally.
  • the orthographic projection of the fourth connection pattern 1021 - 3 on the base substrate 101 at least partially overlaps with the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 .
  • the orthographic projection of the second connection pattern 1061 - 2 on the base substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 .
  • the connection between the dummy electrode pattern 1061 and the second pixel circuit group 105 can be prevented from being affected by the second connection wiring 108, and the second light-emitting unit group 104 connected to the second pixel circuit group 105 can be ensured.
  • the second light-emitting unit in the light-emitting unit normally emits light.
  • the orthographic projection of the third connection pattern 1061-3 of the dummy electrode pattern 1061 on the base substrate 101 is at least the same as the orthographic projection of the plurality of first connection traces 107 on the base substrate 101. Partially overlapping.
  • the third connection patterns 1061-3 of the dummy electrode patterns 1061 need to be connected to the first connection traces 107, the third connection patterns 1061-3 on the base substrate
  • the orthographic projection on 101 must at least partially overlap with the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 .
  • each second pattern group 106b may be arranged along the row direction X with a part of the first pattern groups 106a.
  • the orthographic projections of the dummy electrode patterns 1061 in the second pattern group 106b on the base substrate 101 and the orthographic projections of the plurality of first connection traces 107 on the base substrate 101 may be the same as the overlapping area of the orthographic projection of the dummy electrode patterns 1061 in the first pattern group 106 a on the base substrate 101 and the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 .
  • the orthographic projection of the third connection pattern 1061-3 of the dummy electrode pattern 1061 on the base substrate 101 and the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 In the case of at least partial overlap, the orthographic projection of the third connection pattern 1061-3 of the dummy electrode pattern 1061 in the second pattern group 106b on the base substrate 101 and the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 The orthographic projections overlap at least partially.
  • FIG. 10 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • the display panel 10 includes two first pattern groups 106 a adjacent along the row direction X.
  • the two first pattern groups 106a each include a plurality of dummy electrode patterns 1061, and one target dummy electrode pattern c1 included in the first first pattern group 106a and another target dummy electrode pattern c1 included in the second first pattern group 106a
  • the electrode pattern c2 corresponds.
  • the colors of the first light emitting units 1021 corresponding to the two target dummy electrode patterns ( c1 and c2 ) are the same.
  • the colors of the first light-emitting units 1021 corresponding to the two target dummy electrode patterns ( c1 and c2 ) are both red as an example.
  • connection portion d of the third connection pattern 1061 - 3 in one target dummy electrode pattern c1 and the third connection pattern 1061 in the other target dummy electrode pattern c2 The connecting line between the connecting parts d of -3 intersects the row direction X.
  • the connection portion d of the third connection pattern 1061 - 3 is used to connect with the first connection trace 107 .
  • the two target dummy electrode patterns ( c1 and c2 ) need to be connected to different first connection traces 107 , and the first connection traces 107 usually extend along the row direction X, the two target dummy electrode patterns c1 In the third connection pattern 1061-3, the connection parts d used to connect the first connection traces 107 have spacing in the column direction, that is, the connection line between the two connection parts d can intersect the row direction X.
  • FIG. 11 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • the colors of the first light emitting units 1021 corresponding to the two target dummy electrode patterns ( c1 and c2 ) are both green as an example.
  • FIG. 12 is a partial schematic diagram of another display panel provided by an embodiment of the present application. Referring to FIG. 12 , in FIG. 12 , the colors of the first light emitting units 1021 corresponding to the two target dummy electrode patterns ( c1 and c2 ) are both blue as an example.
  • the base substrate 101 may further include: a third display area 101c and a peripheral area 101d located on the same side of the first display area 101a and the second display area 101b.
  • the base substrate 101 includes two first display areas 101a.
  • the first display area 101a and the second display area 101b are both rectangular in shape, the two first display areas 101a are located on both sides of the second display area 101b, and the two first display areas 101a and the second display area 101b are Row direction X arrangement.
  • the first display area 101a and the second display area 101b are located at the edges of the display areas.
  • the first display area 101a, the second display area 101b and the third display area 101c are collectively referred to as display areas.
  • the edges of the first display area 101a and the second display area 101b away from the third display area 101c are in contact with the peripheral area 101d.
  • One edge of the second display area 101b (shaped in a rectangle) extending along the row direction X is connected to the third display area 101c, and the other edge is connected to the fourth display area 101d.
  • the two edges of the second display area 101b extending along the column direction Y are respectively connected to the two first display areas 101a.
  • the length of any edge of the first display area 101a ranges from 0.1 mm to 20 mm.
  • the length of any edge of the second display area 101b ranges from 0.2 mm to 10 mm.
  • the shapes and sizes of the two first display regions 101a included in the base substrate 101 may be the same or different, which are not limited in this embodiment of the present application.
  • the display panel 10 may further include: a plurality of third light-emitting unit groups 109 and a plurality of third pixel circuit groups 110 located in the third display area 101c.
  • each third pixel circuit group 110 is connected to a third light-emitting unit group 109, and provides a driving signal for the third light-emitting unit group 109 to drive the third light-emitting unit group 109 to emit light.
  • the density of the plurality of third light-emitting unit groups 109 is greater than the density of the plurality of first light-emitting unit groups 102 , and is greater than the density of the plurality of second light-emitting unit groups 104 .
  • the density (ie pixel density) of the second light-emitting unit group 104 in the under-screen camera area (central area 101b1 of the second display area 101b) is lower than the density of the third light-emitting unit group 109 in the normal display area (third display area 101c).
  • the camera can be placed below an area of low pixel density that allows more light to pass through.
  • the density of the third light-emitting unit groups 109 is greater than the density of the first light-emitting unit groups 102 and greater than the density of the second light-emitting unit groups 104" means that the number of the third light-emitting unit groups is greater than the number of the third light-emitting unit groups under the same area.
  • the number of the two light-emitting unit groups is greater than the number of the first light-emitting unit group.
  • the third display area 101c is the main display area and has a relatively high pixel density (pixel per inch, PPI).
  • the third light-emitting unit group 109 corresponds to a third pixel circuit group 110 , and each third light-emitting unit group 109 is driven to emit light by a corresponding third pixel circuit group 110 .
  • the second display area 101b can allow light incident from the display side of the display panel to pass through the display panel and reach the back side of the display panel, so that components such as sensors located on the back side of the display panel can work normally.
  • the second display area 101b may also allow light emitted from the back side of the display panel to pass through the display panel to reach the display side of the display panel.
  • the first display area 101a and the second display area 101b also include a plurality of light-emitting unit groups for display.
  • the light-emitting unit group of the second display area 101b can be combined with the light-emitting unit that drives the light-emitting unit.
  • the groups of pixel circuits are physically separated from each other.
  • the second pixel circuit group 105 connected to the light-emitting unit group in the second display area 101b eg, the second light-emitting unit group 104 shown by the block in the second display area 101b in FIG. 1
  • the first Display area 101a can be arranged in the first Display area 101a.
  • each dot-filled box in the first display area 101a in FIG. 1 represents a pixel (a pixel includes a first light-emitting unit group 102 and a first pixel circuit group 103).
  • the pixels in the first display area 101a and the second pixel circuit group 105 connected to the second light emitting unit group 104 in the second display area 101b are arranged in an array in the first display area 101a.
  • the resolutions of the first display area 101a and the second display area 101b are lower than the resolution of the third display area 101c, that is, the pixel density of the third display area 101c is greater than that of the first display area 101a and greater than that of the third display area 101c.
  • the pixel density of the second display area 101b is lower than the resolution of the third display area 101c, that is, the pixel density of the third display area 101c is greater than that of the first display area 101a and greater than that of the third display area 101c.
  • FIG. 13 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • the connection lines e at the other ends of the plurality of first connection wires 107 may be parallel to the edge of the first display area 101a away from the second display area 101b, and the other ends of the plurality of first connection wires 107
  • the distance between the connecting line e at one end and the edge of the first display area 101 away from the second display area 101b may be smaller than the distance threshold.
  • the other end of the first connecting wire 107 may be far away from one end of the second display area 101b.
  • the first display area 101a can exist everywhere in the first display area 101a The first connection trace 107 . In this way, the overlapping capacitances in all parts of the first display area 101a can be made consistent, and the uniformity of the display effect of the first display area 101a can be ensured.
  • connection line e at the other end of the plurality of first connection wires 107 and the edge of the first display area 101a away from the second display area 101b may be substantially parallel to the column direction Y.
  • the connection lines e at the other ends of the plurality of first connection wires 107 may be collinear with the edge of the first display area 101a away from the second display area 101b.
  • each first light-emitting unit 1021 can be driven by at least two pixel circuits, thereby improving the brightness of the first light-emitting unit 1021 and ensuring the first display area 101a.
  • the display effect of 101c is consistent with the display effect of the third display area 101c.
  • the first pixel circuit group 103 includes a plurality of first pixel circuit units, each first pixel circuit unit at least includes: a first pixel circuit and a second pixel circuit, and at least two of the first pixel circuit units
  • the pixel circuit is configured to be electrically connected to the first electrode a1 of the same first light-emitting unit 1021 in the first light-emitting unit group 102 .
  • the first connection pattern 1021-2 included in the first electrode a1 of the first light emitting unit 1021 may include: a first body connection part 1021-21 extending along the target direction and a first body connection part 1021-21 located in the first body connection part 1021-21. Two first ends 1021-22 at both ends.
  • the target direction may be substantially parallel to the row direction X, and the two first end portions 1021-22 may be connected to the first pixel circuit and the second pixel circuit, respectively.
  • the extension direction of the plurality of first connection traces 107 is the row direction X
  • the extension direction (target direction) of the first main body connection portion 1021-21 in the first connection pattern 1021-2 is generally made substantially parallel In the row direction X, to ensure that the orthographic projection of the first connection pattern 1021 - 2 on the base substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 .
  • each second light-emitting unit disposed in the second display area 101b is usually small, which may result in the display brightness of the second display area 101b. It is lower than the display brightness of the third display area 101c. Therefore, in order to improve the display brightness of the second display area 101b, each second light-emitting unit can be driven by at least two pixel circuits, thereby improving the brightness of the second light-emitting unit and ensuring the display of the second display area 101b. Effect.
  • the second pixel circuit group 105 includes a plurality of second pixel circuit units, each second pixel circuit unit at least includes a third pixel circuit and a fourth pixel circuit, and at least two of the second pixel circuit units
  • the pixel circuits are configured to be connected to the same dummy electrode pattern 1061 .
  • Each dummy electrode pattern 1061 is connected to the first electrode a1 of one second light-emitting unit, thereby realizing that two pixel circuits are connected to the first electrode a1 of the same second light-emitting unit.
  • the second connection pattern 1061-2 included in the first electrode a1 of the second light emitting unit may include: a second main body connection part 1061-21 extending along the target direction and a second main body connection part 1061-21 located on both sides of the second main body connection part 1061-21.
  • the target direction may be substantially parallel to the row direction X, and the two second end portions 1061-22 may be connected to the third pixel circuit and the fourth pixel circuit, respectively.
  • the extension direction of the plurality of first connection traces 107 is the row direction X
  • the extension direction (target direction) of the second main body connection portion 1061-21 in the second connection pattern 1061-2 is generally made substantially parallel In the row direction X, to ensure that the orthographic projection of the second connection pattern 1061 - 2 on the base substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 .
  • substantially refers to an allowable error range within 15%.
  • substantially parallel may mean that the included angle between the two is between 0 degrees and 30 degrees, such as 0 degrees to 10 degrees, 0 degrees to 15 degrees, and the like.
  • the structures of the first pixel circuit unit and the second pixel circuit unit may be the same, and may both be referred to as a pixel circuit pair f.
  • the two pixel circuits included in each of the first pixel circuit unit and the second pixel circuit unit may be referred to as a first pixel circuit and a second pixel circuit. That is, for convenience of description, the third pixel circuit included in the second pixel circuit unit may be referred to as a first pixel circuit, and the fourth pixel circuit included in the second pixel unit may be referred to as a second pixel circuit.
  • FIG. 15 is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided by an embodiment of the present application.
  • the first pixel circuit group 103 includes a plurality of first pixel circuit units.
  • the second pixel circuit group 105 includes a plurality of second pixel circuit units.
  • at least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the first electrodes a1 of the same first light-emitting unit 1021 in the first light-emitting unit group 102 .
  • At least two pixel circuits in the second pixel circuit unit are configured to be electrically connected to the same dummy electrode pattern 1061 .
  • the first pixel circuit unit and the second pixel circuit unit may include two pixel circuits, and both the first pixel circuit unit and the second pixel unit may be referred to as a pixel circuit pair f.
  • the embodiment of the present application shows that the first pixel circuit unit includes two pixel circuits, but is not limited thereto, and may also include three pixel circuits or more pixel circuits.
  • the first light-emitting unit group 102 includes a plurality of first light-emitting units 1021
  • the first pixel circuit group 103 includes a plurality of pixel circuit pairs f
  • each pixel circuit pair f in the first pixel circuit group 103 is configured to
  • the first electrode a1 of the first light-emitting unit 1021 is connected to drive the first light-emitting unit 1021 to emit light.
  • the second light-emitting unit group 104 includes a plurality of second light-emitting units 1041, the second pixel circuit group 105 may include a plurality of pixel circuit pairs f, and each pixel circuit pair f in the second pixel circuit group 105 is configured to be the same as the one
  • the dummy electrode patterns 1061 are electrically connected to drive a second light emitting unit 1041 to emit light.
  • the display panel 10 further includes reset power signal lines, data lines, scan signal lines, power signal lines, reset control signal lines and light emission control signal lines on the base substrate.
  • the orthographic projection of at least part of at least one target data line located in the second display area 101b on the base substrate 101 among the plurality of data lines included in the display panel 10 is located in the second display area 101b close to the first display area 101a. area.
  • each pixel circuit (the first pixel circuit f1 and the second pixel circuit f2) includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7.
  • the first pole is connected to the first pole of the driving transistor T3, the second pole of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, and the first pole of the first reset control transistor T7 is connected to the reset power signal line to receive the reset signal Vinit, the second pole of the first reset control transistor T7 is connected to the light emitting unit, and the first pole of the data writing transistor T4 is connected to the second pole of the driving transistor T3.
  • the first pole of the data writing transistor T4 is connected to the second pole of the driving transistor T3.
  • the pixel circuit of each pixel unit further includes a storage capacitor C, a first light emission control transistor T6, a second light emission control transistor T5 and a second reset transistor T1.
  • the gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first pole of the storage capacitor C is electrically connected to the power signal line, and the second pole of the storage capacitor C is electrically connected to the gate of the drive transistor T3
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal;
  • the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset;
  • the pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, the second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive reset control signal Reset;
  • the second pole of T5 is electrically connected to the second pole of the driving transistor T3, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM.
  • the above-mentioned power signal line refers to the signal line for outputting the voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T3 is electrically connected to the first scanning signal line, and the threshold compensation transistor
  • the gate of T2 is electrically connected to the second scan signal line, and the signals transmitted by the first scan signal line and the second scan signal line may be the same or different, so that the gate of the data writing transistor T3 and the threshold compensation transistor T2 It can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the light-emitting control signals input to the first light-emitting control transistor T6 and the second light-emitting control transistor T5 may be the same, that is, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 may be electrically connected to The same signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 may also be electrically connected to different light-emitting control signal lines respectively, and the signals transmitted by different light-emitting control signal lines may be the same or different.
  • the reset control signals input to the first reset transistor T7 and the second reset transistor T1 may be the same, that is, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may be electrically connected to the same signal line.
  • the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may also be electrically connected to different reset control signal lines, respectively.
  • the signals on different reset control signal lines may be the same or different.
  • the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage, the same data signal Data passes through two connected data The writing transistor T4, the two driving transistors T3 and the two threshold compensation transistors T2 respectively connected to the two connected data writing transistors T4 are stored in the two N1 nodes of the two pixel circuits; in the third light-emitting stage, the two The second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 in each pixel circuit (ie, the pixel circuit pair f composed of the first pixel circuit f1 and/or the second pixel circuit f2) are all turned on, so that the same The data signal is transmitted to two N4 nodes.
  • the N4 nodes of the two pixel circuits are connected to jointly drive the same light-emitting unit A to emit light, which can achieve the purpose of increasing current and brightness.
  • the light-emitting unit A may be the first light-emitting unit 1021 in the first light-emitting unit group 102 in the first display area 101a, or may be the second light-emitting unit 1041 in the second light-emitting unit group 104 in the second display area 101b.
  • the pixel circuit of the pixel unit may also be a structure including other numbers of transistors.
  • a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure which is not limited in this embodiment of the present application. It is only necessary to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to jointly drive the same light-emitting unit to emit light.
  • FIG. 16 is a schematic partial planar structure diagram of an active semiconductor layer of a pixel circuit in a first display region provided by an embodiment of the present application.
  • the active semiconductor layer 01 can be formed by patterning a semiconductor material.
  • the active semiconductor layer 01 can be used to make the above-mentioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6 and first reset control transistor Active layer of T7.
  • the active semiconductor layer 01 includes the active layer pattern (channel region) and doping region pattern (source-drain doping region) of each transistor of each pixel unit, and the active layer pattern and doping region of each transistor in the same pixel circuit.
  • the miscellaneous area pattern is set as one.
  • the active layer may include an integrally formed low temperature polysilicon layer, and the source region and the drain region may be conductive by doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer 01 of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie, source and drain regions) and active Layer pattern, the active layers of different transistors are separated by doping structures.
  • the active semiconductor layer 01 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials and the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • FIG. 17 is a schematic diagram of the first conductive layer in the first display area provided by the embodiment of the present application.
  • FIG. 18 is a schematic diagram of an active semiconductor layer and a first conductive stack in the first display area provided by an embodiment of the present application.
  • the display panel includes a gate insulating layer on the side of the active semiconductor layer 01 away from the base substrate, for insulating the above-mentioned active semiconductor layer 01 from the subsequently formed first conductive layer 02 (ie, the gate metal layer).
  • FIG. 18 shows the first conductive layer 02 included in the display substrate.
  • the first conductive layer 02 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 01 .
  • the first conductive layer 02 may include the second pole CC2 of the capacitor C, a plurality of scanning signal lines g3 extending along the row direction X, a plurality of reset control signal lines g4, a plurality of light emission control signal lines g5 and a second reset transistor T1,
  • the gate of the data writing transistor T3 may be the portion where the scan signal line g3 overlaps with the active semiconductor layer 01; the gate of the first light-emitting control transistor T6 may be the light-emitting control signal line g5 The first portion overlapping with the active semiconductor layer 01 and the gate of the second light-emitting control transistor T5 may be the second portion where the light-emitting control signal line g5 overlaps the active semiconductor layer 01 .
  • the gate of the second reset transistor T1 is the first part where the reset control signal line g4 and the active semiconductor layer 01 overlap
  • the gate of the first reset control transistor T7 is the second part where the reset control signal line g4 and the active semiconductor layer 01 overlap. part.
  • the threshold compensation transistor T2 may be a thin film transistor with a double gate structure, the first gate of the threshold compensation transistor T2 may be the portion where the scanning signal line g3 and the active semiconductor layer 01 overlap, and the second gate of the threshold compensation transistor T2 It may be a portion where the protruding structure P protruding from the scan signal line g3 overlaps with the active semiconductor layer 01 .
  • the gate of the driving transistor T1 can be the second electrode CC2 of the capacitor C. As shown in FIG.
  • each dotted rectangular frame in FIG. 18 shows each portion where the first conductive layer 02 and the active semiconductor layer 01 overlap.
  • the active semiconductor layers 01 on both sides of each channel region are conductorized by processes such as ion doping as the first and second electrodes of the respective transistors.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain of the transistor can be indistinguishable in physical structure.
  • one of the electrodes in addition to the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. Therefore, all or some of the transistors in the embodiments of the present application have the first electrode. and the second pole are interchangeable as required.
  • the scanning signal line g3, the reset control signal line g4 and the light emission control signal line g5 are arranged in the column direction Y.
  • the scanning signal line g3 is located between the reset control signal line g4 and the light emission control signal line g5.
  • the second electrode CC2 of the capacitor C (ie, the gate electrode of the driving transistor T1 ) is located between the scanning signal line g3 and the light emission control signal line g5.
  • the protruding structure P protruding from the scan signal line g3 is located on the side of the scan signal line g3 away from the light emission control signal line g5.
  • a first insulating layer is formed on the above-mentioned first conductive layer 02 for insulating the above-mentioned first conductive layer 02 from the second conductive layer 03 formed subsequently.
  • FIG. 19 is a schematic partial plan structure diagram of the second conductive layer in the first display area provided by the embodiment of the present application
  • FIG. 20 is the active semiconductor layer, the first conductive layer and the first display area provided by the embodiment of the present application.
  • the second conductive layer 03 includes the first pole CC1 of the capacitor C and a plurality of reset power signal lines g1 extending along the row direction X.
  • the first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.
  • the second conductive layer 03 may be a gate metal layer.
  • the display panel 10 provided by the embodiment of the present application further includes a plurality of first connection parts h1 , the first ends of at least part of the first connection parts h1 and the first pixel circuit f1 in the first pixel circuit unit
  • the second pole of the data writing transistor T4 is connected (for example, the first end of the first connection part h1 can be directly connected to the second pole of the data writing transistor T4 of the first pixel circuit f1 in the first pixel circuit unit, It can also be electrically connected through a conductive layer transfer layer), the second end of the first connection part h1 is connected with the second pole of the data writing transistor T4 of the second pixel circuit f2 in the first pixel circuit unit to make the first pixel
  • At least two data writing transistors T4 of the circuit unit are connected to the same data line, and along the column direction, at least part of the first connection part h1 is located at the second pole of the data writing transistor T2 in the first pixel circuit f1 and the second pole
  • the second electrodes of the data writing transistors of at least two pixel circuits in the first display area 101a are connected through the first connection portion h1 to drive one light-emitting unit A to emit light, and the first display area 101a can be added.
  • the current and brightness of the light-emitting unit For example, the current and brightness of the first light-emitting unit 1021 in the first display area 101a can be increased to 1.8 to 2 times of those driven by one pixel circuit, which solves the problem of low current and brightness in the first display area 101a, and realizes the More uniform full-screen visual display effect.
  • the first end of part of the first connection part h1 is connected to the second pole of the data writing transistor T4 of the third pixel circuit in the second pixel circuit unit, and the second end of the first connection part h1 is connected to the second The second pole of the data writing transistor T4 of the fourth pixel circuit in the pixel circuit unit is connected so that at least two data writing transistors T4 of the second pixel circuit unit are connected to the same data line.
  • the first connection portion h1 is located between the second pole of the data writing transistor T2 and the first pole of the first reset control transistor T7 in the third pixel circuit.
  • the first pixel circuit unit and the second pixel circuit unit in the embodiments of the present application are collectively referred to as the pixel circuit pair f, and the two pixel circuits included in each pixel circuit unit are referred to as the first pixel circuit and the second pixel circuit.
  • the two-pixel circuit that is, the third pixel circuit in the second pixel circuit unit may be referred to as a first pixel circuit
  • the fourth pixel circuit in the second pixel circuit unit may be referred to as a second pixel circuit.
  • the first connection portion h1 is located between the second pole of the threshold compensation transistor T3 and the first pole of the first reset control transistor T7 in the first pixel circuit f1.
  • the first connection part h1 is provided on the same layer as the reset power signal line g1.
  • a second insulating layer is formed on the above-mentioned second conductive layer 03 for insulating the above-mentioned second conductive layer 03 from the source-drain metal layer 04 formed subsequently.
  • FIG. 21 is a schematic partial plane structure diagram of the source-drain metal layer in the first display area provided by the embodiment of the present application
  • FIG. 22 is the active semiconductor layer, the first conductive layer, the first conductive layer, the first display area in the first display area provided by the embodiment of the present application
  • the source-drain metal layer 04 includes a data line g2 and a power signal line g6 extending in the column direction Y.
  • the data line g2 is electrically connected to the second electrode of the data writing transistor T2 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the power signal line g6 is electrically connected to the first electrode of the second light emitting control transistor T5 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the power signal lines g6 and the data lines g2 are alternately arranged in the row direction.
  • the power signal line g6 is electrically connected to the first electrode CC1 of the capacitor C through a via hole penetrating the second insulating layer.
  • a third insulating layer may be provided on the side of the above-mentioned source-drain metal layer 04 away from the base substrate 101 to protect the above-mentioned source-drain metal layer 04 .
  • FIGS. 20 to 22 schematically illustrate some pixel circuits in the first pixel circuit group 103 and some pixel circuits in the second pixel circuit group 105 .
  • the embodiment of the present disclosure schematically shows that the first pixel circuit group 103 and the second pixel circuit group 105 each include a pixel circuit pair f, and the pixel circuit pair f includes a first pixel circuit f1 and a second pixel circuit arranged along the row direction X f2, and the second electrodes of the data writing transistors T4 of the two pixel circuits in each pixel circuit pair f are connected through the first connection part h1 to drive the same light-emitting unit to emit light.
  • the embodiment of the present application is not limited thereto.
  • only the first pixel circuit group 103 may include the above-mentioned pixel circuit pair f
  • only the second pixel circuit group 105 may include the above-mentioned pixel circuit pair f.
  • the first pixel circuit group 103 and the second pixel circuit group 105 may include eight pixel circuits arranged in two rows, ie, four pixel circuit pairs f arranged in a two-dimensional array.
  • the third pixel circuit group does not include the above-mentioned pixel circuit pair f (not shown), but only includes four pixel circuits arranged in a two-dimensional array, and two adjacent pixels in the third pixel circuit group arranged along the row direction X
  • Each circuit drives one light-emitting unit to emit light, and the two data writing transistors in the two adjacent pixel circuits are independent of each other and are respectively connected to different data lines.
  • the layout difference between the third pixel circuit group and the first pixel circuit group 103 in the embodiment of the present application mainly lies in whether the first connection part h1 is provided, and the layout of the second pole of the data writing transistor connected to the first connection part h1 location settings.
  • the display panel 10 provided by the embodiment of the present application may adopt a quarter high definition (QHD), but due to the difference between the pixel circuits designed with this resolution
  • QHD quarter high definition
  • the distance along the column direction between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor is small, eg, less than 2 microns, eg, 1.4 microns to 1.8 microns. Therefore, it is difficult to provide a first connection connecting the second electrodes (data input nodes) of the two data writing transistors of the pixel circuit pair f between the second electrodes of the threshold compensation transistors and the first electrodes of the first reset control transistors.
  • the pixel circuit with QHD resolution is designed to the pixel with FHD resolution In the pixel pitch, the distance along the column direction Y between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7 in each pixel circuit is increased, so as to ensure that the pixel circuit has a good response to f.
  • the data input nodes of the two pixel circuits are connected by punching through the first connection part h1.
  • the first display area includes a plurality of light-emitting units and a plurality of pixel circuits connected to the plurality of light-emitting units in a one-to-one correspondence.
  • the first connection part h1 is used to connect the dummy pixel circuit (the pixel circuit in the second pixel circuit group 105) and the first display area 101a.
  • the dummy pixel circuit can be effectively used on the basis of changing the overall structure of the pixel circuit as little as possible, so that the pixel circuit of the first display area 101a (and at least one of the second display area 101b) can be increased.
  • the current and brightness of the light-emitting unit achieve a more uniform full-screen visual display effect.
  • the distance along the column direction Y between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7 is 7 micrometers to 12 micrometers, so that the second pole of the threshold compensation transistor T2 and the A first connection portion h1 is provided between the first electrodes of the first reset control transistor T7.
  • each pixel circuit further includes: a second connection part h2 and a third connection part h3 provided at the same layer as the data line g2, and the second connection part h2 is configured to connect the first connection part of the threshold compensation transistor T2.
  • the diode and the gate of the driving transistor T3, the third connection part h3 is configured to connect the first electrode of the first reset control transistor T7 and the reset power supply signal line g1.
  • one end of the second connection portion h2 is electrically connected to the second electrode of the threshold compensation transistor T2 through a via hole passing through the gate insulating layer, the first insulating layer and the second insulating layer, and the other end of the second connection portion h2 is electrically connected to the second electrode of the threshold compensation transistor T2.
  • One end is electrically connected to the gate electrode of the driving transistor T3 (ie, the second electrode CC2 of the capacitor C) through a via hole penetrating through the first insulating layer and the second insulating layer.
  • One end of the third connection portion h3 is electrically connected to the reset power signal line g1 through a via hole penetrating through the second insulating layer, and the other end of the third connection portion h3 is electrically connected through the gate insulating layer, the first insulating layer and the second insulating layer
  • the via hole in is electrically connected to the first pole of the first reset control transistor T7.
  • the distance in the column direction between the edges of the second connection portion h2 and the third connection portion h3 that are close to each other is 7 ⁇ m and 12 ⁇ m so that the second connection A first connection portion h1 is provided between the portion h2 and the third connection portion h3.
  • the distance in the column direction between the edges of the second connection part h2 and the third connection part h3 that are close to each other may be 8 to 11 micrometers.
  • the first connection part h1 and the data line g2 are located in different layers, and along the third direction perpendicular to the base substrate, each of the first connection parts h1 has a connection with the data line g2 and the power signal line g6 overlap.
  • a data line 410 and a power supply signal line g6 are provided between the two data writing transistors T4 included in the pixel circuit pair f, connecting the first connection part h1 of the above two data writing transistors T4 with the data lines 410 and The power signal lines g6 are all overlapped.
  • each pixel circuit further includes a fourth connection part h4 provided on the same layer as the data line g2, and the fourth connection part h4 is configured to connect the first connection part h1 and the first connection part of the data writing transistor T4.
  • Diode there is a gap between the fourth connection part h4 of one pixel circuit (eg, the second pixel circuit f2 ) of the pixel circuit pair f and the adjacent data line g2 , and the other pixel circuit (eg, the first pixel circuit f2 ) of the pixel circuit pair f
  • the fourth connection part h4 of the pixel circuit f1) is integrated with the data line g2 to realize that the pixel circuit pair f is only connected to one data line g2.
  • the data line next to each other means that there is no other data line between the fourth connection part h4 and the data line g2.
  • the plurality of third light emitting units 110 are arranged in an array along the row direction X and the column direction Y.
  • the plurality of first pixel circuit groups 103 and the plurality of second pixel circuit groups 105 are alternately arranged, and along the column direction Y, the plurality of first pixel circuit groups 103 and the plurality of second pixel circuit groups 105 are alternately arranged, And the first pixel circuit group 103 and the second pixel circuit group 105 are connected to different data lines g2.
  • a straight line extending in the row direction X passes through the second poles of the two data writing transistors in the pixel circuit pair f, and the entirety of the first connection portion h1 extends in the row direction.
  • different pixel circuit groups are connected to different data lines, so the lengths of the first connection portions h1 in the different pixel circuit groups along the row direction X may be different.
  • the lengths of the first connection portions h1 in different pixel circuit pairs f along the row direction X may also be different.
  • the fourth connection portion h4 integrated with the data line g2 is the first sub-portion h41
  • the fourth connection portion h4 with an interval from the data line g2 is the second sub-portion h42
  • the circuit group 105 includes eight pixel circuits arranged in an array (four pixel circuits arranged in the row direction and two pixel circuits arranged in the column direction) as an example, then in the first pixel circuit group 103, the two first subsections
  • the h41 are arranged in the column direction (ie, in a row)
  • the two second sub-sections h42 are arranged in the column direction Y (ie, in a column)
  • the first sub-sections h41 and the second sub-sections h42 are arranged alternately in the row direction X.
  • the arrangement of the first sub-sections and the second sub-sections in the second pixel circuit group 105 is the same as the arrangement of the first sub-sections and the second sub-sections in the first pixel circuit group 103 .
  • the first subsection in the first pixel circuit group 103 and the second subsection in the second pixel circuit group 105 are located in different columns So that the first pixel circuit group 103 and the second pixel circuit group 105 are connected to different data lines.
  • the fourth connection parts in the adjacent two pixel circuits arranged in the row direction X or the column direction in the third light-emitting unit 110 are all integrated with the data lines. In order to realize the electrical connection between each pixel circuit and the corresponding data line.
  • the display panel 10 further includes a plurality of cover parts S disposed in the same layer as the first connection part h1, and each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2 and two gates T2-g1 and T2-g2, The active semiconductor layer 01 between the gates.
  • the covering portion S overlaps with the active semiconductor layer 01 , the data line g2 and the power signal line g6 between the two gates.
  • the active semiconductor layer 01 between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is easily affected by the surrounding line voltage and jumps, thereby affecting the threshold
  • the leakage current of the compensation transistor T2 is compensated, thereby affecting the luminous brightness.
  • the covering part S is designed to form a capacitor with the active semiconductor layer 01 between the two channels of the threshold compensation transistor T2, and the covering part S
  • the power supply signal line g6 can be connected to obtain a constant voltage, so the voltage of the active semiconductor layer 01 in the floating state can be kept stable.
  • the covering portion S overlaps with the active semiconductor layer 01 between the two-stage channels of the double-gate threshold compensation transistor T2, and can also prevent the active semiconductor layer 01 between the two gates from being illuminated to change the characteristics, such as preventing The voltage of this part of the active semiconductor layer 01 is changed to prevent crosstalk.
  • the power signal line g6 may be electrically connected to the cover part S through a via hole penetrating the second insulating layer to supply the cover part S with a constant voltage.
  • the orthographic projection of the covering portion S overlapping with the active semiconductor layer 01 on the first straight line extending along the row direction X overlaps with the orthographic projection of the first connecting portion h1 on the first straight line, and the fourth connecting portion
  • the orthographic projection of h4 on the second straight line extending along the column direction Y overlaps with the orthographic projection of the covering portion S on the second straight line.
  • the overall setting of h1 is non-linear, such as polyline.
  • the first connection portion h1 includes a main body connection portion h1 extending in the row direction X and two end portions h12 located at both ends of the main body connection portion h1 and extending in the column direction Y, two The end portions h12 are respectively connected to the two fourth connection portions h4 of the pixel circuit pair f, and the orthographic projections of the two end portions h12 on the second straight line overlap with the orthographic projection of the covering portion S on the second straight line.
  • the main body connecting portion and both end portions are formed in a zigzag shape to keep a distance from the covering portion.
  • the distance between the covering part S and the second pole of the threshold compensation transistor T2 is smaller than the distance between the covering part S and the first pole of the first reset control transistor T7, that is, the covering part S is closer Threshold compensation transistor T2.
  • the first connection part h1 is set closer to the first pole of the first reset transistor T7, that is, in the column direction Y , the distance between the main body connection part h1 and the second pole of the threshold compensation transistor T2 in the first pixel circuit f1 is greater than the distance between the main body connection part h1 and the first pole of the first reset control transistor T7 in the first pixel circuit f2 the distance.
  • FIG. 23 is a schematic diagram of the connection relationship between the first light-emitting unit group and the first pixel circuit group in the first display area provided by the embodiment of the present application.
  • FIG. 24 is a schematic diagram of a first electrode and a dummy electrode pattern provided by an embodiment of the present application.
  • 25 is a schematic diagram of stacking a first conductive layer, a second conductive layer, a source-drain metal layer, a first connection trace, a first electrode and a dummy electrode pattern in the first display area provided by an embodiment of the present application.
  • FIG. 24 is a schematic diagram of a first electrode and a dummy electrode pattern provided by an embodiment of the present application.
  • 25 is a schematic diagram of stacking a first conductive layer, a second conductive layer, a source-drain metal layer, a first connection trace, a first electrode and a dummy electrode pattern in the first display area provided by an embodiment of the present application.
  • 26 shows the stacking of the active semiconductor layer, the first conductive layer, the second conductive layer, the source-drain metal layer, the first connection trace, the first electrode and the dummy electrode pattern in the first display area provided by the embodiment of the present application Schematic.
  • 27 shows an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer, a first connection trace, a first electrode, a dummy electrode pattern, and a pixel in the first display area provided by the embodiment of the present application Schematic of the stack-up of the defined layers.
  • each light-emitting unit group includes a plurality of light-emitting units.
  • the first light-emitting unit group 102 includes a plurality of first light-emitting units 1021
  • the second light-emitting unit group 104 includes a plurality of second light-emitting units 1041 .
  • the third light-emitting unit group 109 includes a plurality of third light-emitting units 1091 . 24 to 27 , whether the pattern shown is the first electrode a1 or the dummy electrode pattern 1061 depends on whether the pixel defining layer a4 has an opening a41 here.
  • the pattern of the region of the pixel defining layer a4 having the opening a41 is the first electrode a1
  • the pattern of the region of the pixel defining layer a4 having no opening is the dummy electrode pattern 1061 .
  • each first light-emitting unit group 1021 includes a first light-emitting unit b1 of a first color, a first light-emitting unit pair b2 of a second color, and a first light-emitting unit b3 of a third color.
  • the first light-emitting unit b1 of the first color and the first light-emitting unit b3 of the third color are arranged along the column direction Y
  • the first light-emitting unit pair b2 of the second color includes two first light-emitting units of the second color arranged along the column direction Y.
  • the first light emitting unit b1 of the first color and the first light emitting unit pair b2 of the second color are arranged in the row direction.
  • the orthographic projection of the first electrode a1 of the first light-emitting unit b3 of the third color on the straight line extending in the column direction Y and the interval between the first electrodes a1 of the two first light-emitting units 1021 of the second color are on the straight line orthographic overlap.
  • the orthographic projection of the main body pattern (described later) of the first light emitting unit b3 of the third color on a straight line extending in the column direction Y is the same as the orthographic projection of the main body patterns of the two first light emitting units 1021 of the second color in the column direction Y Orthographic projections do not overlap.
  • each light-emitting unit includes a first electrode a1 , a light-emitting layer a2 and a second electrode a3 that are arranged in sequence along a direction away from the base substrate 101 .
  • the display substrate further includes a pixel defining layer a4, and the pixel defining layer a4 includes an opening a41 for defining a light-emitting region of the pixel unit, and the opening a41 exposes the first electrode a1 of the light-emitting unit A.
  • the light-emitting layer a2 of the subsequent light-emitting unit A When in the opening a41 of the pixel defining layer a4, the light-emitting layer a2 is in contact with the first electrode a1, so that this part can drive the light-emitting layer a2 to emit light to form an effective light-emitting region.
  • the "effective light-emitting area” here may refer to a two-dimensional planar area, the planar area being parallel to the base substrate. It should be noted that, due to process reasons, the size of the opening a41 of the pixel defining layer is slightly larger than that of the portion close to the base substrate, or in the direction from the side close to the base substrate to the side away from the base substrate.
  • the size of the effective light-emitting area may be slightly different from the size of the pixel defining layer opening a41 at different positions, but the overall area shape and size are basically the same.
  • the orthographic projection of the effective light-emitting region on the base substrate substantially coincides with the orthographic projection of the corresponding opening a41 of the pixel defining layer on the base substrate.
  • the orthographic projection of the effective light-emitting area on the base substrate completely falls within the orthographic projection of the opening a41 of the corresponding pixel defining layer on the base substrate, and the shapes of the two are similar.
  • the projection of the effective light-emitting area on the base substrate The area is slightly smaller than the projected area of the opening a41 of the corresponding pixel defining layer on the base substrate.
  • each pixel circuit further includes a fifth connection part h5 disposed on the same layer as the data line g2, and the first electrode a1 of the light-emitting unit A located in the second display area 101b and the third display area 101c may be It is directly electrically connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion h5.
  • the second pole of each third light-emitting unit 1091 in the third light-emitting unit group 109 may directly connect with the first The second electrode of the light emission control transistor T6 is electrically connected.
  • the second pole of each first light-emitting unit 1021 in the first light-emitting unit group 102 can directly communicate with the first light-emitting control through the fifth connection portion h5 of the corresponding pixel circuit in the first pixel circuit group 103.
  • the second pole of the transistor T6 is electrically connected.
  • the second pole of each first light emitting unit 1021 in the first light emitting unit group 102 may be connected to the fifth connection portion h5 through the first via i1 in the third insulating layer.
  • the first pixel circuit group 103 includes a plurality of pixel circuit pairs f
  • the first electrode a1 of each first light-emitting unit 1021 of the first light-emitting unit group 102 includes a first body pattern and a connection pattern ( first connection pattern and second connection pattern).
  • the shape of the main body pattern is substantially the same as the shape of the effective light emitting area of each first light emitting unit 1021, and the connection pattern (the first connection pattern 1021-2) is configured to be directly electrically connected to the fifth connection part h5 to be electrically connected to the pixel circuit pair f.
  • the second electrodes of the two first light emission control transistors T6 are electrically connected.
  • the display panel 10 further includes a plurality of first connection traces 107 located between the first electrode a1 and the film layer where the data line g2 is located, and each first connection trace 107 extends along the row direction X.
  • the second pixel circuit group 105 includes a plurality of pixel circuit pairs f
  • the first connection wire 107 is configured to connect the first electrode a1 and the fifth electrode a1 of the second light-emitting unit 1041 in the second light-emitting unit group 104a of the first type
  • the connection part h5 is such that the first electrode a1 of each second light-emitting unit 1041 of the second light-emitting unit group 104 of the first type is connected to the second light-emitting control transistor T6 of the two first light-emitting control transistors T6 of the pixel circuit pair f of the second pixel circuit group 105 . pole electrical connection.
  • the first connection wiring 107 is electrically connected to the fifth connection portion h5 in the second pixel circuit group 105 through the second via hole i21 in the third insulating layer.
  • the first electrode a1 of the second light-emitting unit 1041 is connected to the first connecting wire 107, thereby realizing the connection with the pixel circuit in the first display area 101a.
  • FIG. 28 is a schematic diagram showing the positional relationship between the first light-emitting unit group and the via hole in the first display area shown in FIG. 23 . 28, the dummy electrode pattern group 106 and the fourth connection pattern 1021-3 of the first electrode a1 of the light-emitting unit in the light-emitting unit group are not shown.
  • a first via group i1 composed of a plurality of first via holes i11 connecting a first light-emitting unit group 102 and a first pixel circuit group 103 is connected to a second light-emitting unit group 104310 and a plurality of second via holes i21 of a second pixel circuit group 105 form a second via hole group i2.
  • the plurality of first via hole groups i1 and the plurality of second via hole groups i2 are alternately arranged; along the column direction Y, the plurality of first via hole groups i1 and the plurality of second via hole groups i2 are alternately arranged.
  • the light-emitting unit of the first light-emitting unit group 102 The first electrode a1 is directly connected to the fifth connection part, and the first electrode a1 of the light-emitting unit of the second light-emitting unit group 104 is connected to the fifth connection part through the first connection trace 107, which can leave more space for transparent trace to prevent signal crosstalk.
  • FIG. 29 is a partial plan view of the first display area and the third display area in the display panel shown in FIG. 1 .
  • the third display area 101c and the first display area 101a in the display panel 10 include a plurality of pixel circuits arranged along the row direction X and the column direction Y to form a plurality of pixel circuits.
  • the plurality of pixel circuits located in the third display area 101c include a plurality of third sub-pixel circuits k3.
  • the plurality of pixel circuits located in the first display area 101a include a plurality of first sub-pixel circuits k1, and the plurality of third light-emitting units 1091 in the third display area 101c (that is, the three-color light-emitting units included in the third light-emitting unit group 109) Units, such as R, G1, G2, B shown in the figure, are connected to a plurality of third sub-pixel circuits k3 in a one-to-one correspondence, and each first light-emitting unit 1021 (ie, the first light-emitting unit group 102) of the first display area 101a
  • the three-color light-emitting units included in the figure, such as R, G1, G2, and B shown in the figure, are connected to at least two first sub-pixel circuits k1.
  • the third display area 101c and the first display area 101a are connected in the column direction Y (ie, the extending direction of the data lines).
  • the second display area 101b includes a center area 101b1 and an edge area 101b2 surrounding the center area 101b1, and the edge area 101b2 of the second display area 101b and the third display area 101c are connected in the column direction Y.
  • 1 schematically shows that the shape of the second display area 101b is a rectangle, the shape of the center area 101b1 of the second display area 101b is a circle, and the edge area 101b2 is located in the rectangle except for the center area of the circle.
  • the embodiment of the present application is not limited to this, and the shapes of the center area 101b1 and the edge area 101b2 of the second display area 101b can be set according to actual product requirements.
  • both the central area 101b1 and the edge area 101b2 of the second display area 101b are provided with second light-emitting unit groups 104, and the plurality of second light-emitting unit groups 104 located in the second display area 101b pass through the first
  • the connection wires 107 or the second connection wires 108 are respectively electrically connected to the plurality of second pixel circuit groups 105 in the first display area 101a, so as to drive the second light emitting unit group 104 to emit light.
  • the central area 101b1 of the second display area 101b is only provided with the light-emitting unit group, and the pixel circuit group is not provided so that the metal coverage area can be reduced to achieve higher light transmittance, while the edge area 101b2 of the second display area 101b is provided with light-emitting units except for A light-blocking structure is also provided outside the group so that the second display area 101b forms a light-transmitting area (ie, the central area 101b1 ) having a predetermined shape.
  • the light-blocking structure disposed in the edge region 101b2 of the second display region 101b may be a plurality of dummy pixel circuit groups 111, and the plurality of dummy pixel circuit groups 111 include the second light-emitting unit group 104 and the substrate.
  • each dummy pixel circuit group 111 is not connected to any light emitting unit group, but is only a floating pixel circuit.
  • the edge region 101b2 is a ring-shaped wiring region.
  • the data lines, scanning signal lines g3, power signal lines, reset control lines, light emission control signal lines, reset power signal lines and other lines connected to the second pixel circuit group 105 are all located in the annular line area.
  • the second light-emitting unit group 104 in the second display area 101b may be controlled in half left and right.
  • the second pixel circuit groups 105 in the first display area 101a are controlled respectively.
  • the second light-emitting unit group 104 located on the left side of the center line is controlled by the second pixel circuit group 105 in the first display area 101a located on the left side of the center line
  • the second light-emitting unit group 104 located on the right side of the center line is controlled by the second pixel circuit group 105 It is controlled by the second pixel circuit group 105 located in the first display area 101a to the right of the center line.
  • the traces for driving the light-emitting units in the circular central area 101b1 are arranged in the edge area 101b2 in a dense arrangement, so that the circular central area 101b1 serving as the under-screen display area can have as large an area as possible.
  • the third display area 101c and the first display area 101a include a plurality of pixel circuits arranged in a row direction X and a column direction Y to form a plurality of pixel circuit rows j1 and a plurality of pixel circuit columns j2.
  • the edge area 101b2 of the second display area 101b includes a plurality of dummy pixel circuits 1111 arranged in the row direction X and the column direction Y to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows.
  • the dummy pixel circuit in the second display area 101b is also referred to as a pixel circuit here.
  • the dummy pixel circuit is not connected to any light-emitting unit, its structure may be substantially the same as that of pixel circuits in other areas.
  • both include a 7T1C (ie, seven transistors and one capacitor) structure.
  • a plurality of data lines g2 extending along the column direction Y are respectively connected to a plurality of pixel circuit columns j2.
  • each pixel circuit column j2 includes a pixel circuit column group composed of four adjacent columns, and each pixel circuit column group includes a pixel circuit column along the row direction X (that is, intersecting the extending direction of the data line g2 ). direction) the first pixel circuit column j21, the second pixel circuit column j22, the third pixel circuit column j23 and the fourth pixel circuit column j24 are arranged in sequence.
  • the first pixel circuit column j21, the second pixel circuit column j22, the third pixel circuit column j23 and the fourth pixel circuit column j24 in the third display area 101c are respectively connected with the first data line g21 arranged in sequence along the row direction X, The second data line g22, the third data line g23 and the fourth data line g24 are connected.
  • At least part of the pixel circuits in the column j24 are respectively connected to the first data line g21 , the second data line g22 , the third data line g23 and the fourth data line g24 arranged in sequence along the row direction X.
  • the first display area 101a in at least one pixel circuit column group, at least one pixel circuit row j1 located in the same pixel circuit row j1 and located in the first pixel circuit column j21 and the second pixel circuit column j22
  • the data output terminals (ie, the fourth connection portion h4) of the two pixel circuits are electrically connected to form a first pixel circuit pair f1a, which are located in the same pixel circuit row j1 and located in the third pixel circuit column j23 and the fourth pixel circuit column j24.
  • each pixel circuit column group in the first display area 101a includes the first pixel circuit pair f1a and the second pixel circuit pair f2a as an example, but is not limited to this, and can be based on actual products. needs to be set.
  • the third display area 101c, the first display area 101a and the second display area 101b each include a plurality of light-emitting units A, and the plurality of light-emitting units 1091 in the third display area 101c are respectively connected to the third display area 101c.
  • a plurality of pixel circuits of the display area 101c are connected.
  • the plurality of light emitting units 1021 in the first display area 101a are respectively connected with a part of pixel circuits in the first display area 101a, and the plurality of light emitting units 1041 in the second display area 101b are respectively connected with another part of the pixel circuits in the first display area 101a.
  • the light-emitting units 20 in the first light-emitting unit group 102 are connected to the pixel circuits in the first pixel circuit group 103; the second light-emitting units in the second light-emitting unit group 104 in the second display area 101b
  • the unit 1041 is connected to the pixel circuits in the second pixel circuit group 105 in the first display area 101a.
  • the embodiment of the present application schematically shows that the first display area 101a only includes the first pixel circuit group 103 and the second pixel circuit group 105, but is not limited to this. According to factors such as space design requirements in the product, the first display area 101a also includes Other pixel circuit groups may be included, such as dummy pixel circuit groups (not connected to the light emitting unit) and the like.
  • the first pixel circuit group 103 and the second pixel circuit group 105 in the first display area 101a both include a first pixel circuit pair f1a and a second pixel circuit pair f2a, then the first pixel circuit pair f1a and the second pixel circuit pair f2a In the display area 101a and the second display area 101b, the plurality of light emitting units are respectively connected to the plurality of first pixel circuit pairs f1a and the plurality of second pixel circuit pairs f2a in the first display area 101a.
  • the light-emitting unit provided in the third display area 101c may be referred to as the third light-emitting unit 1091
  • the light-emitting unit provided in the first display area 101a may be referred to as the first light-emitting unit 1021
  • the light-emitting unit provided in the second display area 101b may be referred to as the first light-emitting unit 1021
  • the light emitting unit may be referred to as a second light emitting unit 1041 .
  • the data line g2 is connected. Therefore, some pixel circuits in the first pixel circuit column j21 located in the first display area 101a are connected to the first data line g21, for example, the pixel circuits in the first pixel circuit group 103 located in the first pixel circuit column j21 are connected to the first data line g21.
  • the first data line g21 is connected, and the pixel circuits in the second pixel circuit group 105 in the first pixel circuit column j21 are not connected with the first data line g21.
  • some pixel circuits in the second pixel circuit column j22 located in the first display area 101a are connected to the second data line g22, for example, the pixel circuits in the second pixel circuit group 105 located in the second pixel circuit column j22 It is connected to the second data line g22, and the pixel circuits in the first pixel circuit group 103 in the second pixel circuit column j22 are not connected to the second data line g22.
  • Some pixel circuits in the third pixel circuit column j23 located in the first display area 101a are connected to the third data line g23, for example, the pixel circuits in the second pixel circuit group 105 located in the third pixel circuit column j23 are connected to the third data line g23.
  • the data line g23 is connected, and the pixel circuits in the first pixel circuit group 103 in the third pixel circuit column j23 are not connected with the third data line g23.
  • Some pixel circuits in the fourth pixel circuit column j24 located in the first display area 101a are connected to the fourth data line g24, for example, the pixel circuits in the first pixel circuit group 103 located in the fourth pixel circuit column j24 are connected to the fourth data line g24.
  • the data line 422 is connected, and the pixel circuits in the second pixel circuit group 105 in the fourth pixel circuit column j24 are not connected with the fourth data line g24.
  • the plurality of first pixel circuit pairs f1a connected to the plurality of light-emitting units in the first display area 101a are connected to the first data line g21 and connected to the plurality of light-emitting units in the first display area 101a
  • the plurality of second pixel circuit pairs f2a are connected to the fourth data line g24, and the plurality of first pixel circuit pairs f1a connected to the plurality of light-emitting units of the second display area 101b are connected to the second data line g22, and the second display area 101b is connected to the second data line g22.
  • the plurality of second pixel circuit pairs f2a to which the plurality of light emitting units of the region 101b are connected are connected to the third data line g23.
  • the first pixel circuit group 103 two pixel circuits in the first pixel circuit pair f1a are connected to the first data line g21, and two pixel circuits in the second pixel circuit pair f2a are connected to the fourth data line g24.
  • the second pixel circuit group 105 two pixel circuits in the first pixel circuit pair f1a are connected to the second data line g22, and two pixel circuits in the second pixel circuit pair f2a are connected to the third data line g23.
  • the first pixel circuit pair f1a connected to the light-emitting unit b1 of the first color and the light-emitting unit b3 of the third color in the first light-emitting unit group 102 is connected to the first data line g21
  • the second pixel circuit pair f2a connected to the light-emitting unit pair b2 of the second color in the first light-emitting unit group 102 is connected to the fourth data line g24.
  • FIG. 30 is a schematic diagram of a partial pixel circuit structure at the junction of the third display area and the first display area provided by an embodiment of the present application
  • FIG. 31 is a schematic diagram of the film layer structure where the data line connection part at the position shown in FIG. 30 is located
  • FIG. 32 is a schematic diagram of 30 is a schematic diagram of the structure of the film layer where the data line is located.
  • the second data line g22, the third data line g23 and the fourth data line connected to at least one pixel circuit column group
  • the g24 is disconnected to form the first fracture m1, and the first data line g21 remains continuous without fracture.
  • the part of the second data line g22 located in the first display area 101a and the part located in the third display area 101c are not connected at the junction of the third display area 101c and the first display area 101a.
  • the part of the third data line g23 located in the first display area 101a and the part located in the third display area 101c are not connected at the junction of the third display area 101c and the first display area 101a.
  • the part of the fourth data line g24 located in the first display area 101a and the part located in the third display area 101c are not connected at the junction of the third display area 101c and the first display area 101a.
  • the part of the second data line g22 located in the third display area 101c is close to the end point m2 of the first display area 101a and is connected to the end point m3 of the fourth data line g24 located in the first display area 101a and close to the third display area 101c through the data line connection part i , the data line connecting portion i passes through the first fracture m1 of the third data line g23.
  • the first data line g21, the second data line g22, the third data line g23 and the fourth data line g24 may refer to a continuous data line, for example, the first data line g21 is a continuous data line; it may also refer to the same Column pixel circuits are connected to discontinuous data lines, such as the second data line g22, the third data line g23 and the fourth data line g24.
  • the second data line g22 connected to the third sub-pixel circuit and the second data line g22 connected to the first sub-pixel circuit are configured to transmit different signals;
  • the third data line connected to the third sub-pixel circuit The g23 and the third data line g23 connected with the first sub-pixel circuit are configured to transmit different signals;
  • the fourth data line g24 connected with the third sub-pixel circuit and the fourth data line g24 connected with the first sub-pixel circuit are configured to transmit different signals.
  • the data lines located in the same straight line in the third display area and the first display area are referred to as the second data line, the third data line or the fourth data line, they are located in different display areas.
  • the second data line (the third data line or the fourth data line) is configured to transmit different signals.
  • the embodiment of the present application schematically shows that the end point of the second data line in the third display area close to the first display area is connected to the end point of the fourth data line in the first display area close to the third display area through the data line connecting part , but not limited to this.
  • the end point of the second data line in the third display area close to the first display area can also be connected to the end point of the third data line in the first display area close to the third display area through the data line connection part.
  • the pixel circuit located in the third display area is called the third sub-pixel circuit k3
  • the pixel circuit connected to the light-emitting unit located in the first display area 101a is called the first sub-pixel circuit k1
  • the pixel circuit to which the light-emitting unit located in the second display area 101b is connected is referred to as a second sub-pixel circuit k2.
  • the plurality of light-emitting units connected to the first pixel circuit column j21 in the third display area 101c include light-emitting units of the first color and light-emitting units of the third color, which are in line with the third display
  • the plurality of light-emitting units connected to the second pixel circuit column j22 in the area 101c include pairs of light-emitting units of the second color
  • the plurality of light-emitting units connected to the third pixel circuit column j23 in the third display area 101c include light-emitting units of the first color.
  • the plurality of light-emitting units connected to the fourth pixel circuit column j24 in the third display area 101c includes the light-emitting unit pair of the second color as an example.
  • the data signal is transmitted from the source driver integrated circuit located on the side of the third display area 101c away from the first display area 101a to the pixel circuits in the third display area 101c and the first display area 101a via the data lines , the data signal transmitted to the pixel circuit connected to the light-emitting unit of one color in the first display area 101a should be the same as the data signal transmitted to the pixel circuit connected to the light-emitting unit of the same color in the third display area 101c. Therefore, when the same pixel circuit column in the third display area 101c is connected to the same data line, and the pixel circuit pair f in the first display area 101a is connected to the same data line, it is easy to cause transmission to and the third display area 101c.
  • the data signal of the pixel circuit connected to the light-emitting unit of one color has the same problem as the data signal transmitted to the pixel circuit pair f connected to the light-emitting unit pair of the second color in the first display area 101a, resulting in the third display area 101c and The data signals of the first display area 101a do not match.
  • each third light-emitting unit group 109 includes a first-color light-emitting unit b1, a second-color light-emitting unit pair b2, and a third-color light-emitting unit b3.
  • Each light emitting cell pair of the second color includes a first light emitting cell block b21 and a second light emitting cell block b22.
  • the light-emitting unit b1 of the first color and the light-emitting unit b3 of the third color are arranged along a direction parallel to the extending direction of the data line (column direction Y), and the light-emitting unit pair b2 of the second color includes a first light-emitting unit block b21 and a second light-emitting unit block b21.
  • the light-emitting unit blocks b22 are arranged along the column direction Y, the light-emitting unit b1 of the first color and the light-emitting unit pair b2 of the second color are arranged along the row direction X, and the light-emitting units of the first color in the adjacent two third light-emitting unit groups point to the first color.
  • the directions of the light-emitting units of the three colors are opposite. That is, the light-emitting units connected to the four pixel circuits in the first row of pixel circuits in the third display area 101c close to the first display area 101a and located in the pixel circuit column group are sequentially the light-emitting unit b1 of the first color, and the light-emitting unit b1 of the first color.
  • the four light-emitting units connected to the pixel circuits in the second row of pixel circuits in the above-mentioned pixel circuit column group and located in the third display area 101c and close to the first display area 101a are sequentially the light-emitting unit b3 of the third color, and the second light-emitting unit block b22 , the first color light-emitting unit b1 and the first light-emitting unit block b21.
  • the arrangement of the light-emitting units of the first color and the light-emitting units of the third color connected to the pixel circuits of the first pixel circuit column and the pixel circuits of the third pixel circuit column is different from that of the second pixel circuit column and the fourth pixel circuit column.
  • the arrangement of the first light-emitting unit block b21 and the second light-emitting unit block b22 connected to the pixel circuits of the circuit columns is different.
  • the data signals transmitted by the data lines are related to the arrangement of the light-emitting units of the corresponding color, and both the third display area and the first display area should transmit matching data signals according to the above-mentioned arrangement of the light-emitting units.
  • the plurality of light-emitting units connected to the first pixel circuit column j21 in the first display area 101a include alternately arranged light-emitting units b1 of the first color and light-emitting units b3 of the third color, and
  • the first display area 101a is close to a row of the third display area 101c and the light-emitting unit connected to the pixel circuits of the first pixel circuit column j21 is, for example, the light-emitting unit b3 of the third color.
  • the plurality of light-emitting units connected to the first pixel circuit column j21 in the third display area 101c include alternately arranged light-emitting units b1 of the first color and light-emitting units b3 of the third color, and are located in the third display area 101c close to the first display A row of the region 101a and the light-emitting units connected to the pixel circuits of the first pixel circuit column j21 are the light-emitting units b1 of the first color.
  • the pixel circuits in the row of pixel circuits in the row of pixel circuits in the third display area 101c close to the first display area 101a and connected to the first data line are connected to the light-emitting unit b1 of the first color
  • the pixel circuits in the first display area 101a close to the third A pixel circuit in a row of pixel circuits in the display area 101c and connected to the same first data line is connected to the light-emitting unit b3 of the third color, and the arrangement of the light-emitting unit matches the data signal transmitted by the first data line, then
  • the first data line can be kept connected at the junction of the third display area 101c and the first display area 101a, and does not need to be disconnected at the junction of the two display areas.
  • the plurality of light-emitting unit pairs b2 of the second color connected to the fourth pixel circuit column j24 in the first display area 101a include alternately arranged first light-emitting unit blocks b21 and second light-emitting unit blocks b22, the light-emitting unit connected to the pixel circuit located in a row of the first display area 101a close to the third display area 101c and which is the fourth pixel circuit column j24 is, for example, the second light-emitting unit block b22.
  • the plurality of light-emitting unit pairs of the second color connected to the fourth pixel circuit column j24 in the third display area 101c include alternately arranged first light-emitting unit blocks b21 and second light-emitting unit blocks b22, which are adjacent to the third display area 101c A row of the first display area 101a and the light-emitting units connected to the pixel circuits of the fourth pixel circuit column j24 are also the second light-emitting unit block b22.
  • the light-emitting units connected to the pixel circuits of a row of pixel circuits in the third display area 101c close to the first display area 101a and the fourth pixel circuit column and the pixel circuits in a row of the first display area close to the third display area 101c If the light-emitting units connected to the pixel circuits in the row and the fourth pixel circuit column are of the same light-emitting unit, the data signal of the fourth data line connected to the fourth pixel circuit column of the third display area 101c and the first display area 101a The data signals of the fourth data lines connected to the fourth pixel circuit column of 100 do not match. Therefore, the fourth data lines should be disconnected at the junction of the third display area 101c and the first display area 101a.
  • the plurality of light-emitting unit pairs b2 of the second color connected to the second pixel circuit column j22 in the third display area 101c include alternately arranged first light-emitting unit blocks b21 and second light-emitting unit blocks b22, and the light-emitting unit connected to the pixel circuit located in the row of the third display area 101c close to the first display area 101a and which is the second pixel circuit column j22 is the first light-emitting unit block b21.
  • the data signal of the fourth data line connected to the fourth pixel circuit column of the first display area 101a matches the data signal of the second data line connected to the second pixel circuit column of the third display area 101c, then The part of the second data line located in the third display area 101c and the part located in the first display area 101a are disconnected at the intersection of the two display areas, and the second data line located in the third display area 101c is connected through the data line The part is connected to the fourth data line located in the first display area 101a, so as to satisfy the unified algorithm processing of the integrated circuit (IC) in the third display area 101c and the first display area 101a.
  • IC integrated circuit
  • the second data line, the third data line and the fourth data line are disconnected at the intersection of the third display area 101c and the first display area 101a, and the second data line is connected through the data line connection part
  • the part of the line located in the third display area 101c is close to the end point of the first display area 101a and the fourth data line is located at the end point of the first display area 101a close to the third display area 101c, so that the transmission from the data line to the third display area 101c can be guaranteed.
  • the data line connecting portion i and the plurality of data lines g2 are located on different layers.
  • the data line connection portion i overlaps with the power signal line g6. Since the data line connection part needs to pass through the first fracture of the third data line and the two power signal lines to connect the end point of the second data line and the end point of the fourth data line, the data line connection part needs to be set at a different location from the data line. Floor.
  • the data line connection portion i and the reset power signal line g1 are located on the same layer to facilitate design.
  • a data line connection part i is provided between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7 in each pixel circuit.
  • the boundary between the third display area 101c and the first display area 101a refers to the first position of the first reset transistor of the pixel circuit in the row j1 of the pixel circuit in the row of pixel circuits in the row j1 of the pixel circuit adjacent to the third display area 101c and the first display area 101a.
  • the interval between the pole and the second pole of the data writing transistor is not limited to the first position of the first reset transistor of the pixel circuit in the row j1 of the pixel circuit in the row of pixel circuits in the row j1 of the pixel circuit adjacent to the third display area 101c and the first display area 101a.
  • the direction Y in the column direction between the second pole of the threshold compensation transistor T2 and the second pole of the first reset control transistor T7 The distance is 7 micrometers to 12 micrometers to set the data line connection part i between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7.
  • the distance in the column direction Y between the edges of the second connection portion h2 and the third connection portion h3 that are close to each other is 7 ⁇ m to 12 ⁇ m, so that the second connection portion h3 A data line connection portion i is provided between the h2 and the third connection portion h3.
  • the threshold value of the pixel circuit is compensated by adjusting the threshold value of the transistor.
  • the distance of the space between the diode and the first pole of the first reset control transistor, the first connection part h1 and the data line connection part can be set between the second pole of the threshold compensation transistor of the pixel circuit and the first reset control transistor A large space is reserved between the first poles to prevent interference to other signals.
  • FIG. 33 is a schematic structural diagram of a partial pixel circuit at the junction of the edge area of the third display area and the second display area according to an embodiment of the present application.
  • the plurality of dummy pixel circuit columns in the second display area 101b include dummy pixel circuit column groups composed of four adjacent columns, and each dummy pixel circuit column group includes first dummy pixel circuits arranged in sequence along the column direction Y.
  • the first dummy pixel circuit row n1, the second dummy pixel circuit row n2, the third dummy pixel circuit row n3 and the fourth dummy pixel circuit row n4 may also be referred to as the first pixel circuit row and the second pixel circuit row, respectively, The third column of pixel circuits and the fourth column of pixel circuits.
  • the pixel circuit pair f connected to the first color light emitting unit b1 and the third color light emitting unit b3 in the second light emitting unit group 104 may be a first pixel circuit pair f1a and a second pixel circuit pair f1a
  • One of the pixel circuit pair f2a, the pixel circuit pair f connected to the second color light emitting unit pair b2 in the second light emitting unit group 104 may be the other of the first pixel circuit pair f1a and the second pixel circuit pair f2a.
  • the pixel circuit pair f connected to the light-emitting unit b1 of the first color and the light-emitting unit b3 of the third color of the second light-emitting unit group 104 may be connected to one of the second data line g22 and the third data line g23,
  • the pixel circuit pair f connected to the first light emitting unit block b21 and the second light emitting unit block b22 of the second light emitting unit group 104 may be connected to the other of the second data line g22 and the third data line g23.
  • the pixel circuit pair f connected to the light-emitting unit b1 of the first color and the light-emitting unit b3 of the third color of the second light-emitting unit group 104 may be connected to the third data line g23, which is connected to the second light-emitting unit group 104.
  • a pixel circuit pair f to which a light emitting unit block b21 and a second light emitting unit block b22 are connected may be connected to the second data line g22.
  • the pixel circuits connected to the second light-emitting unit group 104 cannot be connected to the first display area 101a
  • the data lines in the third display area 101c input the matched data signals. Therefore, in the embodiment of the present application, the continuous first data line and the second data line at the junction of the edge area of the second display area and the third display area 101c are respectively connected to the first light-emitting unit block of the second light-emitting unit group 104 .
  • the pixel circuits connected to the two light-emitting unit groups 104 input matching data signals, which satisfy the unified algorithm processing of the integrated circuits in the third display area 101c and the second display area 101b.
  • the plurality of light-emitting units in the second display area 101b connected to the third pixel circuit column j23 of the first display area 101a include alternately arranged light-emitting units b1 of the first color and light-emitting units b3 of the third color, and are connected with the light-emitting units b1 of the first color and b3 of the first color.
  • the light-emitting units connected to the pixel circuits of the first row of the display area 101a away from the third display area 101c and the third pixel circuit column j23 are the third-color light-emitting units b3.
  • the plurality of light-emitting units 20 connected to the first pixel circuit column j21 in the third display area 101c include alternately arranged light-emitting units b1 of the first color and light-emitting units b3 of the third color.
  • the two display areas 101b are in a row and the data lines connected to the pixel circuits of the light-emitting units b1 of the first color are connected to the first data lines.
  • the plurality of light-emitting units in the second display area 101b connected to the second pixel circuit column j22 of the first display area 101a include alternately arranged first light-emitting unit blocks b21 and second light-emitting unit blocks b22, and are located in the first display area.
  • the light emitting units connected to the pixel circuits in the first row 101a away from the third display area 101c and the second pixel circuit column j22 are the second light emitting unit blocks b22.
  • the plurality of light-emitting units connected to the second pixel circuit column j22 in the third display area 101c include alternately arranged first light-emitting unit blocks b21 and second light-emitting unit blocks b22, and the second display area located close to the third display area 101c A row of 101b and the data lines connected to the pixel circuits of the first light-emitting unit block b21 are the second data lines. Therefore, the data signals on the first data line and the second data line in the region where the third display area 101c and the edge area 101b2 of the second display area 101b are connected are respectively connected with the third data line in the first display area 101a.
  • the data signals transmitted by the third data line and the fourth data line in the area where the third display area 101c and the edge area 101b2 of the second display area 101b are connected are the same as the first display area 101b. If the data signals on the third data line and the second data line in the area 101a do not match, then at the junction of the edge area 101b2 of the second display area 101b and the third display area 101c, the first data line and the second data line remain connected, while the third data line and the fourth data line are disconnected.
  • the display panel 10 further includes a peripheral area 101d located on the side of the second display area 101b away from the third display area 101c, and the first data line g21 located in the peripheral area 101b2 of the second display area 101b around the Passing through the center area 101b1 to be connected to one of the second data line g22 and the third data line g23 of the first display area 101a at the peripheral area 101d, the second data line g22 located at the edge area 101b2 of the second display area 101b bypasses the center
  • the area 101b1 is connected to the other of the second data line g22 and the third data line g23 of the first display area 101a at the peripheral area 101d.
  • the embodiment of the present application schematically shows that the first data line g21 located in the edge region 101b2 of the second display region 101b bypasses the central region 101b1 to be connected to the third data line of the first display region 101a in the peripheral region 101d g23, the second data line g22 located in the edge region 101b2 of the second display region 101b bypasses the central region 101b1 to be connected to the second data line g22 of the first display region 101a in the peripheral region 101d, thereby facilitating the second display region and the first display region 101d.
  • a routing of data lines in the display area is arranged.
  • FIGS. 1 to 33 another embodiment of the present application provides a display panel 10 including a third display area 101c and a first display area 101a.
  • the third display area 101c includes a plurality of third light-emitting units 1091 and a plurality of third sub-pixel circuits k3, and the plurality of third light-emitting units 1091 include a first light-emitting unit column 1091-1 and a second light-emitting unit column 1091 arranged adjacently -2, each column of light-emitting units is connected to a corresponding column of third sub-pixel circuits k3.
  • the first display area 101a includes a plurality of first light-emitting units 1021 and a plurality of first sub-pixel circuits k1, and the plurality of first light-emitting units 1021 includes a third light-emitting unit column 1021-4 and a fourth light-emitting unit column 1021 arranged adjacently -5.
  • Each column of light emitting units in the first display area 101a is connected to a column of first sub-pixel circuit pairs q1, and each column of first sub-pixel circuit pairs q1 includes two adjacent columns of first sub-pixel circuits k1.
  • the display panel 10 further includes a plurality of first sub-data lines r1, a plurality of second sub-data lines r2, a plurality of third sub-data lines r3 and a plurality of first sub-data lines r3 extending along the column direction Y Four sub-data lines r4.
  • Each of the first sub-data lines r1 is connected to each of the first light-emitting cell columns 1091-1
  • each of the second sub-data lines r2 is connected to each of the second light-emitting cell columns 1091-2
  • each of the third sub-data lines r3 is connected to each of the third light-emitting cell columns 1091-2.
  • the cell columns 1021-4 are connected
  • each fourth sub-data line r4 is connected to each fourth light-emitting cell column 1021-5.
  • the arrangement direction of the first light emitting cell column 1091-1 and the second light emitting cell column 1091-2 and the arrangement direction of the third light emitting cell column 1021-4 and the fourth light emitting cell column 1021-5 Similarly, a column of third sub-pixel circuits k3 connected to the first light-emitting unit column 1091-1 and a column of first sub-pixel circuits k1 connected to the third light-emitting unit column 1021-4 are located in the same column, and the first sub-data lines r1 and The third sub-data line r3 is a continuous data line extending along the column direction Y; two columns of first sub-pixel circuits k1 connected to the fourth light-emitting unit column 1021-5 and two columns of first sub-pixel circuits k1 connected to the second light-emitting unit column 1091-2 A column of third sub-pixel circuits k3 are located in different columns. The second sub-data line r2 and the fourth sub-data line r4 are connected by
  • the first sub-data line r1, the second sub-data line r2, the third sub-data line r3 and the fourth sub-data line r4 are the same as the first data line g21, the second data line g22, the third data line g22 and the third data line in the above embodiment.
  • the meanings of the line g23 and the fourth data line g24 are different.
  • the first sub-data line r1 here only refers to the data line connected to the pixel circuit in the third display area in the first data line g21 in the above-mentioned embodiment.
  • the two sub-data lines r2 refer to the data lines connected to the pixel circuits in the third display area in the second data line g22 in the above-mentioned embodiment
  • the third sub-data line r3 here only refers to the first data line g21 in the above-mentioned embodiment.
  • the line r2 and the fourth sub-data line r4 can ensure the matching of the data signal transmitted from the data line to the light emitting unit in the third display area 101c and the data signal transmitted from the data line to the light emitting unit in the first display area 101a.
  • one column of third sub-pixel circuits k3 connected to the second light-emitting unit column 1091-2 and another column of first sub-pixel circuits k1 connected to the third light-emitting unit column 1021-4 are located in the same column .
  • the third display area 101c further includes a fifth light emitting unit column 1091-3 and a sixth light emitting unit column 1091-4, a first light emitting unit column 1091-1, and a second light emitting unit column 1091-3 adjacent to each other.
  • the column 1091-2, the fifth light emitting cell column 1091-3 and the sixth light emitting cell column 1091-4 are repeatedly arranged in the row direction X, and the third light emitting cell column 1021-4 and the fourth light emitting cell column 1021-5 are arranged in the row direction X Alternate arrangement.
  • the display panel 10 further includes a plurality of fifth sub-data lines r5 and a plurality of sixth sub-data lines r6 extending along the column direction Y, each fifth sub-data line r5 and each fifth light-emitting The cell column 1091-3 is connected, and each sixth sub data line r6 is connected to each sixth light emitting cell column 1091-4.
  • a column of third sub-pixel circuits k3 connected to the fifth light-emitting unit column 1091-3 and a column of first sub-pixel circuits k1 connected to the fourth light-emitting unit column 1021-5 are located in the same column
  • a column of third sub-pixel circuits k3 connected to the sixth light-emitting unit column 1091-4 and another column of first sub-pixel circuits k1 connected to the fourth light-emitting unit column 1021-5 are located in the same column.
  • a space is provided between the sixth sub data line r6 or the fifth sub data line r5 and the fourth sub data line r4.
  • FIG. 29 schematically shows that the pixel circuit connected to the sixth sub-data line r6 and the pixel circuit connected to the fourth sub-data line r4 are located in the same column, so that between the sixth sub-data line r6 and the fourth sub-data line r4 An interval is set, but not limited to this.
  • an interval is set between the fourth sub-data line r4 and the fifth sub-data line r5.
  • the fifth sub-data line r5 here only refers to the data line connecting the pixel circuits in the third display area 101c in the third data line g23 in the above-mentioned embodiment
  • the sixth sub-data line r6 here refers to the fourth sub-data line r6 in the above-mentioned embodiment.
  • the data lines g24 are connected to the data lines of the pixel circuits in the third display area 101c.
  • FIG. 34 is a partial plan view of the third display area and the first display area in the display panel provided by another example of the embodiments of the present application.
  • the example shown in FIG. 34 differs from the example shown in FIG. 29 in the arrangement of pixels.
  • the pixel arrangement is a GGRB arrangement, and in the example shown in FIG. 34 , the pixel arrangement is a realRGB arrangement.
  • every six RGB light-emitting units in the third display area 101c is a repetition period.
  • the data line g2 connected to the first column of R light-emitting units in the third display area 101c and the data line g2 connected to the first column of R light-emitting units in the first display area 101a are the same continuous data line; 101c There is a space between the data line g2 connected to the second column G light-emitting unit of the first display area 101a and the data line g2 connected to the second column R light-emitting unit of the first display area 101a;
  • the data line g2 is connected to the data line g2 connected to the light-emitting units of the third column G (or the fourth column G) of the first display area 101a through the data line connecting portion i; to the light-emitting units of the third column B of the third display area 101c
  • the embodiments of the present application are not limited to the above connections, as long as one R light-emitting unit in the third display area 101c and one R light-emitting unit in the first display area 101a are connected to the same data line, and one B light-emitting unit in the third display area 101c is connected to the same data line A B light-emitting unit in the first display area 101a is connected to the same data line, and a G light-emitting unit in the third display area 101c and a G light-emitting unit in the first display area 101a are connected to the same data line.
  • the third display area 101c includes a plurality of first sub-light-emitting unit groups t1 and a plurality of second sub-light-emitting unit groups t2 arranged alternately along the row direction X and the column direction Y, the first sub-light-emitting unit groups t2
  • the cell group t1 includes light-emitting cells in a first light-emitting cell column 1091-1 and a second light-emitting cell column 1091-2
  • the second sub-light-emitting cell group t2 includes a fifth light-emitting cell column 1091-3 and a sixth light-emitting cell column 1091- 4
  • the first display area 101a includes a plurality of third sub-light-emitting unit groups t3.
  • each sub-light-emitting unit group includes a first-color light-emitting unit R, a second-color light-emitting unit pair G1 and G2, and a third-color light-emitting unit B.
  • the first-color light-emitting unit The cell R and the light-emitting cells B of the third color are arranged along the column direction Y, and the pair of light-emitting cells G1 and G2 of the second color includes two light-emitting cells of the second color arranged along the column direction Y.
  • the first-color light-emitting unit R and the second-color light-emitting unit pairs G1 and G2 are arranged along the row direction X, and the arrangement of the first-color light-emitting unit R and the third-color light-emitting unit B in the first sub-light-emitting unit group t1
  • the direction is opposite to the arrangement direction of the light-emitting units R of the first color and the light-emitting units B of the third color in the second sub-light-emitting unit group t2.
  • the relative position distribution of each light-emitting unit in the first sub-light-emitting unit group t1 is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group t3.
  • the light-emitting unit of the first color is a red light-emitting unit
  • the light-emitting unit pair of the second color is a green light-emitting unit pair
  • the light-emitting unit of the third color is a blue light-emitting unit, for example, but not limited to this.
  • the light-emitting units of the first color may be blue light-emitting units
  • the light-emitting unit pair of the second color may be a green light-emitting unit pair
  • the light-emitting units of the third color may be red light-emitting units.
  • the light-emitting unit of the first color is a green light-emitting unit
  • the light-emitting unit pair of the second color is a red light-emitting unit pair
  • the light-emitting unit of the third color is a blue light-emitting unit.
  • the first display area 101a further includes a plurality of second sub-pixel circuit pairs q2
  • the second display area 101b includes a plurality of second light-emitting units 1041
  • the plurality of second light-emitting units 1041 include adjacent
  • a seventh light emitting cell column 1041-1 and an eighth light emitting cell column 1041-2 are provided.
  • the arrangement direction of the first light emitting unit column 1091-1 and the second light emitting unit column 1091-2 is the same as the arrangement direction of the seventh light emitting unit column 1041-1 and the eighth light emitting unit column 1041-2.
  • Each column of light emitting units is connected to a column of second sub-pixel circuit pairs q2, and each column of second sub-pixel circuit pairs q2 includes two adjacent columns of second sub-pixel circuit pairs q2.
  • the display panel 10 further includes a plurality of seventh sub-data lines r7 and a plurality of eighth sub-data lines r8 extending along the column direction Y, and each seventh sub-data line r7 and each seventh light-emitting The cell columns 1041-1 are connected, and each of the eighth sub-data lines r8 is connected to each of the eighth light-emitting cell columns 1041-2.
  • the seventh sub data line r7 and the eighth sub data line r8 is disposed between the third sub data line r3 and the fourth sub data line r4.
  • the seventh sub-data line r7 here only refers to the data line connecting the pixel circuits in the first display area 101a in the second data line g22 in the above-mentioned embodiment
  • the eighth sub-data line r8 here refers to the third sub-data line r8 in the above-mentioned embodiment.
  • the data lines g23 are connected to the data lines of the pixel circuits in the first display area 101a.
  • the seventh sub-data line r7 and the eighth sub-data line r8 are both disposed between the third sub-data line r3 and the fourth sub-data line r4, and the eighth sub-data line r8 and the Spaces are provided between the five sub-data lines r5 to set the data line connection portion i.
  • the data lines of the eighth sub-data line r8 and the fifth sub-data line r5 have a break at the interval between the pixel circuit of the third display area 101c and the pixel circuit of the first display area 101a, and the data line connection part i is set at at the fracture.
  • a plurality of second sub-pixel circuit pairs q2 are configured to be connected to a plurality of fourth sub-light-emitting unit groups t4, and the relative position distribution of each light-emitting unit in each fourth sub-light-emitting unit group t4 is the same as
  • the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group t3 is the same, the first sub-pixel circuit pair q1 connected with the third sub-light-emitting unit group t3 and the second sub-pixel circuit connected with the fourth sub-light-emitting unit group t4
  • the pairs q2 are alternately arranged in the row direction X and the column direction Y.
  • the second display area 101b includes a center area 101b1 and an edge area 101b2 surrounding the center area 101b1, and the edge area 101b2 includes a plurality of dummy pixel circuits arranged along the row direction X and the column direction Y to form multiple Dummy pixel circuit columns u1 and a plurality of dummy pixel circuit rows.
  • the plurality of dummy pixel circuit columns u1 in the second display area 101b include dummy pixel circuit column groups u11 composed of four adjacent columns, and each dummy pixel circuit column group u11 includes a row direction X
  • the first dummy pixel circuit column n1, the second dummy pixel circuit column n2, the third dummy pixel circuit column n3 and the fourth dummy pixel circuit column n4 are arranged in sequence.
  • the display panel 10 further includes a first dummy data line v1, a second dummy data line v2, a third dummy data line v3 and a fourth dummy data line v4, and the first dummy data line v1 and the third dummy data line v2.
  • a dummy pixel circuit row n1 is connected
  • the second dummy data line v2 is connected to the second dummy pixel circuit row n2
  • the third dummy data line v3 is connected to the third dummy pixel circuit row n3
  • the fourth dummy data line v4 is connected to the fourth dummy pixel circuit row n2.
  • the dummy pixel circuit column n4 is connected.
  • a column of third sub-pixel circuits k3 connected to the first light-emitting unit column 1091-1 and the first dummy pixel circuit column n1 are located in the same column, and a column connected to the second light-emitting unit column 1091-2 is located in the same column.
  • a column of third sub-pixel circuits k3 and the second dummy pixel circuit column n2 are located in the same column, and a column of third sub-pixel circuits k3 connected to the fifth light-emitting unit column 1091-3 is located in the same column as the third dummy pixel circuit column n3, and A row of third sub-pixel circuits k3 connected to the sixth light-emitting unit row 1091-4 is located in the same row as the fourth dummy pixel circuit row n4.
  • the two data lines connected to the first sub-light-emitting unit group t1 and the corresponding two dummy data lines are two continuous data lines, or the two data lines connected to the second sub-light-emitting unit group t2 and the corresponding two data lines
  • the dummy data lines are two consecutive data lines.
  • the display panel 10 further includes a peripheral area 101d located on the side of the second display area 101b away from the third display area 101c and connected to the first sub-light-emitting unit group t1 or the second sub-light-emitting unit group t2
  • the two dummy data lines of 101b bypass the central region 101b1 to connect the seventh sub-data line r7 and the eighth sub-data line r8 in the peripheral region 101d, respectively.
  • the first dummy data line v1 and the first sub-data line r1 are a continuous data line
  • the second dummy data line v2 and the second sub-data line r2 are a continuous data line
  • the third dummy data line v3 A space is set between the fifth sub-data line r5 and the fourth dummy data line v4 and a space is set between the sixth sub-data line r6.
  • the first dummy data line v1 bypasses the central area 101b1 to connect the seventh sub data line r7 in the peripheral area 101d
  • the second dummy data line v2 bypasses the central area 101b1 to connect to the peripheral area 101d
  • the eighth data line r8 As shown in FIGS. 1 to 34 , the first dummy data line v1 bypasses the central area 101b1 to connect the seventh sub data line r7 in the peripheral area 101d, and the second dummy data line v2 bypasses the central area 101b1 to connect to the peripheral area 101d
  • the eighth data line r8 bypasses the central area 101b1 to connect to the peripheral area 101d
  • FIG. 35 is a schematic diagram of a first electrode of a light-emitting unit group located in a third display area provided by an embodiment of the present application.
  • FIG. 36 is a schematic diagram of a first electrode of a light-emitting unit group located at a non-edge of the first display area according to an embodiment of the present application.
  • FIG. 37 is a schematic diagram of a first electrode of a light-emitting unit group located in a second display area provided by an embodiment of the present application.
  • the first electrode a1 of each light-emitting unit includes a main body pattern a11 and a connection pattern a12.
  • each light-emitting unit group in the display area includes a plurality of light-emitting units of different colors.
  • each light-emitting unit group includes a first-color light-emitting unit b1, a second-color light-emitting unit pair b2, and a third-color light-emitting unit b3.
  • the area of the main pattern of the light emitting unit of one color located in at least one of the non-edge area of the first display area 101a and the second display area 101b is larger than that located in the third display area 101c and is the same as The area of the main pattern of the light-emitting units of the above-mentioned one color of the light-emitting units of the same color.
  • the area of the main pattern of each color light-emitting unit is related to the area of its effective light-emitting area.
  • the area of the main pattern is set to be larger than the area of the main pattern of the light-emitting unit located in the third display area and the same color as the light-emitting unit of the above-mentioned one color, which can make the non-edge area of the first display area and the second display area.
  • the area of the effective light emitting area of at least one color light emitting unit is larger than the area of the effective light emitting area of the light emitting unit located in the third display area and having the same color as the one color light emitting unit.
  • the first display area 101a and the second display area 101b are divided into The area of the main pattern in at least one of the light-emitting units is designed to be larger than the area of the main pattern in the light-emitting unit of the third display area, so that the area of the main pattern in at least one of the non-edge area of the first display area and the second display area can be made.
  • the area of the effective light-emitting area of the one-color light-emitting unit is larger than the area of the effective light-emitting area of the light-emitting unit located in the third display area and having the same color as the one-color light-emitting unit. Therefore, the brightness of at least one of the first display area and the second display area can be increased on the basis of ensuring the life of the luminescent material of the light-emitting unit, and a more uniform full-screen visual display effect can be achieved.
  • the embodiment of the present application schematically shows that in the non-edge area of the first display area 101a and the second display area 101b, the area of the main pattern of the light-emitting unit of one color is larger than that located in the third display area 101c and is the same as the above-mentioned one
  • the area of the main pattern of the light-emitting unit of the same color is designed so that the area of the effective light-emitting area of one color light-emitting unit located in the non-edge area of the first display area and the second display area is larger than that of the light-emitting unit located in the third display area.
  • the brightness of the first display area and the second display area can be increased on the basis of ensuring the life of the light-emitting unit light-emitting material, so as to achieve a more uniform full-screen visual display.
  • each light-emitting unit in the third display area 101c, the first display area 101a and the second display area 101b is connected to one pixel circuit, that is, the first display area and the second display area
  • Each light-emitting unit in the area may not be connected with the pair of pixel circuits f, but only with one pixel circuit.
  • the densities of the light-emitting unit groups in the first display area 101a and the second display area 101b are both smaller than the density of the light-emitting unit groups in the third display area.
  • the area of the main pattern in the light-emitting unit is set to be larger than the area of the main pattern in the light-emitting unit of the third display area 101c so as to be located in at least one of the non-edge area of the first display area 101a and the second display area 101b
  • the area of the effective light-emitting area of the color light-emitting unit is designed to be larger than the area of the effective light-emitting area of the light-emitting unit located in the third display area 101c and having the same color as the above-mentioned one color light-emitting unit, so as to make the display effect of each display area as uniform as possible.
  • each pixel circuit group includes a plurality of pixel circuits
  • at least one of the first pixel circuit group 103 and the second pixel circuit group 105 in the first display area includes a plurality of pixel circuits
  • the two pixel circuits included in each pixel circuit pair f are configured to be electrically connected to the first electrode a1 of the same light-emitting unit.
  • the first pixel circuit group 103 and the second pixel circuit group 105 in the first display area 101a each include a plurality of pixel circuit pairs f, and each pixel circuit pair f in the first pixel circuit group 103 and the first light-emitting unit group Each light-emitting unit in 102 is connected, and each pixel circuit pair f in the second pixel circuit group 105 is connected with each light-emitting unit in the second light-emitting unit group 104 .
  • the densities of the light-emitting unit groups in the first display area 101a and the second display area 101b are both smaller than the density of the light-emitting unit groups in the third display area 101c, and the pixels to be connected with the light-emitting units in the first display area 101a and the second display area 101b
  • the circuit design is a combination of the scheme of pixel circuit pair f and the scheme of setting the area of the main pattern in the light-emitting units of the first display area 101a and the second display area 101b to be larger than the area of the main pattern in the light-emitting unit of the third display area 101c , on the basis of ensuring the life of the light-emitting material of the light-emitting unit, the current and brightness of the light-emitting units in the first display area 101a and the second display area 101b can be increased to 1.8 to 2 times that in the case of one pixel circuit driving, which solves the problem. Since the current and brightness in the first display area 101a and the second display area 101b are
  • each light-emitting unit group includes a light-emitting unit b1 of a first color, and each light-emitting unit b1 of the first color located in at least one of the non-edge area of the first display area 101a and the second display area 101b emits light of the first color.
  • the area ratio of the main pattern b1-a11 of the unit to the area of the main pattern b1-a11 of each light emitting unit of the first color located in the third display area 101c is 1.5 to 2.5.
  • each light-emitting unit group includes a first-color light-emitting unit b1, and main body patterns b1-a11 of each first-color light-emitting unit located in at least one of the non-edge area of the first display area 101a and the second display area 101b
  • the ratio of the area of ? to the main pattern b1-a11 of each light-emitting unit of the first color located in the third display area 101c is 1.9 to 2.1.
  • the area of the effective light-emitting area of each first-color light-emitting unit b1 located in at least one of the non-edge area of the first display area 101a and the second display area 101b is the same as the area of each of the first-color light-emitting units b1 located in the third display area 101c.
  • the area ratio of the effective light-emitting region of the light-emitting unit b1 of one color is 2.
  • the main pattern b1 - a11 of the first electrode a1 of the light emitting unit b1 of the first color located in each display area and the shape of the effective light emitting area are both hexagonal.
  • the main body patterns of the light-emitting units of the first color in each display area (for example, the first main pattern 1021-1 in FIG. 9 ) have the shapes of the effective light-emitting regions, and the second main pattern 1061 of the dummy electrode pattern 1062 -1 are all oval.
  • the embodiment of the present application does not limit the shape of the main pattern of the first electrode a1 of the light-emitting unit of the first color in each display area.
  • connection patterns b1-a12 of the light-emitting units of the first color located at the non-edge of the first display area 101a may be larger than the area of the connection patterns b1-a12 of the light-emitting units of the first color located in the third display area 101c by more than Realize the connection to the pixel circuit pair f.
  • the area of the main pattern b2-a11 of each light-emitting unit pair of the second color located in at least one of the non-edge area of the first display area 101a and the second display area 101b is the same as the area of the main pattern b2-a11 located in the third display area 101c.
  • the area ratio of the main body patterns b2 - a11 of the light emitting unit pairs of each second color is 1.5 to 2.5.
  • the area of the main body patterns b2-a11 of the light-emitting unit pairs of the second color located in at least one of the non-edge area of the first display area 101a and the second display area 101b is the same as the area of each second color light-emitting unit pair located in the third display area 101c.
  • the area ratio of the body patterns b2-a11 of the two-color light-emitting unit pair is 1.9 to 2.1.
  • the area of the effective light-emitting area of the light-emitting unit pair b2 located in the non-edge area of the first display area 101a and the light-emitting unit of each second color in the second display area 101b and the light-emitting area of each second color in the third display area 101c The area ratio of the effective light-emitting region of the cell pair b2 is 2.
  • the area of the main body patterns b21-a11 of each first light-emitting unit block located in at least one of the non-edge area of the first display area 101a and the second display area 101b is the same as the area of each first light-emitting unit block located in the third display area 101c.
  • the area ratio of the body patterns b21-a11 of a light emitting unit block is 1.5 to 2.5.
  • the area of the main body patterns b22-a11 of each second light emitting unit block located in at least one of the non-edge area of the first display area 101a and the second display area 101b and the area of each second light emitting unit block located in the third display area 101c The area ratio of the body patterns b22-a11 of the unit block is 1.5 to 2.5.
  • the area of the main body patterns b21-a11 of each first light emitting unit block located in at least one of the non-edge area of the first display area 101a and the second display area 101b and the area of each first light emitting unit block located in the third display area 101c The area ratio of the body patterns b21-a11 of the unit block is 1.9 to 2.1.
  • the area ratio of the body patterns b22-a11 of the unit block is 1.9 to 2.1.
  • the area of the connection patterns b21-a12 of the first light-emitting unit blocks located in the non-edge region of the first display area 101a is larger than the area of the connection patterns b21-a12 of the first light-emitting unit blocks located in the third display area 101c. area.
  • the area of the connection patterns 2b22-a12 of the second light-emitting unit blocks located in the non-edge region of the first display area 101a is larger than the area of the connection patterns 2b22-a12 of the second light-emitting unit blocks located in the third display area 101c to facilitate the connection with The pixel circuit pair f is connected.
  • the area of the main body patterns b3-a11 of the light-emitting units of each third color located in at least one of the non-edge area of the first display area 101a and the second display area 101b is the same as the area of each of the third color light-emitting units located in the third display area 101c.
  • the area ratio of the body patterns b3-a11 of the light emitting unit is 1.5 to 2.5.
  • the area of the main body patterns b3-a11 of the light-emitting units of each third color located in at least one of the non-edge area of the first display area 101a and the second display area 101b is the same as the area of each of the third color light-emitting units located in the third display area 101c
  • the area ratio of the main body patterns b3-a11 of the color light emitting cells is 1.9 to 2.1.
  • the area of the body patterns b3-a11 of the light-emitting units of the third color located in the non-edge area of the first display area 101a and the light-emitting units of the third color in the second display area 101b is the same as the area of the light-emitting units of the third color located in the third display area 101c.
  • the area ratio of the main body patterns b3-a11 was 2.
  • the area of the effective light-emitting area of each light-emitting unit b3 of the third color located in the non-edge area of the first display area 101a and the light-emitting unit b3 of each third color located in the third display area 101c The area ratio of the effective light-emitting region was 2.
  • connection patterns b3-a12 of the light-emitting units of the third color located in the non-edge area of the first display area 101a is larger than the area of the connection patterns b3-a12 of the light-emitting units of the third color located in the third display area 101c area to enable connection to the pixel circuit pair f.
  • the main pattern of the light-emitting unit of the third color in each display area and the shape of the effective light-emitting area are both hexagonal.
  • the main pattern and the shape of the effective light-emitting area of the light-emitting units of the third color located in each display area are both elliptical.
  • the embodiment of the present application does not limit the shape of the main pattern of the first electrode a1 of the light-emitting unit of the third color in each display area.
  • the main pattern of the first electrode in the light-emitting unit is referred to as the main pattern of the light-emitting unit
  • the connection pattern of the first electrode in the light-emitting unit is referred to as the connection pattern of the light-emitting unit.
  • the first electrode a1 of the light-emitting unit of the light-emitting unit group of the first display area 101a is directly connected to the pixel circuit pair f, and the area of the connection pattern of the light-emitting unit of the first display area 101a is larger , and the first electrode a1 of the light-emitting unit of the light-emitting unit group of the second display area is connected to the pixel circuit pair f of the first display area through the first connection line or the second connection line, then the light-emitting unit of the second display area
  • the area of the connection pattern can be set smaller.
  • FIG. 38 is a schematic diagram of a first electrode of each light-emitting unit in a two-row light-emitting unit group of a first display area bordering a third display area according to an embodiment of the present application.
  • the shapes of the main body patterns b1-a11 of the light-emitting units of each first color in the light-emitting unit group of a row adjacent to the third display area 101c in the column direction Y of the first display area 101a and the third display area 101c The shape and area are substantially the same as the shape and area of b1-a11 of the main body pattern of each light-emitting unit of the first color located in the third display area 101c.
  • the shapes and areas of the main patterns of the first color light emitting units in the two rows of light emitting unit groups in the first display area and the third display area adjacent to each other in the column direction Y are set to be substantially the same. That is, the area of the main pattern of the light-emitting unit of the first color located at the edge of the first display area is designed to be different from the area of the main pattern of the light-emitting unit of the first color located in the non-edge area of the first display area.
  • the brightness of most of the light-emitting units of the first color is increased to achieve a uniform full-screen display effect, and at the same time, the main patterns of the two rows of light-emitting units are prevented from conflicting in space.
  • the area of the main pattern b2-a11 of each light-emitting unit pair of the second color in a row of light-emitting unit groups adjacent to the third display area 101c in the row direction X of the first display area 101a is the same as the area of the main pattern b2-a11 located at the third
  • the area ratio of the main body patterns b2 - a11 of the light-emitting unit pairs of the second colors in the display area 101c is 0.9 to 1.1.
  • the areas of the main patterns of the light-emitting units of each second color in the two-row light-emitting unit groups of the first display area and the third display area adjacent to each other in the column direction Y are set to be approximately the same, that is
  • the area of the main pattern of the light-emitting unit of the second color at the edge of the first display area is designed to be different from the area of the main pattern of the light-emitting unit of the second color located in the non-edge area of the first display area.
  • the brightness of some of the light-emitting units of the second color is increased to achieve a uniform full-screen display effect, and at the same time, the main patterns of the two rows of light-emitting units are prevented from colliding in space.
  • the shapes of the body patterns of the two second-color light-emitting units included in the second-color light-emitting unit pair b2 in the third display area 101c are the same as those in the first display area 101a and the third In the display area 101c in the row direction X, the shapes of the two main patterns of the light-emitting unit pairs b2 of each second color of the light-emitting unit groups of one row adjacent to each other are different.
  • the size of the gap (PDL gap) of the pixel defining layer between two adjacent light-emitting units located in the non-edge area of the first display area is the same as the size of the gap between the two adjacent light-emitting units located in the edge area of the first display area.
  • the size of the PDL gap between the light-emitting units is approximately the same, so that the first display area displays the uniformity of image light.
  • the shapes of the main patterns of the two second color pixel units included in the second color pixel unit pair b2 in the third display area 101c are both pentagons.
  • the shapes of the main body patterns of the two second-color pixel units included in the second-color pixel unit pair b2 in the third display area 101c are both oval.
  • the embodiment of the present application does not limit the shape of the main pattern of the first electrode a1 of the second color pixel unit.
  • each pentagon includes a A first side 1 extending in the row direction X, two second sides 2 extending in the column direction Y and two third sides 3 connected with the two second sides 2, the two third sides 3 intersect to form a sharp corner .
  • the two sharp corners of the main body patterns of the two second color light emitting units are close to each other.
  • Each main pattern 2021 of each second-color light-emitting unit pair b2 of a row of light-emitting unit groups adjacent to the third display area 101c in the column direction Y of the first display area 101a and the third display area 101c includes a fourth side extending along the row direction X 4.
  • the two seventh sides 7 of the main pattern of pixels are close to each other.
  • the length of the second side 2 of the main pattern of the light-emitting unit of the second color in the third display area 101c is smaller than the length of the main pattern of the light-emitting unit of the second color at the edge of the first display area 101a.
  • the length of the five sides 5 ensures that the area of the main pattern of the second color light emitting unit in the third display area 101c is approximately equal to the area of the main pattern of the second color light emitting unit at the edge of the first display area.
  • the area of the main body pattern of the light emitting cells of the second color at the edge of the first display area 101 a is set to be the same as the area of the main pattern of the light emitting cells of the second color of the third display area 101 c
  • the area is the same, in order to ensure the PDL gap between the light-emitting unit of the second color and the light-emitting unit of the first color (or the light-emitting unit of the third color) at the edge of the first display area 101a, and the non-edge area of the first display area 101a
  • the PDL gap between the light-emitting unit of the second color and the light-emitting unit of the first color (or the light-emitting unit of the third color) is consistent, and the first display area 101a is adjacent to the third display area 101c in the row direction X.
  • the center line connecting the two main patterns of each second-color light-emitting unit pair in a row of light-emitting unit groups is not parallel to the
  • the area of the main pattern of the light-emitting unit of the second color at the edge of the first display area 101a is set to be the same as the area of the main pattern of the light-emitting unit of the second color of the third display area 101c, in order to ensure the first display area 101a
  • the PDL gaps between the light-emitting units (or light-emitting units of the third color) are consistent, then if the shape of the main body pattern of the light-emitting units of the second color located at the edge of the first display area 101a is a pentagon including sharp corners, it will be There is a spatial conflict with the connection pattern of the light emitting unit of the first color (or the light
  • the shape of the main body pattern of the light emitting unit of the second color at the edge of the first display area no longer includes sharp corners.
  • the shape of the main body pattern of the light-emitting unit of the second color is compensated, that is, two sixth sides 6 and a seventh side 7 connecting the two sixth sides 6 are added, so as to ensure the light emission of the second color at the edge of the first display area. Under the condition that the main pattern of the unit does not conflict in space, the area of the unit is equal to that of the light-emitting unit of the second color in the third display area.
  • the main body patterns b3-a11 of the light-emitting units of each third color in a row of light-emitting unit groups adjacent to the third display area 101c The shape and area are substantially the same as those of the main body patterns b3 - a11 of the light emitting units of each third color located in the third display area 101 c .
  • the shapes and areas of the main patterns of the light-emitting units of each third color in the two-row light-emitting unit groups of the first display area and the third display area adjacent to each other in the column direction Y are set to be substantially the same as each other.
  • the area of the main pattern of the light-emitting unit of the third color located at the edge of the first display area and the area of the main pattern of the light-emitting unit of the third color located in the non-edge area of the first display area are designed to be different.
  • the brightness of most of the light-emitting units of the third color in the display area is increased to achieve a uniform full-screen display effect, and at the same time, the main patterns of the two rows of light-emitting units are prevented from conflicting in space.
  • the light-emitting unit pair b2 of the second color is located in the light-emitting unit b1 of the first color and the light-emitting unit b2 of the first color.
  • the three-color light-emitting unit b3 is close to the side of the third display area 101c.
  • the areas and shapes of the main body patterns b2-a11 of the light-emitting unit pair of the second color are substantially the same.
  • the shape and area of the main pattern of each light-emitting unit pair of the second color in the two-column light-emitting unit groups adjacent to each other in the row direction X in the first display area and the third display area are set to be approximately the same as each other.
  • the same, that is, the area of the main pattern of the light-emitting unit pair of the second color located at the edge of the first display area and the area of the main pattern of the light-emitting unit pair of the second color located in the non-edge area of the first display area are designed to be different. While increasing the brightness of most of the light-emitting unit pairs of the second color in the first display area to achieve a uniform full-screen display effect, spatial conflicts between the main patterns of the two columns of light-emitting units are prevented.
  • a second pixel circuit group 105 is arranged between two adjacent first light-emitting unit groups 102 arranged in the column direction Y, so that the No light-emitting unit group is provided at the intervals.
  • a space is provided between two adjacent third light-emitting unit groups in a column of a plurality of third light-emitting unit groups close to the first display area 101a in the row direction X, and the spaced area includes a space that is not connected to the light-emitting unit group.
  • a third pixel circuit group is connected.
  • the third pixel circuit group and the light-emitting unit group in the first light-emitting unit group 102 in a column adjacent to the third display area 101c are located on the same straight line, so that the third pixel circuit group in the row direction X can be balanced.
  • the luminance distribution of the display area and the first display area are located on the same straight line, so that the third pixel circuit group in the row direction X can be balanced.
  • the area of the main pattern b1-a11 of each light-emitting unit of the first color is the same as that in the third display area.
  • the area ratio of the body patterns b1 - a11 of the light emitting cells of each first color of the region 101c is 1.5 to 2.5.
  • the area of the effective light-emitting area of each light-emitting unit b1 of the first color is the same as the area of the light-emitting unit located in the third display area 101c.
  • the area ratio of the effective light-emitting area of each light-emitting unit b1 of the first color is 2.
  • the main patterns of the light-emitting units in a column of light-emitting unit groups adjacent to the third display area in the row direction X in the first display area do not conflict in space
  • the shape and area of the main pattern of the light-emitting unit of the first color at the edge of a display area are approximately the same as the shape and area of the main pattern of the light-emitting unit of the first color located in the non-edge area of the first display area.
  • the brightness of most of the light-emitting units of the first color in the display area is increased to achieve a uniform full-screen display effect, and at the same time, the main patterns of the two columns of light-emitting units are prevented from conflicting in space.
  • the area of the main pattern b3-a11 of each light-emitting unit of the third color is the same as that in the third display area.
  • the area ratio of the body patterns b3 - a11 of the light emitting cells of each third color of the region 101 c is 1.5 to 2.5.
  • the area of the main pattern b3-a11 of each light-emitting unit of the third color is the same as that in the third display area 101c.
  • the area ratio of the main body patterns b3-a11 of the light-emitting units of the third colors is 1.9 to 2.1.
  • the area of the effective light-emitting area of each light-emitting unit b3 of the third color is the same as that located in the third display area.
  • the area ratio of the effective light-emitting regions of the light-emitting units b3 of the third colors of 101c is 2.
  • the shape and area of the main pattern of the light-emitting unit of the third color at the edge of a display area are approximately the same as the shape and area of the main pattern of the light-emitting unit of the third color located in the non-edge area of the first display area.
  • the brightness of most of the third-color light-emitting units in the display area is increased to achieve a uniform full-screen display effect, while preventing spatial conflicts between the main patterns of the two columns of light-emitting units.
  • FIG. 40 is a cross-sectional view in the direction A1 to A2 of FIG. 3 .
  • FIG. 41 is a cross-sectional view along the direction B1 to B2 of FIG. 7 .
  • the display panel 10 may include a fourth insulating layer and a fifth insulating layer.
  • the fourth insulating layer is located on one side of the pixel circuit film layer
  • the plurality of first connecting lines 107 are located on the side of the fourth insulating layer away from the pixel circuit film layer
  • the fifth insulating layer is located on the side away from the plurality of first connecting lines 107 one side of the fourth insulating layer.
  • the first electrode a1 of each light emitting unit is located on the side of the fifth insulating layer away from the plurality of first connecting wires 107 , and the pixel defining layer a4 is located at the side of the first electrode a1 away from the fifth insulating layer.
  • the above-mentioned pixel circuit film layer is the film layer included in the pixel circuit.
  • the pixel circuit film layer includes the active semiconductor layer 01 stacked in sequence along the side away from the base substrate 101 , The gate insulating layer, the first conductive layer 02, the first insulating layer, the second conductive layer 03, the second insulating layer, the source-drain metal layer 04 and the third insulating layer.
  • the third and fifth squares from left to right of the first conductive layer 02 in FIG. 41 are the second poles CC2 of the capacitor C, and the fourth square is the light-emitting control signal line.
  • the second and fifth squares from left to right of the second conductive layer 03 are blocking blocks, and the third and fourth squares are the first pole CC1 of the capacitor C.
  • the twenty-one blocks and the twenty-fourth block are signal lines for outputting the voltage signal VDD.
  • the fifth block, the eighth block, the eleventh block, the fourteenth block, the seventeenth block, the twentieth block, the twenty-second block from left to right of the source-drain metal layer 04 , and the twenty-fifth block is the data signal Data.
  • the second and sixth squares from left to right of the first conductive layer 02 in FIG. 42 are the light-emitting control signal lines, the third square is the reset control signal line, and the fifth square is the second pole CC2 of the capacitor C .
  • the second block from left to right of the second conductive layer 03 is a blocking block, the third block is a connection block, the fourth block is the reset signal Vinit, and the fifth block is the first pole CC1 of the capacitor C.
  • the third block, the sixth block, the eleventh block, and the fourteenth block of the source-drain metal layer 04 from left to right are the data signals Data.
  • the fourth block, the seventh block, the tenth block, and the thirteenth block from the left to the right of the source-drain metal layer 04 are the signal lines for outputting the voltage signal VDD.
  • the embodiments of the present application provide a display panel, in which the plurality of second pixel circuit groups located in the first display area include the first type of second pixel circuit groups far away from the second display area, and A second type of second pixel circuit group close to the second display area.
  • the first type of second pixel circuit group is connected to the first type of second light-emitting unit group located in the second display area and far away from the first display area through the first connecting line, and the second type of second pixel circuit group is connected through the second
  • the connection wires are connected to the second type of second light-emitting unit group located in the second display area and close to the first display area.
  • the solution provided by the embodiment of the present application can also provide a driving signal for the second type of second light-emitting unit group through the second connection wire located on a different layer from the first connection wire, it can be used without adding the first connection wire.
  • the number of the second light-emitting unit groups that can be arranged in the second display area is increased, thereby ensuring the display effect of the second display area in the display panel.
  • FIG. 42 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device may include: a power supply assembly 20 and the display panel 10 provided in the above-mentioned embodiments.
  • the power supply assembly 20 can be used to supply power to the display panel 10 .
  • the display device may be a curved display device.
  • the display device can be an organic light-emitting diode (organic light-emitting diode, OLED) display panel, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame or navigator and any other device with display function. And products or parts with fingerprint recognition function.
  • OLED organic light-emitting diode

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Abstract

本申请公开了一种显示面板及显示装置，涉及显示技术领域。该显示面板中位于第一显示区的多个第二像素电路组包括远离第二显示区的第一类第二像素电路组以及靠近该第二显示区的第二类第二像素电路组。该第一类第二像素电路组通过第一连接走线与位于第二显示区且远离第一显示区的第一类第二发光单元组连接，第二类第二像素电路组通过第二连接走线与位于第二显示区且靠近第一显示区的第二类第二发光单元组连接。由于本申请的方案可以通过与第一连接走线位于异层的第二连接走线为第二类第二发光单元组提供驱动信号，因此可以在不增加第一连接走线的前提下，增加第二显示区所能够设置的第二发光单元组的数量，保证显示面板中第二显示区的显示效果。

Description

显示面板及显示装置
本申请要求于2020年11月27日提交的申请号为202011356201.7、发明名称为“显示基板以及显示装置”的专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
有机发光二极管(organic light-emitting diode，OLED)显示面板由于具有自发光，驱动电压低，以及响应速度块等优点而得到了广泛的应用。该OLED显示面板包括多个像素单元，每个像素单元包括发光单元以及与该发光单元连接的像素电路。
发明内容
本申请提供了一种显示面板及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有相邻的第一显示区和第二显示区；
多个第一发光单元组，所述多个第一发光单元组位于所述第一显示区；
多个第一像素电路组，所述多个第一像素电路组位于所述第一显示区，所述第一像素电路组与一个所述第一发光单元组连接；
多个第二发光单元组，所述多个第二发光单元组位于所述第二显示区，所述多个第二发光单元组包括：至少一个第一类第二发光单元组和至少一个第二类第二发光单元组，所述至少一个第二类第二发光单元组相对于所述至少一个第一类第二发光单元组靠近所述第一显示区；
多个第二像素电路组，所述多个第二像素电路组位于所述第一显示区，所述多个像素电路组包括：至少一个第一类第二像素电路组和至少一个第二类第二像素电路组，所述至少一个第二类第二像素电路组相对于所述至少一个第一类第二像素电路组靠近所述第二显示区；
多个虚设电极图案组，位于所述第一显示区，所述多个虚设电极图案组包括：至少一个第一图案组和至少一个第二图案组，所述至少一个第二图案组相对于所述至少一个第一图案组靠近所述第二显示区；
多个第一连接走线，所述多个第一连接走线与所述多个虚设电极图案组位于异层，所述第一连接走线的一端与一个所述第一类第二发光单元组连接，另一端通过一个所述第一图案组与一个所述第一类第二像素电路组连接；
以及，多个第二连接走线，所述多个第二连接走线与所述多个第一连接走线位于异层，所述第二连接走线的一端与一个所述第二类第二发光单元组连接，另一端通过一个所述第二图案组与一个所述第二类第二像素电路组连接。
可选的，所述虚设电极图案组在所述衬底基板上的正投影，与至少一个所述第二像素电路组在所述衬底基板上的正投影至少部分重叠，且所述虚设电极图案组在所述衬底基板上的正投影与任一所述第一发光单元组在所述衬底基板上的正投影不重叠。
可选的，每个所述第一发光单元组和每个所述第二发光单元组均包括多个发光单元，所述发光单元包括沿远离所述衬底基板的方向依次层叠的第一电极，发光层以及第二电极；
所述虚设电极图案组包括多个虚设电极图案，一个所述虚设电极图案组包括的所述多个虚设电极图案的个数与一个发光单元组包括的所述多个发光单元的个数相同，且所述虚设电极图案与所述第一电极位于同层。
可选的，所述显示面板还包括：位于所述第一电极和所述发光层之间的像素界定层；
所述像素界定层具有多个开口，一个所述开口用于露出一个所述发光单元的第一电极，且多个开口在所述衬底基板上的正投影与任一所述虚设电极图案在所述衬底基板上的正投影不重叠。
可选的，一个所述虚设电极图案组中的多个所述虚设电极图案与一个所述第一发光单元组中的多个第一发光单元一一对应，且所述虚设电极图案与对应的所述第一发光单元中的第一电极的形状和面积相同。
可选的，一个所述第一发光单元组包括：一个第一颜色的第一发光单元，两个第二颜色的第一发光单元，以及一个第三颜色的第一发光单元；
一个所述第二发光单元组包括：一个第一颜色的第二发光单元，两个第二颜色的第二发光单元，以及一个第三颜色的第二发光单元。
可选的，所述第一显示区中沿行方向相邻的两个第一颜色的第一发光单元的中心的距离，与所述第二显示区中沿所述行方向相邻的两个第一颜色的第二发光单元的中心的距离相等；
所述第一显示区中沿行方向相邻的两个第二颜色的第一发光单元的中心的距离，与所述第二显示区中沿所述行方向相邻的两个第二颜色的第二发光单元的中心的距离相等；
所述第一显示区中沿行方向相邻的两个第三颜色的第一发光单元的中心的距离，与所述第二显示区中沿所述行方向相邻的两个第三颜色的第二发光单元的中心的距离相等。
可选的，所述第一显示区中露出第一颜色的第一发光单元的开口在衬底基板上的正投影的面积，与所述第二显示区中露出第一颜色的第二发光单元的开口在衬底基板上的正投影的面积相等，且所述第一显示区中第一颜色的第一发光单元的第一电极在衬底基板上的正投影的面积，大于所述第二显示区中第一颜色的第二发光单元的第一电极在衬底基板上的正投影的面积；
所述第一显示区中露出第二颜色的第一发光单元的开口在衬底基板上的正投影的面积，与所述第二显示区中露出第二颜色的第二发光单元的开口在衬底基板上的正投影的面积相等，且所述第一显示区中第二颜色的第一发光单元的第一电极在衬底基板上的正投影的面积，大于所述第二显示区中第二颜色的第二发光单元的第一电极在衬底基板上的正投影的面积；
所述第一显示区中露出第三颜色的第一发光单元的开口在衬底基板上的正投影的面积，与所述第二显示区中露出第三颜色的第二发光单元的开口在衬底基板上的正投影的面积相等，且所述第一显示区中第三颜色的第一发光单元的第一电极在衬底基板上的正投影的面积，大于所述第二显示区中第三颜色的第二发光单元的第一电极在衬底基板上的正投影的面积。
可选的，所述第一发光单元组中的所述第一发光单元的第一电极包括：第一主体图案，以及与所述第一主体图案连接的第一连接图案，所述第一主体图案的至少部分与所述第一发光单元的发光层接触，且所述第一连接图案与所述第一像素电路组连接；
所述虚设电极图案包括：第二主体图案，以及分别与所述第二主体图案连接的第二连接图案和第三连接图案，所述第二主体图案与任一所述第一发光单元的发光层不接触，且所述第二连接图案与所述第二像素电路组连接，所述第 三连接图案通过第一连接走线或所述第二连接走线与所述第二发光单元组连接。
可选的，所述第一发光单元的第一电极还包括：与所述第一主体图案连接的第四连接图案；
所述第一发光单元中第一电极的第一主体图案在所述衬底基板上的正投影，与所述第一发光单元对应的虚设电极图案的第二主体图案在所述衬底基板上的正投影的形状和面积相同；
所述第一发光单元中的第一电极的第一连接图案在所述衬底基板上的正投影，与所述第一发光单元对应的虚设电极图案的第二连接图案在所述衬底基板上的正投影的形状和面积相同；
所述第一发光单元中的第一电极的第四连接图案在所述衬底基板上的正投影，与所述第一发光单元对应的虚设电极图案的第三连接图案在所述衬底基板上的正投影的形状和面积相同。
可选的，所述第一连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影不重叠，所述第四连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影至少部分重叠；
所述第二连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影不重叠，所述第三连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影至少部分重叠。
可选的，沿行方向相邻的两个所述第一图案组中的两个目标虚设电极图案对应的所述第一发光单元的颜色相同，且所述两个目标虚设电极图案的第三连接图案分别通过一个所述第一连接走线与所述第二发光单元组连接；
其中，所述两个目标虚设电极图案中，一个所述目标虚设电极图案中第三连接图案的连接部与另一个所述目标虚设电极图案中第三连接图案的连接部之间的连线，与所述行方向相交，所述第三连接图案的连接部用于与所述第一连接走线连接。
可选的，所述第一像素电路组包括多个第一像素电路单元，每个所述第一像素电路单元至少包括：第一像素电路和第二像素电路，且所述第一像素电路单元中的至少两个像素电路被配置为与所述第一发光单元组中同一个第一发光单元的第一电极电连接。
可选的，所述第一发光单元的第一电极包括的第一连接图案包括：沿目标方向延伸的第一主体连接部和位于所述第一主体连接部两端的两个第一端部；
其中，所述两个第一端部分别与所述第一像素电路和所述第二像素电路电连接，所述目标方向大致平行于行方向。
可选的，所述第二像素电路组包括多个第二像素电路单元，每个所述第二像素电路单元至少包括：第三像素电路和第四像素电路，且所述第二像素电路单元中的至少两个像素电路被配置为与同一个虚设电极图案电连接。
可选的，所述虚设电极图案包括的第二连接图案包括：沿目标方向延伸的第二主体连接部和位于所述第二主体连接部两端的两个第二端部；
其中，所述两个第二端部分别与所述第三像素电路和所述第四像素电路电连接，所述目标方向大致平行于行方向。
可选的，所述多个第二连接走线与所述虚设电极图案组位于同层。
可选的，所述多个第一连接走线的另一端的连线与所述第一显示区远离所述第二显示区的边缘平行，且所述多个第一连接走线的另一端的连线与所述第一显示区远离所述第二显示区的边缘之间的距离小于距离阈值。
可选的，所述多个第一连接走线的另一端的连线与所述第一显示区远离所述第二显示区的边缘均大致平行于列方向。
可选的，所述多个第一连接走线的另一端的连线与所述第一显示区远离所述第二显示区的边缘共线。
可选的，所述衬底基板还包括：位于所述第一显示区和所述第二显示区同一侧的第三显示区，所述显示面板还包括：位于所述第三显示区的多个第三发光单元组和多个第三像素电路组；
其中，每个所述第三像素电路组与一个所述第三发光单元组连接，所述多个第三发光单元组的密度大于所述多个第一发光单元组的密度，且大于所述多个第二发光单元组的密度。
可选的，所述衬底基板包括：两个所述第一显示区和一个所述第二显示区，所述第二显示区为矩形；
所述矩形沿行方向延伸的至少一个边缘与所述第三显示区相接，所述矩形沿列方向延伸的两个边缘分别与两个所述第一显示区相接。
可选的，所述第一显示区为矩形；所述第一显示区的任一边缘的长度范围为0.1毫米至20毫米；
所述第二显示区的任一边缘的长度范围为0.2毫米至10毫米。
可选的，所述显示面板还包括：多条数据线；
所述多条数据线中位于所述第二显示区域的至少一条目标数据线的至少部分在所述衬底基板上的正投影均位于所述第二显示区靠近所述第一显示区的区域。
另一方面，提供了一种显示装置，所述显示装置包括：供电组件以及如上述方面所述的显示面板；
所述供电组件用于为所述显示面板供电。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的结构示意图；
图2本申请实施例提供的一种显示面板的局部示意图；
图3是本申请实施例提供的另一种显示面板的局部示意图；
图4是本申请实施例提供的一种衬底基板的俯视图；
图5是本申请实施例提供的一种发光单元的示意图；
图6是本申请实施例提供的又一种显示面板的局部示意图；
图7是本申请实施例提供的再一种显示面板的局部示意图；
图8是本申请实施例提供的再一种显示面板的局部示意图；
图9是本申请实施例提供的再一种显示面板的局部示意图；
图10是本申请实施例提供的再一种显示面板的局部示意图；
图11是本申请实施例提供的再一种显示面板的局部示意图；
图12是本申请实施例提供的再一种显示面板的局部示意图；
图13是本申请实施例提供的再一种显示面板的局部示意图；
图14是本申请实施例提供的再一种显示面板的局部示意图；
图15是本申请实施例提供的一种第一像素电路组或第二像素电路组的等效电路图；
图16是本申请实施例提供的第一显示区内的像素电路的有源半导体层的局 部平面结构示意图；
图17是本申请实施例提供的第一显示区内的第一导电层的示意图；
图18是本申请实施例提供的第一显示区内的有源半导体层和第一导电层叠示意图；
图19是本申请实施例提供的第一显示区内的第二导电层的局部平面结构示意图；
图20是本申请实施例提供的第一显示区内的有源半导体层，第一导电层以及第二导电层的层叠示意图；
图21是本申请实施例提供的第一显示区的源漏金属层的局部平面结构示意图；
图22是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层以及源漏金属层的层叠示意图；
图23是本申请实施例提供的第一显示区的第一发光单元组与第一像素电路组的连接关系示意图；
图24是本申请实施例提供的一种第一电极和虚设电极图案的示意图；
图25是本申请实施例提供的第一显示区内的第一导电层，第二导电层，源漏金属层，第一连接走线，第一电极和虚设电极图案的层叠示意图；
图26是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层，源漏金属层，第一连接走线，第一电极和虚设电极图案的层叠示意图；
图27是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层，源漏金属层，第一连接走线，第一电极，虚设电极图案以及像素界定层的层叠示意图；
图28是图23所示第一显示区的第一发光单元组和过孔位置关系示意图；
图29是图1所示的显示面板中的第一显示区和第三显示区的部分平面图；
图30是本申请实施例提供的第三显示区和第一显示区交界处的部分像素电路结构示意图；
图31是图30所示位置的数据线连接部所在膜层结构示意图；
图32是图30所示位置的数据线所在膜层结构示意图；
图33是本申请实施例提供的第三显示区和第二显示区的边缘区交界处的部分像素电路结构示意图；
图34是本申请实施例的另一示例提供的显示面板中的第三显示区和第一显示区的部分平面图；
图35是本申请实施例提供的位于第三显示区的发光单元组的第一电极的示意图；
图36是本申请实施例提供的位于第一显示区非边缘的发光单元组的第一电极的示意图；
图37是本申请实施例提供的位于第二显示区的发光单元组的第一电极的示意图；
图38是本申请实施例提供的第一显示区的与第三显示区交界的两行发光单元组中的各发光单元的第一电极的示意图；
图39是本申请实施例提供的第一显示区的与第三显示区交界的两列发光单元组中的各发光单元的第一电极的示意图；
图40是图3沿A1至A2方向的截面图；
图41是图7沿B1至B2方向的截面图；
图42是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，为了提高显示面板的屏占比，可以将显示装置的摄像头设置在显示面板的显示区域。并且，为了增大摄像头所在区域的透过率，通常将该摄像头所在区域中各像素单元的像素电路设置在非摄像头区域。位于非摄像头区域的像素电路通过连接走线与位于摄像头区域的发光单元连接，从而为位于摄像头区域的发光单元提供驱动信号。
但是，由于显示区域中所能够设置的连接走线的数量有限，因此摄像头区域难以设置较多数量的发光单元，进而导致该摄像头区域的显示效果较差。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以 及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
图1是本申请实施例提供的一种显示面板的结构示意图。图2本申请实施例提供的一种显示面板的局部示意图。图3是本申请实施例提供的另一种显示面板的局部示意图。结合图1至图3可以看出，该显示面板10可以包括：衬底基板101，多个第一发光单元组102，多个第一像素电路组103，多个第二发光单元组104，多个第二像素电路组105，多个虚设电极图案组106，多个第一连接走线107，以及多个第二连接走线108。
图4是本申请实施例提供的一种衬底基板的俯视图。参考图4可以看出，该衬底基板101可以具有相邻的第一显示区101a和第二显示区101b。图4中示出了两个第一显示区101a和一个第二显示区101b。该第二显示区101b可以为设置有摄像头的区域。
结合图1至图4，多个第一发光单元组102位于第一显示区101a，多个第一像素电路组103位于第一显示区101a。第一像素电路组103与一个第一发光单元组102连接，且第一像素电路组103用于为与其连接的第一发光单元组102提供驱动信号，该驱动信号用于驱动该第一发光单元组102发光。
并且，结合图1至图4，多个第二发光单元组104位于第二显示区101b，多个第二像素电路组105位于第一显示区101a。该多个第二发光单元组104包括：至少一个第一类第二发光单元组104a和至少一个第二类第二发光单元组104b。该至少一个第二类第二发光单元组104b相对于至少一个第一类第二发光单元组104a靠近第一显示区101a。该多个第二像素电路组105包括：至少一个第一类第二像素电路组105a和至少一个第二类第二像素电路组105b。该至少一个第二类第二像素电路组105b相对于至少一个第一类第二像素电路组105a靠 近第二显示区101b。多个虚设电极图案组106位于第一显示区101a，该多个虚设电极图案组106包括：至少一个第一图案组106a和至少一个第二图案组106b。该至少一个第二图案组106b相对于至少一个第一图案组106a靠近第二显示区101b。
该多个第一连接走线107可以与多个虚设电极图案组106位于异层，即多个第一连接走线107与多个虚设电极图案组106需采用两次构图工艺分别制备。其中，第一连接走线107的一端与一个第一类第二发光单元组104a连接，另一端通过一个第一图案组106a与一个第一类第二像素电路组105a连接。也即是，位于第一显示区101a的第一类第二像素电路组105a可以通过第一连接走线107和第一图案组106a，与位于第二显示区101b的第一类第二发光单元组104a连接。由此可以使得每个第一类第二像素电路组105a为与其连接的第一类第二发光单元组104a提供驱动信号，该驱动信号用于驱动该第一类第二发光单元组104a发光。
该多个第二连接走线108可以与多个第一连接走线107位于异层，即该多个第二连接走线108与多个第一连接走线107需采用两次构图工艺分别制备。其中，第二连接走线108的一端与一个第二类第二发光单元组104b连接，另一端通过一个第二图案组106b与一个第二类第二像素电路组105b连接。也即是，位于第一显示区101a的第二类第二像素电路组105b可以通过第二连接走线108和第二图案组106b，与位于第二显示区101b的第二类第二发光单元组104b连接。由此可以使得每个第二类第二像素电路组105b为与其连接的第二类第二发光单元组104b提供驱动信号，该驱动信号用于驱动该第二类第二发光单元组104b发光。
由于显示面板10中空间有限，因此所能够设置的第一连接走线107的数量有限。由此，通过设置第二连接走线108，使得第一显示区101a靠近第二显示区101b的第二类第二像素电路组105b通过该第二连接走线108与第二显示区101b靠近第一显示区101a的第二类第二发光单元组104b连接，从而实现第二类第二发光单元组104b发光。也即是，即使显示面板10中所能够设置的第一连接走线107的数量有限，也可以增大第二显示区101b设置的第二发光单元组104的数量，不仅能够保证第二显示区101b的显示效果，而且可以允许设置较大尺寸的摄像头，对显示面板10的制造精度的要求较低。
并且，由于第二连接走线108连接的第二类第二像素电路组105b和第二类 第二发光单元组104b之间的距离较小，因此不仅便于制备，而且能够避免该第二连接走线108对第一显示区101a第一类第二发光单元组104a造成影响，保证第一类第二发光单元组104a的发光效果。
综上所述，本申请实施例提供了一种显示面板，该显示面板中位于第一显示区的多个第二像素电路组包括远离第二显示区的第一类第二像素电路组，以及靠近该第二显示区的第二类第二像素电路组。其中，第一类第二像素电路组通过第一连接走线与位于第二显示区且远离第一显示区的第一类第二发光单元组连接，第二类第二像素电路组通过第二连接走线与位于第二显示区且靠近第一显示区的第二类第二发光单元组连接。由于本申请实施例提供的方案还可以通过与第一连接走线位于异层的第二连接走线为第二类第二发光单元组提供驱动信号，因此可以在不增加第一连接走线的前提下，增加第二显示区所能够设置的第二发光单元组的数量，进而保证显示面板中第二显示区的显示效果。
可选的，该第一连接走线107的材料可以为透明材料，以避免该第一连接走线107对第二显示区101b的透过率造成影响。示例的，该第一连接走线107的材料可以为氧化铟锡(indium tin oxide，ITO)。另外，该多个第一连接走线107的延伸方向可以为行方向X。
在本申请实施例中，如图3所示，每一行像素最多可以设计13条第一连接走线107(该第一连接走线107的数量受限于第一连接走线107的宽度和像素尺寸)。也即是，第二显示区101b沿行方向X最多可设置26个像素(两个第一显示区101a分别设置13条第一连接走线107，即可存在26条第一连接走线107与26个像素一一连接)。但是，第二显示区101b沿行方向X需要更多数量的像素，则会存在一些像素缺少相应的第一连接走线107与其连接。由此，通过使得第一显示区101a靠近第二显示区101b的第二类第二像素电路组105b与第二显示区101b靠近第一显示区101a的第二类第二发光单元组104b通过设置的第二连接走线108连接，从而实现第二类第二发光单元组104b发光。其余第一类第二像素电路组105a通过第一连接走线107与第一显示区101a的第一类第二像素电路组105a连接。
参考图1和图4，该第二显示区101b可以包括中心区101b1以及围绕该中心区101b1的边缘区101b2。例如，图4示意性的示出第二显示区101b的形状为矩形，第二显示区101b的中心区101b1的形状为圆形，则边缘区101b2为位于矩形中除圆形中心区以外的区域。当然，第二显示区101b的中心区101b1以 及边缘区101b2还可以为其他形状，可以根据实际产品需求进行设置，本申请实施例对此不做限定。
可选的，该中心区101b可以作为屏下摄像区，该中心区101b1设置第二发光单元组104，驱动该第二发光单元组104发光的第二像素电路组105设置在第一显示区101a。由此，可以使得该中心区101b1具有较高的光透过率以实现摄像功能，又可以通过与其他区域(第一显示区101a)的像素电路组连接而实现发光，不影响屏幕的显示功能。
在本申请实施例中，参考图1，每个虚设电极图案组106在衬底基板101上的正投影，可以与至少一个第二像素电路组105在衬底基板101上的正投影至少部分重叠。其中，图1中采用同一个小方块表示重叠的第二像素电路组105和虚设电极图案组106，并采用105/106进行标注。可选的，每个虚设电极图案组106在衬底基板101上的正投影，可以与一个第二像素电路组105在衬底基板101上的正投影至少部分重叠。
并且，每个虚设电极图案组106与任一第一发光单元组102在衬底基板101上的正投影不重叠。该虚设电极图案组106与第一发光单元组102不重叠，可以避免该虚设电极图案组106对第一发光单元组102中的第一发光单元1021造成影响，保证该第一发光单元1021的发光效果。
参考图2和图3，每个第一发光单元组102和每个第二发光单元组104均可以包括多个发光单元，例如，第一发光单元组102包括多个第一发光单元1021，第二发光单元组104包括多个第二发光单元1041。图5是本申请实施例提供的一种发光单元的结构示意图。参考图5可以看出，该发光单元可以包括沿远离衬底基板101的方向依次层叠的第一电极a1，发光层a2以及第二电极a3。其中，该第一电极a1可以为阳极，第二电极a3可以为阴极。
并且，参考图6，每个虚设电极图案组106可以包括多个虚设电极图案1061，一个虚设电极图案组106包括的多个虚设电极图案1061的个数，与一个发光单元组(第一发光单元组102或者第二发光单元组104)包括的多个发光单元的个数相同。
示例的，每个虚设电极图案组106包括四个虚设电极图案1061，且每个发光单元组包括四个发光单元。
可选的，虚设电极图案组106中的虚设电极图案1061可以与发光单元中的第一电极a1位于同层，且第二连接走线108与第一电极a1也位于同层。也即是， 多个第二连接走线108可以与多个虚设电极图案组106位于同层。其中，多个第二连接走线108与多个虚设电极图案组106位于同层可以是指：多个第二连接走线108与多个虚设电极图案组106中的虚设电极图案1061位于同层。该虚设电极图案1061可以为虚设阳极图案，第二连接走线108可以为阳极走线。
或者，虚设电极图案组106中的虚设电极图案1061可以与发光单元中的第一电极a1位于同层，且多个第二连接走线108也可以与多个虚设电极图案组106位于异层。也即是，该多个第二连接走线108也可以不与第一电极a1位于同层。可选的，该多个第二连接走线107可以位于其他金属层，例如该多个第二连接走线107可以位于第二源漏极层。该第二源漏金属层和多个第二连接走线之间可以具有绝缘层，位于该第二源漏金属层的第二连接走线与虚设电极图案1061通过绝缘层中的过孔连接。本申请实施例对该虚设电极图案1061的设置位置不做限定。
另外，需要说明的是，虚设电极图案组106并不仅仅表示虚设(dummy)，该虚设电极图案组106还可以起到信号传递的作用。
参考图5可以看出，发光单元还可以包括：位于第一电极a1和发光层a2之间的像素界定层a4。该像素界定层a4可以具有多个开口a41，每个开口a41可以用于露出一个发光单元的第一电极a1。并且，多个开口a41在衬底基板101上的正投影与任一虚设电极图案1061在衬底基板101上的正投影不重叠。
通过使得像素界定层a4的开口a41露出发光单元的第一电极a1，能够使得发光单元的第一电极a1与发光层a2接触而实现发光。由于多个开口a41在衬底基板101上的正投影与任一虚设电极图案1061在衬底基板101上的正投影不重叠，因此该虚设电极图案1061处不发光。
需要说明的是，为了便于示意，本申请实施例提供的俯视图中均未示出发光层a2和阴极层a3，仅采用像素界定层a4的开口a41区分第一电极a1和虚设电极图案1061。其中，具有像素界定层a4开口a41的区域的图案为第一电极a1，不具有像素界定层a4开口a41的区域的图案为虚设电极图案1061。
在本申请实施例中，虚设电极图案组106中的多个虚设电极图案1061与一个第一发光单元组102中的多个第一发光单元1021一一对应，且虚设电极图案1061与对应的第一发光单元1021中的第一电极a1的形状和面积相同。
由于虚设电极图案1061与对应的第一发光单元1021中第一电极a1的形状和面积均相同，因此可以使得第一显示区101a的第一电极a1和第一连接走线 107的重叠面积，与虚设电极图案1061和第一连接走线107的重叠面积相同，进而使得第一显示区101a的第一电极a1以及虚设电极图案1061与第一连接走线107的交叠电容一致，保证显示面板10的显示效果。
当然，虚设电极图案1061与对应的第一发光单元1021中第一电极a1的形状和面积也可以不同，本申请实施例对此不做限定，只需使得第一显示区101a的第一电极a1和第一连接走线107的重叠面积，与虚设电极图案1061和第一连接走线107的重叠面积相同即可。
可选的，参考图7，每个发光单元组(例如第一发光单元组102或第二发光单元组104)可以包括：至少一个第一颜色的发光单元，至少一个第二颜色的发光单元以及至少一个第三颜色的发光单元。其中，该第一颜色，第二颜色和第三颜色可以为三基色。例如第一颜色为红色(red，R)，第二颜色为绿色(green，G)，第三颜色为蓝色(blue，B)。
示例的，参考图7，每个第一发光单元组102包括：一个第一颜色的第一发光单元b1，两个第二颜色的第一发光单元(b21和b22)，以及一个第三颜色的第一发光单元b3。其中，两个第二颜色的第一发光单元(b21和b22)可以统称为第二颜色的第一发光单元对b2。
并且，参考图2，每个第二发光单元组104包括：一个第一颜色的第二发光单元b1，两个第二颜色的第二发光单元(b21和b22)，以及一个第三颜色的第二发光单元b3。其中，两个第二颜色的第二发光单元(b21和b22)可以统称为第二颜色的第二发光单元对b2。
在本申请实施例中，每个虚设电极图案组106中的多个虚设电极图案1061也与一个第二发光单元组104中的多个第二发光单元1041一一对应，且每个虚设电极图案1061对应的第一发光单元1021和对应的第二发光单元1041的颜色相同。
可选的，第一显示区101a中沿行方向X相邻的两个第一颜色的第一发光单元1041的中心的距离，与第二显示区101b中沿行方向X相邻的两个第一颜色的第二发光单元1041的中心的距离相等。第一显示区101a中沿行方向X相邻的两个第二颜色的第一发光单元1021的中心的距离，与第二显示区101b中沿行方向X相邻的两个第二颜色的第二发光单元1041的中心的距离相等。第一显示区101a中沿行方向X相邻的两个第三颜色的第一发光单元1021的中心的距离，与第二显示区101b中沿行方向X相邻的两个第三颜色的第二发光单元1041 的中心的距离。
也即是，显示面板10位于第一显示区101a的部分的分辨率，可以与位于第二显示区101b的部分的分辨率相等。
可选的，第一显示区101a中露出第一颜色的第一发光单元1021的开口在衬底基板101上的正投影的面积，与第二显示区101b中露出第一颜色的第二发光单元1041的开口在衬底基板101上的正投影的面积相等。由此可以使得位于第一显示区101a的第一颜色的第一发光单元1021的发光区域的面积，与位于第二显示区101b的第一颜色的第二发光单元1041的发光区域的面积相等，保证第一显示区101a和第二显示区101b的第一颜色的发光单元的发光效果的均一性。
第一显示区101a中露出第二颜色的第一发光单元1021的开口在衬底基板101上的正投影的面积，与第二显示区101b中露出第二颜色的第二发光单元1041的开口在衬底基板101上的正投影的面积相等。由此可以使得位于第一显示区101a的第二颜色的第一发光单元1021的发光区域的面积，与位于第二显示区101b的第二颜色的第二发光单元1041的发光区域的面积相等，保证第一显示区101a和第二显示区101b的第二颜色的发光单元的发光效果的均一性。
第一显示区101a中露出第三颜色的第一发光单元1021的开口在衬底基板101上的正投影的面积，与第二显示区101b中露出第三颜色的第二发光单元1041的开口在衬底基板101上的正投影的面积相等。由此可以使得位于第一显示区101a的第三颜色的第一发光单元1021的发光区域的面积，与位于第二显示区101b的第三颜色的第二发光单元1041的发光区域的面积相等，保证第一显示区101a和第二显示区101b的第三颜色的发光单元的发光效果的均一性。
并且，在本申请实施例中，第一显示区101a中第一颜色的第一发光单元1021的第一电极a1在衬底基板101上的正投影的面积，大于第二显示区101b中第一颜色的第二发光单元1041的第一电极a1在衬底基板101上的正投影的面积。第一显示区101a中第二颜色的第一发光单元1021的第一电极a1在衬底基板101上的正投影的面积，大于第二显示区101b中第二颜色的第二发光单元1041的第一电极a1在衬底基板101上的正投影的面积。第一显示区101a中第三颜色的第一发光单元1021的第一电极a1在衬底基板101上的正投影的面积，大于第二显示区101b中第三颜色的第二发光单元1041的第一电极a1在衬底基板101上的正投影的面积。
图8是本申请实施例提供的再一种显示面板的局部示意图。参考图8，多个虚设电极图案组106中第二图案组包括第一个虚设电极图案1061a，第二个虚设电极图案1061b，第三个虚设电极图案1061c以及第四个虚设电极图案1061d。多个第二发光单元组104中的第二类第二发光单元组包括第一个第二发光单元1041a，第二个第二发光单元1041b，第三个第二发光单元1041c以及第四个第二发光单元1041d。其中，第一个虚设电极图案1061a与第一个第二发光单元1041a对应，第二个虚设电极图案1061b与第二个第二发光单元1041b对应，第三个虚设电极图案1061c与第三个第二发光单元1041c对应，第四个虚设电极图案1061d与第四个第二发光单元1041d对应。
参考图8，第一个虚设电极图案1061a与第二个第二发光单元1041b通过第二个第二连接走线108b连接。第二个虚设电极图案1061b与第一个第二发光单元1041a通过第一个第二连接走线108a连接。第三个虚设电极图案1061c与第四个第二发光单元1041d通过第四个第二连接走线108d。第四个虚设电极图案1061d与第三个第二发光单元1041c通过第三个第二连接走线108c连接。也即是，第二图案组中每个虚设电极图案1061并不是与第二类第二发光单元组104中对应的第二发光单元1041连接。当然，上述对应的连接方式也只是一种可选的情况，也可以通过其他的对应连接方式连接，例如第二图案组中每个虚设电极图案1061与第二类第二发光单元组104中对应的第二发光单元1041连接，本申请实施例对此不做限定。
图9是本申请实施例提供的一种显示面板的局部示意图。参考图9，该第一发光单元组102中的第一发光单元1021的第一电极a1包括：第一主体图案1021-1，以及与第一主体图案1021-1连接的第一连接图案1021-2。该第一主体图案1021-1所在区域具有像素界定层a4的开口a41，因此第一主体图案1021-1的至少部分与第一发光单元1021的发光层a2接触，且第一连接图案1021-2可以与第一像素电路组103连接。
并且，参考图9，虚设电极图案1061可以包括：第二主体图案1061-1，以及分别与第二主体图案1061-1连接的第二连接图案1061-2和第三连接图案1061-3。该第二主体图案1061-1所在区域不具有像素界定层a4的开口a41，因此第二主体图案1061-1可以与任一第一发光单元1021的发光层a2不接触。第二连接图案1061-2与第二像素电路组105连接，第三连接图案1061-3通过第一连接走线107或第二连接走线108与第二发光单元组104连接。
其中，对于某个虚设电极图案1061为第一图案组106a中的虚设电极图案1061，则该虚设电极图案1061的第三连接图案1061-3可以通过第一连接走线107与第一类第二发光单元组104a连接。对于某个虚设电极图案1061为第二图案组106b中的虚设电极图案1061，则该虚设电极图案1061的第三连接图案1061-3可以通过第二连接走线108与第二类第二发光单元组104b连接。
参考图9，该第一发光单元1021的第一电极a1也可以包括：与第一主体图案1021-1连接的第四连接图案1021-3。其中，第一电极a1的第一主体图案1021-1可以与虚设电极图案1061的第二主体图案1061-1对应，第一电极a1的第一连接图案1021-2可以与虚设电极图案1061的第二连接图案1061-2对应，第一电极a1的第四连接图案1021-3可以与虚设电极图案1061的第三连接图案1061-3对应。可选的，对应的两个图案的形状和面积相同，且对应的两个图案分别与第一连接走线107的重叠面积相同。
也即是，第一发光单元1021中第一电极a1的第一主体图案1021-1在衬底基板101上的正投影，与第一发光单元1021对应的虚设电极图案1061的第二主体图案1061-1在衬底基板101上的正投影的形状和面积相同。第一发光单元1021中的第一电极a1的第一连接图案1021-2在衬底基板101上的正投影，与第一发光单元1021对应的虚设电极图案1061的第二连接图案1061-2在衬底基板101上的正投影的形状和面积相同。第一发光单元1021中的第一电极a1的第四连接图案1021-3在衬底基板101上的正投影，与第一发光单元1021对应的虚设电极图案1061的第三连接图案1061-3在衬底基板101上的正投影的形状和面积相同。
在本申请实施例中，由于第一发光单元1021对应的虚设电极图案1061包括用于连接第一连接走线107或第二连接走线108的第三连接图案1061-3，因此为了使得第一电极a1与虚设电极图案1061的形状和面积相同，该第一电极a1也可以包括：与第三连接图案1061-3形状和面积相同的第四连接图案1021-3。其中，该第四连接图案1021-3无需与第一连接走线107或第二连接走线108连接。
在本申请实施例中，结合图7和图9，第一连接图案1021-2在衬底基板101上的正投影，与多个第一连接走线107在衬底基板101上的正投影不重叠。由此，可以使得第一电极a1的第一连接图案1021-2与第一像素电路组103的连接处，不会受到第一连接走线107的影响，可以确保与该第一像素电路组103连 接的第一发光单元组102中的第一发光单元1021正常发光。并且，第四连接图案1021-3在衬底基板101上的正投影，与多个第一连接走线107在衬底基板101上的正投影至少部分重叠。
结合图7和图9，第二连接图案1061-2在衬底基板101上的正投影，与多个第一连接走线107在衬底基板101上的正投影不重叠。由此，可以使得虚设电极图案1061与第二像素电路组105的连接处，不会受到第二连接走线108的影响，可以确保与该第二像素电路组105连接的第二发光单元组104中的第二发光单元正常发光。
并且，结合图7和图9，虚设电极图案1061的第三连接图案1061-3在衬底基板101上的正投影，与多个第一连接走线107在衬底基板101上的正投影至少部分重叠。
对于第一图案组106a中的虚设电极图案1061，由于该虚设电极图案1061的第三连接图案1061-3需要与第一连接走线107连接，因此该第三连接图案1061-3在衬底基板101上的正投影必然与多个第一连接走线107在衬底基板101上的正投影至少部分重叠。
通常情况下，为了保证第一显示区101a中虚设电极图案组106排布的均匀性，每个第二图案组106b可以与部分第一图案组106a沿行方向X排布。对于第二图案组106b中的虚设电极图案1061，该第二图案组106b中虚设电极图案1061在衬底基板101上的正投影和多个第一连接走线107在衬底基板101上的正投影的重叠面积，可以与第一图案组106a中虚设电极图案1061在衬底基板101上的正投影和多个第一连接走线107在衬底基板101上的正投影的重叠面积相同。
也即是，在第一图案组106a中虚设电极图案1061的第三连接图案1061-3在衬底基板101上的正投影和多个第一连接走线107在衬底基板101上的正投影至少部分重叠的情况下，第二图案组106b中虚设电极图案1061的第三连接图案1061-3在衬底基板101上的正投影和多个第一连接走线107在衬底基板101上的正投影至少部分重叠。
图10是本申请实施例提供的再一种显示面板的局部示意图。参考图10，显示面板10中包括沿行方向X相邻的两个第一图案组106a。该两个第一图案组106a均包括多个虚设电极图案1061，且第一个第一图案组106a包括的一个目标虚设电极图案c1，与第二个第一图案组106a包括的另一个目标虚设电极图案c2 对应。其中，两个目标虚设电极图案(c1和c2)对应的第一发光单元1021的颜色相同。例如，图10中以两个目标虚设电极图案(c1和c2)对应的第一发光单元1021的颜色均为红色为例。
参考图10，该两个目标虚设电极图案(c1和c2)中，一个目标虚设电极图案c1中第三连接图案1061-3的连接部d与另一个目标虚设电极图案c2中第三连接图案1061-3的连接部d之间的连线，与行方向X相交。其中，该第三连接图案1061-3的连接部d用于与第一连接走线107连接。
需要说明的是，由于两个目标虚设电极图案(c1和c2)需连接不同的第一连接走线107，且第一连接走线107通常沿行方向X延伸，因此两个目标虚设电极图案c1的第三连接图案1061-3中用于连接第一连接走线107的连接部d在列方向上存在间距，即这两个连接部d之间的连线可以与行方向X相交。
图11是本申请实施例提供的再一种显示面板的局部示意图。参考图11，图11中以两个目标虚设电极图案(c1和c2)对应的第一发光单元1021的颜色均为绿色为例。图12是本申请实施例提供的又一种显示面板的局部示意图。参考图12，图12中以两个目标虚设电极图案(c1和c2)对应的第一发光单元1021的颜色均为蓝色为例。
参考图1和图4可以看出，衬底基板101还可以包括：位于第一显示区101a和第二显示区101b同一侧的第三显示区101c以及周边区101d。
可选的，参考图4，衬底基板101包括两个第一显示区101a。第一显示区101a和第二显示区101b的形状均为矩形，两个第一显示区101a分别位于第二显示区101b的两侧，且两个第一显示区101a和第二显示区101b沿行方向X排布。
示例的，第一显示区101a和第二显示区101b位于显示区的边缘。其中，第一显示区101a，第二显示区101b以及第三显示区101c统称为显示区。第一显示区101a和第二显示区101b远离第三显示区101c的边缘与周边区101d相接。第二显示区101b(形状为矩形)沿行方向X延伸的一个边缘与第三显示区101c相接，另一个边缘与第四显示区101d相接。第二显示区101b沿列方向Y延伸的两个边缘分别与两个第一显示区101a相接。
可选的，第一显示区101a的任一边缘的长度范围为0.1毫米至20毫米。第二显示区101b的任一边缘的长度范围为0.2毫米至10毫米。并且，衬底基板101包括的两个第一显示区101a的形状和尺寸可以相同，也可以不同，本申请 实施例对此不做限定。
参考图1可以看出，该显示面板10还可以包括：位于第三显示区101c的多个第三发光单元组109和多个第三像素电路组110。其中，每个第三像素电路组110与一个第三发光单元组109连接，为该第三发光单元组109提供驱动信号，以驱动该第三发光单元组109发光。
可选的，多个第三发光单元组109的密度大于多个第一发光单元组102的密度，且大于多个第二发光单元组104的密度。屏下摄像区(第二显示区101b的中心区101b1)的第二发光单元组104的密度(即像素密度)低于正常显示区(第三显示区101c)的第三发光单元组109的密度，则摄像头可以设置在能够允许更多光透过的低像素密度区域的下方。上述“多个第三发光单元组109的密度大于多个第一发光单元组102的密度，且大于多个第二发光单元组104的密度”指相同面积下第三发光单元组的数量大于第二发光单元组的数量，且大于第一发光单元组的数量。
在本申请实施例中，第三显示区101c为主要的显示区域，具有较高的像素密度(pixel per inch，PPI)，即第三显示区101c内排布有密度较高的用于显示的第三发光单元组109。每个第三发光单元组109对应一个第三像素电路组110，且每个第三发光单元组109通过对应的一个第三像素电路组110驱动发光。第二显示区101b可以允许从显示面板显示侧射入的光透过显示面板而到达显示面板的背侧，从而使位于显示面板背侧的传感器等部件的正常工作。本申请实施例不限于此，例如，第二显示区101b也可以允许从显示面板的背侧发出的光通过显示面板而到达显示面板的显示侧。第一显示区101a和第二显示区101b也包括多个发光单元组，以用于显示。
但是，由于驱动发光单元组发光的像素电路组通常不透光，因此为了提高第二显示区101b的中心区101b1的透光性，可以将第二显示区101b的发光单元组与驱动该发光单元组的像素电路组从物理位置上分离。例如，与第二显示区101b中的发光单元组(例如图1中第二显示区101b内的方框所示的第二发光单元组104)连接的第二像素电路组105可以设置在第一显示区101a。也即是，第二像素电路组105会占据第一显示区101a的部分空间。并且，第一显示区101a的剩余空间用于设置第一显示区101a的第一发光单元组102和第一像素电路组103。例如图1中第一显示区101a中的每一个点填充方框代表一个像素(一个像素包括一个第一发光单元组102和一个第一像素电路组103)。此时， 第一显示区101a中的像素以及与第二显示区101b中的第二发光单元组104连接的第二像素电路组105在第一显示区101a中阵列排布。由此，第一显示区101a和第二显示区101b的分辨率低于第三显示区101c的分辨率，即第三显示区101c的像素密度大于第一显示区101a的像素密度，且大于第二显示区101b的像素密度。
图13是本申请实施例提供的再一种显示面板的局部示意图。参考图13可以看出，多个第一连接走线107的另一端的连线e可以与第一显示区101a远离第二显示区101b的边缘平行，且多个第一连接走线107的另一端的连线e可以与第一显示区101远离第二显示区101b的边缘之间的距离小于距离阈值。
该第一连接走线107的另一端可以远离第二显示区101b的一端。通过使得多个第一连接走线107的另一端的连线e与第一显示区101a远离第二显示区101b的边缘的距离设计的较小，可以使得第一显示区101a中各处均存在第一连接走线107。由此可以使得第一显示区101a中各处的交叠电容一致，保证该第一显示区101a的显示效果的均一性。
可选的，多个第一连接走线107的另一端的连线e与第一显示区101a远离第二显示区101b的边缘均可以大致平行于列方向Y。多个第一连接走线107的另一端的连线e可以与第一显示区101a远离第二显示区101b的边缘共线。
在本申请实施例中，由于第一显示区101a中能够发光的第一发光单元1021的数量较少，而第三显示区101c中能够发光的第三发光单元1091的数量较多，因此可能会导致该第一显示区101a的显示亮度比第三显示区101c的显示亮度低。由此，为了提高该第一显示区101a的显示亮度，可以使得每个第一发光单元1021通过至少两个像素电路进行驱动，进而提高该第一发光单元1021的亮度，保证第一显示区101a的显示效果和第三显示区101c的显示效果的一致性。
例如，第一像素电路组103包括的多个第一像素电路单元，每个第一像素电路单元至少包括：第一像素电路和第二像素电路，且该第一像素电路单元中的至少两个像素电路被配置为与第一发光单元组102中同一个第一发光单元1021的第一电极a1电连接。
参考图14，该第一发光单元1021的第一电极a1包括的第一连接图案1021-2可以包括：沿目标方向延伸的第一主体连接部1021-21和位于第一主体连接部1021-21两端的两个第一端部1021-22。其中，该目标方向可以大致平行于行方向X，两个第一端部1021-22可以分别与第一像素电路和第二像素电路连接。
可选的，由于多个第一连接走线107的延伸方向为行方向X，因此通常使得该第一连接图案1021-2中第一主体连接部1021-21的延伸方向(目标方向)大致平行于行方向X，以保证第一连接图案1021-2在衬底基板101上的正投影与多个第一连接走线107在衬底基板101上的正投影不重叠。
在本申请实施例中，为了保证第二显示区101b的透过率，通常该第二显示区101b设置的第二发光单元的数量较少，因此可能会导致该第二显示区101b的显示亮度比第三显示区101c的显示亮度低。由此，为了提高该第二显示区101b的显示亮度，可以使得每个第二发光单元通过至少两个像素电路进行驱动，进而提高该第二发光单元的亮度，保证第二显示区101b的显示效果。
例如，第二像素电路组105包括的多个第二像素电路单元，每个第二像素电路单元至少包括：第三像素电路和第四像素电路，且该第二像素电路单元中的至少两个像素电路被配置为与同一个虚设电极图案1061连接。每个虚设电极图案1061与一个第二发光单元的第一电极a1连接，由此实现两个像素电路与同一个第二发光单元的第一电极a1连接。
参考图14，该第二发光单元的第一电极a1包括的第二连接图案1061-2可以包括：沿目标方向延伸的第二主体连接部1061-21和位于第二主体连接部1061-21两端的两个第二端部1061-22。其中，该目标方向可以大致平行于行方向X，两个第二端部1061-22可以分别与第三像素电路和第四像素电路连接。
可选的，由于多个第一连接走线107的延伸方向为行方向X，因此通常使得该第二连接图案1061-2中第二主体连接部1061-21的延伸方向(目标方向)大致平行于行方向X，以保证第二连接图案1061-2在衬底基板101上的正投影与多个第一连接走线107在衬底基板101上的正投影不重叠。
在本申请实施例中，“大致”指的是可以允许有15％以内的误差范围。例如，“大致平行”可以是指两者的夹角在0度至30度之间，如可以为0度至10度，0度至15度等。
在本申请实施例中，第一像素电路单元和第二像素电路单元的结构可以相同，可以均称为像素电路对f。为了后续方便描述，可以将第一像素电路单元和第二像素电路单元中的每个像素电路单元包括的两个像素电路均称为第一像素电路和第二像素电路。也即是，为了方便描述，第二像素电路单元包括的第三像素电路可以称为第一像素电路，第二像素单元包括的第四像素电路可以称为第二像素电路。
图15是本申请实施例提供的一种第一像素电路组或第二像素电路组的等效电路图。参考图15，该第一像素电路组103包括多个第一像素电路单元。第二像素电路组105包括多个第二像素电路单元。并且，第一像素电路单元中的至少两个像素电路被配置为与第一发光单元组102中同一个第一发光单元1021的第一电极a1电连接。第二像素电路单元中的至少两个像素电路被配置为与同一个虚设电极图案1061电连接。
参考图15，第一像素电路单元和第二像素电路单元可以包括两个像素电路，则第一像素电路单元和第二像素单元均可以称为像素电路对f。本申请实施例示出第一像素电路单元包括两个像素电路，但不限于此，还可以包括三个像素电路或更多个像素电路。例如，第一发光单元组102包括多个第一发光单元1021，第一像素电路组103包括多个像素电路对f，第一像素电路组103中的每个像素电路对f被配置为与一个第一发光单元1021的第一电极a1连接以驱动该第一发光单元1021发光。第二发光单元组104包括多个第二发光单元1041，第二像素电路组105可以包括多个像素电路对f，第二像素电路组105中的每个像素电路对f被配置为与同一个虚设电极图案1061电连接以驱动一个第二发光单元1041发光。
可选的，显示面板10还包括位于衬底基板上的复位电源信号线，数据线，扫描信号线，电源信号线，复位控制信号线以及发光控制信号线。
其中，显示面板10包括的多条数据线中位于第二显示区101b的至少一条目标数据线的至少部分在衬底基板101上的正投影均位于第二显示区101b靠近第一显示区101a的区域。
如图15所示，各像素电路(第一像素电路f1和第二像素电路f2)包括数据写入晶体管T4，驱动晶体管T3，阈值补偿晶体管T2以及第一复位控制晶体管T7，阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极连接，第一复位控制晶体管T7的第一极与复位电源信号线连接以接收复位信号Vinit，第一复位控制晶体管T7的第二极与发光单元连接，数据写入晶体管T4的第一极与驱动晶体管T3的第二极连接。例如，如图15所示，各像素单元的像素电路还包括存储电容C，第一发光控制晶体管T6，第二发光控制晶体管T5和第二复位晶体管T1。数据写入晶体管T4的栅极与扫描信号线电连接以接收扫描信号Gate；存储电容C的第一极与电源信号线电连接，存储电容C的第二极与驱动晶体管T3的栅极电连接；阈值 补偿晶体管T2的栅极与扫描信号线电连接以接收补偿控制信号；第一复位晶体管T7的栅极与复位控制信号线电连接以接收复位控制信号Reset；第二复位晶体管T1的第一极与复位电源信号线电连接以接收复位信号Vinit，第二复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset；第一发光控制晶体管T6的栅极与发光控制信号线电连接以接收发光控制信号EM；第二发光控制晶体管T5的第一极与电源信号线电连接，第二发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM。上述电源信号线指输出电压信号VDD的信号线，可以与电压源连接以输出恒定的电压信号，例如正电压信号。
可选的，扫描信号和补偿控制信号可以相同，即数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T3的栅极电连接到第一扫描信号线，阈值补偿晶体管T2的栅极电连接到第二扫描信号线，而第一扫描信号线和第二扫描信号线传输的信号可以相同，也可以不同，从而使得数据写入晶体管T3的栅极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。
可选的，第一发光控制晶体管T6和第二发光控制晶体管T5被输入的发光控制信号可以相同，即第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的发光控制信号线，而不同的发光控制信号线传输的信号可以相同，也可以不同。
可选的，第一复位晶体管T7和第二复位晶体管T1被输入的复位控制信号可以相同，即第一复位晶体管T7的栅极和第二复位晶体管T1的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极也可以分别电连接至不同的复位控制信号线，此时，不同复位控制信号线上的信号可以相同也可以不相同。
例如，如图15所示，显示面板10工作时，画面显示的第一阶段，第二复位晶体管T1打开，使N1节点的电压初始化；第二阶段，同一个数据信号Data 通过两个相连的数据写入晶体管T4，以及与两个相连的数据写入晶体管T4分别连接的两个驱动晶体管T3以及两个阈值补偿晶体管T2存储在两个像素电路的两个N1节点；在第三发光阶段，两个像素电路(即第一像素电路f1和或第二像素电路f2组成的像素电路对f)中的第二发光控制晶体管T5，驱动晶体管T3以及第一发光控制晶体管T6均打开，以将同样的数据信号传输到两个N4节点，此时，两个像素电路的N4节点相连，共同驱动同一个发光单元A发光，可以达到增加电流和亮度的目的。其中，该发光单元A可以为第一显示区101a中第一发光单元组102中的第一发光单元1021，也可以为第二显示区101b中第二发光单元组104中第二发光单元1041。
需要说明的是，在本申请实施例中，像素单元的像素电路除了可以为图15所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构，6T1C结构，6T2C结构或者9T2C结构，本申请实施例对此不作限定。只要将两个像素电路的数据写入晶体管T4相连，并将两个像素电路的N4节点相连以实现共同驱动同一个发光单元发光即可。
图16是本申请实施例提供的第一显示区内的像素电路的有源半导体层的局部平面结构示意图。如图16所示，有源半导体层01可采用半导体材料图案化形成。有源半导体层01可用于制作上述的第二复位晶体管T1，阈值补偿晶体管T2，驱动晶体管T3，数据写入晶体管T4，第二发光控制晶体管T5，第一发光控制晶体管T6和第一复位控制晶体管T7的有源层。有源半导体层01包括各像素单元的各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层01为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，有源半导体层01可采用非晶硅，多晶硅，氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
图17是本申请实施例提供的第一显示区内的第一导电层的示意图。图18是本申请实施例提供的第一显示区内的有源半导体层和第一导电层叠示意图。 显示面板包括位于有源半导体层01远离衬底基板一侧的栅极绝缘层，用于将上述的有源半导体层01与后续形成的第一导电层02(即栅极金属层)绝缘。图18示出了该显示基板包括的第一导电层02，第一导电层02设置在栅极绝缘层上，从而与有源半导体层01绝缘。第一导电层02可以包括电容C的第二极CC2，沿行方向X延伸的多条扫描信号线g3，多条复位控制信号线g4，多条发光控制信号线g5以及第二复位晶体管T1，阈值补偿晶体管T2，驱动晶体管T3，数据写入晶体管T4，第二发光控制晶体管T5，第一发光控制晶体管T6和第一复位控制晶体管T7的栅极。
例如，结合图16至图18，数据写入晶体管T3的栅极可以为扫描信号线g3与有源半导体层01交叠的部分；第一发光控制晶体管T6的栅极可以为发光控制信号线g5与有源半导体层01交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线g5与有源半导体层01交叠的第二部分。第二复位晶体管T1的栅极为复位控制信号线g4与有源半导体层01交叠的第一部分，第一复位控制晶体管T7的栅极为复位控制信号线g4与有源半导体层01交叠的第二部分。阈值补偿晶体管T2可为双栅结构的薄膜晶体管，阈值补偿晶体管T2的第一个栅极可为扫描信号线g3与有源半导体层01交叠的部分，阈值补偿晶体管T2的第二个栅极可为从扫描信号线g3突出的突出结构P与有源半导体层01交叠的部分。如图18所示，驱动晶体管T1的栅极可为电容C的第二极CC2。
需要说明的是，图18中的各虚线矩形框示出了第一导电层02与有源半导体层01交叠的各个部分。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层01通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极，漏极在结构上可以是对称的，所以其源极，漏极在物理结构上可以是没有区别的。在本申请实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本申请实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
如图18所示，扫描信号线g3，复位控制信号线g4和发光控制信号线g5沿列方向Y排布。扫描信号线g3位于复位控制信号线g4和发光控制信号线g5之间。
在列方向Y上，电容C的第二极CC2(即驱动晶体管T1的栅极)位于扫描信号线g3和发光控制信号线g5之间。从扫描信号线g3突出的突出结构P位于扫描信号线g3的远离发光控制信号线g5的一侧。
在上述的第一导电层02上形成有第一绝缘层，用于将上述的第一导电层02与后续形成的第二导电层03绝缘。
图19是本申请实施例提供的第一显示区内的第二导电层的局部平面结构示意图，图20是本申请实施例提供的第一显示区内的有源半导体层，第一导电层以及第二导电层的层叠示意图。如图19和图20所示，第二导电层03包括电容C的第一极CC1以及沿行方向X延伸的多条复位电源信号线g1。电容C的第一极CC1与电容C的第二极CC2至少部分重叠以形成电容C。其中，该第二导电层03可以为栅极金属层。
参考图19和图20，本申请实施例提供的显示面板10还包括多个第一连接部h1，至少部分第一连接部h1的第一端与第一像素电路单元中的第一像素电路f1的数据写入晶体管T4的第二极连接(例如，第一连接部h1的第一端与第一像素电路单元中的第一像素电路f1的数据写入晶体管T4的第二极可以直接连接，也可以通过导电层转接层电连接)，第一连接部h1的第二端与第一像素电路单元中的第二像素电路f2的数据写入晶体管T4的第二极连接以使第一像素电路单元的至少两个数据写入晶体管T4与同一条数据线连接，且沿列方向，第一连接部h1的至少部分位于第一像素电路f1中的数据写入晶体管T2的第二极与第一复位控制晶体管T7的第一极之间。
在本申请实施例中，第一显示区101a内的至少两个像素电路的数据写入晶体管的第二极通过第一连接部h1连接以驱动一个发光单元A发光，可以增加第一显示区101a的发光单元的电流和亮度。例如可使第一显示区101a的第一发光单元1021的电流和亮度增加到采用一个像素电路驱动情况下的1.8到2倍，解决了第一显示区101a中电流和亮度偏小的问题，实现更加均匀的全面屏的视觉显示效果。
可选的，部分第一连接部h1的第一端与第二像素电路单元中的第三像素电路的数据写入晶体管T4的第二极连接，第一连接部h1的第二端与第二像素电路单元中的第四像素电路的数据写入晶体管T4的第二极连接以使第二像素电路单元的至少两个数据写入晶体管T4与同一条数据线连接。且沿列方向Y，第一连接部h1位于第三像素电路中的数据写入晶体管T2的第二极与第一复位控制晶体管T7的第一极之间。为了方便后续描述，本申请实施例中的第一像素电路单元和第二像素电路单元统一称为像素电路对f，则各像素电路单元包括的两个像素电路均称为第一像素电路和第二像素电路，即第二像素电路单元中的第三 像素电路可以称为第一像素电路，第二像素电路单元中的第四像素电路可以称为第二像素电路。
可选的，沿列方向Y，第一连接部h1位于第一像素电路f1中的阈值补偿晶体管T3的第二极与第一复位控制晶体管T7的第一极之间。
可选的，第一连接部h1与复位电源信号线g1同层设置。
可选的，在上述的第二导电层03上形成有第二绝缘层，用于将上述的第二导电层03与后续形成的源漏极金属层04绝缘。
图21是本申请实施例提供的第一显示区的源漏金属层的局部平面结构示意图，图22是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层以及源漏金属层的层叠示意图。如图21和图22所示，源漏极金属层04包括沿列方向Y延伸的数据线g2以及电源信号线g6。数据线g2通过贯穿栅极绝缘层，第一绝缘层和第二绝缘层的过孔与数据写入晶体管T2的第二极电连接。电源信号线g6通过贯穿栅极绝缘层，第一绝缘层和第二绝缘层的过孔与第二发光控制晶体管T5的第一极电连接。电源信号线g6和数据线g2沿行方向交替设置。电源信号线g6通过贯穿第二绝缘层的过孔与电容C的第一极CC1电连接。
在本申请实施例中，在上述的源漏极金属层04远离衬底基板101的一侧可以设置第三绝缘层用于保护上述的源漏极金属层04。
例如，图20至图22示意性的示出第一像素电路组103中的部分像素电路以及第二像素电路组105中的部分像素电路。本公开实施例示意性的示出第一像素电路组103和第二像素电路组105均包括像素电路对f，像素电路对f包括沿行方向X排列的第一像素电路f1和第二像素电路f2，且各像素电路对f中的两个像素电路的数据写入晶体管T4的第二极均通过第一连接部h1连接以驱动同一个发光单元发光。本申请实施例不限于此，例如，还可以仅第一像素电路组103包括上述像素电路对f，或者仅第二像素电路组105包括上述像素电路对f。
例如，如图20至图22所示，第一像素电路组103和第二像素电路组105可以包括排列为两行的八个像素电路，即二维阵列排布的四个像素电路对f。而第三像素电路组不包括上述像素电路对f(未示出)，仅包括二维阵列排布的四个像素电路，第三像素电路组中沿行方向X排列的相邻的两个像素电路各驱动一个发光单元发光，且该相邻的两个像素电路中的两个数据写入晶体管彼此独 立，且分别连接不同的数据线。本申请实施例中的第三像素电路组与第一像素电路组103的版图区别主要在于是否设置了第一连接部h1，以及与第一连接部h1连接的数据写入晶体管的第二极的位置的设置。
例如，如图20至图22所示，本申请实施例提供的显示面板10可以采用四分之一全高屏分辨率(quarter high definition，QHD)，但是由于以该分辨率设计的各个像素电路的阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间沿列方向的距离很小，例如小于2微米，例如为1.4微米至1.8微米。由此，阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间很难设置连接像素电路对f的两个数据写入晶体管的第二极(data输入节点)的第一连接部h1。由于QHD分辨率产品中像素的大小一般小于全屏分辨率(full high definition，FHD)产品中像素的大小，因此本申请实施例中，将具有QHD分辨率的像素电路设计到具有FHD分辨率的像素间距(pixel pitch)里，从而增加各像素电路中阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间在沿列方向Y上的距离，以保证像素电路对f的两个像素电路的data输入节点通过第一连接部h1实现打孔连接。
例如，如图20至图22所示，相对于一种显示面板，其第一显示区中包括多个发光单元以及与多个发光单元一一对应连接的多个像素电路，相邻像素电路之间设置不与任何发光单元连接的虚设像素电路的情况，本申请实施例中，采用第一连接部h1连接虚设像素电路(第二像素电路组105中的像素电路)与连接第一显示区101a中的第一发光单元1021的像素电路，可以在尽量少改变像素电路整体结构的基础上，有效利用虚设像素电路，从而可以增加第一显示区101a(和第二显示区101b至少之一)的发光单元的电流和亮度，实现更加均匀的全面屏的视觉显示效果。
可选的，阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间在沿列方向Y上的距离为7微米至12微米以在阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间设置第一连接部h1。
如图16至图22所示，各像素电路还包括：与数据线g2同层设置的第二连接部h2和第三连接部h3，第二连接部h2被配置为连接阈值补偿晶体管T2的第二极和驱动晶体管T3的栅极，第三连接部h3被配置为连接第一复位控制晶体管T7的第一极和复位电源信号线g1。可选的，第二连接部h2的一端通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层中的过孔与阈值补偿晶体管T2的第二极 电连接，第二连接部h2的另一端通过贯穿第一绝缘层和第二绝缘层中的过孔与驱动晶体管T3的栅极(即电容C的第二极CC2)电连接。第三连接部h3的一端通过贯穿第二绝缘层中的过孔与复位电源信号线g1电连接，第三连接部h3的另一端通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层中的过孔与第一复位控制晶体管T7的第一极电连接。
如图16至图22所示，第一像素电路f1中，第二连接部h2与第三连接部h3的彼此靠近的边缘之间的在列方向的距离为7微米12微米以在第二连接部h2与第三连接部h3之间设置第一连接部h1。例如，第一像素电路f1中，第二连接部h2与第三连接部h3的彼此靠近的边缘之间的在列方向的距离可以为8微米至11微米。
如图16至图22所示，第一连接部h1与数据线g2位于不同层，且沿垂直于衬底基板的第三方向，各第一连接部h1与数据线g2和电源信号线g6有交叠。例如，像素电路对f包括的两个数据写入晶体管T4之间设置有一条数据线410和一条电源信号线g6，连接上述两个数据写入晶体管T4的第一连接部h1与数据线410和电源信号线g6均有交叠。
如图16至图22所示，各像素电路还包括与数据线g2同层设置的第四连接部h4，第四连接部h4被配置为连接第一连接部h1和数据写入晶体管T4的第二极，像素电路对f中的一个像素电路(例如第二像素电路f2)的第四连接部h4与紧邻的数据线g2之间具有间隔，像素电路对f的另一个像素电路(例如第一像素电路f1)的第四连接部h4与数据线g2为一体结构以实现像素电路对f仅与一条数据线g2连接。上述“第四连接部h4与紧邻的数据线g2之间具有间隔”中“紧邻的数据线”指第四连接部h4和该数据线g2之间没有其他数据线。
如图1以及图16至图22所示，多个第三发光单元110沿行方向X和列方向Y呈阵列排布。沿行方向X，多个第一像素电路组103和多个第二像素电路组105交替设置，沿列方向Y，多个第一像素电路组103和多个第二像素电路组105交替设置，且第一像素电路组103和第二像素电路组105与不同的数据线g2连接。
沿行方向X延伸的直线经过像素电路对f中的两个数据写入晶体管的第二极，第一连接部h1的整体沿行方向延伸。例如，不同像素电路组连接不同的数据线，因此不同像素电路组中的第一连接部h1沿行方向X的长度可以不同。例如，同一像素电路组中，不同像素电路对f中的第一连接部h1沿行方向X的长 度也可以不同。
如图21所示，以与数据线g2为一体的第四连接部h4为第一子部h41，与紧邻数据线g2具有间隔的第四连接部h4为第二子部h42，以第二像素电路组105包括八个阵列排布的像素电路(沿行方向排列四个像素电路，沿列方向排列的两个像素电路)为例，则第一像素电路组103中，两个第一子部h41沿列方向排列(即位于一行)，两个第二子部h42沿列方向Y排列(即位于一列)，且第一子部h41与第二子部h42在行方向X上交替排列。同理，第二像素电路组105中的第一子部和第二子部的排列方式与第一像素电路组103中的第一子部和第二子部的排列方式相同。对于沿列方向Y交替排列的第一像素电路组103和第二像素电路组105，第一像素电路组103中的第一子部和第二像素电路组105中的第二子部位于不同列以使第一像素电路组103与第二像素电路组105连接至不同的数据线。
由于第三发光单元110中没有像素电路对f的设计，所以第三发光单元110中沿行方向X或列方向排列的相邻两个像素电路中的第四连接部均与数据线为一体结构以实现各像素电路与相应数据线的电连接。
如图16至图22所示，显示面板10还包括与第一连接部h1同层设置的多个覆盖部S，各阈值补偿晶体管T2包括两个栅极T2-g1和T2-g2以及位于两个栅极之间的有源半导体层01。沿垂直于衬底基板101的承载面的方向，覆盖部S与两个栅极之间的有源半导体层01、数据线g2以及电源信号线g6均有交叠。
双栅型阈值补偿晶体管T2的两段沟道之间的有源半导体层01在阈值补偿晶体管T2关闭时处于浮置(floating)状态，易受周围线路电压的影响而跳变，从而会影响阈值补偿晶体管T2的漏电流，进而影响发光亮度。为了保持阈值补偿晶体管T2的两段沟道之间的有源半导体层01电压稳定，设计覆盖部S与阈值补偿晶体管T2的两段沟道之间的有源半导体层01形成电容，覆盖部S可以连接至电源信号线g6以获得恒定电压，因此处于浮置状态的有源半导体层01的电压可以保持稳定。覆盖部S与双栅型阈值补偿晶体管T2的两段沟道之间的有源半导体层01交叠，还可以防止两个栅极之间的有源半导体层01被光照而改变特性，例如防止该部分有源半导体层01的电压发生变化，以防止产生串扰。电源信号线g6可以通过贯穿第二绝缘层的过孔与覆盖部S电连接以为覆盖部S提供恒定电压。
与有源半导体层01交叠的覆盖部S在沿行方向X延伸的第一直线上的正投 影与第一连接部h1在第一直线上的正投影有交叠，第四连接部h4在沿列方向Y延伸的第二直线上的正投影与覆盖部S在第二直线上的正投影有交叠，由此，为了与同层设置的覆盖部S保持距离，第一连接部h1的整体设置为非直线型，例如折线形。
例如，如图16至图22所示，第一连接部h1包括沿行方向X延伸的主体连接部h1和位于主体连接部h1两端的且沿列方向Y延伸的两个端部h12，两个端部h12分别与像素电路对f的两个第四连接部h4连接，两个端部h12在第二直线上的正投影与覆盖部S在第二直线上的正投影有交叠。由此，主体连接部和两个端部形成了折线形以与覆盖部保持距离。
例如，在列方向Y上，覆盖部S与阈值补偿晶体管T2的第二极之间的距离小于覆盖部S与第一复位控制晶体管T7的第一极之间的距离，即覆盖部S更靠近阈值补偿晶体管T2。由此，为了方便设计，且使得第一连接部h1与覆盖部S之间保持一定间隔，第一连接部h1设置为更靠近第一复位晶体管T7的第一极，即，在列方向Y上，主体连接部h1与第一像素电路f1中的阈值补偿晶体管T2的第二极之间的距离大于主体连接部h1与第一像素电路f2中的第一复位控制晶体管T7的第一极之间的距离。
图23是本申请实施例提供的第一显示区的第一发光单元组与第一像素电路组的连接关系示意图。图24是本申请实施例提供的一种第一电极和虚设电极图案的示意图。图25是本申请实施例提供的第一显示区内的第一导电层，第二导电层，源漏金属层，第一连接走线，第一电极和虚设电极图案的层叠示意图。图26是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层，源漏金属层，第一连接走线，第一电极和虚设电极图案的层叠示意图。图27是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层，源漏金属层，第一连接走线，第一电极，虚设电极图案以及像素界定层的层叠示意图。
如图1至图27所示，各发光单元组包括多个发光单元，例如第一发光单元组102包括多个第一发光单元1021，第二发光单元组104包括多个第二发光单元1041，第三发光单元组109包括多个第三发光单元1091。其中，结合图24至图27，所示的图案为第一电极a1还是为虚设电极图案1061，取决于像素界定层a4在此处是否具有开口a41。像素界定层a4具有开口a41的区域的图案为第一电极a1，像素界定层a4不具有开口的区域的图案为虚设电极图案1061。
例如，各第一发光单元组1021包括一个第一颜色的第一发光单元b1，一个第二颜色的第一发光单元对b2以及一个第三颜色的第一发光单元b3。第一颜色的第一发光单元b1和第三颜色的第一发光单元b3沿列方向Y排列，第二颜色的第一发光单元对b2包括沿列方向Y排列的两个第二颜色的第一发光单元1021。第一颜色的第一发光单元b1和第二颜色的第一发光单元对b2沿行方向排列。例如，第一颜色的第一发光单元b1的第一电极a1在沿列方向Y延伸的直线上的正投影与第二颜色的第一发光单元b21的第一电极a1在该直线上的正投影有交叠。第三颜色的第一发光单元b3的第一电极a1在列方向Y延伸的直线上的正投影与两个第二颜色的第一发光单元1021的第一电极a1之间的间隔在该直线上的正投影交叠。例如，第三颜色的第一发光单元b3的主体图案(后续描述)在列方向Y延伸的直线上的正投影与两个第二颜色的第一发光单元1021的主体图案在列方向Y上的正投影没有交叠。
例如，参考图5，各发光单元包括沿远离衬底基板101的方向依次设置的第一电极a1，发光层a2以及第二电极a3。显示基板还包括像素限定层a4，像素限定层a4包括用于限定像素单元的发光区的开口a41，该开口a41暴露发光单元A的第一电极a1，当后续的发光单元A的发光层a2形成在上述像素限定层a4的开口a41中时，发光层a2与第一电极a1接触，从而这部分能够驱动发光层a2进行发光以形成有效发光区。这里的“有效发光区”可以指二维的平面区域，该平面区域平行于衬底基板。需要说明的是，像素限定层的开口a41由于工艺原因，远离衬底基板的部分尺寸略大于靠近衬底基板部分的尺寸，或者从靠近衬底基板一侧到远离衬底基板一侧的方向上呈现尺寸逐渐增加的形态，因此有效发光区的尺寸与像素限定层开口a41的不同位置的尺寸可能略有不同，但整体区域形状和尺寸基本相当。例如，有效发光区在衬底基板上的正投影与对应的像素限定层的开口a41在衬底基板上的正投影大致重合。例如，有效发光区在衬底基板上的正投影完全落在对应的像素限定层的开口a41在衬底基板上的正投影内，且二者形状相似，有效发光区在衬底基板上的投影面积相比对应的像素限定层的开口a41在衬底基板上的投影面积略小。
如图1至图27所示，各像素电路还包括与数据线g2同层设置的第五连接部h5，位于第二显示区101b和第三显示区101c的发光单元A的第一电极a1可以直接通过第五连接部h5与第一发光控制晶体管T6的第二极电连接。例如，第三显示区101c中，第三发光单元组109中的各个第三发光单元1091的第二 极可以直接通过第三像素电路组110中相应的像素电路的第五连接部h5与第一发光控制晶体管T6的第二极电连接。第一显示区101a中，第一发光单元组102中的各个第一发光单元1021的第二极可以直接通过第一像素电路组103中相应的像素电路的第五连接部h5与第一发光控制晶体管T6的第二极电连接。例如，第一显示区101a中，第一发光单元组102中的各个第一发光单元1021的第二极可以通过第三绝缘层中的第一过孔i1与第五连接部h5连接。
参考图1至图27所示，第一像素电路组103包括多个像素电路对f，第一发光单元组102的各个第一发光单元1021的第一电极a1包括第一主体图案以及连接图案(第一连接图案和第二连接图案)。主体图案的形状与各个第一发光单元1021的有效发光区的形状基本相同，连接图案(第一连接图案1021-2)被配置为直接与第五连接部h5电连接以与像素电路对f的两个第一发光控制晶体管T6的第二极电连接。
如图1至图27所示，显示面板10还包括位于第一电极a1与数据线g2所在膜层之间多条第一连接走线107，各第一连接走线107沿行方向X延伸。例如，第二像素电路组105包括多个像素电路对f，第一连接走线107被配置为连接第一类第二发光单元组104a中的第二发光单元1041的第一电极a1以及第五连接部h5以使第一类第二发光单元组104的各个第二发光单元1041的第一电极a1与第二像素电路组105的像素电路对f的两个第一发光控制晶体管T6的第二极电连接。
第一显示区101a中，第一连接走线107通过第三绝缘层中的第二过孔i21与第二像素电路组105中的第五连接部h5电连接。第二显示区101b中，第二发光单元1041的第一电极a1通过与第一连接走线107连接，进而实现与第一显示区101a中的像素电路的连接。
例如，图28是图23所示第一显示区的第一发光单元组和过孔位置关系示意图。其中，图28中未示出虚设电极图案组106以及发光单元组中发光单元的第一电极a1的第四连接图案1021-3。如图23和图28所示，连接一个第一发光单元组102和一个第一像素电路组103的多个第一过孔i11组成的一个第一过孔组i1，连接一个第二发光单元组104310和一个第二像素电路组105的多个第二过孔i21组成一个第二过孔组i2。沿行方向X，多个第一过孔组i1和多个第二过孔组i2交替排列；沿列方向Y，多个第一过孔组i1和多个第二过孔组i2交替排列。相对于第一发光单元组102和第二发光单元组104均通过第一连接走线 105所在膜层与第五连接部连接的情况，本申请实施例中，第一发光单元组102的发光单元的第一电极a1直接与第五连接部连接，而第二发光单元组104的发光单元的第一电极a1通过第一连接走线107与第五连接部连接，可以将更多空间留给透明走线，防止信号发生串扰。
例如，图29是图1所示的显示面板中的第一显示区和第三显示区的部分平面图。如图1和图29所示，本申请实施例中，显示面板10中的第三显示区101c和第一显示区101a包括沿行方向X和列方向Y排列的多个像素电路以形成多个像素电路行j1和多个像素电路列j2。位于第三显示区101c的多个像素电路包括多个第三子像素电路k3。位于第一显示区101a的多个像素电路包括多个第一子像素电路k1，第三显示区101c的多个第三发光单元1091(即第三发光单元组109中包括的三种颜色的发光单元，例如图中所示的R、G1、G2、B)与多个第三子像素电路k3一一对应连接，第一显示区101a的各个第一发光单元1021(即第一发光单元组102中包括的三种颜色的发光单元，例如图中所示的R、G1、G2、B)与至少两个第一子像素电路k1连接。
如图1所示，第三显示区101c和第一显示区101a在列方向Y(即数据线的延伸方向)上相接。第二显示区101b包括中心区101b1以及围绕中心区101b1的边缘区101b2，且第二显示区101b的边缘区101b2与第三显示区101c在列方向Y上相接。图1示意性的示出第二显示区101b的形状为矩形，第二显示区101b的中心区101b1的形状为圆形，则边缘区101b2为位于矩形中除圆形中心区以外的区域。本申请实施例不限于此，第二显示区101b的中心区101b1和边缘区101b2的形状可以根据实际产品需求进行设置。
例如，如图1所示，第二显示区101b的中心区101b1和边缘区101b2均设置有第二发光单元组104，且位于第二显示区101b的多个第二发光单元组104通过第一连接走线107或第二连接走线108分别与第一显示区101a中的多个第二像素电路组105电连接，从而驱动第二发光单元组104发光。第二显示区101b的中心区101b1仅设置发光单元组，不设置像素电路组从而可以减少金属覆盖面积，以实现较高的透光率，而第二显示区101b的边缘区101b2除设置发光单元组外还设置有挡光结构以使得第二显示区101b形成具有预设形状的透光区(即中心区101b1)。例如，本申请实施例中设置在第二显示区101b的边缘区101b2的挡光结构可以为多个虚设像素电路组111，多个虚设像素电路组111包括位于第二发光单元组104与衬底基板101之间的部分，以及位于相邻第二发 光单元组104之间的间隔的部分，各虚设像素电路组111不与任何发光单元组连接，仅为悬空的像素电路。例如，边缘区101b2为环形走线区。例如，连接第二像素电路组105的数据线，扫描信号线g3，电源信号线，复位控制线，发光控制信号线，复位电源信号线等走线均位于环形走线区。
例如，如图1所示，第二显示区101b中的第二发光单元组104可以采用左右对半控制的方式，由关于第二显示区101b的沿列方向Y延伸的中心线轴对称的两个第一显示区101a中的第二像素电路组105分别进行控制。例如，位于上述中心线左侧的第二发光单元组104由位于中心线左侧的第一显示区101a内的第二像素电路组105控制，位于上述中心线右侧的第二发光单元组104由位于中心线右侧的第一显示区101a内的第二像素电路组105控制。用于驱动圆形中心区101b1中的发光单元的走线以密集排布的方式布置在边缘区101b2中，可以使作为屏下显示区的圆形中心区101b1具有尽量大的面积。
例如，如图1所示，第三显示区101c和第一显示区101a包括沿行方向X和列方向Y排列的多个像素电路以形成多个像素电路行j1和多个像素电路列j2。例如，第二显示区101b的边缘区101b2包括沿行方向X和列方向Y排列的多个虚设像素电路1111以形成多个虚设像素电路列和多个虚设像素电路行。这里将第二显示区101b中的虚设像素电路也称为像素电路，虽然虚设像素电路不与任何发光单元连接，但是其结构可以与其他区域的像素电路结构大致相同。例如，均包括7T1C(即七个晶体管和一个电容)结构。可选的，多条沿列方向Y延伸的数据线g2分别与多个像素电路列j2相连。
例如，如图1至图23所示，各像素电路列j2包括相邻四列组成的像素电路列组，每个像素电路列组包括沿行方向X(即与数据线g2的延伸方向相交的方向)依次排列的第一像素电路列j21，第二像素电路列j22，第三像素电路列j23和第四像素电路列j24。第三显示区101c内的第一像素电路列j21，第二像素电路列j22，第三像素电路列j23以及第四像素电路列j24分别与沿第行方向X依次排列的第一数据线g21，第二数据线g22，第三数据线g23和第四数据线g24相连。第一显示区101a内的第一像素电路列j21中的至少部分像素电路，第二像素电路列j22中的至少部分像素电路，第三像素电路列j23中的至少部分像素电路以及第四像素电路列j24中的至少部分像素电路分别与沿第行方向X依次排列的第一数据线g21，第二数据线g22，第三数据线g23和第四数据线g24相连。
例如，如图1至图23所示，在第一显示区101a内，在至少一个像素电路列组中，位于同一像素电路行j1且位于第一像素电路列j21和第二像素电路列j22的两个像素电路的数据输出端(即第四连接部h4)电连接以形成第一像素电路对f1a，位于同一像素电路行j1且位于第三像素电路列j23和第四像素电路列j24的两个像素电路的数据输出端(即第四连接部h4)电连接以形成第二像素电路对f2a。本申请实施例示意性的示出第一显示区101a内的各像素电路列组均包括第一像素电路对f1a和第二像素电路对f2a为例进行描述，但不限于此，可以根据实际产品需求进行设置。
例如，如图1至图23，第三显示区101c，第一显示区101a和第二显示区101b均包括多个发光单元A，第三显示区101c内的多个发光单元1091分别与第三显示区101c的多个像素电路连接。第一显示区101a的多个发光单元1021分别与第一显示区101a的一部分像素电路连接，第二显示区101b的多个发光单元1041分别与第一显示区101a的另一部分像素电路连接。即第一显示区101a中，第一发光单元组102中的发光单元20与第一像素电路组103中的像素电路连接；第二显示区101b中的第二发光单元组104中的第二发光单元1041与第一显示区101a中的第二像素电路组105中的像素电路连接。本申请实施例示意性的示出第一显示区101a仅包括第一像素电路组103和第二像素电路组105，但不限于此，根据产品中空间设计需求等因素，第一显示区101a还可以包括其他像素电路组，例如虚设像素电路组(不与发光单元连接的)等。
例如，如图1至图23所示，第一显示区101a内的第一像素电路组103和第二像素电路组105均包括第一像素电路对f1a和第二像素电路对f2a，则第一显示区101a和第二显示区101b中，多个发光单元分别与第一显示区101a内的多个第一像素电路对f1a和多个第二像素电路对f2a连接。
例如，本申请实施例中第三显示区101c设置的发光单元可以称为第三发光单元1091，第一显示区101a设置的发光单元可以称为第一发光单元1021，第二显示区101b设置的发光单元可以称为第二发光单元1041。
由于第一像素电路组103和第二像素电路组105在行方向X和列方向Y均交替排列，且沿列方向Y排列的同一列第一像素电路组103和第二像素电路组105与不同的数据线g2连接。因此，位于第一显示区101a内的第一像素电路列j21中的部分像素电路与第一数据线g21相连，例如位于第一像素电路列j21中的第一像素电路组103中的像素电路与第一数据线g21相连，而位于第一像素 电路列j21中的第二像素电路组105中的像素电路与第一数据线g21不相连。同理，位于第一显示区101a内的第二像素电路列j22中的部分像素电路与第二数据线g22相连，例如位于第二像素电路列j22中的第二像素电路组105中的像素电路与第二数据线g22相连，而位于第二像素电路列j22中的第一像素电路组103中的像素电路与第二数据线g22不相连。位于第一显示区101a内的第三像素电路列j23中的部分像素电路与第三数据线g23相连，例如位于第三像素电路列j23中的第二像素电路组105中的像素电路与第三数据线g23相连，而位于第三像素电路列j23中的第一像素电路组103中的像素电路与第三数据线g23不相连。位于第一显示区101a内的第四像素电路列j24中的部分像素电路与第四数据线g24相连，例如位于第四像素电路列j24中的第一像素电路组103中的像素电路与第四数据线422相连，而位于第四像素电路列j24中的第二像素电路组105中的像素电路与第四数据线g24不相连。
如图1至图23所示，与第一显示区101a的多个发光单元连接的多个第一像素电路对f1a与第一数据线g21相连，与第一显示区101a的多个发光单元连接的多个第二像素电路对f2a与第四数据线g24相连，与第二显示区101b的多个发光单元连接的多个第一像素电路对f1a与第二数据线g22相连，与第二显示区101b的多个发光单元连接的多个第二像素电路对f2a与第三数据线g23相连。
例如，第一像素电路组103中，第一像素电路对f1a中的两个像素电路与第一数据线g21相连，第二像素电路对f2a中的两个像素电路与第四数据线g24相连。第二像素电路组105中，第一像素电路对f1a中的两个像素电路与第二数据线g22相连，第二像素电路对f2a中的两个像素电路与第三数据线g23相连。
例如，如图1至图23所示，与第一发光单元组102中的第一颜色的发光单元b1和第三颜色的发光单元b3连接的第一像素电路对f1a与第一数据线g21相连，与第一发光单元组102中的第二颜色的发光单元对b2连接的第二像素电路对f2a与第四数据线g24相连。
图30是本申请实施例提供的第三显示区和第一显示区交界处的部分像素电路结构示意图，图31是图30所示位置的数据线连接部所在膜层结构示意图，图32是图30所示位置的数据线所在膜层结构示意图。如图1至图32所示，在第三显示区101c和第一显示区101a的交界处，与至少一个像素电路列组连接的第二数据线g22，第三数据线g23以及第四数据线g24断开以形成第一断口m1，第一数据线g21保持连续，没有断口。也就是，第二数据线g22中位于第一显 示区101a的部分与位于第三显示区101c的部分在第三显示区101c和第一显示区101a交界处不连接。同理，第三数据线g23中位于第一显示区101a的部分与位于第三显示区101c的部分在第三显示区101c和第一显示区101a交界处不连接。第四数据线g24中位于第一显示区101a的部分与位于第三显示区101c的部分在第三显示区101c和第一显示区101a交界处不连接。第二数据线g22位于第三显示区101c的部分靠近第一显示区101a的端点m2通过数据线连接部i连接到第四数据线g24位于第一显示区101a靠近第三显示区101c的端点m3，数据线连接部i穿过第三数据线g23的第一断口m1。这里的第一数据线g21，第二数据线g22，第三数据线g23和第四数据线g24可以指一条连续的数据线，如第一数据线g21为连续的数据线；也可以指与同一列像素电路连接且不连续的数据线，如第二数据线g22，第三数据线g23以及第四数据线g24。由此，与第三子像素电路连接的第二数据线g22和与第一子像素电路连接的第二数据线g22被配置为传输不同的信号；与第三子像素电路连接的第三数据线g23和与第一子像素电路连接的第三数据线g23被配置为传输不同的信号；与第三子像素电路连接的第四数据线g24和与第一子像素电路连接的第四数据线g24被配置为传输不同的信号。
也即是，本申请实施例中虽然将第三显示区和第一显示区中位于同一直线的数据线均称为第二数据线，第三数据线或第四数据线，但是位于不同显示区的第二数据线(第三数据线或第四数据线)被配置为传输不同的信号。
本申请实施例示意性的示出第三显示区中的第二数据线靠近第一显示区的端点通过数据线连接部与第一显示区中的第四数据线靠近第三显示区的端点连接，但不限于此。第三显示区中的第二数据线靠近第一显示区的端点还可以通过数据线连接部与第一显示区中的第三数据线靠近第三显示区的端点连接。
在本申请实施例中，位于第三显示区中的像素电路称为第三子像素电路k3，与位于第一显示区101a中的发光单元连接的像素电路称为第一子像素电路k1，与位于第二显示区101b中的发光单元连接的像素电路称为第二子像素电路k2。
如图30所示，本申请实施例以与第三显示区101c中的第一像素电路列j21连接的多个发光单元包括第一颜色的发光单元和第三颜色的发光单元，与第三显示区101c中的第二像素电路列j22连接的多个发光单元包括第二颜色的发光单元对，与第三显示区101c中的第三像素电路列j23连接的多个发光单元包括第一颜色的发光单元和第三颜色的发光单元，与第三显示区101c中的第四像素 电路列j24连接的多个发光单元包括第二颜色的发光单元对为例。
在本申请实施例中，数据信号从位于第三显示区101c远离第一显示区101a一侧的源极驱动集成电路经数据线传输给第三显示区101c和第一显示区101a中的像素电路，传输给和第一显示区101a中一种颜色发光单元连接的像素电路的数据信号，应与传输给和第三显示区101c中的上述相同颜色发光单元连接的像素电路的数据信号相同。由此，第三显示区101c中同一像素电路列连接至同一数据线，而第一显示区101a中的像素电路对f连接至同一数据线时，容易出现传输至和第三显示区101c中第一颜色的发光单元连接的像素电路的数据信号，与传输至和第一显示区101a中第二颜色的发光单元对连接的像素电路对f的数据信号相同的问题，导致第三显示区101c和第一显示区101a的数据信号不匹配。
示例的，第三显示区101c中，各第三发光单元组109包括一个第一颜色的发光单元b1，一个第二颜色的发光单元对b2以及一个第三颜色的发光单元b3。各第二颜色的发光单元对包括第一发光单元块b21和第二发光单元块b22。第一颜色的发光单元b1和第三颜色的发光单元b3沿平行于数据线延伸方向的方向(列方向Y)排列，第二颜色的发光单元对b2包括的第一发光单元块b21和第二发光单元块b22沿列方向Y排列，第一颜色的发光单元b1和第二颜色的发光单元对b2沿行方向X排列，相邻两个第三发光单元组中第一颜色的发光单元指向第三颜色的发光单元的方向相反。也即是，与第三显示区101c中靠近第一显示区101a的第一行像素电路且位于像素电路列组中的四个像素电路连接的发光单元依次为第一颜色的发光单元b1，第一发光单元块b21，第三颜色的发光单元b3以及第二发光单元块b22。而与上述像素电路列组中的且位于第三显示区101c靠近第一显示区101a的第二行像素电路连接的四个发光单元依次为第三颜色的发光单元b3，第二发光单元块b22，第一颜色发光单元b1以及第一发光单元块b21。
由此，与第一像素电路列和与第三像素电路列的像素电路连接的第一颜色的发光单元和第三颜色的发光单元的排列方式不同，与第二像素电路列和与第四像素电路列的像素电路连接的第一发光单元块b21和第二发光单元块b22的排列方式不同。数据线传输的数据信号与相应颜色的发光单元的排列相关，且第三显示区和第一显示区均应按照上述发光单元排列方式传输匹配的数据信号。
如图1至图32所示，与第一显示区101a中第一像素电路列j21连接的多个发光单元包括交替排列的第一颜色的发光单元b1和第三颜色的发光单元b3，与位于第一显示区101a靠近第三显示区101c的一行且为第一像素电路列j21的像素电路连接的发光单元例如为第三颜色的发光单元b3。第三显示区101c中与第一像素电路列j21连接的多个发光单元包括交替排列的第一颜色的发光单元b1和第三颜色的发光单元b3，与位于第三显示区101c靠近第一显示区101a的一行且为第一像素电路列j21的像素电路连接的发光单元为第一颜色的发光单元b1。由此，第三显示区101c的靠近第一显示区101a的一行像素电路行中且与第一数据线连接的像素电路与第一颜色的发光单元b1连接，第一显示区101a的靠近第三显示区101c的一行像素电路行中且与同一条第一数据线连接的像素电路与第三颜色的发光单元b3连接，该发光单元的排列方式与第一数据线传输的数据信号相匹配，则第一数据线可以在第三显示区101c和第一显示区101a的交界处保持连接，无需在两个显示区交界处断开。
如图1至图32所示，与第一显示区101a中第四像素电路列j24连接的多个第二颜色的发光单元对b2包括交替排列的第一发光单元块b21和第二发光单元块b22，与位于第一显示区101a靠近第三显示区101c的一行且为第四像素电路列j24的像素电路连接的发光单元例如为第二发光单元块b22。第三显示区101c中与第四像素电路列j24连接的多个第二颜色的发光单元对包括交替排列的第一发光单元块b21和第二发光单元块b22，与位于第三显示区101c靠近第一显示区101a的一行且为第四像素电路列j24的像素电路连接的发光单元也为第二发光单元块b22。由此，与第三显示区101c靠近第一显示区101a的一行像素电路行且为第四像素电路列的像素电路连接的发光单元和与第一显示区靠近第三显示区101c的一行像素电路行且为第四像素电路列的像素电路连接的发光单元为同一种发光单元，则与第三显示区101c的第四像素电路列连接的第四数据线的数据信号和与第一显示区101a的第四像素电路列连接的第四数据线的数据信号不匹配，因此，第四数据线在第三显示区101c和第一显示区101a的交界处应断开连接。
如图1至图32所示，第三显示区101c中与第二像素电路列j22连接的多个第二颜色的发光单元对b2包括交替排列的第一发光单元块b21和第二发光单元块b22，且与位于第三显示区101c靠近第一显示区101a的一行且为第二像素电路列j22的像素电路连接的发光单元为第一发光单元块b21。由此，与第一显示 区101a的第四像素电路列连接的第四数据线的数据信号和与第三显示区101c的第二像素电路列连接的第二数据线的数据信号相匹配，则第二数据线中位于第三显示区101c的部分与位于第一显示区101a的部分在两个显示区交界位置处断开连接，且位于第三显示区101c的第二数据线通过数据线连接部与位于第一显示区101a的第四数据线连接，以满足集成电路(IC)在第三显示区101c和第一显示区101a统一的算法处理。
在本申请实施例中，在第三显示区101c和第一显示区101a交界的位置，断开第二数据线，第三数据线以及第四数据线，并通过数据线连接部连接第二数据线位于第三显示区101c的部分靠近第一显示区101a的端点与第四数据线位于第一显示区101a靠近第三显示区101c的端点，从而可以保证从数据线传输至第三显示区101c中发光单元的数据信号与从数据线传输至第一显示区101a中发光单元的数据信号的匹配。
如图30至图32所示，数据线连接部i与多条数据线g2位于不同层。例如，沿垂直于衬底基板的方向，数据线连接部i与电源信号线g6有交叠。由于数据线连接部需要穿过第三数据线的第一断口以及两条电源信号线实现连接第二数据线的端点和第四数据线的端点，因此数据线连接部需要与数据线设置在不同层。
可选的，如图30至图32所示，数据线连接部i与复位电源信号线g1位于同层以方便设计。
如图30至图32所示，第三显示区101c中与第一显示区101a相邻的一行第一像素电路行j1中的且位于第三像素电路列j23和第四像素电路列j24的两个像素电路中的阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间设置有数据线连接部i。
在本申请实施例中，第三显示区101c和第一显示区101a交界处指与第三显示区101c靠近第一显示区101a的一行像素电路行j1中像素电路的第一复位晶体管的第一极与数据写入晶体管的第二极之间的间隔。
例如，第三显示区101c中与第一显示区101a相邻的一行像素电路行j1中，阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第二极之间的在列方向Y的距离为7微米至12微米以在阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间设置数据线连接部i。
在第三显示区101c中的像素电路中，第二连接部h2与第三连接部h3的彼 此靠近的边缘之间的在列方向Y的距离为7微米至12微米，以在第二连接部h2与第三连接部h3之间设置数据线连接部i。在本申请实施例中，第一连接部h1与数据线连接部虽然分别设置在第一显示区，以及第三显示区和第一显示区的交界，但是通过调整像素电路的阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间的空间的距离，可以将第一连接部h1和数据线连接部均设置在像素电路的阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间的预留出的较大的空间，以防止对其他信号产生干扰。
图33是本申请实施例提供的第三显示区和第二显示区的边缘区交界处的部分像素电路结构示意图。参考图33，第二显示区101b内的多个虚设像素电路列包括相邻四列组成的虚设像素电路列组，每个虚设像素电路列组包括沿列方向Y依次排列的第一虚设像素电路列n1，第二虚设像素电路列n2，第三虚设像素电路列n3和第四虚设像素电路列n4，第一虚设像素电路列n1的至少部分虚设像素电路1111，第二虚设像素电路列n2的至少部分虚设像素电路1111，第三虚设像素电路列n3的至少部分虚设像素电路1111以及第四虚设像素电路列n4的至少部分虚设像素电路1111分别与沿列方向Y依次排列的第一数据线g21，第二数据线g22，第三数据线g23和第四数据线g24相连，虚设像素电路1111和第一子像素电路k3的间隔处(例如第二显示区101b的边缘区101b2和第三显示区101c的交界处)，第三数据线g23和第四数据线g24断开以形成第二断口m4。
上述的第一虚设像素电路列n1，第二虚设像素电路列n2，第三虚设像素电路列n3和第四虚设像素电路列n4也可以分别称为第一像素电路列，第二像素电路列，第三像素电路列和第四像素电路列。
如图1至图33所示，与第二发光单元组104中的第一颜色的发光单元b1和第三颜色的发光单元b3连接的像素电路对f可以为第一像素电路对f1a和第二像素电路对f2a之一，与第二发光单元组104中的第二颜色的发光单元对b2连接的像素电路对f可以为第一像素电路对f1a和第二像素电路对f2a的另一个。
可选的，与第二发光单元组104的第一颜色的发光单元b1和第三颜色的发光单元b3连接的像素电路对f可以与第二数据线g22和第三数据线g23之一连接，与第二发光单元组104的第一发光单元块b21和第二发光单元块b22连接的像素电路对f可以与第二数据线g22和第三数据线g23的另一个连接。示例的，与第二发光单元组104的第一颜色的发光单元b1和第三颜色的发光单元b3连 接的像素电路对f可以与第三数据线g23连接，与第二发光单元组104的第一发光单元块b21和第二发光单元块b22连接的像素电路对f可以与第二数据线g22连接。
由于在第三显示区101c和第一显示区101a的交界，第二数据线和第三数据线均断开，与第二发光单元组104连接的像素电路不能被与第一显示区101a相接的第三显示区101c中的数据线输入匹配的数据信号。因此，本申请实施例中采用第二显示区的边缘区和第三显示区101c的交界处连续的第一数据线和第二数据线分别连接与第二发光单元组104的第一发光单元块b21和第二发光单元块b22连接的像素电路对f以及与第二发光单元组104的第一颜色的发光单元b1和第三颜色的发光单元b3连接的像素电路对f，以实现对与第二发光单元组104连接的像素电路输入匹配的数据信号，满足集成电路在第三显示区101c和第二显示区101b统一的算法处理。
第二显示区101b中与第一显示区101a的第三像素电路列j23连接的多个发光单元包括交替排列的第一颜色的发光单元b1和第三颜色的发光单元b3，且与位于第一显示区101a远离第三显示区101c的第一行以及第三像素电路列j23的像素电路连接的发光单元为第三颜色发光单元b3。第三显示区101c中与第一像素电路列j21连接的多个发光单元20包括交替排列的第一颜色的发光单元b1和第三颜色的发光单元b3，与位于第三显示区101c靠近的第二显示区101b一行且连接第一颜色的发光单元b1的像素电路连接的数据线为第一数据线。
第二显示区101b中与第一显示区101a的第二像素电路列j22连接的多个发光单元包括交替排列的第一发光单元块b21和第二发光单元块b22，且与位于第一显示区101a远离第三显示区101c的第一行以及第二像素电路列j22中的像素电路连接的发光单元为第二发光单元块b22。第三显示区101c中与第二像素电路列j22连接的多个发光单元包括交替排列的第一发光单元块b21和第二发光单元块b22，与位于第三显示区101c靠近的第二显示区101b一行且连接第一发光单元块b21的像素电路连接的数据线为第二数据线。由此，第三显示区101c与第二显示区101b的边缘区101b2相接的区域中的第一数据线和第二数据线上的数据信号分别与第一显示区101a中的第三数据线和第二数据线上的数据信号匹配，而第三显示区101c与第二显示区101b的边缘区101b2相接的区域中的第三数据线和第四数据线传输的数据信号与第一显示区101a中的第三数据线和第二数据线上的数据信号不匹配，则第二显示区101b的边缘区101b2和第三显示 区101c的交界处，第一数据线和第二数据线保持连接，而第三数据线和第四数据线断开连接。
如图1至图33所示，显示面板10还包括位于第二显示区101b远离第三显示区101c一侧的周边区101d，位于第二显示区101b的边缘区101b2的第一数据线g21绕过中心区101b1以在周边区101d连接到第一显示区101a的第二数据线g22和第三数据线g23之一，位于第二显示区101b的边缘区101b2的第二数据线g22绕过中心区101b1以在周边区101d连接到第一显示区101a的第二数据线g22和第三数据线g23的另一个。
例如，本申请实施例示意性的示出，位于第二显示区101b的边缘区101b2的第一数据线g21绕过中心区101b1以在周边区101d连接到第一显示区101a的第三数据线g23，位于第二显示区101b的边缘区101b2的第二数据线g22绕过中心区101b1以在周边区101d连接到第一显示区101a的第二数据线g22，从而方便第二显示区和第一显示区中数据线的走线。
如图1至图33所示，本申请另一实施例提供一种显示面板10包括第三显示区101c和第一显示区101a。第三显示区101c包括多个第三发光单元1091和多个第三子像素电路k3，多个第三发光单元1091包括相邻设置的第一发光单元列1091-1和第二发光单元列1091-2，各发光单元列与相应的一列第三子像素电路k3连接。第一显示区101a包括多个第一发光单元1021和多个第一子像素电路k1，多个第一发光单元1021包括相邻设置的第三发光单元列1021-4和第四发光单元列1021-5。第一显示区101a中的各发光单元列与一列第一子像素电路对q1连接，各列第一子像素电路对q1包括相邻两列第一子像素电路k1。
如图1至图33所示，显示面板10还包括沿列方向Y延伸的多条第一子数据线r1，多条第二子数据线r2，多条第三子数据线r3以及多条第四子数据线r4。各第一子数据线r1与各第一发光单元列1091-1连接，各第二子数据线r2与各第二发光单元列1091-2连接，各第三子数据线r3与各第三发光单元列1021-4连接，各第四子数据线r4与各第四发光单元列1021-5连接。
如图1至图33所示，第一发光单元列1091-1和第二发光单元列1091-2的排列方向与第三发光单元列1021-4和第四发光单元列1021-5的排列方向相同，与第一发光单元列1091-1连接的一列第三子像素电路k3和与第三发光单元列1021-4连接的一列第一子像素电路k1位于同一列，第一子数据线r1和第三子数据线r3为沿列方向Y延伸且连续的一条数据线；与第四发光单元列1021-5连接 的两列第一子像素电路k1和与第二发光单元列1091-2连接的一列第三子像素电路k3均位于不同列，第二子数据线r2与第四子数据线r4通过数据线连接部i连接，且数据线连接部i的延伸方向与列方向Y相交。
这里的第一子数据线r1，第二子数据线r2，第三子数据线r3和第四子数据线r4与上述实施例中的第一数据线g21，第二数据线g22，第三数据线g23和第四数据线g24指代的含义不同，这里的第一子数据线r1仅指上述实施例中的第一数据线g21中连接第三显示区中像素电路的数据线，这里的第二子数据线r2指上述实施例中的第二数据线g22中连接第三显示区中像素电路的数据线，这里的第三子数据线r3仅指上述实施例中的第一数据线g21中连接第一显示区中像素电路的数据线，这里的第四子数据线r4仅指上述实施例中的第四数据线g24中连接第一显示区101a中像素电路的数据线。
在第三显示区101c的像素电路和第一显示区101a的像素电路交界的位置，断开第二子数据线r2与第四子数据线r4，并通过数据线连接部i连接第二子数据线r2与第四子数据线r4，从而可以保证从数据线传输至第三显示区101c中发光单元的数据信号与从数据线传输至第一显示区101a中发光单元的数据信号的匹配。
如图1至图33所示，与第二发光单元列1091-2连接的一列第三子像素电路k3和与第三发光单元列1021-4连接的另一列第一子像素电路k1位于同一列。
如图1至图33所示，第三显示区101c还包括相邻设置第五发光单元列1091-3和第六发光单元列1091-4，第一发光单元列1091-1，第二发光单元列1091-2，第五发光单元列1091-3和第六发光单元列1091-4沿行方向X重复排列，第三发光单元列1021-4和第四发光单元列1021-5沿行方向X交替排列。
如图1至图33所示，显示面板10还包括沿列方向Y延伸的多条第五子数据线r5和多条第六子数据线r6，各第五子数据线r5与各第五发光单元列1091-3连接，各第六子数据线r6与各第六发光单元列1091-4连接。
如图1至图33所示，与第五发光单元列1091-3连接的一列第三子像素电路k3和与第四发光单元列1021-5连接的一列第一子像素电路k1位于同一列，与第六发光单元列1091-4连接的一列第三子像素电路k3和与第四发光单元列1021-5连接的另一列第一子像素电路k1位于同一列。第六子数据线r6或第五子数据线r5与第四子数据线r4之间设置有间隔。图29示意性的示出与第六子数据线r6连接的像素电路和与第四子数据线r4连接的像素电路位于同一列，则第 六子数据线r6和第四子数据线r4之间设置有间隔，但不限于此。在第四子数据线r4连接的像素电路与第五子数据线r5连接的像素电路位于同一列时，第四子数据线r4与第五子数据线r5之间设置有间隔。这里的第五子数据线r5仅指上述实施例中的第三数据线g23中连接第三显示区101c中像素电路的数据线，这里的第六子数据线r6指上述实施例中的第四数据线g24中连接第三显示区101c中像素电路的数据线。
图34是本申请实施例的另一示例提供的显示面板中的第三显示区和第一显示区的部分平面图。图34所示示例与图29所示示例不同之处在于像素的排列，图29所示示例中像素排列为GGRB排列，图34所示示例中像素排列为realRGB排列。如图34所示，位于第三显示区101c中的每六个RGB发光单元为一个重复周期。与第三显示区101c的第一列R发光单元连接的数据线g2和与第一显示区101a的第一列R发光单元连接的数据线g2为同一条连续的数据线；与第三显示区101c第二列G发光单元连接的数据线g2和与第一显示区101a的第二列R发光单元连接的数据线g2之间具有间隔；与第三显示区101c第二列G发光单元连接的数据线g2通过数据线连接部i和与第一显示区101a的第三列G(或第四列G)发光单元连接的数据线g2连接；与第三显示区101c第三列B发光单元连接的数据线g2和与第一显示区101a的第三列G发光单元连接的数据线g2之间具有间隔；与第三显示区101c第三列B发光单元连接的数据线g2通过数据线连接部i和与第一显示区101a的第五列B(或第六列B)发光单元连接的数据线g2连接；与第三显示区101c第四列G发光单元连接的数据线g2和与第一显示区101a的第四列G发光单元连接的数据线g2之间具有间隔；与第三显示区101c第五列R发光单元连接的数据线g2和与第一显示区101a的第五列B发光单元连接的数据线g2之间具有间隔；与第三显示区101c第六列G发光单元连接的数据线g2和与第一显示区101a的第六列B发光单元连接的数据线g2之间具有间隔。本申请实施例不限于上述连接，只要第三显示区101c中的一个R发光单元与第一显示区101a中的一个R发光单元连接至同一数据线，第三显示区101c中的一个B发光单元与第一显示区101a中的一个B发光单元连接至同一数据线，第三显示区101c中的一个G发光单元与第一显示区101a中的一个G发光单元连接至同一数据线即可。
如图1至图34所示，第三显示区101c包括沿行方向X和列方向Y交替排列的多个第一子发光单元组t1和多个第二子发光单元组t2，第一子发光单元组 t1包括第一发光单元列1091-1和第二发光单元列1091-2中的发光单元，第二子发光单元组t2包括第五发光单元列1091-3和第六发光单元列1091-4中的发光单元，第一显示区101a包括多个第三子发光单元组t3。
如图1至图34所示，各子发光单元组包括一个第一颜色的发光单元R，一个第二颜色的发光单元对G1和G2以及一个第三颜色的发光单元B，第一颜色的发光单元R和第三颜色的发光单元B沿列方向Y排列，第二颜色的发光单元对G1和G2包括沿列方向Y排列的两个第二颜色的发光单元。第一颜色的发光单元R和第二颜色的发光单元对G1和G2沿行方向X排列，且第一子发光单元组t1中第一颜色的发光单元R和第三颜色的发光单元B的排列方向与第二子发光单元组t2中第一颜色的发光单元R和第三颜色的发光单元B的排列方向相反。第一子发光单元组t1中各发光单元的相对位置分布与第三子发光单元组t3中各发光单元的相对位置分布相同。本申请实施例示意性的以第一颜色的发光单元为红色发光单元，第二颜色的发光单元对为绿色发光单元对，且第三颜色的发光单元为蓝色发光单元为例，但不限于此。例如，第一颜色的发光单元可以为蓝色发光单元，第二颜色的发光单元对为绿色发光单元对且第三颜色的发光单元可以为红色发光单元。例如，第一颜色的发光单元为绿色发光单元，第二颜色的发光单元对为红色发光单元对，且第三颜色的发光单元为蓝色发光单元。
如图1至图34所示，第一显示区101a还包括多个第二子像素电路对q2，第二显示区101b包括多个第二发光单元1041，多个第二发光单元1041包括相邻设置的第七发光单元列1041-1和第八发光单元列1041-2。第一发光单元列1091-1和第二发光单元列1091-2的排列方向与第七发光单元列1041-1和第八发光单元列1041-2的排列方向相同，第二显示区101b中的各发光单元列与一列第二子像素电路对q2连接，各列第二子像素电路对q2包括相邻两列第二子像素电路对q2。
如图1至图34所示，显示面板10还包括沿列方向Y延伸的多条第七子数据线r7和多条第八子数据线r8，各第七子数据线r7与各第七发光单元列1041-1连接，各第八子数据线r8与各第八发光单元列1041-2连接。
如图1至图34所示，第七子数据线r7和第八子数据线r8的至少之一设置在第三子数据线r3和第四子数据线r4之间。这里的第七子数据线r7仅指上述实施例中的第二数据线g22中连接第一显示区101a中像素电路的数据线，这里的第八子数据线r8指上述实施例中的第三数据线g23中连接第一显示区101a 中像素电路的数据线。
如图1至图34所示，第七子数据线r7和第八子数据线r8均设置在第三子数据线r3和第四子数据线r4之间，且第八子数据线r8与第五子数据线r5之间设置有间隔以设置数据线连接部i。
例如，第八子数据线r8与第五子数据线r5数据线在第三显示区101c的像素电路和第一显示区101a的像素电路之间间隔位置处有断口，数据线连接部i设置在断口处。
如图1至图34所示，多个第二子像素电路对q2被配置为与多个第四子发光单元组t4连接，各第四子发光单元组t4中各发光单元的相对位置分布与第三子发光单元组t3中各发光单元的相对位置分布相同，与第三子发光单元组t3连接的第一子像素电路对q1和与第四子发光单元组t4连接的第二子像素电路对q2沿行方向X和列方向Y交替排列。
如图1至图34所示，第二显示区101b包括中心区101b1以及围绕中心区101b1的边缘区101b2，边缘区101b2包括沿行方向X和列方向Y排列的多个虚设像素电路以形成多个虚设像素电路列u1和多个虚设像素电路行。
如图1至图34所示，第二显示区101b内的多个虚设像素电路列u1包括相邻四列组成的虚设像素电路列组u11，每个虚设像素电路列组u11包括沿行方向X依次排列的第一虚设像素电路列n1，第二虚设像素电路列n2，第三虚设像素电路列n3和第四虚设像素电路列n4。
如图1至图34所示，显示面板10还包括第一虚设数据线v1，第二虚设数据线v2，第三虚设数据线v3和第四虚设数据线v4，第一虚设数据线v1与第一虚设像素电路列n1连接，第二虚设数据线v2与第二虚设像素电路列n2连接，第三虚设数据线v3与第三虚设像素电路列n3连接，且第四虚设数据线v4与第四虚设像素电路列n4连接。
如图1至图34所示，与第一发光单元列1091-1连接的一列第三子像素电路k3和第一虚设像素电路列n1位于同一列，与第二发光单元列1091-2连接的一列第三子像素电路k3和第二虚设像素电路列n2位于同一列，与第五发光单元列1091-3连接的一列第三子像素电路k3与第三虚设像素电路列n3位于同一列，与第六发光单元列1091-4连接的一列第三子像素电路k3与第四虚设像素电路列n4位于同一列。与第一子发光单元组t1连接的两条数据线与相应的两条虚设数据线为连续的两条数据线，或者与第二子发光单元组t2连接的两条数据线与相 应的两条虚设数据线为连续的两条数据线。
如图1至图34所示，显示面板10还包括位于第二显示区101b远离第三显示区101c一侧的周边区101d，与第一子发光单元组t1或第二子发光单元组t2连接的两条虚设数据线绕过中心区101b1以在周边区101d分别连接第七子数据线r7和第八子数据线r8。
参考图33，第一虚设数据线v1和第一子数据线r1为一条连续的数据线，第二虚设数据线v2和第二子数据线r2为一条连续的数据线，第三虚设数据线v3和第五子数据线r5之间设置有间隔，第四虚设数据线v4和第六子数据线r6之间设置有间隔。
如图1至图34所示，第一虚设数据线v1绕过中心区101b1以在周边区101d连接第七子数据线r7，第二虚设数据线v2绕过中心区101b1以在周边区101d连接第八数据线r8。
图35是本申请实施例提供的位于第三显示区的发光单元组的第一电极的示意图。图36是本申请实施例提供的位于第一显示区非边缘的发光单元组的第一电极的示意图。图37是本申请实施例提供的位于第二显示区的发光单元组的第一电极的示意图。如图1至图37所示，各发光单元的第一电极a1包括主体图案a11以及连接图案a12，主体电极a11的形状与各发光单元的有效发光区的形状基本相同，连接图案a12被配置为通过与第五连接部h5以与像素电路的第一发光控制晶体管T6的第二极电连接。位于显示区的各发光单元组包括多个不同颜色的发光单元，例如，各发光单元组包括一个第一颜色的发光单元b1，第二颜色的发光单元对b2以及第三颜色的发光单元b3。
在本申请实施例中，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的一种颜色的发光单元的主体图案的面积大于位于第三显示区101c的且与上述一种颜色的发光单元颜色相同的发光单元的主体图案的面积。各颜色发光单元的主体图案的面积与其有效发光区的面积相关，本申请实施例中，通过将位于第一显示区的非边缘区域和第二显示区的至少之一中的一种颜色发光单元的主体图案的面积设置为大于位于第三显示区的且与上述一种颜色发光单元颜色相同的发光单元的主体图案的面积，可以使得位于第一显示区的非边缘区域和第二显示区的至少之一中的一种颜色发光单元的有效发光区的面积大于位于第三显示区的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积。
本申请实施例中，由于第一显示区101a和第二显示区101b的发光单元组的密度均小于第三显示区的发光单元组的密度，因此将第一显示区101a和第二显示区101b的至少之一的发光单元中主体图案的面积设计的大于第三显示区的发光单元中主体图案的面积，可以使位于第一显示区的非边缘区域和第二显示区的至少之一中的一种颜色发光单元的有效发光区的面积大于位于第三显示区的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积。由此可以在保证发光单元发光材料寿命的基础上增加第一显示区和第二显示区至少之一的亮度，实现更加均匀的全面屏视觉显示效果。
本申请实施例示意性的示出位于第一显示区101a的非边缘区域和第二显示区101b中，一种颜色发光单元的主体图案的面积大于位于第三显示区101c的且与上述一种颜色发光单元颜色相同的发光单元的主体图案的面积以使位于第一显示区的非边缘区域和第二显示区的一种颜色发光单元的有效发光区的面积设计为大于位于第三显示区的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积，由此，可以在保证发光单元发光材料寿命的基础上增加第一显示区和第二显示区的亮度，实现更加均匀的全面屏视觉显示效果。
例如，在本申请实施例的一示例中，第三显示区101c，第一显示区101a和第二显示区101b中的各发光单元均与一个像素电路连接，即第一显示区和第二显示区中各发光单元可以不与像素电路对f连接，而仅是与一个像素电路连接。此时，第一显示区101a和第二显示区101b的发光单元组的密度均小于第三显示区的发光单元组的密度，通过将第一显示区101a和第二显示区101b的至少之一的发光单元中主体图案的面积设置为大于第三显示区101c的发光单元中主体图案的面积以使位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的一种颜色发光单元的有效发光区的面积设计为大于位于第三显示区101c的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积，可以尽量均匀各显示区的显示效果。
例如，在本申请实施例的另一示例中，各像素电路组包括多个像素电路，第一显示区中的第一像素电路组103和第二像素电路组105至少之一包括多个像素电路对f，各像素电路对f包括的两个像素电路被配置为与同一个发光单元的第一电极a1电连接。例如，第一显示区101a中的第一像素电路组103和第二像素电路组105均包括多个像素电路对f，第一像素电路组103中的各像素电路对f与第一发光单元组102中的各发光单元连接，第二像素电路组105中的各像 素电路对f与第二发光单元组104中的各发光单元连接。第一显示区101a和第二显示区101b的发光单元组的密度均小于第三显示区101c的发光单元组的密度，将与第一显示区101a和第二显示区101b的发光单元连接的像素电路设计为像素电路对f的方案，以及将第一显示区101a和第二显示区101b的发光单元中主体图案的面积设置为大于第三显示区101c的发光单元中主体图案的面积的方案结合，可以在保证发光单元的发光材料寿命的基础上，将使第一显示区101a和第二显示区101b的发光单元的电流和亮度增加到一个像素电路驱动情况下的1.8到2倍，解决了第一显示区101a和第二显示区101b中电流和亮度偏小的问题，实现更加均匀的全面屏的视觉显示效果。
如图1至图37所示，各发光单元组包括第一颜色的发光单元b1，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第一颜色的发光单元的主体图案b1-a11的面积与位于第三显示区101c的各第一颜色的发光单元的主体图案b1-a11的面积比为1.5至2.5。例如，各发光单元组包括第一颜色的发光单元b1，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第一颜色的发光单元的主体图案b1-a11的面积与位于第三显示区101c的各第一颜色的发光单元的主体图案b1-a11的面积比为1.9至2.1。
可选的，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第一颜色的发光单元b1的有效发光区的面积与位于第三显示区101c的各第一颜色的发光单元b1的有效发光区的面积比为2。
如图1至图37所示，位于各显示区的第一颜色的发光单元b1的第一电极a1的主体图案b1-a11和有效发光区的形状均为六边形。当然，参考图9，位于各显示区的第一颜色的发光单元的主体图案(例如图9中第一主体图案1021-1)有效发光区的形状，以及虚设电极图案1062的第二主体图案1061-1均为椭圆形。本申请实施例对各显示区的第一颜色的发光单元的第一电极a1的主体图案的形状不做限定。并且，位于第一显示区101a的非边缘的第一颜色的发光单元的连接图案b1-a12的面积可以大于位于第三显示区101c的第一颜色的发光单元的连接图案b1-a12的面积以实现与像素电路对f的连接。
可选的，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第二颜色的发光单元对的主体图案b2-a11的面积与位于第三显示区101c的各第二颜色的发光单元对的主体图案b2-a11的面积比为1.5至2.5。例如，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第二 颜色的发光单元对的主体图案b2-a11的面积与位于第三显示区101c的各第二颜色的发光单元对的主体图案b2-a11的面积比为1.9至2.1。
可选的，位于第一显示区101a的非边缘区域和第二显示区101b的各第二颜色的发光单元对b2的有效发光区的面积与位于第三显示区101c的各第二颜色的发光单元对b2的有效发光区的面积比为2。
可选的，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第一发光单元块的主体图案b21-a11的面积与位于第三显示区101c的各第一发光单元块的主体图案b21-a11的面积比为1.5至2.5。例如，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第二发光单元块的主体图案b22-a11的面积与位于第三显示区101c的各第二发光单元块的主体图案b22-a11的面积比为1.5至2.5。例如，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第一发光单元块的主体图案b21-a11的面积与位于第三显示区101c的各第一发光单元块的主体图案b21-a11的面积比为1.9至2.1。例如，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第二发光单元块的主体图案b22-a11的面积与位于第三显示区101c的各第二发光单元块的主体图案b22-a11的面积比为1.9至2.1。
可选的，位于第一显示区101a的非边缘区域的各第一发光单元块的连接图案b21-a12的面积大于位于第三显示区101c的各第一发光单元块的连接图案b21-a12的面积。位于第一显示区101a的非边缘区域的各第二发光单元块的连接图案2b22-a12的面积大于位于第三显示区101c的各第二发光单元块的连接图案2b22-a12的面积以方便与像素电路对f连接。
位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第三颜色的发光单元的主体图案b3-a11的面积与位于第三显示区101c的各第三颜色的发光单元的主体图案b3-a11的面积比为1.5至2.5。例如，位于第一显示区101a的非边缘区域和第二显示区101b的至少之一中的各第三颜色的发光单元的主体图案b3-a11的面积与位于第三显示区101c的各第三颜色的发光单元的主体图案b3-a11的面积比为1.9至2.1。
例如，位于第一显示区101a的非边缘区域和第二显示区101b的各第三颜色的发光单元的主体图案b3-a11的面积与位于第三显示区101c的各第三颜色的发光单元的主体图案b3-a11的面积比为2。例如，位于第一显示区101a的非边缘区域和第二显示区101b的各第三颜色的发光单元b3的有效发光区的面积与 位于第三显示区101c的各第三颜色的发光单元b3的有效发光区的面积比为2。
例如，位于第一显示区101a的非边缘区域的各第三颜色的发光单元的连接图案b3-a12的面积大于位于第三显示区101c的各第三颜色的发光单元的连接图案b3-a12的面积以实现与像素电路对f的连接。
各显示区的第三颜色的发光单元的主体图案和有效发光区的形状均为六边形。当然，位于各显示区的第三颜色的发光单元的主体图案和有效发光区的形状均为椭圆形。本申请实施例对各显示区的第三颜色的发光单元的第一电极a1的主体图案的形状不做限定。本申请实施例中，为了简化描述，将发光单元中第一电极的主体图案称为发光单元的主体图案，将发光单元中第一电极的连接图案称为发光单元的连接图案。
如图36和图37所示，第一显示区101a的发光单元组的发光单元的第一电极a1直接与像素电路对f连接，则第一显示区101a的发光单元的连接图案的面积较大，而第二显示区的发光单元组的发光单元的第一电极a1通过第一连接走线或第二连接走线与第一显示区的像素电路对f连接，则第二显示区的发光单元的连接图案的面积可以设置的较小。
图38是本申请实施例提供的第一显示区的与第三显示区交界的两行发光单元组中的各发光单元的第一电极的示意图。如图1至图38所示，第一显示区101a的与第三显示区101c在列方向Y上相邻的一行发光单元组中的各第一颜色的发光单元的主体图案b1-a11的形状和面积与位于第三显示区101c的各第一颜色的发光单元的主体图案的b1-a11形状和面积均大致相同。本申请实施例将第一显示区的与第三显示区在列方向Y上彼此相邻的两行发光单元组中的各第一颜色发光单元的主体图案的形状和面积设置为均大致相同。即位于第一显示区边缘的第一颜色的发光单元的主体图案的面积与位于第一显示区非边缘区域的第一颜色的发光单元的主体图案的面积设计为不同，可以在将第一显示区大部分第一颜色的发光单元的亮度增加以均匀全面屏显示效果的同时，防止两行发光单元的主体图案在空间上出现冲突。
可选的，第一显示区101a的与第三显示区101c在行方向X上相邻的一行发光单元组中的各第二颜色的发光单元对的主体图案b2-a11的面积与位于第三显示区101c的各第二颜色的发光单元对的主体图案b2-a11的面积比为0.9至1.1。本申请实施例将第一显示区的与第三显示区在列方向Y上彼此相邻的两行发光单元组中的各第二颜色的发光单元的主体图案的面积设置为大致相同，即 位于第一显示区边缘的第二颜色的发光单元的主体图案的面积与位于第一显示区非边缘区域的第二颜色的发光单元的主体图案的面积设计为不同，可以在将第一显示区大部分第二颜色的发光单元的亮度增加以均匀全面屏显示效果的同时，防止两行发光单元的主体图案在空间上出现冲突。
如图1至图38所示，第三显示区101c内的第二颜色的发光单元对b2包括的两个第二颜色的发光单元的主体图案的形状，与第一显示区101a中和第三显示区101c在行方向X上相邻的一行发光单元组的各第二颜色的发光单元对b2的两个主体图案的形状不同。
本申请实施例中，位于第一显示区非边缘区域中的相邻两个发光单元之间的像素限定层的间隙(PDL gap)的尺寸与位于第一显示区边缘区域中的相邻两个发光单元之间的PDL gap的尺寸大致相同，以使得第一显示区显示图像光的均一性。
如图1至图38所示，第三显示区101c内的第二颜色的像素单元对b2包括的两个第二颜色的像素单元的主体图案的形状均为五边形。或者，第三显示区101c内的第二颜色的像素单元对b2包括的两个第二颜色的像素单元的主体图案的形状均为椭圆形。本申请实施例对该第二颜色的像素单元的第一电极a1的主体图案的形状不做限定。
在第三显示区101c内的第二颜色的像素单元对b2包括的两个第二颜色的像素单元的主体图案的形状均为五边形的情况下，参考图38，各五边形包括沿行方向X延伸的一条第一边1，沿列方向Y延伸的两条第二边2以及与两条第二边2连接的两条第三边3，两条第三边3交叉形成尖角。两个第二颜色的发光单元的主体图案的两个尖角彼此靠近。第一显示区101a的与第三显示区101c在列方向Y上相邻的一行发光单元组的各第二颜色的发光单元对b2的各主体图案2021包括沿行方向X延伸的一条第四边4，沿列方向Y延伸的两条第五边5，与两条第五边5连接的两条第六边6以及连接两条第六边6的第七边7，两个第二颜色子像素的主体图案的两条第七边7彼此靠近。
如图35至图38所示，第三显示区101c的第二颜色的发光单元的主体图案的第二边2的长度小于第一显示区101a边缘的第二颜色的发光单元的主体图案的第五边5的长度，以保证第三显示区101c的第二颜色的发光单元的主体图案的面积与第一显示区边缘的第二颜色的发光单元的主体图案的面积大致相等。
例如，如图35至图38所示，在第一显示区101a的边缘的第二颜色的发光 单元的主体图案的面积设置为与第三显示区101c的第二颜色的发光单元的主体图案的面积相同时，为了保证第一显示区101a边缘的第二颜色的发光单元和第一颜色的发光单元(或第三颜色的发光单元)之间的PDL gap，与第一显示区101a非边缘区域的第二颜色的发光单元与第一颜色的发光单元(或第三颜色的发光单元)之间的PDL gap一致，第一显示区101a的与第三显示区101c在行方向X上相邻的一行发光单元组中的各第二颜色的发光单元对的两个主体图案的中心连线与第三显示区的各第二颜色的发光单元对的两个主体图案的中心连线不平行。
在第一显示区101a的边缘的第二颜色的发光单元的主体图案的面积设置为与第三显示区101c的第二颜色的发光单元的主体图案的面积相同时，为了保证第一显示区101a边缘的第二颜色的发光单元和第一颜色的发光单元(或第三颜色的发光单元)之间的PDL gap，与第一显示区101a非边缘区域的第二颜色的发光单元和第一颜色的发光单元(或第三颜色发光单元)之间的PDL gap一致，则位于第一显示区101a边缘的第二颜色的发光单元的主体图案的形状如果为包括尖角的五边形，则会与第一颜色的发光单元(或第三颜色的发光单元)的连接图案在空间上存在冲突。因此第一显示区边缘的第二颜色的发光单元的主体图案的形状不再包括尖角。此时，为了保证第一显示区边缘的第二颜色的发光单元的主体图案的面积与第三显示区的第二颜色的发光单元的主体图案的面积大致相同，则需要对第一显示区边缘的第二颜色的发光单元的主体图案形状进行补偿，即增加两条第六边6以及连接两条第六边6的第七边7，从而在保证第一显示区边缘的第二颜色的发光单元的主体图案在空间上没有冲突的情况下，实现其面积与第三显示区的第二颜色的发光单元的面积相等。
如图1至图38所示，第一显示区101a中与第三显示区101c在列方向Y上的相邻的一行发光单元组中的各第三颜色的发光单元的主体图案b3-a11的形状和面积与位于第三显示区101c的各第三颜色的发光单元的主体图案b3-a11的形状和面积均大致相同。本申请实施例将第一显示区的与第三显示区在列方向Y上彼此相邻的两行发光单元组中的各第三颜色的发光单元的主体图案的形状和面积设置为均大致相同，即位于第一显示区边缘的第三颜色的发光单元的主体图案的面积与位于第一显示区非边缘区域的第三颜色的发光单元的主体图案的面积设计为不同，可以在将第一显示区大部分第三颜色的发光单元的亮度增加以均匀全面屏显示效果的同时，防止两行发光单元的主体图案在空间上出现冲 突。
图39是本申请实施例提供的第一显示区的与第三显示区交界的两列发光单元组中的各发光单元的第一电极的示意图。如图39所示，第一显示区101a的与第三显示区101c在行方向X上相邻的一列发光单元组中，第二颜色的发光单元对b2位于第一颜色的发光单元b1和第三颜色的发光单元b3靠近第三显示区101c的一侧，该列发光单元组中的各第二颜色的发光单元对的主体图案b2-a11的面积和形状与位于第三显示区101c的各第二颜色的发光单元对的主体图案b2-a11的面积和形状均大致相同。本申请实施例将第一显示区的与第三显示区在行方向X上彼此相邻的两列发光单元组中的各第二颜色的发光单元对的主体图案的形状和面积设置为均大致相同，即位于第一显示区边缘的第二颜色的发光单元对的主体图案的面积与位于第一显示区非边缘区域的第二颜色的发光单元对的主体图案的面积设计为不同，可以在将第一显示区大部分第二颜色的发光单元对的亮度增加以均匀全面屏显示效果的同时，防止两列发光单元的主体图案在空间上出现冲突。
沿列方向Y排列的相邻两个第一发光单元组102之间设置有第二像素电路组105，由此，沿列方向Y排列的相邻的两个第一发光单元组102之间的间隔处不设置发光单元组。第三显示区101c在行方向X靠近第一显示区101a的一列多个第三发光单元组中的相邻两个第三发光单元组之间设置有间隔，该间隔区域包括不与发光单元组连接的一个第三像素电路组。且沿行方向X，该第三像素电路组和与第三显示区101c紧邻的一列第一发光单元组102中的发光单元组位于同一直线上，由此，可以平衡在行方向X上第三显示区与第一显示区的亮度分布。
可选的，第一显示区101a中与第三显示区101c在行方向X上相邻的一列发光单元组中，各第一颜色的发光单元的主体图案b1-a11的面积与位于第三显示区101c的各第一颜色的发光单元的主体图案b1-a11的面积比为1.5至2.5。例如，第一显示区101a中与第三显示区101c在行方向X上相邻的一列发光单元组中，各第一颜色的发光单元b1的有效发光区的面积与位于第三显示区101c的各第一颜色的发光单元b1的有效发光区的面积比为2。
在本申请实施例中，在保证第一显示区的与第三显示区在行方向X上相邻的一列发光单元组中的发光单元的主体图案在空间上不发生冲突的情况下，位于第一显示区边缘的第一颜色的发光单元的主体图案的形状和面积与位于第一 显示区非边缘区域的第一颜色的发光单元的主体图案的形状和面积均大致相同，可以在将第一显示区大部分第一颜色的发光单元的亮度增加以均匀全面屏显示效果的同时，防止两列发光单元的主体图案在空间上出现冲突。
可选的，第一显示区101a的与第三显示区101c在行方向X上相邻的一列发光单元组中，各第三颜色的发光单元的主体图案b3-a11的面积与位于第三显示区101c的各第三颜色的发光单元的主体图案b3-a11的面积比为1.5至2.5。例如，第一显示区101a的与第三显示区101c在行方向X上相邻的一列发光单元组中，各第三颜色的发光单元的主体图案b3-a11的面积与位于第三显示区101c的各第三颜色的发光单元的主体图案b3-a11的面积比为1.9至2.1。
可选的，第一显示区101a的与第三显示区101c在行方向X上相邻的一列发光单元组中，各第三颜色的发光单元b3的有效发光区的面积与位于第三显示区101c的各第三颜色的发光单元b3的有效发光区的面积比为2。在本申请实施例中，在保证第一显示区的与第三显示区在行方向X上相邻的一列发光单元组中的发光单元的主体图案在空间上不发生冲突的情况下，位于第一显示区边缘的第三颜色的发光单元的主体图案的形状和面积与位于第一显示区非边缘区域的第三颜色的发光单元的主体图案的形状和面积均大致相同，可以在将第一显示区大部分第三颜色的发光单元的亮度增加以均匀全面屏显示效果的同时，防止两列发光单元的主体图案在空间上出现冲突。
图40是图3沿A1至A2方向的截面图。图41是图7沿B1至B2方向的截面图。结合图40和图41可以看出，该显示面板10可以包括第四绝缘层和第五绝缘层。该第四绝缘层位于像素电路膜层的一侧，多个第一连接走线107位于第四绝缘层远离像素电路膜层的一侧，第五绝缘层位于多个第一连接走线107远离第四绝缘层的一侧。各个发光单元的第一电极a1位于第五绝缘层远离多个第一连接走线107的一侧，像素界定层a4位于第一电极a1远离第五绝缘层的一侧。
其中，上述像素电路膜层即为像素电路所包括的膜层，例如，参考图40和图41，该像素电路膜层包括沿远离衬底基板101的一侧依次层叠的有源半导体层01，栅极绝缘层，第一导电层02，第一绝缘层，第二导电层03，第二绝缘层，源漏极金属层04以及第三绝缘层。
其中，图41中的第一导电层02自左至右第三个方块和第五个方块均为电容C的第二极CC2，第四个方块为发光控制信号线。第二导电层03自左至右第 二个方块和第五个方块为遮挡块，第三个方块和第四个方块为电容C的第一极CC1。源漏极金属层04自左至右第一个方块，第四个方块，第七个方块，第十个方块，第十三个方块，第十六个的方块，第十九个方块，第二十一个方块，以及第二十四个方块均为输出电压信号VDD的信号线。源漏极金属层04自左至右第五个方块，第八个方块，第十一个方块，第十四个方块，第十七个方块，第二十个方块，第二十二个方块，以及第二十五个方块均为数据信号Data。
图42中的第一导电层02自左至右第二个方块和第六个方块为发光控制信号线，第三个方块为复位控制信号线，第五个方块为电容C的第二极CC2。第二导电层03自左至右第二个方块为遮挡块，第三个方块为连接块，第四个方块为复位信号Vinit，第五个方块为电容C的第一极CC1。源漏极金属层04自左至右第三个方块，第六个方块，第十一个方块，第十四个方块为数据信号Data。源漏金属层04自左至右第四个方块，第七个方块，第十个方块，以及第十三个方块为输出电压信号VDD的信号线。
综上所述，本申请实施例提供了一种显示面板，该显示面板中位于第一显示区的多个第二像素电路组包括远离第二显示区的第一类第二像素电路组，以及靠近该第二显示区的第二类第二像素电路组。其中，第一类第二像素电路组通过第一连接走线与位于第二显示区且远离第一显示区的第一类第二发光单元组连接，第二类第二像素电路组通过第二连接走线与位于第二显示区且靠近第一显示区的第二类第二发光单元组连接。由于本申请实施例提供的方案还可以通过与第一连接走线位于异层的第二连接走线为第二类第二发光单元组提供驱动信号，因此可以在不增加第一连接走线的前提下，增加第二显示区所能够设置的第二发光单元组的数量，进而保证显示面板中第二显示区的显示效果。
图42是本申请实施例提供的一种显示装置的结构示意图。参考图42可以看出，该显示装置可以包括：供电组件20以及上述实施例提供的显示面板10。该供电组件20可以用于为显示面板10供电。其中，该显示装置可以为曲面显示装置。
可选的，该显示装置可以为有机发光二极管(organic light-emitting diode，OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能以及指纹识别功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (25)

  1. 一种显示面板，其特征在于，所述显示面板包括：
    衬底基板，所述衬底基板具有相邻的第一显示区和第二显示区；
    多个第一发光单元组，所述多个第一发光单元组位于所述第一显示区；
    多个第一像素电路组，所述多个第一像素电路组位于所述第一显示区，所述第一像素电路组与一个所述第一发光单元组连接；
    多个第二发光单元组，所述多个第二发光单元组位于所述第二显示区，所述多个第二发光单元组包括：至少一个第一类第二发光单元组和至少一个第二类第二发光单元组，所述至少一个第二类第二发光单元组相对于所述至少一个第一类第二发光单元组靠近所述第一显示区；
    多个第二像素电路组，所述多个第二像素电路组位于所述第一显示区，所述多个像素电路组包括：至少一个第一类第二像素电路组和至少一个第二类第二像素电路组，所述至少一个第二类第二像素电路组相对于所述至少一个第一类第二像素电路组靠近所述第二显示区；
    多个虚设电极图案组，位于所述第一显示区，所述多个虚设电极图案组包括：至少一个第一图案组和至少一个第二图案组，所述至少一个第二图案组相对于所述至少一个第一图案组靠近所述第二显示区；
    多个第一连接走线，所述多个第一连接走线与所述多个虚设电极图案组位于异层，所述第一连接走线的一端与一个所述第一类第二发光单元组连接，另一端通过一个所述第一图案组与一个所述第一类第二像素电路组连接；
    以及，多个第二连接走线，所述多个第二连接走线与所述多个第一连接走线位于异层，所述第二连接走线的一端与一个所述第二类第二发光单元组连接，另一端通过一个所述第二图案组与一个所述第二类第二像素电路组连接。
  2. 根据权利要求1所述的显示面板，其特征在于，所述虚设电极图案组在所述衬底基板上的正投影，与至少一个所述第二像素电路组在所述衬底基板上的正投影至少部分重叠，且所述虚设电极图案组在所述衬底基板上的正投影与任一所述第一发光单元组在所述衬底基板上的正投影不重叠。
  3. 根据权利要求1或2所述的显示面板，其特征在于，每个所述第一发光单 元组和每个所述第二发光单元组均包括多个发光单元，所述发光单元包括沿远离所述衬底基板的方向依次层叠的第一电极，发光层以及第二电极；
    所述虚设电极图案组包括多个虚设电极图案，一个所述虚设电极图案组包括的所述多个虚设电极图案的个数与一个发光单元组包括的所述多个发光单元的个数相同，且所述虚设电极图案与所述第一电极位于同层。
  4. 根据权利要求3所述的显示面板，其特征在于，所述显示面板还包括：位于所述第一电极和所述发光层之间的像素界定层；
    所述像素界定层具有多个开口，一个所述开口用于露出一个所述发光单元的第一电极，且多个开口在所述衬底基板上的正投影与任一所述虚设电极图案在所述衬底基板上的正投影不重叠。
  5. 根据权利要求3或4所述的显示面板，其特征在于，一个所述虚设电极图案组中的多个所述虚设电极图案与一个所述第一发光单元组中的多个第一发光单元一一对应，且所述虚设电极图案与对应的所述第一发光单元中的第一电极的形状和面积相同。
  6. 根据权利要求5所述的显示面板，其特征在于，一个所述第一发光单元组包括：一个第一颜色的第一发光单元，两个第二颜色的第一发光单元，以及一个第三颜色的第一发光单元；
    一个所述第二发光单元组包括：一个第一颜色的第二发光单元，两个第二颜色的第二发光单元，以及一个第三颜色的第二发光单元。
  7. 根据权利要求6所述的显示面板，其特征在于，所述第一显示区中沿行方向相邻的两个第一颜色的第一发光单元的中心的距离，与所述第二显示区中沿所述行方向相邻的两个第一颜色的第二发光单元的中心的距离相等；
    所述第一显示区中沿行方向相邻的两个第二颜色的第一发光单元的中心的距离，与所述第二显示区中沿所述行方向相邻的两个第二颜色的第二发光单元的中心的距离相等；
    所述第一显示区中沿行方向相邻的两个第三颜色的第一发光单元的中心的 距离，与所述第二显示区中沿所述行方向相邻的两个第三颜色的第二发光单元的中心的距离相等。
  8. 根据权利要求6所述的显示面板，其特征在于，所述第一显示区中露出第一颜色的第一发光单元的开口在衬底基板上的正投影的面积，与所述第二显示区中露出第一颜色的第二发光单元的开口在衬底基板上的正投影的面积相等，且所述第一显示区中第一颜色的第一发光单元的第一电极在衬底基板上的正投影的面积，大于所述第二显示区中第一颜色的第二发光单元的第一电极在衬底基板上的正投影的面积；
    所述第一显示区中露出第二颜色的第一发光单元的开口在衬底基板上的正投影的面积，与所述第二显示区中露出第二颜色的第二发光单元的开口在衬底基板上的正投影的面积相等，且所述第一显示区中第二颜色的第一发光单元的第一电极在衬底基板上的正投影的面积，大于所述第二显示区中第二颜色的第二发光单元的第一电极在衬底基板上的正投影的面积；
    所述第一显示区中露出第三颜色的第一发光单元的开口在衬底基板上的正投影的面积，与所述第二显示区中露出第三颜色的第二发光单元的开口在衬底基板上的正投影的面积相等，且所述第一显示区中第三颜色的第一发光单元的第一电极在衬底基板上的正投影的面积，大于所述第二显示区中第三颜色的第二发光单元的第一电极在衬底基板上的正投影的面积。
  9. 根据权利要求3至8任一所述的显示面板，其特征在于，所述第一发光单元组中的所述第一发光单元的第一电极包括：第一主体图案，以及与所述第一主体图案连接的第一连接图案，所述第一主体图案的至少部分与所述第一发光单元的发光层接触，且所述第一连接图案与所述第一像素电路组连接；
    所述虚设电极图案包括：第二主体图案，以及分别与所述第二主体图案连接的第二连接图案和第三连接图案，所述第二主体图案与任一所述第一发光单元的发光层不接触，且所述第二连接图案与所述第二像素电路组连接，所述第三连接图案通过第一连接走线或所述第二连接走线与所述第二发光单元组连接。
  10. 根据权利要求9所述的显示面板，其特征在于，所述第一发光单元的第一电极还包括：与所述第一主体图案连接的第四连接图案；
    所述第一发光单元中第一电极的第一主体图案在所述衬底基板上的正投影，与所述第一发光单元对应的虚设电极图案的第二主体图案在所述衬底基板上的正投影的形状和面积相同；
    所述第一发光单元中的第一电极的第一连接图案在所述衬底基板上的正投影，与所述第一发光单元对应的虚设电极图案的第二连接图案在所述衬底基板上的正投影的形状和面积相同；
    所述第一发光单元中的第一电极的第四连接图案在所述衬底基板上的正投影，与所述第一发光单元对应的虚设电极图案的第三连接图案在所述衬底基板上的正投影的形状和面积相同。
  11. 根据权利要求10所述的显示面板，其特征在于，所述第一连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影不重叠，所述第四连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影至少部分重叠；
    所述第二连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影不重叠，所述第三连接图案在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影至少部分重叠。
  12. 根据权利要求9至11任一所述的显示面板，其特征在于，沿行方向相邻的两个所述第一图案组中的两个目标虚设电极图案对应的所述第一发光单元的颜色相同，且所述两个目标虚设电极图案的第三连接图案分别通过一个所述第一连接走线与所述第二发光单元组连接；
    其中，所述两个目标虚设电极图案中，一个所述目标虚设电极图案中第三连接图案的连接部与另一个所述目标虚设电极图案中第三连接图案的连接部之间的连线，与所述行方向相交，所述第三连接图案的连接部用于与所述第一连接走线连接。
  13. 根据权利要求3至12任一所述的显示面板，其特征在于，所述第一像素 电路组包括多个第一像素电路单元，每个所述第一像素电路单元至少包括：第一像素电路和第二像素电路，且所述第一像素电路单元中的至少两个像素电路被配置为与所述第一发光单元组中同一个第一发光单元的第一电极电连接。
  14. 根据权利要求13所述的显示面板，其特征在于，所述第一发光单元的第一电极包括的第一连接图案包括：沿目标方向延伸的第一主体连接部和位于所述第一主体连接部两端的两个第一端部；
    其中，所述两个第一端部分别与所述第一像素电路和所述第二像素电路电连接，所述目标方向大致平行于行方向。
  15. 根据权利要求3至14任一所述的显示面板，其特征在于，所述第二像素电路组包括多个第二像素电路单元，每个所述第二像素电路单元至少包括：第三像素电路和第四像素电路，且所述第二像素电路单元中的至少两个像素电路被配置为与同一个虚设电极图案电连接。
  16. 根据权利要求15所述的显示面板，其特征在于，所述虚设电极图案包括的第二连接图案包括：沿目标方向延伸的第二主体连接部和位于所述第二主体连接部两端的两个第二端部；
    其中，所述两个第二端部分别与所述第三像素电路和所述第四像素电路电连接，所述目标方向大致平行于行方向。
  17. 根据权利要求1至16任一所述的显示面板，其特征在于，所述多个第二连接走线与所述虚设电极图案组位于同层。
  18. 根据权利要求1至17任一所述的显示面板，其特征在于，所述多个第一连接走线的另一端的连线与所述第一显示区远离所述第二显示区的边缘平行，且所述多个第一连接走线的另一端的连线与所述第一显示区远离所述第二显示区的边缘之间的距离小于距离阈值。
  19. 根据权利要求18所述的显示面板，其特征在于，所述多个第一连接走线 的另一端的连线与所述第一显示区远离所述第二显示区的边缘均大致平行于列方向。
  20. 根据权利要求19所述的显示面板，其特征在于，
    所述多个第一连接走线的另一端的连线与所述第一显示区远离所述第二显示区的边缘共线。
  21. 根据权利要求1至20任一所述的显示面板，其特征在于，所述衬底基板还包括：位于所述第一显示区和所述第二显示区同一侧的第三显示区，所述显示面板还包括：位于所述第三显示区的多个第三发光单元组和多个第三像素电路组；
    其中，每个所述第三像素电路组与一个所述第三发光单元组连接，所述多个第三发光单元组的密度大于所述多个第一发光单元组的密度，且大于所述多个第二发光单元组的密度。
  22. 根据权利要求21所述的显示面板，其特征在于，所述衬底基板包括：两个所述第一显示区和一个所述第二显示区，所述第二显示区为矩形；
    所述矩形沿行方向延伸的至少一个边缘与所述第三显示区相接，所述矩形沿列方向延伸的两个边缘分别与两个所述第一显示区相接。
  23. 根据权利要求22所述的显示面板，其特征在于，所述第一显示区为矩形；所述第一显示区的任一边缘的长度范围为0.1毫米至20毫米；
    所述第二显示区的任一边缘的长度范围为0.2毫米至10毫米。
  24. 根据权利要求1至23任一所述的显示面板，其特征在于，所述显示面板还包括：多条数据线；
    所述多条数据线中位于所述第二显示区的至少一条目标数据线的至少部分在所述衬底基板上的正投影均位于所述第二显示区靠近所述第一显示区的区域。
  25. 一种显示装置，其特征在于，所述显示装置包括：供电组件以及如权利要求1至24任一所述的显示面板；
    所述供电组件用于为所述显示面板供电。
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