WO2022109874A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022109874A1
WO2022109874A1 PCT/CN2020/131497 CN2020131497W WO2022109874A1 WO 2022109874 A1 WO2022109874 A1 WO 2022109874A1 CN 2020131497 W CN2020131497 W CN 2020131497W WO 2022109874 A1 WO2022109874 A1 WO 2022109874A1
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WO
WIPO (PCT)
Prior art keywords
electrostatic discharge
transistor
electrically connected
sub
circuit
Prior art date
Application number
PCT/CN2020/131497
Other languages
English (en)
French (fr)
Inventor
刘聪
周宏军
杜丽丽
魏锋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/131497 priority Critical patent/WO2022109874A1/zh
Priority to US17/434,481 priority patent/US11842665B2/en
Priority to CN202080002984.0A priority patent/CN114846533A/zh
Publication of WO2022109874A1 publication Critical patent/WO2022109874A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • ESD Electrostatic Discharge
  • Embodiments of the present disclosure provide a display panel, including:
  • a base substrate including a display area and a peripheral area surrounding the display area
  • a plurality of sub-pixels located on the base substrate and in the display area, the plurality of sub-pixels are arranged in an array;
  • a plurality of data signal lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data signal lines being configured to transmit data signals to the plurality of sub-pixels;
  • an electrostatic discharge circuit located on the base substrate and located in the peripheral region, the electrostatic discharge circuit is electrically connected to the plurality of data traces;
  • an encapsulation layer located on the side of the plurality of sub-pixels and the electrostatic discharge circuit away from the base substrate, and the orthographic projection of the electrostatic discharge circuit on the base substrate is located on the base substrate of the encapsulation layer in the orthographic projection.
  • the edge of the peripheral area includes an annular encapsulation area surrounding the display area, the encapsulation area is provided with an annular dam, and the electrostatic discharge circuit is located between the encapsulation area and the display area .
  • the encapsulation layer includes a first inorganic material layer, a second inorganic material layer, and an organic material layer located between the first inorganic material layer and the second inorganic material layer, wherein the organic material layer is located in the In the area enclosed by the annular dam portion, the first inorganic material layer and the second inorganic material layer are located on the side of the dam portion away from the base substrate.
  • the encapsulation layer includes a cover plate
  • the edge of the peripheral area includes an annular encapsulation area surrounding the display area, an adhesive layer is arranged in the encapsulation area, and the adhesive layer is located on the side of the cover plate facing the base substrate,
  • the electrostatic discharge circuit is located between the packaging area and the display area.
  • the electrostatic discharge circuit includes a plurality of electrostatic discharge units, the plurality of electrostatic discharge units are respectively electrically connected to the plurality of data traces, and at least a part of the electrostatic discharge units in the plurality of electrostatic discharge units are along the lines of the plurality of electrostatic discharge units. the edge arrangement of the display area.
  • the edge of the display area on the side facing the electrostatic protection circuit has at least one arc-shaped portion, and at least a part of the electrostatic discharge cells in the plurality of electrostatic discharge cells are arranged along the at least one arc-shaped portion.
  • the at least a portion of the electrostatic discharge cells each have a first reference axis and a second reference axis perpendicular to the first reference axis, and the first reference axis of each electrostatic discharge cell in the at least a portion of the electrostatic discharge cells is parallel to the the normal direction of the arc portion adjacent to the electrostatic discharge unit, the second reference axis of each electrostatic discharge unit in the at least a part of the electrostatic discharge unit is parallel to the tangent direction of the arc portion adjacent to the electrostatic discharge unit .
  • the at least a portion of the electrostatic discharge cells each have a first reference axis and a second reference axis perpendicular to the first reference axis, the first reference axis being parallel to the first direction, and the second reference axis being parallel to the first direction A second direction, wherein the first direction is the row direction of the array, and the second direction is the column direction of the array.
  • the display area has a circular outline, and the plurality of electrostatic discharge cells are arranged along an arc-shaped edge of the circular outline facing the side of the electrostatic discharge circuit.
  • the display area has a rounded rectangular outline, and a part of the electrostatic discharge cells in the plurality of electrostatic discharge cells are arranged along the rounded arc edge of the rounded rectangular outline facing the side of the electrostatic discharge circuit, Another part of the electrostatic discharge units in the plurality of electrostatic discharge units are arranged along a straight edge of the rounded rectangular outline facing the side of the electrostatic discharge circuit.
  • the display area has a rectangular outline, and the plurality of electrostatic discharge cells are arranged along a straight edge of the rectangular outline facing the side of the electrostatic discharge circuit.
  • the display panel further includes:
  • a first power signal line located between the electrostatic discharge circuit and the display area, and electrically connected to the electrostatic discharge circuit
  • a first reference signal line located between the electrostatic discharge circuit and the packaging area, and electrically connected to the electrostatic discharge circuit, the voltage of the first power supply signal line is higher than the voltage of the first reference signal line .
  • each electrostatic discharge unit is electrically connected to the first power supply signal line
  • the reference signal terminal of each electrostatic discharge unit is electrically connected to the first reference signal line
  • the output terminal of each electrostatic discharge unit is electrically connected to the first reference signal line. It is electrically connected to at least one data trace in the plurality of data traces.
  • the display panel further includes:
  • the gate drive circuit is located between the display area and the electrostatic discharge circuit
  • a plurality of gate signal lines are located in the display area and are electrically connected to the plurality of sub-pixels, and the gate driving circuit is electrically connected to the plurality of sub-pixels in the display area through the plurality of gate signal lines connect;
  • a second power supply signal line located between the gate driving circuit and the first reference signal line, and electrically connected to the gate driving circuit
  • a second reference signal line is located between the second power supply signal line and the gate driving circuit, and is electrically connected to the gate driving circuit, and the voltage of the second power supply signal line is higher than that of the second power supply signal line The voltage of the reference signal line.
  • the display panel further includes:
  • the gate driving circuit is located between the display area and the packaging area, and is electrically connected to the plurality of sub-pixels in the display area through the plurality of gate signal lines, the An electrostatic discharge circuit is located on the side of the gate driving circuit facing the packaging area;
  • a second power signal line located between the gate driving circuit and the electrostatic discharge circuit, and electrically connected to the gate driving circuit and the electrostatic discharge circuit;
  • a second reference signal line located between the second power supply signal line and the gate driving circuit, and electrically connected to the gate driving circuit and the electrostatic discharge circuit
  • each electrostatic discharge unit is electrically connected to the second power signal line
  • the reference signal terminal of each electrostatic discharge unit is electrically connected to the second reference signal line
  • the output terminal of each electrostatic discharge unit is electrically connected to the second reference signal line. It is electrically connected to at least one data trace in the plurality of data traces.
  • the display panel further includes:
  • a multiplexing circuit located between the display area and the packaging area, the multiple data traces are electrically connected to the multiple data signal lines through the multiplexing circuit;
  • K selection signal lines are located between the multiplexing circuit and the electrostatic discharge circuit, and are electrically connected to the multiplexing circuit, wherein K is an integer greater than 1,
  • the multiplexing circuit includes a plurality of multiplexing units, wherein the input terminal of the i-th multiplexing unit and the output terminal of the i-th electrostatic discharge unit are connected to the i-th one of the plurality of data lines.
  • Data routing, K output terminals of the i-th multiplexing unit are respectively connected to K data signal lines in the plurality of data signal lines, and K control signal terminals of the i-th multiplexing unit are respectively connected to the K selection signal lines, where i is an integer greater than or equal to 1.
  • each electrostatic discharge unit includes a first electrostatic discharge unit and a second electrostatic discharge unit
  • each multiplexing unit includes a first multiplexing subunit and a second multiplexing subunit
  • each The data routing includes a first sub-line, a second sub-line and a third sub-line, wherein,
  • the first sub-wire of the i-th data line is connected to the input end of the first electrostatic discharge sub-unit and the input end of the second electrostatic discharge sub-unit of the i-th electrostatic discharge unit;
  • the second sub-line of the i-th data wiring is connected between the input end of the first electrostatic discharge sub-unit of the i-th electrostatic discharge unit and the input end of the first multiplexing sub-unit of the i-th multiplexing unit;
  • the third sub-line of the i-th data line is connected between the input end of the second electrostatic discharge sub-unit of the i-th electrostatic discharge unit and the input end of the second multiplexing sub-unit of the i-th multiplexing unit.
  • the first electrostatic discharge unit includes a first transistor, a second transistor, a third transistor and a fourth transistor, and the gate of the first transistor and the first electrode of the first transistor are electrically connected as the The power signal terminal of the first electrostatic discharge unit, the second pole of the first transistor is electrically connected to the gate of the second transistor and the first pole of the second transistor, the second pole of the second transistor is electrically connected
  • the electrode is electrically connected to the gate of the third transistor and the first electrode of the third transistor as the output end of the first electrostatic discharge unit, and the second electrode of the third transistor is connected to the fourth transistor.
  • the gate of the fourth transistor is electrically connected to the first pole of the fourth transistor, and the second pole of the fourth transistor serves as the reference signal terminal of the first electrostatic discharge unit;
  • the second electrostatic discharge unit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the gate of the fifth transistor and the first electrode of the fifth transistor are electrically connected as the second transistor
  • the power signal terminal of the electrostatic discharge unit, the second pole of the fifth transistor is electrically connected to the gate of the sixth transistor and the first pole of the sixth transistor, and the second pole of the sixth transistor is electrically connected to the gate of the sixth transistor and the first pole of the sixth transistor.
  • the gate of the seventh transistor and the first electrode of the seventh transistor are electrically connected as the output end of the second electrostatic discharge unit, and the second electrode of the seventh transistor and the gate of the eighth transistor are electrically connected
  • the electrode is electrically connected to the first electrode of the eighth transistor, and the second electrode of the eighth transistor serves as the reference signal terminal of the second electrostatic discharge unit.
  • each electrostatic discharge unit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein,
  • the gate of the ninth transistor and the first electrode of the ninth transistor are electrically connected as the power supply signal terminal of the electrostatic discharge unit, and the second electrode of the ninth transistor and the gate of the tenth transistor and the The first electrode of the tenth transistor is electrically connected, and the second electrode of the tenth transistor is electrically connected to the gate of the eleventh transistor and the first electrode of the eleventh transistor as the electrostatic discharge unit the output terminal of the 11th transistor, the second pole of the eleventh transistor is electrically connected to the gate of the twelfth transistor and the first pole of the twelfth transistor, and the second pole of the twelfth transistor serves as the The reference signal terminal of the electrostatic discharge unit.
  • the display panel further includes:
  • a first clock signal line located between the second power supply signal line and the second reference signal line and electrically connected to the gate driving circuit
  • the second clock signal line is located between the first clock signal line and the second power supply signal line, and is electrically connected to the gate driving circuit.
  • At least one sub-pixel of the plurality of sub-pixels includes a drive transistor including a gate, a source, and a drain;
  • Each electrostatic discharge unit includes a plurality of transistors, wherein the gate of each transistor is disposed in the same layer as the gate of the driving transistor, and the first electrode and the second electrode of each transistor are the source and drain of the driving transistor. Very homogenous settings.
  • Embodiments of the present disclosure also provide a display device, including the above-mentioned display panel.
  • FIG. 1A shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 1B shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 2 shows a schematic diagram of a display area in a display panel according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic circuit diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic layout diagram of an electrostatic discharge circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 5 shows a layout diagram of an example of the area XX of the display panel of FIG. 1B .
  • FIG. 6 shows a schematic circuit diagram of the area shown in FIG. 5 .
  • FIG. 7 shows a circuit diagram of the area shown in FIG. 5 .
  • FIG. 8 shows a schematic layout diagram of an electrostatic discharge circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 9 shows a layout diagram of another example of the area XX of the display panel of FIG. 1B .
  • FIG. 10 shows a schematic circuit diagram of the area shown in FIG. 9 .
  • FIG. 11 shows a circuit diagram of the area shown in FIG. 9 .
  • FIG. 12 shows an enlarged layout of the electrostatic discharge circuit in FIG. 9 .
  • FIG. 13A illustrates a cross-sectional view of a display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 13B shows a cross-sectional view of an electrostatic discharge circuit of the display panel of FIG. 13A.
  • FIG. 13C shows a cross-sectional view of an encapsulation area of the display panel of FIG. 13A .
  • FIG. 14A illustrates a cross-sectional view of a display area of a display panel according to another embodiment of the present disclosure.
  • FIG. 14B illustrates a cross-sectional view of an electrostatic discharge circuit of the display panel of FIG. 14A.
  • FIG. 14C shows a cross-sectional view of an encapsulation area of the display panel of FIG. 14A .
  • FIG. 15 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 16 shows a schematic diagram of a display panel according to yet another embodiment of the present disclosure.
  • FIG. 17 shows a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 1A shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 100A includes a base substrate 110 and an electrostatic discharge circuit 130 .
  • the base substrate 110 is provided with a display area AA and a peripheral area SA surrounding the display area, and an annular encapsulation area PA surrounding the display area AA is included at the edge of the peripheral area SA.
  • a plurality of sub-pixels are arranged in the display area AA, and the electrostatic discharge circuit 130 is located between the display area AA and the packaging area PA.
  • the projection of the display area AA on the base substrate 110 has a circular outline, and the electrostatic discharge circuits 130 are located on one side of the display area AA along the y direction and surround a part of the arc edge of the display area AA.
  • the embodiments of the present disclosure are not limited thereto, and the display area AA may be designed to have contours of other shapes, such as oval, rectangle, rounded rectangle, or even irregular shape, as required.
  • the outline shapes of the base substrate 110 and the display area AA are the same, and both are circular.
  • the outline shape of the base substrate 110 may be different from the display area AA.
  • the base substrate 110 may also include two rectangular portions located on both sides of the circular portion, for example, for a special-shaped display device such as a watch.
  • the display panel 100A further includes a plurality of data lines DATA located in the peripheral area SA, and the plurality of data lines DATA are located on one side of the display area AA, and can pass through the data signal lines in the display area AA and the sub-pixels in the display area AA. electrical connection.
  • the electrostatic discharge circuit 130 is electrically connected to the plurality of data lines DATA for discharging static electricity on the plurality of data lines DATA.
  • the data wiring DATA can be led out from the display panel 110 so as to be electrically connected with the driving IC.
  • the display panel 100A may further include a multiplexing circuit 120 .
  • the multiplexing circuit 120 is electrically connected to the plurality of data lines DATA, and the multiplexing circuit 120 can multiplex the m channels of input data signals on the plurality of data lines DATA into M channels of output data signals.
  • the data signal lines in the display area AA are provided to a plurality of sub-pixels in the display area AA, wherein m and M are both integers greater than 1, and M is an integer multiple of m.
  • the electrostatic discharge circuit is usually located in the peripheral area of the packaging area, such as a flexible circuit board located at the periphery of the packaging area.
  • the electrostatic discharge circuit is easily damaged.
  • the electrostatic discharge circuit By arranging the electrostatic discharge circuit in the area between the packaging area PA and the display area AA in the embodiments of the present disclosure, on the one hand, the length of the data traces between the electrostatic discharge circuit and the pixels in the AA area is shortened, and the quality of electrostatic discharge is improved. ; On the other hand, the electrostatic discharge circuit can be protected by the package in the package area, reducing the risk of circuit damage.
  • FIG. 1B shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel 100B of FIG. 1B is similar to the above-mentioned display panel 100A, except that the display panel 100B further includes a gate driving circuit 140 , and the above description of the display panel 100A is also applicable to the display panel 100B.
  • the gate driving circuit 140 is located between the display area AA and the packaging area PA, and the electrostatic discharge circuit 120 is located on the side of the gate driving circuit 140 close to the AA area.
  • the gate driving circuit 140 may be electrically connected to a plurality of sub-pixels in the display area AA through a plurality of gate signal lines, which will be described in further detail below.
  • the gate driving circuit 140 is provided around the entire edge of the display area AA, and the multiplexing circuit 120 is provided in the area between the gate driving circuit 140 and the display area AA.
  • the gate driving circuit 140 and the multiplexing circuit 130 may be arranged in other manners as required.
  • FIG. 2 shows a schematic diagram of a display area in a display panel according to an embodiment of the present disclosure.
  • a plurality of sub-pixels Px1 are provided in the display area AA, and the plurality of sub-pixel cloths Px1 are arranged in the form of an array.
  • a plurality of sub-pixels Px1 are arranged in N rows and M columns, and the row direction is taken as the x direction (second direction), and the column direction is taken as the y direction (first direction).
  • the number of sub-pixels is different between multiple rows and the number of sub-pixels between multiple columns is different, so that the array as a whole is circular, so that the projection of the display area AA on the base substrate 110 has a circular shape contour.
  • the embodiments of the present disclosure are not limited thereto, and the plurality of sub-pixels Px1 may be arranged in arrays of other shapes, such as rectangles, rounded rectangles, and the like, as required.
  • the display area AA is also provided with a plurality of gate signal lines G1, G2, . . . GN electrically connected to the plurality of sub-pixels Px1.
  • a plurality of data signal lines D1, D2, . . . DM electrically connected to the plurality of sub-pixels Px1 are also provided in the display area AA.
  • N rows of sub-pixels Px1 are connected to N gate signal lines G1, G2, ... GN in one-to-one correspondence
  • M columns of sub-pixels Px1 are connected to M data signal lines D1, D2, ...
  • each row of sub-pixels is connected to one gate signal line
  • each column of sub-pixels is connected to one data signal line.
  • the embodiments of the present disclosure are not limited thereto, and the number and connection manner of the gate signal lines and the data signal lines can be selected as required.
  • two gate signal lines can be connected to each row of sub-pixels, and the number of the gate signal lines is Twice the number of sub-pixel rows; or every two columns of sub-pixels are connected to a data signal line, and the number of data signal lines is half the number of sub-pixel columns, and so on.
  • FIG. 3 shows a schematic circuit diagram of a display panel according to an embodiment of the present disclosure.
  • the multiplexing units MUX1, MUX2, . . . MUXm are respectively electrically connected to the data wirings DATA1, DATA2, . . . DATAm.
  • each multiplexing unit MUX1, MUX2, ... MUXm can be a one-to-six multiplexing unit, that is, each multiplexing unit can multiplex one input data signal into six outputs The data signals are respectively supplied to the 6 data signal lines.
  • the input end of the multiplexing circuit MUX1 is connected to the data line DATA1
  • the output end of the multiplexing circuit MUX1 is connected to the data signal lines D1 to D6
  • the multiplexing circuit MUX1 can connect the input data at the data line DATA1
  • the signals are multiplexed into six output data signals, which are respectively provided to the data signal lines D1 to D6; in a similar manner, the multiplexing circuit MUX2 can multiplex the input data signals at the data line DATA2 into six output data signals, which are respectively provided to the data signal lines D1 to D6.
  • the electrostatic discharge units ESD1, ESD2, . . . ESDm are respectively electrically connected to the data wirings DATA1, DATA2, . . . DATAm.
  • the electrostatic discharge unit ESD1 is electrically connected to the data line DATA1 for discharging static electricity on the data line DATA1;
  • the electrostatic discharge unit ESD2 is electrically connected to the data line DATA2 for discharging the static electricity on the data line DATA2 to And so on.
  • the gate driving circuit 140 includes a plurality of shift register units GOA1, GOA2, . . . GOAN.
  • the shift register units GOA1, GOA2, . . . GOAN are electrically connected to the gate signal lines G1, G2, . . . GN, respectively.
  • the shift register unit GOA1 is electrically connected to the gate signal line G1
  • the shift register unit GOA2 is electrically connected to the gate signal line G2, and so on, so that the gate driving circuit 140 and the multiple rows of sub-lines of the display area AA are implemented. Electrical connection of pixel Pxl.
  • the embodiments of the present disclosure are not limited to this, and the type of the multiplexing circuit can be selected according to needs.
  • the embodiments of the present disclosure are not limited to this, and the number of data lines can be selected according to requirements.
  • the number of electrostatic discharge units and the number of multiplexing units may be equal to or different from the number of data traces.
  • FIG. 4 shows a schematic layout diagram of an electrostatic discharge circuit in a display panel according to an embodiment of the present disclosure.
  • the layout of the electrostatic discharge circuit in FIG. 4 is applicable to the display panel of any of the above embodiments.
  • the projection of the display area AA on the base substrate 110 has a circular outline, and a plurality of electrostatic discharge units ESD1 , ESD2 , . . . ESDm are arranged along the arc edge of the circular outline of the display area AA, so as to surround the display Part of District AA.
  • FIG. 4 shows 7 electrostatic discharge cells for convenience of description, however, those skilled in the art should understand that the embodiments of the present disclosure are not limited thereto.
  • Each electrostatic discharge cell ESDi may have a first reference axis ay and a second reference axis ax perpendicular to the first reference axis ay, where i is an integer and 1 ⁇ i ⁇ m.
  • the projection of the electrostatic discharge unit ESDi on the base substrate 110 may have a substantially rectangular outline, and the symmetry axis of the rectangular outline parallel to its short side may be taken as the first reference axis ay, and the The symmetry axis of its long side is taken as the second reference axis ax.
  • the first reference axis ay of each electrostatic discharge unit is parallel to the y direction
  • the second reference axis ax is parallel to the x direction, so that the electrostatic discharge units ESD1, ESD2, . . . ESDm are along the contour of the display area AA
  • the generally conformal trajectories (shown in dashed lines in Figure 4) are arranged in steps.
  • FIG. 5 shows a layout diagram of an example of the area XX of the display panel of FIG. 1B .
  • FIG. 6 shows a schematic circuit diagram of the area shown in FIG. 5 .
  • the display panel includes electrostatic discharge units ESD1, ESD2, . . . ESDm, multiplexing units MUX1, MUX2, . . . MUXm, and shift register units GOA1, GOA2, . . . GOAN.
  • ESDi electrostatic discharge units
  • ESD(i+1) multiplexing units
  • MUXi multiplexing units
  • MUX(i+1) shift register units
  • GOAj GOA(j +1) Marked with a dashed box.
  • the electrostatic discharge cells ESD1 , ESD2 , . . . ESDm follow a first substantially conformal shape to the arc edge of the display area AA (as shown by the dot-dash line in FIG. 5 ) in the manner shown in FIG. 4 .
  • the tracks are arranged in steps.
  • the multiplexing units MUX1, MUX2, . . . MUXm are arranged in a stepped manner along a second track that is substantially conformal to the edge of the display area AA in a manner similar to the electrostatic discharge units ESD1, ESD2, . . . ESDm.
  • GOAN are stair-stepped along a third track that is generally conformal to the edge of the display area AA in a manner similar to the electrostatic discharge cells ESD1, ESD2, . . . ESDm.
  • the first track, the second track and the third track are three tracks extending in parallel, the second track is located between the display area AA and the first track, and the third track is located between the second track and the first track .
  • the base substrate 110 is further provided with a second power supply signal line VGH and a second reference signal line VGL.
  • the second power signal line VGH is located between the gate driving circuit 140 (including the shift register units GOA1, GOA2, ... GOAN) and the electrostatic discharge circuit 130 (including the electrostatic discharge units ESD1, ESD2, ... ESDm), the second reference signal line VGL is located between the second power signal line VGH and the gate driving circuit 140 .
  • a single shift register unit GOAj, a multiplexing unit MUXi and an electrostatic discharge unit ESDi are taken as examples for schematic illustration.
  • the gate driving circuit 140 and the electrostatic discharge circuit 130 share the second power supply signal line VGH and the second reference signal line VGL.
  • the power signal terminal of each shift register unit GOA1, GOA2, ... GOAN is electrically connected to the second power signal line VGH, and the reference signal of each shift register unit GOA1, GOA2, ... GOAN
  • the terminal is electrically connected to the second reference signal line VGL;
  • the power signal terminal of each electrostatic discharge unit ESD1, ESD2, ... ESDm is electrically connected to the second power signal line VGH, and the reference signal of each electrostatic discharge unit ESD1, ESD2, ... ESDm
  • the terminal is electrically connected to the second reference signal line VGL.
  • the base substrate 110 is further provided with a first clock signal line CK and a second clock signal line CB.
  • the first clock signal line CK is located between the second power signal line VGH and the second reference signal line VGL
  • the second clock signal line CB is located between the first clock signal line CK and the second power signal line VGH.
  • Each of the shift register units GOA1, GOA2, . . . GOAN in the gate driving circuit 140 is electrically connected to the first clock signal line CK and the second clock signal line CB. For example, in FIG.
  • each register unit GOAj is electrically connected to the first clock signal line CK, and the second clock signal terminal is electrically connected to the second clock signal line CB; the register units are all GOA(j+1) The first clock signal terminal is electrically connected to the second clock signal line CB, the second clock signal terminal is electrically connected to the first clock signal line CK, and so on.
  • Each shift register cell eg GOAj
  • the selection signal lines Mux1 to Mux6 are located between the multiplexing circuit 120 (including the multiplexing units MUX1, MUX2, . . . MUXm) and the electrostatic discharge circuit 130 (including the electrostatic discharge units ESD1, ESD2, . . . ESDm), in FIG. 5 between the multiplexing units MUX1 , MUX2 , . . . MUXm of the multiplexing circuit 120 and the shift register units GOA1 , GOA2 , . . .
  • the selection signal lines Mux1 to Mux6 are electrically connected to the multiplexing circuit 120 .
  • the six control signal terminals of the i-th multiplexing unit MUXi are respectively connected to six selection signal lines Mux1 to Mux6, and the input terminal of the i-th multiplexing unit MUXi is connected to the i-th data line.
  • the output end of the i-th electrostatic discharge unit ESDi is also connected to the i-th data line DATAi.
  • the second power signal line VGH, the second reference signal line VGL, the first clock signal line CK, the second clock signal line CB, and the selection signal lines Mux1 to Mux6 all extend in the form of broken lines, and the broken lines
  • the corners may be, for example, 90 degrees to accommodate the layout of multiplexing cells, shift register cells and electrostatic discharge cells.
  • FIG. 7A shows a circuit diagram of the area shown in FIG. 5, in which the circuit structure of each multiplexing unit and the electrostatic discharge unit is shown. As shown in FIG. 7A , the multiplexing unit MUXi and the electrostatic discharge unit ESDi are both connected to the data wiring DATAi.
  • the multiplexing unit MUXi includes transistors Tm1 to Tm6, wherein the gates of the transistors Tm1 to Tm6 are electrically connected to the selection signal lines Mux1 to Mux6 in one-to-one correspondence, and the first electrodes of the transistors Tm1 to Tm6 are all connected to the data line DATAi, The second poles of the transistors Tm1 to Tm6 are electrically connected to the six data signal lines Di1 to Di6 in a one-to-one correspondence.
  • the transistor Tm1 When the signal at the selection signal line Mux1 is at a high level, the transistor Tm1 is turned on, thereby providing the data signal at the data trace DATAi to the data signal line Di1; when the signal at the selection signal line Mux2 is at a high level, the transistor Tm2 turn on, so that the data signal at the data line DATAi is provided to the data signal line Di2, and so on, so that the multiplexing unit MUXi can multiplex one input data signal at the data line DATAi into 6 output data Signals are supplied to the six data signal lines Di1 to Di6, respectively.
  • FIG. 7B shows a layout diagram of the electrostatic discharge unit ESDi in FIG. 7A .
  • the electrostatic discharge unit ESDi includes a ninth transistor T9 , a tenth transistor T10 , an eleventh transistor T11 and a twelfth transistor T12 .
  • the gate of the ninth transistor T9 is electrically connected to the first electrode, and is connected to the second power signal line VGH as a power signal terminal of the electrostatic discharge unit ESDi.
  • the second electrode of the ninth transistor T9 is electrically connected to the gate electrode and the first electrode of the tenth transistor T10.
  • the second electrode of the tenth transistor T10 is electrically connected to the gate electrode and the first electrode of the eleventh transistor T11, so as to be used as the output end of the electrostatic discharge unit ESDi and connected to the data line DATAi.
  • the second electrode of the eleventh transistor T11 is electrically connected to the gate electrode and the first electrode of the twelfth transistor T12.
  • the second electrode of the twelfth transistor T12 is connected to the second reference signal line VGL as a reference signal terminal of the electrostatic discharge unit ESDi.
  • the ninth transistor T9 and the tenth transistor T10 are turned on, so that the potential at the data wiring DATAi is released by using the potential of the second power signal line VGH.
  • High voltage static electricity when the potential at the data trace DATAi is lower than the potential of the second reference signal line VGL, the eleventh transistor T11 and the twelfth transistor T12 are turned on, thereby using the potential of the second reference signal line VGL to release Low voltage static electricity at data trace DATAi.
  • FIG. 8 shows a schematic layout diagram of an electrostatic discharge circuit in a display panel according to an embodiment of the present disclosure.
  • the projected shape of the display area AA on the base substrate and the arrangement of the electrostatic discharge circuit in FIG. 8 are similar to those in FIG. 4 , and the difference lies at least in the placement angle of the electrostatic discharge unit. In order to simplify the description, the different parts will be mainly described in detail below.
  • the projection of the display area AA on the base substrate has a circular outline, and the electrostatic discharge units ESD1 , ESD2 , . part of the circular profile.
  • the difference from FIG. 4 is that the first reference axis ay of each electrostatic discharge unit in FIG.
  • the electrostatic discharge units ESD1 , ESD2 , . . . ESDm are arranged in a step-arc shape along a track that is substantially conformal to the outline of the display area AA (as shown by the dotted line in FIG. 4 ).
  • FIG. 9 shows a layout diagram of another example of the area XX of the display panel of FIG. 1B .
  • FIG. 10 shows a schematic circuit diagram of the area shown in FIG. 9 .
  • the display panels shown in FIGS. 9 and 10 are similar to the display panels shown in FIGS. 5 and 6 , and the difference lies at least in the placement angles of the electrostatic discharge unit, the shift register unit and the multiplexing unit, and FIGS. 9 and 6
  • the electrostatic discharge circuit in the display panel of 10 is connected to a separate set of the first power supply signal line VGH' and the first reference signal line VGL', instead of sharing the second power supply signal line VGH and the second reference signal line VGL with the gate driving circuit .
  • the following will mainly describe the different parts in detail.
  • the display panel of FIGS. 9 and 10 includes electrostatic discharge cells ESD1, ESD2, . . . ESDm, multiplexing cells MUX1, MUX2, . . . MUXm, and shift register cells GOA1, GOA2, .
  • FIG. 9 has marked one of the electrostatic discharge unit ESDi, one multiplexer unit MUXi and one shift register unit GOAj with a dashed box.
  • the electrostatic discharge units ESD1 , ESD2 , . . . ESDm in FIG. 9 are generally along the arc edge (as shown by the dot-dash line in FIG. 9 ) with the display area AA in the manner shown in FIG. 8 .
  • the conformal first tracks are arranged in an arc shape.
  • the shift register cells GOA1, GOA2, . . . GOAN are arranged in arcs along a second track that is substantially conformal to the edge of the display area AA in a manner similar to the electrostatic discharge cells ESD1, ESD2, . . . ESDm.
  • the multiplexing units MUX1, MUX2,...MUXm are also arranged along the second track in a manner similar to the electrostatic discharge units ESD1, ESD2,...ESDm, wherein the multiplexing units MUX1, MUX2,...MUXm are distributed in the shift register Cells GOA1, GOA2, ... GOAN are in the gaps between each other.
  • the first track and the second track are two tracks extending in parallel, and the second track is located between the display area AA and the first track.
  • the display panel of FIGS. 9 and 10 includes a second power supply signal line VGH, a second reference signal line VGL, a first clock signal line CK, a second clock signal line CB, and selection signal lines Mux1 to Mux6.
  • Each of the shift register units GOA1, GOA2, . . . GOAN is connected to the second power supply signal line VGH, the second reference signal line VGL, the first clock signal line CK, and the second clock signal line CB.
  • Each multiplexing unit MUX1, MUX2, . . . MUXm connects selection signal lines Mux1 to Mux6.
  • the display panel of FIGS. 9 and 10 further includes a first power signal line VGH' and a first reference signal line VGL'.
  • the power supply signal terminal of each electrostatic discharge unit ESD1, ESD2, ...ESDm is electrically connected to the first power supply signal line VGH'
  • the reference signal terminal of each electrostatic discharge unit ESD1, ESD2, ...ESDm is electrically connected to the first reference signal line VGL'
  • the output end of each electrostatic discharge unit ESD1, ESD2, . . . ESDm is electrically connected to at least one data line among the data lines DATA1, DATA2, .
  • the first power signal line VGH' is located between the electrostatic discharge circuit 120 including a plurality of electrostatic discharge units ESD1, ESD2, . . . ESDm and the display area AA
  • the first reference signal line VGL' is located between the electrostatic discharge circuit 120 including a plurality of electrostatic discharge units
  • the second power signal line VGH includes the gate driving circuit 140 of the shift register units GOA1, GOA2, . . . GOAN and the first reference signal line VGL'
  • the second reference signal line VGL is located between the second power signal line VGH and the Between gate drive circuits including shift register units GOA1, GOA2, . . . GOAN.
  • FIG. 11 shows a circuit diagram of the area shown in FIG. 9, in which the circuit structure of each multiplexing unit and each electrostatic discharge unit is shown.
  • the circuit of FIG. 11 is similar to that of FIG. 7, except that each multiplexing unit includes a first multiplexing subunit and a second multiplexing subunit, and each electrostatic discharge unit includes a first electrostatic discharge subunit and a second electrostatic discharge unit.
  • each multiplexing unit includes a first multiplexing subunit and a second multiplexing subunit
  • each electrostatic discharge unit includes a first electrostatic discharge subunit and a second electrostatic discharge unit.
  • the data line DATAi (the i-th data line) is electrically connected to the multiplexing unit MUXi (the i-th multiplexing unit) and the electrostatic discharge unit ESDi (the i-th electrostatic discharge unit) , where i is an integer and 1 ⁇ i ⁇ m.
  • the electrostatic discharge unit ESDi includes a first electrostatic discharge unit ESDi_1 and a second electrostatic discharge unit ESDi_2, and the multiplexing unit MUXi includes a first multiplexing subunit MUXi_1 and a second multiplexing subunit MUXi_2.
  • the line DATAi includes a first sub-line DATAi_1, a second sub-line DATAi_2 and a third sub-line DATAi_3.
  • the first sub-line DATAi_1 is connected to the input terminal of the first electrostatic discharge sub-unit ESDi_1 and the input terminal of the second electrostatic discharge sub-unit ESDi_2.
  • the second sub-line DATAi_2 is connected between the input terminal of the first electrostatic discharge sub-unit ESDi_1 and the input terminal of the first multiplexing sub-unit MUXi_1.
  • the third sub-line DATAi_3 is connected between the input terminal of the second electrostatic discharge sub-unit ESDi_2 and the input terminal of the second multiplexing sub-unit MUXi_2.
  • the first electrostatic discharge unit ESDi_1 includes a first transistor T1 , a second transistor T2 , a third transistor T3 and a fourth transistor T4 .
  • the gate and the first electrode of the first transistor T1 are electrically connected to serve as a power supply signal terminal of the first electrostatic discharge unit ESDi_1 and electrically connected to the first power supply signal line VGH'.
  • the second electrode of the first transistor T1 is electrically connected to the gate electrode and the first electrode of the second transistor T2.
  • the second electrode of the second transistor T2 is electrically connected to the gate electrode and the first electrode of the third transistor T3, so as to be used as the output terminal of the first electrostatic discharge unit ESDi_1 and electrically connected to the second sub-line DATAi_2.
  • the second electrode of the third transistor 3 is electrically connected to the gate and the first electrode of the fourth transistor T4.
  • the second electrode of the fourth transistor T4 is electrically connected to the first reference signal line VGL' as a reference signal terminal of the first electrostatic discharge sub-unit ESDi_1.
  • the second electrostatic discharge unit ESDi_2 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • the gate of the fifth transistor T5 is electrically connected to the first electrode, and is electrically connected to the first power supply signal line VGH' as a power supply signal terminal of the second electrostatic discharge unit ESDi_2.
  • the second electrode of the fifth transistor T5 is electrically connected to the gate electrode and the first electrode of the sixth transistor T6.
  • the second electrode of the sixth transistor T6 is electrically connected to the gate electrode and the first electrode of the seventh transistor T7, so as to be used as an output terminal of the second electrostatic discharge unit ESDi_2 and electrically connected to the first sub-line DATAi_1.
  • the second electrode of the seventh transistor T7 is electrically connected to the gate electrode and the first electrode of the eighth transistor T8.
  • the second electrode of the eighth transistor T8 is electrically connected to the first reference signal line VGL' as a reference signal terminal of the second electrostatic discharge sub-unit ESDi_2.
  • the first multiplexing subunit MUXi_1 includes transistors Tm1 , Tm2 and Tm3
  • the second multiplexing subunit MUXi_2 includes transistors Tm4 , Tm5 and Tm6 .
  • the gates of the transistors Tm1 to Tm6 are respectively connected to the selection signal lines Mux1 to Mux6, and the second electrodes are respectively connected to the six data signal lines Di1 to Di6.
  • the first poles of the transistors Tm1, Tm2 and Tm3 are connected to the second sub-line DATAi_2 as input terminals of the first multiplexing sub-unit MUXi_1.
  • the first poles of the transistors Tm4, Tm5 and Tm6 are connected to the third sub-line DATAi_3 as the input terminal of the second multiplexing sub-unit MUXi_2.
  • FIG. 12 shows an enlarged layout of the electrostatic discharge circuit in FIG. 9 .
  • the first electrostatic discharge unit ESDi_1 of the electrostatic discharge unit ESDi includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, and the second electrostatic discharge unit ESDi_2 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.
  • the first sub-line DATAi_1 of the data wiring DATAi is connected to the input end of the first electrostatic discharge unit ESDi_1 and the input end of the second electrostatic discharge unit ESDi_2.
  • the second sub-line DATAi_2 of the data wiring DATAi is connected between the input end of the first electrostatic discharge sub-unit ESDi_2 and the input end of the first multiplexing sub-unit MUXi_1 of the multiplexing unit MUXi.
  • the third sub-line DATAi_3 of the data wiring DATAi is connected between the input terminal of the second electrostatic discharge sub-unit ESDi_2 and the input terminal of the second multiplexing sub-unit MUXi_2 of the multiplexing unit MUXi.
  • FIG. 13A illustrates a cross-sectional view of a display area of a display panel according to an embodiment of the present disclosure.
  • the cross-sectional view of FIG. 13A is applicable to the display area of the display panel of any of the foregoing embodiments.
  • the display panel includes a base substrate 110 , sub-pixels on the base substrate, and an encapsulation layer 160 .
  • the base substrate is 110 flexible and includes a first flexible layer 1101 , a first barrier layer 1102 , a second flexible layer 1103 , a second barrier layer 1104 and a buffer layer 1105 .
  • the second flexible layer 1103 is located on the first flexible layer 1101 and faces the display circuit (for example, including at least one of the sub-pixels, electrostatic discharge circuits, gate driving circuits, multiplexing circuits, and various signal lines and traces described above) a) side.
  • the first barrier layer 1102 is located between the first flexible layer 1101 and the second flexible layer 1103 .
  • the second barrier layer 1104 is located on the side of the second flexible layer 1103 away from the first flexible layer 1101 .
  • the buffer layer 1105 is located on the side of the second barrier layer 1104 away from the first flexible layer 1101 .
  • the display panel further includes a first gate insulating layer 1501, a second gate insulating layer 1502, an interlayer insulating layer 1503 and a planarization layer 1504.
  • the first insulating layer 1501 is located on the base substrate 110
  • the second gate insulating layer 1502 is located on the base substrate 110.
  • the interlayer insulating layer 1503 is located on the side of the first insulating layer 1501 away from the base substrate 110
  • the interlayer insulating layer 1503 is located at the side of the second gate insulating layer 1502 away from the base substrate 110 .
  • the planarization layer 1504 is located on the side of the interlayer insulating layer 1503 away from the base substrate 110 .
  • the sub-pixels in the display area AA include a driving transistor 210 , and the driving transistor 210 includes a gate electrode 2101 , a source electrode 2102 and a drain electrode 2103 .
  • the gate electrode 2101 of the driving transistor 210 is located between the first gate insulating layer 1501 and the second gate insulating layer 1502
  • the source electrode 2102 and the drain electrode 2103 of the driving transistor 210 are located between the interlayer insulating layer 1503 and the planarization layer 1504 .
  • the driving transistor 210 may further include an active region 2104, the active region 2104 is located between the base substrate 110 and the first gate insulating layer 1501, and the source electrode 2102 and the drain electrode 2103 of the driving transistor 210 are provided on the first gate insulating layer by means of Vias in layer 1501 are electrically connected to active region 2104 .
  • the sub-pixel may further include a storage capacitor 220 , the first pole of the storage capacitor 220 has a first part 2201 and a second part 2202 , wherein the first part 2201 and the gate 2101 of the driving transistor 210 are arranged in the same layer, and the second part 2202 and the driving transistor 210 The source electrode 2102 and the drain electrode 2103 are arranged in the same layer.
  • the second portion 2202 is electrically connected to the first portion 2201 through via holes provided in the second gate insulating layer 1502 and the interlayer insulating layer 1503 .
  • the second pole 2203 of the storage capacitor 220 is disposed between the second gate insulating layer 1502 and the interlayer insulating layer 1503 .
  • the second pole 2203 of the storage capacitor 220 may be provided with a via hole, and the first portion 2201 of the first pole of the storage capacitor 220 may pass through the via hole in the second pole 2203 and the second gate insulating layer 1502 and the interlayer insulating layer 1503
  • the vias in are connected to the second portion 2202.
  • the storage capacitor 220 may further include a semiconductor layer 2204, the semiconductor layer 2204 may be located on the side of the first portion 2201 of the first electrode of the storage capacitor 220 facing the base substrate 110, and the semiconductor layer 2204 may be provided in the same layer as the active region 2104.
  • the subpixels may also include light emitting elements 230 .
  • the light emitting element 230 is disposed on the side of the planarization layer 1504 away from the base substrate 110 .
  • the light emitting element 230 includes a first electrode 2301 , a second electrode 2303 , and a light emitting layer 2302 located between the first electrode 2301 and the second electrode 2303 .
  • the first electrode 2301 of the light emitting element 230 is electrically connected to the drain electrode 2103 of the driving transistor 210 through a via hole provided in the planarization layer 1504 .
  • the display panel may further include an encapsulation layer 160 .
  • the encapsulation layer 160 is located on the display circuit (eg, including at least one of the above-described sub-pixels, electrostatic discharge circuits, gate driving circuits, multiplexing circuits, and various signal lines and traces, etc.) away from the base substrate 110 . side.
  • the projection of the electrostatic discharge circuit described above on the base substrate 110 is within the projection of the encapsulation layer 110 on the base substrate. For example, in the above-mentioned FIG. 1A and FIG.
  • the projection of the encapsulation layer 160 on the base substrate 110 can cover the projection of the area surrounded by the encapsulation area PA on the base substrate 110 , so that the display area AA, multiplexing
  • the projections of the circuit 120 , the electrostatic discharge circuit 130 , and the gate driving circuit 140 on the base substrate 110 are all within the projection of the encapsulation layer 160 on the base substrate 110 .
  • the encapsulation layer 160 includes a first inorganic material layer 1601 , a second inorganic material layer 1603 , and an organic material layer 1602 between the first inorganic material layer 1601 and the second inorganic material layer 1603 .
  • the first inorganic material layer 1601 is located on the side of the organic material layer 1602 facing the base substrate 110
  • the second inorganic material layer 1603 is located on the side of the organic material layer 1602 away from the base substrate 110 .
  • the display panel further includes a pixel definition layer 1505 .
  • the pixel defining layer 1505 is located between the planarization layer 1504 and the light-emitting layer 2302 and covers the edge of the first electrode 2301 of the light-emitting element 230 .
  • a spacer 170 is further disposed on the side of the driving transistor 210 away from the base substrate 110 , and the spacer 170 is located between the pixel defining layer 1505 and the light-emitting layer 2302 .
  • FIG. 13B shows a cross-sectional view of the electrostatic discharge circuit of the display panel of FIG. 13A , wherein the cross-sectional view is taken along line Y-Y' of FIG. 12 . It can be seen in conjunction with FIG. 12 , FIG. 13B shows the gate and first pole of the third transistor T3 of the electrostatic discharge circuit in FIG. 12 and the second sub-section of the data trace DATAi connected to the first pole of the third transistor T3 Line DATAi_2.
  • the gate 1301 of the third transistor T3 and the gate 2101 of the driving transistor 210 in FIG. 13A are arranged in the same layer, and the first electrode 1302 of the third transistor T3 and the source 2102 and the drain of the driving transistor 210 2103 Same layer settings.
  • the second electrode of the third transistor T3 is also disposed in the same layer as the source electrode 2102 and the drain electrode 2103 of the driving transistor 210 .
  • the third transistor T3 in the electrostatic discharge circuit is taken as an example for schematic illustration above, but the embodiments of the present disclosure are not limited thereto. Other transistors of the electrostatic discharge circuit (for example, any one or more of the transistors T1 to T8 in FIG.
  • any one or more of the transistors T9 to T12 in FIG. 7 may have a similar layer structure as the third transistor T3, and the gate of each transistor in the electrostatic discharge circuit may be in the same layer as the gate 2101 of the driving transistor
  • the first electrode and the second electrode of each transistor in the electrostatic discharge circuit can be arranged in the same layer as the source electrode 2102 and the drain electrode 2103 of the driving transistor 210 .
  • At least a part of at least one data line among the plurality of data lines is disposed at the same layer as the second pole 2203 of the storage capacitor 220 in FIG. 3A or the gate 2101 of the driving transistor 210 .
  • the second sub-line DATAi_2 of the data line DATAi in FIG. 13B is arranged in the same layer as the second pole 2203 of the storage capacitor 220 in FIG. 13A .
  • the third sub-line DATAi_3 of the data wiring DATAi may also be disposed in the same layer as the second pole 2203 of the storage capacitor 220 in FIG. 13A .
  • the first sub-line DATAi_1 of the data trace DATAi may be disposed in the same layer as the gate electrode 2101 of the driving transistor 210 or the second electrode 2203 of the storage capacitor 220 in FIG. 13A .
  • the first sub-line DATAi_1 of the data line DATAi can be arranged in the same layer as the second pole 2203 of the storage capacitor 220 , and the first sub-line DATA( i+1)_1 may be disposed in the same layer as the gate electrode 2101 of the driving transistor 210 .
  • the embodiments of the present disclosure are not limited thereto, and the data lines may be arranged in different manners as required.
  • each of the data traces DATA1 , DATA2 , . . . DATAm may be disposed in the same layer as the gate electrode 2101 of the driving transistor 210 .
  • a reference electrode layer 310 is further provided between the electrostatic discharge circuit and the encapsulation layer 150 , and the reference electrode layer 310 may be provided in the same layer as the first electrode 2301 of the light emitting element 230 in FIG. 13A .
  • a positive voltage signal may be applied to the reference electrode layer 310 .
  • FIG. 13C shows a cross-sectional view of an encapsulation area of the display panel of FIG. 13A .
  • a dam (DAM) is provided in the package area PA, and the dam includes a groove in the first inorganic material layer 1601 and a groove in the second inorganic material layer 1603 and the groove matching bumps.
  • a first conductive layer 4101 is disposed in the encapsulation area PA, and the first conductive layer 4101 may be disposed in the same layer as the first electrode 2301 of the light emitting element 230 in FIG. 13A .
  • a first raised portion 4102 and a second raised portion 4103 are provided on the side of the first conductive layer 4101 away from the base substrate 110 , wherein the first raised portion 4102 covers the edge of the first conductive layer 4101 , and the second raised portion 4103 is located on the side of the first raised portion 4102 facing the display area AA.
  • the first protruding portion 4102 and the second protruding portion 4103 may be provided in the same layer as the planarization layer 1504 in FIG. 13A .
  • the package area PA is also provided with a second conductive layer 4104.
  • the second conductive layer 4104 covers a part of the first raised portion 4102, the second raised portion 4103, and the first conductive layer 4101 not covered by the first raised portion 4102 and the first raised portion 4102. The part covered by the two protruding parts 4103 .
  • the second conductive layer 4104 may be provided in the same layer as the source electrode 2102 and the drain electrode 2103 of the driving transistor 210 in FIG. 13A .
  • the side of the first protruding portion 4102 facing away from the base substrate 110 is provided with a third protruding portion 4105 ; the side of the second protruding portion 4103 facing away from the base substrate 110 is provided with a fourth protruding portion 4106 .
  • the third protruding portion 4105 covers the edge of the second conductor layer 4104 , and the fourth protruding portion 4106 is located between the second conductor layer 4104 and the first inorganic material layer 1601 .
  • a part of each of the third protruding part 4105 and the fourth protruding part 4106 may be provided in the same layer as the pixel defining layer 1505 in FIG. 13A , and the other part may be provided in the same layer as the spacer 170 in FIG.
  • the first inorganic material layer 1601 covers the edges of the first protrusions 4102 , the third protrusions 4105 , the fourth protrusions 4106 and the second conductive layer 4104 not covered by the third protrusions 4105 and the fourth protrusions 4106 the covered portion, thereby forming a groove in the package area PA.
  • the organic material layer 1602 terminates at the sidewall of the groove, and the second inorganic material layer 1603 covers the first inorganic material layer 1601 located in the encapsulation area PA, thereby forming a protrusion matching the groove.
  • the second inorganic material layer 1603 also covers the organic material layer 1602 on the side of the encapsulation area PA facing the AA area, thereby realizing encapsulation.
  • FIG. 14A illustrates a cross-sectional view of a display area of a display panel according to another embodiment of the present disclosure.
  • 14B illustrates a cross-sectional view of an electrostatic discharge circuit of the display panel of FIG. 14A.
  • the display panel of FIGS. 14A to 14C is similar to the display panel of FIGS. 13A to 13C , except that the base substrate and the encapsulation layer of the display panel of FIGS. 14A to 14C are rigid rather than flexible. In order to simplify the description, the following will mainly describe the different parts in detail.
  • the layer structure of the display area of the display panel shown in FIG. 14A is similar to that of FIG. 13A
  • the layer structure of the area where the electrostatic discharge circuit of the display panel shown in FIG. 14B is located is similar to that of FIG. 13B .
  • the base substrate 110 ′ of the display panel of FIGS. 14A and 14B is rigid, except that the base substrate 110 ′ includes the first flexible layer 1101 and the first barrier layer 1102 which are stacked in sequence.
  • the second flexible layer 1103 , the second barrier layer 1104 and the buffer layer 1105 a glass substrate 1106 is also included.
  • the glass substrate 1106 is located on the side of the first flexible layer 1101 away from the first barrier layer 1102 .
  • the encapsulation layer 180 ′ of the display substrate of FIGS. 14A and 14B is also rigid, and the encapsulation layer 180 ′ may be a glass cover plate, which is disposed on the display circuit (including the above-mentioned sub-pixels, the multiplexing circuit 120 , the electrostatic discharge circuit 130 , etc. ) facing away from the side of the base substrate 110'.
  • the encapsulation layer 180' may cover the area formed around the encapsulation area PA as shown in FIGS. 1A and 1B .
  • the layer structure of the encapsulation area of the display panel shown in FIG. 14C is different from that of FIG. 13C , because the display panels of FIGS. 14A to 14C are rigid display panels, which adopt a different packaging method than the flexible display panels.
  • an adhesive layer 5101 is provided in the packaging area PA, and the adhesive layer 5101 is located on the side of the cover glass 180' facing the base substrate 110'.
  • the material of the adhesive layer 5101 may include, but is not limited to, frit glue.
  • the adhesive layer 5101 may include a plurality of protrusions 51011 , and the plurality of protrusions 51011 may extend to the first through vias disposed in the second gate insulating layer 1502 and the interlayer dielectric layer 1503 in the gate insulating layer 1501. By providing a plurality of protrusions 51011, the adhesive strength of the adhesive layer 5101 can be increased.
  • a third conductor layer 5102 and a fourth conductor layer 5103 may also be disposed in the package area PA.
  • the third conductor layer 5102 may be disposed in the same layer as the gate electrode 2101 of the driving transistor 210 in FIG. 13A
  • the fourth conductor layer 5103 may be disposed in the same layer as that in FIG. 13A .
  • the source electrode 2102 and the drain electrode 2103 of the middle driving transistor 210 are arranged in the same layer.
  • the third conductor layer 5102 is located between the first gate insulating layer 1501 and the second gate insulating layer 1502, and via holes may be provided in the third conductor layer 5102, so that the protrusions 51011 of the adhesive layer 1501 can pass through Vias in the third conductor layer 5102 extend into the first gate insulating layer 1501 .
  • the fourth conductor layer 5103 may be located at an edge region of the encapsulation area PA facing the display area AA, and the edge of the fourth conductor layer 1503 is covered by the adhesive layer 5101 .
  • the fourth conductor layer 5103 may be connected to the third conductor layer 5102 through via holes provided in the second gate insulating layer 1502 and the interlayer dielectric layer 1503 .
  • the reference voltage VSS may be applied to at least one of the fourth conductor layer 5103 and the third conductor layer 5102 .
  • the protruding portion 51011 of the adhesive layer 5101 in the above-mentioned embodiment extends to a specific position (for example, to a certain depth in the first gate insulating layer 1501 ), the embodiment of the present disclosure is not limited thereto, and the protruding portion 51011 may be It needs to be extended to different positions, for example, it can extend into the second gate insulating layer 1502 , or extend to a deeper position into the first gate insulating layer 1501 .
  • the third conductor layer 5102 in the package area PA is a conductor layer disposed in the same layer as the gate electrode 2101 of the driving transistor 210 in the above embodiments, the embodiments of the present disclosure are not limited thereto.
  • the third conductor layer 5102 may be a conductor layer disposed in the same layer as the second electrode 2203 of the storage capacitor 220 , or a conductor layer disposed in the same layer as the source electrode 2102 and the drain electrode 2103 of the driving transistor 210 .
  • FIG. 15 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel of FIG. 15 is similar to the display panel of FIGS. 1A and 1B , except that the projection of the display area AA on the base substrate has a rounded rectangular outline instead of a circular outline.
  • the following will mainly describe the different parts in detail.
  • the display panel 100C includes a base substrate 110C and an electrostatic discharge circuit 130C disposed in a region between the display area AA and the packaging area PA of the base substrate 110C.
  • the above description of the base substrate and electrostatic discharge circuit of any embodiment is equally applicable to the base substrate 110C and electrostatic discharge circuit 130C of FIG. 15 .
  • the projection of the display area AA of the display panel 100C on the base substrate 110C has a rounded rectangular outline.
  • the electrostatic discharge circuit 130C is located on one side of the display area AA along the y direction.
  • the rounded rectangular outline of the display area AA facing the electrostatic discharge circuit 130C has two arcuate edges and a straight edge extending along the x direction.
  • a part of the plurality of electrostatic discharge units in the electrostatic discharge circuit 130C are arranged along the two arc-shaped edges of the display area AA, and the other part of the plurality of electrostatic discharge units are arranged in a straight line along the straight edge of the display area AA, thereby forming a configuration as shown in FIG. 15 .
  • the electrostatic discharge units arranged around the arc-shaped portion may be arranged in a stepped manner in a manner similar to that shown in FIG. 4 , or in an arc-shaped manner in a manner similar to that shown in FIG. 8 .
  • the electrostatic discharge units arranged in a straight line may be arranged along the x direction, and the first reference axis ay and the second reference axis ax of each electrostatic discharge unit may be parallel to the x direction and the y direction, respectively.
  • the gate driving circuit may be disposed on both sides of the display area AA along the x-direction, and between the packaging area PA and the display area AA.
  • the multiplexing circuit may be located between the display area AA and the electrostatic discharge circuit 130C, and arranged in a manner similar to the electrostatic discharge circuit 130C.
  • FIG. 16 shows a schematic diagram of a display panel according to yet another embodiment of the present disclosure.
  • the display panel of FIG. 16 is similar to the display panel of 15, except that the projection of the display area AA on the base substrate has a rectangular outline instead of a circular outline.
  • the display panel 100C includes a base substrate 110D and an electrostatic discharge circuit 130D disposed in a region between the display area AA and the packaging area PA of the base substrate 110D.
  • the above description of the base substrate and the electrostatic discharge circuit of any embodiment is equally applicable to the base substrate 110D and the electrostatic discharge circuit 130D of FIG. 16 . Different from FIG. 15 , the display area AA of FIG.
  • each electrostatic discharge unit may have a first reference axis ay and a second reference axis ax, and the first reference axis ay and the second reference axis ax of each electrostatic discharge unit may be parallel to the x direction, respectively and the y direction.
  • FIG. 17 shows a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 1700 includes a display panel 1701 .
  • the display panel 1701 may be implemented by the display panel of any of the above-described embodiments.
  • the display device 1700 may further include a flexible circuit board and a control chip.
  • the flexible circuit board is bonded to the bonding area of the display panel, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby being connected to the display area. electrical connection.
  • control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), or the like.
  • the control chip may further include a memory, a power supply module, etc., and implement power supply and signal input and output functions through additionally provided wires, signal wires, and the like.
  • the control chip may also include hardware circuits, computer executable codes, and the like.
  • Hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays as well as off-the-shelf semiconductors such as logic chips, transistors, or other discrete components; hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • VLSI very large scale integration
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种显示面板（100A）和显示装置（1700）。该显示面板（100A）包括：衬底基板（110），包括显示区（AA）和围绕该显示区（AA）的周边区（SA）；多个子像素，位于该衬底基板（110）上且位于该显示区（AA）中，该多个子像素呈阵列排布；多条数据信号线，位于该显示区（AA）且与该多个子像素电连接，该多条数据信号线被配置为向该多个子像素传递数据信号；多条数据走线（DATA），位于该周边区（SA）且与该多条数据信号线电连接；静电放电电路（130），位于该衬底基板（110）上且位于该周边区（SA），该静电放电电路（130）与该多条数据走线（DATA）电连接；以及封装层（160），位于该多个子像素和该静电放电电路（130）远离该衬底基板（110）的一侧，该静电放电电路（130）在该衬底基板（110）的正投影位于该封装层（160）在该衬底基板（110）的正投影内。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
对于显示产品来说，生产、使用等过程中产生的静电会影响显示质量，甚至使显示产品损坏。为此，通常在显示面板中设置静电放电(ESD，Electrostatic Discharge)电路对显示面板内部电路进行保护。但是传统技术中静电放电电路的放电效果不理想。
发明内容
本公开的实施例提供了一种显示面板，包括：
衬底基板，包括显示区和围绕所述显示区的周边区；
多个子像素，位于所述衬底基板上且位于所述显示区中，所述多个子像素呈阵列排布；
多条数据信号线，位于所述显示区且与所述多个子像素电连接，所述多条数据信号线被配置为向所述多个子像素传递数据信号；
多条数据走线，位于所述周边区且与所述多条数据信号线电连接；
静电放电电路，位于所述衬底基板上且位于所述周边区，所述静电放电电路与所述多条数据走线电连接；以及
封装层，位于所述多个子像素和所述静电放电电路远离所述衬底基板的一侧，所述静电放电电路在所述衬底基板的正投影位于所述封装层在所述衬底基板的正投影内。
例如，所述周边区的边缘包括围绕所述显示区的环状的封装区，所述封装区内设有环形的坝部，所述静电放电电路位于所述封装区与所述显示区之间。
例如，所述封装层包括第一无机材料层、第二无机材料层以及位于所述第一无机材料层和所述第二无机材料层之间的有机材料层，其中，所述有机材料层位于所述环形的坝部围成的区域内，所述第一无机材料层和所述第二无机材料层位于所述坝部远离所述衬底基板的一侧。
例如，所述封装层包括盖板；并且
所述周边区的边缘包括围绕所述显示区的环状的封装区，所述封装区内设有粘合层，所述粘合层位于所述盖板面向所述衬底基板的一侧，所述静电放电电路位于所述封装区与所述显示区之间。
例如，所述静电放电电路包括多个静电放电单元，所述多个静电放电单元分别与所述多条数据走线电连接，所述多个静电放电单元中的至少一部分静电放电单元沿着所述显示区的边缘排列。
例如，所述显示区面向所述静电防护电路一侧的边缘具有至少一个弧形部分，所述多个静电放电单元中的至少一部分静电放电单元沿着所述至少一个弧形部分排列。
例如，所述至少一部分静电放电单元各自具有第一参考轴和垂直于所述第一参考轴的第二参考轴，所述至少一部分静电放电单元中每个静电放电单元的第一参考轴平行于与该静电放电单元相邻的弧形部分的法线方向，所述至少一部分静电放电单元中每个静电放电单元的第二参考轴平行于与该静电放电单元相邻的弧形部分的切线方向。
例如，所述至少一部分静电放电单元各自具有第一参考轴和垂直于所述第一参考轴的第二参考轴，所述第一参考轴平行于第一方向，所述第二参考轴平行于第二方向，其中所述第一方向为所述阵列的行方向，所述第二方向为所述阵列的列方向。
例如，所述显示区具有圆形轮廓，所述多个静电放电单元沿着所述圆形轮廓面向所述静电放电电路一侧的弧形边缘排列。
例如，所述显示区具有圆角矩形轮廓，所述多个静电放电单元中的一部分静电放电单元沿着所述圆角矩形轮廓面向所述静电放电电路一侧的圆角的弧形边缘排列，所述多个静电放电单元中的另一部分静电放电单元沿着所述圆角矩形轮廓的面向所述静电放电电路一侧的直线边缘排列。
例如，所述显示区具有矩形轮廓，所述多个静电放电单元沿着所述矩形轮廓面向所述静电放电电路一侧的直线边缘排列。
例如，所述显示面板还包括：
第一电源信号线，位于所述静电放电电路与所述显示区之间，并且与所述静电放电电路电连接；以及
第一参考信号线，位于所述静电放电电路与所述封装区之间，并且与所述静电放电电路电连接，所述第一电源信号线的电压高于所述第一参考信号线的电压。
例如，每个静电放电单元的电源信号端与所述第一电源信号线电连接，每个静电放电单元的参考信号端与所述第一参考信号线电连接，每个静电放电单元的输出端与 所述多条数据走线中的至少一条数据走线电连接。
例如，所述显示面板还包括：
栅极驱动电路，所述栅极驱动电路位于所述显示区与所述静电放电电路之间；
多条栅极信号线，位于所述显示区内且与所述多个子像素电连接，所述栅极驱动电路通过所述多条栅极信号线与所述显示区的所述多个子像素电连接；
第二电源信号线，位于所述栅极驱动电路与所述第一参考信号线之间，并且与所述栅极驱动电路电连接；
第二参考信号线，位于所述第二电源信号线与所述栅极驱动电路之间，并且与所述栅极驱动电路电连接，所述第二电源信号线的电压高于所述第二参考信号线的电压。
例如，所述显示面板还包括：
栅极驱动电路，所述栅极驱动电路位于所述显示区与所述封装区之间，并且通过所述多条栅极信号线与所述显示区的所述多个子像素电连接，所述静电放电电路位于所述栅极驱动电路面向所述封装区的一侧；
第二电源信号线，位于所述栅极驱动电路与所述静电放电电路之间，并且与所述栅极驱动电路和所述静电放电电路电连接；
第二参考信号线，位于所述第二电源信号线与所述栅极驱动电路之间，并且与所述栅极驱动电路和所述静电放电电路电连接，
其中，每个静电放电单元的电源信号端与所述第二电源信号线电连接，每个静电放电单元的参考信号端与所述第二参考信号线电连接，每个静电放电单元的输出端与所述多条数据走线中的至少一条数据走线电连接。
例如，所述显示面板还包括：
多路复用电路，位于所述显示区与所述封装区之间，所述多条数据走线通过所述多路复用电路与所述多条数据信号线电连接；以及
K条选择信号线，位于所述多路复用电路与所述静电放电电路之间，与所述多路复用电路电连接，其中K为大于1的整数，
其中，所述多路复用电路包括多个多路复用单元，其中第i多路复用单元的输入端和第i静电放电单元的输出端连接所述多条数据走线中的第i数据走线，第i多路复用单元的K个输出端分别连接所述多条数据信号线中的K条数据信号线，第i多路复用单元的K个控制信号端分别连接所述K条选择信号线，其中i为大于或等于1的整数。
例如，每个静电放电单元包括第一静电放电子单元和第二静电放电子单元，每个 多路复用单元包括第一多路复用子单元和第二多路复用子单元，每条数据走线包括第一子线、第二子线和第三子线，其中，
第i数据走线的第一子线连接至第i静电放电单元的第一静电放电子单元的输入端和第二静电放电子单元的输入端；
第i数据走线的第二子线连接在第i静电放电单元的第一静电放电子单元的输入端与第i多路复用单元的第一多路复用子单元的输入端之间；
第i数据走线的第三子线连接在第i静电放电单元的第二静电放电子单元的输入端与第i多路复用单元的第二多路复用子单元的输入端之间。
例如，所述第一静电放电子单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极电连接作为所述第一静电放电子单元的电源信号端，所述第一晶体管的第二极与所述第二晶体管的栅极和所述第二晶体管的第一极电连接，所述第二晶体管的第二极与所述第三晶体管的栅极和所述第三晶体管的第一极电连接作为所述第一静电放电子单元的输出端，所述第三晶体管的第二极与所述第四晶体管的栅极和所述第四晶体管的第一极电连接，所述第四晶体管的第二极作为所述第一静电放电子单元的参考信号端；
所述第二静电放电子单元包括第五晶体管、第六晶体管、第七晶体管和第八晶体管，所述第五晶体管的栅极和所述第五晶体管的第一极电连接作为所述第二静电放电子单元的电源信号端，所述第五晶体管的第二极与所述第六晶体管的栅极和所述第六晶体管的第一极电连接，所述第六晶体管的第二极与所述第七晶体管的栅极和所述第七晶体管的第一极电连接作为所述第二静电放电子单元的输出端，所述第七晶体管的第二极与所述第八晶体管的栅极和所述第八晶体管的第一极电连接，所述第八晶体管的第二极作为所述第二静电放电子单元的参考信号端。
例如，每个静电放电单元包括第九晶体管、第十晶体管、第十一晶体管和第十二晶体管，其中，
所述第九晶体管的栅极和所述第九晶体管的第一极电连接作为所述静电放电单元的电源信号端，所述第九晶体管的第二极与所述第十晶体管的栅极和所述第十晶体管的第一极电连接，所述第十晶体管的第二极与所述第十一晶体管的栅极和所述第十一晶体管的第一极电连接作为所述静电放电单元的输出端，所述第十一晶体管的第二极与所述第十二晶体管的栅极和所述第十二晶体管的第一极电连接，所述第十二晶体管的第二极作为所述静电放电单元的参考信号端。
例如，所述显示面板还包括：
第一时钟信号线，位于所述第二电源信号线与所述第二参考信号线之间，并且与所述栅极驱动电路电连接；以及
第二时钟信号线，位于所述第一时钟信号线与所述第二电源信号线之间，并且与所述栅极驱动电路电连接。
例如，所述多个子像素中的至少一个子像素包括驱动晶体管，所述驱动晶体管包括栅极、源极和漏极；
每个静电放电单元包括多个晶体管，其中每个晶体管的栅极与所述驱动晶体管的栅极同层设置，每个晶体管的第一极和第二极与所述驱动晶体管的源极和漏极同层设置。
本公开实施例还提供了一种显示装置，包括上述显示面板。
附图说明
图1A示出了根据本公开一实施例的显示面板的示意图。
图1B示出了根据本公开另一实施例的显示面板的示意图。
图2示出了根据根据本公开实施例的显示面板中的显示区的示意图。
图3示出了根据本公开实施例的显示面板的电路原理图。
图4示出了根据本公开一实施例的显示面板中静电放电电路的示意布局图。
图5示出了图1B的显示面板的区域XX的示例的布局图。
图6示出了图5所示区域的电路原理图。
图7示出了图5所示区域的电路图。
图8示出了根据本公开一实施例的显示面板中静电放电电路的示意布局图。
图9示出了图1B的显示面板的区域XX的另一示例的布局图。
图10示出了图9所示区域的电路原理图。
图11示出了图9所示区域的电路图。
图12示出了图9中的静电放电电路的放大布局图。
图13A示出了根据本公开一实施例的显示面板的显示区的截面图。
图13B示出了图13A的显示面板的静电放电电路的截面图。
图13C示出了图13A的显示面板的封装区的截面图。
图14A示出了根据本公开另一实施例的显示面板的显示区的截面图。
图14B示出了图14A的显示面板的静电放电电路的截面图。
图14C示出了图14A的显示面板的封装区的截面图。
图15示出了根据本公开另一实施例的显示面板的示意图。
图16示出了根据本公开又一实施例的显示面板的示意图。
图17示出了根据本公开实施例的显示装置的示意图。
具体实施方式
虽然将参照含有本公开的较佳实施例的附图充分描述本公开，但在此描述之前应了解本领域的普通技术人员可修改本文中所描述的公开，同时获得本公开的技术效果。因此，须了解以上的描述对本领域的普通技术人员而言为一广泛的揭示，且其内容不在于限制本公开所描述的示例性实施例。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
图1A示出了根据本公开一实施例的显示面板的示意图。
如图1A所示，显示面板100A包括衬底基板110和静电放电电路130。衬底基板110设有显示区AA和围绕所述显示区的周边区SA，在所述周边区SA的边缘包括围绕所述显示区AA的环状的封装区PA。显示区AA内设有多个子像素，静电放电电路130位于显示区AA与封装区PA之间。在图1A中，显示区AA在衬底基板110上的投影具有圆形轮廓，静电放电电路130均沿y方向位于显示区AA的一侧，并且围绕显示区AA的弧形边缘的一部分。然而本公开的实施例不限于此，显示区AA可以根据需要而设计成具有其他形状的轮廓，例如椭圆形、矩形、圆角矩形、甚至不规则形状。在图1A中，衬底基板110与显示区AA的轮廓形状相同，均为圆形。然而本公开的实施例不限于此，衬底基板110的轮廓形状可以与显示区AA不同。例如，衬底基板110除了包括如图1A所示的圆形部分以外，还可以包括分别位于圆形部分两侧的两个矩形部分，例如以用于诸如手表之类的异形显示设备。
显示面板100A还包括位于周边区SA的多条数据走线DATA，多条数据走线DATA位于所显示区AA的一侧，可以通过显示区AA内的数据信号线与显示区AA内的子像素电连接。静电放电电路130与所述多条数据走线DATA电连接，以用于释放所述多条数据走线DATA上的静电。数据走线DATA可以从显示面板110引出，以便与驱动IC 电连接。在一些实施例中，显示面板100A还可以包括多路复用电路120。多路复用电路120与所述多条数据走线DATA电连接，多路复用电路120可以将所述多条数据走线DATA上的m路输入数据信号复用成M路输出数据信号并通过显示区AA内的数据信号线提供给显示区AA中的多个子像素，其中m和M均为大于1的整数，M是m的整数倍。
传统技术中静电放电电路通常位于封装区的***区域，例如位于封装区***的柔性电路板上，一方面使得静电放电电路与显示区之间的数据走线的长度过长，静电放电效果不理想，另一方面静电放电电路容易损坏。本公开实施例的实施例通过将静电放电电路设置在封装区PA与显示区AA之间的区域内，一方面缩短静电放电电路与AA区像素之间的数据走线的长度，提高静电放电质量；另一方面使静电放电电路可以受到封装区内的封装保护，降低电路损坏的风险。
图1B示出了根据本公开另一实施例的显示面板的示意图。图1B的显示面板100B与上述显示面板100A类似，区别至少在于显示面板100B还包括栅极驱动电路140，以上对于显示面板100A的描述同样适用于显示面板100B。为了简明起见，下面主要对区别部分进行详细说明。如图1B所示，栅极驱动电路140位于显示区AA与封装区PA之间，静电放电电路120位于栅极驱动电路140靠近AA区的一侧。栅极驱动电路140可以通过多条栅极信号线与显示区AA的多个子像素电连接，下文将对此进一步详细说明。在图1B中，栅极驱动电路140围绕显示区AA的整个边缘设置，多路复用电路120设置在栅极驱动电路140与显示区AA之间的区域。然而本公开的实施例不限于此，栅极驱动电路140和多路复用电路130可以根据需要以其他方式布局。
图2示出了根据本公开实施例的显示面板中的显示区的示意图。
如图2所示，显示区AA中设置有多个子像素Pxl，所述多个子像素布Pxl布置成阵列的形式。在图2中，多个子像素Pxl排列成N行M列，以行方向作为x方向(第二方向)，以列方向作为y方向(第一方向)。如图2所示，多个行之间子像素数量不同且多个列之间子像素数量不同，使得阵列整体上呈圆形，从而使显示区AA在衬底基板110上的投影具有圆形轮廓。然而本公开的实施例不限于此，多个子像素Pxl可以根据需要排列成其他形状的阵列，例如矩形、圆角矩形等等。
显示区AA中还设置有与所述多个子像素Pxl电连接的多条栅极信号线G1，G2，…GN。显示区AA中还设置有与所述多个子像素Pxl电连接的多条数据信号线D1，D2，…DM。在图2中，N行子像素Pxl与N条栅极信号线G1，G2，…GN一一对应地 连接，M列子像素Pxl与M条数据信号线D1，D2，…DM一一对应地连接，也就是说每行子像素连接一条栅极信号线，每列子像素连接一条数据信号线。然而本公开的实施例不限于此，栅极信号线和数据信号线的数量和连接方式可以根据需要来选择，例如可以每行子像素连接两条栅极信号线，栅极信号线的数量是子像素行数的两倍；或者每两列子像素连接一条数据信号线，数据信号线的数量是子像素列数的二分之一，等等。
图3示出了根据本公开实施例的显示面板的电路原理图。
如图3所示，多路复用电路120包括多个多路复用单元MUX1，MUX2，…MUXm，图3中m＝3。多路复用单元MUX1，MUX2，…MUXm分别与数据走线DATA1，DATA2，…DATAm电连接。在图3中，每个多路复用单元MUX1，MUX2，…MUXm可以为一分六多路复用单元，即，每个多路复用单元可以将一路输入数据信号复用成6路输出数据信号分别提供给6条数据信号线。例如，多路复用电路MUX1的输入端连接数据走线DATA1，多路复用电路MUX1的输出端连接数据信号线D1至D6，多路复用电路MUX1可以将数据走线DATA1处的输入数据信号复用成六路输出数据信号分别提供给数据信号线D1至D6；以类似的方式，多路复用电路MUX2可以将数据走线DATA2处的输入数据信号复用成六路输出数据信号分别提供给数据信号线D7至D12，以此类推。通过这种方式，多路复用电路120可以将m条数据走线DATA上的m路输入数据信号复用成M路输出数据信号并分别提供给M条数据信号线D1至DM，从而提供给显示区AA中的M列子像素，其中M＝6m，在图3中m＝3，M＝18。
静电放电电路130可以包括多个静电放电单元ESD1，ESD2，…ESDm，在图3中m＝3。静电放电单元ESD1，ESD2，…ESDm分别与数据走线DATA1、DATA2，…DATAm电连接。例如静电放电单元ESD1与数据走线DATA1电连接，以用于释放数据走线DATA1上的静电；静电放电单元ESD2与数据走线DATA2电连接，以用于释放数据走线DATA2上的静电，以此类推。
栅极驱动电路140包括多个移位寄存器单元GOA1，GOA2，…GOAN。移位寄存器单元GOA1，GOA2，…GOAN分别与栅极信号线G1，G2，…GN电连接。例如移位寄存器单元GOA1与栅极信号线G1电连接，移位寄存器单元GOA2与栅极信号线G2电连接，以此类推，从而实现栅极驱动电路140与显示区AA的所述多行子像素Pxl的电连接。
虽然图3中为了便于描述以N＝4，m＝3，M＝12为例进行了示意，然而本公开的实 施例不限于此，m、M和N的数值可以根据需要来进行设置。
虽然上述实施例中以一分六形式的多路复用电路为例进行了说明，然而本公开的实施例不限于此，多路复用电路的类型可以根据需要来选择，例如可以采用一分二型多路复用电路、一分四型多路复用电路，等等。
虽然上述实施例中以3条数据走线为例进行了说明，然而本公开的实施例不限于此，数据走线的数量可以根据需要来选择。静电放电单元的数量和多路复用单元的数量可以均与数据走线的数量相等，也可以不等。
图4示出了根据本公开一实施例的显示面板中静电放电电路的示意布局图。图4的静电放电电路的布局适用于上述任意实施例的显示面板。
如图4所示，显示区AA在衬底基板110的投影具有圆形轮廓，多个静电放电单元ESD1，ESD2，…ESDm沿着显示区AA的圆形轮廓的弧形边缘排列，从而围绕显示区AA的一部分。图4为了便于描述示出了7个静电放电单元，然而本领域技术人员应了解，本公开的实施例不限于此。每个静电放电单元ESDi可以具有第一参考轴ay和垂直于所述第一参考轴ay的第二参考轴ax，其中i为整数，1≤i≤m。在图4中，静电放电单元ESDi在衬底基板110的投影可以具有大体呈矩形的轮廓，可以将矩形轮廓的平行于其短边的对称轴作为第一参考轴ay，将矩形轮廓的平行于其长边的对称轴作为第二参考轴ax。如图4所示，每个静电放电单元的第一参考轴ay平行于y方向，第二参考轴ax平行于x方向，使得静电放电单元ESD1，ESD2，…ESDm沿着与显示区AA的轮廓大体共形的轨迹(如图4中的虚线所示)呈阶梯状排列。
图5示出了图1B的显示面板的区域XX的示例的布局图。图6示出了图5所示区域的电路原理图。
如图5所示，显示面板包括静电放电单元ESD1，ESD2，…ESDm、多路复用单元MUX1，MUX2，…MUXm和移位寄存器单元GOA1，GOA2，…GOAN。为了便于说明，图5中对其中两个静电放电单元ESDi、ESD(i+1)、两个多路复用单元MUXi、MUX(i+1)和两个移位寄存器单元GOAj、GOA(j+1)用虚线框进行了标记。
在图5中，静电放电单元ESD1，ESD2，…ESDm以如图4所示的方式沿着与显示区AA的弧线边缘(如图5中的点划线所示)大体共形的第一轨迹呈阶梯状排列。多路复用单元MUX1，MUX2，…MUXm以类似于静电放电单元ESD1，ESD2，…ESDm的方式沿着与显示区AA的边缘大体共形的第二轨迹呈阶梯状排列。移位寄存器单元GOA1，GOA2，…GOAN以类似于静电放电单元ESD1，ESD2，…ESDm的方式沿着与显示区AA 的边缘大体共形的第三轨迹呈阶梯状排列。在图5中，第一轨迹、第二轨迹和第三轨迹是三条并行延伸的轨迹，第二轨迹位于显示区AA与第一轨迹之间，第三轨迹位于第二轨迹与第一轨迹之间。
如图5和图6所示，衬底基板110上还设置有第二电源信号线VGH和第二参考信号线VGL。第二电源信号线VGH位于栅极驱动电路140(包括移位寄存器单元GOA1，GOA2，…GOAN)与静电放电电路130(包括静电放电单元ESD1，ESD2，…ESDm)之间，第二参考信号线VGL位于第二电源信号线VGH与栅极驱动电路140之间。图6中为了简明起见，以单个的移位寄存器单元GOAj、多路复用单元MUXi和静电放电单元ESDi为例进行了示意说明。栅极驱动电路140和静电放电电路130共用第二电源信号线VGH和第二参考信号线VGL。如图5和图6所示，每个移位寄存器单元GOA1，GOA2，…GOAN的电源信号端与第二电源信号线VGH电连接，每个移位寄存器单元GOA1，GOA2，…GOAN的参考信号端与第二参考信号线VGL电连接；每个静电放电单元ESD1，ESD2，…ESDm的电源信号端与第二电源信号线VGH电连接，每个静电放电单元ESD1，ESD2，…ESDm的参考信号端与第二参考信号线VGL电连接。
如图5和图6所示，衬底基板110上还设置有第一时钟信号线CK和第二时钟信号线CB。第一时钟信号线CK位于第二电源信号线VGH与第二参考信号线VGL之间，第二时钟信号线CB位于第一时钟信号线CK与第二电源信号线VGH之间。栅极驱动电路140中每个移位寄存器单元均GOA1，GOA2，…GOAN与第一时钟信号线CK和第二时钟信号线CB电连接。例如在图5中，寄存器单元均GOAj的第一时钟信号端与第一时钟信号线CK电连接，第二时钟信号端与第二时钟信号线CB电连接；寄存器单元均GOA(j+1)的第一时钟信号端与第二时钟信号线CB电连接，第二时钟信号端与第一时钟信号线CK电连接，以此类推。每个移位寄存器单元(例如GOAj)基于所连接的第一时钟信号线CK和第二时钟信号线CB处的时钟信号向所连接的栅极信号线(例如Gj)提供栅极驱动信号。
如图5和图6所示，衬底基板110上还设置有K条选择信号线Mux1至MuxK，在图5和图6中K＝6。选择信号线Mux1至Mux6位于多路复用电路120(包括多路复用单元MUX1，MUX2，…MUXm)与静电放电电路130(包括静电放电单元ESD1，ESD2，…ESDm)之间，在图5中位于多路复用电路120的多路复用单元MUX1，MUX2，…MUXm与栅极驱动电路140的移位寄存器单元GOA1，GOA2，…GOAN之间。选择信号线Mux1至Mux6与多路复用电路120电连接。如图5和图6所示，第i多路复 用单元MUXi的6个控制信号端分别连接6条选择信号线Mux1至Mux6，第i多路复用单元MUXi的输入端连接第i数据走线DATAi，第i多路复用单元的6个输出端分别连接6条数据信号线Di1至Di6(例如i＝1的情况下，Di1至Di6分别为D1至D6，在i＝2的情况下，Di1至Di6分别为D6至D12，以此类推)，其中i为大于或等于1的整数。第i静电放电单元ESDi的输出端也连接第i数据走线DATAi。
在图5和图6中，第二电源信号线VGH、第二参考信号线VGL、第一时钟信号线CK、第二时钟信号线CB以及选择信号线Mux1至Mux6均以折线形式延伸，折线的拐角可以例如为90度，以适应多路复用单元、移位寄存器单元和静电放电单元的布局。
图7A示出了图5所示区域的电路图，其中示出了每个多路复用单元和静电放电单元的电路结构。如图7A所示，多路复用单元MUXi和静电放电单元ESDi均连接数据走线DATAi。
多路复用单元MUXi包括晶体管Tm1至Tm6，其中晶体管Tm1至Tm6的栅极与选择信号线Mux1至Mux6一一对应地电连接，晶体管Tm1至Tm6的第一极均连接至数据走线DATAi，晶体管Tm1至Tm6的第二极与6条数据信号线Di1至Di6一一对应地电连接。当选择信号线Mux1处的信号为高电平时，晶体管Tm1导通，从而将数据走线DATAi处的数据信号提供至数据信号线Di1；当选择信号线Mux2处的信号为高电平时，晶体管Tm2导通，从而将数据走线DATAi处的数据信号提供至数据信号线Di2，以此类推，使得多路复用单元MUXi可以将数据走线DATAi处的一路输入数据信号复用成6路输出数据信号分别提供给6条数据信号线Di1至Di6。
图7B示出了图7A中的静电放电单元ESDi的布局图。如图7A和图7B所示，静电放电单元ESDi包括第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12。第九晶体管T9的栅极和第一极连电连接，以作为静电放电单元ESDi的电源信号端与第二电源信号线VGH连接。第九晶体管T9的第二极与第十晶体管T10的栅极和第一极电连接。第十晶体管T10的第二极与第十一晶体管T11的栅极和第一极电连接，以作为静电放电单元ESDi的输出端与数据走线DATAi连接。第十一晶体管T11的第二极与第十二晶体管T12的栅极和第一极电连接。第十二晶体管T12的第二极作为所静电放电单元ESDi的参考信号端与第二参考信号线VGL连接。当数据走线DATAi处的电位高于第二电源信号线VGH的电位时，第九晶体管T9和第十晶体管T10导通，从而利用第二电源信号线VGH的电位来释放数据走线DATAi处的高电压静电；当数据走线DATAi处的电位低于第二参考信号线VGL的电位时，第十一晶体 管T11和第十二晶体管T12导通，从而利用第二参考信号线VGL的电位来释放数据走线DATAi处的低电压静电。
图8示出了根据本公开一实施例的显示面板中静电放电电路的示意布局图。图8中显示区AA在衬底基板的投影形状和静电放电电路的排列与图4类似，区别至少在于静电放电单元的摆放角度。为了简化描述，下面将主要对区别部分进行详细说明。如图8所示，与图4类似，显示区AA在衬底基板的投影具有圆形轮廓，静电放电单元ESD1，ESD2，…ESDm沿着所述圆形轮廓一侧的弧形边缘排列，包围所述圆形轮廓的一部分。与图4不同的是，图8中每个静电放电单元的第一参考轴ay平行于所述圆形轮廓与该静电放电单元相邻的弧形部分的法线AY，每个静电放电单元的第二参考轴ax平行于与该静电放电单元相邻的弧形部分的切线AX。通过这种方式，使得静电放电单元ESD1，ESD2，…ESDm沿着与显示区AA的轮廓大体共形的轨迹(如图4中的虚线所示)呈阶弧线形排列。
图9示出了图1B的显示面板的区域XX的另一示例的布局图。图10示出了图9所示区域的电路原理图。图9和图10所示的显示面板与图5和图6所示的显示面板类似，区别至少在于静电放电单元、移位寄存器单元和多路复用单元的摆放角度，并且图9和图10的显示面板中静电放电电路连接单独的一组第一电源信号线VGH’和第一参考信号线VGL’，而不是与栅极驱动电路共用第二电源信号线VGH和第二参考信号线VGL。为了简化描述，下文将主要对区别部分进行详细说明。
类似于图5和图6，图9和图10的显示面板包括静电放电单元ESD1，ESD2，…ESDm、多路复用单元MUX1，MUX2，…MUXm和移位寄存器单元GOA1，GOA2，…GOAN。为了便于说明，图9对其中一个静电放电单元ESDi、一个多路复用单元MUXi和一个移位寄存器单元GOAj用虚线框进行了标记。
与图5不同的是，图9的静电放电单元ESD1，ESD2，…ESDm以如图8所示的方式沿着与显示区AA的弧线边缘(如图9中的点划线所示)大体共形的第一轨迹呈弧线形排列。移位寄存器单元GOA1，GOA2，…GOAN以类似于静电放电单元ESD1，ESD2，…ESDm的方式沿着与显示区AA的边缘大体共形的第二轨迹呈弧线形排列。多路复用单元MUX1，MUX2，…MUXm也沿着第二轨迹以类似于静电放电单元ESD1，ESD2，…ESDm的方式排列，其中多路复用单元MUX1，MUX2，…MUXm分布在移位寄存器单元GOA1，GOA2，…GOAN彼此之间的间隙中。在图9中，第一轨迹和第二轨迹是两条并行延伸的轨迹，第二轨迹位于显示区AA与第一轨迹之间。
类似于图5和图6，图9和图10的显示面板包括第二电源信号线VGH、第二参考信号线VGL、第一时钟信号线CK、第二时钟信号线CB以及选择信号线Mux1至Mux6。每个移位寄存器单元GOA1，GOA2，…GOAN连接第二电源信号线VGH、第二参考信号线VGL、第一时钟信号线CK和第二时钟信号线CB。每个多路复用单元MUX1，MUX2，…MUXm连接选择信号线Mux1至Mux6。
与图5和图6不同的是，图9和图10的显示面板还包括第一电源信号线VGH’和第一参考信号线VGL’。每个静电放电单元ESD1，ESD2，…ESDm的电源信号端与第一电源信号线VGH’电连接，每个静电放电单元ESD1，ESD2，…ESDm的参考信号端与第一参考信号线VGL’电连接，每个静电放电单元ESD1，ESD2，…ESDm的输出端与数据走线DATA1，DATA2，…DATAm中的至少一条数据走线电连接。在图9中，第一电源信号线VGH’位于包括多个静电放电单元ESD1，ESD2，…ESDm的静电放电电路120与显示区AA之间，第一参考信号线VGL’位于包括多个静电放电单元ESD1，ESD2，…ESDm的静电放电电路120与封装区PA之间。第二电源信号线VGH包括移位寄存器单元GOA1，GOA2，…GOAN的栅极驱动电路140与第一参考信号线之间VGL’之间，第二参考信号线VGL位于第二电源信号线VGH与包括移位寄存器单元GOA1，GOA2，…GOAN的栅极驱动电路之间。
图11示出了图9所示区域的电路图，其中示出了每个多路复用单元和每个静电放电单元的电路结构。图11的电路与图7类似，区别至少在于每个多路复用单元包括第一多路复用子单元和第二多路复用子单元，每个静电放电单元包括第一静电放电子单元和第二静电放电子单元。为了简化描述，下文将主要对区别部分进行详细说明。
如图9和图11所示，数据走线DATAi(第i数据走线)与多路复用单元MUXi(第i多路复用单元)和静电放电单元ESDi(第i静电放电单元)电连接，其中i为整数且1≤i≤m。静电放电单元ESDi包括第一静电放电子单元ESDi_1和第二静电放电子单元ESDi_2，多路复用单元MUXi包括第一多路复用子单元MUXi_1和第二多路复用子单元MUXi_2，数据走线DATAi包括第一子线DATAi_1、第二子线DATAi_2和第三子线DATAi_3。第一子线DATAi_1连接至第一静电放电子单元ESDi_1的输入端和第二静电放电子单元ESDi_2的输入端。第二子线DATAi_2连接在第一静电放电子单元ESDi_1的输入端与第一多路复用子单元MUXi_1的输入端之间。第三子线DATAi_3连接在第二静电放电子单元ESDi_2的输入端与第二多路复用子单元MUXi_2的输入端之间。
在9和图11中，第一静电放电子单元ESDi_1包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。第一晶体管T1的栅极和第一极连电连接，以作为第一静电放电子单元ESDi_1的电源信号端与第一电源信号线VGH’电连接。第一晶体管T1的第二极与第二晶体管T2的栅极和第一极电连接。第二晶体管T2的第二极与第三晶体管T3的栅极和第一极电连接，以作为第一静电放电子单元ESDi_1的输出端与第二子线DATAi_2电连接。第三晶体管3的第二极与第四晶体管T4的栅极和第一极电连接。第四晶体管T4的第二极作为第一静电放电子单元ESDi_1的参考信号端与第一参考信号线VGL’电连接。
在图9和图11中，第二静电放电子单元ESDi_2包括第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8。第五晶体管T5的栅极和第一极连电连接，以作为第二静电放电子单元ESDi_2的电源信号端与第一电源信号线VGH’电连接。第五晶体管T5的第二极与第六晶体管T6的栅极和第一极电连接。第六晶体管T6的第二极与第七晶体管T7的栅极和第一极电连接，以作为第二静电放电子单元ESDi_2的输出端与第一子线DATAi_1电连接。第七晶体管T7的第二极与第八晶体管T8的栅极和第一极电连接。第八晶体管T8的第二极作为第二静电放电子单元ESDi_2的参考信号端与第一参考信号线VGL’电连接。
在图9和图11中，第一多路复用子单元MUXi_1包括晶体管Tm1、Tm2和Tm3，第二多路复用子单元MUXi_2包括晶体管Tm4、Tm5和Tm6。晶体管Tm1至Tm6的栅极分别连接至选择信号线Mux1至Mux6，第二极分别连接6个数据信号线Di1至Di6。晶体管Tm1、Tm2和Tm3的第一极作为第一多路复用子单元MUXi_1的输入端连接至第二子线DATAi_2。晶体管Tm4、Tm5和Tm6的第一极作为第二多路复用子单元MUXi_2的输入端连接至第三子线DATAi_3。
图12示出了图9中的静电放电电路的放大布局图。
如图9和12所示，静电放电单元ESDi的第一静电放电子单元ESDi_1包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4，第二静电放电子单元ESDi_2包括第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8。数据走线DATAi的第一子线DATAi_1连接至第一静电放电子单元ESDi_1的输入端和第二静电放电子单元ESDi_2的输入端。数据走线DATAi的第二子线DATAi_2连接在第一静电放电子单元ESDi_2的输入端与多路复用单元MUXi的第一多路复用子单元MUXi_1的输入端之间。数据走线DATAi的第三子线DATAi_3连接在第二静电放电子单元ESDi_2的输 入端与多路复用单元MUXi的第二多路复用子单元MUXi_2的输入端之间。
图13A示出了根据本公开一实施例的显示面板的显示区的截面图。图13A的截面图适用于前述任意实施例的显示面板的显示区。
如图13A所示，显示面板包括衬底基板110、位于衬底基板上的子像素以及封装层160。在图13A中，衬底基板是110柔性的，包括第一柔性层1101、第一阻挡层1102、第二柔性层1103、第二阻挡层1104和缓冲层1105。第二柔性层1103位于第一柔性层1101面向显示电路(例如包括以上描述的子像素、静电放电电路、栅极驱动电路、多路复用电路以及各种信号线和走线等中的至少之一)的一侧。第一阻挡层1102位于第一柔性层1101和第二柔性层1103之间。第二阻挡层1104位于第二柔性层1103背离第一柔性层1101的一侧。缓冲层1105位于第二阻挡层1104背离第一柔性层1101的一侧。
显示面板还包括第一栅极绝缘层1501、第二栅极绝缘层1502、层间绝缘层1503和平坦化层1504，第一绝缘层1501位于衬底基板110上，第二栅极绝缘1502层位于第一绝缘层1501背离衬底基板110的一侧，层间绝缘层1503位于第二栅极绝缘层1502背离衬底基板110的一侧。平坦化层1504位于层间绝缘层1503背离衬底基板110的一侧。
显示区AA中的子像素包括驱动晶体管210，驱动晶体管210包括栅极2101、源极2102和漏极2103。驱动晶体管210的栅极2101位于第一栅极绝缘层1501与第二栅极绝缘层1502之间，驱动晶体管210的源极2102和漏极2103位于层间绝缘层1503和平坦化层1504之间。驱动晶体管210还可以包括有源区2104，有源区2104位于衬底基板110与第一栅极绝缘层1501之间，驱动晶体管210的源极2102和漏极2103通过设置在第一栅极绝缘层1501中的过孔与有源区2104电连接。
子像素还可以包括存储电容220，存储电容220的第一极具有第一部分2201和第二部分2202，其中第一部分2201与驱动晶体管210的栅极2101同层设置，第二部分2202与驱动晶体管210的源极2102和漏极2103同层设置。第二部分2202通过设置在第二栅极绝缘层1502和层间绝缘层1503中的过孔与第一部分2201电连接。存储电容220的第二极2203设置在第二栅极绝缘层1502和层间绝缘层1503之间。存储电容220的第二极2203中可以设有过孔，存储电容220的第一极的第一部分2201可以经由第二极2203中的过孔以及第二栅极绝缘层1502和层间绝缘层1503中的过孔与第二部分2202连接。存储电容220还可以包括半导体层2204，半导体层2204可以位于存储电容220的第一电极的第一部分2201面向衬底基板110的一侧，半导体层2204可以与有源 区2104同层设置。
子像素还可以包括发光元件230。发光元件230设置在平坦化层1504背离衬底基板110的一侧。发光元件230包括第一电极2301、第二电极2303以及位于第一电极2301和第二电极2303之间的发光层2302。发光元件230的第一电极2301通过设置在平坦化层1504中的过孔与驱动晶体管210的漏极2103电连接。
显示面板还可以包括封装层160。封装层160位于显示电路(例如包括以上描述的子像素、静电放电电路、栅极驱动电路、多路复用电路以及各种信号线和走线等中的至少之一)背离衬底基板110的一侧。以上描述的静电放电电路在衬底基板110上的投影位于封装层110在衬底基板上的投影内。例如在上述图1A和图1B中，封装层160在衬底基板110上的投影可以覆盖封装区PA所围绕形成的区域在衬底基板110上的投影，从而使显示区AA、多路复用电路120、静电放电电路130、栅极驱动电路140在衬底基板110上的投影均位于封装层160在衬底基板110上的投影之内。
在图13A的示例中，封装层160包括第一无机材料层1601、第二无机材料层1603以及位于第一无机材料层1601和第二无机材料层1603之间的有机材料层1602。第一无机材料层1601位于有机材料层1602面向衬底基板110的一侧，第二无机材料层1603位于有机材料层1602背离衬底基板110的一侧。
在一些实施例中，显示面板还包括像素界定层1505。如图13A所示，像素界定层1505位于平坦化层1504与发光层2302之间，并且覆盖发光元件230的第一电极2301的边缘。驱动晶体管210背离衬底基板110一侧还设置有间隔物170，间隔物170位于像素界定层1505与发光层2302之间。
图13B示出了图13A的显示面板的静电放电电路的截面图，其中该截面图是沿图12的Y-Y’线截取的。结合图12可以看出，图13B示出了图12中静电放电电路的第三晶体管T3的栅极和第一极以及与第三晶体管T3的第一极连接的数据走线DATAi的第二子线DATAi_2。
参考图13A和图13B，第三晶体管T3的栅极1301与图13A中驱动晶体管210的栅极2101同层设置，第三晶体管T3的第一极1302与驱动晶体管210的源极2102和漏极2103同层设置。以类似的方式，第三晶体管T3的第二极也与驱动晶体管210的源极2102和漏极2103同层设置。上文以静电放电电路中的第三晶体管T3为例进行了示意说明，然而本公开实施例不限于此，静电放电电路的其他晶体管(例如图11中的晶体管T1至T8中的任意一个或多个，或者图7中的晶体管T9至T12中的任意一个或多个)可以与 第三晶体管T3具有类似的层结构，静电放电电路中各个晶体管的栅极可以与驱动晶体管的栅极2101同层设置，静电放电电路中各个晶体管的第一极和第二极可以与驱动晶体管210的源极2102和漏极2103同层设置。
根据本公开的实施例，所述多条数据走线中至少一条数据走线的至少一部分与图3A中存储电容220的第二极2203或者与驱动晶体管210的栅极2101同层设置。例如图13B中数据走线DATAi的第二子线DATAi_2与图13A中存储电容220的第二极2203同层设置。以类似的方式，参考图9，数据走线DATAi的第三子线DATAi_3也可以与图13A中存储电容220的第二极2203同层设置。数据走线DATAi的第一子线DATAi_1可以与图13A中驱动晶体管210的栅极2101或者存储电容220的第二极2203同层设置。例如在图9中，数据走线DATAi的第一子线DATAi_1可以与存储电容220的第二极2203同层设置，而相邻的数据走线DATA(i+1)的第一子线DATA(i+1)_1可以与驱动晶体管210的栅极2101同层设置。然而本公开的实施例不限于此，数据走线可以根据需要以不同方式设置。例如参考图5，数据走线DATA1，DATA2，…DATAm中的每一条可以均与驱动晶体管210的栅极2101同层设置。
在一些实施例中，静电放电电路与封装层150之间还设有参考电极层310，参考电极层310可以与图13A中发光元件230的第一电极2301同层设置。可以向参考电极层310施加正电压信号。
图13C示出了图13A的显示面板的封装区的截面图。如图13C所示，封装区PA内设有坝部(DAM)，所述坝部包括位于所述第一无机材料层1601中的凹槽以及位于第二无机材料层1603中与所述凹槽匹配的凸起。
在图13C中，封装区PA内设有第一导电层4101，第一导电层4101可以与图13A中发光元件230的第一电极2301同层设置。第一导电层4101背离衬底基板110的一侧设置有第一凸起部4102和第二凸起部4103，其中第一凸起部4102覆盖第一导电层4101的边缘，第二凸起部4103位于第一凸起部4102面向显示区AA的一侧。第一凸起部4102和第二凸起部4103可以与图13A中的平坦化层1504同层设置。
封装区PA还内设有第二导电层4104，第二导电层4104覆盖第一凸起部4102的一部分、第二凸起部4103以及第一导电层4101未被第一凸起部4102和第二凸起部4103覆盖的部分。第二导电层4104可以与图13A中驱动晶体管210的源极2102和漏极2103同层设置。
第一凸起部4102背离衬底基板110的一侧设有第三凸起部4105；第二凸起部4103 背离衬底基板110的一侧设有第四凸起部4106。第三凸起部4105覆盖第二导体层4104的边缘，第四凸起部4106位于第二导体层4104与第一无机材料层1601之间。第三凸起部4105和第四凸起部4106各自的一部分可以与图13A中的像素界定层1505同层设置，另一部分可以与图13A中的间隔物170同层设置。第一无机材料层1601覆盖第一凸起部4102的边缘、第三凸起部4105、第四凸起部4106以及第二导电层4104未被第三凸起部4105和第四凸起部4106覆盖的部分，从而在封装区PA形成凹槽。有机材料层1602终止于凹槽的侧壁，第二无机材料层1603覆盖位于封装区PA的第一无机材料层1601，从而形成与凹槽匹配的凸起。第二无机材料层1603还覆盖封装区PA面向AA区一侧的有机材料层1602，从而实现封装。
图14A示出了根据本公开另一实施例的显示面板的显示区的截面图。图14B示出了图14A的显示面板的静电放电电路的截面图。图14A至图14C的显示面板与图13A至图13C的显示面板类似，区别至少在于图14A至图14C的显示面板的衬底基板和封装层是刚性的，而非柔性的。为了简化描述，下文将主要对区别部分进行详细说明。
图14A所示的显示面板的显示区的层结构与图13A类似，图14B所示的显示面板的静电放电电路所在的区域的层结构与图13B类似。与图13A和图13B不同的是，图14A和图14B的显示面板的衬底基板110’是刚性的，衬底基板110’除了包括上述依次堆叠的第一柔性层1101、第一阻挡层1102、第二柔性层1103、第二阻挡层1104和缓冲层1105之外，还包括玻璃基板1106。玻璃基板1106位于第一柔性层1101背离第一阻挡层1102的一侧。图14A和图14B的显示基板的封装层180’也是刚性的，封装层180’可以是玻璃盖板，设置在显示电路(包括上述子像素、多路复用电路120、静电放电电路130等等)背离衬底基板110’的一侧。封装层180’可以覆盖如图1A和图1B所示的封装区PA所围绕形成的区域。
图14C所示的显示面板的封装区的层结构与图13C不同，因为图14A至图14C的显示面板是刚性显示面板，其采用不同于柔性显示面板的封装方式。
如图14C所示，封装区PA内设有粘合层5101，粘合层5101位于玻璃盖板180’面向衬底基板110’的一侧。粘合层5101的材料可以包括但不限于玻璃粉(Frit)胶。在一些实施例中，粘合层5101可以包括多个伸出部51011，多个伸出部51011可以通过设置在第二栅极绝缘层1502和层间介质层1503中的过孔延伸至第一栅极绝缘层1501中。通过设置多个伸出部51011，可以增大粘合层5101的粘合强度。
封装区PA内还可以设置有第三导体层5102和第四导体层5103，第三导体层5102 可以与图13A中驱动晶体管210的栅极2101同层设置，第四导体层5103可以与图13A中驱动晶体管210的源极2102和漏极2103同层设置。第三导体层5102位于第一栅极绝缘层1501与第二栅极绝缘层1502之间，第三导体层5102中可以设置有过孔，以使得粘合层1501的伸出部51011可以穿过第三导体层5102中的过孔延伸到第一栅极绝缘层1501中。第四导体层5103可以位于封装区PA面向显示区AA一侧的边缘区域，并且第四导体层1503的边缘被粘合层5101覆盖。第四导体层5103可以通过设置在第二栅极绝缘层1502和层间介质层1503中的过孔与第三导体层5102连接。可以向第四导体层5103和第三导体层5102中的至少一者施加参考电压VSS。
虽然上述实施例中粘合层5101的伸出部51011延伸到特定的位置(例如到达第一栅极绝缘层1501中一定深度)，然而本公开的实施例不限于此，伸出部51011可以根据需要延伸至不同的位置，例如可以延伸至第二栅极绝缘层1502中，或者向第一栅极绝缘层1501中延伸到更深的位置。
虽然上述实施例中在封装区PA中第三导体层5102是与驱动晶体管210的栅极2101同层设置的导体层，然而本公开的实施例不限于此。在一些实施例中，第三导体层5102可以使与存储电容220的第二极2203同层设置的导体层，或者与驱动晶体管210的源极2102和漏极2103同层设置的导体层。
图15示出了根据本公开另一实施例的显示面板的示意图。图15的显示面板与图1A和图1B的显示面板类似，区别至少在于显示区AA在衬底基板的投影具有圆角矩形轮廓，而不是圆形轮廓。为了简化描述，下文将主要对区别部分进行详细说明。
如图15所示，显示面板100C包括衬底基板110C以及设置在衬底基板110C的显示区AA与封装区PA之间的区域中的静电放电电路130C。以上对于任意实施例的衬底基板和静电放电电路的描述同样适用于图15的衬底基板110C和静电放电电路130C。与上述实施例不同的是，显示面板100C的显示区AA在衬底基板110C上的投影具有圆角矩形轮廓。静电放电电路130C沿y方向位于显示区AA的一侧，显示区AA的圆角矩形轮廓面向静电放电电路130C一侧具有两个弧形边缘和一个沿x方向延伸的直线边缘。静电放电电路130C中的多个静电放电单元一部分沿着显示区AA的两个弧形边缘排列，多个静电放电单元的另一部分沿着显示区AA的直线边缘呈直线排列，从而形成如图15所示的整体图案。围绕弧形部分排列的静电放电单元可以采用类似于图4所示的方式呈阶梯状摆放，或者采用类似于图8所示的方式呈弧形摆放。呈直线排列的静电放电单元可以沿x方向排列，每个静电放电单元的第一参考轴ay和第二参考轴 ax可以分别平行于x方向和y方向。
在显示面案100C中，栅极驱动电路可以沿x方向设置在显示区AA两侧，且位于封装区PA与显示区AA之间。多路复用电路可以位于显示区AA与静电放电电路130C之间，并且以类似于静电放电电路130C的方式排列。
图16示出了根据本公开又一实施例的显示面板的示意图。图16的显示面板与15的显示面板类似，区别至少在于显示区AA在衬底基板的投影具有矩形轮廓，而不是圆形轮廓。如图16所示，显示面板100C包括衬底基板110D以及设置在衬底基板110D的显示区AA与封装区PA之间的区域中的静电放电电路130D。以上对于任意实施例的衬底基板和静电放电电路的描述同样适用于图16的衬底基板110D和静电放电电路130D。与图15不同，图16的显示区AA具有矩形轮廓，静电放电电路130D的多个静电放电单元沿着矩形轮廓面向所述静电放电电路一侧的直线边缘排列，在图16中是沿x方向排列。类似于图4和图8，每个静电放电单元可以具有第一参考轴ay和第二参考轴ax，每个静电放电单元的第一参考轴ay和第二参考轴ax可以分别平行于x方向和y方向。
图17示出了根据本公开实施例的显示装置的示意图。如图17所示，显示装置1700包括显示面板1701。显示面板1701可以由上述任意实施例的显示面板来实现。
例如，在一些示例中，显示装置1700还可以包括柔性电路板及控制芯片。例如，柔性电路板邦定到显示面板的邦定区，而控制芯片安装在柔性电路板上，由此与显示区电连接；或者，控制芯片直接邦定到邦定区，由此与显示区电连接。
例如，控制芯片可以为中央处理器、数字信号处理器、***芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
例如，本公开至少一个实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本领域的技术人员可以理解，上面所描述的实施例都是示例性的，并且本领域的技术人员可以对其进行改进，各种实施例中所描述的结构在不发生结构或者原理方面的冲突的情况下可以进行自由组合。
在详细说明本公开的较佳实施例之后，熟悉本领域的技术人员可清楚的了解，在不脱离随附权利要求的保护范围与精神下可进行各种变化与改变，且本公开亦不受限于说明书中所举示例性实施例的实施方式。

Claims (22)

  1. 一种显示面板，包括：
    衬底基板，包括显示区和围绕所述显示区的周边区；
    多个子像素，位于所述衬底基板上且位于所述显示区中，所述多个子像素呈阵列排布；
    多条数据信号线，位于所述显示区且与所述多个子像素电连接，所述多条数据信号线被配置为向所述多个子像素传递数据信号；
    多条数据走线，位于所述周边区且与所述多条数据信号线电连接；
    静电放电电路，位于所述衬底基板上且位于所述周边区，所述静电放电电路与所述多条数据走线电连接；以及
    封装层，位于所述多个子像素和所述静电放电电路远离所述衬底基板的一侧，所述静电放电电路在所述衬底基板的正投影位于所述封装层在所述衬底基板的正投影内。
  2. 根据权利要求1所述的显示面板，其中，所述周边区的边缘包括围绕所述显示区的环状的封装区，所述封装区内设有环形的坝部，所述静电放电电路位于所述封装区与所述显示区之间。
  3. 根据权利要求2所述的显示面板，其中，所述封装层包括第一无机材料层、第二无机材料层以及位于所述第一无机材料层和所述第二无机材料层之间的有机材料层，其中，所述有机材料层位于所述环形的坝部围成的区域内，所述第一无机材料层和所述第二无机材料层位于所述坝部远离所述衬底基板的一侧。
  4. 根据权利要求1所述的显示面板，其中，
    所述封装层包括盖板；并且
    所述周边区的边缘包括围绕所述显示区的环状的封装区，所述封装区内设有粘合层，所述粘合层位于所述盖板面向所述衬底基板的一侧，所述静电放电电路位于所述封装区与所述显示区之间。
  5. 根据权利要求1所述的显示面板，其中，所述静电放电电路包括多个静电放电单元，所述多个静电放电单元分别与所述多条数据走线电连接，所述多个静电放电单元中的至少一部分静电放电单元沿着所述显示区的边缘排列。
  6. 根据权利要求5所述的显示面板，其中，所述显示区面向所述静电防护电路一侧的边缘具有至少一个弧形部分，所述多个静电放电单元中的至少一部分静电放电单元沿着所述至少一个弧形部分排列。
  7. 根据权利要求5所述的显示面板，其中，所述至少一部分静电放电单元各自具有第一参考轴和垂直于所述第一参考轴的第二参考轴，所述至少一部分静电放电单元中每个静电放电单元的第一参考轴平行于与该静电放电单元相邻的弧形部分的法线方向，所述至少一部分静电放电单元中每个静电放电单元的第二参考轴平行于与该静电放电单元相邻的弧形部分的切线方向。
  8. 根据权利要求5所述的显示面板，其中，所述至少一部分静电放电单元各自具有第一参考轴和垂直于所述第一参考轴的第二参考轴，所述第一参考轴平行于第一方向，所述第二参考轴平行于第二方向，其中所述第一方向为所述阵列的行方向，所述第二方向为所述阵列的列方向。
  9. 根据权利要求5所述的显示面板，其中，所述显示区具有圆形轮廓，所述多个静电放电单元沿着所述圆形轮廓面向所述静电放电电路一侧的弧形边缘排列。
  10. 根据权利要求5所述的显示面板，其中，所述显示区具有圆角矩形轮廓，所述多个静电放电单元中的一部分静电放电单元沿着所述圆角矩形轮廓面向所述静电放电电路一侧的圆角的弧形边缘排列，所述多个静电放电单元中的另一部分静电放电单元沿着所述圆角矩形轮廓的面向所述静电放电电路一侧的直线边缘排列。
  11. 根据权利要求5所述的显示面板，其中，所述显示区具有矩形轮廓，所述多个静电放电单元沿着所述矩形轮廓面向所述静电放电电路一侧的直线边缘排列。
  12. 根据权利要求1所述的显示面板，还包括：
    第一电源信号线，位于所述静电放电电路与所述显示区之间，并且与所述静电放电电路电连接；以及
    第一参考信号线，位于所述静电放电电路与所述封装区之间，并且与所述静电放电电路电连接，所述第一电源信号线的电压高于所述第一参考信号线的电压。
  13. 根据权利要求10所述的显示面板，其中，每个静电放电单元的电源信号端与所述第一电源信号线电连接，每个静电放电单元的参考信号端与所述第一参考信号线电连接，每个静电放电单元的输出端与所述多条数据走线中的至少一条数据走线电连接。
  14. 根据权利要求12所述的显示面板，还包括：
    栅极驱动电路，所述栅极驱动电路位于所述显示区与所述静电放电电路之间；
    多条栅极信号线，位于所述显示区内且与所述多个子像素电连接，所述栅极驱动电路通过所述多条栅极信号线与所述显示区的所述多个子像素电连接；
    第二电源信号线，位于所述栅极驱动电路与所述第一参考信号线之间，并且与所述栅极驱动电路电连接；
    第二参考信号线，位于所述第二电源信号线与所述栅极驱动电路之间，并且与所述栅极驱动电路电连接，所述第二电源信号线的电压高于所述第二参考信号线的电压。
  15. 根据权利要求1所述的显示面板，还包括：
    栅极驱动电路，所述栅极驱动电路位于所述显示区与所述封装区之间，并且通过所述多条栅极信号线与所述显示区的所述多个子像素电连接，所述静电放电电路位于所述栅极驱动电路面向所述封装区的一侧；
    第二电源信号线，位于所述栅极驱动电路与所述静电放电电路之间，并且与所述栅极驱动电路和所述静电放电电路电连接；
    第二参考信号线，位于所述第二电源信号线与所述栅极驱动电路之间，并且与所述栅极驱动电路和所述静电放电电路电连接，
    其中，每个静电放电单元的电源信号端与所述第二电源信号线电连接，每个静电放电单元的参考信号端与所述第二参考信号线电连接，每个静电放电单元的输出端与所述多条数据走线中的至少一条数据走线电连接。
  16. 根据权利要求1所述的显示面板，还包括：
    多路复用电路，位于所述显示区与所述封装区之间，所述多条数据走线通过所述多路复用电路与所述多条数据信号线电连接；以及
    K条选择信号线，位于所述多路复用电路与所述静电放电电路之间，与所述多路复用电路电连接，其中K为大于1的整数，
    其中，所述多路复用电路包括多个多路复用单元，其中第i多路复用单元的输入端和第i静电放电单元的输出端连接所述多条数据走线中的第i数据走线，第i多路复用单元的K个输出端分别连接所述多条数据信号线中的K条数据信号线，第i多路复用单元的K个控制信号端分别连接所述K条选择信号线，其中i为大于或等于1的整数。
  17. 根据权利要求16所述的显示面板，其中，每个静电放电单元包括第一静电放电子单元和第二静电放电子单元，每个多路复用单元包括第一多路复用子单元和第二多路复用子单元，每条数据走线包括第一子线、第二子线和第三子线，其中，
    第i数据走线的第一子线连接至第i静电放电单元的第一静电放电子单元的输入端和第二静电放电子单元的输入端；
    第i数据走线的第二子线连接在第i静电放电单元的第一静电放电子单元的输入端 与第i多路复用单元的第一多路复用子单元的输入端之间；
    第i数据走线的第三子线连接在第i静电放电单元的第二静电放电子单元的输入端与第i多路复用单元的第二多路复用子单元的输入端之间。
  18. 根据权利要求17所述的显示面板，其中，
    所述第一静电放电子单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极电连接作为所述第一静电放电子单元的电源信号端，所述第一晶体管的第二极与所述第二晶体管的栅极和所述第二晶体管的第一极电连接，所述第二晶体管的第二极与所述第三晶体管的栅极和所述第三晶体管的第一极电连接作为所述第一静电放电子单元的输出端，所述第三晶体管的第二极与所述第四晶体管的栅极和所述第四晶体管的第一极电连接，所述第四晶体管的第二极作为所述第一静电放电子单元的参考信号端；
    所述第二静电放电子单元包括第五晶体管、第六晶体管、第七晶体管和第八晶体管，所述第五晶体管的栅极和所述第五晶体管的第一极电连接作为所述第二静电放电子单元的电源信号端，所述第五晶体管的第二极与所述第六晶体管的栅极和所述第六晶体管的第一极电连接，所述第六晶体管的第二极与所述第七晶体管的栅极和所述第七晶体管的第一极电连接作为所述第二静电放电子单元的输出端，所述第七晶体管的第二极与所述第八晶体管的栅极和所述第八晶体管的第一极电连接，所述第八晶体管的第二极作为所述第二静电放电子单元的参考信号端。
  19. 根据权利要求16所述的显示面板，其中，每个静电放电单元包括第九晶体管、第十晶体管、第十一晶体管和第十二晶体管，其中，
    所述第九晶体管的栅极和所述第九晶体管的第一极电连接作为所述静电放电单元的电源信号端，所述第九晶体管的第二极与所述第十晶体管的栅极和所述第十晶体管的第一极电连接，所述第十晶体管的第二极与所述第十一晶体管的栅极和所述第十一晶体管的第一极电连接作为所述静电放电单元的输出端，所述第十一晶体管的第二极与所述第十二晶体管的栅极和所述第十二晶体管的第一极电连接，所述第十二晶体管的第二极作为所述静电放电单元的参考信号端。
  20. 根据权利要求14或15所述的显示面板，还包括：
    第一时钟信号线，位于所述第二电源信号线与所述第二参考信号线之间，并且与所述栅极驱动电路电连接；以及
    第二时钟信号线，位于所述第一时钟信号线与所述第二电源信号线之间，并且与 所述栅极驱动电路电连接。
  21. 根据权利要求5所述的显示面板，其中，所述多个子像素中的至少一个子像素包括驱动晶体管，所述驱动晶体管包括栅极、源极和漏极；
    每个静电放电单元包括多个晶体管，其中每个晶体管的栅极与所述驱动晶体管的栅极同层设置，每个晶体管的第一极和第二极与所述驱动晶体管的源极和漏极同层设置。
  22. 一种显示装置，包括根据权利要求1至21中任一项权利要求所述的显示面板。
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