WO2022100976A1 - Composant semi-conducteur optoélectronique et son procédé de production - Google Patents

Composant semi-conducteur optoélectronique et son procédé de production Download PDF

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Publication number
WO2022100976A1
WO2022100976A1 PCT/EP2021/079178 EP2021079178W WO2022100976A1 WO 2022100976 A1 WO2022100976 A1 WO 2022100976A1 EP 2021079178 W EP2021079178 W EP 2021079178W WO 2022100976 A1 WO2022100976 A1 WO 2022100976A1
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WO
WIPO (PCT)
Prior art keywords
optoelectronic semiconductor
semiconductor component
semiconductor chip
layer
carrier
Prior art date
Application number
PCT/EP2021/079178
Other languages
German (de)
English (en)
Inventor
Thomas Schwarz
Original Assignee
Ams-Osram International Gmbh
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Filing date
Publication date
Application filed by Ams-Osram International Gmbh filed Critical Ams-Osram International Gmbh
Publication of WO2022100976A1 publication Critical patent/WO2022100976A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • an optoelectronic semiconductor component and a method for its production are specified.
  • the optoelectronic semiconductor component is a surface-mountable semiconductor component.
  • Semiconductor components which have a rectangular outline.
  • the rectangular outline is often due to the production or separation method with which the semiconductor components are produced.
  • the semiconductor components can be separated from a composite by means of sawing along straight separating lines.
  • the size of the components is also determined by the space required for wire contacts and separating trenches. Due to the circumstances described, the components are usually relatively large. However, large components cause higher production costs and a larger space requirement in the customer's application.
  • one problem to be solved is to specify an area-optimized optoelectronic semiconductor component.
  • Another problem to be solved is to specify a method for producing an area-optimized optoelectronic semiconductor component.
  • an optoelectronic semiconductor component comprises at least one optoelectronic semiconductor chip. Furthermore, the optoelectronic semiconductor component comprises a carrier element on which the at least one optoelectronic semiconductor chip is arranged.
  • the carrier element can have at least one first connection element and at least one second connection element for making electrical contact with the optoelectronic semiconductor component, the at least one optoelectronic semiconductor chip being electrically conductively connected to a first and second connection element of the carrier element.
  • the first connection element serves as an electrical contact of a first polarity
  • the second connection element serves as an electrical contact of a second polarity different from the first. Electrical contact can preferably be made with the optoelectronic semiconductor component from the outside by means of a first and second connection element.
  • the optoelectronic semiconductor component has a housing which at least partially surrounds the at least one optoelectronic semiconductor chip.
  • the housing is located on surfaces of the semiconductor chip that are not covered by the carrier element.
  • the optoelectronic semiconductor component advantageously has a polygonal, non-rectangular outline.
  • the floor plan has a polygonal shape, which is suitable for arranging several optoelectronic semiconductor components in a row without gaps.
  • a transition between two semiconductor components lined up next to one another takes place essentially without a gap, it being possible for gaps that are small in relation to the size of the semiconductor components to occur due to manufacturing fluctuations and roughness.
  • the “floor plan” is to be understood as meaning a two-dimensional image of an element, for example the semiconductor component, in a mounting plane of the optoelectronic semiconductor component along a component axis running transversely, in particular perpendicularly, to the mounting plane.
  • the outline of the optoelectronic semiconductor component is hexagonal.
  • the outline preferably corresponds to an equilateral hexagon, particularly preferably a regular hexagon.
  • This form not only enables the semiconductor components to be lined up without gaps, but also to reduce the component area or production area, as will be explained in more detail below in connection with the figures.
  • the outline of the optoelectronic semiconductor component can correspond to the shape of part of a hexagon.
  • the hexagon can be divided into identical pieces, for example into two identical pentagons or into two or six identical non-rectangular quadrilaterals or into six or twelve identical triangles.
  • the floor plan of the optoelectronic The semiconductor component can therefore also correspond to a triangle, a non-rectangular square or a pentagon.
  • the carrier element has a polygonal, non-rectangular outline.
  • the carrier element has an outline that corresponds to the outline of the optoelectronic semiconductor component in terms of shape and preferably also in size and thus has the features already described in connection with the outline of the optoelectronic semiconductor component.
  • the carrier element can have a prismatic shape.
  • a first and second main surface of the carrier element, which extend essentially parallel to a mounting plane of the semiconductor component, are polygonal, for example triangular, quadrangular, pentagonal or hexagonal.
  • the carrier element is preferably a structured layer or layer sequence. During the structuring of the initially continuous layer or layer sequence, the first and second connection elements are produced, which are spaced apart from one another by an intermediate space. More preferably, the layer or layer sequence is formed from at least one metal and/or a metal compound. In particular, solderable metals or metal compounds with at least one of the following materials come into consideration for the carrier element: Cu, Ti, Pt, Au. Furthermore, the carrier element can contain a mirror layer, which is arranged on a side of the carrier element that faces the semiconductor chip. The mirror layer can contain or consist of Ag, for example. Furthermore, the housing according to at least one
  • the housing has a floor plan that corresponds to the floor plan of the optoelectronic semiconductor component or carrier element in terms of shape and preferably also in size and thus has the features already described in connection with the floor plan of the optoelectronic semiconductor component.
  • the housing does not protrude laterally, that is to say in directions parallel to the mounting plane, essentially, that is to say within the framework of normal manufacturing tolerances, not beyond the carrier element.
  • the housing has a layer or a plurality of layers arranged one above the other, which is/are applied to the carrier element.
  • the housing is therefore preferably not a self-supporting element, but an element arranged in a form-fitting manner on the carrier element.
  • Plastic materials such as silicones, epoxides or epoxy resins can be used for the housing.
  • the housing can also contain particles, such as converter particles for wavelength conversion of part of the radiation emitted by the semiconductor chip and/or reflective particles for deflecting part of the radiation emitted by the semiconductor chip and/or absorbing particles for absorbing part of the radiation emitted by the semiconductor chip.
  • the layer or layers of the housing each have at least one inwardly curved side surface.
  • the housing has a first area and a second area adjoining the first area, with the first and second areas being formed from different materials.
  • the first and second areas can have different functionalities and accordingly have materials suitable for this purpose.
  • the specific configuration of the first and second area depends, for example, on what type of emission characteristic, for example an isotropic or anisotropic emission characteristic, is desired in the semiconductor component.
  • the first area is preferably an area generated first and the second area is an area generated subsequently.
  • the second region is surrounded by the first region in a plan view of the semiconductor component.
  • the first area is arranged laterally downstream of the second area, starting from the semiconductor chip.
  • the second area is arranged in a cavity of the first area.
  • the cavity can have a constant diameter or a diameter that tapers in the direction of the carrier element.
  • the first area can protrude vertically, ie perpendicularly to the mounting plane, beyond the second area.
  • the first and second areas can be flush with one another.
  • the second area can protrude beyond the first area.
  • the second area can be convexly curved.
  • the first area can be designed to be radiation-transmissive, for example.
  • the second area can be a wavelength-converting or reflecting area be .
  • the semiconductor chip is advantageously arranged in the second area.
  • the first area can be a reflective or radiation-absorbing area.
  • the second region can be designed to be radiation-transmissive.
  • the semiconductor chip is advantageously arranged in the first area.
  • the second area is arranged on the first area.
  • the first area can be a reflective or radiation-absorbing area, while the second area is preferably radiation-transmissive.
  • the semiconductor chip is advantageously arranged in the first region.
  • the housing has a spacer on its front side facing away from the carrier element.
  • the spacer preferably protrudes from a main surface of the housing on the front side of the housing facing away from the carrier element.
  • the spacer can be arranged circumferentially or selectively in a plan view of the front side.
  • the first and/or second connecting means is/are not covered laterally by the spacer.
  • the spacer can protect the connecting means(s) from mechanical loads during the assembly of the semiconductor component. In particular, the spacer protects against pressure from above by forces from above being directed past the connecting means(s) by means of the spacer.
  • the semiconductor chip comprises a semiconductor body and a first and second connection contact for making electrical contact with the semiconductor body.
  • the semiconductor body has a first main area and a second main area opposite the first main area and at least one side area which connects the first main area to the second main area.
  • the semiconductor chip can be connected to the carrier element on the second main area.
  • the semiconductor chip or semiconductor body can have a prismatic shape.
  • the first and second main surfaces are polygonal, for example triangular, quadrangular, in particular rectangular, or hexagonal.
  • the three-dimensional shape of the semiconductor chip can differ from the three-dimensional shape of the optoelectronic semiconductor component.
  • the optoelectronic semiconductor chip can have a layout that differs from the layout of the optoelectronic semiconductor component.
  • the optoelectronic semiconductor chip can have a rectangular, in particular square, outline.
  • the semiconductor chip it is also conceivable for the semiconductor chip to have a triangular or hexagonal outline.
  • the semiconductor body comprises a carrier substrate and a first and second semiconductor region of different conductivity, which are arranged on the carrier substrate, and an active zone arranged between the first and second semiconductor region.
  • the carrier substrate is a growth substrate on which the first and second semiconductor regions are deposited epitaxially.
  • Deposited epitaxially on the growth substrate is understood in the present context to mean that the growth substrate is used for the deposition and/or growth of the first and second semiconductor region.
  • the second semiconductor region is in direct contact with the growth substrate. After the first and second semiconductor regions have been grown, the growth substrate can remain in the semiconductor body or be detached.
  • the first semiconductor region has p conductivity, while the second semiconductor region has n conductivity.
  • the first semiconductor region can be arranged on the first main area and the second semiconductor region can be arranged on the second main area.
  • nitride compound semiconductors Materials based on nitride compound semiconductors are preferably suitable for the first and second semiconductor region of the semiconductor body. "Based on nitride compound semiconductors" means in the present context that at least one layer of the semiconductor regions comprises a nitride III/V compound semiconductor material, preferably Al n Ga m Inin nm N, where 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and n+m ⁇ 1. This material does not necessarily have to have a mathematically exact composition according to the above formula.
  • the carrier or growth substrate preferably includes or consists of sapphire, SiC and/or GaN.
  • a sapphire substrate is transparent to short-wavelength visible radiation, particularly in the blue to green range.
  • the semiconductor component is preferably a radiation-emitting component, the active zone being provided for generating electromagnetic radiation.
  • electromagnetic radiation is used here to mean, in particular, infrared, visible and/or ultraviolet radiation.
  • part of the radiation generated preferably passes through the first main surface of the semiconductor body. Another part of the radiation can pass through the at least one side surface of the semiconductor body are decoupled.
  • the semiconductor chip can be a volume emitter, which emits the generated radiation essentially isotropically, or a surface emitter, which emits the generated radiation essentially anisotropically, in particular on the first main surface.
  • the semiconductor component can also be a volume emitter or surface emitter.
  • the first and second connection contact can be arranged on the same surface, for example on the first or second main surface, or on different surfaces, for example on the first and second main surface.
  • the optoelectronic semiconductor chip is preferably electrically conductively connected to the first connection element by means of a first connection means and to the second connection element by means of a second connection means.
  • the first and second connecting means it is in each case a bonding wire or an electrically conductive connecting layer, in particular a planar, electrically conductive connecting layer (so-called "planar interconnect").
  • At least the first connection element, to which the optoelectronic semiconductor chip is electrically conductively connected, can be partially laterally covered by the optoelectronic semiconductor chip.
  • the optoelectronic semiconductor chip can be arranged completely on the first connection element and partially cover it.
  • the optoelectronic semiconductor chip is arranged partially on the first and partially on the second connection element and spans the gap between the first and second connection element, with each part of the connection elements being covered by the semiconductor chip.
  • the optoelectronic semiconductor component has a delimiting layer which partially covers the carrier element on its side facing away from the optoelectronic semiconductor chip.
  • the first and second connection elements are uncovered by the delimiting layer in some areas.
  • the delimiting layer is preferably a soldering stop layer which is intended to prevent a soldering material from flowing when the semiconductor component is soldered onto an assembly support, for example a printed circuit board.
  • the semiconductor component on a plurality of optoelectronic semiconductor chips.
  • the semiconductor component also has in this case several first and / or second connection elements.
  • At least two of the semiconductor chips preferably emit radiation of different colors during operation.
  • the method described below is suitable for producing an optoelectronic semiconductor component as described above or a plurality of optoelectronic semiconductor components as described above. Additional features described in connection with the semiconductor component can therefore also be used for the method and vice versa.
  • this comprises the following steps:
  • At least one housing which at least partially surrounds the at least one optoelectronic semiconductor chip, by applying one or more layers, the one layer or more layers being applied following a structure or being structured after the application.
  • the process steps are preferably carried out in the order given.
  • Frollowing a structure means here in particular that the layer or multiple layers are applied not continuously but with interruptions.
  • the layer or layer sequence can be formed from at least one metal and/or a metal compound.
  • the carrier can be a glass, ceramic or metal carrier.
  • the metal support can contain or consist of steel, FeNi, Mo or MoCu, for example.
  • the carrier can be a printed circuit board (so-called "PCB").
  • an adhesion layer is arranged between the carrier and the carrier element, which provides a mechanical connection between the carrier and the carrier element during manufacture.
  • the adhesion layer is preferably a detachable layer which can be detached from the carrier element, for example by means of a laser lift-off method or a peel-off method.
  • a silicon nitride is preferably considered for the adhesion layer.
  • a polymer such as polydimethylsiloxane (“PDMS”) is particularly suitable for the adhesion layer.
  • PDMS polydimethylsiloxane
  • the layer or layer sequence for producing the at least one carrier element can be applied continuously, ie without interruption, to the carrier and then structured.
  • the layer or layer sequence is preferably structured by means of photolithography.
  • the carrier elements After the carrier elements have been produced, they are advantageously present in isolated form on the carrier, so that the associated semiconductor components can be self-separated by detaching the carrier.
  • one of the following methods is used to produce the housing: lithography, additive manufacturing.
  • the housing is preferably produced from a single layer of starting material, with the layer being structured after application.
  • the housing is preferably produced from a plurality of layers of a starting material, with the layers particularly preferably being structured in each case after application.
  • a stereolithographic process is preferably used in additive manufacturing.
  • a photostructurable material such as a photoresist, for example a negative resist
  • a photoresist for example a negative resist
  • the negative resist is crosslinked in the areas that are exposed. Because the exposure of takes place at the top, cross-linking decreases downwards due to light absorption. Developing removes the less crosslinked material below, resulting in an undercut.
  • the housing can have an undercut or at least one inwardly curved side face on a side edge.
  • a plurality of optoelectronic semiconductor components are advantageously present as separate components on the carrier without a further isolation step.
  • the carrier can be detached to separate the optoelectronic semiconductor components.
  • an intermediate carrier can be applied to the front sides of the housings before separation and the carrier can be detached.
  • a delimiting layer can be applied to the carrier element or the carrier elements, which partially covers them on their side facing away from the optoelectronic semiconductor chip. The intermediate carrier is then detached in order to separate the optoelectronic semiconductor components.
  • the optoelectronic semiconductor component is particularly suitable for general lighting, for vehicle applications, for displays, sensor applications and signaling devices.
  • FIG. 1A shows a schematic cross-sectional view
  • FIG. 1B shows a schematic plan view of an assembly of optoelectronic semiconductor components according to a first exemplary embodiment
  • FIGS. 2A to 5A schematic cross-sectional views and FIGS. 2B to 5B schematic plan views of various steps of a method for producing an optoelectronic semiconductor component as illustrated in FIGS. 6A to 6C according to a second exemplary embodiment
  • FIG. 7A shows a schematic plan view of a front side
  • FIG. 7B shows a schematic cross-sectional view
  • FIG. 7C shows a schematic plan view of a rear side of an optoelectronic semiconductor component according to a third exemplary embodiment
  • FIG. 8A shows a schematic cross-sectional view
  • FIG. 8B shows a schematic plan view of an assembly of optoelectronic semiconductor components according to a fourth exemplary embodiment
  • FIG. 9A shows a schematic cross-sectional view and FIG. 9B shows a schematic top view of an assembly of optoelectronic semiconductor components according to a fifth exemplary embodiment
  • FIGS. 10 to 15 schematic cross-sectional views of optoelectronic semiconductor components according to further exemplary embodiments
  • FIG. 16A shows a schematic top view of a comparative example of an optoelectronic semiconductor component
  • FIG. 16B shows a schematic top view of an optoelectronic semiconductor component described here
  • FIG. 17 is a table showing production areas and area savings of the semiconductor component described here compared to the comparative example for different chip edge lengths
  • FIGS. 18 to 21 schematic top views of optoelectronic semiconductor components according to further exemplary embodiments
  • FIGS. 22A to 22H show different exemplary embodiments of outlines of an optoelectronic semiconductor component described here.
  • FIGS. 1A and 1B show a plurality of optoelectronic semiconductor components 1 according to a first exemplary embodiment, which are present in the composite, with the optoelectronic semiconductor components 1 being arranged on a common carrier 12 .
  • the optoelectronic semiconductor components 1 each have an optoelectronic semiconductor chip 2 .
  • the respective optoelectronic semiconductor component 1 comprises a carrier element 3 on which the optoelectronic semiconductor chip 2 is arranged.
  • the carrier element 3 has a first connection element 4 and a second connection element 5, the optoelectronic semiconductor chip 2 being connected to the first connection element 4 by means of a first connection means 7, which is a bonding wire, and by means of a second connection means 8, in which it which is also a bonding wire, is electrically conductively connected to the second connection element 5 .
  • the first connection element 4 is an anode and the second connection element 5 is a cathode of the semiconductor component 1 .
  • the optoelectronic semiconductor chip 2 comprises a semiconductor body 9 and a first, in particular parabola-shaped, and second, in particular rectilinear, connection contact 10 , 11 , the first connection means 7 being attached to the first connection contact 10 and the second connection means 8 to the second connection contact 11 .
  • the first connection contact 10 is an anode and the second connection contact 11 is a cathode of the semiconductor chip 2 .
  • the first and second connection contacts 10 , 11 are arranged on a first main surface 9A of the semiconductor body 9 .
  • a first main surface 9A of the semiconductor body 9 On a second, opposite the first main surface 9A Main surface 9B is the semiconductor body 9 respectively
  • the optoelectronic semiconductor component 1 has a housing 6 which partially surrounds the optoelectronic semiconductor chip 2 , the housing 6 being arranged on the first main surface 9A and on side surfaces 9C of the semiconductor body 9 or semiconductor chip 2 .
  • the semiconductor components 1 are radiation-emitting components, with the semiconductor body 9 each having an active zone that is provided for generating electromagnetic radiation.
  • electromagnetic radiation is understood to mean, in particular, infrared, visible and/or ultraviolet electromagnetic radiation.
  • part of the radiation generated preferably passes through the first main surface 9A of the semiconductor body 9 .
  • Another part of the radiation can be coupled out through the side areas 9C of the semiconductor body 9 .
  • the semiconductor components 1 are preferably volume emitters with isotropic emission characteristics.
  • the optoelectronic semiconductor components 1 each have a hexagonal ground plan G.
  • This outline shape is advantageously suitable for arranging the optoelectronic semiconductor components 1 in a row without gaps.
  • under the "floor plan G" is a two-dimensional image of an element, for example the semiconductor component 1, in a mounting plane E of the optoelectronic semiconductor component 1 along a transverse, in particular perpendicular to the mounting plane E
  • the semiconductor chip 2 or semiconductor body 9 can have a cuboid shape and also a rectangular outline G, so that the outline shape of the semiconductor chip 2 differs from the outline shape of the optoelectronic semiconductor component 1 .
  • the carrier element 3 has a hexagonal outline G, the outline G of the carrier element 3 corresponding to the outline G of the optoelectronic semiconductor component 1 in its shape and preferably also in its size.
  • the carrier element 3 is preferably a structured layer sequence, with the carrier element 3 having a first, preferably solderable layer 3A facing the carrier 12 and a second layer 3B facing away from the carrier 12, which is preferably a mirror layer.
  • the first and second connection elements 4 , 5 are produced, which are spaced apart from one another by an intermediate space S.
  • the first and second connecting element 4 , 5 each have a pentagonal outline G .
  • the structuring is preferably carried out by means of lithography, as a result of which the intermediate space S can be produced with the smallest possible width B between in particular 50 ⁇ m and 100 ⁇ m.
  • a width B that is as small as possible reduces radiation losses in the intermediate space S .
  • the layers 3A, 3B are preferably formed from at least one metal and/or a metal compound, a TiPtAu compound being suitable for example for the solderable layer 3A and Ag for example being suitable for the mirror layer 3B.
  • the optoelectronic semiconductor chip 2 is arranged partly on the first and partly on the second connection element 4, 5, with the semiconductor chip 2 spanning the gap S between the first and second connection elements 4, 5 and in each case a part of the connection elements 4 , 5 is covered by the semiconductor chip 2 .
  • the housing 6 has a hexagonal layout G, with the layout G of the housing 6 corresponding in particular to the layout G of the optoelectronic semiconductor component 1 and the layout G of the carrier element 3 in terms of shape and preferably also the size.
  • the housing 6 protrudes laterally, ie in directions parallel to the mounting plane E, essentially, ie within the scope of usual manufacturing tolerances, not beyond the carrier element 3 and is preferably flush with the carrier element 3 .
  • the housing 6 can be formed from one layer or from a plurality of layers arranged one above the other, which is/are applied to the semiconductor chip 2 and the carrier element 3 .
  • Plastic materials such as silicones, epoxides or epoxy resins can be used for the housing 6 .
  • the housing 6 can contain converter particles for the wavelength conversion of part of the radiation emitted by the semiconductor body 9 .
  • the semiconductor components 1 are separated from one another by separating regions T whose widths 2t are as small as possible, preferably between 50 ⁇ m and 100 ⁇ m. With conventional sawing, blade widths of 100 or even 200 gm are usually used. In terms of manufacturing technology, the small widths 2t can be realized in particular by using lithographic or stereolithographic methods when producing the housings 6 . As a result, the production areas P2 of the semiconductor components 1 can be reduced and thus the production costs can be reduced.
  • a carrier 12 is provided, to which a layer sequence 3A, 3B is applied, which initially covers the carrier 12 in particular continuously and is then structured (cf. FIGS. 2A and 2B). It is advantageous to use a particularly large carrier 12, for example with an area of 300 mm ⁇ 450 mm, in order to enable cost-effective production.
  • the carrier 12 can be a glass, ceramic or metal carrier.
  • the metal support can contain or consist of steel, FeNi, Mo or MoCu, for example.
  • the carrier 12 can be a printed circuit board (so-called “PCB”).
  • the materials already mentioned in connection with FIGS. 1A and 1B are suitable for the layer sequence 3A, 3B.
  • the layer sequence 3A, 3B is structured in such a way that a plurality of hexagonal carrier elements 3 are formed, each of which has a first, for example pentagonal, connection element 4 and a second, for example, pentagonal, connection element 5, which are separated from one another by a space S. Furthermore, each two adjacent carrier elements 3 are separated from one another by a separating region T.
  • the layer sequence 3A, 3B is structured in particular by means of photolithography.
  • An adhesion layer 13 is arranged between the carrier 12 and the layer sequence 3A, 3B or the carrier elements 3, which provides a mechanical connection between the carrier 12 and the layer sequence 3A, 3B or the carrier elements 3 during production.
  • the adhesion layer 13 is preferably a detachable layer which can be detached from the layer sequence 3A, 3B or the carrier elements 3, for example by means of a laser lift-off method or a peel-off method.
  • a silicon nitride is preferably suitable for the adhesion layer 13 .
  • a polymer such as polydimethylsiloxane (“PDMS”) is particularly suitable for the adhesion layer 13 .
  • a respective semiconductor chip 2 is arranged on the carrier elements 3 .
  • the semiconductor chips 2 can each be attached to the associated carrier element 3 by means of a connecting layer 14 which is, for example, a stamped, printed or phototechnically structured adhesive layer.
  • the semiconductor chips 2 are electrically conductively connected in each case by means of a first and second connecting means 7, 8 to the first and second connection element 4, 5 of the carrier element 3 on which they are arranged (cf. FIGS. 3A and 3B).
  • the connecting means 7 , 8 are bonding wires here.
  • housings 6 are produced, each of which partially surrounds an optoelectronic semiconductor chip 2 (cf. FIGS. 4A and 4B).
  • the housings 6 can be produced from a single layer of starting material, with the layer being structured photolithographically after application.
  • the starting material is preferably a photostructurable material, for example a negative lacquer, which can lead to an undercut or one or more inwardly curved side surfaces 6B on a side edge of each housing 6 .
  • the negative resist is crosslinked in the areas that are exposed. Since exposure is from above, crosslinking decreases downwards due to light absorption. Developing removes the less crosslinked material below, resulting in an undercut.
  • the optoelectronic semiconductor components 1 are advantageously present as individual components on the carrier 12 .
  • the separating areas T are free from the material of the carrier elements
  • the carrier 12 is detached after the step illustrated in FIGS. 4A and 4B, which leads to the isolation of the optoelectronic semiconductor components 1.
  • an intermediate carrier 15 can be applied to the front sides of the housings 6 before the carrier 12 is detached or before the separation.
  • a delimiting layer 16 can be applied to the carrier elements 3 in each case, which partially covers them on their side facing away from the optoelectronic semiconductor chip 2 .
  • the delimiting layer 16 surrounds the carrier element 3 and covers the intermediate space S between the connection elements 4 , 5 .
  • the delimiting layer 16 is designed to be reflective, so that radiation losses in the intermediate space S can be reduced.
  • a wider configuration of the intermediate space S in particular with a width B of more than 200 ⁇ m, is advantageous in order to enable the surface mounting of the semiconductor component 1 .
  • the barrier layer 16 is a white solder resist.
  • the intermediate carrier 15 is detached in order to separate the optoelectronic semiconductor components 1 .
  • FIG. 6C front plan view
  • FIG. 6C rear plan view
  • the optoelectronic semiconductor component 1 additionally has a delimiting layer 16 which partially covers the carrier element 3 on its side facing away from the optoelectronic semiconductor chip 2 .
  • the carrier element 3 is covered by the boundary layer 16 at the side edge and in the region of the intermediate space S.
  • the delimiting layer 16 is preferably a solder stop layer which is intended to prevent a solder material from flowing when the semiconductor component 1 is soldered onto a mounting support, for example a printed circuit board.
  • the delimiting layer 16 particularly preferably has reflective properties, so that radiation losses on the rear side can be reduced.
  • FIGS. 7A top view of the front side
  • 7B cross-sectional view
  • 7C top view of the rear side
  • the semiconductor chip 2 has its two connection contacts 10 , 11 on the main surface 9B of the semiconductor body 9 facing the carrier element 3 .
  • the semiconductor chip 2 is preferably a flip chip, in which in particular the first semiconductor region of the semiconductor body 9 is arranged on the second main surface 9B and the second semiconductor region is arranged on the first main surface 9A.
  • the two connection contacts 10 , 11 are each electrically conductively connected to the associated connection element 4 , 5 by means of a connection means 7 , 8 (not shown), which is in particular a connection layer here.
  • the semiconductor chip 2 according to the third embodiment differs from the rectangular outline according to the first and second embodiment by its hexagonal outline shape corresponding to the carrier element 3 and the housing 6 .
  • FIGS. 8A and 8B show different views of an assembly of optoelectronic semiconductor components 1 according to a fourth exemplary embodiment.
  • the housing 6 has a first area 61 and a second area 62 adjoining the first area 61, with the first and second areas 61, 62 being formed from different materials.
  • the first region 61 is preferably designed to be radiation-permeable, that is to say translucent.
  • the second area 62 is advantageously a wavelength-converting area.
  • the semiconductor chip 2 is arranged in the second region 62, with part of the radiation emitted by the semiconductor chip 2 passing through the second region 62 and being at least partially wavelength-converted before the radiation reaches the first region 61 and can be coupled out of the semiconductor component 1.
  • the second region 62 is surrounded by the first region 61 in a plan view of the semiconductor component 1 (cf. FIG. 8B). This means that the first region 61 is arranged laterally downstream of the second region 62 starting from the semiconductor chip 2 .
  • the second area 62 is arranged in a cavity of the first area 61, the cavity having a substantially constant diameter, that is to say within the scope of normal manufacturing tolerances. In this case, the first area 61 protrudes vertically, that is to say perpendicularly to the mounting plane, beyond the second area 62 .
  • the first area 61 possibly also the second area 62 of the housing 6 is formed from a plurality of layers 60A, 60B, 60C, 60D arranged one on top of the other, which are each applied to the carrier element 3 .
  • the housing 6 can be produced by means of additive manufacturing, with the layers 60A, 60B, 60C, 60D each being structured after application.
  • the starting material for the layers 60A, 60B, 60C, 60D is in particular a photostructurable material, preferably a negative resist, which leads to an undercut or a plurality of inwardly curved side faces 6B on a side edge of each layer 60A, 60B, 60C, 60D.
  • a stereolithographic process is preferably used in additive manufacturing.
  • the housing 6 has on its front side facing away from the carrier element 3 a spacer 17 which is formed in particular from the layer 60D.
  • the spacer 17 protrudes from a main surface 6A of the housing 6 on the front side and is arranged circumferentially in a plan view of the front side (cf. FIG. 8B).
  • the first and second connecting means 7 , 8 are not laterally covered by the spacer 17 .
  • the Spacers 17 can protect the connecting means 7, 8 from mechanical stress during the assembly of the semiconductor component 1, in particular from pressure from above, as is the case with surface mounting, and can divert the acting forces laterally, so that the bonding wires are not bent.
  • FIGS. 9A and 9B show different views of an assembly of optoelectronic semiconductor components 1 according to a fifth exemplary embodiment.
  • the cavity of the first area 61 in which the second area 62 is arranged has a diameter that tapers in the direction of the carrier element 3 .
  • the second region 62 can be reflective and, in particular, can be formed from white casting.
  • the first region 61 can be transparent to radiation.
  • the semiconductor chip 2 is preferably a surface-emitting chip which emits a substantial part of the radiation generated at the first main surface 9A.
  • the semiconductor chip 2 is arranged on the first connection element 4 and is electrically conductively connected thereto at its first connection contact 10 (not shown) by means of a connection means 7, in particular a connection layer.
  • the first connection element 4 is partially laterally covered by the entire optoelectronic semiconductor chip 2 .
  • the semiconductor chip 2 has a second connection contact 11 on the first main area 9A, which is electrically conductively connected to the second connection element 5 by means of a connecting means 8 , in particular a bonding wire.
  • a connecting means 8 in particular a bonding wire.
  • the semiconductor chip 2 is arranged in the first area 61 of the housing 6 .
  • the first area 61 is reflective and formed in particular from a white encapsulation, while the second area 62 is transparent to radiation.
  • these optoelectronic semiconductor components 1 have an anisotropic emission, in particular in the vertical direction V, while the optoelectronic semiconductor component 1 according to the fourth exemplary embodiment has an isotropic emission characteristic.
  • the first and second areas 61 , 62 on the front side of the semiconductor component 1 end flush with one another.
  • the second area 62 is arranged on the first area 61 .
  • the second area 62 is arranged in a cavity of the first area 61 , which has a diameter that tapers in the direction of the carrier element 3 , and protrudes beyond the first area 61 .
  • the second area 62 is convexly curved and in particular has the effect of a lens.
  • the first area 61 advantageously has a stop layer 61A surrounding the cavity, which restricts the spread of a material used for the production of the second area 62 in a targeted manner during the production of the second area 62, preferably by means of dispensing.
  • FIG. 12 the second area 62 is arranged in a cavity of the first area 61 , which has a diameter that tapers in the direction of the carrier element 3 , and protrudes beyond the first area 61 .
  • the second area 62 is convexly curved and in particular has the effect of a lens.
  • the first area 61 advantageously has a stop layer 61A surrounding the cavity, which restricts the spread of a material used for the production of
  • the semiconductor chip 2 which is preferably a surface-emitting chip, has a conversion element 18, such as a small ceramic plate, on the first main surface 9A for wavelength conversion of the radiation emitted by the semiconductor body 9.
  • the semiconductor chip 2 is arranged in the second area 62 which is located in a cavity of the first area 61 .
  • the housing 6 can be manufactured as described in connection with the fourth exemplary embodiment, with the second area 62 preferably being formed from a reflective material, for example a white filling.
  • the optoelectronic semiconductor component 1 has in particular an isotropic emission characteristic. Otherwise, the statements made on the previous exemplary embodiments apply.
  • the semiconductor chip 2 which is preferably a surface-emitting chip, is arranged in the first area 61 of the housing 6 .
  • the first region 61 contains absorbent particles for absorbing part of the radiation emitted by the semiconductor body 9 .
  • the second area 62 of the housing 6 is arranged on the first area 61 and is designed as a preferably radiation-transmissive spacer 17 .
  • the two areas 61 , 62 can each be produced in layers by means of stereolithography. For the rest, the explanations given for the previous exemplary embodiments apply.
  • the semiconductor component 1 in contrast to that in Figure 14
  • the illustrated embodiment has a flat second connecting means 8, a so-called “planar interconnect".
  • the "planar interconnect” is equivalent to the electrical contacts in the so-called “eWLP” (embedded wafer level packaging).
  • the connecting means 8 is preferably embedded in the second area 62 of the housing 6, with the second area 62 being arranged as a continuous, flat layer on the first area 61.
  • Figure 16A shows a schematic top view of a square semiconductor component 1
  • Figure 16B shows a schematic top view of a hexagonal semiconductor component 1, each having a base or chip area CI or C2, which correspond in size in particular to the first and second main areas 9A, 9B, and a component area Dl or Have D2, the component area D1, D2 being increased by a space required for the connecting means 7, 8 compared to the chip area C1, C2.
  • the component area D1, D2 corresponds in particular to the size of the floor plan G.
  • a production area P1, P2 required for the respective component 1 results from the component area D1, D2 plus the width t of the separating area T.
  • the production area P2 of the hexagonal semiconductor device 1 which is a regular hexagon, can be calculated as follows: where "r” corresponds to a height of the equilateral triangles included in the hexagonal semiconductor chip 2 and "r+b" corresponds to a height of the equilateral triangles included in the hexagonal semiconductor device 1.
  • the optoelectronic semiconductor components 1 have a plurality of semiconductor chips 2A, 2B, 2C, with at least two of the semiconductor chips 2A, 2B, 2C emitting radiation of different colors during operation.
  • the optoelectronic semiconductor components 1 preferably emit white light during operation.
  • the carrier element 3 has a hexagonal outline and a plurality of first and a plurality of second connection elements 4 , 5 which are spaced apart from one another by intermediate spaces S.
  • the semiconductor chips 2A which preferably emit red and infrared radiation, are arranged on a common first connection element 4 and are each electrically conductively connected to a separate second connection element 5 by means of a second connection means 8, in particular a bonding wire.
  • the differently colored semiconductor chip 2B for example green, is arranged on a separate second connection element 5 and is electrically conductively connected to a separate first connection element 4 by means of a first connection means 7, in particular a bonding wire.
  • the semiconductor chips 2A, 2B can each be electrically controlled separately.
  • the semiconductor chips 2A are on a common first one as in the embodiment shown in FIG. 19, the semiconductor chips 2A are on a common first one as in the embodiment shown in FIG. 19,
  • connection element 4 arranged while the differently colored Semiconductor chip 2B is arranged on a separate second connection element 5 . Furthermore, the second connection means 8 of the semiconductor chips 2A are electrically conductively connected to the same second connection element 5 and are therefore connected in parallel. The differently colored semiconductor chip 2B is electrically conductively connected by means of the first connecting means 7 to the first connection element 4 on which the semiconductor chips 2A are arranged.
  • the optoelectronic semiconductor component 1 has three differently colored semiconductor chips 2A, for example red, 2B, for example blue, 2C, for example green, with the semiconductor chips 2A, 2B, 2C being connected to a common first connection element 4 are arranged and are each electrically conductively connected to a separate second connection element 5 by means of second connecting means 8, so that the semiconductor chips 2A, 2B, 2C are electrically controllable separately.
  • the carrier element 3 is not hexagonal but triangular, while the semiconductor chips 2A, 2B, 2C are square.
  • the differently colored semiconductor chips 2A, 2B, 2C are interconnected and arranged in the same way as in the exemplary embodiment shown in FIG.
  • the semiconductor chips 2A, 2B, 2C have a triangular outline shape and the carrier element 3 has a quadrangular outline shape.
  • FIGS. 22A to 22H illustrate possible outline shapes of the optoelectronic semiconductor components described here
  • the ground plan G can be a hexagon (cf. Figure 22H), in particular a regular hexagon (cf.
  • Figure 22A a quadrilateral created by bisecting a hexagon along an axis of symmetry X (see Figures 22B and 22D), a pentagon created by bisecting a hexagon along an axis of symmetry X (see Figure 22C) or a hexagon created by dividing a hexagon along several axes of symmetry X resulting triangle (see. Figures 22E and 22G) or square (see. Figure 22F).
  • the invention is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses every new feature and every combination of features, which in particular includes every combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.

Abstract

L'invention porte sur un composant semi-conducteur optoélectronique (1) comprenant : - au moins une puce semi-conductrice optoélectronique (2), - un élément de support (3) qui présente au moins un premier élément de raccordement (4) et au moins un deuxième élément de raccordement (5) pour la mise en contact électrique du composant semi-conducteur optoélectronique (1) depuis l'extérieur, la ou les puces semi-conductrices optoélectroniques (2) étant disposées sur l'élément de support (3) et étant électriquement connectées à un premier et un second élément de raccordement (4, 5) de l'élément de support (3), - un boîtier (6), qui s'étend au moins partiellement autour de la ou des puces semi-conductrices optoélectroniques (2). Le composant semi-conducteur optoélectronique (1) présente une zone de base (G) polygonale et non rectangulaire. L'invention concerne en outre un procédé de fabrication d'au moins un composant semi-conducteur optoélectronique.
PCT/EP2021/079178 2020-11-16 2021-10-21 Composant semi-conducteur optoélectronique et son procédé de production WO2022100976A1 (fr)

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