WO2022099648A1 - 驱动电路、其驱动方法及显示装置 - Google Patents

驱动电路、其驱动方法及显示装置 Download PDF

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Publication number
WO2022099648A1
WO2022099648A1 PCT/CN2020/128814 CN2020128814W WO2022099648A1 WO 2022099648 A1 WO2022099648 A1 WO 2022099648A1 CN 2020128814 W CN2020128814 W CN 2020128814W WO 2022099648 A1 WO2022099648 A1 WO 2022099648A1
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Prior art keywords
transistor
level
nth row
electrically connected
light
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Application number
PCT/CN2020/128814
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English (en)
French (fr)
Inventor
黄耀
黄炜赟
龙跃
王本莲
徐元杰
杜丽丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/128814 priority Critical patent/WO2022099648A1/zh
Priority to CN202080002786.4A priority patent/CN114930440A/zh
Priority to US18/036,422 priority patent/US20240021141A1/en
Publication of WO2022099648A1 publication Critical patent/WO2022099648A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • other electroluminescent diodes have self-illumination, low energy consumption, etc.
  • the advantages are one of the hot spots in the field of application research of electroluminescent display devices.
  • driving circuits are used to drive electroluminescent diodes to emit light.
  • the brightness adjustment range of the electroluminescent diode is limited.
  • a light-emitting device configured to emit light under the control of the driving current
  • a drive transistor configured to generate the drive current according to a data signal
  • a first control circuit configured to provide an initialization signal to the gate of the driving transistor and the first light emitting device of the light emitting device in response to the first scan signal of the Nth row and the first light emission control signal of the Nth row, respectively electrode;
  • N is an integer;
  • a data writing circuit is configured to supply the data signal to the driving transistor in response to the second scan signal of the Nth row.
  • the first control circuit includes:
  • a first sub-control circuit respectively electrically connected to the first scan signal terminal of the Nth row, the first light emission control signal terminal of the Nth row, the initialization signal terminal and the gate of the driving transistor, and
  • the first sub-control circuit is configured to initialize the initialization in response to a first scan signal at the first scan signal terminal of the Nth row and a first lighting control signal at the first lighting control signal terminal of the Nth row
  • the initialization signal loaded by the signal terminal is provided to the gate of the driving transistor;
  • the third sub-control circuit is respectively electrically connected to the first light-emitting control signal terminal of the Nth row, the second electrode of the driving transistor and the first electrode of the light-emitting device, and the third sub-control circuit is It is configured to turn on the second electrode of the driving transistor and the first electrode of the light emitting device in response to the first light emitting control signal at the first light emitting control signal terminal of the Nth row.
  • the gate of the first transistor is electrically connected to the first scan signal terminal of the Nth row, the first pole of the first transistor is electrically connected to the initialization signal terminal, and the second pole of the first transistor is electrically connected electrically connected to the first pole of the second transistor;
  • the gate of the second transistor is electrically connected to the first light-emitting control signal terminal of the Nth row, and the second electrode of the second transistor is electrically connected to the gate of the driving transistor.
  • the gate of the third transistor is electrically connected to the first scan signal terminal of the Nth row, the first electrode of the third transistor is electrically connected to the gate of the driving transistor, and the first electrode of the third transistor is electrically connected to the gate of the driving transistor.
  • the diode is electrically connected to the second electrode of the driving transistor.
  • the third sub-control circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the first light-emitting control signal terminal of the Nth row, the first pole of the fourth transistor is electrically connected to the second pole of the driving transistor, and the fourth transistor The second electrode of the light emitting device is electrically connected to the first electrode of the light emitting device.
  • the data writing circuit includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the second scan signal of the Nth row, and the first electrode of the fifth transistor is electrically connected to the data signal terminal for loading the data signal.
  • the driving circuit further includes: a second control circuit configured to turn on the first power supply terminal and the driving transistor in response to the second lighting control signal of the Nth row.
  • the second control circuit includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the second light-emitting control signal terminal of the Nth row loaded with the second light-emitting control signal, and the first electrode of the sixth transistor is electrically connected to the first power supply terminal connected, the second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor.
  • the drive circuit further includes a storage capacitor
  • the first electrode plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second electrode plate of the storage capacitor is electrically connected to the first power supply terminal.
  • the driving circuit provided by the embodiment of the present disclosure includes: a driving transistor, a first transistor to a sixth transistor, and a storage capacitor;
  • the gate of the first transistor is electrically connected to the first scan signal terminal of the Nth row, the first pole of the first transistor is electrically connected to the initialization signal terminal, and the second pole of the first transistor is electrically connected electrically connected to the first pole of the second transistor;
  • the gate of the second transistor is electrically connected to the first light-emitting control signal terminal of the Nth row, and the second electrode of the second transistor is electrically connected to the gate of the driving transistor;
  • the gate of the third transistor is electrically connected to the first scan signal terminal of the Nth row, the first electrode of the third transistor is electrically connected to the gate of the driving transistor, and the first electrode of the third transistor is electrically connected to the gate of the driving transistor.
  • the diode is electrically connected to the second electrode of the driving transistor;
  • the gate of the fourth transistor is electrically connected to the first light-emitting control signal terminal of the Nth row, the first pole of the fourth transistor is electrically connected to the second pole of the driving transistor, and the fourth transistor
  • the second electrode of the light-emitting device is electrically connected to the first electrode of the light-emitting device
  • the gate of the fifth transistor is electrically connected to the second scan signal of the Nth row, and the first electrode of the fifth transistor is electrically connected to the data signal terminal for loading the data signal;
  • the gate of the sixth transistor is electrically connected to the second light-emitting control signal terminal of the Nth row loaded with the second light-emitting control signal, and the first electrode of the sixth transistor is electrically connected to the first power supply terminal connected, the second pole of the sixth transistor is electrically connected to the first pole of the driving transistor;
  • the first electrode plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second electrode plate of the storage capacitor is electrically connected to the first power supply terminal.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned driving circuit.
  • the level of the first scan signal of the Nth row is controlled to be the first level
  • the level of the second scan signal of the Nth row is controlled to be the second level
  • the level of the Nth row of the first scan signal is controlled to be the second level.
  • the level of a light-emitting control signal is a first level, so that the first control circuit provides an initialization signal to the gate of the driving transistor and the first electrode of the light-emitting device, respectively;
  • the level of the first scan signal of the Nth row is controlled to be the first level
  • the level of the second scan signal of the Nth row is controlled to be the first level
  • the level of the Nth row The level of the first light-emitting control signal is a second level, so that the data writing circuit provides the data signal to the driving transistor;
  • the level of the first scan signal of the Nth row is controlled to be the second level
  • the level of the second scan signal of the Nth row to the second level
  • the level of the Nth row of the second scan signal is controlled to be the second level.
  • the level of a light-emitting control signal is a first level, so that the driving transistor generates a driving current according to the data signal, and the light-emitting device emits light under the control of the driving current.
  • the driving method further includes:
  • the level of the second light-emitting control signal of the Nth row is controlled to be the first level.
  • the level of the first scan signal of the Nth row is controlled to be the second level, the level of the second scan signal of the Nth row to the first level, and the level of the Nth row
  • the level of the first lighting control signal is the second level.
  • the first buffering stage further includes: controlling the level of the second lighting control signal of the Nth row to be a second level.
  • the level of the first scan signal of the Nth row is controlled to be the second level, the level of the second scan signal of the Nth row to the second level, and the level of the Nth row
  • the level of the first lighting control signal is the second level.
  • the second buffering stage further includes: controlling the level of the second lighting control signal of the Nth row to be a first level.
  • FIG. 2 is some circuit timing diagrams of the driving circuit provided by the embodiments of the present disclosure.
  • FIG. 3 is further circuit timing diagrams of the driving circuit provided by the embodiments of the present disclosure.
  • FIG. 4 is further circuit timing diagrams of the driving circuit provided by the embodiments of the present disclosure.
  • FIG. 5 is a flowchart of a driving method provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a driving circuit, as shown in FIG. 1 , which may include:
  • the light-emitting device L configured to emit light under the control of the driving current
  • a driving transistor M0 configured to generate a driving current according to the data signal
  • the first control circuit 10 is configured to provide an initialization signal to the gate of the driving transistor M0 and the first electrode of the light emitting device L in response to the first scan signal of the Nth row and the first light emission control signal of the Nth row, respectively ;
  • the data writing circuit 20 is configured to supply a data signal to the driving transistor M0 in response to the second scan signal of the Nth row.
  • the first control circuit 10 may include: a first sub-control circuit 11 , a second sub-control circuit 12 and a third sub-control circuit 13 ;
  • the first sub-control circuit 11 is respectively electrically connected to the first scan signal terminal GA1 of the Nth row, the first light-emitting control signal terminal EM1 of the Nth row, the initialization signal terminal and the gate of the driving transistor M0, and the first sub-control circuit 11 is configured to provide the initialization signal loaded by the initialization signal terminal to the first scan signal of the first scan signal terminal GA1 of the Nth row and the first lighting control signal of the first lighting control signal terminal EM1 of the Nth row. the gate of the drive transistor M0;
  • the second sub-control circuit 12 is respectively electrically connected to the first scan signal terminal GA1 of the Nth row, the gate of the driving transistor M0 and the second electrode, and the second sub-control circuit 12 is configured to respond to the first scan signal terminal GA1 of the Nth row.
  • the first scanning signal of the scanning signal terminal GA1 conducts the gate of the driving transistor M0 and the second electrode thereof;
  • the third sub-control circuit 13 is respectively electrically connected to the first light-emitting control signal terminal EM1 of the Nth row, the second electrode of the driving transistor M0 and the first electrode of the light-emitting device L, and the third sub-control circuit 13 is configured to respond to The first light-emitting control signal of the first light-emitting control signal terminal EM1 in the Nth row conducts the second electrode of the driving transistor M0 and the first electrode of the light-emitting device L into conduction.
  • the initialization can be performed.
  • the initialization signal loaded at the signal terminal is provided to the gate of the driving transistor M0 to initialize the gate of the driving transistor M0.
  • the second sub-control circuit 12 responds to the first scan signal of the first scan signal terminal GA1 of the Nth row, the gate of the driving transistor M0 and its second pole are turned on; and the third sub-control circuit 13 responds to The first light-emitting control signal of the first light-emitting control signal terminal EM1 of the Nth row conducts the second electrode of the driving transistor M0 and the first electrode of the light-emitting device L, so that the initialization of the gate input to the driving transistor M0 can be performed.
  • a signal is input to the first electrode of the light-emitting device L through the second sub-control circuit 12 and the third sub-control circuit 13 to initialize the first electrode of the light-emitting device L at the same time.
  • the driving circuit may further include: a second control circuit 30 configured to connect the first power supply terminal to the second light-emitting control signal of the Nth row in response to the VDD is turned on with the driving transistor M0.
  • the first electrode of the light emitting device L is electrically connected to the third sub-control circuit 13
  • the second electrode of the light emitting device L is electrically connected to the second power supply terminal VSS.
  • the first electrode of the light-emitting device L may be its positive electrode
  • the second electrode may be its negative electrode.
  • the light-emitting device L may be configured as an electroluminescent diode, for example, the light-emitting device L may include: a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED) and At least one of quantum dot light-emitting diodes (Quantum Dot Light Emitting Diodes, QLED).
  • the light-emitting device L generally has a light-emitting threshold voltage, and emits light when the voltage across the light-emitting device L is greater than or equal to the light-emitting threshold voltage.
  • the specific structure of the light emitting device L can be designed and determined according to the actual application environment, which is not limited herein.
  • the first sub-control circuit 11 may include: a first transistor M1 and a second transistor M2;
  • the gate of the second transistor M2 is electrically connected to the first light-emitting control signal terminal EM1 of the Nth row, and the second electrode of the second transistor M2 is electrically connected to the gate of the driving transistor M0.
  • the second sub-control circuit 12 may include a third transistor M3;
  • the gate of the third transistor M3 is electrically connected to the first scan signal terminal GA1 of the Nth row, the first pole of the third transistor M3 is electrically connected to the gate of the driving transistor M0, and the second pole of the third transistor M3 is electrically connected to the driving transistor The second pole of M0 is electrically connected.
  • the third sub-control circuit 13 may include a fourth transistor M4;
  • the gate of the fourth transistor M4 is electrically connected to the first light-emitting control signal terminal EM1 of the Nth row, the first pole of the fourth transistor M4 is electrically connected to the second pole of the driving transistor M0, and the second pole of the fourth transistor M4 is electrically connected to the second pole of the driving transistor M0.
  • the first electrodes of the light emitting device L are electrically connected.
  • the data writing circuit 20 may include a fifth transistor M5;
  • the gate of the fifth transistor M5 is electrically connected to the second scan signal terminal GA2 of the Nth row, and the first electrode of the fifth transistor M5 is electrically connected to the data signal terminal DA for loading the data signal.
  • the second control circuit 30 may include a sixth transistor M6;
  • the gate of the sixth transistor M6 is electrically connected to the second light-emitting control signal terminal EM2 of the Nth row loaded with the second light-emitting control signal, the first pole of the sixth transistor M6 is electrically connected to the first power supply terminal VDD, and the sixth transistor M6
  • the second electrode of the transistor M0 is electrically connected to the first electrode of the driving transistor M0.
  • the driving circuit may further include a storage capacitor CST;
  • the first electrode plate of the storage capacitor CST is electrically connected to the gate of the driving transistor M0, and the second electrode plate of the storage capacitor CST is electrically connected to the first power supply terminal VDD.
  • the driving transistor M0 may be a P-type transistor; wherein, the first pole of the driving transistor M0 is its source, and the second pole of the driving transistor M0 is its drain , and when the driving transistor M0 is in a saturated state, the current flows from the source of the driving transistor M0 to the drain thereof.
  • the driving transistor M0 may also be an N-type transistor; wherein, the first electrode of the driving transistor M0 is its drain electrode, the second electrode of the driving transistor M0 is its source electrode, and the When the drive transistor M0 is in a saturated state, current flows from the drain of the drive transistor M0 to its source.
  • the first to sixth transistors M1 to M6 may all be P-type transistors.
  • the first to sixth transistors M1 ⁇ M6 can also be all N-type transistors, which can also be designed and determined according to the actual application environment, which is not limited here.
  • the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
  • the N-type transistor is turned on under the action of a high-level signal, and turned off under the action of a low-level signal.
  • the transistor mentioned in the above-mentioned embodiments of the present disclosure may be a thin film transistor (Thin Film Transistor, TFT) or a metal oxide semiconductor field effect transistor (Metal Oxide Scmiconductor, MOS), which is not limited here.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Scmiconductor
  • the first electrode of the transistor can be used as its source electrode, and the second electrode can be used as its drain electrode; or, conversely, the first electrode of the transistor can be used as its drain electrode , the second pole is used as its source, which can be designed and determined according to the actual application environment, and no specific distinction will be made here.
  • the voltage Vdd of the first power supply terminal is generally positive, and the voltage Vss of the second power supply terminal is generally grounded or negative.
  • the specific values of the voltage Vdd of the first power supply terminal and the voltage Vss of the second power supply terminal can be designed and determined according to the actual application environment, which is not limited herein.
  • the voltage Vinit of the initialization signal and the voltage Vss of the second power supply terminal may satisfy the following formula: Vinit ⁇ Vss ⁇ VL.
  • VL represents the emission threshold voltage of the light emitting device L.
  • Embodiments of the present disclosure also provide a driving method for the above-mentioned driving circuit, as shown in FIG. 5 , which may include the following steps:
  • the level of the first level is the first level, so that the first control circuit provides the initialization signal to the gate of the driving transistor and the first electrode of the light-emitting device respectively;
  • the level of the first scan signal in the Nth row is controlled to be the first level
  • the level of the second scan signal in the Nth row is the first level
  • the first light emission in the Nth row is controlled
  • the level of the control signal is the second level, so that the data writing circuit provides the data signal to the driving transistor
  • the first control circuit in the initialization stage, can respectively provide the initialization signal to the driving transistor in response to the first scanning signal of the Nth row and the first light-emitting control signal of the Nth row. the gate electrode and the first electrode of the light emitting device, so as to simultaneously initialize the gate electrode of the driving transistor and the first electrode of the light emitting device.
  • the data writing circuit can provide the data signal to the driving transistor in response to the second scan signal of the Nth row, so that the driving transistor can generate the driving current according to the data signal in the light emitting stage, so that the light emitting device can be It emits light under the control of driving current.
  • the driving method may further include: in the initialization stage, controlling the level of the second lighting control signal of the Nth row to be the second level; in the data writing stage, the level of the second light-emitting control signal controlling the Nth row is the second level; in the light-emitting stage, the level of the second light-emitting control signal controlling the Nth row is the first level .
  • ga1-N represents the first scan signal of the Nth row
  • ga2-N represents the second scan signal of the Nth row
  • em1-N represents the first light-emitting control signal of the Nth row
  • em2-N represents the first light-emitting control signal of the Nth row
  • the working process of a driving circuit in one display frame may include: an initialization phase T1, a data writing phase T2, and a light-emitting phase T3.
  • the first transistor M1 is turned on under the control of the low level of the signal ga1-N, and the second transistor M2 is also turned on under the control of the low level of the signal em1-N, which makes the initialization signal terminal
  • the initialization signal of VINIT can be provided to the gate N3 of the driving transistor M0 through the turned-on first transistor M1 and the second transistor M2, so that the voltage of the gate N3 of the driving transistor M0 is Vinit, and then the gate of the driving transistor M0 is N3 is initialized.
  • the third transistor M3 is turned on under the control of the low level of the signal ga1-N
  • the fourth transistor M4 is also turned on under the control of the low level of the signal em1-N, so that the initialization of the initialization signal terminal VINIT A signal may be provided to the first electrode of the light emitting device L through the turned-on third transistor M3 and the fourth transistor M4 to initialize the first electrode of the light emitting device L.
  • the sixth transistor M6 is turned off under the control of the high level of the signal em2-N.
  • the fifth transistor M5 is turned off under the control of the high level of the signal ga2-N.
  • the fifth transistor M5 is turned on under the control of the low level of the signal ga2-N, so as to provide the data signal of the data signal terminal DA to the first pole N1 of the driving transistor M0, so that the driving transistor
  • the voltage of the first pole N1 of M0 is the voltage Vda of the data signal.
  • the third transistor M3 is turned on under the control of the low level of the signal ga1-N, which can make the driving transistor M0 form a diode connection, so that the voltage Vda of the first pole N1 of the driving transistor M0 is connected to the gate of the driving transistor M0.
  • the pole N3 is charged and stored through the storage capacitor CST.
  • the second transistor M2 and the fourth transistor M4 are turned off under the control of the high level of the signal em1-N
  • the sixth transistor M6 is turned off under the control of the high level of the signal em2-N.
  • the sixth transistor M6 is turned on under the control of the low level of the signal em2-N, and the turned-on sixth transistor M6 can provide the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor M0 N1, so that the voltage of the first pole N1 of the driving transistor M0 is Vdd.
  • the fourth transistor M4 is turned on under the control of the low level of the signal em1-N, and the turned-on fourth transistor M4 can conduct the second electrode N2 of the driving transistor M0 and the first electrode of the light emitting device L, thereby The driving current Ids is made to flow into the light emitting device L to drive the light emitting device L to emit light.
  • K is a structural constant related to process and design.
  • the first transistor M1 and the third transistor M3 are turned off under the control of the high level of the signal ga1-N.
  • the fifth transistor M5 is turned off under the control of the high level of the signal ga2-N.
  • a first buffer stage may be further included.
  • the level of the first scan signal of the Nth row is controlled to be the second level, the level of the second scan signal of the Nth row to the first level, and the first light emission of the Nth row
  • the level of the control signal is the second level.
  • the first buffering stage may further include: controlling the level of the second lighting control signal of the Nth row to be the second level.
  • the first transistor M1 is turned on under the control of the low level of the signal ga1-N, and the second transistor M2 is also turned on under the control of the low level of the signal em1-N, which makes the initialization signal terminal
  • the initialization signal of VINIT can be provided to the gate N3 of the driving transistor M0 through the turned-on first transistor M1 and the second transistor M2, so that the voltage of the gate N3 of the driving transistor M0 is Vinit, and then the gate of the driving transistor M0 is N3 is initialized.
  • the third transistor M3 is turned on under the control of the low level of the signal ga1-N
  • the fourth transistor M4 is also turned on under the control of the low level of the signal em1-N, so that the initialization of the initialization signal terminal VINIT A signal may be provided to the first electrode of the light emitting device L through the turned-on third transistor M3 and the fourth transistor M4 to initialize the first electrode of the light emitting device L.
  • the sixth transistor M6 is turned off under the control of the high level of the signal em2-N.
  • the fifth transistor M5 is turned off under the control of the high level of the signal ga2-N.
  • the fifth transistor M5 is turned on under the control of the low level of the signal ga2-N, so as to provide the data signal of the data signal terminal DA to the first pole N1 of the driving transistor M0, so that the driving transistor
  • the voltage of the first pole N1 of M0 is the voltage Vda of the data signal.
  • the third transistor M3 is turned on under the control of the low level of the signal ga1-N, which can make the driving transistor M0 form a diode connection, so that the voltage Vda of the first pole N1 of the driving transistor M0 is connected to the gate of the driving transistor M0.
  • the pole N3 is charged and stored through the storage capacitor CST.
  • the second transistor M2 and the fourth transistor M4 are turned off under the control of the high level of the signal em1-N
  • the sixth transistor M6 is turned off under the control of the high level of the signal em2-N.
  • the sixth transistor M6 is turned on under the control of the low level of the signal em2-N, and the turned-on sixth transistor M6 can provide the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor M0 N1, so that the voltage of the first pole N1 of the driving transistor M0 is Vdd.
  • the first buffering stage and before the light-emitting stage further includes: a second buffering stage.
  • the level of the first scan signal of the Nth row is controlled to be the second level, the level of the second scan signal of the Nth row to the second level, and the first light emission of the Nth row
  • the level of the control signal is the second level.
  • the second buffering stage further includes: controlling the level of the second light-emitting control signal of the Nth row to be the first level.
  • the first transistor M1 is turned on under the control of the low level of the signal ga1-N, and the second transistor M2 is also turned on under the control of the low level of the signal em1-N, which makes the initialization signal terminal
  • the initialization signal of VINIT can be provided to the gate N3 of the driving transistor M0 through the turned-on first transistor M1 and the second transistor M2, so that the voltage of the gate N3 of the driving transistor M0 is Vinit, and then the gate of the driving transistor M0 is N3 is initialized.
  • the fifth transistor M5 is turned on under the control of the low level of the signal ga2-N, so as to provide the data signal of the data signal terminal DA to the first pole N1 of the driving transistor M0, so that the driving transistor
  • the voltage of the first pole N1 of M0 is the voltage Vda of the data signal.
  • the third transistor M3 is turned on under the control of the low level of the signal ga1-N, which can make the driving transistor M0 form a diode connection, so that the voltage Vda of the first pole N1 of the driving transistor M0 is connected to the gate of the driving transistor M0.
  • the pole N3 is charged and stored through the storage capacitor CST.
  • the second transistor M2 and the fourth transistor M4 are turned off under the control of the high level of the signal em1-N
  • the sixth transistor M6 is turned off under the control of the high level of the signal em2-N.
  • the fifth transistor M5 is turned on under the control of the low level of the signal ga2-N, so as to provide the data signal of the data signal terminal DA to the first pole N1 of the driving transistor M0, so that the driving transistor M0
  • the voltage of the first pole N1 of M0 continues to be the voltage Vda of the data signal.
  • the first transistor M1 and the third transistor M3 are turned off under the control of the high level of the signal ga1-N.
  • the second transistor M2 and the fourth transistor M4 are turned off under the control of the high level of the signal em1-N.
  • the sixth transistor M6 is turned off under the control of the high level of the signal em2-N.
  • the sixth transistor M6 is turned on under the control of the high level of the signal em2-N.
  • the turned-on sixth transistor M6 may provide the voltage Vdd of the first power supply terminal VDD to the first pole N1 of the driving transistor M0, so that the voltage of the first pole N1 of the driving transistor M0 is Vdd. In this way, the first pole N1 of the driving transistor M0 can be precharged through the first power supply terminal VDD.
  • the first transistor M1 and the third transistor M3 are turned off under the control of the high level of the signal ga1-N.
  • the second transistor M2 and the fourth transistor M4 are turned off under the control of the high level of the signal em1-N.
  • the fifth transistor M5 is turned off under the control of the high level of the signal ga2-N.
  • the sixth transistor M6 is turned on under the control of the low level of the signal em2-N, and the turned-on sixth transistor M6 can provide the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor M0 N1, so that the voltage of the first pole N1 of the driving transistor M0 is Vdd.
  • the fourth transistor M4 is turned on under the control of the low level of the signal em1-N, and the turned-on fourth transistor M4 can conduct the second electrode N2 of the driving transistor M0 and the first electrode of the light emitting device L, thereby The driving current Ids is made to flow into the light emitting device L to drive the light emitting device L to emit light.
  • K is a structural constant related to process and design.
  • the first transistor M1 and the third transistor M3 are turned off under the control of the high level of the signal ga1-N.
  • the fifth transistor M5 is turned off under the control of the high level of the signal ga2-N.
  • the fifth transistor M5 can be turned on continuously, so as to make the charging more sufficient.
  • the fourth transistor M4 can be controlled to be turned off, so that the voltage of the gate of the driving transistor can be further increased. After stabilization, even if the current generated by the driving transistor is further stabilized, it is provided to the light-emitting device, so that the light-emitting stability of the light-emitting device can be further improved.
  • the gate driving circuit in the related art can be used to provide signals to the first scanning signal line and the second scanning signal line, and the gate driving circuit in the related art can be used.
  • the lighting control circuit provides signals to the first lighting control signal line and the second lighting control signal line.
  • the first buffer stage T4 and the second buffer stage T5 may not be provided, so that the structures of the gate driving circuit and the light-emitting control circuit can be redesigned to satisfy the signal timing shown in FIG. 2 .
  • an embodiment of the present disclosure further provides a display device including the above-mentioned driving circuit provided by the embodiment of the present disclosure.
  • the principle of solving the problem of the display device is similar to that of the aforementioned driving circuit, so the implementation of the display device can refer to the implementation of the aforementioned driving circuit, and the repetition is not repeated here.
  • the display device may include a display area, and the display area includes a Q row signal line group and a Y column data line, and the Q row signal line group and the Y column data line are crossed.
  • each row signal line group includes a first scan signal line, a second scan signal line, a first light emission control signal line, and a second light emission control signal line.
  • the Q-row signal line groups are sequentially arranged along the extending direction of the data lines.
  • the first lighting control signal line in the signal line group of the Nth row may be the first lighting control signal line of the Nth row, then the first lighting control signal of the Nth row is transmitted on the first lighting control signal line of the Nth row signal, that is, the first lighting control signal terminal of the Nth row is electrically connected to the first lighting control signal line of the Nth row.
  • the second lighting control signal line in the signal line group of the Nth row may be the second lighting control signal line of the Nth row, and the second lighting control signal of the Nth row is transmitted on the second lighting control signal line of the Nth row.
  • signal that is, the second lighting control signal terminal of the Nth row is electrically connected to the second lighting control signal line of the Nth row.
  • the data lines are used to transmit data signals.
  • the data signal terminal is electrically connected with the data line, so that the data signal terminal is loaded with the data signal.
  • the display area may further include driving circuits of Q rows and Y columns.
  • one row of driving circuits may correspond to one row of signal line groups. That is, one row of driving circuits corresponds to one first scanning signal line, one second scanning signal line, one first light-emitting control signal line, and one second light-emitting control signal line. Then, the first scan signal terminal of the driving circuit in the Nth row is electrically connected to the first scan signal line in the Nth row. The second scan signal terminal of the driving circuit in the Nth row is electrically connected to the second scan signal line in the Nth row. The first lighting control signal terminal of the driving circuit in the Nth row is electrically connected to the first lighting control signal line in the Nth row. The second light-emitting control signal terminal of the driving circuit in the Nth row is electrically connected to the second light-emitting control signal line in the Nth row.
  • the first scanning signal line of this row can provide the first scanning signal to the driving circuit of this row, so that the first scanning signal of the Nth row and the first scanning signal of the N-1th row or the N+1th row can be made Signals are transmitted using mutually independent signal lines to reduce delay and interference of the first scan signal.
  • the second scanning signal line of this row can provide the second scanning signal to the driving circuit of this row, so that the second scanning signal of the Nth row and the second scanning signal of the N-1th row or the N+1th row can be made
  • the two scan signals are transmitted using mutually independent signal lines, so as to reduce the delay and interference of the second scan signal.
  • the second lighting control signal line of this row can provide the second lighting control signal to the driving circuit of this row, so that the second lighting control signal of the Nth row and the N-1th row or the N+1th row can be
  • the second lighting control signal of the row is transmitted using mutually independent signal lines, so as to reduce the delay and interference of the second lighting control signal.
  • the display area includes a plurality of pixel units arranged in an array.
  • Each pixel unit includes a plurality of sub-pixels.
  • the pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to realize color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that red, green, blue and white colors can be mixed to realize color display.
  • the emission colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited here.
  • each sub-pixel may include the above-mentioned driving circuit, so that the sub-pixel can realize electroluminescence display.
  • one column of sub-pixels may correspond to one data line, and the data signal terminals of the driving circuits in the column are electrically connected to the corresponding data line.
  • One row of sub-pixels may correspond to one row of signal line groups, and then one row of sub-pixels may correspond to one first scan signal line, one second scan signal line, one first light emission control signal line, and one second light emission control signal line. That is to say, the first scanning signal terminal GA1 of the driving circuit in the first row of sub-pixels is electrically connected to the first scanning signal line of the first row, and the second scanning signal terminal GA2 of the driving circuit in the first row of sub-pixels is electrically connected to the first scanning signal line of the first row.
  • the first scan signal terminal GA1 of the driver circuit in the second row of sub-pixels is electrically connected to the first scan signal line of the second row
  • the second scan signal terminal GA2 of the driver circuit in the second row of sub-pixels is electrically connected to the second row of sub-pixels.
  • the second scanning signal line is electrically connected
  • the first light-emitting control signal terminal EM1 of the driving circuit in the sub-pixels in the second row is electrically connected with the first light-emitting control signal line in the second row
  • the first light-emitting control signal terminal EM1 of the driving circuit in the sub-pixels in the second row is electrically connected.
  • the two light-emitting control signal terminals EM2 are electrically connected to the second light-emitting control signal lines of the second row.
  • the first scanning signal terminal GA1 of the driving circuit in the sub-pixel in the Qth row is electrically connected to the first scanning signal line in the Qth row
  • the second scanning signal of the driving circuit in the sub-pixel in the Qth row is electrically connected
  • the signal terminal GA2 is electrically connected to the second scanning signal line in the Qth row
  • the first light-emitting control signal terminal EM1 of the driver circuit in the sub-pixel in the Qth row is electrically connected to the first light-emitting control signal line in the Qth row.
  • the second light-emitting control signal terminal EM2 of the driving circuit in the sub-pixel is electrically connected to the second light-emitting control signal line in the Qth row.
  • Q represents the total number of rows of sub-pixels in the display area, 1 ⁇ N ⁇ Q, and both N and Q are integers.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a mobile phone such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.
  • the first control circuit 10 can respectively provide the initialization signal to the first scanning signal of the Nth row and the first light-emitting control signal of the Nth row by the first control circuit 10 .
  • the gate of the driving transistor M0 and the first electrode of the light emitting device L are initialized to simultaneously initialize the gate of the driving transistor M0 and the first electrode of the light emitting device L.
  • the data writing circuit 20 in response to the second scan signal of the Nth row, the data signal can be provided to the driving transistor M0, so that the driving transistor M0 can generate a driving current according to the data signal, so that the light-emitting device L can be controlled by the driving current Glow down.

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Abstract

一种驱动电路、其驱动方法及显示装置，包括：发光器件(L)，被配置为在驱动电流(Ids)的控制下发光；驱动晶体管(M0)，被配置为根据数据信号生成驱动电流(Ids)；第一控制电路(10)，被配置为响应于第N行的第一扫描信号(ga1-N)与第N行的第一发光控制信号(em1-N)，将初始化信号分别提供给驱动晶体管(M0)的栅极和发光器件(L)的第一电极；数据写入电路(20)，被配置为响应于第N行的第二扫描信号(ga2-N)，将数据信号提供给驱动晶体管(M0)。

Description

驱动电路、其驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及驱动电路、其驱动方法及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。一般电致发光显示装置中采用驱动电路来驱动电致发光二极管发光。然而，由于制程的限制，使得电致发光二极管亮度调节范围受限。
发明内容
本公开实施例提供的一种驱动电路，其中，包括：
发光器件，被配置为在驱动电流的控制下发光；
驱动晶体管，被配置为根据数据信号生成所述驱动电流；
第一控制电路，被配置为响应于第N行的第一扫描信号与所述第N行的第一发光控制信号，将初始化信号分别提供给所述驱动晶体管的栅极和发光器件的第一电极；N为整数；
数据写入电路，被配置为响应于所述第N行的第二扫描信号，将所述数据信号提供给所述驱动晶体管。
在一些示例中，所述第一控制电路包括：
第一子控制电路，分别与所述第N行的第一扫描信号端、所述第N行的第一发光控制信号端，所述初始化信号端以及所述驱动晶体管的栅极电连接，且所述第一子控制电路被配置为响应于所述第N行的第一扫描信号端的第一扫描信号与所述第N行的第一发光控制信号端的第一发光控制信号，将所述 初始化信号端加载的所述初始化信号提供给所述驱动晶体管的栅极；
第二子控制电路，分别与所述第N行的第一扫描信号端、所述驱动晶体管的栅极以及第二极电连接，且所述第二子控制电路被配置为响应于所述第N行的第一扫描信号端的第一扫描信号，将所述驱动晶体管的栅极与其第二极导通；
第三子控制电路，分别与所述第N行的第一发光控制信号端、所述驱动晶体管的第二极以及所述发光器件的第一电极电连接，且所述第三子控制电路被配置为响应于所述第N行的第一发光控制信号端的第一发光控制信号，将所述驱动晶体管的第二极与所述发光器件的第一电极导通。
在一些示例中，所述第一子控制电路包括：第一晶体管和第二晶体管；
所述第一晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第一晶体管的第一极与所述初始化信号端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
所述第二晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第二晶体管的第二极与所述驱动晶体管的栅极电连接。
在一些示例中，所述第二子控制电路包括第三晶体管；
所述第三晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第三晶体管的第一极与所述驱动晶体管的栅极电连接，所述第三晶体管的第二极与所述驱动晶体管的第二极电连接。
在一些示例中，所述第三子控制电路包括第四晶体管；
所述第四晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第四晶体管的第一极与所述驱动晶体管的第二极电连接，所述第四晶体管的第二极与所述发光器件的第一电极电连接。
在一些示例中，所述数据写入电路包括第五晶体管；
所述第五晶体管的栅极与所述第N行的第二扫描信号电连接，所述第五晶体管的第一极与加载所述数据信号的数据信号端电连接。
在一些示例中，所述驱动电路还包括：第二控制电路，被配置为响应于 所述第N行的第二发光控制信号，将第一电源端与所述驱动晶体管导通。
在一些示例中，所述第二控制电路包括第六晶体管；
所述第六晶体管的栅极与加载所述第二发光控制信号的所述第N行的第二发光控制信号端电连接，所述第六晶体管的第一极与所述第一电源端电连接，所述第六晶体管的第二极与所述驱动晶体管的第一极电连接。
在一些示例中，所述驱动电路还包括存储电容；
所述存储电容的第一电极板与所述驱动晶体管的栅极电连接，所述存储电容的第二电极板与第一电源端电连接。
本公开实施例提供的驱动电路，其中，包括：驱动晶体管、第一晶体管至第六晶体管、存储电容；
所述第一晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第一晶体管的第一极与所述初始化信号端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
所述第二晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第二晶体管的第二极与所述驱动晶体管的栅极电连接；
所述第三晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第三晶体管的第一极与所述驱动晶体管的栅极电连接，所述第三晶体管的第二极与所述驱动晶体管的第二极电连接；
所述第四晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第四晶体管的第一极与所述驱动晶体管的第二极电连接，所述第四晶体管的第二极与所述发光器件的第一电极电连接；
所述第五晶体管的栅极与所述第N行的第二扫描信号电连接，所述第五晶体管的第一极与加载所述数据信号的数据信号端电连接；
所述第六晶体管的栅极与加载所述第二发光控制信号的所述第N行的第二发光控制信号端电连接，所述第六晶体管的第一极与所述第一电源端电连接，所述第六晶体管的第二极与所述驱动晶体管的第一极电连接；
所述存储电容的第一电极板与所述驱动晶体管的栅极电连接，所述存储 电容的第二电极板与第一电源端电连接。
本公开实施例提供的显示装置，包括上述驱动电路。
本公开实施例提供的驱动电路的驱动方法，包括：
初始化阶段，控制所述第N行的第一扫描信号的电平为第一电平，所述第N行的第二扫描信号的电平为第二电平，以及所述第N行的第一发光控制信号的电平为第一电平，使所述第一控制电路将初始化信号分别提供给所述驱动晶体管的栅极和发光器件的第一电极；
数据写入阶段，控制所述第N行的第一扫描信号的电平为第一电平，所述第N行的第二扫描信号的电平为第一电平，以及所述第N行的第一发光控制信号的电平为第二电平，使所述数据写入电路将所述数据信号提供给所述驱动晶体管；
发光阶段，控制所述第N行的第一扫描信号的电平为第二电平，所述第N行的第二扫描信号的电平为第二电平，以及所述第N行的第一发光控制信号的电平为第一电平，使所述驱动晶体管根据数据信号生成驱动电流，所述发光器件在所述驱动电流的控制下发光。
在一些示例中，在所述驱动电路还包括第二控制电路时，所述驱动方法还包括：
在所述初始化阶段，控制所述第N行的第二发光控制信号的电平为第二电平；
在所述数据写入阶段，控制所述第N行的第二发光控制信号的电平为第二电平；
在所述发光阶段，控制所述第N行的第二发光控制信号的电平为第一电平。
在一些示例中，在所述数据写入阶段之后，在所述发光阶段之前，还包括：
第一缓冲阶段，控制所述第N行的第一扫描信号的电平为第二电平，所述第N行的第二扫描信号的电平为第一电平，以及所述第N行的第一发光控 制信号的电平为第二电平。
在一些示例中，在所述驱动电路还包括第二控制电路时，所述第一缓冲阶段还包括：控制所述第N行的第二发光控制信号的电平为第二电平。
在一些示例中，在所述第一缓冲阶段之后，在所述发光阶段之前，还包括：
第二缓冲阶段，控制所述第N行的第一扫描信号的电平为第二电平，所述第N行的第二扫描信号的电平为第二电平，以及所述第N行的第一发光控制信号的电平为第二电平。
在一些示例中，在所述驱动电路还包括第二控制电路时，所述第二缓冲阶段还包括：控制所述第N行的第二发光控制信号的电平为第一电平。
附图说明
图1为本公开实施例提供的驱动电路的一些具体结构示意图；
图2为本公开实施例提供的驱动电路的一些电路时序图；
图3为本公开实施例提供的驱动电路的又一些电路时序图；
图4为本公开实施例提供的驱动电路的又一些电路时序图；
图5为本公开实施例提供的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第 二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供一种驱动电路，如图1所示，可以包括：
发光器件L，被配置为在驱动电流的控制下发光；
驱动晶体管M0，被配置为根据数据信号生成驱动电流；
第一控制电路10，被配置为响应于第N行的第一扫描信号与第N行的第一发光控制信号，将初始化信号分别提供给驱动晶体管M0的栅极和发光器件L的第一电极；
数据写入电路20，被配置为响应于第N行的第二扫描信号，将数据信号提供给驱动晶体管M0。
本公开实施例提供的上述驱动电路，通过第一控制电路10响应于第N行的第一扫描信号与第N行的第一发光控制信号，可以将初始化信号分别提供给驱动晶体管M0的栅极和发光器件L的第一电极，以同时对驱动晶体管M0的栅极和发光器件L的第一电极进行初始化。通过数据写入电路20响应于第N行的第二扫描信号，可以将数据信号提供给驱动晶体管M0，以使驱动晶体管M0可以根据数据信号生成驱动电流，从而使发光器件L在驱动电流的控制下发光。
在一些示例中，在具体实施时，如图1所示，第一控制电路10可以包括：第一子控制电路11，第二子控制电路12以及第三子控制电路13；
第一子控制电路11分别与第N行的第一扫描信号端GA1、第N行的第一发光控制信号端EM1，初始化信号端以及驱动晶体管M0的栅极电连接， 且第一子控制电路11被配置为响应于第N行的第一扫描信号端GA1的第一扫描信号与第N行的第一发光控制信号端EM1的第一发光控制信号，将初始化信号端加载的初始化信号提供给驱动晶体管M0的栅极；
第二子控制电路12分别与第N行的第一扫描信号端GA1、驱动晶体管M0的栅极以及第二极电连接，且第二子控制电路12被配置为响应于第N行的第一扫描信号端GA1的第一扫描信号，将驱动晶体管M0的栅极与其第二极导通；
第三子控制电路13分别与第N行的第一发光控制信号端EM1、驱动晶体管M0的第二极以及发光器件L的第一电极电连接，且第三子控制电路13被配置为响应于第N行的第一发光控制信号端EM1的第一发光控制信号，将驱动晶体管M0的第二极与发光器件L的第一电极导通。
示例性地，通过第一子控制电路11响应于第N行的第一扫描信号端GA1的第一扫描信号与第N行的第一发光控制信号端EM1的第一发光控制信号，可以将初始化信号端加载的初始化信号提供给驱动晶体管M0的栅极，以对驱动晶体管M0的栅极进行初始化。并且，由于第二子控制电路12响应于第N行的第一扫描信号端GA1的第一扫描信号，将驱动晶体管M0的栅极与其第二极导通；以及第三子控制电路13响应于第N行的第一发光控制信号端EM1的第一发光控制信号，将驱动晶体管M0的第二极与发光器件L的第一电极导通，从而可以将输入到驱动晶体管M0的栅极的初始化信号通过第二子控制电路12和第三子控制电路13输入到发光器件L的第一电极，以同时对发光器件L的第一电极进行初始化。
在具体实施时，在本公开实施例中，如图1所示，驱动电路还可以包括：第二控制电路30，被配置为响应于第N行的第二发光控制信号，将第一电源端VDD与驱动晶体管M0导通。
在具体实施时，在本公开实施例中，发光器件L的第一电极与第三子控制电路13电连接，发光器件L的第二电极与第二电源端VSS电连接。其中，发光器件L的第一电极可以为其正极，第二电极可以为其负极。示例性地， 发光器件L可以设置为电致发光二极管，例如，发光器件L可以包括：微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机电致发光二极管(Organic Light Emitting Diode，OLED)以及量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。另外，一般发光器件L具有发光阈值电压，在发光器件L两端的电压大于或等于发光阈值电压时进行发光。在实际应用中，可以根据实际应用环境来设计确定发光器件L的具体结构，在此不作限定。
在具体实施时，在本公开实施例中，如图1所示，第一子控制电路11可以包括：第一晶体管M1和第二晶体管M2；
第一晶体管M1的栅极与第N行的第一扫描信号端GA1电连接，第一晶体管M1的第一极与初始化信号端电连接，第一晶体管M1的第二极与第二晶体管M2的第一极电连接；
第二晶体管M2的栅极与第N行的第一发光控制信号端EM1电连接，第二晶体管M2的第二极与驱动晶体管M0的栅极电连接。
在具体实施时，在本公开实施例中，如图1所示，第二子控制电路12可以包括第三晶体管M3；
第三晶体管M3的栅极与第N行的第一扫描信号端GA1电连接，第三晶体管M3的第一极与驱动晶体管M0的栅极电连接，第三晶体管M3的第二极与驱动晶体管M0的第二极电连接。
在具体实施时，在本公开实施例中，如图1所示，第三子控制电路13可以包括第四晶体管M4；
第四晶体管M4的栅极与第N行的第一发光控制信号端EM1电连接，第四晶体管M4的第一极与驱动晶体管M0的第二极电连接，第四晶体管M4的第二极与发光器件L的第一电极电连接。
在具体实施时，在本公开实施例中，如图1所示，数据写入电路20可以包括第五晶体管M5；
第五晶体管M5的栅极与第N行的第二扫描信号端GA2电连接，第五晶 体管M5的第一极与加载数据信号的数据信号端DA电连接。
在具体实施时，在本公开实施例中，如图1所示，第二控制电路30可以包括第六晶体管M6；
第六晶体管M6的栅极与加载第二发光控制信号的第N行的第二发光控制信号端EM2电连接，第六晶体管M6的第一极与第一电源端VDD电连接，第六晶体管M6的第二极与驱动晶体管M0的第一极电连接。
在具体实施时，在本公开实施例中，如图1所示，驱动电路还可以包括存储电容CST；
存储电容CST的第一电极板与驱动晶体管M0的栅极电连接，存储电容CST的第二电极板与第一电源端VDD电连接。
在具体实施时，在本公开实施例中，如图1所示，驱动晶体管M0可以为P型晶体管；其中，驱动晶体管M0的第一极为其源极，驱动晶体管M0的第二极为其漏极，并且该驱动晶体管M0处于饱和状态时，电流由驱动晶体管M0的源极流向其漏极。
当然，在具体实施时，在本公开实施例中，驱动晶体管M0也可以为N型晶体管；其中，驱动晶体管M0的第一极为其漏极，驱动晶体管M0的第二极为其源极，并且该驱动晶体管M0处于饱和状态时，电流由驱动晶体管M0的漏极流向其源极。
以上仅是举例说明本公开实施例提供的驱动电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内，具体在此不作限定。
可选地，为了降低制备工艺，在具体实施时，在本公开实施例中，如图1所示，第一至第六晶体管M1～M6可以均为P型晶体管。当然，第一至第六晶体管M1～M6也可以均为N型晶体管，这也可以根据实际应用环境来设计确定，在此不作限定。
进一步的，在具体实施时，在本公开实施例中，P型晶体管在高电平信号 作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
需要说明的是，本公开上述实施例中提到的晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Scmiconductor，MOS)，在此不作限定。
在具体实施中，可以根据晶体管的类型以及其栅极的信号，将晶体管的第一极作为其源极，第二极作为其漏极；或者，反之，将晶体管的第一极作为其漏极，第二极作为其源极，这可以根据实际应用环境来设计确定，具体在此不做具体区分。
在具体实施时，在本公开实施例中，第一电源端的电压Vdd一般为正值，第二电源端的电压Vss一般接地或为负值。在实际应用中，第一电源端的电压Vdd和第二电源端的电压Vss的具体数值可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，初始化信号的电压Vinit与第二电源端的电压Vss可以满足如下公式：Vinit-Vss<VL。VL代表发光器件L的发光阈值电压。
本公开实施例还提供了上述驱动电路的驱动方法，如图5所示，可以包括如下步骤：
S10、初始化阶段，控制第N行的第一扫描信号的电平为第一电平，第N行的第二扫描信号的电平为第二电平，以及第N行的第一发光控制信号的电平为第一电平，使第一控制电路将初始化信号分别提供给驱动晶体管的栅极和发光器件的第一电极；
S20、数据写入阶段，控制第N行的第一扫描信号的电平为第一电平，第N行的第二扫描信号的电平为第一电平，以及第N行的第一发光控制信号的电平为第二电平，使数据写入电路将数据信号提供给驱动晶体管；
S30、发光阶段，控制第N行的第一扫描信号的电平为第二电平，第N行的第二扫描信号的电平为第二电平，以及第N行的第一发光控制信号的电 平为第一电平，使驱动晶体管根据数据信号生成驱动电流，发光器件在驱动电流的控制下发光。
本公开实施例提供的上述驱动方法，在初始化阶段，通过第一控制电路响应于第N行的第一扫描信号与第N行的第一发光控制信号，可以将初始化信号分别提供给驱动晶体管的栅极和发光器件的第一电极，以同时对驱动晶体管的栅极和发光器件的第一电极进行初始化。在数据写入阶段，通过数据写入电路响应于第N行的第二扫描信号，可以将数据信号提供给驱动晶体管，以在发光阶段使驱动晶体管可以根据数据信号生成驱动电流，从而使发光器件在驱动电流的控制下发光。
在具体实施时，在本公开实施例中，在驱动电路还包括第二控制电路30时，驱动方法还可以包括：在初始化阶段，控制第N行的第二发光控制信号的电平为第二电平；在数据写入阶段，控制第N行的第二发光控制信号的电平为第二电平；在发光阶段，控制第N行的第二发光控制信号的电平为第一电平。
下面以图1所示的驱动电路为例，结合图2所示的电路时序图，对本公开实施例提供的上述驱动电路的工作过程作以描述。如图2所示，ga1-N代表第N行的第一扫描信号，ga2-N代表第N行的第二扫描信号，em1-N代表第N行的第一发光控制信号，em2-N代表第N行的第二发光控制信号。并且，一个驱动电路在一个显示帧中的工作过程，可以包括：初始化阶段T1、数据写入阶段T2、发光阶段T3。
在初始化阶段T1，第一晶体管M1在信号ga1-N的低电平的控制下导通，且第二晶体管M2在信号em1-N的低电平的控制下也导通，这样使得初始化信号端VINIT的初始化信号可以通过导通的第一晶体管M1和第二晶体管M2提供给驱动晶体管M0的栅极N3，从而使驱动晶体管M0的栅极N3的电压为Vinit，进而对驱动晶体管M0的栅极N3进行初始化。并且，第三晶体管M3在信号ga1-N的低电平的控制下导通，且第四晶体管M4在信号em1-N的低电平的控制下也导通，这样使得初始化信号端VINIT的初始化信号可以通 过导通的第三晶体管M3和第四晶体管M4提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。以及，第六晶体管M6在信号em2-N的高电平的控制下截止。第五晶体管M5在信号ga2-N的高电平的控制下截止。
在数据写入阶段T2，第五晶体管M5在信号ga2-N的低电平的控制下导通，以将数据信号端DA的数据信号提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压为数据信号的电压Vda。并且，第三晶体管M3在信号ga1-N的低电平的控制下导通，可以使驱动晶体管M0形成二极管连接方式，从而使驱动晶体管M0的第一极N1的电压Vda对驱动晶体管M0的栅极N3进行充电并通过存储电容CST进行存储。以及，第二晶体管M2和第四晶体管M4在信号em1-N的高电平的控制下截止，第六晶体管M6在信号em2-N的高电平的控制下截止。
在发光阶段T3，第六晶体管M6在信号em2-N的低电平的控制下导通，导通的第六晶体管M6可以将第一电源端VDD的电压Vdd提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压为Vdd。这样可以使驱动晶体管M0处于饱和状态，从而使驱动晶体管M0产生驱动电流Ids：Ids＝K(Vda-Vdd) 2。并且，第四晶体管M4在信号em1-N的低电平的控制下导通，导通的第四晶体管M4可以将驱动晶体管M0的第二极N2与发光器件L的第一电极导通，从而使驱动电流Ids流入发光器件L，以驱动发光器件L发光。其中，K为与工艺和设计有关的结构常数。并且，第一晶体管M1和第三晶体管M3在信号ga1-N的高电平的控制下截止。第五晶体管M5在信号ga2-N的高电平的控制下截止。
在又一些示例中，在本公开实施例中，在数据写入阶段之后，在发光阶段之前，还可以包括：第一缓冲阶段。在第一缓冲阶段中，控制第N行的第一扫描信号的电平为第二电平，第N行的第二扫描信号的电平为第一电平，以及第N行的第一发光控制信号的电平为第二电平。
并且，在本公开实施例中，在驱动电路还包括第二控制电路30时，第一缓冲阶段还可以包括：控制第N行的第二发光控制信号的电平为第二电平。
下面以图1所示的驱动电路为例，结合图3所示的电路时序图，对本公开实施例提供的上述驱动电路的工作过程作以描述。如图3所示，ga1-N代表第N行的第一扫描信号，ga2-N代表第N行的第二扫描信号，em1-N代表第N行的第一发光控制信号，em2-N代表第N行的第二发光控制信号。并且，一个驱动电路在一个显示帧中的工作过程，可以包括：初始化阶段T1、数据写入阶段T2、第一缓冲阶段T4、发光阶段T3。
在初始化阶段T1，第一晶体管M1在信号ga1-N的低电平的控制下导通，且第二晶体管M2在信号em1-N的低电平的控制下也导通，这样使得初始化信号端VINIT的初始化信号可以通过导通的第一晶体管M1和第二晶体管M2提供给驱动晶体管M0的栅极N3，从而使驱动晶体管M0的栅极N3的电压为Vinit，进而对驱动晶体管M0的栅极N3进行初始化。并且，第三晶体管M3在信号ga1-N的低电平的控制下导通，且第四晶体管M4在信号em1-N的低电平的控制下也导通，这样使得初始化信号端VINIT的初始化信号可以通过导通的第三晶体管M3和第四晶体管M4提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。以及，第六晶体管M6在信号em2-N的高电平的控制下截止。第五晶体管M5在信号ga2-N的高电平的控制下截止。
在数据写入阶段T2，第五晶体管M5在信号ga2-N的低电平的控制下导通，以将数据信号端DA的数据信号提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压为数据信号的电压Vda。并且，第三晶体管M3在信号ga1-N的低电平的控制下导通，可以使驱动晶体管M0形成二极管连接方式，从而使驱动晶体管M0的第一极N1的电压Vda对驱动晶体管M0的栅极N3进行充电并通过存储电容CST进行存储。以及，第二晶体管M2和第四晶体管M4在信号em1-N的高电平的控制下截止，第六晶体管M6在信号em2-N的高电平的控制下截止。
在第一缓冲阶段T4，第五晶体管M5在信号ga2-N的低电平的控制下导通，以将数据信号端DA的数据信号提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压继续为数据信号的电压Vda。并且，第 一晶体管M1和第三晶体管M3在信号ga1-N的高电平的控制下截止。第二晶体管M2和第四晶体管M4在信号em1-N的高电平的控制下截止。第六晶体管M6在信号em2-N的高电平的控制下截止。
在发光阶段T3，第六晶体管M6在信号em2-N的低电平的控制下导通，导通的第六晶体管M6可以将第一电源端VDD的电压Vdd提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压为Vdd。这样可以使驱动晶体管M0处于饱和状态，从而使驱动晶体管M0产生驱动电流Ids：Ids＝K(Vda-Vdd) 2。并且，第四晶体管M4在信号em1-N的低电平的控制下导通，导通的第四晶体管M4可以将驱动晶体管M0的第二极N2与发光器件L的第一电极导通，从而使驱动电流Ids流入发光器件L，以驱动发光器件L发光。其中，K为与工艺和设计有关的结构常数。并且，第一晶体管M1和第三晶体管M3在信号ga1-N的高电平的控制下截止。第五晶体管M5在信号ga2-N的高电平的控制下截止。
在又一些示例中，在本公开实施例中，在第一缓冲阶段之后，在发光阶段之前，还包括：第二缓冲阶段。在第二缓冲阶段中，控制第N行的第一扫描信号的电平为第二电平，第N行的第二扫描信号的电平为第二电平，以及第N行的第一发光控制信号的电平为第二电平。
并且，在本公开实施例中，在驱动电路还包括第二控制电路30时，第二缓冲阶段还包括：控制第N行的第二发光控制信号的电平为第一电平。
下面以图1所示的驱动电路为例，结合图4所示的电路时序图，对本公开实施例提供的上述驱动电路的工作过程作以描述。如图4所示，ga1-N代表第N行的第一扫描信号，ga2-N代表第N行的第二扫描信号，em1-N代表第N行的第一发光控制信号，em2-N代表第N行的第二发光控制信号。并且，一个驱动电路在一个显示帧中的工作过程，可以包括：初始化阶段T1、数据写入阶段T2、第一缓冲阶段T4、第二缓冲阶段T5、发光阶段T3。
在初始化阶段T1，第一晶体管M1在信号ga1-N的低电平的控制下导通，且第二晶体管M2在信号em1-N的低电平的控制下也导通，这样使得初始化 信号端VINIT的初始化信号可以通过导通的第一晶体管M1和第二晶体管M2提供给驱动晶体管M0的栅极N3，从而使驱动晶体管M0的栅极N3的电压为Vinit，进而对驱动晶体管M0的栅极N3进行初始化。并且，第三晶体管M3在信号ga1-N的低电平的控制下导通，且第四晶体管M4在信号em1-N的低电平的控制下也导通，这样使得初始化信号端VINIT的初始化信号可以通过导通的第三晶体管M3和第四晶体管M4提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。以及，第六晶体管M6在信号em2-N的高电平的控制下截止。第五晶体管M5在信号ga2-N的高电平的控制下截止。
在数据写入阶段T2，第五晶体管M5在信号ga2-N的低电平的控制下导通，以将数据信号端DA的数据信号提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压为数据信号的电压Vda。并且，第三晶体管M3在信号ga1-N的低电平的控制下导通，可以使驱动晶体管M0形成二极管连接方式，从而使驱动晶体管M0的第一极N1的电压Vda对驱动晶体管M0的栅极N3进行充电并通过存储电容CST进行存储。以及，第二晶体管M2和第四晶体管M4在信号em1-N的高电平的控制下截止，第六晶体管M6在信号em2-N的高电平的控制下截止。
在第一缓冲阶段T4，第五晶体管M5在信号ga2-N的低电平的控制下导通，以将数据信号端DA的数据信号提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压继续为数据信号的电压Vda。并且，第一晶体管M1和第三晶体管M3在信号ga1-N的高电平的控制下截止。第二晶体管M2和第四晶体管M4在信号em1-N的高电平的控制下截止。第六晶体管M6在信号em2-N的高电平的控制下截止。
在第二缓冲阶段T5，第六晶体管M6在信号em2-N的高电平的控制下导通。导通的第六晶体管M6可以将第一电源端VDD的电压Vdd提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压为Vdd。这样可以通过第一电源端VDD对驱动晶体管M0的第一极N1进行预充电。并且，第一晶体管M1和第三晶体管M3在信号ga1-N的高电平的控制下截止。 第二晶体管M2和第四晶体管M4在信号em1-N的高电平的控制下截止。第五晶体管M5在信号ga2-N的高电平的控制下截止。
在发光阶段T3，第六晶体管M6在信号em2-N的低电平的控制下导通，导通的第六晶体管M6可以将第一电源端VDD的电压Vdd提供给驱动晶体管M0的第一极N1，以使驱动晶体管M0的第一极N1的电压为Vdd。这样可以使驱动晶体管M0处于饱和状态，从而使驱动晶体管M0产生驱动电流Ids：Ids＝K(Vda-Vdd) 2。并且，第四晶体管M4在信号em1-N的低电平的控制下导通，导通的第四晶体管M4可以将驱动晶体管M0的第二极N2与发光器件L的第一电极导通，从而使驱动电流Ids流入发光器件L，以驱动发光器件L发光。其中，K为与工艺和设计有关的结构常数。并且，第一晶体管M1和第三晶体管M3在信号ga1-N的高电平的控制下截止。第五晶体管M5在信号ga2-N的高电平的控制下截止。
需要说明的是，通过在第一缓冲阶段T4中使第N行的第二扫描信号ga2-N为低电平，可以使第五晶体管M5继续打开，以使充电更充分。
需要说明的是，通过在第二缓冲阶段T5中使第N行的第一发光控制信号em1-N为高电平，可以控制第四晶体管M4截止，这样可以使驱动晶体管的栅极的电压进一步稳定后，即使驱动晶体管产生的电流进一步稳定后再提供给发光器件，从而可以进一步提高发光器件的发光稳定性。
需要说明的是，通过设置第一缓冲阶段T4和第二缓冲阶段T5，可以采用相关技术中的栅极驱动电路向第一扫描信号线和第二扫描信号线提供信号，以及采用相关技术中的发光控制电路向第一发光控制信号线和第二发光控制信号线提供信号。当然，也可以不设置第一缓冲阶段T4和第二缓冲阶段T5，这样可以通过重新设计栅极驱动电路和发光控制电路的结构，以使其满足图2所示的信号时序。
基于同一公开构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述驱动电路。该显示装置解决问题的原理与前述驱动电路相似，因此该显示装置的实施可以参见前述驱动电路的实施，重复之处在此不再赘 述。
在具体实施时，在本公开实施例中，显示装置可以包括显示区，显示区包括Q行信号线组和Y列数据线，Q行信号线组和Y列数据线交叉设置。其中，各行信号线组包括一条第一扫描信号线，一条第二扫描信号线，一条第一发光控制信号线、以及一条第二发光控制信号线。并且，Q行信号线组沿数据线的延伸方向依次排列。
示例性地，可以使1≤N≤Q，且N、Q以及Y均为整数。例如，第N行信号线组中的第一扫描信号线可以为第N行的第一扫描信号线，则第N行的第一扫描信号为第N行的第一扫描信号线上传输的信号，即第N行的第一扫描信号端与第N行的第一扫描信号线电连接。
第N行信号线组中的第二扫描信号线可以为第N行的第二扫描信号线，则第N行的第二扫描信号为第N行的第二扫描信号线上传输的信号，即第N行的第二扫描信号端与第N行的第二扫描信号线电连接。
第N行信号线组中的第一发光控制信号线可以为第N行的第一发光控制信号线，则第N行的第一发光控制信号为第N行的第一发光控制信号线上传输的信号，即第N行的第一发光控制信号端与第N行的第一发光控制信号线电连接。
第N行信号线组中的第二发光控制信号线可以为第N行的第二发光控制信号线，则第N行的第二发光控制信号为第N行的第二发光控制信号线上传输的信号，即第N行的第二发光控制信号端与第N行的第二发光控制信号线电连接。
并且，数据线用于传输数据信号。数据信号端与数据线电连接，以使数据信号端加载数据信号。
示例性地，显示区还可以包括Q行Y列的驱动电路。并且，一行驱动电路可以对应一行信号线组。即一行驱动电路对应一条第一扫描信号线，一条第二扫描信号线，一条第一发光控制信号线、以及一条第二发光控制信号线。则第N行的驱动电路的第一扫描信号端与第N行的第一扫描信号线电连接。 第N行的驱动电路的第二扫描信号端与第N行的第二扫描信号线电连接。第N行的驱动电路的第一发光控制信号端与第N行的第一发光控制信号线电连接。第N行的驱动电路的第二发光控制信号端与第N行的第二发光控制信号线电连接。
这样可以使本行的第一扫描信号线向本行的驱动电路提供第一扫描信号，从而可以使第N行的第一扫描信号和第N-1行或第N+1行的第一扫描信号采用相互独立的信号线进行传输，降低第一扫描信号的延迟和干扰。
并且，这样可以使本行的第二扫描信号线向本行的驱动电路提供第二扫描信号，从而可以使第N行的第二扫描信号和第N-1行或第N+1行的第二扫描信号采用相互独立的信号线进行传输，降低第二扫描信号的延迟和干扰。
并且，这样可以使本行的第一发光控制信号线向本行的驱动电路提供第一发光控制信号，从而可以使第N行的第一发光控制信号和第N-1行或第N+1行的第一发光控制信号采用相互独立的信号线进行传输，降低第一发光控制信号的延迟和干扰。
并且，这样可以使本行的第二发光控制信号线向本行的驱动电路提供第二发光控制信号，从而可以使第N行的第二发光控制信号和第N-1行或第N+1行的第二发光控制信号采用相互独立的信号线进行传输，降低第二发光控制信号的延迟和干扰。
示例性地，显示区包括阵列排布的多个像素单元。每个像素单元包括多个子像素。示例性地，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，每一个子像素可以包括上述驱动电路，这样可以使子像素实现电致发光显示。
在具体实施时，在本公开实施例中，一列子像素可以对应一条数据线， 则该列中的驱动电路的数据信号端与对应该条数据线电连接。一行子像素可以对应一行信号线组，则一行子像素可以对应一条第一扫描信号线，一条第二扫描信号线，一条第一发光控制信号线、以及一条第二发光控制信号线。也就是说，第一行子像素中的驱动电路的第一扫描信号端GA1与第一行的第一扫描信号线电连接，第一行子像素中的驱动电路的第二扫描信号端GA2与第一行的第二扫描信号线电连接，第一行子像素中的驱动电路的第一发光控制信号端EM1与第一行的第一发光控制信号线电连接，第一行子像素中的驱动电路的第二发光控制信号端EM2与第一行的第二发光控制信号线电连接。
第二行子像素中的驱动电路的第一扫描信号端GA1与第二行的第一扫描信号线电连接，第二行子像素中的驱动电路的第二扫描信号端GA2与第二行的第二扫描信号线电连接，第二行子像素中的驱动电路的第一发光控制信号端EM1与第二行的第一发光控制信号线电连接，第二行子像素中的驱动电路的第二发光控制信号端EM2与第二行的第二发光控制信号线电连接。
其余同理，以此类推，第Q行子像素中的驱动电路的第一扫描信号端GA1与第Q行的第一扫描信号线电连接，第Q行子像素中的驱动电路的第二扫描信号端GA2与第Q行的第二扫描信号线电连接，第Q行子像素中的驱动电路的第一发光控制信号端EM1与第Q行的第一发光控制信号线电连接，第Q行子像素中的驱动电路的第二发光控制信号端EM2与第Q行的第二发光控制信号线电连接。其中，Q代表显示区中子像素的总行数，可以使1≤N≤Q，且N和Q均为整数。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的驱动电路、其驱动方法及显示装置，通过第一控制电路10响应于第N行的第一扫描信号与第N行的第一发光控制信号，可以将初始化信号分别提供给驱动晶体管M0的栅极和发光器件L的第一电极， 以同时对驱动晶体管M0的栅极和发光器件L的第一电极进行初始化。通过数据写入电路20响应于第N行的第二扫描信号，可以将数据信号提供给驱动晶体管M0，以使驱动晶体管M0可以根据数据信号生成驱动电流，从而使发光器件L在驱动电流的控制下发光。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种驱动电路，其中，包括：
    发光器件，被配置为在驱动电流的控制下发光；
    驱动晶体管，被配置为根据数据信号生成所述驱动电流；
    第一控制电路，被配置为响应于第N行的第一扫描信号与所述第N行的第一发光控制信号，将初始化信号分别提供给所述驱动晶体管的栅极和发光器件的第一电极；N为整数；
    数据写入电路，被配置为响应于所述第N行的第二扫描信号，将所述数据信号提供给所述驱动晶体管。
  2. 如权利要求1所述的驱动电路，其中，所述第一控制电路包括：
    第一子控制电路，分别与所述第N行的第一扫描信号端、所述第N行的第一发光控制信号端，所述初始化信号端以及所述驱动晶体管的栅极电连接，且所述第一子控制电路被配置为响应于所述第N行的第一扫描信号端的第一扫描信号与所述第N行的第一发光控制信号端的第一发光控制信号，将所述初始化信号端加载的所述初始化信号提供给所述驱动晶体管的栅极；
    第二子控制电路，分别与所述第N行的第一扫描信号端、所述驱动晶体管的栅极以及第二极电连接，且所述第二子控制电路被配置为响应于所述第N行的第一扫描信号端的第一扫描信号，将所述驱动晶体管的栅极与其第二极导通；
    第三子控制电路，分别与所述第N行的第一发光控制信号端、所述驱动晶体管的第二极以及所述发光器件的第一电极电连接，且所述第三子控制电路被配置为响应于所述第N行的第一发光控制信号端的第一发光控制信号，将所述驱动晶体管的第二极与所述发光器件的第一电极导通。
  3. 如权利要求2所述的驱动电路，其中，所述第一子控制电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第 一晶体管的第一极与所述初始化信号端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
    所述第二晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第二晶体管的第二极与所述驱动晶体管的栅极电连接。
  4. 如权利要求2所述的驱动电路，其中，所述第二子控制电路包括第三晶体管；
    所述第三晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第三晶体管的第一极与所述驱动晶体管的栅极电连接，所述第三晶体管的第二极与所述驱动晶体管的第二极电连接。
  5. 如权利要求2所述的驱动电路，其中，所述第三子控制电路包括第四晶体管；
    所述第四晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第四晶体管的第一极与所述驱动晶体管的第二极电连接，所述第四晶体管的第二极与所述发光器件的第一电极电连接。
  6. 如权利要求1-5任一项所述的驱动电路，其中，所述数据写入电路包括第五晶体管；
    所述第五晶体管的栅极与所述第N行的第二扫描信号电连接，所述第五晶体管的第一极与加载所述数据信号的数据信号端电连接。
  7. 如权利要求1-6任一项所述的驱动电路，其中，所述驱动电路还包括：第二控制电路，被配置为响应于所述第N行的第二发光控制信号，将第一电源端与所述驱动晶体管导通。
  8. 如权利要求7所述的驱动电路，其中，所述第二控制电路包括第六晶体管；
    所述第六晶体管的栅极与加载所述第二发光控制信号的所述第N行的第二发光控制信号端电连接，所述第六晶体管的第一极与所述第一电源端电连接，所述第六晶体管的第二极与所述驱动晶体管的第一极电连接。
  9. 如权利要求1-8任一项所述的驱动电路，其中，所述驱动电路还包括 存储电容；
    所述存储电容的第一电极板与所述驱动晶体管的栅极电连接，所述存储电容的第二电极板与第一电源端电连接。
  10. 一种驱动电路，其中，包括：驱动晶体管、第一晶体管至第六晶体管、存储电容；
    所述第一晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第一晶体管的第一极与所述初始化信号端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
    所述第二晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第二晶体管的第二极与所述驱动晶体管的栅极电连接；
    所述第三晶体管的栅极与所述第N行的第一扫描信号端电连接，所述第三晶体管的第一极与所述驱动晶体管的栅极电连接，所述第三晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述第四晶体管的栅极与所述第N行的第一发光控制信号端电连接，所述第四晶体管的第一极与所述驱动晶体管的第二极电连接，所述第四晶体管的第二极与所述发光器件的第一电极电连接；
    所述第五晶体管的栅极与所述第N行的第二扫描信号电连接，所述第五晶体管的第一极与加载所述数据信号的数据信号端电连接；
    所述第六晶体管的栅极与加载所述第二发光控制信号的所述第N行的第二发光控制信号端电连接，所述第六晶体管的第一极与所述第一电源端电连接，所述第六晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述存储电容的第一电极板与所述驱动晶体管的栅极电连接，所述存储电容的第二电极板与第一电源端电连接。
  11. 一种显示装置，其中，包括如权利要求1-10任一项所述的驱动电路。
  12. 一种如权利要求1-10任一项所述的驱动电路的驱动方法，其中，包括：
    初始化阶段，控制所述第N行的第一扫描信号的电平为第一电平，所述 第N行的第二扫描信号的电平为第二电平，以及所述第N行的第一发光控制信号的电平为第一电平，使所述第一控制电路将初始化信号分别提供给所述驱动晶体管的栅极和发光器件的第一电极；
    数据写入阶段，控制所述第N行的第一扫描信号的电平为第一电平，所述第N行的第二扫描信号的电平为第一电平，以及所述第N行的第一发光控制信号的电平为第二电平，使所述数据写入电路将所述数据信号提供给所述驱动晶体管；
    发光阶段，控制所述第N行的第一扫描信号的电平为第二电平，所述第N行的第二扫描信号的电平为第二电平，以及所述第N行的第一发光控制信号的电平为第一电平，使所述驱动晶体管根据数据信号生成驱动电流，所述发光器件在所述驱动电流的控制下发光。
  13. 如权利要求12所述的驱动方法，其中，在所述驱动电路还包括第二控制电路时，所述驱动方法还包括：
    在所述初始化阶段，控制所述第N行的第二发光控制信号的电平为第二电平；
    在所述数据写入阶段，控制所述第N行的第二发光控制信号的电平为第二电平；
    在所述发光阶段，控制所述第N行的第二发光控制信号的电平为第一电平。
  14. 如权利要求12所述的驱动方法，其中，在所述数据写入阶段之后，在所述发光阶段之前，还包括：
    第一缓冲阶段，控制所述第N行的第一扫描信号的电平为第二电平，所述第N行的第二扫描信号的电平为第一电平，以及所述第N行的第一发光控制信号的电平为第二电平。
  15. 如权利要求14所述的驱动方法，其中，在所述驱动电路还包括第二控制电路时，所述第一缓冲阶段还包括：控制所述第N行的第二发光控制信号的电平为第二电平。
  16. 如权利要求14所述的驱动方法，其中，在所述第一缓冲阶段之后，在所述发光阶段之前，还包括：
    第二缓冲阶段，控制所述第N行的第一扫描信号的电平为第二电平，所述第N行的第二扫描信号的电平为第二电平，以及所述第N行的第一发光控制信号的电平为第二电平。
  17. 如权利要求16所述的驱动方法，其中，在所述驱动电路还包括第二控制电路时，所述第二缓冲阶段还包括：控制所述第N行的第二发光控制信号的电平为第一电平。
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