WO2022082564A1 - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022082564A1
WO2022082564A1 PCT/CN2020/122695 CN2020122695W WO2022082564A1 WO 2022082564 A1 WO2022082564 A1 WO 2022082564A1 CN 2020122695 W CN2020122695 W CN 2020122695W WO 2022082564 A1 WO2022082564 A1 WO 2022082564A1
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Prior art keywords
electrode
array substrate
sub
line
electrically connected
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PCT/CN2020/122695
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English (en)
French (fr)
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WO2022082564A9 (zh
Inventor
张健
王珍
王德帅
张寒
闫伟
孙建
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/427,622 priority Critical patent/US11921390B2/en
Priority to PCT/CN2020/122695 priority patent/WO2022082564A1/zh
Priority to CN202080002395.2A priority patent/CN114981762A/zh
Publication of WO2022082564A1 publication Critical patent/WO2022082564A1/zh
Publication of WO2022082564A9 publication Critical patent/WO2022082564A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • a display product generally includes a display panel and a driver chip on one side of the display panel.
  • the driver chip is used to provide the display panel with various functional signals required for its display.
  • the function signal needs to go through a long transmission path before it can be transmitted from the side of the display panel close to the driver chip to the side far from the driver chip.
  • the purpose of the present disclosure is to provide an array substrate, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides an array substrate, including: a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines and the data lines The lines are crossed to define a plurality of sub-pixel regions distributed in the array; the array substrate further includes:
  • the first electrode includes a first part located in the display area and a second part located in the peripheral area;
  • the electrode connecting line is located in the peripheral region, the electrode connecting line is electrically connected with the second part, and is used for providing a first signal to the first electrode;
  • a plurality of compensation signal lines, at least part of the compensation signal lines are located in the display area, and the compensation signal lines are electrically connected to the first part.
  • the multiple sub-pixel regions are divided into multiple rows of sub-pixel regions, and the compensation signal lines correspond to at least one row of sub-pixel regions one-to-one;
  • At least a portion of the compensation signal line is located in a corresponding row of sub-pixel regions, and in the corresponding row of sub-pixel regions, the compensation signal line is electrically connected to the first portion through at least one first via structure.
  • each row of sub-pixel regions can form multiple pixel regions, and each of the pixel regions includes at least two adjacent sub-pixel regions;
  • the compensation signal line is electrically connected to the first part through a plurality of first via structures, and the plurality of first via structures are distributed in the plurality of pixel regions formed by a corresponding row of sub-pixel regions in a one-to-one correspondence. middle.
  • the pixel area includes a first sub-pixel area, a second sub-pixel area and a third sub-pixel area,
  • the first via structure in the pixel area is located in the first sub-pixel area included in the pixel area.
  • the first via structure includes: a first via hole, a second via hole and a first conductive pattern
  • the first conductive pattern is located between the compensation signal line and the first part, the compensation signal line is electrically connected to the first conductive pattern through the first via hole, and the first conductive pattern passes through the The second via hole is electrically connected to the first part.
  • the compensation signal line includes a third portion and a fourth portion, and along an extension direction perpendicular to the compensation signal line, the width of the third portion is greater than the width of the fourth portion, and the first portion
  • the orthographic projection of the via hole on the base of the array substrate overlaps with the orthographic projection of the third portion on the base; and/or the orthographic projection of the second via hole on the base, Overlaps the orthographic projection of the third portion on the substrate.
  • the first conductive pattern and the data line are provided in the same layer and the same material.
  • the extension direction of the compensation signal line is the same as the extension direction of the gate line, and the compensation signal line and the gate line are provided in the same layer and material.
  • the array substrate further includes:
  • the second electrodes are located in the plurality of sub-pixel regions in a one-to-one correspondence, and the second electrodes are located on the side of the first electrode facing away from the base of the array substrate; the first electrodes The electrodes are provided with a plurality of openings corresponding to the plurality of second electrodes one-to-one;
  • Two via structures are electrically connected to the corresponding second electrodes; the second via structure includes a third via hole, a fourth via hole and a second conductive pattern, the second conductive pattern is located at the driving signal output end and between the second electrodes; the drive signal output terminal is electrically connected to the second conductive pattern through the third via hole, and the second conductive pattern is connected to the corresponding second electrode through the fourth via hole electrical connection;
  • the orthographic projection of the fourth via hole on the base of the array substrate is surrounded by the orthographic projection of the corresponding opening on the base.
  • the array substrate further includes:
  • the second electrodes are located in the plurality of sub-pixel regions in a one-to-one correspondence, and the second electrodes are located between the first electrodes and the base of the array substrate;
  • the array substrate further includes a first signal input terminal disposed on the first side of the first electrode;
  • the second portion surrounds the first portion, the second portion includes a first sub-portion, a second sub-portion and a third sub-portion, and along the extending direction of the data line, the second sub-portion is located in the between the first subsection and the third subsection;
  • the electrode connecting line includes:
  • the first electrode connection line is respectively electrically connected to the first sub-section and the first signal input terminal;
  • the second electrode connecting line is respectively electrically connected to the second sub-section and the first signal input terminal;
  • a third electrode connecting line, the third electrode connecting line is electrically connected to the third sub-section and the first signal input terminal, respectively.
  • the electrode connection line includes a plurality of the first electrode connection lines, and the plurality of the first electrode connection lines are arranged in sequence along the extending direction of the grid line;
  • the electrode connection line includes two second electrode connection lines, one second electrode connection line is located on the third side of the first electrode, and the other second electrode connection line is located on the fourth side of the first electrode, so the third side and the fourth side are opposite along the extending direction of the grid lines;
  • the third electrode connecting line surrounds the second side, the third side and the fourth side of the first electrode, the second side is opposite to the first side along the extending direction of the data line, and the first side is opposite to the first side along the extending direction of the data line.
  • the three-electrode connecting line is electrically connected to two ends of the third sub-section along the extending direction of the gate line, respectively.
  • a second aspect of the present disclosure provides a display device including the above-mentioned array substrate.
  • the display device further includes a color filter substrate and a liquid crystal layer, the color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located between the color filter substrate and the array substrate.
  • a third aspect of the present disclosure provides a method for fabricating an array substrate, the array substrate includes a display area and a peripheral area surrounding the display area; the fabrication method includes:
  • the first electrode comprising a first part located in the display area and a second part located in the peripheral area;
  • the electrode connecting line is located in the peripheral region, and the electrode connecting line is electrically connected to the second part for providing a first signal for the first electrode;
  • a plurality of compensation signal lines are fabricated, at least part of the compensation signal lines is located in the display area, and the compensation signal lines are electrically connected to the first part.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of point selection provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a first signal input by an IC and a first signal at seven points according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a first signal input by an IC and a first signal at three points according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a second structure of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the first electrode and the compensation signal line in FIG. 5;
  • FIG. 7 is a schematic structural diagram of a sub-pixel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view along the A1A2 direction in FIG. 7;
  • FIG. 9 is a schematic diagram of a first signal input by an IC and a first signal at five points according to an embodiment of the present disclosure
  • Figure 10 is a schematic diagram of RC Loading generated at the proximal and distal ends of the first electrode before and after compensation using the compensation signal line.
  • the present disclosure provides an array substrate, which includes: a display area 10 and a peripheral area surrounding the display area 10 ; the display area 10 is provided with a plurality of gate lines and a plurality of data lines, The gate lines and the data lines are crossed to define a plurality of sub-pixel regions distributed in an array (eg, a first sub-pixel region 201, a second sub-pixel region 202, and a third sub-pixel region 203); the array substrate also include:
  • the first electrode 30 includes a first part 301 located in the display area 10 and a second part 302 located in the peripheral area;
  • electrode connection lines may include: first electrode connection lines 401, second electrode connection lines 402 and third electrode connection lines 403), the electrode connection lines are located in the peripheral region, and the electrode connection lines are connected to the second electrode connection lines
  • the portion 302 is electrically connected for providing a first signal to the first electrode 30 .
  • the first electrode 30 is a block-shaped common electrode, and the common electrode includes a first part 301 and a second part 302 of an integrated structure, the first part 301 is located in the display area 10, and the second part 302 is located in the display area 10. In the peripheral area, the second portion 302 surrounds the first portion 301 .
  • the size of the first electrode 30 and the length of the electrode connecting lines are both larger , so that after the first signal is input to the array substrate by the driver chip, the resistance-capacitance load loaded on the first electrode 30 and the electrode connecting line inside the array substrate has a larger delay effect on signal transmission (ie, RC Loading); moreover, for the first signal During the transmission process, the capacitive coupling of the scanning signal transmitted on the gate line, the capacitive coupling of the data signal transmitted on the data line, and the capacitive coupling of the storage capacitor included in the driving circuit used to drive the sub-pixel display in the array substrate are more serious. , causing the display product to be prone to the phenomenon of uneven display screen.
  • the periphery of the array substrate adopts the VCOM0 signal, the VCOM1 signal, the VCOM2 signal input, the VCOM0 signal, the VCOM1 signal, and the VCOM2 signal are all the first signals.
  • DP side transmits the first signal of the near-end pixel of the array substrate close to the IC;
  • VCOM1 is input from the left and right sides of the array substrate to the middle of the array substrate;
  • VCOM2 is input from the left and right sides of the array substrate to the side of the array substrate away from the IC (ie DO side) input to transmit the first signal of the remote pixel of the array substrate.
  • the electrode connecting line is fabricated by stacking Ti/Al/Ti metal layers with thicker film layers, and the sheet resistance is in the order of 1E-2.
  • the first electrode 30 is made of indium tin oxide (ITO) material, and the sheet resistance is in the order of 1E+1.
  • the first electrode 30 points corresponding to the pixels located at different positions in the display area 10 are selected, and the horizontal H direction of the array substrate corresponds to the abscissa of each point, The vertical V direction of the array substrate corresponds to the ordinate of each point.
  • the electrode connecting lines located in the peripheral area of the array substrate are made of Ti/Al/Ti metal layers with thicker layers, (0,0), (0,1), (0,2), (0,3), (0,4); (1,0), (1,4); (2,0), (2,1), (2,2), (2,3), (2,4) and other points It is close to the surrounding area, so the impedance of the corresponding first signal input is relatively small.
  • FIG. 3 it is a schematic diagram of the waveform of the first signal input by the IC, and the schematic diagram of the waveform of the first signal input at the above-mentioned part of the points.
  • Data_in is the first signal input by IC
  • Data_out1 ⁇ 7 are (0,0), (0,1), (0,2), (0,3), (0,4); (1,0), (1, 4)
  • the first signal in the display area 10 corresponding to the point position. It can be seen that the rise time Tr and the fall time Tf of Data_out1-7 are consistent with the rise time Tr and the fall time Tf of Data_in.
  • the points (2,0), (2,1), (2,2), (2,3), (2,4) are the same as (0,0) , (0,1), (0,2), (0,3), (0,4) the same resistance, (2,0), (2,1), (2,2), (2,3) , the rise time Tr and fall time Tf of the first signal corresponding to the point (2, 4) are also consistent with the rise time Tr and fall time Tf of Data_in. Therefore, it can be determined that the first signal corresponding to the pixel located in the display area 10 close to the peripheral area in the array substrate is normally transmitted, and the first signal behaves uniformly at the position of the display area 10 close to the peripheral area in the array substrate. It should be noted that the above-mentioned rising time Tr and falling time Tf are generated at the moment when the display product is turned on and off when the array substrate is applied to the display product.
  • the first signals at points (1,1), (1,2) and (1,3) need to be transmitted through a larger area of the ITO film layer.
  • the waveform diagram of the first signal input at the point (1,1), (1,2), (1,3) shown in Figure 4 is obtained.
  • Data_out1 ⁇ 3 are respectively is the first signal in the display area 10 corresponding to the three points (1,1), (1,2), and (1,3).
  • the Tr at the point (1,1) is 80ns
  • the Tr at the point (1,2) is 271ns
  • the Tr at the point (1,3) is 530ns.
  • the Tr and Tf of the first signal transmission need to be less than 2.5 times of the near end fluctuations in order to satisfy the transmission uniformity of the first signal. Therefore, when the near-end Tr is 80ns, the far-end needs to be less than 200ns to meet the signal uniformity requirement. Therefore, it can be concluded from the waveform in FIG. 4 that when the first signal inside the array substrate is only transmitted by the ITO film layer, it is easy to cause uneven display of the array substrate, which ultimately affects the display quality.
  • an embodiment of the present disclosure provides an array substrate, including: a display area 10 and a peripheral area surrounding the display area 10 ; the display area 10 is provided with a plurality of gate lines 71 and a plurality of Data lines 72, the gate lines 71 and the data lines 72 are arranged to intersect, and define a plurality of sub-pixel regions distributed in an array; the array substrate further includes:
  • the first electrode 30 includes a first part 301 located in the display area 10 and a second part 302 located in the peripheral area;
  • the electrode connection line is located in the peripheral region, and the electrode connection line is electrically connected to the second part 302 for providing a first signal to the first electrode 30;
  • a plurality of compensation signal lines 50 is located in the display area 10 , and the compensation signal lines 50 are electrically connected to the first part 301 .
  • the gate line 71 extends along the first direction
  • at least part of the data line 72 extends along the second direction.
  • the first direction includes a horizontal direction
  • the second direction includes a vertical direction.
  • the array substrate further includes a drive circuit corresponding to the sub-pixel regions one-to-one.
  • the drive circuit includes a transistor 73 and a storage capacitor, and the gate of the transistor 73 is electrically connected to the corresponding gate line 71 .
  • the input electrode of the transistor 73 is electrically connected to the corresponding data line 72, and the output electrode of the transistor 73 is electrically connected to the pixel electrode in the corresponding sub-pixel region.
  • the pixel electrode is multiplexed as one electrode plate of the storage capacitor, and the first electrode 30 is multiplexed as another electrode plate of the storage capacitor.
  • the first electrode 30 is a block-shaped common electrode, and the common electrode includes a first part 301 and a second part 302 in an integrated structure.
  • the first part 301 is located in the display area 10 and the second part 302 is located in the peripheral area.
  • the second portion 302 surrounds the first portion 301 .
  • the array substrate includes a base, and a light-shielding layer, an active layer (P-Si can be used), a gate insulating layer, a gate metal layer, an interlayer insulating layer, a source-drain metal layer, Flat layer, C-ITO layer, passivation layer and P-ITO layer, etc.
  • the fabrication of the light shielding layer, active layer, gate metal layer, interlayer insulating layer, source-drain metal layer, flat layer, C-ITO layer, passivation layer and P-ITO layer requires a total of 9 patterning processes (ie, 9 mask processes). ).
  • the gate metal layer is used to form the gate of the transistor 73 and the gate line 71 included in the driving circuit in the array substrate.
  • the source-drain metal layer is used to form the data lines 72 and some conductive patterns in the array substrate.
  • the C-ITO layer includes a first electrode 30, and the P-ITO layer includes a pixel electrode. Notably, the C-ITO layer and the P-ITO layer can be interchanged.
  • the electrode connecting line and the source-drain metal layer are provided in the same layer and material, and can be formed in the same patterning process.
  • the electrode connection lines and the second portion 302 are electrically connected through via holes penetrating through a flat layer (eg, an organic resin layer).
  • the array substrate includes a plurality of compensation signal lines 50.
  • the extension directions of the compensation signal lines 50 are the same, and the plurality of compensation signal lines 50 are arranged at intervals along a direction perpendicular to the extension direction.
  • the resistance of the first electrode 30 is reduced, thereby reducing the resistance of the first electrode 30, thereby reducing the resistance of the first electrode 30.
  • the transmission delay of the first signal in the display area 10 is relatively large is effectively improved, the rise time and fall time of the first signal at the power-on and power-off instants are reduced, and the degree of capacitive coupling is improved; therefore, the present disclosure
  • the array substrate provided by the embodiment is applied to a large-size and high-resolution display product, the uniformity of the first signal of the large-size display product in different display areas 10 can be well ensured, thereby better improving the display product's performance. Display quality.
  • the plurality of sub-pixel regions are divided into a plurality of rows of sub-pixel regions, and the compensation signal lines 50 are in one-to-one correspondence with at least one row of sub-pixel regions;
  • At least part of the compensation signal line 50 is located in a corresponding row of sub-pixel regions, and in the corresponding row of sub-pixel regions, the compensation signal line 50 is electrically connected to the first part 301 through at least one first via structure.
  • the plurality of compensation signal lines 50 are in one-to-one correspondence with the plurality of rows of sub-pixels, and at least part of each of the compensation signal lines 50 is located in a corresponding row of sub-pixel regions.
  • Each of the compensation signal lines 50 can be electrically connected to the first part 301 through at least one first via structure.
  • setting each row of sub-pixel regions can form a plurality of pixel regions 20, and each of the pixel regions 20 includes at least two adjacent sub-pixel regions (eg, a sub-pixel area 201, a second sub-pixel area 202, a third sub-pixel area 203); the compensation signal line 50 is electrically connected to the first part 301 through a plurality of first via structures 61, and the plurality of first A via structure 61 is distributed in the plurality of pixel regions formed by a corresponding row of sub-pixel regions in a one-to-one correspondence.
  • the compensation signal line 50 is electrically connected to the first part 301 through a plurality of first via structures 61
  • the plurality of first A via structure 61 is distributed in the plurality of pixel regions formed by a corresponding row of sub-pixel regions in a one-to-one correspondence.
  • each row of sub-pixel regions can form multiple pixel regions, each of the pixel regions includes at least two adjacent sub-pixel regions, and each sub-pixel region can only belong to one pixel region.
  • the plurality of first via structures are arranged in a one-to-one correspondence in the plurality of pixel regions formed by a corresponding row of sub-pixel regions, so that the plurality of first via structures connected to each compensation signal line 50 can be Evenly distributed.
  • each compensation signal line 50 to be electrically connected to the first part 301 through a plurality of first via structures evenly distributed, thereby greatly improving the transmission of the first signal in the display area 10 uniformity.
  • the first electrode 30 is exemplarily made of ITO
  • the compensation signal line 50 is made of a first gate metal layer
  • the first gate metal layer is made of In the metal stack structure of Ti/Al/Ti
  • the sheet resistance of the compensation signal line 50 is reduced by more than one order of magnitude relative to the first electrode 30 .
  • the first signals at points (1,0), (1,1), (1,2), (1,3), (1,4) simultaneously pass through the first electrode 30 and the compensation signal line 50 Transmission, after calculating the impedance of the first signal input corresponding to the 5 points, the (1,0), (1,1), (1,2), (1,3), (1 shown in Figure 9 are obtained.
  • the waveform diagram of the first signal input at the point, Data_out1 ⁇ 5 are (1,0), (1,1), (1,2), (1,3), (1,4) points respectively The first signal in the corresponding display area 10 .
  • the Tr at points (1,0) and (1,4) are all 80ns, and the Tr at points (1,1), (1,2), and (1,3) are all 126ns; it can be seen that the above embodiments provide In the array substrate, the Tr and Tf of the first signal transmission satisfy that the far-end fluctuation is less than 2.5 times that of the near-end. Therefore, in the array substrate provided by the above embodiment, the first electrode is compensated by the compensation signal line 50 30, the transmission uniformity of the first signal is satisfied.
  • FIG. 10 shows the RC Loading generated at the proximal end and the distal end of the first electrode 30 before compensation by the compensation signal line 50 , and after compensation by the compensation signal line 50 , the first electrode 30 RC Loading generated by the near and far ends. From the figure, it can be determined that after the compensation using the compensation signal line 50, the RC Loading generated at the proximal end and the distal end of the first electrode 30 is significantly reduced.
  • the pixel area includes a first sub-pixel area 201 , a second sub-pixel area 202 and a third sub-pixel area 203 , and the first via structure in the pixel area is located at The pixel area includes the first sub-pixel area 201 .
  • the first sub-pixel region 201 includes a blue sub-pixel region
  • the second sub-pixel region 202 includes a red sub-pixel region
  • the third sub-pixel region 203 includes a green sub-pixel region.
  • the first sub-pixel region 201 includes a red sub-pixel region
  • the second sub-pixel region 202 includes a green sub-pixel region
  • the third sub-pixel region 203 includes a blue sub-pixel region.
  • the first sub-pixel region 201 includes a green sub-pixel region
  • the second sub-pixel region 202 includes a blue sub-pixel region
  • the third sub-pixel region 203 includes a red sub-pixel region.
  • the above arrangement makes the compensation signal line 50 disposed in each pixel area, and in each sub-pixel, the compensation signal line 50 can be electrically connected to the first part 301 through the first via structure, so as to better improve The uniformity of the transmission of the first signal in the display area 10 is ensured.
  • the compensation signal line 50 is electrically connected to the first part 301 through a plurality of first via structures 61 , and the plurality of first via structures 61 are distributed in a one-to-one correspondence in a plurality of sub-pixel regions included in a corresponding row of sub-pixel regions.
  • each sub-pixel area has a compensation signal line 50, and in each sub-pixel area, the compensation signal line 50 can be electrically connected to the first part 301 through the first via structure 61, so as to better The uniformity of the transmission of the first signal in the display area 10 is improved.
  • disposing the first via structure 61 includes: a first via hole 611 , a second via hole 612 and a first conductive pattern 613 ; the first conductive pattern 613 is located between the compensation signal line 50 and the first part 301, the compensation signal line 50 is electrically connected to the first conductive pattern 613 through the first via hole 611, and the first conductive pattern 613 passes through the The second via hole 612 is electrically connected to the first portion 301 .
  • the first conductive pattern 613 and the source-drain metal layer are provided in the same layer and the same material, the first via hole 611 penetrates the interlayer insulating layer ILD, and the compensation signal line 50 can pass through the The first via hole 611 is electrically connected to the first conductive pattern 613 , the second via hole 612 penetrates the flat layer PLN, and the first conductive pattern 613 can be connected to the first conductive pattern 613 through the second via hole 612 .
  • a portion 301 is electrically connected.
  • FIG. 8 also illustrates a substrate 91, a gate insulating layer GI and a passivation layer PVX, and other film layers may also be included between the substrate 91 and the gate insulating layer GI, which are not shown in the figure.
  • the compensation signal line 50 is provided to be electrically connected to the first part 301 through the first via structure, which not only ensures the connection between the compensation signal line 50 and the first part 301 Good electrical connection performance improves the working stability of the array substrate; and avoids forming too deep via holes between the compensation signal line 50 and the first part 301, thereby reducing the realization of The process difficulty of the compensation signal line 50 being electrically connected with the first part 301 is.
  • the compensation signal line 50 includes a third portion 501 and a fourth portion 502 , and the width of the third portion 501 is perpendicular to the extending direction of the compensation signal line 50 . Greater than the width of the fourth portion 502, the orthographic projection of the first via hole 611 on the base of the array substrate is arranged to overlap with the orthographic projection of the third portion 501 on the base; and/ Or, the orthographic projection of the second via hole on the substrate overlaps the orthographic projection of the third portion 501 on the substrate.
  • the compensation signal line 50 includes a third part 501 and a fourth part 502 of an integrated structure; exemplarily, the third part 501 and the fourth part 502 are alternately arranged.
  • the orthographic projection of the first via hole on the base of the array substrate is located inside the orthographic projection of the third portion 501 on the base; and/or, the second via hole
  • the orthographic projection on the substrate is located inside the orthographic projection of the third portion 501 on the substrate.
  • the above arrangement can better ensure the connection performance between the compensation signal line 50 and the first part 301 .
  • the first conductive pattern 613 and the data line 72 are provided in the same layer and material.
  • both the first conductive pattern 613 and the data line 72 are formed on the surface of the interlayer insulating layer facing away from the substrate, and both the first conductive pattern 613 and the data line 72 are made of Ti/ Al/Ti metal lamination structure.
  • the above arrangement enables the first conductive pattern 613 and the data line 72 to be formed simultaneously in the same patterning process, thereby effectively simplifying the fabrication process of the array substrate and saving the fabrication cost of the array substrate.
  • the extension direction of the compensation signal line 50 is substantially the same as the extension direction of the gate line 71 , and the compensation signal line 50 and the gate line 71 are provided in the same layer and material.
  • both the compensation signal line 50 and the gate line 71 extend in a horizontal direction.
  • a plurality of the compensation signal lines 50 and a plurality of the gate lines 71 are alternately arranged at intervals.
  • the compensation signal line 50 and the gate line 71 are both formed on the surface of the gate insulating layer facing away from the substrate, and both the compensation signal line 50 and the gate line 71 are made of Ti/Al/ The metal lamination structure of Ti.
  • the above arrangement enables the compensation signal line 50 and the gate line 71 to be formed at the same time in the same patterning process, without adding an additional patterning process specially used for fabricating the compensation signal line 50, thereby effectively simplifying the array substrate
  • the manufacturing process can save the manufacturing cost of the array substrate. Therefore, when the array substrate provided in the above embodiment includes the compensation signal line 50 , the fabrication can also be completed by the 9mask process.
  • the array substrate further includes:
  • the second electrodes 70 are located in the plurality of sub-pixel regions in a one-to-one correspondence, and the second electrodes 70 are located on the side of the first electrode 30 facing away from the base of the array substrate;
  • the first electrode 30 is provided with a plurality of openings 3011 corresponding to the plurality of second electrodes 70 one-to-one;
  • the second via structure 62 is electrically connected to the corresponding second electrode 70;
  • the second via structure 62 includes a third via hole 621, a fourth via hole 622 and a second conductive pattern 623, the second conductive pattern 623 is located between the driving signal output terminal and the second electrode 70;
  • the driving signal output terminal is electrically connected to the second conductive pattern 623 through the third via hole 621, and the second conductive pattern 623 It is electrically connected to the corresponding second electrode 70 through the fourth via hole 622;
  • the orthographic projection of the fourth via hole 622 on the base of the array substrate is surrounded by the orthographic projection of the corresponding opening 3011 on the base.
  • the second electrode 70 includes a pixel electrode, and the pixel electrode is formed in a structure having a slit (ie, a slit structure).
  • the second electrodes 70 and the driving circuits are in one-to-one correspondence with the sub-pixel regions.
  • the driving circuit is located between the corresponding second electrode 70 and the base of the array substrate.
  • the second electrode 70 is located on the side of the first electrode 30 facing away from the base of the array substrate.
  • the drive signal output end of the drive circuit that is, the output end of the transistor 73 is made of an active layer, and there are at least a gate insulating layer, an interlayer insulating layer and a flat layer between the drive signal output end and the corresponding second electrode 70 . , the first electrode 30 and the passivation layer. Therefore, if the driving signal output terminal is to be electrically connected to the corresponding second electrode 70, it needs to pass through the gate insulating layer, the interlayer insulating layer, the flat layer, the first electrode 30 and the passivation layer.
  • the array substrate further includes the second via structure, and the second via structure corresponds to the second electrodes 70 one-to-one.
  • the second via structure includes a third via hole, a fourth via hole and a second conductive pattern, and the second conductive pattern is located between the driving signal output end and the second electrode 70 .
  • the second conductive pattern and the source-drain metal layer are provided in the same layer and material, and the third via hole penetrates through the gate insulating layer and the interlayer insulating layer, so that the driving signal is output.
  • the terminal can be electrically connected to the second conductive pattern through the third via hole; the fourth via hole penetrates through the flat layer, the first electrode 30 and the passivation layer, so that the second conductive pattern is conductive
  • the pattern can be electrically connected to the corresponding second electrode 70 through the fourth via hole.
  • the first electrode 30 has conductivity, in order to avoid the short circuit between the second electrode 70 and the first electrode 30 , a plurality of second electrodes can be provided on the first electrode 30 .
  • the electrodes 70 have a one-to-one correspondence of the openings 3011, so that the orthographic projection of the fourth via hole passing through the first electrode 30 on the substrate can be surrounded by the orthographic projection of the corresponding opening 3011 on the substrate, and the There is a certain distance between the inner wall of the fourth via hole and the boundary of the corresponding opening 3011 .
  • the driving signal output terminal is set to be electrically connected to the corresponding second electrode 70 through the second via structure, so as to ensure a good connection between the driving signal output terminal and the corresponding second electrode 70 .
  • the electrical connection performance is improved, and the working stability of the array substrate is better improved.
  • the array substrate further includes:
  • the second electrodes 70 are located in the plurality of sub-pixel regions in a one-to-one correspondence, and the second electrodes 70 are located between the first electrodes 30 and the base of the array substrate;
  • the plurality of second electrodes 70 may also be disposed between the first electrodes 30 and the base of the array substrate, so that a gate is spaced between the driving signal output end and the corresponding second electrode 70 A polar insulating layer, an interlayer insulating layer and a flat layer. Therefore, if the driving signal output terminal is to be electrically connected to the corresponding second electrode 70 , it only needs to pass through the gate insulating layer, the interlayer insulating layer and the flat layer, and there is no need to form an opening on the first electrode 30 .
  • the driving signal output terminal may be electrically connected to the corresponding second electrode 70 through a third via structure.
  • the third via structure includes a fifth via hole, a sixth via hole and a third conductive pattern.
  • the third conductive pattern is located between the fifth via hole and the sixth via hole.
  • the third conductive pattern and the source-drain metal layer are provided in the same layer and material, and the fifth via hole penetrates through the gate insulating layer and the interlayer insulating layer, so that the driving signal is output.
  • the terminal can be electrically connected to the third conductive pattern through the fifth via hole; the sixth via hole penetrates the flat layer, so that the third conductive pattern can pass through the sixth via hole to be connected to the corresponding third conductive pattern.
  • the two electrodes 70 are electrically connected.
  • the driving signal output terminal is set to be electrically connected to the corresponding second electrode 70 through the third via structure, so as to ensure a good connection between the driving signal output terminal and the corresponding second electrode 70 .
  • the electrical connection performance is improved, and the working stability of the array substrate is better improved.
  • the array substrate further includes a first signal input terminal disposed on the first side of the first electrode 30 ;
  • the second portion 302 surrounds the first portion 301, and the second portion 302 includes a first sub-portion 3021, a second sub-portion 3022 and a third sub-portion 3023.
  • the The second subsection 3022 is located between the first subsection 3021 and the third subsection 3023;
  • the electrode connecting line includes:
  • first electrode connection line 401 is respectively electrically connected to the first sub-section 3021 and the first signal input end;
  • the second electrode connection line 402 is electrically connected to the second sub-section 3022 and the first signal input terminal, respectively;
  • the third electrode connecting line 403 is electrically connected to the third sub-section 3023 and the first signal input terminal, respectively.
  • the first signal input terminal includes one or more ports.
  • the first signal input terminal includes one port, all the electrode connecting lines are electrically connected to the one port, and receive the electrical signal provided by the one port.
  • the first signal input terminal includes multiple ports, the multiple ports all output the same first signal; exemplarily, the first signal input terminal includes multiple first ports and two second ports and two third ports, the plurality of first ports are used for outputting the VCOM0 signal, the two second ports are used for outputting the VCOM1 signal, and the two third ports are used for outputting the VCOM2 signal.
  • the second part 302 is formed in a back-shaped structure, the second part 302 can be divided into three sub-parts, the first sub-part 3021 is located on the first side, and the first sub-part 3021 includes all the The back-shaped structure is located on one side of the first side, the third sub-section 3023 is located on the second side of the first electrode 30, and the third sub-section 3023 includes the side of the back-shaped structure on the second side,
  • the second sub-section 3022 includes a side on the third side of the first electrode 30 and a side on the fourth side of the first electrode 30 .
  • the above-mentioned arrangement of the electrode connection line includes the first electrode connection line 401, the second electrode connection line 402 and the third electrode connection line 403, so that the first electrode 30 can be on the first side, The second side and the position between the first side and the second side simultaneously write the first signal to the first electrode 30, thereby further improving the display area of the first signal 10 Uniformity of transmission.
  • the electrode connection lines include a plurality of the first electrode connection lines 401 , and the plurality of the first electrode connection lines 401 are arranged in sequence along the extending direction of the gate lines 71 . ;
  • the electrode connecting line includes two second electrode connecting lines 402 , one second electrode connecting line 402 is located on the third side of the first electrode 30 , and the other second electrode connecting line 402 is located on the third side of the first electrode 30 .
  • the fourth side, the third side and the fourth side are opposite along the extending direction of the gate line 71;
  • the third electrode connection line 403 surrounds the second side, the third side and the fourth side of the first electrode 30 , and the second side is opposite to the first side along the extending direction of the data line 72 ,
  • the third electrode connecting line 403 is electrically connected to two ends of the third sub-section 3023 along the extending direction of the gate line 71 , respectively.
  • the electrode connection lines include a plurality of first electrode connection lines 401, and the plurality of first electrode connection lines 401 are arranged in sequence along the extending direction of the grid lines 71; the first electrode connection lines 401 are connected to the The first ports are in one-to-one correspondence, and each of the first electrode connecting lines 401 is electrically connected to the first sub-section 3021 and the corresponding first port, respectively.
  • the electrode connecting line includes two second electrode connecting lines 402, the two second electrode connecting lines 402 correspond to the two second ports one-to-one, and one second electrode connecting line 402 corresponds to the corresponding
  • the second port is electrically connected to the second sub-portion 3022 located on the third side of the first electrode 30
  • another second electrode connection line 402 is respectively connected to the corresponding second port and the second sub-portion 3022 located on the third side of the first electrode 30 .
  • the second subsection 3022 of the fourth side is electrically connected.
  • the second electrode connecting line 402 may be electrically connected to the middle part of the second sub-part 3022 .
  • Both ends of the third electrode connecting line 403 are electrically connected to the two third ports in a one-to-one correspondence, and the third electrode connecting line 403 and the third sub-portion 3023 are connected along the extending direction of the gate line 71 .
  • the two ends are respectively electrically connected; exemplarily, the third electrode connecting line 403 is electrically connected to the two ends of the third sub-section 3023 along the extending direction of the gate line 71 through the two conductive parts 80, and the conductive The extending direction of the portion 80 is the same as the extending direction of the data line 72 .
  • the conductive portion 80 and the third electrode connecting line 340 are formed as an integral structure.
  • the first electrode 30 can simultaneously write to the first electrode 30 on the first side, the second side, the third side and the fourth side the first signal, thereby further improving the uniformity of the transmission of the first signal in the display area 10 .
  • FIG. 5 also illustrates the electrostatic discharge structure ESD in the array substrate, the gate driving circuit GOA, the border line 90 and the feed line 81 of the array substrate.
  • Embodiments of the present disclosure further provide a display device including the array substrate provided by the above embodiments.
  • the resistance of the first electrode 30 is reduced, thereby effectively improving the electrical resistance of the first signal.
  • the problem of large transmission delay in the display area 10 reduces the rise time and fall time of the first signal at the moment of power-on and power-off, and improves the degree of capacitive coupling;
  • the uniformity of the first signal in different display areas 10 of large-size display products can be well ensured, thereby better improving the display quality of the display products.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned array substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer.
  • the display device further includes a color filter substrate and a liquid crystal layer, the color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located between the color filter substrate and the array substrate.
  • the color filter substrate includes color resist patterns corresponding to the sub-pixel regions in the array substrate one-to-one, and at least part of the orthographic projection of the color resist pattern on the array substrate is located in the corresponding sub-pixel regions middle.
  • the display device is a liquid crystal display device, and the first electrode 30 and the second electrode 70 in the array substrate jointly drive the liquid crystal in the liquid crystal layer to deflect, thereby realizing the display function of the display device.
  • An embodiment of the present disclosure further provides a method for fabricating an array substrate, where the array substrate includes a display area 10 and a peripheral area surrounding the display area 10; the fabrication method includes:
  • the first electrode 30 includes a first part 301 located in the display area 10 and a second part 302 located in the peripheral area;
  • the electrode connecting line is located in the peripheral region, and the electrode connecting line is electrically connected to the second part 302 for providing a first signal to the first electrode 30;
  • a plurality of compensation signal lines 50 are fabricated, at least part of the compensation signal lines 50 is located in the display area 10 , and the compensation signal lines 50 are electrically connected to the first part 301 .
  • the embodiments of the present disclosure provide When the array substrate produced by the manufacturing method is applied to a large-size, high-resolution display product, the uniformity of the first signal of the large-size display product in different display areas 10 can be well ensured, so as to better improve the display product. display quality.

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Abstract

一种阵列基板及其制作方法、显示装置。所述阵列基板包括：显示区域（10）和围绕所述显示区域（10）的周边区域；所述显示区域（10）设置有多条栅线（71）和多条数据线（72），所述栅线（71）与所述数据线（72）交叉设置，限定出阵列分布的多个子像素区（201、202、203）；所述阵列基板还包括：第一电极（30），所述第一电极（30）包括位于所述显示区域（10）的第一部分（301）和位于所述周边区域的第二部分（302）；电极连接线（401、402、403），所述电极连接线（401、402、403）位于所述周边区域，所述电极连接线（401、402、403）与所述第二部分（302）电连接，用于为所述第一电极（30）提供第一信号；多条补偿信号线（50），所述补偿信号线（50）的至少部分位于所述显示区域（10），所述补偿信号线（50）与所述第一部分（301）电连接。

Description

一种阵列基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，显示产品的应用范围越来越广泛。显示产品一般包括显示面板和位于显示面板一侧的驱动芯片，驱动芯片用于为显示面板提供其显示所需的各种功能信号。对于大尺寸的显示产品，该功能信号需要经过较长的传输路径，才能够从显示面板靠近驱动芯片的一侧传输至远离驱动芯片的一侧。
发明内容
本公开的目的在于提供一种阵列基板及其制作方法、显示装置。
本公开的第一方面提供一种阵列基板，包括：显示区域和围绕所述显示区域的周边区域；所述显示区域设置有多条栅线和多条数据线，所述栅线与所述数据线交叉设置，限定出阵列分布的多个子像素区；所述阵列基板还包括：
第一电极，所述第一电极包括位于所述显示区域的第一部分和位于所述周边区域的第二部分；
电极连接线，所述电极连接线位于所述周边区域，所述电极连接线与所述第二部分电连接，用于为所述第一电极提供第一信号；
多条补偿信号线，所述补偿信号线的至少部分位于所述显示区域，所述补偿信号线与所述第一部分电连接。
可选的，所述多个子像素区划分为多行子像素区，所述补偿信号线与至少一行子像素区一一对应；
所述补偿信号线的至少部分位于对应的一行子像素区中，在对应的一行子像素区中，所述补偿信号线通过至少一个第一过孔结构与所述第一部分电 连接。
可选的，每行子像素区均能够形成多个像素区，每个所述像素区包括至少两个相邻的子像素区；
所述补偿信号线通过多个第一过孔结构与所述第一部分电连接，所述多个第一过孔结构一一对应分布在对应的一行子像素区所形成的所述多个像素区中。
可选的，所述像素区包括第一子像素区、第二子像素区和第三子像素区，
所述像素区中的第一过孔结构位于该像素区包括的第一子像素区中。
可选的，所述第一过孔结构包括：第一过孔、第二过孔和第一导电图形；
所述第一导电图形位于所述补偿信号线与所述第一部分之间，所述补偿信号线通过所述第一过孔与所述第一导电图形电连接，所述第一导电图形通过所述第二过孔与所述第一部分电连接。
可选的，所述补偿信号线包括第三部分和第四部分，沿垂直于所述补偿信号线的延伸方向，所述第三部分的宽度大于所述第四部分的宽度，所述第一过孔在所述阵列基板的基底上的正投影，与所述第三部分在所述基底上的正投影交叠；和/或，所述第二过孔在所述基底上的正投影，与所述第三部分在所述基底上的正投影交叠。
可选的，所述第一导电图形与所述数据线同层同材料设置。
可选的，所述补偿信号线的延伸方向与所述栅线的延伸方向相同，所述补偿信号线与所述栅线同层同材料设置。
可选的，所述阵列基板还包括：
多个第二电极，所述第二电极一一对应位于所述多个子像素区中，所述第二电极位于所述第一电极背向所述阵列基板的基底的一侧；所述第一电极上设置有与所述多个第二电极一一对应的多个开口；
与所述多个第二电极一一对应的多个驱动电路，所述驱动电路位于对应的所述第二电极与所述阵列基板的基底之间，所述驱动电路的驱动信号输出端通过第二过孔结构与对应的第二电极电连接；所述第二过孔结构包括第三过孔、第四过孔和第二导电图形，所述第二导电图形位于所述驱动信号输出端与所述第二电极之间；所述驱动信号输出端通过所述第三过孔与所述第二 导电图形电连接，所述第二导电图形通过所述第四过孔与对应的第二电极电连接；
所述第四过孔在所述阵列基板的基底上的正投影，被对应的开口在所述基底上的正投影包围。
可选的，所述阵列基板还包括：
多个第二电极，所述第二电极一一对应位于所述多个子像素区中，所述第二电极位于所述第一电极与所述阵列基板的基底之间；
与所述多个第二电极一一对应的多个驱动电路，所述驱动电路位于对应的所述第二电极与所述阵列基板的基底之间，所述驱动电路的驱动信号输出端与对应的第二电极电连接。
可选的，所述阵列基板还包括设置于所述第一电极的第一侧的第一信号输入端；
所述第二部分包围所述第一部分，所述第二部分包括第一子部分、第二子部分和第三子部分，沿所述数据线的延伸方向，所述第二子部分位于所述第一子部分和所述第三子部分之间；
所述电极连接线包括：
第一电极连接线，所述第一电极连接线分别与所述第一子部分和所述第一信号输入端电连接；
第二电极连接线，所述第二电极连接线分别与所述第二子部分和所述第一信号输入端电连接；
第三电极连接线，所述第三电极连接线分别与所述第三子部分和所述第一信号输入端电连接。
可选的，所述电极连接线包括多条所述第一电极连接线，多条所述第一电极连接线沿所述栅线的延伸方向依次排列；
所述电极连接线包括两条第二电极连接线，一条第二电极连接线位于所述第一电极的第三侧，另一条第二电极连接线位于所述第一电极的第四侧，所述第三侧和所述第四侧沿所述栅线的延伸方向相对；
所述第三电极连接线围绕所述第一电极的第二侧、第三侧和第四侧，所述第二侧与所述第一侧沿所述数据线的延伸方向相对，所述第三电极连接线 与所述第三子部分沿所述栅线延伸方向的两端分别电连接。
基于上述阵列基板的技术方案，本公开的第二方面提供一种显示装置，包括上述阵列基板。
可选的，所述显示装置还包括彩膜基板和液晶层，所述彩膜基板与所述阵列基板相对设置，所述液晶层位于所述彩膜基板与所述阵列基板之间。
基于上述阵列基板的技术方案，本公开的第三方面提供一种阵列基板的制作方法，所述阵列基板包括显示区域和包围所述显示区域的周边区域；所述制作方法包括：
制作多条栅线和多条数据线，所述栅线与所述数据线交叉设置，限定出阵列分布的多个子像素区；
制作第一电极，所述第一电极包括位于所述显示区域的第一部分和位于所述周边区域的第二部分；
制作电极连接线，所述电极连接线位于所述周边区域，所述电极连接线与所述第二部分电连接，用于为所述第一电极提供第一信号；
制作多条补偿信号线，所述补偿信号线的至少部分位于所述显示区域，所述补偿信号线与所述第一部分电连接。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的阵列基板的第一种结构示意图；
图2为本公开实施例提供的点位选取示意图；
图3为本公开实施例提供的IC输入的第一信号和七个点位的第一信号的示意图；
图4为本公开实施例提供的IC输入的第一信号和三个点位的第一信号的示意图；
图5为本公开实施例提供的阵列基板的第二种结构示意图；
图6为图5中第一电极和补偿信号线示意图；
图7为本公开实施例提供的一个子像素的结构示意图；
图8为图7中沿A1A2方向的截面示意图；
图9为本公开实施例提供的IC输入的第一信号和五个点位的第一信号的示意图；
图10为采用补偿信号线补偿前后第一电极近端和远端产生的RC Loading示意图。
具体实施方式
为了进一步说明本公开实施例提供的阵列基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
如图1所示，本公开提供一种阵列基板，该阵列基板包括：显示区域10和围绕所述显示区域10的周边区域；所述显示区域10设置有多条栅线和多条数据线，所述栅线与所述数据线交叉设置，限定出阵列分布的多个子像素区(如第一子像素区201、第二子像素区202、第三子像素区203)；所述阵列基板还包括：
第一电极30，所述第一电极30包括位于所述显示区域10的第一部分301和位于所述周边区域的第二部分302；
电极连接线(可包括：第一电极连接线401、第二电极连接线402和第三电极连接线403)，所述电极连接线位于所述周边区域，所述电极连接线与所述第二部分302电连接，用于为所述第一电极30提供第一信号。
示例性的，所述第一电极30为块状的公共电极，该公共电极包括一体结构的第一部分301和第二部分302，所述第一部分301位于显示区域10，所述第二部分302位于周边区域，所述第二部分302包围所述第一部分301。
当所述阵列基板应用于31.5英寸8K，分辨率为7680(RGB)×4320的显示产品时，由于所需阵列基板的尺寸较大，第一电极30的尺寸和电极连接线的长度均较大，使得第一信号由驱动芯片输入阵列基板后，阵列基板内部加载在第一电极30和电极连接线的电阻电容负载对信号传输的延迟作用(即RC Loading)较大；而且，对于第一信号传输过程中受到栅线上传输的扫描信号的电容耦合，受到数据线上传输的数据信号的电容耦合，以及受到阵列 基板中用于驱动子像素显示的驱动电路包括的存储电容的电容耦合更加严重，导致显示产品容易出现显示画面不均匀的不良现象。
更详细地说，阵列基板的周边采用VCOM0信号，VCOM1信号，VCOM2信号输入，VCOM0信号，VCOM1信号，VCOM2信号均是所述第一信号，VCOM0从阵列基板靠近驱动芯片(IC)的一侧(即DP侧)输入，传输阵列基板靠近IC的近端像素的第一信号；VCOM1从阵列基板左右两侧输入阵列基板中部；VCOM2从阵列基板左右两侧输入阵列基板远离IC的一侧(即DO侧)输入，传输阵列基板远端像素的第一信号。
示例性的，所述电极连接线采用膜层较厚的Ti/Al/Ti金属层层叠制作，方块电阻为1E-2数量级。所述第一电极30采用氧化铟锡(ITO)材料制作，方块电阻为1E+1数量级。
为评估第一信号传输过程中的阻抗，如图2所示，选取显示区域10中位于不同位置的像素对应的第一电极30点位，阵列基板的水平H向对应各点位的横坐标，阵列基板的竖直V向对应各点位的纵坐标。
由于位于阵列基板周边区域的电极连接线采用膜层较厚的Ti/Al/Ti金属层层叠制作，(0,0)，(0,1)，(0,2)，(0,3)，(0,4)；(1,0)，(1,4)；(2,0)，(2,1)，(2,2)，(2,3)，(2,4)等点位靠近周边区域，因此对应的第一信号输入的阻抗较小。如图3所示，为IC输入的第一信号的波形示意图，以及上述部分点位的第一信号输入的波形示意。Data_in是IC输入的第一信号，Data_out1～7分别为(0,0)，(0,1)，(0,2)，(0,3)，(0,4)；(1,0)，(1,4)点位对应的显示区域10内的第一信号。可见，Data_out1～7的上升时间Tr和下降时间Tf与Data_in的上升时间Tr和下降时间Tf一致。由于阵列基板左右两侧电极连接线结构相同，因此(2,0)，(2,1)，(2,2)，(2,3)，(2,4)点位与(0,0)，(0,1)，(0,2)，(0,3)，(0,4)电阻一致，(2,0)，(2,1)，(2,2)，(2,3)，(2,4)点位对应的第一信号的上升时间Tr和下降时间Tf与Data_in的上升时间Tr和下降时间Tf也一致。由此能够确定阵列基板中位于显示区域10靠近周边区域处的像素对应的第一信号传输正常，第一信号在阵列基板中显示区域10靠近周边区域的位置表现均一。需要说明，上述上升时间Tr和下降时间Tf是阵列基板在应用于显示产品中时，显示产品在开机和关机的瞬间产生的。
在所述第一电极30采用ITO制作时，(1,1)，(1,2)，(1,3)点位的第一信号需要较大面积的ITO膜层传输，实际计算该3个点位对应的第一信号输入的阻抗后，得到图4所示的(1,1)，(1,2)，(1,3)点位的第一信号输入的波形示意图，Data_out1～3分别为(1,1)，(1,2)，(1,3)三个点位对应的显示区域10内的第一信号。(1,1)点位的Tr为80ns，(1,2)点位的Tr为271ns，(1,3)点位的Tr为530ns。根据非触控显示产品第一信号均一性的经验，第一信号传输的Tr和Tf需要远端波动是近端的2.5倍以下，才能满足第一信号的传输均一性。因此对于近端Tr为80ns时，远端需要在200ns以下才能够满足信号的均一性要求。因此，从图4中的波形可以得出上述阵列基板内部第一信号仅用ITO膜层传输时，容易造成阵列基板显示的不均一，最终影响显示质量。
请参阅图5～图7，本公开实施例提供了一种阵列基板，包括：显示区域10和围绕所述显示区域10的周边区域；所述显示区域10设置有多条栅线71和多条数据线72，所述栅线71与所述数据线72交叉设置，限定出阵列分布的多个子像素区；所述阵列基板还包括：
第一电极30，所述第一电极30包括位于所述显示区域10的第一部分301和位于所述周边区域的第二部分302；
电极连接线，所述电极连接线位于所述周边区域，所述电极连接线与所述第二部分302电连接，用于为所述第一电极30提供第一信号；
多条补偿信号线50，所述补偿信号线50的至少部分位于所述显示区域10，所述补偿信号线50与所述第一部分301电连接。
具体地，所述栅线71的至少部分沿第一方向延伸，所述数据线72的至少部分沿第二方向延伸。示例性的，所述第一方向包括水平方向，所述第二方向包括竖直方向。
所述阵列基板还包括与所述子像素区一一对应的驱动电路，示例性的，所述驱动电路包括晶体管73和存储电容，所述晶体管73的栅极与对应的栅线71电连接，所述晶体管73的输入电极与对应的数据线72电连接，所述晶体管73的输出电极与其对应的子像素区中的像素电极电连接。所述像素电极复用为所述存储电容的一个极板，所述第一电极30复用为所述存储电容的另 一个极板。
所述第一电极30为块状的公共电极，该公共电极包括一体结构的第一部分301和第二部分302，所述第一部分301位于显示区域10，所述第二部分302位于周边区域。示例性的，所述第二部分302包围所述第一部分301。当所述阵列基板应用于非触控功能的显示产品时，公共电极仅提供第一信号(即VCOM信号)，该第一信号需要保证在显示区域10内传输的电平一致。
所述阵列基板包括基底，以及沿远离基底的方向依次层叠设置的遮光层、有源层(可采用P-Si)、栅极绝缘层、栅金属层、层间绝缘层、源漏金属层、平坦层、C-ITO层、钝化层和P-ITO层等。制作所述遮光层、有源层、栅金属层、层间绝缘层、源漏金属层、平坦层、C-ITO层、钝化层和P-ITO层共需要9次构图工艺(即9mask工艺)。所述栅金属层用于形成阵列基板中驱动电路包括的晶体管73的栅极，和栅线71。所述源漏金属层用于形成所述数据线72和所述阵列基板中的一些导电图形。所述C-ITO层包括第一电极30，所述P-ITO层包括像素电极。值得注意，所述C-ITO层和所述P-ITO层可以互换位置。
示例性的，所述电极连接线与所述源漏金属层同层同材料设置，能够在同一次构图工艺中形成。在所述周边区域，所述电极连接线与所述第二部分302之间通过贯穿平坦层(如：有机树脂层)的过孔电连接。
所述阵列基板包括多条补偿信号线50，示例性的，所述补偿信号线50的延伸方向相同，所述多条补偿信号线50沿垂直于该延伸方向的方向上间隔排布。
根据上述阵列基板的具体结构可知，本公开实施例提供的阵列基板中，通过设置所述多条补偿信号线50与所述第一部分301电连接，降低了所述第一电极30的电阻，从而有效改善了所述第一信号在显示区域10传输延时较大的问题，降低了所述第一信号在开机和关机瞬间的上升时间和下降时间，改善了电容耦合的程度；因此，本公开实施例提供的阵列基板在应用于大尺寸、高分辨率的显示产品时，能够很好的保证大尺寸显示产品在不同显示区域10中第一信号的均一性，从而更好的提升显示产品的显示质量。
在一些实施例中，所述多个子像素区划分为多行子像素区，所述补偿信 号线50与至少一行子像素区一一对应；
所述补偿信号线50的至少部分位于对应的一行子像素区中，在对应的一行子像素区中，所述补偿信号线50通过至少一个第一过孔结构与所述第一部分301电连接。
示例性的，所述多条补偿信号线50与所述多行子像素一一对应，每条所述补偿信号线50的至少部分均位于对应的一行子像素区中。
每条所述补偿信号线50均能够通过至少一个第一过孔结构与所述第一部分301电连接。
如图5和图7所示，在一些实施例中，设置每行子像素区均能够形成多个像素区20，每个所述像素区20包括至少两个相邻的子像素区(如第一子像素区201、第二子像素区202、第三子像素区203)；所述补偿信号线50通过多个第一过孔结构61与所述第一部分301电连接，所述多个第一过孔结构61一一对应分布在对应的一行子像素区所形成的所述多个像素区中。
示例性的，每行子像素区均能够形成多个像素区，每个所述像素区包括至少两个相邻的子像素区，每个子像素区仅能够属于一个像素区。
上述设置所述多个第一过孔结构一一对应分布在对应的一行子像素区所形成的多个像素区中，使得每一条补偿信号线50对应连接的多个第一过孔结构均能够均匀分布。
上述设置方式使得每条补偿信号线50均能够通过均匀分布的多个第一过孔结构与所述第一部分301电连接，从而很好的提升了所述第一信号在所述显示区域10传输的均一性。
更详细地说，上述实施例提供的阵列基板中，示例性的，所述第一电极30采用ITO制作，所述补偿信号线50采用第一栅金属层制作，所述第一栅金属层采用Ti/Al/Ti的金属层叠结构，所述补偿信号线50的方块电阻相对于所述第一电极30降低一个数量级以上。(1,0)，(1,1)，(1,2)，(1,3)，(1,4)点位的第一信号同时通过所述第一电极30和所述补偿信号线50传输，计算该5个点位对应的第一信号输入的阻抗后，得到图9所示的(1,0)，(1,1)，(1,2)，(1,3)，(1,4)点位的第一信号输入的波形示意图，Data_out1～5分别为(1,0)，(1,1)，(1,2)，(1,3)，(1,4)点位对应的显示区域10内的第一信 号。(1,0)，(1,4)点位的Tr均为80ns，(1,1)，(1,2)，(1,3)点位的Tr均为126ns；可见，上述实施例提供的阵列基板中，第一信号传输的Tr和Tf满足了远端波动是近端的2.5倍以下，因此，上述实施例提供的阵列基板，在通过所述补偿信号线50补偿所述第一电极30时，满足了第一信号的传输均一性。
如图10所示，图10中示意了采用所述补偿信号线50补偿前，第一电极30近端和远端产生的RC Loading，以及采用所述补偿信号线50补偿后，第一电极30近端和远端产生的RC Loading。从图中能够确定采用所述补偿信号线50补偿后，第一电极30近端和远端产生的RC Loading明显降低。
如图5所示，在一些实施例中，所述像素区包括第一子像素区201、第二子像素区202和第三子像素区203，所述像素区中的第一过孔结构位于该像素区包括的第一子像素区201中。
示例性的，所述第一子像素区201包括蓝色子像素区，所述第二子像素区202包括红色子像素区，所述第三子像素区203包括绿色子像素区。
示例性的，所述第一子像素区201包括红色子像素区，所述第二子像素区202包括绿色子像素区，所述第三子像素区203包括蓝色子像素区。
示例性的，所述第一子像素区201包括绿色子像素区，所述第二子像素区202包括蓝色子像素区，所述第三子像素区203包括红色子像素区。
上述设置方式使得每个像素区中均设置有补偿信号线50，且在各子像素中，补偿信号线50均能够通过第一过孔结构与所述第一部分301电连接，从而更好的提升了所述第一信号在显示区域10内传输的均一性。
需要说明，图5中仅示意了部分子像素区，实际子像素区会布满整个显示区域10。
如图7所示，在一些实施例中，所述补偿信号线50通过多个第一过孔结构61与所述第一部分301电连接，所述多个第一过孔结构61一一对应分布在对应的一行子像素区所包括的多个子像素区中。
上述设置方式使得每个子像素区中均设置有补偿信号线50，且在各子像素区中，补偿信号线50均能够通过第一过孔结构61与所述第一部分301电连接，从而更好的提升了所述第一信号在显示区域10内传输的均一性。
如图7和图8所示，在一些实施例中，设置所述第一过孔结构61包括：第一过孔611、第二过孔612和第一导电图形613；所述第一导电图形613位于所述补偿信号线50与所述第一部分301之间，所述补偿信号线50通过所述第一过孔611与所述第一导电图形613电连接，所述第一导电图形613通过所述第二过孔612与所述第一部分301电连接。
示例性的，所述第一导电图形613与所述源漏金属层同层同材料设置，所述第一过孔611贯穿所述层间绝缘层ILD，所述补偿信号线50能够通过所述第一过孔611与所述第一导电图形613电连接，所述第二过孔612贯穿所述平坦层PLN，所述第一导电图形613能够通过所述第二过孔612与所述第一部分301电连接。值得注意，图8中还示意了基底91，栅极绝缘层GI和钝化层PVX，所述基底91和所述栅极绝缘层GI之间还可以包括其它膜层，图中未示出。
上述实施例提供的阵列基板中，设置所述补偿信号线50通过所述第一过孔结构与所述第一部分301电连接，不仅保证了所述补偿信号线50与所述第一部分301之间良好的电连接性能，更好的提升了所述阵列基板的工作稳定性；而且，避免了在所述补偿信号线50与所述第一部分301之间形成太深的过孔，从而降低了实现所述补偿信号线50与所述第一部分301电连接的工艺难度。
如图7所示，在一些实施例中，所述补偿信号线50包括第三部分501和第四部分502，沿垂直于所述补偿信号线50的延伸方向，所述第三部分501的宽度大于所述第四部分502的宽度，设置所述第一过孔611在所述阵列基板的基底上的正投影，与所述第三部分501在所述基底上的正投影交叠；和/或，所述第二过孔在所述基底上的正投影，与所述第三部分501在所述基底上的正投影交叠。
具体地，所述补偿信号线50包括一体结构的第三部分501和第四部分502；示例性的，所述第三部分501和所述第四部分502交替设置。
示例性的，所述第一过孔在所述阵列基板的基底上的正投影，位于所述第三部分501在所述基底上的正投影的内部；和/或，所述第二过孔在所述基底上的正投影，位于所述第三部分501在所述基底上的正投影的内部。
上述设置方式能够更好的保证所述补偿信号线50与所述第一部分301之间的连接性能。
在一些实施例中，将所述第一导电图形613与所述数据线72同层同材料设置。
具体地，所述第一导电图形613和所述数据线72均形成在所述层间绝缘层背向所述基底的表面，所述第一导电图形613和所述数据线72均采用Ti/Al/Ti的金属层叠结构。
上述设置方式使得所述第一导电图形613与所述数据线72能够在同一次构图工艺中同时形成，从而有效简化了阵列基板的制作流程，节约了阵列基板的制作成本。
在一些实施例中，所述补偿信号线50的延伸方向与所述栅线71的延伸方向大致相同，所述补偿信号线50与所述栅线71同层同材料设置。
示例性的，所述补偿信号线50与所述栅线71均沿水平方向延伸。
示例性的，多条所述补偿信号线50与多条所述栅线71交替间隔设置。
具体地，所述补偿信号线50和所述栅线71均形成在所述栅极绝缘层背向所述基底的表面，所述补偿信号线50和所述栅线71均采用Ti/Al/Ti的金属层叠结构。
上述设置方式使得所述补偿信号线50和所述栅线71能够在同一次构图工艺中同时形成，无需增加额外的专门用于制作所述补偿信号线50的构图工艺，从而有效简化了阵列基板的制作流程，节约了阵列基板的制作成本。因此，上述实施例提供的阵列基板在包括所述补偿信号线50时，同样能够通过9mask工艺完成制作。
如图7所示，在一些实施例中，所述阵列基板还包括：
多个第二电极70，所述第二电极70一一对应位于所述多个子像素区中，所述第二电极70位于所述第一电极30背向所述阵列基板的基底的一侧；所述第一电极30上设置有与所述多个第二电极70一一对应的多个开口3011；
与所述多个第二电极70一一对应的多个驱动电路，所述驱动电路位于对应的所述第二电极70与所述阵列基板的基底之间，所述驱动电路的驱动信号输出端通过第二过孔结构62与对应的第二电极70电连接；所述第二过孔结 构62包括第三过孔621、第四过孔622和第二导电图形623，所述第二导电图形623位于所述驱动信号输出端与所述第二电极70之间；所述驱动信号输出端通过所述第三过孔621与所述第二导电图形623电连接，所述第二导电图形623通过所述第四过孔622与对应的第二电极70电连接；
所述第四过孔622在所述阵列基板的基底上的正投影，被对应的开口3011在所述基底上的正投影包围。
具体地，所述第二电极70包括像素电极，所述像素电极形成为具有狭缝的结构(即slit结构)。
所述第二电极70和所述驱动电路均与所述子像素区一一对应。所述驱动电路位于对应的所述第二电极70与所述阵列基板的基底之间，所述第二电极70位于所述第一电极30背向所述阵列基板的基底的一侧，所述驱动电路的驱动信号输出端，即晶体管73的输出端采用有源层制作，所述驱动信号输出端与对应的第二电极70之间至少间隔有栅极绝缘层、层间绝缘层、平坦层、第一电极30和钝化层。因此，所述驱动信号输出端若要与对应的第二电极70实现电连接，就需要穿过栅极绝缘层、层间绝缘层、平坦层、第一电极30和钝化层。
所述阵列基板还包括所述第二过孔结构，所述第二过孔结构与所述第二电极70一一对应。所述第二过孔结构包括第三过孔、第四过孔和第二导电图形，所述第二导电图形位于所述驱动信号输出端与所述第二电极70之间。示例性的，所述第二导电图形与所述源漏金属层同层同材料设置，所述第三过孔贯穿所述栅极绝缘层和所述层间绝缘层，使得所述驱动信号输出端能够通过所述第三过孔与所述第二导电图形电连接；所述第四过孔贯穿所述平坦层、所述第一电极30和所述钝化层，使得所述第二导电图形能够通过所述第四过孔与对应的第二电极70电连接。
而且，由于所述第一电极30具有导电性，因此，为了避免所述第二电极70与所述第一电极30短接，可以在所述第一电极30上设置与所述多个第二电极70一一对应的多个开口3011，使得穿过所述第一电极30的第四过孔在基底上的正投影，能够被对应的开口3011在基底上的正投影包围，并使得所述第四过孔的内壁与对应的开口3011的边界之间具有一定的距离。
上述实施例提供的阵列基板中，设置驱动信号输出端通过所述第二过孔结构与对应的第二电极70电连接，保证了所述驱动信号输出端与对应的第二电极70之间良好的电连接性能，更好的提升了所述阵列基板的工作稳定性。
在一些实施例中，所述阵列基板还包括：
多个第二电极70，所述第二电极70一一对应位于所述多个子像素区中，所述第二电极70位于所述第一电极30与所述阵列基板的基底之间；
与所述多个第二电极70一一对应的多个驱动电路，所述驱动电路位于对应的所述第二电极70与所述阵列基板的基底之间，所述驱动电路的驱动信号输出端与对应的第二电极70电连接。
具体地，所述多个第二电极70也可以设置在所述第一电极30与所述阵列基板的基底之间，这样所述驱动信号输出端与对应的第二电极70之间间隔有栅极绝缘层、层间绝缘层和平坦层。因此，所述驱动信号输出端若要与对应的第二电极70实现电连接，仅需要穿过栅极绝缘层、层间绝缘层和平坦层即可，无需在第一电极30上形成开孔。
所述驱动信号输出端可以通过第三过孔结构与对应的第二电极70电连接，示例性的，所述第三过孔结构包括第五过孔、第六过孔和第三导电图形，所述第三导电图形位于所述第五过孔与所述第六过孔之间。示例性的，所述第三导电图形与所述源漏金属层同层同材料设置，所述第五过孔贯穿所述栅极绝缘层和所述层间绝缘层，使得所述驱动信号输出端能够通过所述第五过孔与所述第三导电图形电连接；所述第六过孔贯穿所述平坦层，使得所述第三导电图形能够通过所述第六过孔与对应的第二电极70电连接。
上述实施例提供的阵列基板中，设置驱动信号输出端通过所述第三过孔结构与对应的第二电极70电连接，保证了所述驱动信号输出端与对应的第二电极70之间良好的电连接性能，更好的提升了所述阵列基板的工作稳定性。
如图5和图6所示，在一些实施例中，所述阵列基板还包括设置于所述第一电极30的第一侧的第一信号输入端；
所述第二部分302包围所述第一部分301，所述第二部分302包括第一子部分3021、第二子部分3022和第三子部分3023，沿所述数据线72的延伸方向，所述第二子部分3022位于所述第一子部分3021和所述第三子部分3023 之间；
所述电极连接线包括：
第一电极连接线401，所述第一电极连接线401分别与所述第一子部分3021和所述第一信号输入端电连接；
第二电极连接线402，所述第二电极连接线402分别与所述第二子部分3022和所述第一信号输入端电连接；
第三电极连接线403，所述第三电极连接线403分别与所述第三子部分3023和所述第一信号输入端电连接。
具体地，所述第一信号输入端包括一个或者多个端口。当所述第一信号输入端包括一个端口时，全部所述电极连接线均与该一个端口电连接，接收由该一个端口提供的电信号。当所述第一信号输入端包括多个端口时，所述多个端口均输出相同的第一信号；示例性的，所述第一信号输入端包括多个第一端口，两个第二端口和两个第三端口，所述多个第一端口用于输出所述VCOM0信号，所述两个第二端口用于输出所述VCOM1信号，所述两个第三端口用于输出VCOM2信号。
示例性的，所述第二部分302形成为回字形结构，所述第二部分302可以划分为三个子部分，第一子部分3021位于所述第一侧，所述第一子部分3021包括所述回字形结构位于第一侧的一边，所述第三子部分3023位于所述第一电极30的第二侧，所述第三子部分3023包括所述回字形结构位于第二侧的一边，所述第二子部分3022包括位于所述第一电极30第三侧的一边和位于所述第一电极30第四侧的一边。
上述设置所述电极连接线包括所述第一电极连接线401、所述第二电极连接线402和所述第三电极连接线403，使得所述第一电极30能够在所述第一侧、所述第二侧、以及位于所述第一侧和所述第二侧之间的位置，同时向所述第一电极30写入第一信号，从而进一步改善了所述第一信号在显示区域10传输的均一性。
如图5所示，在一些实施例中，所述电极连接线包括多条所述第一电极连接线401，多条所述第一电极连接线401沿所述栅线71的延伸方向依次排列；
所述电极连接线包括两条第二电极连接线402，一条第二电极连接线402位于所述第一电极30的第三侧，另一条第二电极连接线402位于所述第一电极30的第四侧，所述第三侧和所述第四侧沿所述栅线71的延伸方向相对；
所述第三电极连接线403围绕所述第一电极30的第二侧、第三侧和第四侧，所述第二侧与所述第一侧沿所述数据线72的延伸方向相对，所述第三电极连接线403与所述第三子部分3023沿所述栅线71延伸方向的两端分别电连接。
具体地，所述电极连接线包括多条第一电极连接线401，多条所述第一电极连接线401沿所述栅线71的延伸方向依次排列；所述第一电极连接线401与所述第一端口一一对应，每条所述第一电极连接线401均分别与所述第一子部分3021和对应的所述第一端口电连接。
所述电极连接线包括两条第二电极连接线402，所述两条第二电极连接线402与所述两个第二端口一一对应，一条所述第二电极连接线402分别与对应的第二端口和位于所述第一电极30的第三侧的第二子部分3022电连接，另一条所述第二电极连接线402分别与对应的第二端口和位于所述第一电极30的第四侧的第二子部分3022电连接。示例性的，所述第二电极连接线402可以与所述第二子部分3022的中间部分电连接。
所述第三电极连接线403的两端与所述两个第三端口一一对应电连接，所述第三电极连接线403与所述第三子部分3023沿所述栅线71延伸方向的两端分别电连接；示例性的，所述第三电极连接线403通过两个导电部80与所述第三子部分3023沿所述栅线71延伸方向的两端分别电连接，所述导电部80的延伸方向与所述数据线72的延伸方向相同。示例性的，所述导电部80与所述第三电极连接线340形成为一体结构。
上述实施例提供的阵列基板中，所述第一电极30能够在所述第一侧、所述第二侧、所述第三侧和所述第四侧同时向所述第一电极30写入第一信号，从而进一步改善了所述第一信号在显示区域10传输的均一性。
需要说明，图5中还示意了阵列基板中的静电释放结构ESD，栅极驱动电路GOA，阵列基板的边框线90和feed线81。
本公开实施例还提供了一种显示装置，包括上述实施例提供的阵列基板。
由于上述实施例提供的阵列基板中，通过设置所述多条补偿信号线50与所述第一部分301电连接，降低了所述第一电极30的电阻，从而有效改善了所述第一信号在显示区域10传输延时较大的问题，降低了所述第一信号在开机和关机瞬间的上升时间和下降时间，改善了电容耦合的程度；因此，上述实施例提供的阵列基板在应用于大尺寸、高分辨率的显示产品时，能够很好的保证大尺寸显示产品在不同显示区域10中第一信号的均一性，从而更好的提升显示产品的显示质量。
因此，本公开实施例提供的显示装置在包括上述阵列基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
在一些实施例中，所述显示装置还包括彩膜基板和液晶层，所述彩膜基板与所述阵列基板相对设置，所述液晶层位于所述彩膜基板与所述阵列基板之间。
具体地，所述彩膜基板包括与所述阵列基板中的子像素区一一对应的色阻图形，所述色阻图形在所述阵列基板上的正投影的至少部分位于对应的子像素区中。
所述显示装置为液晶显示装置，所述阵列基板中的第一电极30和第二电极70共同驱动所述液晶层中的液晶发生偏转，从而实现所述显示装置的显示功能。
本公开实施例还提供了一种阵列基板的制作方法，所述阵列基板包括显示区域10和包围所述显示区域10的周边区域；所述制作方法包括：
制作多条栅线71和多条数据线72，所述栅线71与所述数据线72交叉设置，限定出阵列分布的多个子像素区；
制作第一电极30，所述第一电极30包括位于所述显示区域10的第一部分301和位于所述周边区域的第二部分302；
制作电极连接线，所述电极连接线位于所述周边区域，所述电极连接线与所述第二部分302电连接，用于为所述第一电极30提供第一信号；
制作多条补偿信号线50，所述补偿信号线50的至少部分位于所述显示 区域10，所述补偿信号线50与所述第一部分301电连接。
采用本公开实施例提供的制作方法制作的阵列基板中，通过设置所述多条补偿信号线50与所述第一部分301电连接，降低了所述第一电极30的电阻，从而有效改善了所述第一信号在显示区域10传输延时较大的问题，降低了所述第一信号在开机和关机瞬间的上升时间和下降时间，改善了电容耦合的程度；因此，采用本公开实施例提供的制作方法制作的阵列基板在应用于大尺寸、高分辨率的显示产品时，能够很好的保证大尺寸显示产品在不同显示区域10中第一信号的均一性，从而更好的提升显示产品的显示质量。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护 范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，包括：显示区域和围绕所述显示区域的周边区域；所述显示区域设置有多条栅线和多条数据线，所述栅线与所述数据线交叉设置，限定出阵列分布的多个子像素区；所述阵列基板还包括：
    第一电极，所述第一电极包括位于所述显示区域的第一部分和位于所述周边区域的第二部分；
    电极连接线，所述电极连接线位于所述周边区域，所述电极连接线与所述第二部分电连接，用于为所述第一电极提供第一信号；
    多条补偿信号线，所述补偿信号线的至少部分位于所述显示区域，所述补偿信号线与所述第一部分电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述多个子像素区划分为多行子像素区，所述补偿信号线与至少一行子像素区一一对应；
    所述补偿信号线的至少部分位于对应的一行子像素区中，在对应的一行子像素区中，所述补偿信号线通过至少一个第一过孔结构与所述第一部分电连接。
  3. 根据权利要求2所述的阵列基板，其中，每行子像素区均能够形成多个像素区，每个所述像素区包括至少两个相邻的子像素区；
    所述补偿信号线通过多个第一过孔结构与所述第一部分电连接，所述多个第一过孔结构一一对应分布在对应的一行子像素区所形成的所述多个像素区中。
  4. 根据权利要求3所述的阵列基板，其中，所述像素区包括第一子像素区、第二子像素区和第三子像素区，
    所述像素区中的第一过孔结构位于该像素区包括的第一子像素区中。
  5. 根据权利要求2所述的阵列基板，其中，所述第一过孔结构包括：第一过孔、第二过孔和第一导电图形；
    所述第一导电图形位于所述补偿信号线与所述第一部分之间，所述补偿信号线通过所述第一过孔与所述第一导电图形电连接，所述第一导电图形通过所述第二过孔与所述第一部分电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述补偿信号线包括第三部分和第四部分，沿垂直于所述补偿信号线的延伸方向，所述第三部分的宽度大于所述第四部分的宽度，所述第一过孔在所述阵列基板的基底上的正投影，与所述第三部分在所述基底上的正投影交叠；和/或，所述第二过孔在所述基底上的正投影，与所述第三部分在所述基底上的正投影交叠。
  7. 根据权利要求5所述的阵列基板，其中，所述第一导电图形与所述数据线同层同材料设置。
  8. 根据权利要求1所述的阵列基板，其中，所述补偿信号线的延伸方向与所述栅线的延伸方向相同，所述补偿信号线与所述栅线同层同材料设置。
  9. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    多个第二电极，所述第二电极一一对应位于所述多个子像素区中，所述第二电极位于所述第一电极背向所述阵列基板的基底的一侧；所述第一电极上设置有与所述多个第二电极一一对应的多个开口；
    与所述多个第二电极一一对应的多个驱动电路，所述驱动电路位于对应的所述第二电极与所述阵列基板的基底之间，所述驱动电路的驱动信号输出端通过第二过孔结构与对应的第二电极电连接；所述第二过孔结构包括第三过孔、第四过孔和第二导电图形，所述第二导电图形位于所述驱动信号输出端与所述第二电极之间；所述驱动信号输出端通过所述第三过孔与所述第二导电图形电连接，所述第二导电图形通过所述第四过孔与对应的第二电极电连接；
    所述第四过孔在所述阵列基板的基底上的正投影，被对应的开口在所述基底上的正投影包围。
  10. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    多个第二电极，所述第二电极一一对应位于所述多个子像素区中，所述第二电极位于所述第一电极与所述阵列基板的基底之间；
    与所述多个第二电极一一对应的多个驱动电路，所述驱动电路位于对应的所述第二电极与所述阵列基板的基底之间，所述驱动电路的驱动信号输出端与对应的第二电极电连接。
  11. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括设置 于所述第一电极的第一侧的第一信号输入端；
    所述第二部分包围所述第一部分，所述第二部分包括第一子部分、第二子部分和第三子部分，沿所述数据线的延伸方向，所述第二子部分位于所述第一子部分和所述第三子部分之间；
    所述电极连接线包括：
    第一电极连接线，所述第一电极连接线分别与所述第一子部分和所述第一信号输入端电连接；
    第二电极连接线，所述第二电极连接线分别与所述第二子部分和所述第一信号输入端电连接；
    第三电极连接线，所述第三电极连接线分别与所述第三子部分和所述第一信号输入端电连接。
  12. 根据权利要求11所述的阵列基板，其中，所述电极连接线包括多条所述第一电极连接线，多条所述第一电极连接线沿所述栅线的延伸方向依次排列；
    所述电极连接线包括两条第二电极连接线，一条第二电极连接线位于所述第一电极的第三侧，另一条第二电极连接线位于所述第一电极的第四侧，所述第三侧和所述第四侧沿所述栅线的延伸方向相对；
    所述第三电极连接线围绕所述第一电极的第二侧、第三侧和第四侧，所述第二侧与所述第一侧沿所述数据线的延伸方向相对，所述第三电极连接线与所述第三子部分沿所述栅线延伸方向的两端分别电连接。
  13. 一种显示装置，包括如权利要求1～12中任一项所述的阵列基板。
  14. 根据权利要求13所述的显示装置，其中，所述显示装置还包括彩膜基板和液晶层，所述彩膜基板与所述阵列基板相对设置，所述液晶层位于所述彩膜基板与所述阵列基板之间。
  15. 一种阵列基板的制作方法，所述阵列基板包括显示区域和包围所述显示区域的周边区域；所述制作方法包括：
    制作多条栅线和多条数据线，所述栅线与所述数据线交叉设置，限定出阵列分布的多个子像素区；
    制作第一电极，所述第一电极包括位于所述显示区域的第一部分和位于 所述周边区域的第二部分；
    制作电极连接线，所述电极连接线位于所述周边区域，所述电极连接线与所述第二部分电连接，用于为所述第一电极提供第一信号；
    制作多条补偿信号线，所述补偿信号线的至少部分位于所述显示区域，所述补偿信号线与所述第一部分电连接。
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