WO2022082519A1 - 移位寄存器单元、驱动方法、驱动电路及显示装置 - Google Patents

移位寄存器单元、驱动方法、驱动电路及显示装置 Download PDF

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Publication number
WO2022082519A1
WO2022082519A1 PCT/CN2020/122558 CN2020122558W WO2022082519A1 WO 2022082519 A1 WO2022082519 A1 WO 2022082519A1 CN 2020122558 W CN2020122558 W CN 2020122558W WO 2022082519 A1 WO2022082519 A1 WO 2022082519A1
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Prior art keywords
terminal
electrically connected
transistor
node
signal terminal
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PCT/CN2020/122558
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English (en)
French (fr)
Inventor
闫伟
秦文文
山岳
王德帅
王继国
王珍
杨小艳
张寒
张健
张亚东
孙建
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/032,512 priority Critical patent/US11961442B2/en
Priority to CN202080002406.7A priority patent/CN114981871A/zh
Priority to PCT/CN2020/122558 priority patent/WO2022082519A1/zh
Publication of WO2022082519A1 publication Critical patent/WO2022082519A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register unit, a driving method, a driving circuit and a display device.
  • the GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the driving circuit is usually composed of a plurality of cascaded shift registers.
  • the output of the shift register is not stable and can cause abnormal display.
  • control circuit respectively electrically connected to the input signal terminal, the reset signal terminal, the first control signal terminal, the second control signal terminal, the first reference signal terminal, the first node and the second node; and the control circuit is configured according to the input signal terminal, the first control signal terminal, the second control signal terminal, and the first reference signal terminal, adjust the signals of the first node and the second node;
  • a cascade circuit which is respectively electrically connected to the first cascaded clock signal terminal, the first node and the cascaded output terminal; and the cascaded circuit is configured to connect the first cascaded clock signal according to the signal of the first node
  • the signal of the cascaded clock signal terminal is provided to the cascaded output terminal;
  • an output circuit respectively electrically connected to the control clock signal terminal, the first node, the second node, the second reference signal terminal and the driving output terminal; and the output circuit is configured to be based on the signal of the first node , providing the signal of the control clock signal terminal to the driving output terminal, and providing the signal of the second reference signal terminal to the driving output terminal according to the signal of the second node.
  • the output circuit includes: a first transistor and a second transistor;
  • the gate of the first transistor is electrically connected to the first node, the first terminal of the first transistor is electrically connected to the control clock signal terminal, and the second terminal of the first transistor is electrically connected to the driving output terminal electrical connection;
  • the gate of the second transistor is electrically connected to the second node, the first terminal of the second transistor is electrically connected to the second reference signal terminal, and the second terminal of the second transistor is electrically connected to the driver The output terminal is electrically connected.
  • the output circuit further includes: a third transistor and a fourth transistor;
  • the gate of the third transistor is electrically connected to the control signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the third transistor is electrically connected to the driver The output terminal is electrically connected;
  • the gate of the fourth transistor is electrically connected to the regulation signal terminal, the first terminal of the fourth transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the fourth transistor is electrically connected to the second terminal of the fourth transistor.
  • the drive output terminal is electrically connected.
  • the cascade circuit includes: a fifth transistor and a storage capacitor
  • the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the first cascaded clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the first node.
  • the cascaded output terminals are electrically connected;
  • the first terminal of the storage capacitor is electrically connected to the first node, and the storage capacitor is electrically connected to the cascaded output terminal.
  • the shift register unit further includes: a sixth transistor
  • the gate of the sixth transistor is electrically connected to the driving output terminal, the first terminal of the sixth transistor is electrically connected to the first reference signal terminal, and the second terminal of the sixth transistor is electrically connected to the first reference signal terminal.
  • the two nodes are electrically connected.
  • control circuit includes:
  • an input circuit which is respectively electrically connected to the input signal terminal, the first control signal terminal and the intermediate node; and the input circuit is configured to convert the first control signal under the control of the signal of the input signal terminal
  • the signal of the terminal is provided to the intermediate node;
  • a reset circuit which is respectively electrically connected to the reset signal terminal, the second control signal terminal and the intermediate node; and the reset circuit is configured to, under the control of the signal of the reset signal terminal, reset the second control signal terminal The signal of the control signal terminal is provided to the intermediate node;
  • a node adjustment circuit respectively electrically connected to the first reference signal terminal, the second cascaded clock signal terminal, the second node and the intermediate node; and the node adjustment circuit is configured to be connected to the intermediate node
  • the signal of the first reference signal terminal is provided to the second node under the control of the signal; the signal of the first reference signal terminal is provided under the control of the second cascaded clock signal terminal and the signal of the second node. a signal is provided to the intermediate node;
  • a stabilization circuit which is respectively electrically connected to the intermediate node, the first node and the regulation signal terminal; and the stabilization circuit is configured to connect the intermediate node to the first regulation signal terminal under the control of the signal of the regulation signal terminal The node is turned on.
  • the input circuit includes: a seventh transistor
  • the gate of the seventh transistor is electrically connected to the input signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the middle Nodes are electrically connected.
  • the reset circuit includes: an eighth transistor;
  • the gate of the eighth transistor is electrically connected to the reset signal terminal, the first terminal of the eighth transistor is electrically connected to the second control signal terminal, and the second terminal of the eighth transistor is electrically connected to the middle Nodes are electrically connected.
  • the node adjustment circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a stabilization capacitor;
  • the gate of the ninth transistor is electrically connected to the intermediate node, the first terminal of the ninth transistor is electrically connected to the first reference signal terminal, and the second terminal of the ninth transistor is electrically connected to the second terminal Node electrical connection;
  • the gate and first terminal of the tenth transistor are both electrically connected to the second cascaded clock signal terminal, and the second terminal of the tenth transistor is electrically connected to the second node;
  • the gate of the eleventh transistor is electrically connected to the second node, the first terminal of the eleventh transistor is electrically connected to the first reference signal terminal, and the second terminal of the eleventh transistor is electrically connected to the first reference signal terminal.
  • the intermediate node is electrically connected;
  • the first end of the stabilization capacitor is electrically connected to the second node, and the second end of the stabilization capacitor is electrically connected to the first reference signal end.
  • the stabilization circuit includes: a twelfth transistor
  • the gate of the twelfth transistor is electrically connected to the control signal terminal, the first terminal of the twelfth transistor is electrically connected to the intermediate node, and the second terminal of the twelfth transistor is electrically connected to the A node is electrically connected.
  • the shift register unit further includes: a thirteenth transistor and a fourteenth transistor;
  • the gate of the thirteenth transistor is electrically connected to the frame reset signal terminal, the first terminal of the thirteenth transistor is electrically connected to the first reference signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the middle Node electrical connection;
  • the gate of the fourteenth transistor is electrically connected to the touch control terminal, the first terminal of the fourteenth transistor is electrically connected to the second reference signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the second reference signal terminal.
  • the drive output terminal is electrically connected.
  • the driving circuit provided by the embodiment of the present disclosure includes: a plurality of the above-mentioned shift register units in cascade;
  • the input signal terminal of the first-stage shift register unit is electrically connected to the frame trigger signal terminal;
  • the input signal terminal of the next-stage shift register unit is electrically connected to the cascaded output terminal of the previous-stage shift register unit, and the reset signal terminal of the previous-stage shift register unit is electrically connected. It is electrically connected to the cascade output terminal of the next stage shift register unit.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned driving circuit.
  • the display device further includes: a plurality of gate lines; one of the gate lines is electrically connected to a driving output terminal of one of the shift register units in the driving circuit.
  • the display device further includes: a plurality of gate lines and gate scanning circuits;
  • the driving circuit is electrically connected to the gate lines separated by one gate line, and the gate scanning circuit is electrically connected to the remaining gate lines.
  • FIG. 1 is a schematic diagram of some structures of a shift register provided by an embodiment of the present disclosure
  • FIG. 2 is another schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of some specific structures of a shift register provided by an embodiment of the present disclosure.
  • FIG. 4 provides some signal timing diagrams according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a driving circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of some structures of a display device according to an embodiment of the present disclosure.
  • FIG. 8 is another schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 9 is further schematic structural diagrams of the display device provided by the embodiments of the present disclosure.
  • FIG. 10 is another schematic structural diagram of the display device provided by the embodiments of the present disclosure.
  • the shift register unit provided by the embodiment of the present invention, as shown in FIG. 1 may include:
  • the control circuit 10 is respectively electrically connected to the input signal terminal INP, the reset signal terminal RST, the first control signal terminal CN1, the second control signal terminal CN2, the first reference signal terminal VREF1, the first node N1 and the second node N2; and The control circuit 10 is configured to adjust the signals of the first node N1 and the second node N2 according to the input signal terminal INP, the first control signal terminal CN1, the second control signal terminal CN2, and the first reference signal terminal VREF1;
  • the cascade circuit 20 is electrically connected to the first cascade clock signal terminal GCK1, the first node N1 and the cascade output terminal GO respectively; and the cascade circuit 20 is configured to connect the first cascade connection according to the signal of the first node N1
  • the signal of the clock signal terminal GCK1 is provided to the cascade output terminal GO;
  • the output circuit 30 is respectively electrically connected to the control clock signal terminal CCK, the first node N1, the second node N2, the second reference signal terminal VREF2 and the driving output terminal SO; and the output circuit 30 is configured to be based on the signal of the first node N1 , the signal of the control clock signal terminal CCK is provided to the driving output terminal SO, and the signal of the second reference signal terminal VREF2 is provided to the driving output terminal SO according to the signal of the second node N2.
  • control circuit 10 when implemented, as shown in FIG. 2 , the control circuit 10 may include:
  • the input circuit 11 is electrically connected to the input signal terminal INP, the first control signal terminal CN1 and the intermediate node N0 respectively; and the input circuit 11 is configured to be controlled by the signal of the input signal terminal INP, the first control signal terminal CN1 The signal is provided to the intermediate node N0;
  • the reset circuit 12 is electrically connected to the reset signal terminal RST, the second control signal terminal CN2 and the intermediate node N0 respectively; and the reset circuit 12 is configured to be under the control of the signal of the reset signal terminal RST, the second control signal terminal CN2 The signal is provided to the intermediate node N0;
  • the node adjustment circuit 13 is respectively electrically connected to the first reference signal terminal VREF1, the second cascaded clock signal terminal, the second node N2 and the intermediate node N0; and the node adjustment circuit 13 is configured to be under the control of the signal of the intermediate node N0
  • the signal of the first reference signal terminal VREF1 is provided to the second node N2; the signal of the first reference signal terminal VREF1 is provided to the intermediate node N0 under the control of the second cascaded clock signal terminal and the signal of the second node N2;
  • the stabilization circuit 14 is electrically connected to the intermediate node N0, the first node N1 and the regulation signal terminal VC respectively; and the stabilization circuit 14 is configured to conduct the intermediate node N0 and the first node N1 under the control of the signal of the regulation signal terminal VC .
  • the input circuit 11 may include: a seventh transistor M7;
  • the gate of the seventh transistor M7 is electrically connected to the input signal terminal INP, the first terminal of the seventh transistor M7 is electrically connected to the first control signal terminal CN1, and the second terminal of the seventh transistor M7 is electrically connected to the intermediate node N0.
  • the reset circuit 12 may include: an eighth transistor M8;
  • the gate of the eighth transistor M8 is electrically connected to the reset signal terminal RST, the first terminal of the eighth transistor M8 is electrically connected to the second control signal terminal CN2, and the second terminal of the eighth transistor M8 is electrically connected to the intermediate node N0.
  • the node adjustment circuit 13 may include: a ninth transistor M9 and a tenth transistor M10;
  • the gate of the ninth transistor M9 is electrically connected to the intermediate node N0, the first end of the ninth transistor M9 is electrically connected to the first reference signal terminal VREF1, and the second end of the ninth transistor M9 is electrically connected to the second node N2;
  • the gate and the first terminal of the tenth transistor M10 are both electrically connected to the second cascaded clock signal terminal, and the second terminal of the tenth transistor M10 is electrically connected to the second node N2;
  • the gate of the eleventh transistor M11 is electrically connected to the second node N2, the first terminal of the eleventh transistor M11 is electrically connected to the first reference signal terminal VREF1, and the second terminal of the eleventh transistor M11 is electrically connected to the intermediate node N0 .
  • the stabilization circuit 14 may include: a twelfth transistor M12;
  • the gate of the twelfth transistor M12 is electrically connected to the regulation signal terminal VC, the first end of the twelfth transistor M12 is electrically connected to the intermediate node N0, and the second end of the twelfth transistor M12 is electrically connected to the first node N1.
  • the output circuit 30 may include: a first transistor M1 and a second transistor M2;
  • the gate of the first transistor M1 is electrically connected to the first node N1, the first terminal of the first transistor M1 is electrically connected to the control clock signal terminal CCK, and the second terminal of the first transistor M1 is electrically connected to the driving output terminal SO;
  • the gate of the second transistor M2 is electrically connected to the second node N2, the first terminal of the second transistor M2 is electrically connected to the second reference signal terminal VREF2, and the second terminal of the second transistor M2 is electrically connected to the driving output terminal SO.
  • the cascade circuit 20 includes: a fifth transistor M5 and a storage capacitor;
  • the gate of the fifth transistor M5 is electrically connected to the first node N1, the first terminal of the fifth transistor M5 is electrically connected to the first cascaded clock signal terminal GCK1, and the second terminal of the fifth transistor M5 is electrically connected to the cascaded output terminal GO. connect;
  • the first end of the storage capacitor is electrically connected to the first node N1, and the storage capacitor is electrically connected to the cascaded output terminal GO.
  • the first end of the transistor can be used as its source electrode, and the second end can be used as its drain electrode; No specific distinction is made here.
  • the transistor mentioned in the above embodiments of the present disclosure may be a TFT or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor, MOS), which is not limited herein.
  • MOS Metal Oxide Semiconductor
  • all transistors may be N-type transistors.
  • the N-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th .
  • the twelfth transistor M12 can be an N-type transistor, then the relationship between the voltage difference V gs1 between the gate and the source of the twelfth transistor M12 and its threshold voltage V th1 satisfies the formula: V gs1 >V th1 turn on.
  • the transistors are N-type transistors as an example for description.
  • the design principle is the same as that of the present disclosure, and also falls within the protection scope of the present disclosure.
  • the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the twelfth transistor M12 may be a P-type transistor, and the relationship between the voltage difference V gs1 between the gate and the source of the twelfth transistor M12 and its threshold voltage V th1 satisfies the formula: when V gs1 ⁇ V th1 Pass.
  • the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
  • the N-type transistor is turned on under the action of a high-level signal, and turned off under the action of a low-level signal.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • 1 and 0 are logic levels, which are only for better explanation of the specific working process of the embodiments of the present disclosure, and Not the voltage applied to the gate of each transistor in the implementation.
  • the signal timing diagram shown in FIG. 4 is only a working process of a certain shift register unit in one display frame.
  • the operation process of the shift register unit in other display frames is basically the same as the operation process in the display frame, which is not repeated here.
  • the signal of the first reference signal terminal VREF1 is a low-level signal
  • the signal of the second reference signal terminal VREF2 is a high-level signal
  • the regulation signal terminal VC is a high-level signal.
  • the signal of the first control signal terminal CN1 is a high-level signal
  • the signal of the second control signal terminal CN2 is a low-level signal.
  • the seventh transistor M7 is turned on to provide the signal of the first control signal terminal CN1 to the intermediate node N0, so that the intermediate node N0 is a high-level signal, so that the ninth transistor M9 can be controlled to be turned on.
  • the turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low level signal, so that the eleventh transistor M11 and the second transistor M2 can be controlled deadline.
  • the twelfth transistor M12 is turned on under the control of the high-level signal of the regulation signal terminal VC, so as to turn on the intermediate node N0 and the first node N1, so that the signal of the first node N1 is a high-level signal, thereby controlling the first node N1.
  • a transistor M1 and a fifth transistor M5 are turned on.
  • the turned-on first transistor M1 provides the high-level signal of the control clock signal terminal CCK to the driving output terminal SO, so that the driving output terminal SO outputs a high-level signal.
  • the turned-on fifth transistor M5 provides the low-level signal of the first cascaded clock signal terminal GCK1 to the cascaded output terminal GO, so that the cascaded output terminal GO outputs a low-level signal.
  • the turned-on first transistor M1 provides the high-level signal of the control clock signal terminal CCK to the driving output terminal SO, so that the driving output terminal SO outputs a high-level signal.
  • the turned-on fifth transistor M5 provides the low-level signal of the first cascaded clock signal terminal GCK1 to the cascaded output terminal GO, so that the cascaded output terminal GO outputs a low-level signal.
  • the intermediate node N0 is a high level signal, so that the ninth transistor M9 can be controlled to be turned on.
  • the turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low level signal, so that the eleventh transistor M11 and the second transistor M2 can be controlled deadline.
  • the turned-on fifth transistor M5 provides the high-level signal of the first cascaded clock signal terminal GCK1 to the cascaded output terminal GO, so that the cascaded output terminal GO outputs a high-level signal. Due to the effect of the storage capacitor, the level of the first node N1 can be further pulled up, so that the first transistor M1 and the fifth transistor M5 can be turned on as completely as possible.
  • the turned-on first transistor M1 provides the low-level signal of the control clock signal terminal CCK to the driving output terminal SO, so that the driving output terminal SO outputs a low-level signal.
  • the turned-on fifth transistor M5 provides the high-level signal of the first cascaded clock signal terminal GCK1 to the cascaded output terminal GO, so that the cascaded output terminal GO outputs a high-level signal. Since the signal of the first node N1 is further pulled high, the twelfth transistor M12 is turned off. In addition, the intermediate node N0 is a high level signal, so that the ninth transistor M9 can be controlled to be turned on.
  • the turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low level signal, so that the eleventh transistor M11 and the second transistor M2 can be controlled deadline.
  • the turned-on fifth transistor M5 provides the low-level signal of the first cascaded clock signal terminal GCK1 to the cascaded output terminal GO, so that the cascaded output terminal GO outputs a low-level signal.
  • the turned-on first transistor M1 provides the high-level signal of the control clock signal terminal CCK to the driving output terminal SO, so that the driving output terminal SO outputs a high-level signal.
  • the intermediate node N0 is a high level signal, so that the ninth transistor M9 can be controlled to be turned on.
  • the turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low level signal, so that the eleventh transistor M11 and the second transistor M2 can be controlled deadline.
  • the drive output terminal SO maintains a high-level signal output
  • the cascade output terminal GO maintains a low-level signal output.
  • the transistor M11 and the second transistor M2 are turned on.
  • the turned-on eleventh transistor M11 provides the low-level signal of the first reference signal terminal VREF1 to the intermediate node N0, so that the signal of the intermediate node N0 is a low-level signal, and the first transistor M1 and the fifth transistor M5 are turned off.
  • the turned-on second transistor M2 provides the high-level signal of the second reference signal terminal VREF2 to the driving output terminal SO, so that the driving output terminal SO outputs a high-level signal.
  • the cascade output terminal GO keeps a low level signal output.
  • Embodiments of the present disclosure further provide some shift register units, the schematic structural diagram of which is shown in FIG. 5 , which is modified from the implementations in the foregoing embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the output circuit 30 may further include: a third transistor M3 and a fourth transistor M4; wherein, the gate of the third transistor M3 is electrically connected to the regulation signal terminal VC, The first end of the third transistor M3 is electrically connected to the second end of the first transistor M1, the second end of the third transistor M3 is electrically connected to the driving output end SO; the gate of the fourth transistor M4 is electrically connected to the regulation signal end VC , the first end of the fourth transistor M4 is electrically connected to the second end of the second transistor M2, and the second end of the fourth transistor M4 is electrically connected to the driving output end SO.
  • the first transistor M1 when the driving output terminal SO is outputting, the first transistor M1 may couple out a noise voltage through the first node N1, and the noise voltage is superimposed on the driving output terminal SO, which may affect the driving output terminal SO.
  • the third transistor M3 in the shift register unit provided by the embodiment of the present invention, the noise voltage coupled out by the first transistor M1 due to the first node N1 can be eliminated, and the output stability of the driving output terminal SO can be improved.
  • the second transistor M2 may couple out a noise voltage through the second node N2, and the noise voltage is superimposed on the driving output terminal SO, which may affect the driving output terminal SO.
  • the fourth transistor M4 in the shift register unit provided in the embodiment of the present invention, the noise voltage coupled out by the second transistor M2 due to the second node N2 can be eliminated, and the output stability of the driving output end SO can be improved.
  • the shift register unit may further include: a sixth transistor M6; wherein the gate of the sixth transistor M6 is electrically connected to the driving output terminal SO, and the sixth transistor M6 The first terminal of the transistor M6 is electrically connected to the first reference signal terminal VREF1, and the second terminal of the sixth transistor M6 is electrically connected to the second node N2.
  • the sixth transistor M6 may be a P-type transistor.
  • the sixth transistor M6 it can be turned on when the signal of the driving output terminal SO is a low-level signal, so as to provide the low-level signal of the first reference signal terminal VREF1 to the second node N2, and further make the second node The signal of N2 is stable as a low level signal.
  • the shift register unit may further include: a thirteenth transistor M13 and a fourteenth transistor M14 ; wherein the gate of the thirteenth transistor M13 is related to the frame reset signal
  • the terminal RST is electrically connected, the first terminal of the thirteenth transistor M13 is electrically connected to the first reference signal terminal VREF1, the second terminal of the thirteenth transistor M13 is electrically connected to the intermediate node N0; the gate of the fourteenth transistor M14 is electrically connected to the contact
  • the control terminal is electrically connected, the first terminal of the fourteenth transistor M14 is electrically connected to the second reference signal terminal VREF2, and the second terminal of the fourteenth transistor M14 is electrically connected to the driving output terminal SO.
  • a blanking time (Blacking Time) is set between two adjacent display frames, and the thirteenth transistor M13 can be controlled to be turned on by the frame reset signal terminal RST during the blanking time, so as to make the intermediate node N0
  • the signal is stabilized to a low level signal, thereby improving the output stability of the shift register unit.
  • the fourteenth transistor M14 can be controlled to be turned off through the touch control terminal.
  • the fourteenth transistor M14 can be controlled to be turned on through the touch control terminal, so as to provide the high-level signal of the second reference signal terminal VREF2 to the driving output terminal SO, so that the driving output terminal SO outputs a high level level signal.
  • the sixth transistor M6 may be a P-type transistor, and the remaining transistors may be N-type transistors, which are not limited herein.
  • the driving circuit provided in the embodiment of the present invention may include: a plurality of shift register units in cascade: for example, shift register units SR(1), SR(2)...SR(n-1), SR(n)...SR(N-1), SR(N) (N shift register units in total, 1 ⁇ n ⁇ N, n is an integer);
  • the input signal terminal INP of the first-stage shift register unit SR(1) is electrically connected to the frame trigger signal terminal;
  • the input signal terminal INP of the next-stage shift register unit SR(n) is electrically connected to the cascaded output terminal GO of the previous-stage shift register unit SR(n-1)
  • the reset signal terminal RST of the shift register unit SR(n-1) of the previous stage is electrically connected to the cascade output terminal GO of the shift register unit SR(n) of the next stage.
  • each shift register unit in the above-mentioned driving circuit is the same in function and structure as the above-mentioned shift register unit of the present disclosure, and the repetition will not be repeated.
  • the driving circuit may be configured as a liquid crystal display device, or may be configured as an electroluminescence display device, which is not limited herein.
  • the first reference signal terminals VREF1VREF1 of the shift register units SR(n) of all levels are all coupled to the same DC signal terminal vss, and the shift register units SR(n) of all levels are coupled to the same DC signal terminal vss.
  • the second reference signal terminals VREF2 and VREF2 of n) are all coupled to the same DC signal terminal vdd.
  • the first cascaded clock signal terminal GCK1GCK1 of the 2k-1st stage shift register unit is coupled to the same clock terminal, that is, the first clock terminal gck1 catch.
  • the second cascaded clock signal terminal GCK2 of the 2k-1 stage shift register unit is coupled to the same clock terminal, that is, the second clock terminal gck2.
  • the first cascaded clock signal terminal GCK1GCK1 of the 2k-stage shift register is coupled to the same clock terminal, that is, the fourth clock terminal gck4.
  • the second cascaded clock signal terminal GCK2 of the 2k-stage shift register is coupled to the same clock terminal, that is, the third clock terminal gck3.
  • k is a positive integer.
  • control clock signal terminal CCK of the 2k-1st stage shift register unit is all electrically connected to the cck1 terminal, and the 2kth stage shift register unit is electrically connected to the cck1 terminal.
  • the control clock signal terminals CCK of both are electrically connected to the cck2 terminal.
  • Embodiments of the present disclosure also provide a display device including the above-mentioned driving circuit.
  • the principle of solving the problem of the display device is similar to that of the aforementioned shift register unit, so the implementation of the display device can refer to the implementation of the aforementioned shift register unit, and the repetition will not be repeated here.
  • the display device may include a plurality of pixel units, a plurality of gate lines and data lines, and each pixel unit may include a plurality of sub-pixels, such as red sub-pixels, green sub-pixels and blue sub-pixels.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited herein.
  • one row of sub-pixels spx is electrically connected to one gate line GA
  • one column of sub-pixels spx is electrically connected to one data line DA.
  • the sub-pixel spx may include a scan transistor N00 and a pixel electrode 200 .
  • the gate of the scan transistor N00 may be electrically connected to the gate line GA
  • the source of the scan transistor N00 may be electrically connected to the data line DA
  • the drain of the scan transistor N00 may be electrically connected to the pixel electrode 200 .
  • one gate line GA is electrically connected to the driving output terminal SOSO of one shift register unit in the driving circuit.
  • the above-mentioned driving circuit can be used as a gate driving circuit to be applied to provide a gate scanning signal of the scanning transistor N00.
  • the scan transistor N00 may be a P-type transistor, which is turned on under the control of the low-level signal transmitted on the gate line and turned off under the control of the high-level signal transmitted on the gate line.
  • the scan transistor N00 may also be an N-type transistor, which is turned on under the control of a high-level signal transmitted on the gate line and turned off under the control of a low-level signal transmitted on the gate line.
  • the display device may further include a gate scanning circuit, wherein the driving circuit is electrically connected to the gate lines separated by one gate line, and the gate scanning circuit is electrically connected to the remaining gate lines.
  • the display device may include a plurality of gate lines GA-1, GA-2, GA-3, GA-4, ... GA-2m, ... GA-2M, and one row of sub-pixels is electrically connected a grid line.
  • m and M are integers, 1 ⁇ m ⁇ M).
  • the transistors N01 in the sub-pixels electrically connected to the odd-numbered row gate lines such as: GA-1, GA-3, ...
  • GA-2m-1, ... GA-2M-11 are P-type transistors, and the even-numbered row gate lines ( For example: GA-2, GA-3, ... GA-2m, ... GA-2M)
  • the transistors N02 in the sub-pixels that are electrically connected are N-type transistors.
  • the odd-numbered row gate lines (such as: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11) can be electrically connected with the driving circuit, and one shift register unit in the driving circuit
  • the drive output terminal SO is electrically connected to one of the odd-numbered row gate lines (eg: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11).
  • Even-numbered row gate lines eg: GA-2, GA-3, ... GA-2m, ...
  • GA-2M can be electrically connected to the gate scanning circuit, and the gate scanning circuit can include a cascade of multiple Shift register, the output terminal of a shift register in the gate scanning circuit can be connected with a gate in the even-numbered row gate lines (eg: GA-2, GA-3, ... GA-2m, ... GA-2M) electrical connection.
  • the gate scanning circuit can include a cascade of multiple Shift register, the output terminal of a shift register in the gate scanning circuit can be connected with a gate in the even-numbered row gate lines (eg: GA-2, GA-3, ... GA-2m, ... GA-2M) electrical connection.
  • the transistor N02 in the sub-pixels electrically connected to the odd-numbered row gate lines (eg: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11) is N.
  • the transistors N02 in the sub-pixels electrically connected to the gate lines of even rows (eg: GA-2, GA-3, ... GA-2m, ... GA-2M) are P-type transistors.
  • the odd-numbered row gate lines (eg: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11) can be electrically connected to the gate scanning circuit, and one of the gate scanning circuits is shifted.
  • the output end of the bit register is electrically connected to one of the grid lines in odd-numbered rows (eg: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11).
  • the even-numbered row gate lines eg: GA-2, GA-3, ... GA-2m, ... GA-2M
  • the SO can be electrically connected to one of the grid lines in the even-numbered rows (eg: GA-2, GA-3, ... GA-2m, ... GA-2M).
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a mobile phone as shown in FIG. 10 .
  • the above-mentioned display device provided by the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.

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Abstract

一种移位寄存器单元、驱动方法、驱动电路及显示装置，其中，移位寄存器单元包括：控制电路（10），被配置为根据输入信号端（INP）、第一控制信号端（CN1）、第二控制信号端（CN2）、第一参考信号端（VREF1），调整第一节点（N1）和第二节点（N2）的信号；级联电路（20），被配置为根据第一节点（N1）的信号，将第一级联时钟信号端（GCK1）的信号提供给级联输出端（GO）；输出电路（30），被配置为根据第一节点（N1）的信号，将控制时钟信号端（CCK）的信号提供给驱动输出端（SO），以及根据第二节点（N2）的信号，将第二参考信号端（VREF2）的信号提供给驱动输出端（SO）。

Description

移位寄存器单元、驱动方法、驱动电路及显示装置 技术领域
本公开涉及显示技术领域，特别涉及移位寄存器单元、驱动方法、驱动电路及显示装置。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)驱动电路集成在显示装置的阵列基板上以形成对显示装置的扫描驱动。其中，驱动电路通常由多个级联的移位寄存器构成。然而，移位寄存器输出不稳定，会导致显示异常。
发明内容
本公开实施例提供的移位寄存器单元，包括：
控制电路，分别与输入信号端、复位信号端、第一控制信号端、第二控制信号端、第一参考信号端、第一节点和第二节点电连接；且所述控制电路被配置为根据所述输入信号端、所述第一控制信号端、所述第二控制信号端、所述第一参考信号端，调整所述第一节点和所述第二节点的信号；
级联电路，分别与第一级联时钟信号端、所述第一节点以及级联输出端电连接；且所述级联电路被配置为根据所述第一节点的信号，将所述第一级联时钟信号端的信号提供给所述级联输出端；
输出电路，分别与控制时钟信号端、所述第一节点、所述第二节点、第二参考信号端以及驱动输出端电连接；且所述输出电路被配置为根据所述第一节点的信号，将所述控制时钟信号端的信号提供给所述驱动输出端，以及根据所述第二节点的信号，将所述第二参考信号端的信号提供给所述驱动输出端。
在一些示例所述输出电路包括：第一晶体管和第二晶体管；
所述第一晶体管的栅极与所述第一节点电连接，所述第一晶体管的第一端与所述控制时钟信号端电连接，所述第一晶体管的第二端与所述驱动输出端电连接；
所述第二晶体管的栅极与所述第二节点电连接，所述第二晶体管的第一端与所述第二参考信号端电连接，所述第二晶体管的第二端与所述驱动输出端电连接。
在一些示例中，所述输出电路还包括：第三晶体管和第四晶体管；
所述第三晶体管的栅极与调控信号端电连接，所述第三晶体管的第一端与所述第一晶体管的第二端电连接，所述第三晶体管的第二端与所述驱动输出端电连接；
所述第四晶体管的栅极与所述调控信号端电连接，所述第四晶体管的第一端与所述第二晶体管的第二端电连接，所述第四晶体管的第二端与所述驱动输出端电连接。
在一些示例中，所述级联电路包括：第五晶体管和存储电容；
所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一端与所述第一级联时钟信号端电连接，所述第五晶体管的第二端与所述级联输出端电连接；
所述存储电容的第一端与所述第一节点电连接，所述存储电容与所述级联输出端电连接。
在一些示例中，所述移位寄存器单元还包括：第六晶体管；
所述第六晶体管的栅极与所述驱动输出端电连接，所述第六晶体管的第一端与所述第一参考信号端电连接，所述第六晶体管的第二端与所述第二节点电连接。
在一些示例中，所述控制电路包括：
输入电路，分别与所述输入信号端、所述第一控制信号端以及中间节点电连接；且所述输入电路被配置为在所述输入信号端的信号的控制下，将所 述第一控制信号端的信号提供给所述中间节点；
复位电路，分别与所述复位信号端、所述第二控制信号端以及所述中间节点电连接；且所述复位电路被配置为在所述复位信号端的信号的控制下，将所述第二控制信号端的信号提供给所述中间节点；
节点调整电路，分别与所述第一参考信号端、第二级联时钟信号端、所述第二节点以及所述中间节点电连接；且所述节点调整电路被配置为在所述中间节点的信号的控制下将所述第一参考信号端的信号提供给所述第二节点；在所述第二级联时钟信号端和所述第二节点的信号的控制下将所述第一参考信号端的信号提供给所述中间节点；
稳定电路，分别与所述中间节点、所述第一节点以及调控信号端电连接；且所述稳定电路被配置为所述调控信号端的信号的控制下，将所述中间节点和所述第一节点导通。
在一些示例中，所述输入电路包括：第七晶体管；
所述第七晶体管的栅极与所述输入信号端电连接，所述第七晶体管的第一端与所述第一控制信号端电连接，所述第七晶体管的第二端与所述中间节点电连接。
在一些示例中，所述复位电路包括：第八晶体管；
所述第八晶体管的栅极与所述复位信号端电连接，所述第八晶体管的第一端与所述第二控制信号端电连接，所述第八晶体管的第二端与所述中间节点电连接。
在一些示例中，所述节点调整电路包括：第九晶体管、第十晶体管、第十一晶体管以及稳定电容；
所述第九晶体管的栅极与所述中间节点电连接，所述第九晶体管的第一端与所述第一参考信号端电连接，所述第九晶体管的第二端与所述第二节点电连接；
所述第十晶体管的栅极和第一端均与所述第二级联时钟信号端电连接，所述第十晶体管的第二端与所述第二节点电连接；
所述第十一晶体管的栅极与所述第二节点电连接，所述第十一晶体管的第一端与所述第一参考信号端电连接，所述第十一晶体管的第二端与所述中间节点电连接；
所述稳定电容的第一端与所述第二节点电连接，所述稳定电容的第二端与所述第一参考信号端电连接。
在一些示例中，所述稳定电路包括：第十二晶体管；
所述第十二晶体管的栅极与所述调控信号端电连接，所述第十二晶体管的第一端与所述中间节点电连接，所述第十二晶体管的第二端与所述第一节点电连接。
在一些示例中，所述移位寄存器单元还包括：第十三晶体管和第十四晶体管；
所述第十三晶体管的栅极与帧复位信号端电连接，所述第十三晶体管的第一端与所述第一参考信号端电连接，所述第十三晶体管的第二端与中间节点电连接；
所述第十四晶体管的栅极与触控控制端电连接，所述第十四晶体管的第一端与所述第二参考信号端电连接，所述第十四晶体管的第二端与所述驱动输出端电连接。
本公开实施例提供的驱动电路，包括：级联的多个上述移位寄存器单元；
第一级移位寄存器单元的输入信号端与帧触发信号端电连接；
每相邻的两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的级联输出端电连接，上一级移位寄存器单元的复位信号端与下一级移位寄存器单元的级联输出端电连接。
本公开实施例提供的显示装置，包括上述驱动电路。
在一些示例中，所述显示装置还包括：多条栅线；一条所述栅线与所述驱动电路中的一个所述移位寄存器单元的驱动输出端电连接。
在一些示例中，所述显示装置还包括：多条栅线和栅极扫描电路；
所述驱动电路与间隔一条栅线的栅线电连接，所述栅极扫描电路与其余 栅线电连接。
附图说明
图1为本公开实施例提供的移位寄存器的一些结构示意图；
图2为本公开实施例提供的移位寄存器的又一些结构示意图；
图3为本公开实施例提供的移位寄存器的一些具体结构示意图；
图4为本公开实施例提供的一些信号时序图；
图5为本公开实施例提供的移位寄存器的又一些具体结构示意图；
图6为本公开实施例提供的驱动电路的结构示意图；
图7为本公开实施例提供的显示装置的一些结构示意图；
图8为本公开实施例提供的显示装置的另一些结构示意图；
图9为本公开实施例提供的显示装置的又一些结构示意图；
图10为本公开实施例提供的显示装置的又一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者 机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本发明内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本发明实施例提供的移位寄存器单元，如图1所示，可以包括：
控制电路10，分别与输入信号端INP、复位信号端RST、第一控制信号端CN1、第二控制信号端CN2、第一参考信号端VREF1、第一节点N1和第二节点N2电连接；且控制电路10被配置为根据输入信号端INP、第一控制信号端CN1、第二控制信号端CN2、第一参考信号端VREF1，调整第一节点N1和第二节点N2的信号；
级联电路20，分别与第一级联时钟信号端GCK1、第一节点N1以及级联输出端GO电连接；且级联电路20被配置为根据第一节点N1的信号，将第一级联时钟信号端GCK1的信号提供给级联输出端GO；
输出电路30，分别与控制时钟信号端CCK、第一节点N1、第二节点N2、第二参考信号端VREF2以及驱动输出端SO电连接；且输出电路30被配置为根据第一节点N1的信号，将控制时钟信号端CCK的信号提供给驱动输出端SO，以及根据第二节点N2的信号，将第二参考信号端VREF2的信号提供给驱动输出端SO。
在一些示例中，在具体实施时，如图2所示，控制电路10可以包括：
输入电路11，分别与输入信号端INP、第一控制信号端CN1以及中间节点N0电连接；且输入电路11被配置为在输入信号端INP的信号的控制下，将第一控制信号端CN1的信号提供给中间节点N0；
复位电路12，分别与复位信号端RST、第二控制信号端CN2以及中间节点N0电连接；且复位电路12被配置为在复位信号端RST的信号的控制下，将第二控制信号端CN2的信号提供给中间节点N0；
节点调整电路13，分别与第一参考信号端VREF1、第二级联时钟信号端、第二节点N2以及中间节点N0电连接；且节点调整电路13被配置为在中间 节点N0的信号的控制下将第一参考信号端VREF1的信号提供给第二节点N2；在第二级联时钟信号端和第二节点N2的信号的控制下将第一参考信号端VREF1的信号提供给中间节点N0；
稳定电路14，分别与中间节点N0、第一节点N1以及调控信号端VC电连接；且稳定电路14被配置为调控信号端VC的信号的控制下，将中间节点N0和第一节点N1导通。
在一些示例中，在具体实施时，如图3所示，输入电路11可以包括：第七晶体管M7；
第七晶体管M7的栅极与输入信号端INP电连接，第七晶体管M7的第一端与第一控制信号端CN1电连接，第七晶体管M7的第二端与中间节点N0电连接。
在一些示例中，在具体实施时，如图3所示，复位电路12可以包括：第八晶体管M8；
第八晶体管M8的栅极与复位信号端RST电连接，第八晶体管M8的第一端与第二控制信号端CN2电连接，第八晶体管M8的第二端与中间节点N0电连接。
在一些示例中，在具体实施时，如图3所示，节点调整电路13可以包括：第九晶体管M9和第十晶体管M10；
第九晶体管M9的栅极与中间节点N0电连接，第九晶体管M9的第一端与第一参考信号端VREF1电连接，第九晶体管M9的第二端与第二节点N2电连接；
第十晶体管M10的栅极和第一端均与第二级联时钟信号端电连接，第十晶体管M10的第二端与第二节点N2电连接；
第十一晶体管M11的栅极与第二节点N2电连接，第十一晶体管M11的第一端与第一参考信号端VREF1电连接，第十一晶体管M11的第二端与中间节点N0电连接。
在一些示例中，在具体实施时，如图3所示，稳定电路14可以包括：第 十二晶体管M12；
第十二晶体管M12的栅极与调控信号端VC电连接，第十二晶体管M12的第一端与中间节点N0电连接，第十二晶体管M12的第二端与第一节点N1电连接。
在一些示例中，在具体实施时，如图3所示，输出电路30可以包括：第一晶体管M1和第二晶体管M2；
第一晶体管M1的栅极与第一节点N1电连接，第一晶体管M1的第一端与控制时钟信号端CCK电连接，第一晶体管M1的第二端与驱动输出端SO电连接；
第二晶体管M2的栅极与第二节点N2电连接，第二晶体管M2的第一端与第二参考信号端VREF2电连接，第二晶体管M2的第二端与驱动输出端SO电连接。
在一些示例中，在具体实施时，如图3所示，级联电路20包括：第五晶体管M5和存储电容；
第五晶体管M5的栅极与第一节点N1电连接，第五晶体管M5的第一端与第一级联时钟信号端GCK1电连接，第五晶体管M5的第二端与级联输出端GO电连接；
存储电容的第一端与第一节点N1电连接，存储电容与级联输出端GO电连接。
在具体实施时，根据信号的流通方向，上述晶体管的第一端可以作为其源极，第二端可以作为其漏极；或者，第一端作为其漏极，第二端作为其源极，在此不作具体区分。
需要说明的是，本公开上述实施例中提到的晶体管可以是TFT，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)，在此不作限定。
为了简化制备工艺，在具体实施时，在本公开实施例中，如图3所示，可以使所有晶体管均为N型晶体管。其中，N型晶体管在其栅极与其源极之 间的电压差V gs与其阈值电压V th满足关系V gs>V th时导通。例如，第十二晶体管M12可以为N型晶体管，则第十二晶体管M12在其栅极与其源极之间的电压差V gs1与其阈值电压V th1之间的关系满足公式：V gs1>V th1时导通。当然，在本公开实施例中，仅是以晶体管为N型晶体管为例进行说明的，对于晶体管为P型晶体管的情况，设计原理与本公开相同，也属于本公开保护的范围。并且，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs<V th时导通。例如第十二晶体管M12可以为P型晶体管，第十二晶体管M12在其栅极与其源极之间的电压差V gs1与其阈值电压V th1之间的关系满足公式：V gs1<V th1时导通。
进一步的，在具体实施时，P型晶体管在高电平信号作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
以上仅是举例说明本公开实施例提供的移位寄存器单元的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
下面以图3所示的移位寄存器单元为例，结合图4所示的信号时序图对本公开实施例提供的上述移位寄存器单元的工作过程作以描述。下述描述中以1表示高电平信号，0表示低电平信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，选取如图4所示的信号时序图中的T1、T2、T3、T4、T5、T6六个阶段。需要说明的是，图4所示的信号时序图仅是某一个移位寄存器单元在一个显示帧中的工作过程。该移位寄存器单元在其他显示帧中的工作过程分别与该显示帧中的工作过程基本相同，在此不作赘述。其中，第一参考信号端VREF1的信号为低电平信号，第二参考信号端VREF2的信号为高电平信号，调控信号端VC为高电平信号。第一控制信号端CN1的信号为高电平信号，第二控制信号端CN2的信号为低电平信号。
在T1阶段，GCK2＝0，GCK1＝0，INP＝1，CCK＝1，RST＝0。
由于INP＝1，因此第七晶体管M7导通，以将第一控制信号端CN1的信号提供给中间节点N0，使中间节点N0为高电平信号，从而可以控制第九晶体管M9导通。导通的第九晶体管M9将第一参考信号端VREF1的信号提供给第二节点N2，以使第二节点N2的信号为低电平信号，从而可以控制第十一晶体管M11、第二晶体管M2截止。第十二晶体管M12在调控信号端VC的高电平信号的控制下导通，以将中间节点N0和第一节点N1导通，使第一节点N1的信号为高电平信号，从而控制第一晶体管M1和第五晶体管M5导通。导通的第一晶体管M1将控制时钟信号端CCK的高电平信号提供给驱动输出端SO，使驱动输出端SO输出高电平信号。导通的第五晶体管M5将第一级联时钟信号端GCK1的低电平信号提供给级联输出端GO，使级联输出端GO输出低电平信号。
在T2阶段，GCK2＝1，GCK1＝0，INP＝0，CCK＝1，RST＝0。
由于INP＝0，因此第七晶体管M7截止。由于存储电容的作用，可以保持第一节点N1的信号为高电平，从而控制第一晶体管M1和第五晶体管M5导通。导通的第一晶体管M1将控制时钟信号端CCK的高电平信号提供给驱动输出端SO，使驱动输出端SO输出高电平信号。导通的第五晶体管M5将第一级联时钟信号端GCK1的低电平信号提供给级联输出端GO，使级联输出端GO输出低电平信号。并且，中间节点N0为高电平信号，从而可以控制第九晶体管M9导通。导通的第九晶体管M9将第一参考信号端VREF1的信号提供给第二节点N2，以使第二节点N2的信号为低电平信号，从而可以控制第十一晶体管M11、第二晶体管M2截止。
在T3阶段，GCK2＝0，GCK1＝1，INP＝0，CCK＝0，RST＝0。
由于INP＝0，因此第七晶体管M7截止。由于存储电容的作用，可以保持第一节点N1的信号为高电平，从而控制第一晶体管M1和第五晶体管M5导通。导通的第五晶体管M5将第一级联时钟信号端GCK1的高电平信号提供给级联输出端GO，使级联输出端GO输出高电平信号。由于存储电容的作用， 可以进一步拉高第一节点N1的电平，从而可以使第一晶体管M1和第五晶体管M5尽可能完全导通。则导通的第一晶体管M1将控制时钟信号端CCK的低电平信号提供给驱动输出端SO，使驱动输出端SO输出低电平信号。导通的第五晶体管M5将第一级联时钟信号端GCK1的高电平信号提供给级联输出端GO，使级联输出端GO输出高电平信号。由于第一节点N1的信号被进一步拉高，因此第十二晶体管M12截止。并且，中间节点N0为高电平信号，从而可以控制第九晶体管M9导通。导通的第九晶体管M9将第一参考信号端VREF1的信号提供给第二节点N2，以使第二节点N2的信号为低电平信号，从而可以控制第十一晶体管M11、第二晶体管M2截止。
在T4阶段，GCK2＝0，GCK1＝0，INP＝0，CCK＝1，RST＝0。
由于INP＝0，因此第七晶体管M7截止。由于存储电容的作用，可以保持第一节点N1的信号为高电平，从而控制第一晶体管M1和第五晶体管M5导通。导通的第五晶体管M5将第一级联时钟信号端GCK1的低电平信号提供给级联输出端GO，使级联输出端GO输出低电平信号。导通的第一晶体管M1将控制时钟信号端CCK的高电平信号提供给驱动输出端SO，使驱动输出端SO输出高电平信号。并且，中间节点N0为高电平信号，从而可以控制第九晶体管M9导通。导通的第九晶体管M9将第一参考信号端VREF1的信号提供给第二节点N2，以使第二节点N2的信号为低电平信号，从而可以控制第十一晶体管M11、第二晶体管M2截止。
在T5阶段，GCK2＝0，GCK1＝0，INP＝0，CCK＝1，RST＝1。
由于INP＝0，因此第七晶体管M7截止。由于RST＝1，因此第八晶体管M8导通，以将第二控制信号端CN2的低电平信号提供给中间节点N0，第十二晶体管M12在调控信号端VC的高电平信号的控制下导通，以将中间节点N0和第一节点N1导通，使第一节点N1的信号为低电平信号，从而控制第一晶体管M1和第五晶体管M5截止。驱动输出端SO保持高电平信号输出，级联输出端GO保持低电平信号输出。
在T6阶段，GCK2＝1，GCK1＝0，INP＝0，CCK＝1，RST＝0。
由于INP＝0，因此第七晶体管M7截止。由于RST＝0，因此第八晶体管M8截止。由于GCK2＝1，因此第十晶体管M10导通，以将第二级联时钟信号端的高电平信号提供给第二节点N2，使第二节点N2的信号为高电平，以控制第十一晶体管M11和第二晶体管M2导通。导通的第十一晶体管M11将第一参考信号端VREF1的低电平信号提供给中间节点N0，使中间节点N0的信号为低电平信号，则第一晶体管M1和第五晶体管M5截止。导通的第二晶体管M2将第二参考信号端VREF2的高电平信号提供给驱动输出端SO，使驱动输出端SO输出高电平信号。并且，级联输出端GO保持低电平信号输出。
本公开实施例又提供了一些移位寄存器单元，其结构示意图如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在一些示例中，在具体实施时，如图5所示，输出电路30还可以包括：第三晶体管M3和第四晶体管M4；其中，第三晶体管M3的栅极与调控信号端VC电连接，第三晶体管M3的第一端与第一晶体管M1的第二端电连接，第三晶体管M3的第二端与驱动输出端SO电连接；第四晶体管M4的栅极与调控信号端VC电连接，第四晶体管M4的第一端与第二晶体管M2的第二端电连接，第四晶体管M4的第二端与驱动输出端SO电连接。
在应用时，驱动输出端SO在输出的时候，第一晶体管M1可能会通过第一节点N1耦合出噪声电压，该噪声电压叠加到驱动输出端SO，可能会对驱动输出端SO造成影响。本发明实施例提供的移位寄存器单元通过设置第三晶体管M3，可以消除第一晶体管M1因第一节点N1耦合出的噪声电压，提高驱动输出端SO的输出稳定性。
在应用时，驱动输出端SO在输出的时候，第二晶体管M2可能会通过第二节点N2耦合出噪声电压，该噪声电压叠加到驱动输出端SO，可能会对驱动输出端SO造成影响。本发明实施例提供的移位寄存器单元通过设置第四晶体管M4，可以消除第二晶体管M2因第二节点N2耦合出的噪声电压，提高驱动输出端SO的输出稳定性。
在一些示例中，在具体实施时，如图5所示，移位寄存器单元还可以包括：第六晶体管M6；其中，第六晶体管M6的栅极与驱动输出端SO电连接，第六晶体管M6的第一端与第一参考信号端VREF1电连接，第六晶体管M6的第二端与第二节点N2电连接。示例性地，第六晶体管M6可以为P型晶体管。并且，通过设置第六晶体管M6可以在驱动输出端SO的信号为低电平信号时导通，以将第一参考信号端VREF1的低电平信号提供给第二节点N2，进一步使第二节点N2的信号稳定为低电平信号。
在一些示例中，在具体实施时，如图5所示，移位寄存器单元还可以包括：第十三晶体管M13和第十四晶体管M14；其中，第十三晶体管M13的栅极与帧复位信号端RST电连接，第十三晶体管M13的第一端与第一参考信号端VREF1电连接，第十三晶体管M13的第二端与中间节点N0电连接；第十四晶体管M14的栅极与触控控制端电连接，第十四晶体管M14的第一端与第二参考信号端VREF2电连接，第十四晶体管M14的第二端与驱动输出端SO电连接。
在实际应用中，相邻的两个显示帧之间会设置消隐时间(Blacking Time)，可以在消隐时间内通过帧复位信号端RST控制第十三晶体管M13导通，以使中间节点N0的信号稳定为低电平信号，从而提高移位寄存器单元的输出稳定性。
在实际应用中，显示装置中不仅能够实现显示功能，还可以实现触控功能。在具体实施时，可以使显示功能和触控功能分时进行，因此，在显示装置实现显示功能时可以通过触控控制端控制第十四晶体管M14截止。在显示装置实现触控功能时可以通过触控控制端控制第十四晶体管M14导通，以将第二参考信号端VREF2的高电平信号提供给驱动输出端SO，使驱动输出端SO输出高电平信号。
需要说明的是，在上述实施例中，可以使第六晶体管M6可以为P型晶体管，其余晶体管为N型晶体管，在此不作限定。
本发明实施例提供的驱动电路，如图6所示，可以包括：级联的多个移 位寄存器单元：例如移位寄存器单元SR(1)、SR(2)…SR(n-1)、SR(n)…SR(N-1)、SR(N)(共N个移位寄存器单元，1≤n≤N，n为整数)；
第一级移位寄存器单元SR(1)的输入信号端INP与帧触发信号端电连接；
每相邻的两级移位寄存器单元中，下一级移位寄存器单元SR(n)的输入信号端INP与上一级移位寄存器单元SR(n-1)的级联输出端GO电连接，上一级移位寄存器单元SR(n-1)的复位信号端RST与下一级移位寄存器单元SR(n)的级联输出端GO电连接。
具体地，上述驱动电路中的每个移位寄存器单元的具体结构与本公开上述移位寄存器单元在功能和结构上均相同，重复之处不再赘述。该驱动电路可以应被配置为液晶显示装置中，也可以应被配置为电致发光显示装置中，在此不作限定。
具体地，在本公开实施例提供的上述驱动电路中，各级移位寄存器单元SR(n)的第一参考信号端VREF1VREF1均与同一直流信号端vss耦接，各级移位寄存器单元SR(n)的第二参考信号端VREF2VREF2均与同一直流信号端vdd耦接。
具体地，在本公开实施例提供的上述驱动电路中，如图6所示，第2k-1级移位寄存器单元的第一级联时钟信号端GCK1GCK1与同一时钟端即第一时钟端gck1耦接。第2k-1级移位寄存器单元的第二级联时钟信号端GCK2与同一时钟端即第二时钟端gck2耦接。第2k级移位寄存器的第一级联时钟信号端GCK1GCK1与同一时钟端即第四时钟端gck4耦接。第2k级移位寄存器的第二级联时钟信号端GCK2与同一时钟端即第三时钟端gck3耦接。其中，k为正整数。
具体地，在本公开实施例提供的上述驱动电路中，如图6所示，第2k-1级移位寄存器单元的控制时钟信号端CCK均与cck1端电连接，第2k级移位寄存器单元的控制时钟信号端CCK均与cck2端电连接。
本公开实施例还提供了显示装置，包括上述驱动电路。该显示装置解决问题的原理与前述移位寄存器单元相似，因此该显示装置的实施可以参见前 述移位寄存器单元的实施，重复之处在此不再赘述。
在具体实施时，显示装置可以包括多个像素单元，多条栅线和数据线，每个像素单元可以包括多个子像素，例如红色子像素、绿色子像素以及蓝色子像素。本公开实施例提供的上述显示装置可以为有机发光显示装置，或者也可以为液晶显示装置，在此不作限定。
在显示装置中，如图7所示，一行子像素spx电连接一条栅线GA，一列子像素spx电连接一条数据线DA。子像素spx可以包括扫描晶体管N00和像素电极200。其中，扫描晶体管N00的栅极可以与栅线GA电连接，扫描晶体管N00的源极与数据线DA电连接，扫描晶体管N00的漏极与像素电极200电连接。并且，一条栅线GA与驱动电路中的一个移位寄存器单元的驱动输出端SOSO电连接。这样可以使移位寄存器单元的驱动输出端SOSO向子像素中的扫描晶体管N00的栅极提供信号，并且使移位寄存器单元的级联输出端GOGO用于为下一级移位寄存器单元传递启动信号。这样在本公开实施例提供的上述显示装置为液晶显示装置时，使上述驱动电路可以作为栅极驱动电路，应用于提供扫描晶体管N00的栅极扫描信号。需要说明的是，扫描晶体管N00可以为P型晶体管，在扫描晶体管N00在栅线上传输的低电平信号的控制下导通，在栅线上传输的高电平信号的控制下截止。或者，扫描晶体管N00也可以为N型晶体管，在扫描晶体管N00在栅线上传输的高电平信号的控制下导通，在栅线上传输的低电平信号的控制下截止。
进一步地，不同的子像素中也可以设置两个不同类型的晶体管。如图8与图9所示，显示装置还可以包括栅极扫描电路，其中，驱动电路与间隔一条栅线的栅线电连接，栅极扫描电路与其余栅线电连接。示例性地，如图8所示，显示装置可以包括多条栅线GA-1、GA-2、GA-3、GA-4……GA-2m、……GA-2M，一行子像素电连接一条栅线。其中，m和M为整数，1≤m≤M)。奇数行栅线(如：GA-1、GA-3、……GA-2m-1、……GA-2M-11)电连接的子像素中的晶体管N01为P型晶体管，偶数行栅线(如：GA-2、GA-3、……GA-2m、……GA-2M)电连接的子像素中的晶体管N02为N型晶体管。可以 使奇数行栅线(如：GA-1、GA-3、……GA-2m-1、……GA-2M-11)与驱动电路电连接，并且驱动电路中的一个移位寄存器单元的驱动输出端SO与奇数行栅线(如：GA-1、GA-3、……GA-2m-1、……GA-2M-11)中一条栅线电连接。可以使偶数行栅线(如：GA-2、GA-3、……GA-2m、……GA-2M)与栅极扫描电路电连接，并且，栅极扫描电路可以包括级联的多个移位寄存器，栅极扫描电路中的一个移位寄存器的输出端可以与偶数行栅线(如：GA-2、GA-3、……GA-2m、……GA-2M)中的一条栅线电连接。
或者，如图9所示，奇数行栅线(如：GA-1、GA-3、……GA-2m-1、……GA-2M-11)电连接的子像素中的晶体管N02为N型晶体管，偶数行栅线(如：GA-2、GA-3、……GA-2m、……GA-2M)电连接的子像素中的晶体管N02为P型晶体管。可以使奇数行栅线(如：GA-1、GA-3、……GA-2m-1、……GA-2M-11)与栅极扫描电路电连接，并且栅极扫描电路中的一个移位寄存器的输出端与奇数行栅线(如：GA-1、GA-3、……GA-2m-1、……GA-2M-11)中一条栅线电连接。可以使偶数行栅线(如：GA-2、GA-3、……GA-2m、……GA-2M)与驱动电路电连接，并且，驱动电路中的一个移位寄存器单元的驱动输出端SO可以与偶数行栅线(如：GA-2、GA-3、……GA-2m、……GA-2M)中的一条栅线电连接。
在具体实施时，本公开实施例提供的上述显示装置可以为如图10所示的手机。当然，本公开实施例提供的上述显示装置也可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变 型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (15)

  1. 一种移位寄存器单元，其中，包括：
    控制电路，分别与输入信号端、复位信号端、第一控制信号端、第二控制信号端、第一参考信号端、第一节点和第二节点电连接；且所述控制电路被配置为根据所述输入信号端、所述第一控制信号端、所述第二控制信号端、所述第一参考信号端，调整所述第一节点和所述第二节点的信号；
    级联电路，分别与第一级联时钟信号端、所述第一节点以及级联输出端电连接；且所述级联电路被配置为根据所述第一节点的信号，将所述第一级联时钟信号端的信号提供给所述级联输出端；
    输出电路，分别与控制时钟信号端、所述第一节点、所述第二节点、第二参考信号端以及驱动输出端电连接；且所述输出电路被配置为根据所述第一节点的信号，将所述控制时钟信号端的信号提供给所述驱动输出端，以及根据所述第二节点的信号，将所述第二参考信号端的信号提供给所述驱动输出端。
  2. 如权利要求1所述的移位寄存器单元，其中，所述输出电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的栅极与所述第一节点电连接，所述第一晶体管的第一端与所述控制时钟信号端电连接，所述第一晶体管的第二端与所述驱动输出端电连接；
    所述第二晶体管的栅极与所述第二节点电连接，所述第二晶体管的第一端与所述第二参考信号端电连接，所述第二晶体管的第二端与所述驱动输出端电连接。
  3. 如权利要求2所述的移位寄存器单元，其中，所述输出电路还包括：第三晶体管和第四晶体管；
    所述第三晶体管的栅极与调控信号端电连接，所述第三晶体管的第一端与所述第一晶体管的第二端电连接，所述第三晶体管的第二端与所述驱动输 出端电连接；
    所述第四晶体管的栅极与所述调控信号端电连接，所述第四晶体管的第一端与所述第二晶体管的第二端电连接，所述第四晶体管的第二端与所述驱动输出端电连接。
  4. 如权利要求1所述的移位寄存器单元，其中，所述级联电路包括：第五晶体管和存储电容；
    所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一端与所述第一级联时钟信号端电连接，所述第五晶体管的第二端与所述级联输出端电连接；
    所述存储电容的第一端与所述第一节点电连接，所述存储电容与所述级联输出端电连接。
  5. 如权利要求1-4任一项所述的移位寄存器单元，其中，所述移位寄存器单元还包括：第六晶体管；
    所述第六晶体管的栅极与所述驱动输出端电连接，所述第六晶体管的第一端与所述第一参考信号端电连接，所述第六晶体管的第二端与所述第二节点电连接。
  6. 如权利要求1-5任一项所述的移位寄存器单元，其中，所述控制电路包括：
    输入电路，分别与所述输入信号端、所述第一控制信号端以及中间节点电连接；且所述输入电路被配置为在所述输入信号端的信号的控制下，将所述第一控制信号端的信号提供给所述中间节点；
    复位电路，分别与所述复位信号端、所述第二控制信号端以及所述中间节点电连接；且所述复位电路被配置为在所述复位信号端的信号的控制下，将所述第二控制信号端的信号提供给所述中间节点；
    节点调整电路，分别与所述第一参考信号端、第二级联时钟信号端、所述第二节点以及所述中间节点电连接；且所述节点调整电路被配置为在所述中间节点的信号的控制下将所述第一参考信号端的信号提供给所述第二节点； 在所述第二级联时钟信号端和所述第二节点的信号的控制下将所述第一参考信号端的信号提供给所述中间节点；
    稳定电路，分别与所述中间节点、所述第一节点以及调控信号端电连接；且所述稳定电路被配置为所述调控信号端的信号的控制下，将所述中间节点和所述第一节点导通。
  7. 如权利要求6所述的移位寄存器单元，其中，所述输入电路包括：第七晶体管；
    所述第七晶体管的栅极与所述输入信号端电连接，所述第七晶体管的第一端与所述第一控制信号端电连接，所述第七晶体管的第二端与所述中间节点电连接。
  8. 如权利要求6所述的移位寄存器单元，其中，所述复位电路包括：第八晶体管；
    所述第八晶体管的栅极与所述复位信号端电连接，所述第八晶体管的第一端与所述第二控制信号端电连接，所述第八晶体管的第二端与所述中间节点电连接。
  9. 如权利要求6所述的移位寄存器单元，其中，所述节点调整电路包括：第九晶体管、第十晶体管、第十一晶体管以及稳定电容；
    所述第九晶体管的栅极与所述中间节点电连接，所述第九晶体管的第一端与所述第一参考信号端电连接，所述第九晶体管的第二端与所述第二节点电连接；
    所述第十晶体管的栅极和第一端均与所述第二级联时钟信号端电连接，所述第十晶体管的第二端与所述第二节点电连接；
    所述第十一晶体管的栅极与所述第二节点电连接，所述第十一晶体管的第一端与所述第一参考信号端电连接，所述第十一晶体管的第二端与所述中间节点电连接；
    所述稳定电容的第一端与所述第二节点电连接，所述稳定电容的第二端与所述第一参考信号端电连接。
  10. 如权利要求6所述的移位寄存器单元，其中，所述稳定电路包括：第十二晶体管；
    所述第十二晶体管的栅极与所述调控信号端电连接，所述第十二晶体管的第一端与所述中间节点电连接，所述第十二晶体管的第二端与所述第一节点电连接。
  11. 如权利要求1-10任一项所述的移位寄存器单元，其中，所述移位寄存器单元还包括：第十三晶体管和第十四晶体管；
    所述第十三晶体管的栅极与帧复位信号端电连接，所述第十三晶体管的第一端与所述第一参考信号端电连接，所述第十三晶体管的第二端与中间节点电连接；
    所述第十四晶体管的栅极与触控控制端电连接，所述第十四晶体管的第一端与所述第二参考信号端电连接，所述第十四晶体管的第二端与所述驱动输出端电连接。
  12. 一种驱动电路，其中，包括：级联的多个如权利要求1-11任一项所述的移位寄存器单元；
    第一级移位寄存器单元的输入信号端与帧触发信号端电连接；
    每相邻的两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的级联输出端电连接，上一级移位寄存器单元的复位信号端与下一级移位寄存器单元的级联输出端电连接。
  13. 一种显示装置，其中，包括如权利要求12所述的驱动电路。
  14. 如权利要求13所述的显示装置，其中，所述显示装置还包括：多条栅线；
    一条所述栅线与所述驱动电路中的一个所述移位寄存器单元的驱动输出端电连接。
  15. 如权利要求13所述的显示装置，其中，所述显示装置还包括：多条栅线和栅极扫描电路；
    所述驱动电路与间隔一条栅线的栅线电连接，所述栅极扫描电路与其余 栅线电连接。
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CN109872699A (zh) * 2019-04-15 2019-06-11 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置
CN111312322A (zh) * 2020-03-12 2020-06-19 深圳市华星光电半导体显示技术有限公司 一种移位寄存器单元、栅极驱动电路以及显示面板
CN111653228A (zh) * 2020-06-17 2020-09-11 京东方科技集团股份有限公司 移位寄存单元的驱动方法、栅极驱动电路和显示装置
CN111710281A (zh) * 2020-07-01 2020-09-25 福州京东方光电科技有限公司 一种移位寄存器、其驱动方法及栅极驱动电路、显示装置

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