WO2022063283A1 - 半导体封装结构及其制造方法和半导体器件 - Google Patents

半导体封装结构及其制造方法和半导体器件 Download PDF

Info

Publication number
WO2022063283A1
WO2022063283A1 PCT/CN2021/120800 CN2021120800W WO2022063283A1 WO 2022063283 A1 WO2022063283 A1 WO 2022063283A1 CN 2021120800 W CN2021120800 W CN 2021120800W WO 2022063283 A1 WO2022063283 A1 WO 2022063283A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
pin
pins
plastic
connecting portion
Prior art date
Application number
PCT/CN2021/120800
Other languages
English (en)
French (fr)
Inventor
乔云飞
吴凡坤
王军鹤
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21871652.0A priority Critical patent/EP4207269A4/en
Publication of WO2022063283A1 publication Critical patent/WO2022063283A1/zh
Priority to US18/190,388 priority patent/US20230238315A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present application relates to the technical field of semiconductor devices, and in particular, to a semiconductor packaging structure, a method for manufacturing the same, and a semiconductor device.
  • the shell-type top-out PIN (pin) packaging structure This type of packaging structure has a short electrical path and small parasitic parameters due to the top-out PIN. It has the advantage of high flexibility of PIN, but the cavity in the shell of this structure is filled with silica gel, the module has poor heat dissipation capacity, high cost, and the pins are prone to kneeling problems during assembly; the other type is plastic package form + pin welding Package structure, this type of package structure has PINs on both sides, which has the advantages of good thermal conductivity, high reliability, and high PIN strength; however, the PINs on both sides lead to long electrical paths, large parasitic parameters, and need to be soldered to the target circuit on the application side board, not removable. In view of this, it is necessary to provide a semiconductor package structure to solve the problem that the existing package structure is difficult to satisfy the requirements of top-out PIN and high heat dissipation performance at the same time.
  • the embodiments of the present application provide a semiconductor packaging structure and a manufacturing method thereof.
  • the semiconductor packaging structure is a top-out PIN packaging structure in a plastic packaging form, which has the advantages of short electrical path, small parasitic parameters, flexible pin position setting, and good
  • the heat dissipation performance is high, and the packaging process is simple, the connection of each component is reliable, and the cost is low.
  • a first aspect of the embodiments of the present application provides a semiconductor packaging structure, comprising: a circuit board, a chip and pins disposed on the circuit board, and a plastic package covering the circuit board, the chip, and the pins body;
  • the pin includes a connecting portion and a pin, one end of the connecting portion is welded on the circuit board, and the other end is flush with the top surface of the plastic package, the connecting portion has a mounting hole, and the pin is arranged In the mounting hole and in interference fit with the connecting part, one end of the pin is exposed on the top surface of the plastic sealing body; the top surface of the plastic sealing body is a polished rough surface; the The end face of the other end is a ground rough surface;
  • the pins include pins
  • the plastic sealing body is provided with mounting holes penetrating from the top surface of the plastic sealing body to the circuit board, the pins are arranged in the mounting holes, and the One end is welded on the circuit board, the other end is exposed on the top surface of the plastic package, the mounting hole is filled with insulating resin, and the insulating resin wraps around the pin.
  • the semiconductor package structure of the embodiment of the present application is a top-out PIN package structure in the form of plastic packaging, which has the advantages of short electrical path and small parasitic parameters, which is conducive to signal transmission, and the position of the pins can be flexibly set according to needs, and the number of pins is the same as The setting density can also be increased as required, and at the same time, the pins are not easily bent and deformed, and there will be no problems of bending, collapse and kneeling.
  • the semiconductor package structure of the present application also has good heat dissipation performance, can form a good heat dissipation channel, can dissipate the heat generated inside the device to the outside in time, has high reliability, and can be applied to high-power semiconductor devices.
  • the semiconductor package structure can be molded into a plastic package, grind the plastic package and the connecting portion to expose the mounting holes, and then install the pins in the mounting holes with an interference fit to achieve a top-out PIN package structure in the form of plastic packaging; or by using a specific After the plastic sealing mold of the structure is injection-molded to form a plastic sealing body with mounting holes, the pins are welded in the mounting holes, and the insulating resin is filled to realize the top-out PIN packaging structure of the plastic sealing shape.
  • the entire packaging process is simple and the cost is controllable.
  • the connecting portion includes a surrounding side wall, and one end of the side wall (ie, the bottom of the side wall) of the connecting portion is welded on the circuit board.
  • a welding portion is formed between the bottom of the side wall and the circuit board.
  • the bottom of the side wall is one end of the connecting portion connected to the circuit board.
  • the thickness of the sidewall of the connecting portion can be set according to the flow requirements of the device. If the flow is larger, the thickness of the sidewall of the connecting portion can be set larger, and if the flow is smaller, the thickness of the sidewall of the connecting portion can be set smaller.
  • the connecting portion includes a base and a surrounding side wall, and the base of the connecting portion is welded on the circuit board. A welding portion is formed between the base and the circuit board.
  • the thickness of the sidewall of the connecting portion can be set according to the flow requirements of the device. If the flow is larger, the thickness of the sidewall of the connecting portion can be set larger, and if the flow is smaller, the thickness of the sidewall of the connecting portion can be set smaller.
  • the connecting portion is made of conductive metal material. Specifically, it can be metals such as copper, silver, and aluminum with excellent electrical conductivity.
  • connection part includes a connection part body and a surface treatment layer disposed on the surface of the connection part body, and the surface treatment layer is an electroplated tin layer, an electroplated nickel layer, an electroless nickel gold layer or an electroless nickel palladium gold layer .
  • the arrangement of the surface treatment layer can improve the soldering performance of the connection part, thereby forming a better connection with the circuit board, and at the same time, the surface treatment layer can also improve the oxidation resistance of the connection part.
  • the length of the pin located in the mounting hole of the connecting portion is greater than or equal to 1/2 of the total length of the pin. In this way, it can be ensured that the length of the interference fit part between the pin and the connecting part is greater than or equal to 1/2 of the total length of the pin, and the connection reliability between the pin and the connecting part is improved.
  • the roughness Ra of the grinding rough surface of the plastic sealing body is greater than 0.1 micrometer; the roughness Ra of the grinding rough surface of the connecting portion is greater than 0.1 micrometer.
  • the insulating resin includes epoxy resin.
  • Epoxy resins have good insulating properties and are readily available.
  • the filling height of the insulating resin is greater than or equal to 1/4 of the length of the pin.
  • the insulating resin has a certain filling height, which can better wrap the pins, thereby effectively ensuring the structural stability of the pins.
  • the pins are made of conductive metal material. Specifically, it can be metals such as copper, silver, and aluminum with excellent electrical conductivity.
  • the pin may include a pin body and a protective layer disposed on the surface of the pin body.
  • the material of the protective layer may be, for example, tin.
  • the pins are straight pins without bending parts.
  • Straight pins have short electrical paths and small parasitic parameters, which are beneficial to signal transmission.
  • the pins are vertical pins, and the pins extend in a direction perpendicular to the surface of the circuit board.
  • the vertical pin electrical path is the shortest and the parasitic parameters are minimized, which is beneficial to signal transmission.
  • the semiconductor package structure includes a plurality of the pins, and the plurality of pins are arranged at intervals.
  • a plurality of the pins are vertical pins.
  • the semiconductor package structure includes a plurality of chips, and the plurality of chips may have different functions.
  • the semiconductor package structure further includes other electronic components arranged on the circuit board.
  • the other electronic components may include, but are not limited to, resistors, capacitors, inductors, thermal sensing elements, and the like.
  • Other electronic components can also be packaged various components.
  • an embodiment of the present application provides a method for manufacturing a semiconductor package structure, including:
  • the connecting seat has a closed mounting hole; or the connecting seat has a mounting hole open to one end, and after the welding, the mounting hole is closed;
  • the circuit board provided with the chip and the connecting part is plastic-sealed with plastic-sealing material to form a plastic-sealed body;
  • the top surface of the plastic sealing body and the connecting seat are ground to expose the mounting holes; after grinding, the connecting seat forms a connecting portion, and the ground end of the connecting portion is connected to the top surface of the plastic sealing body. flush;
  • a pin is installed in the installation hole, and the pin is in an interference fit with the connecting portion; one end of the pin is located in the installation hole, and the other end of the pin is exposed from the installation hole.
  • the manufacturing method of the semiconductor packaging structure provided in the second aspect of the embodiment of the present application can realize the top-out PIN packaging in the form of plastic packaging, and there is no special requirement for the shape of the plastic packaging mold.
  • the semiconductor devices of the structure can be encapsulated, so the plastic encapsulation mold can be reused, which can greatly reduce the encapsulation cost.
  • the packaging method is also not limited by the product thickness, and can be applied to product packaging of different thicknesses, and can be used to package products with a larger thickness greater than 5 mm. When multiple pins need to be set, the method has no special requirements on the flatness of the multiple connection bases, and the multiple connection bases are allowed to have a certain height difference, so the packaging method has high practicability.
  • embodiments of the present application provide a method for manufacturing a semiconductor package structure, including:
  • the circuit board on which the chip is fixed is encapsulated by a plastic encapsulation mold and a plastic encapsulation material to form a plastic encapsulation body; wherein, the plastic encapsulation mold includes a matching first mold and a second mold, and the first mold corresponds to the predetermined pin.
  • the position is provided with a protruding structure; after the plastic sealing, the plastic sealing body forms a mounting hole penetrating from the top surface of the plastic sealing body to the circuit board at the position of the predetermined pin;
  • Insulating resin is injected into the mounting hole, and after curing, a semiconductor package structure is obtained.
  • the method for manufacturing a semiconductor package structure provided in the third aspect of the embodiment of the present application can realize a top-out PIN package in a plastic package form, and by designing a plastic package mold with a specific shape and structure, mounting holes for mounting pins can be directly injection-molded.
  • the position can be set flexibly, and the pins will not be squeezed by the molding material during the molding process, so that a stable structure can be maintained, and a reliable connection to the circuit board can be achieved by soldering and wrapping with insulating resin.
  • the embodiments of the present application further provide a semiconductor device, including the semiconductor package structure described in the first aspect of the embodiments of the present application.
  • an embodiment of the present application further provides an electronic device, and the electronic device includes the semiconductor device described in the fourth aspect of the embodiment of the present application.
  • the electronic device may be a mobile phone, an ipad, a notebook computer, a desktop computer, a smart wearable device, a display, a server, an instrument, and other devices.
  • the semiconductor package structure provided by the embodiments of the present application is a top-out PIN package structure in the form of plastic packaging, and has the advantages of short electrical paths, small parasitic parameters, high PIN-out flexibility, good thermal conductivity, and high reliability.
  • the semiconductor package structure when the semiconductor package structure is further assembled, it can be assembled by pressure bonding without reflow soldering, which can simplify the assembly process of the semiconductor device and reduce the cost.
  • the packaging process of the semiconductor packaging structure is simple, the connection of each component is reliable, and the cost is low.
  • FIG. 1 is a schematic diagram of a semiconductor packaging structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a semiconductor packaging structure provided by another embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a semiconductor package structure provided by an embodiment of the present application
  • FIG. 4 is a schematic flowchart of a method for manufacturing a semiconductor package structure provided by another embodiment of the present application.
  • an embodiment of the present application provides a semiconductor package structure 100 , including: a circuit board 10 , a chip 20 disposed on one side surface of the circuit board 10 , pins 30 , and a packaged circuit board 10 ,
  • the plastic package 40 of the chip 20 and the pins 30; the plastic package 40 includes a bottom surface and a top surface arranged oppositely, and the bottom surface and the top surface are generally parallel to the surface of the circuit board 10, wherein the top surface is the one where the chip 20 is arranged close to the circuit board 10.
  • One side surface is the side surface above the chip; the bottom surface is the side surface near the circuit board 10 where the chip 20 is not provided, and the pins 30 are exposed on the top surface of the plastic package 40 .
  • the pin 30 includes a connecting portion 31 and a pin 32 .
  • One end of the connecting portion 31 is welded on the circuit board 10 , and the other end (ie, the end away from the circuit board 10 ) is directed away from the circuit board 10 .
  • the direction of the surface of the board 10 extends and is flush with the top surface of the plastic package 40 , the connecting portion 31 has a mounting hole 41 , the pin 32 is arranged in the mounting hole 41 and has an interference fit with the connecting portion 31 , and one end of the pin 32 is exposed
  • the top surface of the plastic sealing body 40; the plastic sealing body 40 is a grindable material, the top surface of the plastic sealing body 40 is a grinding rough surface; the end surface of the other end of the connecting portion 31 is a grinding rough surface.
  • the specific shape and structure of the connecting portion 31 is not limited.
  • the connecting portion 31 has a mounting hole 41 that penetrates up and down, the connecting portion 31 includes a surrounding side wall, the bottom of the side wall of the connecting portion 31 is welded on the circuit board 10 , and the bottom of the side wall and the circuit board 10 are welded.
  • a welded portion 50 is formed (see FIG. 1 ).
  • the bottom of the mounting hole 41 is the circuit board 10 or the soldering portion 50 formed on the circuit board 10 .
  • the top end face of the side wall of the connecting portion 31 is the end face of the other end of the connecting portion 31 , and the top end face of the side wall of the connecting portion 31 is flush with the top surface of the plastic package 40 and is a polished rough surface.
  • the connecting portion 31 includes a base and a surrounding side wall extending upward from the base.
  • the base of the connecting portion 31 is welded on the circuit board 10 , and a welding portion is formed between the base and the circuit board 10 .
  • the bottom of the mounting hole 41 is the base of the connecting portion 31 .
  • the connecting portion 31 is made of conductive metal material.
  • the pin 32 is made of conductive metal material.
  • the material of the connecting portion 31 and the pin 32 may be, but not limited to, metals such as copper, silver, and aluminum with excellent electrical conductivity.
  • the specific shape of the connecting portion 31 is not limited, and its cross-sectional shape may be but not limited to regular shapes such as cylinder, elliptical cylinder, cuboid, and polygon; of course, it may also be irregular.
  • the pin 32 may include a pin body and a protective layer disposed on the surface of the pin body. The material of the protective layer may be, for example, tin.
  • the pins 32 are copper pins with tin-plated surfaces.
  • the pins 32 are flat, and the thickness of the pins 32 can be selected from different specifications as required.
  • the thickness of the pin 32 may be, for example, 0.64 mm or 0.8 mm.
  • the length of the pins 32 exposed from the top surface of the plastic package 40 can be designed as required.
  • the thickness of the sidewall of the connecting portion 31 can be specifically set according to the flow requirement of the semiconductor device. If the flow requirement is larger, the sidewall thickness of the connection portion 31 can be set larger, while the flow requirement is smaller. Then, the thickness of the side wall of the connecting portion 31 can be set to be smaller.
  • the plastic sealing body 40 is a grindable material.
  • the plastic sealing body 40 has the characteristic of being grindable, and the thickness (height) of the plastic sealing body can be reduced by grinding, so that the connecting portion 31 covered by the plastic sealing body is exposed.
  • the connecting portion 31 is made of grindable metal, and the thickness (height) of the connecting portion can be reduced by grinding.
  • the end surface of the other end of the connecting portion 31 and the top surface of the plastic sealing body 40 are both ground rough surfaces, and the end surface of the other end of the connecting portion 31 is flush with the top surface of the plastic sealing body 40 , and the grinding rough surface is It is obtained by grinding, and its roughness is determined by the specification of the tool (such as sandpaper) used for grinding.
  • the roughness Ra of the ground rough surface of the top surface of the plastic package 40 may be greater than 0.1 ⁇ m; in other embodiments, the roughness Ra of the ground rough surface of the top surface of the plastic package 40 may be greater than or equal to 0.2 ⁇ m, for example, 0.2 ⁇ m-0.3 ⁇ m.
  • the roughness Ra of the ground rough surface of the other end face of the connecting portion 31 may be greater than 0.1 ⁇ m; in other embodiments, the roughness Ra of the ground rough face of the other end face of the connecting portion 31 may be greater than 0.1 ⁇ m. or equal to 0.2 ⁇ m, for example, 0.2 ⁇ m-0.3 ⁇ m.
  • the semiconductor packaging structure 100 of the embodiment of the present application when plastic sealing is performed, the pins are not yet installed, and the mounting holes are completely closed. Therefore, when the plastic sealing compound is injected, the pins will not be squeezed and deformed by the plastic sealing compound. In addition, the plastic sealing compound will not enter the mounting hole, and the mounting hole does not need to be degummed during pin installation. Therefore, the semiconductor package structure of the embodiment of the present application not only realizes the reliable connection of the pins, but also keeps the shape and structure of the pins stable, and avoids problems such as bending and kneeling.
  • the connecting portion 31 may be properly surface treated.
  • the connecting portion 31 includes a connecting portion body and a surface treatment layer disposed on the surface of the connecting portion body.
  • the surface treatment layer may be, but not limited to, electroplating. Tin layer, electroplated nickel layer, electroless nickel gold layer or electroless nickel palladium gold layer.
  • the thickness of the surface treatment layer may be 0.03 ⁇ m to 25 ⁇ m. Specifically, in some embodiments, the thickness of the surface treatment layer is 0.1 ⁇ m-20 ⁇ m. In other embodiments, the thickness of the surface treatment layer is 0.5 ⁇ m-15 ⁇ m. In some other embodiments, the thickness of the surface treatment layer is 1 ⁇ m-5 ⁇ m.
  • the setting of the surface treatment layer can improve the soldering performance of the connection part, so as to form a better connection with the circuit board.
  • the surface treatment layer can also improve the oxidation resistance of the connection part, effectively preventing the connection part from being preserved and packaged in a conventional environment. oxidized during the process.
  • the improvement of welding performance and oxidation resistance can be taken into account, without increasing the plating cost of the surface treatment layer.
  • the pins 32 are matched with the mounting holes 41 of the connecting portion 31 .
  • the pin 32 may not be inserted into the bottom of the mounting hole 41 , that is, there is a certain distance or gap between the end of the pin 32 located in the mounting hole 41 and the circuit board 10 or the base of the connecting portion 31 .
  • the pin 32 may also be inserted into the bottom of the mounting hole 41 , that is, one end of the pin 32 located in the mounting hole 41 abuts the circuit board 10 or the soldering portion on the circuit board 10 .
  • the length of the pins 32 in the installation holes 41 is greater than or equal to 1/2 of the total length of the pins 32 . Therefore, the height (ie, length) of the mounting hole 41 needs to be set to be greater than or equal to 1/2 of the total length of the pins 32 . Specifically, in some embodiments of the present application, the length of the pin 32 in the mounting hole 41 is 1/2 of the total length of the pin 32 . In other embodiments of the present application, the length of the pins 32 located in the mounting holes 41 is 2/3 of the total length of the pins 32 .
  • the length of the pin 32 in the mounting hole 41 is 3/4 of the total length of the pin 32 . Understandably, the longer the length of the pins 32 in the mounting holes 41 , the larger the contact surface with the connecting portion 31 through interference fit, so that a more stable and reliable connection can be achieved, and the pins 32 can be effectively prevented from falling off.
  • the pins 30 include pins 32
  • the plastic package 40 is provided with mounting holes 42 penetrating from the top surface of the plastic package 40 to the circuit board 10
  • the pins 32 are provided in the mounting holes In 42
  • one end of the pin 32 is welded on the circuit board 10, forming a welding part 51 with the circuit board 10, and the other end is exposed on the top surface of the plastic package 10,
  • the mounting hole 42 is filled with insulating resin 33
  • the insulating resin 33 is wrapped around pin 32.
  • the pin 32 is made of conductive metal material.
  • the material of the pins 32 may be, but not limited to, metals such as copper, silver, and aluminum with excellent electrical conductivity.
  • the pin 32 may include a pin body and a protective layer disposed on the surface of the pin body.
  • the material of the protective layer may be, for example, tin.
  • the pins 32 are copper pins with tin-plated surfaces.
  • the pins 32 are flat, and the thickness of the pins 32 can be selected from different specifications as required.
  • the thickness of the pin 32 may be, for example, 0.64 mm or 0.8 mm.
  • the length of the pins 32 exposed from the top surface of the plastic package 40 can be designed as required.
  • the mounting holes 42 are filled with insulating resin 33, which can firmly fix the pins 32, prevent the pins 32 from falling off, and protect the pins 32 from being damaged by the outside during subsequent use.
  • the insulating resin 33 includes, but is not limited to, epoxy resin.
  • the insulating resin 33 may be a resin composition composed of one or more epoxy resins. There are many types of epoxy resins and high availability, which is beneficial to control the packaging cost.
  • the epoxy resin used for filling the mounting holes 42 is a liquid epoxy resin.
  • the filling height of the insulating resin 33 may be less than or equal to the height (ie length) of the mounting hole 42 , that is, the upper surface of the insulating resin 33 may be lower than the top surface of the plastic sealing body 40 , or may be the same as that of the plastic sealing body 40 .
  • the top surface of the body 40 is flush.
  • the filling height of the insulating resin 33 in the mounting holes 42 is greater than or equal to 1/4 of the length of the pins .
  • the filling height of the insulating resin 33 is greater than or equal to 1/2 of the length of the pin. In other embodiments of the present application, the filling height of the insulating resin 33 is greater than or equal to 2/3 of the length of the pin. In other embodiments of the present application, the filling height of the insulating resin 33 is greater than or equal to 3/4 of the length of the pin. It can be understood that the higher the filling height of the insulating resin 33 is, the better the pins 32 are wrapped, and a more stable and reliable connection can be achieved, thereby effectively preventing the pins from falling off.
  • the semiconductor package structures 100 provided above in the embodiments of the present application all have a PIN (pin) structure on the top surface.
  • the top surface of the present application has a PIN (pin) structure.
  • the structure has the advantages of short electrical path and small parasitic parameters, which is conducive to signal transmission, and the position of the pins can be flexibly set according to needs. It can match more complex internal circuit design and realize multi-function pin layout.
  • the semiconductor package structure 100 of the embodiment of the present application can ensure that the pins are not easily bent and deformed, and protect the pins from being bent and collapsed.
  • the semiconductor package structure 100 of the embodiment of the present application when the semiconductor package structure 100 is further assembled, it is only necessary to press the entire semiconductor package structure 100 to the target circuit board through the side where the pins are arranged to perform mechanical connection. Reflow soldering is required, which can simplify the assembly process of the semiconductor device and reduce the cost. Moreover, since the pin connection of the present application is stable and reliable, bending deformation is not easy to occur during the crimping process.
  • the semiconductor packaging structure of the present application is packaged with a plastic sealing body.
  • the plastic sealing body has good heat dissipation performance, can form a good heat dissipation channel, can dissipate the heat generated inside the device to the outside in time, and is suitable for high-power semiconductor devices.
  • the pin 30, that is, the pin is a wire drawn from the internal circuit of the integrated circuit for connecting to the peripheral circuit, and the pin constitutes an interface for connecting the chip to the outside.
  • the pins are electrically connected to the circuit board by welding, and the connection surface between the pins and the circuit board is usually small.
  • the welding method can increase the connection strength and avoid the risk of the pins falling off.
  • the specific welding method of the pins is not limited, and can be solder paste welding, solder tab welding or laser welding.
  • the lead 30 is a straight lead without a bent portion.
  • Straight pins have the shortest electrical path and the lowest parasitic parameters, which are beneficial to signal transmission.
  • the pins 30 are vertical pins, that is, the pins 30 extend in a direction perpendicular to the surface of the circuit board 10 .
  • the pin includes a connection seat and a pin
  • the side wall of the connection seat is perpendicular to the surface of the circuit board
  • the pin is also perpendicular to the surface of the circuit board.
  • the pins include pins
  • the pins are perpendicular to the surface of the board. Set the pins as vertical pins, the structure is more stable.
  • the semiconductor package structure 100 may include a plurality of pins 30 , and the specific arrangement number and distribution density of the pins 30 may be designed according to current requirements.
  • a plurality of pins 30 are arranged on the circuit board 10 at intervals.
  • the plurality of pins 30 there is no special requirement for the spacing distance between the pins, for example, it may be >0.8 mm.
  • the material of the plastic sealing body 40 may be epoxy resin.
  • the material of the plastic sealing body 40 is solid epoxy resin, which is obtained by liquefying the solid epoxy resin and then injection molding.
  • the plastic package 40 has good heat dissipation performance and can form a good heat dissipation channel; meanwhile, the plastic package can provide mechanical support for electronic components such as chips, and protect electronic components such as chips from external physical or chemical damage.
  • the semiconductor package structure 100 further includes metal bonding wires 60 , and the chips and the pins and the chips and the chips can be electrically connected through the metal bonding wires 60 .
  • the circuit board 10 includes a first surface and a second surface disposed opposite to each other, and the chip 20, the pins 30, etc. are arranged on the first surface of the circuit board 10, that is, the side surface with the circuit pattern, the circuit board 10
  • the second surface of the circuit board 10 (ie, the side not provided with the chip 20 ) exposes the plastic packaging body 40 , that is, the second surface of the circuit board 10 is not covered by the plastic packaging body 40 and is exposed outside the plastic packaging body 40 .
  • the circuit board 10 includes a substrate 11 and metal layers 12 and 13 disposed on the substrate.
  • the material of the substrate 11 is not limited, and may be ceramics, organic resins, metal frames, etc. .
  • the circuit board 11 is a double-sided copper-clad ceramic substrate.
  • the double-sided copper-clad ceramic substrate includes a ceramic substrate and a sintered copper plate arranged on both sides of the ceramic substrate.
  • the copper plate on one side of the ceramic substrate is patterned to form a circuit pattern.
  • the side 12 on which the circuit pattern is formed is electrically connected to the chip 20 .
  • the electrical connection between the chip 20 and the circuit board 10 can be achieved in different ways.
  • the electrical connection between the chip and the circuit board is achieved by silver glue or welding, wherein the electrical connection between the chip and the circuit board is achieved by welding.
  • the connection strength between the chip and the circuit board can be increased, and the precision is high, which facilitates the connection of components after the device is miniaturized.
  • the chip can be fixed on the circuit board by reflow soldering through a surface mount process.
  • the thickness specification of the circuit board can be selected according to actual needs, which is not particularly limited in this application.
  • a heat dissipation component may be further provided on the second surface of the circuit board 10 to realize a heat dissipation function.
  • the heat dissipation member may be, but not limited to, a heat dissipation plate, a heat dissipation fin, etc., and the heat dissipation member may be connected to the second surface of the circuit board 10 by welding.
  • the circuit board 10 is used as a carrier component to carry the chip 20 and is electrically connected when carrying the chip 20 .
  • the chip 20 is disposed on the circuit board 10 and stacked with the circuit board 10 .
  • the chip 20 may be a chip with different functions, and may be selected according to different functional requirements.
  • chip 20 may be a power amplifier chip.
  • the chip 20 may be a radio frequency microwave millimeter wave chip.
  • the chip 20 may also be an IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) or the like.
  • the semiconductor package structure 100 may include a plurality of chips 20 .
  • the plurality of chips may be chips with different functions.
  • the front side of the chip 20, that is, the side facing away from the circuit board 10 is the active surface, including functional transistors and related circuits
  • the back side that is, the side close to the circuit board 10
  • the metal layer may include gold, silver, copper layers and the like.
  • the chip and the circuit board are electrically connected, and the metal layer on the back of the chip is electrically connected with the pad on the circuit board.
  • Metal bonding wires connect the signal source on the front of the chip and the circuit traces on the circuit board.
  • the semiconductor package structure 100 may further include other electronic components disposed on the circuit board 10 , and the other electronic components may include but are not limited to resistors, capacitors, inductors, and thermal sensing elements Wait. Other electronic components can also be packaged various types of devices.
  • An embodiment of the present application provides a method for manufacturing a semiconductor packaging structure, and a schematic diagram of the manufacturing process is shown in FIG. 3 , including:
  • circuit board 10 can be a double-sided copper clad laminate; the circuit board includes a first surface and a second surface arranged oppositely, and the copper plate on the first surface is patterned to form a circuit pattern.
  • solder paste printing can be set according to the setting positions of chips, pins and other electronic components.
  • connection seat 3 Weld the chip 20 and the connection seat 3 on the first surface of the circuit board 10; the material of the connection seat is a conductive metal, which can be but not limited to copper, silver, aluminum and other metals with excellent conductivity.
  • connection base 3 has a closed mounting hole, including a base and a top wall oppositely arranged, and a surrounding side wall, the base, the top wall and the surrounding side wall together define a closed mounting hole.
  • the base of the connection socket 3 is welded on the circuit board 10 .
  • the connecting base 3 has a mounting hole open to one end, including a top wall and a surrounding side wall disposed oppositely, and the top wall and the surrounding side wall together define a mounting hole open at one end.
  • the bottom of the side wall of the connection seat 3 (that is, the open side) is soldered on the circuit board. After soldering and reflow, the circuit board and the connection seat define a closed mounting hole, that is, the connection seat 3 has a mounting hole that is open to one end. Closed after solder reflow.
  • connection seat is not limited, and its cross-sectional shape may be but not limited to regular shapes such as cylinder, elliptical cylinder, cuboid, and polygon; of course, it may also be irregular.
  • the chip may not be fixed on the circuit board by means of reflow soldering, for example, it may be fixed by silver glue.
  • wire bonding the chip and the circuit board to form the metal bonding wire 60 when there are multiple chips, wire bonding can also be carried out between the chips; the wire bonding is carried out according to conventional methods in the art Just operate, wire bonding can make internal chips, other electronic components, etc., to achieve electrical connection with circuit boards and pins.
  • the circuit board provided with the chip and the connection seat is plastic-sealed with a plastic-sealing material to form a plastic-sealed body 40 ; the plastic-sealed body 40 completely encloses the chip and the connection seat.
  • the second surface of the circuit board is exposed outside the plastic package, that is, the second surface of the circuit board is flush with the bottom surface of the plastic package.
  • the plastic package 40 extends beyond the edge of the circuit board by a certain width, so as to better protect the internal electronic components and circuits enclosed in the plastic package.
  • the plastic sealing mold used in the plastic sealing process may be an ordinary conventional plastic sealing mold, and the plastic sealing mold defines a plastic sealing cavity.
  • the plastic encapsulation material of the present application can be various plastic encapsulation materials commonly used in the field of semiconductor encapsulation, such as epoxy resin.
  • the plastic sealing process may include liquefying the solid epoxy resin, then injecting it into a plastic sealing cavity, and obtaining a plastic sealing body after the liquefied epoxy resin is cured.
  • grinding tools such as sandpaper, grinding wheel, and automatic grinder can be used for grinding, and the specifications and grinding parameters of the grinding tools can be determined according to the thickness of the plastic package removed by grinding.
  • the specifications of the sandpaper can be 400 mesh, 800 mesh, 1200 mesh, 2400 mesh and so on.
  • the semiconductor package structure shown in FIG. 1 in the embodiment of the present application can be prepared by referring to the above-mentioned manufacturing methods S11-S17.
  • the manufacturing method has low requirements on plastic packaging molds, and can use common plastic packaging molds in the field.
  • the cost is low, and the top-out PIN packaging structure in the form of plastic packaging can be realized.
  • the electrical paths of the pins are short, the parasitic parameters are small, and good heat dissipation can be obtained at the same time. performance; and the pins are not prone to problems such as kneeling, bending and deformation.
  • the embodiment of the present application also provides a method for manufacturing a semiconductor packaging structure, and the schematic diagram of the manufacturing process is shown in FIG. 4 , including:
  • circuit board 10 can be a double-sided copper clad laminate; the circuit board includes a first surface and a second surface arranged oppositely, and the copper plate on the first surface is patterned to form a circuit pattern.
  • Solder paste printing is performed on the first surface of the circuit board, and the chip 20 is welded on the first surface of the circuit board 10; then the chip and the circuit board are wire-bonded;
  • the plastic sealing mold includes a first mold 43 and a second mold (not shown in the figure) that are matched, and the first mold 43 is provided with a protruding structure 431 corresponding to the position of the predetermined pin; after plastic sealing, the plastic sealing body 40 A mounting hole 42 penetrating from the top surface of the plastic package to the circuit board is formed at the position of the predetermined pin; the size of the protruding structure is consistent with the size of the mounting hole.
  • the first mold 43 is cooperatively connected with the second mold to define an injection cavity, and the size and shape of the injection cavity determine the size and shape of the final molded plastic package.
  • a glue injection port is opened on the first mold, and the plastic sealing material is injected through the glue injection port.
  • the plastic encapsulation material can be various plastic encapsulation materials commonly used in the field of semiconductor encapsulation, such as epoxy resin.
  • the plastic sealing process may include liquefying the solid epoxy resin, then injecting it into a plastic sealing cavity, and obtaining a plastic sealing body after the liquefied epoxy resin is cured.
  • the insulating resin may specifically be, but not limited to, epoxy resin.
  • the insulating resin may fill the mounting holes or partially fill the mounting holes, that is, the upper surface of the insulating resin may be flush with the top surface of the plastic package 40 or lower than the top surface of the plastic package 40 .
  • the epoxy resin used for filling the mounting hole is a liquid epoxy resin.
  • the epoxy resin used to form the plastic body 40 by injection molding is a solid epoxy resin, which are epoxy resins of different systems, and can form a clear boundary after molding.
  • the semiconductor package structure shown in FIG. 2 in the embodiment of the present application can be prepared by using the above-mentioned manufacturing methods S21-S25.
  • the manufacturing method can realize the top-out PIN package in the form of plastic encapsulation.
  • the mounting holes for mounting the pins can be directly injection-molded, the pin positions can be set flexibly, and the pins are not affected by the plastic encapsulation process.
  • the extrusion of the material can maintain a stable structure and achieve a reliable connection with the circuit board through soldering and wrapping of insulating resin.
  • Embodiments of the present application further provide a semiconductor device, including the semiconductor package structure described above in the embodiments of the present application.
  • the semiconductor device can be a power semiconductor device, that is, a power electronic device, which is a high-power electronic device used in power conversion and control circuits of power equipment (usually referring to a current of tens to thousands of amps and a voltage of hundreds of volts or more).
  • the embodiments of the present application further provide an electronic device, which includes the semiconductor device described above in the embodiments of the present application, and the electronic device may be a notebook computer, a tablet computer (ipad), a desktop computer, a server, a display, and various peripheral devices in the computer field. ; It can also include mobile phones, telephones and other various terminal and central office equipment in the field of network communication; it can also include smart wearable devices in the field of consumer electronics, traditional black and white home appliances and various digital products; It can also include industrial control in the field of industrial control. Personal computers, automobiles, various instrumentation and control equipment, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本申请实施例提供一种半导体封装结构，包括电路板、芯片、引脚和塑封体；引脚包括连接部和插针，连接部一端焊接在电路板上，另一端与塑封体顶面齐平，连接部具有安装孔，插针设置于安装孔内并与连接部过盈配合，插针露出塑封体的顶面；塑封体的顶面和连接部的另一端的端面均为研磨粗糙面；或者引脚包括插针，塑封体设置贯穿塑封体的安装孔，插针设于安装孔内，插针一端焊接在电路板上，另一端露出塑封体的顶面，安装孔内填充绝缘树脂，绝缘树脂包裹在插针周围。该半导体封装结构为塑封形态的顶部出PIN封装结构，具有电气路径短，寄生参数小，引脚设置灵活，可靠性高，散热性好等优势。本申请实施例还提供半导体封装结构的制造方法。

Description

半导体封装结构及其制造方法和半导体器件
本申请要求于2020年9月28日提交中国专利局、申请号为202011046780.5、申请名称为“半导体封装结构及其制造方法和半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，尤其涉及一种半导体封装结构及其制造方法和半导体器件。
背景技术
目前，半导体封装领域中的功率模组封装结构主要有两类，一类是外壳型顶部出PIN(引脚)封装结构，该类封装结构由于顶部出PIN，具有电气路径短，寄生参数小，出PIN灵活性高的优势，但该结构的外壳内的腔体使用硅胶填充，模块散热能力差，成本高，组装时引脚易产生跪脚问题；另一类是塑封形态+插针焊接的封装结构，该类封装结构为两侧出PIN，具有导热性能好，可靠性高，PIN强度高的优势；但两侧出PIN导致电气路径长，寄生参数大，而且需要焊接到应用端的目标线路板上，不可拆卸。鉴于此，有必要提供一种半导体封装结构，以解决现有封装结构难以同时满足顶部出PIN和高散热性能需求的问题。
发明内容
本申请实施例提供了一种半导体封装结构及其制造方法，该半导体封装结构为塑封形态的顶部出PIN封装结构，具有电气路径短，寄生参数小，引脚位置设置灵活的优势，同时具有良好的散热性能，且封装工艺简单、各部件连接可靠、成本低。
本申请实施例第一方面提供一种半导体封装结构，包括：电路板、设置在所述电路板上的芯片和引脚、以及包覆所述电路板、所述芯片和所述引脚的塑封体；
所述引脚包括连接部和插针，所述连接部一端焊接在所述电路板上，另一端与所述塑封体的顶面齐平，所述连接部具有安装孔，所述插针设置于所述安装孔内并与所述连接部过盈配合，所述插针的一端露出所述塑封体的顶面；所述塑封体的顶面为研磨粗糙面；所述连接部的所述另一端的端面为研磨粗糙面；
或者，所述引脚包括插针，所述塑封体设置有从所述塑封体顶面贯穿至所述电路板的安装孔，所述插针设置于所述安装孔内，所述插针的一端焊接在所述电路板上，另一端露出所述塑封体的顶面，所述安装孔内填充有绝缘树脂，所述绝缘树脂包裹在所述插针周围。
本申请实施例半导体封装结构，为塑封形态的顶部出PIN封装结构，具有电气路径短，寄生参数小的优势，有利于信号传输，且引脚的位置可根据需要灵活设置，引脚的数量即设置密度也可根据需要增大，同时引脚不易弯折变形，不会出现压弯、塌陷和跪脚问题。本申请半导体封装结构还具有良好的散热性能，可以形成良好的散热通道，能够及时将器件内部产生的热量散发至外部，可靠性高，可适用于大功率半导体器件。该半导体封装结构可通过注塑形成塑封体后，研磨塑封体和连接部使安装孔露出，再将插针过盈配合安装于安装孔内，实现塑封形态的顶部出PIN封装结构；或者通过采用特定结构的塑封模具注塑形成具有安装孔的塑封体后，在安装孔内焊接插针，并填充绝缘树脂实现塑封形态的顶部出PIN封装结构。 整个封装工艺简单，成本可控。
本申请一些实施方式中，所述连接部包括环绕的侧壁，所述连接部的侧壁一端(即侧壁底部)焊接在所述电路板上。所述侧壁底部与所述电路板之间形成焊接部。侧壁底部为连接部与电路板连接的一端。连接部的侧壁厚度可以根据器件的通流要求进行设定，通流较大则连接部的侧壁厚度可以设置大一些，而通流较小则连接部的侧壁厚度可以设置小一些。
本申请另一些实施方式中，所述连接部包括底座和环绕的侧壁，所述连接部的底座焊接在所述电路板上。所述底座与所述电路板之间形成焊接部。连接部的侧壁厚度可以根据器件的通流要求进行设定，通流较大则连接部的侧壁厚度可以设置大一些，而通流较小则连接部的侧壁厚度可以设置小一些。
本申请实施方式中，所述连接部为导电金属材质。具体地，可以是具有优异导电性能的铜、银、铝等金属。
本申请实施方式中，所述连接部包括连接部本体和设置在连接部本体表面的表面处理层，所述表面处理层为电镀锡层、电镀镍层、化学镍金层或化学镍钯金层。表面处理层的设置可以提高连接部的焊接性能，从而与电路板之间形成更好的连接，同时，表面处理层还可以提高连接部的抗氧化性能。
本申请实施方式中，所述插针位于所述连接部的安装孔内的长度大于或等于1/2插针的总长度。这样可以保证插针与连接部过盈配合的部分的长度大于或等于1/2插针的总长度，提高插针与连接部的连接可靠性。
本申请实施方式中，所述塑封体的研磨粗糙面的粗糙度Ra大于0.1微米；所述连接部的研磨粗糙面的粗糙度Ra大于0.1微米。
本申请实施方式中，所述绝缘树脂包括环氧树脂。环氧树脂具有良好绝缘性能，且易得。
本申请实施方式中，所述绝缘树脂的填充高度大于或等于1/4所述插针的长度。绝缘树脂具有一定填充高度能够更好地包裹住插针，从而有效保证插针的结构稳定性。
本申请实施方式中，所述插针为导电金属材质。具体地，可以是具有优异导电性能的铜、银、铝等金属。插针可以是包括插针本体和设置在插针本体表面的保护层。保护层的材质例如可以是锡。
本申请实施方式中，所述引脚为直线型引脚，不存在弯折部。直线型引脚的电气路径短，寄生参数小，有利于信号传输。
本申请实施方式中，所述引脚为垂直引脚，所述引脚沿垂直于所述电路板表面的方向延伸。垂直引脚电气路径最短，寄生参数最小，有利于信号传输。
本申请实施方式中，所述半导体封装结构包括多个所述引脚，多个所述引脚间隔设置。本申请实施方式中，多个所述引脚均为垂直引脚。
本申请实施方式中，所述半导体封装结构包括多个芯片，多个芯片可以是具有不同功能。
本申请实施方式中，所述半导体封装结构还包括设置在所述电路板上的其他电子元器件。所述其他电子元器件可以包括但不限于是电阻、电容、电感、热感测元件等。其他电子元器件也可以是封装好的各类元器件。
第二方面，本申请实施例提供一种半导体封装结构的制造方法，包括：
将芯片固定在电路板上；
将连接座焊接在所述电路板上；所述连接座具有一封闭的安装孔；或者所述连接座具有一朝一端开口的安装孔，经所述焊接后，所述安装孔被封闭；
将所述芯片与所述电路板进行金属线键合；
采用塑封材料将设置有芯片、连接部的电路板进行塑封，形成塑封体；
对所述塑封体的顶面和所述连接座进行研磨使所述安装孔露出；经研磨后，所述连接座形成连接部，所述连接部被研磨的一端与所述塑封体的顶面齐平；
将插针安装在所述安装孔内，所述插针与所述连接部过盈配合；所述插针一端位于所述安装孔内，另一端露出所述安装孔。
本申请实施例第二方面提供的半导体封装结构的制造方法，可实现塑封形态的顶部出PIN封装，且对塑封模具的形状没有特殊要求，采用普通塑封模具即可，模具易得，对于不同内部结构的半导体器件都可以进行封装，因此塑封模具可以重复使用，可以大大降低封装成本。该封装方法也不受产品厚度限制，可以适用于不同厚度的产品封装，可以是用于封装厚度大于5mm的较大厚度的产品。当需要设置多个引脚时，该方法对多个连接座的平整度也没有特殊的要求，多个连接座允许有一定的高度差，因此该封装方法实用性高。
第三方面，本申请实施例提供一种半导体封装结构的制造方法，包括：
将芯片固定在电路板上，将所述芯片与所述电路板进行金属线键合；
采用塑封模具、塑封材料将固定有芯片的电路板进行塑封，形成塑封体；其中，所述塑封模具包相配合的第一模具和第二模具，所述第一模具对应于预设引脚的位置设有凸起结构；经所述塑封后，所述塑封体在所述预设引脚的位置形成从所述塑封体顶面贯穿至所述电路板的安装孔；
将插针焊接在所述安装孔内，所述插针与所述电路板之间形成焊接部；所述插针一端位于所述安装孔内，另一端露出所述安装孔；
向所述安装孔内注入绝缘树脂，固化后，得到半导体封装结构。
本申请实施例第三方面提供的半导体封装结构的制造方法，可实现塑封形态的顶部出PIN封装，通过设计特定形状结构的塑封模具可以直接注塑成型出用于安装引脚的安装孔，引脚位置可灵活设置，引脚不会受到塑封过程塑封材料的挤压，从而能够保持稳定结构，并通过焊接以及绝缘树脂的包裹与电路板实现可靠连接。
第四方面，本申请实施例还提供一种半导体器件，包括本申请实施例第一方面所述的半导体封装结构。
另外，本申请实施例还提供一种电子设备，该电子设备包括本申请实施例第四方面所述的半导体器件。该电子设备可以是手机、ipad、笔记本电脑、台式电脑、智能穿戴设备、显示器、服务器、仪器仪表等设备。
本申请实施例提供的半导体封装结构，为塑封形态的顶部出PIN封装结构，具有电气路径短、寄生参数小、出PIN灵活性高、导热性能好、可靠性高等优势。而且该半导体封装结构在进行进一步组装时，可采用压接组装，不需要通过回流焊接，可以简化半导体器件的组装工艺，降低成本。该半导体封装结构的封装工艺简单，各部件连接可靠，成本低，采用普通塑封模具、塑封工艺即可实现加工，适于大规模工业化生产。
附图说明
图1是本申请一实施例提供的一种半导体封装结构的示意图；
图2是本申请另一实施例提供的一种半导体封装结构的示意图；
图3是本申请一实施例提供的半导体封装结构的制造方法流程示意图；
图4是本申请另一实施例提供的半导体封装结构的制造方法流程示意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
请参见图1和图2，本申请实施例提供一种半导体封装结构100，包括：电路板10、设置在电路板10一侧表面的芯片20、引脚30、以及封装包覆电路板10、芯片20和引脚30的塑封体40；塑封体40包括相对设置的底面和顶面，底面和顶面一般是平行于电路板10表面的，其中，顶面为靠近电路板10设置芯片20的一侧表面，即位于芯片上方的一侧表面；底面为靠近电路板10未设置芯片20的一侧表面，引脚30露出塑封体40的顶面。
本申请一实施方式中，如图1所示，引脚30包括连接部31和插针32，连接部31一端焊接在电路板10上，另一端(即远离电路板10的一端)向远离电路板10表面的方向延伸，并与塑封体40的顶面齐平，连接部31具有安装孔41，插针32设置于安装孔41内并与连接部31过盈配合，插针32的一端露出塑封体40的顶面；塑封体40为可研磨材料，塑封体40的顶面为研磨粗糙面；连接部31的另一端的端面为研磨粗糙面。
该实施方式中，连接部31的具体形状结构不限。本申请一些实施方式中，连接部31具有上下贯通的安装孔41，连接部31包括环绕的侧壁，连接部31的侧壁底部焊接在电路板10上，侧壁底部与电路板10之间形成焊接部50(参见图1)。此时，安装孔41的底部为电路板10或形成在电路板10上的焊接部50。连接部31的侧壁顶部端面即为连接部31的另一端的端面，连接部31的侧壁顶部端面与塑封体40的顶面齐平，且为研磨粗糙面。
本申请另一些实施方式中，连接部31包括底座和由底座向上延伸的环绕的侧壁，连接部31的底座焊接在电路板10上，底座与电路板10之间经焊接形成焊接部。此时，安装孔41的底部即为连接部31的底座。底座的厚度无特殊要求。
本申请实施方式中，连接部31为导电金属材质。本申请实施方式中，插针32为导电金属材质。具体地，连接部31、插针32的材质可以但不限于是具有优异导电性能的铜、银、铝等金属。本申请实施方式中，连接部31的具体形状不限，其横截面形状可以但不限于是圆柱形、椭圆柱形、长方体形、多边体形等规则形状；当然也可以是非规则形状。本申请实施方式中，插针32可以是包括插针本体和设置在插针本体表面的保护层。保护层的材质例如可以是锡。例如，本申请一具体实施方式中，插针32为表面镀锡的铜插针。本申请一些实施方式中，插针32为扁平状，插针32的厚度可以根据需要选择不同规格。插针32的厚度例如可以是0.64mm，也可以是0.8mm。插针32露出塑封体40顶面的长度可以根据需要进行设计。
本申请实施方式中，连接部31的侧壁厚度可以根据半导体器件的通流要求进行具体设定，通流要求较大则连接部31的侧壁厚度可以设置大一些，而通流要求较小则连接部31的侧壁厚度可以设置小一些。
本申请实施方式中，塑封体40为可研磨材料。该塑封体40具有可研磨的特性，通过研磨可以减薄塑封体的厚度(高度)，使被塑封体包覆的连接部31露出。连接部31为可研磨金属，通过研磨可以减薄连接部的厚度(高度)。本申请实施方式中，连接部31的另一端的端面和塑封体40的顶面均为研磨粗糙面，且连接部31的另一端的端面与塑封体40的顶面齐平，该研磨粗糙面是通过研磨获得，其粗糙度根据研磨采用的工具(如砂纸)的规格而决定。在一些实施方式中，塑封体40的顶面的研磨粗糙面的粗糙度Ra可以是大于0.1μm；在另一些实施方式中，塑封体40的顶面的研磨粗糙面的粗糙度Ra可以是大于或等于0.2μm，具体例如为0.2μm-0.3μm。在一些实施方式中，连接部31另一端端面的研磨粗糙面的粗糙度Ra可以是大于0.1μm；在另一些实施方式中，连接部31另一端端面的研磨粗糙面的粗糙度Ra可以是大于或等于0.2μm，具体例如为0.2μm-0.3μm。
本申请实施例半导体封装结构100，在进行塑封时，插针还未安装，且安装孔是完全封闭的，因此在注入塑封胶料时不会出现塑封胶料将插针挤压变形的情况，而且塑封胶料也不会进入到安装孔中，在进行插针安装时不需要对安装孔进行除胶处理。因此，本申请实施例的半导体封装结构不仅实现了插针的可靠连接，而且可保持插针的形状结构稳定，避免弯折、跪脚等问题出现。
本申请实施方式中，可对连接部31进行适当表面处理，经表面处理后，连接部31包括连接部本体和设置在连接部本体表面的表面处理层，该表面处理层可以但不限于是电镀锡层、电镀镍层、化学镍金层或化学镍钯金层。表面处理层的厚度可以是0.03μm-25μm。具体地，一些实施方式中，表面处理层的厚度为0.1μm-20μm。另一些实施方式中，表面处理层的厚度为0.5μm-15μm。在其他一些实施方式中，表面处理层的厚度为1μm-5μm。表面处理层的设置可以提高连接部的焊接性能，从而与电路板之间形成更好的连接，同时，表面处理层还可以提高连接部的抗氧化性能，有效防止连接部在常规环境保存和封装工艺过程中被氧化。而通过设置适合厚度的表面处理层，可以兼顾到焊接性能和抗氧化性能的提高，又不会提高表面处理层的镀制成本。
该实施方式中，插针32与连接部31的安装孔41是相配合的。插针32可以是如图1所示，不***到安装孔41的最底部，即插针32位于安装孔41内的一端与电路板10或连接部31的底座之间留有一定距离或间隙。插针32也可以是***到安装孔41的最底部，即插针32位于安装孔41内的一端与电路板10或电路板10上的焊接部相抵接。为了保证插针32的安装可靠性，实现稳固连接，本申请实施方式中，插针32位于安装孔41内的长度大于或等于1/2插针32的总长度。因此，安装孔41的高度(即长度)需要设置为大于或等于1/2插针32总长度。具体地，本申请一些实施方式中，插针32位于安装孔41内的长度为1/2插针32的总长度。本申请另一些实施方式中，插针32位于安装孔41内的长度为2/3插针32的总长度。本申请其他一些实施方式中，插针32位于安装孔41内的长度为3/4插针32的总长度。可以理解地，插针32位于安装孔41内的长度越长，则与连接部31通过过盈配合的接触面越大，因此可以实现更稳固可靠的连接，有效防止插针32脱落。
本申请另一实施方式中，如图2所示，引脚30包括插针32，塑封体40设置有从塑封体40顶面贯穿至电路板10的安装孔42，插针32设置于安装孔42内，插针32的一端焊接在电路板10上，与电路板10之间形成焊接部51，另一端露出塑封体10的顶面，安装孔42内填充有绝缘树脂33，绝缘树脂33包裹在插针32周围。该实施方式中，插针32为导电金属材质。具体地，插针32的材质可以但不限于是具有优异导电性能的铜、银、铝等金属。本申请实施方式中，插针32可以是包括插针本体和设置在插针本体表面的保护层。保护层的材质例如可以是锡。例如，本申请一具体实施方式中，插针32为表面镀锡的铜插针。本申请一些实施方式中，插针32为扁平状，插针32的厚度可以根据需要选择不同规格。插针32的厚度例如可以是0.64mm，也可以是0.8mm。插针32露出塑封体40顶面的长度可以根据需要进行设计。
本申请实施方式中，在安装孔42中填充绝缘树脂33，绝缘树脂33能够将插针32牢牢固定，防止插针32脱落，并能保护插针32在后续使用过程中不被外界损坏。本申请实施方式中，绝缘树脂33包括但不限于是环氧树脂。具体地，绝缘树脂33可以是一种或多种环氧树脂构成的树脂组合物。环氧树脂种类多，可获得性高，有利于控制封装成本。本申请中，用于填充安装孔42的环氧树脂为液态型环氧树脂。
本申请实施方式中，绝缘树脂33的填充高度可以是小于或等于安装孔42的高度(即长 度)，即绝缘树脂33的上表面可以是低于塑封体40的顶面，也可以是与塑封体40的顶面齐平。为了给插针32提供更稳固的支撑，防止插针32弯折变形，同时提高插针32的连接可靠性，安装孔42中的绝缘树脂33的填充高度大于或等于1/4插针的长度。同时本申请一些实施方式中，绝缘树脂33的填充高度大于或等于1/2插针的长度。本申请另一些实施方式中，绝缘树脂33的填充高度大于或等于2/3插针的长度。本申请其他一些实施方式中，绝缘树脂33的填充高度大于或等于3/4插针的长度。可以理解地，绝缘树脂33的填充高度越高，插针32被包裹得越好，可以实现更稳固可靠的连接，从而有效防止插针脱落。
本申请实施例上述提供的半导体封装结构100，均为顶面出PIN(引脚)结构，相对于现有技术的侧面出PIN(引脚)结构，本申请的顶面出PIN(引脚)结构具有电气路径短，寄生参数小的优势，有利于信号传输，而且引脚的位置可根据需要灵活设置，引脚的数量即设置密度也可根据需要增大，扩大了产品的设计自由度，可匹配更为复杂的内部电路设计，实现多功能引脚布置。本申请实施例的半导体封装结构100可以保证引脚不易弯折变形，保护插针不压弯、塌陷。而且本申请实施例的半导体封装结构100，将半导体封装结构100进行进一步组装时，只需要将半导体封装结构100整体通过设置插针的一面压接到目标线路板上，进行机械连接即可，不需要通过回流焊接，可以简化半导体器件的组装工艺，降低成本。而且由于本申请的引脚连接稳定可靠，在压接过程中不易出现弯折变形。本申请半导体封装结构采用塑封体进行封装，塑封体具有良好的散热性能，可以形成良好的散热通道，能够及时将器件内部产生的热量散发至外部，可适用于大功率半导体器件。
本申请实施方式中，引脚30，即管脚，是从集成电路的内部电路引出的用于与***电路连接的接线，引脚构成芯片与外部进行连接的接口。本申请实施方式中，引脚通过焊接的方式与电路板实现电气连接，引脚与电路板的连接面通常较小，采用焊接的方式可以增加连接强度，避免引脚脱落风险。引脚的具体焊接方式不限，可以是锡膏焊接、焊片焊接或激光焊接。
本申请实施方式中，引脚30为直线型引脚，不存在弯折部。直线型引脚电气路径最短，寄生参数最低，有利于信号传输。本申请一些实施方式中，引脚30为垂直引脚，即引脚30沿垂直于电路板10表面的方向延伸。当引脚包括连接座和插针时，连接座的侧壁与电路板表面垂直，插针也与电路板的表面垂直。当引脚包括插针时，插针与电路板的表面垂直。将引脚设置为垂直引脚，结构更稳定。
本申请实施方式中，半导体封装结构100可以是包括多个引脚30，引脚30的具体设置数量，分布密度可根据通流需求进行设计。多个引脚30间隔设置在电路板10上。多个引脚30中，引脚与引脚之间的间隔距离无特殊要求，例如可以是＞0.8mm。
本申请实施方式中，塑封体40的材质可以是环氧树脂。具体地，塑封体40的材质为固态型环氧树脂，是通过将固态型环氧树脂液化后，注塑成型获得。塑封体40具有良好的散热性能，可以形成良好的散热通道；同时塑封体可以为芯片等电子元器件提供机械支撑，并保护芯片等电子元器件免受外界物理或化学损伤。
本申请实施方式中，如图1和图2所示，半导体封装结构100还包括金属键合线60，芯片与引脚、芯片与芯片之间可以通过金属键合线60实现电气连接。
本申请实施方式中，电路板10包括相对设置的第一表面和第二表面，芯片20、引脚30等设置在电路板10的第一表面，即具有电路图案的一侧表面，电路板10的第二表面(即未设置芯片20的一侧)露出塑封体40，即电路板10的第二表面不被塑封体40包覆，裸露在塑封体40外。
本申请实施方式中，如图1和图2所示，电路板10包括基板11和设置在基板上的金属层12、13，基板11的材质不限，可以是陶瓷、有机树脂、金属框架等。本申请一具体实施方式中，电路板11为双面覆铜陶瓷基板，双面覆铜陶瓷基板包括陶瓷基板和设置在陶瓷基板两面的烧结铜板，陶瓷基板一面的铜板被图案化形成电路图案，形成电路图案的一侧12与芯片20电气连接。本申请实施方式中，芯片20与电路板10之间的电气连接可以采用不同的方式来实现，具体地，如芯片与电路板之间采用银胶或焊接的方式实现电连接，其中，通过焊接方式将芯片与电路板电连接，能够增加芯片与电路板之间的连接强度，且精度高，便于器件小型化后部件的连接。芯片可以是通过表面贴装工艺，经回流焊接固定在电路板上。电路板的厚度规格可以根据实际需要进行选择，本申请不特殊限定。
本申请实施方式中，电路板10的第二表面可以进一步设置散热部件，以实现散热功能。具体地，散热部件可以但不限于为散热板、散热片等，散热部件可以通过焊接的方式与电路板10的第二表面实现连接。
本申请实施方式中，电路板10作为承载部件承载芯片20，并在承载芯片20时实现电连接，芯片20设置在电路板10上并与电路板10层叠。本申请实施方式中，芯片20可以是具有不同功能的芯片，具体可根据不同功能需要进行选择。在一些实施方式中，芯片20可以是功率放大器芯片。在另一些实施方式中，芯片20可以是射频微波毫米波芯片。在其他一些实施方式中，芯片20也可以是IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)等。本申请实施方式中，根据实际功能需要，半导体封装结构100可以是包括多个芯片20。多个芯片可以是具有不同功能的芯片。
本申请实施方式中，芯片20的正面即背离电路板10的一面为有源面，包含功能晶体管和相关电路，背面即靠近电路板10的一面为一整层金属层，作为电路的参考地或散热面，金属层可以是包括金、银、铜层等。芯片与电路板之间电连接，通过芯片背面的金属层与电路板上的焊盘导电连通。金属键合线则连接芯片正面信号源和电路板上的电路走线。
本申请实施方式中，根据实际功能需要，半导体封装结构100还可以包括设置在电路板10上的其他电子元器件，其他电子元器件可以包括但不限于是电阻、电容、电感、热感测元件等。其他电子元器件也可以是封装好的各类器件。
本申请实施例提供一种半导体封装结构的制造方法，其制备流程示意图如图3所示，包括：
S11、提供电路板10；该电路板可以是双面覆铜板；电路板包括相对设置的第一表面和第二表面，第一表面的铜板图案化，形成电路图案。
S12、在电路板的第一表面进行锡膏印刷；锡膏印刷的位置可根据芯片、引脚及其他电子元器件的设置位置进行设定。
S13、将芯片20、连接座3焊接在电路板10的第一表面上；连接座的材质为导电金属，可以但不限于是具有优异导电性能的铜、银、铝等金属。
本申请一些实施方式中，连接座3具有一封闭的安装孔，包括相对设置的底座和顶壁，以及环绕的侧壁，底座、顶壁和环绕的侧壁一同限定出封闭的安装孔。连接座3的底座焊接在电路板10上。
本申请另一些实施方式中，连接座3具有一朝一端开口的安装孔，包括相对设置的顶壁以及环绕的侧壁，顶壁和环绕的侧壁一同限定出一端开口的安装孔。连接座3的侧壁底部(即开口的一侧)焊接在电路板上，经焊接回流后，电路板与连接座限定出一封闭的安装孔，即连接座3具有的朝一端开口的安装孔经焊接回流后被封闭。
本申请实施方式中，连接座的具体外形不限，其横截面形状可以但不限于是圆柱形、椭圆柱形、长方体形、多边体形等规则形状；当然也可以是非规则形状。
当然，在其他实施方式中，芯片也可以不采用回流焊接的方式固定在电路板上，例如可以是通过银胶固定。
S14、将芯片与电路板进行金属线键合，形成金属键合线60；当有多个芯片时，芯片与芯片之间也可进行金属线键合；金属线键合根据本领域常规方式进行操作即可，金属线键合可以使内部芯片、其他电子元器件等与电路板、引脚实现电气连接。
S15、采用塑封材料将设置有芯片、连接座的电路板进行塑封，形成塑封体40；塑封体40将芯片、连接座完全包覆在内。其中，电路板的第二表面裸露在塑封体外，即电路板的第二表面与塑封体的底面齐平。一般地，塑封体40超出电路板的边缘一定宽度，从而能更好地保护包裹在塑封体内的内部电子元器件和电路。
本申实施方式中，塑封过程采用的塑封模具可以是普通常规塑封模具，塑封模具限定出塑封腔。本申请的塑封材料可以是半导体封装领域常用的各种塑封材料，例如可以是环氧树脂。具体地，塑封过程可以是将固态型环氧树脂液化后，注入塑封腔内，待液化后的环氧树脂固化后得到塑封体。
S16、对塑封体40顶面和连接座顶壁进行研磨使连接座封闭的安装孔41露出；经研磨后，塑封体40的厚度减薄，顶面形成研磨粗糙面，粗糙度Ra可以是大于0.1微米；连接座3的顶壁被研磨去除，形成连接部31，连接部31被研磨的一端也形成研磨粗糙面，粗糙度Ra可以是大于0.1微米，连接部31被研磨的一端与塑封体40的顶面齐平，即连接部31的研磨粗糙面与塑封体40的研磨粗糙面齐平，这样有利于控制实施研磨操作，也有利于后续进行进一步组装。
本申请实施方式中，研磨可采用砂纸、砂轮、自动研磨机等研磨工具，研磨工具的规格、研磨参数可以根据研磨去除的塑封体的厚度而定。例如，砂纸的规格可以是400目、800目，1200目、2400目等。
S17、将插针32安装在安装孔41内，插针32与连接部31过盈配合；插针32一端位于安装孔内，另一端露出安装孔，即露出塑封体40的顶面，得到半导体封装结构。
本申请实施例图1所示的半导体封装结构可以参照上述S11-S17的制造方法制备得到。该制造方法对塑封模具的要求低，采用领域内普通塑封模具即可，成本低，且可以实现塑封形态的顶部出PIN封装结构，引脚的电气路径短，寄生参数小，同时可获得良好散热性能；且引脚不易产生跪脚、弯折变形等问题。
本申请实施例还提供一种半导体封装结构的制造方法，其制备流程示意图如图4所示，包括：
S21、提供电路板10；该电路板可以是双面覆铜板；电路板包括相对设置的第一表面和第二表面，第一表面的铜板图案化，形成电路图案。
在电路板的第一表面进行锡膏印刷，将芯片20焊接在电路板10的第一表面上；再将芯片与电路板进行金属线键合；
S22、采用塑封模具、塑封材料将固定有芯片的电路板进行塑封，形成塑封体40；
其中，塑封模具包括相配合的第一模具43和第二模具(图中未示出)，第一模具43对应于预设引脚的位置设有凸起结构431；经塑封后，塑封体40在预设引脚的位置形成从塑封体顶面贯穿至电路板的安装孔42；凸起结构的尺寸与安装孔的尺寸一致。
本申请实施方式中，第一模具43与第二模具配合连接以限定出注塑腔，注塑腔的尺寸形 状决定了最终成型的塑封体的尺寸形状。一般地，第一模具上开设有注胶口，通过该注胶口注入塑封材料。塑封材料可以是半导体封装领域常用的各种塑封材料，例如可以是环氧树脂。具体地，塑封过程可以是将固态型环氧树脂液化后，注入塑封腔内，待液化后的环氧树脂固化后得到塑封体。
S23、在安装孔42内点锡膏；
S24、将插针32焊接在安装孔42内，插针与电路板之间形成焊接部；插针一端位于安装孔内，另一端露出安装孔，也即露出塑封体40的顶面；
S25、向安装孔内注入绝缘树脂33，固化后，得到半导体封装结构。
绝缘树脂具体可以但不限于是环氧树脂。绝缘树脂可以是填满安装孔，也可以是部分填充安装孔，即绝缘树脂的上表面可以是与塑封体40的顶面齐平，也可以是低于塑封体40的顶面。本申请中，用于填充安装孔的环氧树脂为液态型环氧树脂。而注塑形成塑封体40的环氧树脂为固态型环氧树脂，是不同体系的环氧树脂，两者成型后可形成明显的分界。
本申请实施例图2所示的半导体封装结构可以采用上述S21-S25的制造方法制备得到。该制造方法可实现塑封形态的顶部出PIN封装，通过设计特定形状结构的塑封模具可以直接注塑成型出用于安装引脚的安装孔，引脚位置可灵活设置，引脚不会受到塑封过程塑封材料的挤压，从而能够保持稳定结构，并通过焊接以及绝缘树脂的包裹与电路板实现可靠连接。
本申请实施例还提供一种半导体器件，包括本申请实施例上述的半导体封装结构。该半导体器件可以是功率半导体器件，即电力电子器件(Power Electronic Device)，是用于电力设备的电能变换和控制电路方面的大功率电子器件(通常指电流为数十至数千安，电压为数百伏以上)。
本申请实施例还提供一种电子设备，其包括本申请实施例上述的半导体器件，该电子设备可以是包括计算机领域的笔记本、平板电脑(ipad)、台式电脑、服务器、显示器以及各种外设；也可以包括网络通信领域的手机、电话以及其它各种终端和局端设备；也可以包括消费电子领域的智能穿戴设备、传统黑白家电和各种数码产品；还可以包括工业控制领域中的工业个人电脑、汽车、各类仪器仪表和控制设备等。

Claims (18)

  1. 一种半导体封装结构，其特征在于，包括：电路板、设置在所述电路板上的芯片和引脚、以及包覆所述电路板、所述芯片和所述引脚的塑封体；
    所述引脚包括连接部和插针，所述连接部一端焊接在所述电路板上，另一端与所述塑封体的顶面齐平，所述连接部具有安装孔，所述插针设置于所述安装孔内并与所述连接部过盈配合，所述插针的一端露出所述塑封体的顶面；所述塑封体的顶面为研磨粗糙面；所述连接部的所述另一端的端面为研磨粗糙面；
    或者，所述引脚包括插针，所述塑封体设置有从所述塑封体顶面贯穿至所述电路板的安装孔，所述插针设置于所述安装孔内，所述插针的一端焊接在所述电路板上，另一端露出所述塑封体的顶面，所述安装孔内填充有绝缘树脂，所述绝缘树脂包裹在所述插针周围。
  2. 如权利要求1所述的半导体封装结构，其特征在于，所述连接部包括环绕的侧壁，所述连接部的侧壁一端焊接在所述电路板上。
  3. 如权利要求1所述的半导体封装结构，其特征在于，所述连接部包括底座和环绕的侧壁，所述连接部的底座焊接在所述电路板上。
  4. 如权利要求1-3任一项所述的半导体封装结构，其特征在于，所述连接部为导电金属材质。
  5. 如权利要求1-4任一项所述的半导体封装结构，其特征在于，所述连接部包括连接部本体和设置在连接部本体表面的表面处理层，所述表面处理层为电镀锡层、电镀镍层、化学镍金层或化学镍钯金层。
  6. 如权利要求1-5任一项所述的半导体封装结构，其特征在于，所述插针位于所述连接部的安装孔内的长度大于或等于1/2插针的总长度。
  7. 如权利要求1-6任一项所述的半导体封装结构，其特征在于，所述塑封体的研磨粗糙面的粗糙度Ra大于0.1微米；所述连接部的研磨粗糙面的粗糙度Ra大于0.1微米。
  8. 如权利要求1所述的半导体封装结构，其特征在于，所述绝缘树脂包括环氧树脂。
  9. 如权利要求1或8所述的半导体封装结构，其特征在于，所述绝缘树脂的填充高度大于或等于1/4所述插针的长度。
  10. 如权利要求1-9任一项所述的半导体封装结构，其特征在于，所述插针为导电金属材质。
  11. 如权利要求1-10任一项所述的半导体封装结构，其特征在于，所述引脚为直线型引脚，不存在弯折部。
  12. 如权利要求11所述的半导体封装结构，其特征在于，所述引脚为垂直引脚，所述引脚沿垂直于所述电路板表面的方向延伸。
  13. 如权利要求1-12任一项所述的半导体封装结构，其特征在于，所述半导体封装结构包括多个所述引脚，多个所述引脚间隔设置。
  14. 如权利要求1-13任一项所述的半导体封装结构，其特征在于，所述半导体封装结构还包括设置在所述电路板上的其他电子元器件。
  15. 一种半导体封装结构的制造方法，其特征在于，包括：
    将芯片固定在电路板上；
    将连接座焊接在所述电路板上；所述连接座具有一封闭的安装孔；或者所述连接部具有一朝一端开口的安装孔，经所述焊接后，所述安装孔被封闭；
    将所述芯片与所述电路板进行金属线键合；
    采用塑封材料将设置有芯片、连接座的电路板进行塑封，形成塑封体；
    对所述塑封体的顶面和所述连接座进行研磨使所述安装孔露出；经研磨后，所述连接座形成连接部，所述连接部被研磨的一端与所述塑封体的顶面齐平；
    将插针安装在所述安装孔内，所述插针与所述连接部过盈配合；所述插针一端位于所述安装孔内，另一端露出所述安装孔。
  16. 一种半导体封装结构的制造方法，其特征在于，包括：
    将芯片固定在电路板上，将所述芯片与所述电路板进行金属线键合；
    采用塑封模具、塑封材料将固定有芯片的电路板进行塑封，形成塑封体；其中，所述塑封模具包括第一模具和第二模具，所述第一模具对应于预设引脚的位置设有凸起结构；经所述塑封后，所述塑封体在所述预设引脚的位置形成从所述塑封体顶面贯穿至所述电路板的安装孔；
    将插针焊接在所述安装孔内，所述插针与所述电路板之间形成焊接部；所述插针一端位于所述安装孔内，另一端露出所述安装孔；
    向所述安装孔内注入绝缘树脂，固化后，得到半导体封装结构。
  17. 一种半导体器件，其特征在于，包括如权利要求1-14任一项所述的半导体封装结构。
  18. 一种电子设备，其特征在于，包括如权利要求17所述的半导体器件。
PCT/CN2021/120800 2020-09-28 2021-09-26 半导体封装结构及其制造方法和半导体器件 WO2022063283A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21871652.0A EP4207269A4 (en) 2020-09-28 2021-09-26 SEMICONDUCTOR PACKAGE STRUCTURE AND RELATED MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
US18/190,388 US20230238315A1 (en) 2020-09-28 2023-03-27 Semiconductor packaged structure and manufacturing method thereof, and semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011046780.5A CN112271165A (zh) 2020-09-28 2020-09-28 半导体封装结构及其制造方法和半导体器件
CN202011046780.5 2020-09-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/190,388 Continuation US20230238315A1 (en) 2020-09-28 2023-03-27 Semiconductor packaged structure and manufacturing method thereof, and semiconductor device

Publications (1)

Publication Number Publication Date
WO2022063283A1 true WO2022063283A1 (zh) 2022-03-31

Family

ID=74348622

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/120800 WO2022063283A1 (zh) 2020-09-28 2021-09-26 半导体封装结构及其制造方法和半导体器件

Country Status (4)

Country Link
US (1) US20230238315A1 (zh)
EP (1) EP4207269A4 (zh)
CN (1) CN112271165A (zh)
WO (1) WO2022063283A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115062575A (zh) * 2022-06-10 2022-09-16 扬州虹扬科技发展有限公司 一种三相整流桥塑封模注胶口位置优化方法及***
EP4354498A1 (en) * 2022-09-29 2024-04-17 Littelfuse, Inc. Isolated power packaging with flexible connectivity

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112271165A (zh) * 2020-09-28 2021-01-26 华为技术有限公司 半导体封装结构及其制造方法和半导体器件
CN114040563A (zh) * 2021-11-05 2022-02-11 上海杰瑞兆新信息科技有限公司 一种高散热性能的电子产品的封装结构及其封装方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100127389A1 (en) * 2008-11-26 2010-05-27 Mitsubishi Electric Corporation Power semiconductor module
CN103489792A (zh) * 2013-08-06 2014-01-01 江苏长电科技股份有限公司 先封后蚀三维***级芯片倒装封装结构及工艺方法
US20150145123A1 (en) * 2013-11-25 2015-05-28 Samsung Electro-Mechanics Co., Ltd. Power semiconductor module and method of manufacturing the same
CN109545759A (zh) * 2018-12-24 2019-03-29 芜湖启迪半导体有限公司 一种功率模块结构及其制造方法
CN111769090A (zh) * 2020-07-21 2020-10-13 无锡利普思半导体有限公司 塑封功率模块、塑封模具及塑封方法
CN112271165A (zh) * 2020-09-28 2021-01-26 华为技术有限公司 半导体封装结构及其制造方法和半导体器件

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656031B2 (en) * 2007-02-05 2010-02-02 Bridge Semiconductor Corporation Stackable semiconductor package having metal pin within through hole of package
JP4825259B2 (ja) * 2008-11-28 2011-11-30 三菱電機株式会社 電力用半導体モジュール及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100127389A1 (en) * 2008-11-26 2010-05-27 Mitsubishi Electric Corporation Power semiconductor module
CN103489792A (zh) * 2013-08-06 2014-01-01 江苏长电科技股份有限公司 先封后蚀三维***级芯片倒装封装结构及工艺方法
US20150145123A1 (en) * 2013-11-25 2015-05-28 Samsung Electro-Mechanics Co., Ltd. Power semiconductor module and method of manufacturing the same
CN109545759A (zh) * 2018-12-24 2019-03-29 芜湖启迪半导体有限公司 一种功率模块结构及其制造方法
CN111769090A (zh) * 2020-07-21 2020-10-13 无锡利普思半导体有限公司 塑封功率模块、塑封模具及塑封方法
CN112271165A (zh) * 2020-09-28 2021-01-26 华为技术有限公司 半导体封装结构及其制造方法和半导体器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4207269A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115062575A (zh) * 2022-06-10 2022-09-16 扬州虹扬科技发展有限公司 一种三相整流桥塑封模注胶口位置优化方法及***
CN115062575B (zh) * 2022-06-10 2023-08-29 扬州虹扬科技发展有限公司 一种三相整流桥塑封模注胶口位置优化方法及***
EP4354498A1 (en) * 2022-09-29 2024-04-17 Littelfuse, Inc. Isolated power packaging with flexible connectivity

Also Published As

Publication number Publication date
US20230238315A1 (en) 2023-07-27
EP4207269A4 (en) 2024-03-06
EP4207269A1 (en) 2023-07-05
CN112271165A (zh) 2021-01-26

Similar Documents

Publication Publication Date Title
WO2022063283A1 (zh) 半导体封装结构及其制造方法和半导体器件
US7638364B2 (en) Multilayer integrated circuit for RF communication and method for assembly thereof
US20070053167A1 (en) Electronic circuit module and manufacturing method thereof
US10096562B2 (en) Power module package
US20140029201A1 (en) Power package module and manufacturing method thereof
US20140251658A1 (en) Thermally enhanced wiring board with built-in heat sink and build-up circuitry
TW201543632A (zh) 三維空間封裝結構及其製造方法
TWI670804B (zh) 半導體裝置
WO2014154139A1 (zh) 一种电子件安装结构及制作方法、电子件产品
TWI725426B (zh) 半導體裝置
JPH11191603A (ja) 半導体集積回路装置およびその製造方法
CN218867104U (zh) 异构封装基板和模组
CN107845610A (zh) 基板结构及其制作方法
CN108242434B (zh) 基板结构及其制造方法
CN214099627U (zh) 智能功率模块
US20040173898A1 (en) Semiconductor apparatus having system-in-package arrangement with improved heat dissipation
CN211208440U (zh) 一种芯片和天线集成的三维封装结构
CN209880583U (zh) 半导体封装结构
CN212967676U (zh) 散热芯片及电路板
CN221102058U (zh) 一种氮化镓功率模块
CN216671606U (zh) 一种芯片封装体和电子装置
CN215815865U (zh) 一种半导体模块及封装结构
CN217983329U (zh) 半导体封装结构
US20240120289A1 (en) Electronic package and a method for making the same
WO2023221529A1 (zh) 一种封装结构、封装方法以及电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21871652

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021871652

Country of ref document: EP

Effective date: 20230330

NENP Non-entry into the national phase

Ref country code: DE