WO2022052161A1 - Chip debugging system and debugger - Google Patents
Chip debugging system and debugger Download PDFInfo
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- WO2022052161A1 WO2022052161A1 PCT/CN2020/116886 CN2020116886W WO2022052161A1 WO 2022052161 A1 WO2022052161 A1 WO 2022052161A1 CN 2020116886 W CN2020116886 W CN 2020116886W WO 2022052161 A1 WO2022052161 A1 WO 2022052161A1
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
- G06F9/4451—User profiles; Roaming
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
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- the invention relates to the field of chip testing, in particular to a chip debugging system and a debugger.
- the current EDA chip debugging tools are mainly logic analyzers and debugging equipment for specific occasions. Although a small number of EDA equipment directly uses FPGA, the FPGA debugging tools are customized through the function of the chip to meet the chip production debugging, but this requires the speed of the chip. In other words, it is far from keeping up with the pace of chip development.
- the traditional EDA debugging tools have low debugging efficiency, relatively fixed interfaces, and poor interface compatibility.
- the purpose of the present invention is to provide a chip debugging system and a debugger with good interface compatibility, aiming at the problems existing in the above-mentioned prior art.
- a chip debugging system which especially includes: an FPGA processor, an FPGA logic array, and a debugger set in a computer,
- the debugger is used to provide a graphical interface for the user to set the interface type of the FPGA, and send the corresponding interface configuration file to the FPGA processor according to the user's setting;
- the FPGA processor is used to program the interface configuration file into the FPGA logic array
- the FPGA logic array is used to simulate a corresponding communication interface according to the interface configuration file.
- the debugger is preset with a plurality of interface configuration files corresponding to the type of the communication interface.
- the communication interface types include a JTAG interface, an I2C interface, an SPI interface, a UART interface and an I/O interface.
- the debugger includes:
- the graphical interface providing module is used to provide a graphical interface for users to set the interface type of the FPGA logic array
- the configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.
- the debugger further includes:
- the script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
- the chip debugger further includes:
- the configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
- a chip debugger which includes:
- Graphical interface providing module used to provide a graphical interface for users to set the interface type of FPGA
- the configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user, so as to configure the FPGA logic array.
- the chip debugger further includes:
- the script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
- the chip debugger further includes:
- the configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
- the designed virtual logic codes are classified and managed, and then encapsulated in their own text library, and the user can indirectly change the FPGA through the visual interface. Internal logic, and then generate the corresponding virtual interface according to the content configured by the interface. Finally, each virtual interface can be selectively assigned to the board hardware interface. By executing the script, each different interface can be instantiated, and then used by the FPGA. Call, and finally generate synthesizable logic, the user can freely configure on the PC side to change the virtual hardware debugging interface, so as to achieve the purpose of configuring different interfaces.
- FIG. 1 is a schematic structural diagram of a chip debugging system according to an embodiment of the present invention.
- FIG. 2 is a schematic structural diagram of a chip debugger according to an embodiment of the present invention.
- FIG. 3 is a flow chart of the use of the chip debugging system according to the embodiment of the present invention.
- a chip debugging system which includes: an FPGA processor, an FPGA logic array, and a debugger set in a computer.
- the computer can communicate with the FPGA processor via Ethernet.
- the FPGA processor and the FPGA may be located in one FPGA mainboard, or may be arranged in different FPGA mainboards.
- the FPGA can be connected with the pins of the chip to be tested through a flexible circuit board.
- the debugger is configured to provide a graphical interface for a user to set the interface type of the FPGA logic array, and send a corresponding interface configuration file to the FPGA processor according to the user's setting.
- the chip debugging system is mainly used to debug the chip. Since different chips have different communication interfaces, different interface devices need to be used to debug the chips. Therefore, in the embodiment of the present invention, an FPGA logic array is used to simulate different communication interfaces.
- a plurality of interface configuration files corresponding to the communication interface type are preset in the debugger, and the debugger is used to provide an image interface to set the interface type of the FPGA. . The user only needs to select the corresponding communication interface type, channel and quantity in the graphical interface provided by the debugger, and the debugger can automatically obtain the corresponding interface configuration file.
- the debugger can send the interface configuration file corresponding to the communication interface set by the user to the FPGA processor.
- the debugger is also used to provide a graphical interface to control the signals collected and output by the PFGA processor, and to display the debug results in real time.
- the FPGA processor is used for programming the interface configuration file into the FPGA logic array.
- the FPGA processor is used to program the FPGA logic array. After the FPGA processor acquires the interface configuration file sent by the debugger, it writes it into the FPGA logic array.
- the PFGA processor can simultaneously program interface configuration files into multiple PFGA logic arrays.
- the FPGA logic array is used for simulating a corresponding communication interface according to the interface configuration file, and the user can assign the position of the interface pins as required.
- the FPGA logic array can simulate various communication interfaces according to the programmed interface configuration file, so as to communicate with the chip to be tested.
- the types of the communication interface include a JTAG interface, an I2C interface, an SPI interface, a UART interface and an I/O interface.
- two FPGA logic arrays are used, and the user can also add multiple FPGA logic arrays according to actual requirements to increase resources and realize more channels.
- the debugger includes a graphical interface providing module, a script library, a configuration file acquisition module and a configuration file transmission module. Each of them will be described below.
- the graphical interface providing module is used to provide a graphical interface for the user to set the interface type of the FPGA.
- the script library is used to pre-store a plurality of interface configuration files corresponding to various communication interface types.
- the configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
- the interface configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.
- the process of using the chip debugging system to debug the chip is as follows:
- the user selects the current device model to be debugged through the graphical interface provided by the debugger on the PC side, and sets relevant parameters of the device according to the requirements.
- the debugger will generate an interface configuration file corresponding to the set parameters and send it to An FPGA processor, where the FPGA processor performs firmware programming on the FPGA logic array.
- chip debugging can be performed.
- the type and quantity of virtual interfaces connected to peripherals can be customized. All virtual peripheral interfaces are composed of logic units, which can be freely programmed to obtain the desired interface, which is very flexible.
- the designed virtual logic codes are classified and managed, and then encapsulated in their own text library.
- the user can indirectly change the internal logic virtual code of the FPGA through the visual interface. Interface, each different interface can be instantiated by executing the script, and then called by the FPGA to finally generate synthesizable logic.
- the user can configure the virtual hardware debugging interface at will on the PC side, so as to achieve their own Purpose.
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Abstract
A chip debugging system and a debugger. The chip debugging system comprises: an FPGA processor, an FPGA logic array, and a debugger which is arranged in a computer, wherein the debugger is used for providing a graphical interface for a user to set an interface type of an FPGA, and sending a corresponding interface configuration file to the FPGA processor according to the setting made by the user; the FPGA processor is used for programming the interface configuration file into the FPGA logic array; and the FPGA logic array is used for simulating a corresponding communication interface according to the interface configuration file. By means of the method, compatibility for chips with a variety of interfaces can be realized.
Description
本发明涉及芯片测试领域,尤其涉及一种芯片调试***及调试器。The invention relates to the field of chip testing, in particular to a chip debugging system and a debugger.
随着EDA行业的发展,全球芯片制造需求不断增大,为了使芯片验证和调试取得既快速又可靠的效果,则对EDA调试***的性能要求会越来越高。当前的EDA芯片调试工具主要为逻辑分析仪和特定场合的调试设备,虽然有少部分EDA设备直接采用FPGA,通过芯片的功能来定制FPGA的调试工具来满足芯片生产调试,但是这对芯片需求速度来讲,其远远跟不上芯片发展的步伐。With the development of the EDA industry, the global chip manufacturing demand continues to increase. In order to achieve fast and reliable chip verification and debugging, the performance requirements of the EDA debugging system will become higher and higher. The current EDA chip debugging tools are mainly logic analyzers and debugging equipment for specific occasions. Although a small number of EDA equipment directly uses FPGA, the FPGA debugging tools are customized through the function of the chip to meet the chip production debugging, but this requires the speed of the chip. In other words, it is far from keeping up with the pace of chip development.
传统的EDA调试工具调试效率低,接口比较固定,接口兼容性差的技术问题。The traditional EDA debugging tools have low debugging efficiency, relatively fixed interfaces, and poor interface compatibility.
发明内容SUMMARY OF THE INVENTION
本发明的目的是针对上述现有技术存在的问题,提供一种接口兼容性好的芯片调试***及调试器。The purpose of the present invention is to provide a chip debugging system and a debugger with good interface compatibility, aiming at the problems existing in the above-mentioned prior art.
本发明实施例中,提供了一种芯片调试***,其特包括:FPGA处理器、FPGA逻辑阵列及设置于计算机中的调试器,In the embodiment of the present invention, a chip debugging system is provided, which especially includes: an FPGA processor, an FPGA logic array, and a debugger set in a computer,
所述调试器,用于提供图形界面,供用户设置所述FPGA的接口类型,并根据用户的设置将相应的接口配置文件发送给所述FPGA处理器;The debugger is used to provide a graphical interface for the user to set the interface type of the FPGA, and send the corresponding interface configuration file to the FPGA processor according to the user's setting;
所述FPGA处理器,用于将所述接口配置文件烧写到所述FPGA逻辑阵列中;The FPGA processor is used to program the interface configuration file into the FPGA logic array;
所述FPGA逻辑阵列,用于根据所述接口配置文件模拟出相应的通讯接口。The FPGA logic array is used to simulate a corresponding communication interface according to the interface configuration file.
本发明实施例中,所述调试器中,预先设置有多个与通讯接口类型相应的接口配置文件。In the embodiment of the present invention, the debugger is preset with a plurality of interface configuration files corresponding to the type of the communication interface.
本发明实施例中,所述通讯接口类型包括JTAG接口、I2C接口、SPI接口、UART接口及I/O接口。In the embodiment of the present invention, the communication interface types include a JTAG interface, an I2C interface, an SPI interface, a UART interface and an I/O interface.
本发明实施例中,所述调试器包括:In this embodiment of the present invention, the debugger includes:
图形界面提供模块,用于提供图像界面,供用户设置FPGA逻辑阵列的接 口类型;The graphical interface providing module is used to provide a graphical interface for users to set the interface type of the FPGA logic array;
配置文件传送模块,用于根据用户的设置的接口类型将相应的接口配置文件发送给所述FPGA处理器。The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.
本发明实施例中,所述调试器还包括:In this embodiment of the present invention, the debugger further includes:
脚本库,用于预先存储多个与多种通讯接口类型相应的接口配置文件。The script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
本发明实施例中,所述的芯片调试器,还包括:In the embodiment of the present invention, the chip debugger further includes:
配置文件获取模块,用于根据用户设置的接口类型从所述脚本库中获取相应的接口配置文件。The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
本发明实施例中,还提供了一种芯片调试器,其包括:In the embodiment of the present invention, a chip debugger is also provided, which includes:
图形界面提供模块,用于提供图像界面,供用户设置FPGA的接口类型;Graphical interface providing module, used to provide a graphical interface for users to set the interface type of FPGA;
配置文件传送模块,用于根据用户的设置的接口类型将相应的接口配置文件发送给FPGA处理器,从而对所述FPGA逻辑阵列进行配置。The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user, so as to configure the FPGA logic array.
本发明实施例中,所述的芯片调试器还包括:In the embodiment of the present invention, the chip debugger further includes:
脚本库,用于预先存储多个与多种通讯接口类型相应的接口配置文件。The script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
本发明实施例中,所述的芯片调试器还包括:In the embodiment of the present invention, the chip debugger further includes:
配置文件获取模块,用于根据用户设置的接口类型从所述脚本库中获取相应的接口配置文件。The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
与现有技术相比较,采用本发明的芯片调试***及调试器,将设计好的虚拟逻辑代码进行分类和管理,然后被封装在自己的文本库里面,用户可以通过可视化界面间接地的改变FPGA内部逻辑,进而按照界面所配置的内容生成相应的虚拟接口,最终每个虚拟接口可选择性的分配到板子硬件接口上,通过执行脚本的方式可以对每个不同接口进行实例化,而被FPGA调用,最终生成可综合的逻辑,用户可以随意的在PC端进行配置使虚拟硬件调试接口发生改变,从而达到配置不同接口的目的。Compared with the prior art, using the chip debugging system and the debugger of the present invention, the designed virtual logic codes are classified and managed, and then encapsulated in their own text library, and the user can indirectly change the FPGA through the visual interface. Internal logic, and then generate the corresponding virtual interface according to the content configured by the interface. Finally, each virtual interface can be selectively assigned to the board hardware interface. By executing the script, each different interface can be instantiated, and then used by the FPGA. Call, and finally generate synthesizable logic, the user can freely configure on the PC side to change the virtual hardware debugging interface, so as to achieve the purpose of configuring different interfaces.
图1是本发明实施例的芯片调试***的结构示意图。FIG. 1 is a schematic structural diagram of a chip debugging system according to an embodiment of the present invention.
图2是本发明实施例的芯片调试器的结构示意图。FIG. 2 is a schematic structural diagram of a chip debugger according to an embodiment of the present invention.
图3是本发明实施例的芯片调试***的使用流程图。FIG. 3 is a flow chart of the use of the chip debugging system according to the embodiment of the present invention.
如图1所示,本发明实施例中,提供了一种芯片调试***,其包括:FPGA处理器、FPGA逻辑阵列及设置于计算机中的调试器。所述计算机可以通过以太网与所述FPGA处理器进行通信。所述FPGA处理器和所述FPGA可以位于一块FPGA主板中,也可以设置与不同的FPGA主板中。所述FPGA可以通过柔性电路板与待测试的芯片引脚进行连接。As shown in FIG. 1 , in an embodiment of the present invention, a chip debugging system is provided, which includes: an FPGA processor, an FPGA logic array, and a debugger set in a computer. The computer can communicate with the FPGA processor via Ethernet. The FPGA processor and the FPGA may be located in one FPGA mainboard, or may be arranged in different FPGA mainboards. The FPGA can be connected with the pins of the chip to be tested through a flexible circuit board.
所述调试器,用于提供图形界面,供用户设置所述FPGA逻辑阵列的接口类型,并根据用户的设置将相应的接口配置文件发送给所述FPGA处理器。The debugger is configured to provide a graphical interface for a user to set the interface type of the FPGA logic array, and send a corresponding interface configuration file to the FPGA processor according to the user's setting.
需要说明的是,所述芯片调试***主要用于对芯片进行调试。由于不同的芯片具有不同的通讯接口,需要采用不同的接口器件对芯片进行调试,因此,本发明实施例中,采用FPGA逻辑阵列来模拟不同的通讯接口。为便于对所述FPGA的进行配置,本发明实施例中,所述调试器中预先设置有多个与通讯接口类型相应的接口配置文件,采用所述调试器提供图像界面来设置FPGA的接口类型。用户只需在所述调试器提供的图形界面中选择相应的通讯接口类型、通道和数量,所述调试器即可自动获取相应的接口配置文件。用户设置完成后,所述调试器即可将与用户设置的通讯接口相应的接口配置文件发送给所述FPGA处理器。所述调试器还用于提供图像界面控制所述PFGA处理器采集和输出的信号,并实时显示调试结果。It should be noted that the chip debugging system is mainly used to debug the chip. Since different chips have different communication interfaces, different interface devices need to be used to debug the chips. Therefore, in the embodiment of the present invention, an FPGA logic array is used to simulate different communication interfaces. In order to facilitate the configuration of the FPGA, in the embodiment of the present invention, a plurality of interface configuration files corresponding to the communication interface type are preset in the debugger, and the debugger is used to provide an image interface to set the interface type of the FPGA. . The user only needs to select the corresponding communication interface type, channel and quantity in the graphical interface provided by the debugger, and the debugger can automatically obtain the corresponding interface configuration file. After the user setting is completed, the debugger can send the interface configuration file corresponding to the communication interface set by the user to the FPGA processor. The debugger is also used to provide a graphical interface to control the signals collected and output by the PFGA processor, and to display the debug results in real time.
所述FPGA处理器,用于将所述接口配置文件烧写到所述FPGA逻辑阵列中。The FPGA processor is used for programming the interface configuration file into the FPGA logic array.
需要说明的是,本发明实施例中,采用所述FPGA处理器对所述FPGA逻辑阵列进行烧写。所述FPGA处理器获取所述调试器发送过来的接口配置文件后,将其烧写到所述FPGA逻辑阵列中。所述PFGA处理器可以将接口配置文件同时烧写到多个PFGA逻辑阵列中。It should be noted that, in the embodiment of the present invention, the FPGA processor is used to program the FPGA logic array. After the FPGA processor acquires the interface configuration file sent by the debugger, it writes it into the FPGA logic array. The PFGA processor can simultaneously program interface configuration files into multiple PFGA logic arrays.
所述FPGA逻辑阵列,用于根据所述接口配置文件模拟出相应的通讯接口,其接口引脚位置用户可以根据需要进行分配。The FPGA logic array is used for simulating a corresponding communication interface according to the interface configuration file, and the user can assign the position of the interface pins as required.
需要说明的是,根据FPGA逻辑阵列的特性,其可以根据烧写的接口配置 文件来模拟出各种通讯接口,从而与待测试的芯片进行通信。本发明实施例中,所述通讯接口的类型包括JTAG接口、I2C接口、SPI接口、UART接口及I/O接口。It should be noted that, according to the characteristics of the FPGA logic array, it can simulate various communication interfaces according to the programmed interface configuration file, so as to communicate with the chip to be tested. In the embodiment of the present invention, the types of the communication interface include a JTAG interface, an I2C interface, an SPI interface, a UART interface and an I/O interface.
本发明实施例中,采用了两个FPGA逻辑阵列,用户也可以根据实际需求增加多个FPGA逻辑阵列,增加资源,实现更多通道。In the embodiment of the present invention, two FPGA logic arrays are used, and the user can also add multiple FPGA logic arrays according to actual requirements to increase resources and realize more channels.
如图2所示,所述调试器包括图形界面提供模块、脚本库、配置文件获取模块和配置文件传送模块。下面分别进行说明。As shown in FIG. 2 , the debugger includes a graphical interface providing module, a script library, a configuration file acquisition module and a configuration file transmission module. Each of them will be described below.
所述图形界面提供模块,用于提供图像界面,供用户设置FPGA的接口类型。The graphical interface providing module is used to provide a graphical interface for the user to set the interface type of the FPGA.
所述脚本库,用于预先存储多个与多种通讯接口类型相应的接口配置文件。The script library is used to pre-store a plurality of interface configuration files corresponding to various communication interface types.
配置文件获取模块,用于根据用户设置的接口类型从所述脚本库中获取相应的接口配置文件。The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
所述接口配置文件传送模块,用于根据用户的设置的接口类型将相应的接口配置文件发送给所述FPGA处理器。The interface configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.
如图3所示,采用所述芯片调试***对芯片进行调试的过程如下:As shown in FIG. 3 , the process of using the chip debugging system to debug the chip is as follows:
用户在PC端通过所述调试器提供的图形界面选择当前被调试设备型号,根据需求对设备进行相关参数设置,参数设置完成后,所述调试器会生成与设置参数相应的接口配置文件发送给FPGA处理器,由所述FPGA处理器对FPGA逻辑阵列进行固件烧写。被测试芯片在接通FPGA逻辑阵列后,就可以进行芯片调试了。对于与外设相连的虚拟接口类型,以及数量统统都可以自定义,所有的虚拟外设接口皆由逻辑单元组成,可以自由编程得到想要的接口,灵活性非常强。The user selects the current device model to be debugged through the graphical interface provided by the debugger on the PC side, and sets relevant parameters of the device according to the requirements. After the parameter setting is completed, the debugger will generate an interface configuration file corresponding to the set parameters and send it to An FPGA processor, where the FPGA processor performs firmware programming on the FPGA logic array. After the chip under test is connected to the FPGA logic array, chip debugging can be performed. The type and quantity of virtual interfaces connected to peripherals can be customized. All virtual peripheral interfaces are composed of logic units, which can be freely programmed to obtain the desired interface, which is very flexible.
综上所述,采用本发明的芯片调试***及调试器,将设计好的虚拟逻辑代码进行分类和管理,然后被封装在自己的文本库里面,用户可以通过可视化界面间接地改变FPGA内部逻辑虚拟接口,通过执行脚本的方式可以对每个不同接口进行实例化,而被FPGA调用,最终生成可综合的逻辑,用户可以随意的在PC端进行配置使虚拟硬件调试接口发生改变,从而达到自己的目的。To sum up, using the chip debugging system and the debugger of the present invention, the designed virtual logic codes are classified and managed, and then encapsulated in their own text library. The user can indirectly change the internal logic virtual code of the FPGA through the visual interface. Interface, each different interface can be instantiated by executing the script, and then called by the FPGA to finally generate synthesizable logic. The user can configure the virtual hardware debugging interface at will on the PC side, so as to achieve their own Purpose.
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发 明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.
Claims (10)
- 一种芯片调试***,其特征在于,包括:FPGA处理器、FPGA逻辑阵列及设置于计算机中的调试器,A chip debugging system, comprising: an FPGA processor, an FPGA logic array, and a debugger set in a computer,所述调试器,用于提供图形界面,供用户设置所述FPGA的通讯接口类型,并根据用户的设置将相应的接口配置文件发送给所述FPGA处理器;The debugger is used to provide a graphical interface for the user to set the communication interface type of the FPGA, and send the corresponding interface configuration file to the FPGA processor according to the user's setting;所述FPGA处理器,用于将所述接口配置文件烧写到所述FPGA逻辑阵列中;The FPGA processor is used to program the interface configuration file into the FPGA logic array;所述FPGA逻辑阵列,用于根据所述接口配置文件模拟出相应的通讯接口。The FPGA logic array is used to simulate a corresponding communication interface according to the interface configuration file.
- 如权利要求1所述的芯片调试***,其特征在于,所述调试器中,预先设置有多个与通讯接口类型相应的接口配置文件。The chip debugging system according to claim 1, wherein, in the debugger, a plurality of interface configuration files corresponding to the communication interface type are preset.
- 如权利要求1所述的芯片调试***,其特征在于,所述通讯接口类型包括JTAG接口、I2C接口、SPI接口、UART接口及I/O接口。The chip debugging system according to claim 1, wherein the communication interface types include JTAG interface, I2C interface, SPI interface, UART interface and I/O interface.
- 如权利要求1所述的芯片调试***,其特征在于,所述调试器包括:The chip debugging system according to claim 1, wherein the debugger comprises:图形界面提供模块,用于提供图像界面,供用户设置FPGA逻辑阵列的接口类型;The graphical interface providing module is used to provide a graphical interface for users to set the interface type of the FPGA logic array;配置文件传送模块,用于根据用户的设置的接口类型将相应的接口配置文件发送给所述FPGA处理器。The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user.
- 如权利要求4所述的芯片调试***,其特征在于,所述调试器还包括:The chip debugging system according to claim 4, wherein the debugger further comprises:脚本库,用于预先存储多个与多种通讯接口类型相应的接口配置文件。The script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
- 如权利要求5所述的芯片调试器,其特征在于,还包括:The chip debugger according to claim 5, further comprising:配置文件获取模块,用于根据用户设置的接口类型从所述脚本库中获取相应的接口配置文件。The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
- 一种芯片调试器,其特征在于,包括:A chip debugger, characterized in that it includes:图形界面提供模块,用于提供图像界面,供用户设置FPGA的接口类型;Graphical interface providing module, used to provide a graphical interface for users to set the interface type of FPGA;配置文件传送模块,用于根据用户的设置的接口类型将相应的接口配置文件发送给FPGA处理器,从而对所述FPGA逻辑阵列进行配置。The configuration file transmission module is configured to send the corresponding interface configuration file to the FPGA processor according to the interface type set by the user, so as to configure the FPGA logic array.
- 如权利要求7所述的芯片调试器,其特征在于,所述通讯接口类型包括JTAG接口、I2C接口、SPI接口、UART接口及I/O接口。The chip debugger according to claim 7, wherein the communication interface types include JTAG interface, I2C interface, SPI interface, UART interface and I/O interface.
- 如权利要求7所述的芯片调试器,其特征在于,还包括:The chip debugger according to claim 7, further comprising:脚本库,用于预先存储多个与多种通讯接口类型相应的接口配置文件。The script library is used to pre-store multiple interface configuration files corresponding to various communication interface types.
- 如权利要求9所述的芯片调试器,其特征在于,还包括:The chip debugger according to claim 9, further comprising:配置文件获取模块,用于根据用户设置的接口类型从所述脚本库中获取相应的接口配置文件。The configuration file obtaining module is configured to obtain the corresponding interface configuration file from the script library according to the interface type set by the user.
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