CN111435143A - Universal testing device and method - Google Patents
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- CN111435143A CN111435143A CN201910026461.9A CN201910026461A CN111435143A CN 111435143 A CN111435143 A CN 111435143A CN 201910026461 A CN201910026461 A CN 201910026461A CN 111435143 A CN111435143 A CN 111435143A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention provides a universal testing device, which comprises: the setting module is used for setting the test parameters according to the test requirements and generating test signals according to the set test parameters; and the debugging module is communicated with the setting module in an unfolding mode and used for determining the waveform type, the communication protocol type and the interface type in the testing process according to the received testing signal so as to test the tested equipment pointed by the testing requirement, and transmitting the fault state signal to the setting module after receiving the fault state signal fed back by the tested equipment. The invention can realize the signal interaction from the setting module to the tested equipment through the control chip, and can automatically select the type of the tested equipment to be debugged through the interaction interface of the setting module, thereby being generally applied to the tested equipment with different interfaces and communication protocols. The interactive interface improves the simplicity and the universality of the operation; need not to select testing arrangement according to equipment under test, promoted equipment under test instantiations test intelligent degree.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a universal testing device and a universal testing method.
Background
In recent years, with the development of science and technology, the category and the number of electronic power equipment are continuously increased, the electronic power equipment brings great convenience to production and life, once the electronic power equipment breaks down, great inconvenience and even loss are brought to production and life, and therefore, the requirement for testing the electronic power equipment is increasing, and a universal testing device is needed.
Specifically, in the field of converters, the interface and communication requirements of different converter modules are different, and a testing device special for the converter module must be manufactured in order to meet the interface and communication requirements of the different converter modules, but the number of the converter modules and the testing device is greatly increased along with the accumulation of time, the testing device needs to be frequently replaced during testing, the complexity of operation is increased, and the management is not facilitated.
Therefore, the invention provides a universal testing device and a universal testing method.
Disclosure of Invention
To solve the above problems, the present invention provides a universal test apparatus, comprising:
the setting module is used for setting the test parameters according to the test requirements and generating test signals according to the set test parameters;
and the debugging module is communicated with the setting module in an unfolding way and used for determining the waveform type, the communication protocol type and the interface type in the testing process according to the received testing signal so as to test the tested equipment pointed by the testing requirement, and transmitting the fault state signal to the setting module after receiving the fault state signal fed back by the tested equipment.
According to one embodiment of the invention, the setup module comprises:
the interactive interface is provided with an adjustable parameter setting interface and is used for setting the test parameters according to the test requirements;
the first signal processing unit is communicated with the interactive interface and used for generating the test signal according to the set test parameters;
and the first communication interface is communicated with the first signal processing unit and the debugging module and is used for sending the test signal to the debugging module and receiving the fault state signal transmitted by the debugging module.
According to one embodiment of the present invention, the interactive element interface comprises:
a parameter setting area, which is provided with a waveform selection interface, a module selection interface and a channel selection interface, and is respectively used for setting a waveform type, a communication protocol type and an interface type so as to generate the test signal through the first signal processing unit, wherein the test signal comprises a waveform selection signal, a module selection signal and a channel selection signal;
and the fault display area is communicated with the first communication interface and is used for displaying the fault state information of the tested equipment represented by the fault state signal.
According to one embodiment of the invention, the debugging module comprises:
the external communication unit is used for carrying out communication with the setting module and the tested device;
and the controller is communicated with the external communication unit and is used for determining the waveform type, the communication protocol type and the interface type in the test process according to the received test signal so as to test the tested device to which the test requirement points.
According to one embodiment of the present invention, the external communication unit includes:
the second communication interface is used for completing data transmission between the setting module and the debugging module;
and the third communication interface is used for completing data transmission between the test module and the tested equipment.
According to one embodiment of the present invention, the controller includes:
a second signal processing unit, in communication with the external communication unit, for converting the received test signal into a waveform selection signal, a module selection signal, and a channel selection signal, which are recognized by the debugging module;
the waveform generating unit is used for receiving the waveform selection signal transmitted by the second signal processing unit and generating a waveform pointed by the waveform selection signal, wherein the waveform comprises a logic output waveform or a chopped wave output waveform;
the comprehensive control unit is used for receiving the waveform generated by the waveform generating unit, the module selection signal and the channel selection signal transmitted by the second signal processing unit and determining the communication protocol type and the interface type in the test process according to the module selection signal and the channel selection signal;
and the fault determination unit is used for receiving the fault state signal fed back by the tested equipment, identifying the fault state information of the tested equipment according to the fault state signal and transmitting the fault state information of the tested equipment to the setting module through the comprehensive control unit.
According to an embodiment of the invention, the controller further comprises:
the communication output unit is communicated with the comprehensive control unit and is used for transmitting the received waveform, the communication protocol type and the interface type determined by the comprehensive control unit to the tested equipment;
and the communication receiving unit is communicated with the tested device and is used for transmitting the received fault feedback signal to the fault judging unit.
According to another aspect of the present invention, there is also provided a universal testing method, the method comprising the steps of:
setting test parameters according to test requirements, and generating test signals according to the set test parameters;
and determining the waveform type, the communication protocol type and the interface type in the test process according to the test signal so as to test the tested equipment pointed by the test requirement, and receiving a fault state signal fed back by the tested equipment.
According to one embodiment of the invention, through an adjustable parameter setting interface, test parameters are set according to test requirements;
and sending the test signal and receiving the fault state signal fed back by the tested device.
According to one embodiment of the invention, a waveform type, a communication protocol type and an interface type are set through a waveform selection interface, a module selection interface and a channel selection interface;
generating the test signal according to the set waveform type, the set communication protocol type and the set interface type, wherein the test signal comprises a waveform selection signal, a module selection signal and a channel selection signal;
and displaying the fault state information of the tested equipment represented by the fault state signal.
The universal testing device and the universal testing method provided by the invention are based on the composition of the setting module and the debugging module, can realize the signal interaction from the setting module to the tested equipment through the control chip, can autonomously select the type of the tested equipment to be debugged through the interaction interface of the setting module, and can be universally applied to the tested equipment with different interfaces and communication protocols. The use of an interactive interface improves the simplicity and the universality of the operation; need not to select testing arrangement according to equipment under test, promoted equipment under test instantiations test intelligent degree.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 shows a block diagram of a generic test device according to an embodiment of the invention;
FIG. 2 shows a block diagram of a generic test device according to another embodiment of the invention;
FIG. 3 shows a block diagram of a universal test apparatus human-machine interface architecture according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating signal transmission between an upper computer and a debugging tool of the universal test apparatus according to an embodiment of the invention;
FIG. 5 shows a block diagram of a generic test device waveform generation unit according to one embodiment of the present invention;
FIG. 6 is a block diagram of a communication output unit and a communication receiving unit of the universal test apparatus according to an embodiment of the present invention;
FIG. 7 is a block diagram of a general test apparatus integrated control unit according to an embodiment of the present invention; and
FIG. 8 shows a flowchart of a generic test method according to one embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
FIG. 1 shows a block diagram of a generic test device according to an embodiment of the invention. As shown in fig. 1, the general test apparatus 100 includes a setup module 101 and a debug module 102. The setting module 101 is configured to set a test parameter according to a test requirement, and generate a test signal according to the set test parameter. The debugging module 102 is in communication with the setting module 101, and is configured to determine a waveform type, a communication protocol type, and an interface type in a testing process according to the received test signal to test a device under test to which a test requirement is directed, and transmit a fault state signal to the setting module 101 after receiving the fault state signal fed back by the device under test.
In one embodiment, the setup module 101 comprises an interactive interface, a first signal processing unit, and a first communication interface. The interactive interface is provided with an adjustable parameter setting interface and is used for setting the test parameters according to the test requirements. The first signal processing unit is communicated with the interactive interface and used for generating a test signal according to the set test parameters. The first communication interface is in communication with the interactive interface and the debugging module 102, and is configured to send a test signal to the debugging module 102 and receive a fault status signal transmitted by the debugging module 102.
Further, the interactive interface comprises a parameter setting area and a fault display area. The parameter setting area is provided with a waveform selection interface, a module selection interface and a channel selection interface which are respectively used for setting a waveform type, a communication protocol type and an interface type so as to generate a test signal through the first signal processing unit, wherein the test signal comprises a waveform selection signal, a module selection signal and a channel selection signal. The fault display area is communicated with the first communication interface and used for displaying the fault state information of the tested equipment represented by the fault state signal.
In one embodiment, the debug module 102 includes an external communication unit and a controller. The external communication unit is used for performing communication with the setting module 101 and the tested device; the controller is communicated with the external communication unit and used for determining the waveform type, the communication protocol type and the interface type in the test process according to the received test signal so as to test the tested device to which the test requirement points.
Further, the external communication unit includes a second communication interface and a third communication interface. The second communication interface is used for completing data transmission between the setting module 101 and the debugging module 102; the third communication interface is used to complete 102 the data transfer between the test module and the device under test.
Further, the controller includes a second signal processing unit, a waveform generating unit, a comprehensive control unit, and a failure determining unit. The second signal processing unit is in communication with the external communication unit and is configured to convert the received test signal into a waveform selection signal, a module selection signal, and a channel selection signal, which are identified by the debug module 102; the waveform generating unit is used for receiving the waveform selection signal transmitted by the second signal processing unit and generating a waveform pointed by the waveform selection signal, wherein the waveform comprises a logic output waveform or a chopping wave output waveform.
The comprehensive control unit is used for receiving the waveform generated by the waveform generating unit, the module selection signal and the channel selection signal transmitted by the second signal processing unit and determining the communication protocol type and the interface type in the test process according to the module selection signal and the channel selection signal; the fault determination unit is used for receiving the fault state signal fed back by the tested equipment, identifying the fault state information of the tested equipment according to the fault state signal and transmitting the fault state information of the tested equipment to the setting module through the comprehensive control unit.
In addition, the controller may further include a communication output unit and a communication receiving unit. The communication output unit is communicated with the comprehensive control unit and is used for transmitting the received waveform, the communication protocol type and the interface type determined by the comprehensive control unit to the tested equipment; the communication receiving unit is communicated with the tested device and used for transmitting the received fault feedback signal to the fault judging unit.
In the field of current transformers, routine tests of current transformer modules mainly comprise logic tests, chopping tests and fault signal detection, and different current transformer modules are distinguished in the routine tests that optical signals or electric signals are adopted as signals and special communication protocol requirements possibly exist. In order to ensure the versatility of the testing apparatus, the optoelectronic selectivity of the signal and the selectivity of the communication protocol need to be solved. Therefore, when the device to be tested is a current transformer module, the invention provides a current transformer module universal testing device as shown in fig. 2. FIG. 2 shows a block diagram of a generic test device according to another embodiment of the invention.
As shown in fig. 2, the universal testing device 200 for converter modules includes an upper computer 201 and a debugging tool 202. The upper computer comprises a human-computer interaction interface, a signal processing unit A and a communication interface A. The debugging tool 202 includes a communication interface B, a controller, and an optical/electrical signal interface unit. The controller can be realized by various control chips and comprises a signal processing unit B, a comprehensive control unit, a fault judgment unit, a waveform generation unit, a communication output unit and a communication receiving unit.
When the testing device shown in fig. 2 is used, the set parameters are input through the human-computer interaction interface, then the set parameters are transmitted to the controller through the signal processing unit A and the communication interface A, and the module selection signal, the channel opening selection signal and the waveform selection signal are analyzed. The waveform selection signal is input to the waveform generation unit to generate a corresponding logic waveform or a chopping waveform, and the module selection signal and the channel opening selection signal are input to the comprehensive control unit to determine the type of the communication protocol, the type of the interface and the opening of the channel.
And reading a fault feedback signal from the communication receiving unit according to the selected communication protocol and the interface type, and identifying the fault state of the current conversion module through the fault judging unit. Specifically, the fault determination unit determines the fault of the converter module analyzed by the communication receiving unit, and identifies the fault state of the converter module. After the fault state is synthesized, the corresponding waveform is transmitted to a current conversion module through a communication output unit to realize routine test, and meanwhile, fault state information is fed back to the upper computer to be displayed on a human-computer interaction interface. The optical/electric signal interface unit completes the optical/electric signal transmission with the tested current transformation module.
The testing device shown in fig. 2 is composed of an upper computer and a debugging tool, signal interaction from the upper computer to a converter module is realized through a control chip, and the type of the converter module to be debugged can be selected automatically through a man-machine interaction interface of the upper computer; the universal automatic routine test device is suitable for universal automatic routine test of the converter module and can be generally used for converter modules with different interfaces and communication protocols. The use of a human-computer interaction interface improves the simplicity and the universality of the operation; a testing device does not need to be selected according to the converter module, so that the intelligent degree of the converter module instantiated testing is improved, and the cost can be saved.
FIG. 3 shows a block diagram of a universal test apparatus human-machine interface structure according to an embodiment of the invention. As shown in fig. 3, the human-computer interface includes a parameter setting area 301 and a display area 302. The parameter setting area 301 includes a module selection signal setting area, a waveform selection signal setting area, and a channel selection signal setting area. In the three setting areas mentioned above, corresponding test parameter settings can be performed according to the test requirements. The display area 302 contains a fault signal display area. The fault signal display area can display the fault state of the current transformation module.
Fig. 4 shows a schematic diagram of signal transmission between the upper computer of the universal testing device and the debugging tool according to an embodiment of the invention. As shown in fig. 4, the upper computer and the debugging tool are respectively provided with a signal processing unit and a communication interface. Wherein, every communication interface all contains receiving interface and transmission interface to carry out the signal transmission between host computer and the debugging frock. And signals needing to be transmitted between the upper computer and the debugging tool comprise a module selection signal, a waveform selection signal, a channel selection signal and a current transformation module fault signal.
It should be noted that, in practical application, the transmission of the module selection signal, the waveform selection signal, the channel opening selection signal and the alternating current module fault feedback signal is completed through the communication interface between the upper computer and the debugging tool. The communication interface can be realized by different modes such as 232 interface, 485 interface, internet access and the like, and the invention does not limit the invention.
FIG. 5 shows a block diagram of a generic test device waveform generation unit according to an embodiment of the present invention. As shown in fig. 5, the waveform generation unit 501 can generate a logic waveform and a chopping waveform to meet different test requirements. The waveform generating unit can generate a corresponding logic waveform or a chopped waveform according to the waveform selection signal.
FIG. 6 is a block diagram of a communication output unit and a communication receiving unit of a universal test apparatus according to an embodiment of the present invention. As shown in fig. 6, the communication output unit 601 receives the waveform signal of each channel and the communication protocol selection signal, can select a communication protocol, and outputs a waveform signal packaged according to the protocol. The communication output unit 602 receives the input signal and the communication protocol selection signal, can select a communication protocol, and outputs an unpacked fault signal.
Specifically, the communication receiving unit/communication output unit includes different communication protocols of existing items, and outputs waveform signals of each channel according to the communication protocol selected by the integrated control unit, and packages the waveform signals into a corresponding protocol to be sent to the external signal interface, and performs protocol unpacking on input signals of the external signal interface to analyze fault signals and send the fault signals to the fault determination unit.
FIG. 7 is a block diagram of a general test apparatus integrated control unit according to an embodiment of the present invention. As shown in fig. 7, the integrated control unit 701 can perform integrated logic processing, receive a model selection signal, a channel selection signal, a waveform selection signal, and a failure state signal, and output a failure state feedback signal, a waveform signal of each channel, and a communication protocol selection signal. The comprehensive control unit is a control core of the whole controller, and performs comprehensive logic processing on signals of the controller to realize signal interaction of each functional unit of the controller.
FIG. 8 shows a flowchart of a generic test method according to one embodiment of the invention.
As shown in fig. 8, in step S801, a test parameter is set according to a test requirement, and a test signal is generated according to the set test parameter. Further, in step S801, setting a test parameter according to a test requirement through an adjustable parameter setting interface; and sending a test signal and receiving a fault state signal fed back by the tested device.
Specifically, a waveform type, a communication protocol type and an interface type are set through a waveform selection interface, a module selection interface and a channel selection interface; and generating a test signal according to the set waveform type, the set communication protocol type and the set interface type, wherein the test signal comprises a waveform selection signal, a module selection signal and a channel selection signal.
Then, in step S802, the waveform type, the communication protocol type, and the interface type in the test process are determined according to the test signal to test the device under test to which the test requirement points, and a fault state signal fed back by the device under test is received. Specifically, in this step, the device under test fault status information characterized by the fault status signal is displayed.
The universal testing device and the universal testing method provided by the invention are based on the composition of the setting module and the debugging module, can realize the signal interaction from the setting module to the tested equipment through the control chip, can autonomously select the type of the tested equipment to be debugged through the interaction interface of the setting module, and can be universally applied to the tested equipment with different interfaces and communication protocols. The use of an interactive interface improves the simplicity and the universality of the operation; need not to select testing arrangement according to equipment under test, promoted equipment under test instantiations test intelligent degree.
It is to be understood that the disclosed embodiments of the invention are not limited to the particular structures, process steps, or materials disclosed herein but are extended to equivalents thereof as would be understood by those ordinarily skilled in the relevant arts. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A universal test apparatus, the apparatus comprising:
the setting module is used for setting the test parameters according to the test requirements and generating test signals according to the set test parameters;
and the debugging module is communicated with the setting module in an unfolding way and used for determining the waveform type, the communication protocol type and the interface type in the testing process according to the received testing signal so as to test the tested equipment pointed by the testing requirement, and transmitting the fault state signal to the setting module after receiving the fault state signal fed back by the tested equipment.
2. The apparatus of claim 1, wherein the setup module comprises:
the interactive interface is provided with an adjustable parameter setting interface and is used for setting the test parameters according to the test requirements;
the first signal processing unit is communicated with the interactive interface and used for generating the test signal according to the set test parameters;
and the first communication interface is communicated with the first signal processing unit and the debugging module and is used for sending the test signal to the debugging module and receiving the fault state signal transmitted by the debugging module.
3. The apparatus of claim 2, wherein the interactive element interface comprises:
a parameter setting area, which is provided with a waveform selection interface, a module selection interface and a channel selection interface, and is respectively used for setting a waveform type, a communication protocol type and an interface type so as to generate the test signal through the first signal processing unit, wherein the test signal comprises a waveform selection signal, a module selection signal and a channel selection signal;
and the fault display area is communicated with the first communication interface and is used for displaying the fault state information of the tested equipment represented by the fault state signal.
4. The apparatus of claim 3, wherein the debugging module comprises:
the external communication unit is used for carrying out communication with the setting module and the tested device;
and the controller is communicated with the external communication unit and is used for determining the waveform type, the communication protocol type and the interface type in the test process according to the received test signal so as to test the tested device to which the test requirement points.
5. The apparatus of claim 4, wherein the external communication unit comprises:
the second communication interface is used for completing data transmission between the setting module and the debugging module;
and the third communication interface is used for completing data transmission between the test module and the tested equipment.
6. The apparatus of claim 4, wherein the controller comprises:
a second signal processing unit, in communication with the external communication unit, for converting the received test signal into a waveform selection signal, a module selection signal, and a channel selection signal, which are recognized by the debugging module;
the waveform generating unit is used for receiving the waveform selection signal transmitted by the second signal processing unit and generating a waveform pointed by the waveform selection signal, wherein the waveform comprises a logic output waveform or a chopped wave output waveform;
the comprehensive control unit is used for receiving the waveform generated by the waveform generating unit, the module selection signal and the channel selection signal transmitted by the second signal processing unit and determining the communication protocol type and the interface type in the test process according to the module selection signal and the channel selection signal;
and the fault determination unit is used for receiving the fault state signal fed back by the tested equipment, identifying the fault state information of the tested equipment according to the fault state signal and transmitting the fault state information of the tested equipment to the setting module through the comprehensive control unit.
7. The apparatus of claim 6, wherein the controller further comprises:
the communication output unit is communicated with the comprehensive control unit and is used for transmitting the received waveform, the communication protocol type and the interface type determined by the comprehensive control unit to the tested equipment;
and the communication receiving unit is communicated with the tested device and is used for transmitting the received fault feedback signal to the fault judging unit.
8. A universal test method, comprising the steps of:
setting test parameters according to test requirements, and generating test signals according to the set test parameters;
and determining the waveform type, the communication protocol type and the interface type in the test process according to the test signal so as to test the tested equipment pointed by the test requirement, and receiving a fault state signal fed back by the tested equipment.
9. The method of claim 8,
setting test parameters according to test requirements through an adjustable parameter setting interface;
and sending the test signal and receiving the fault state signal fed back by the tested device.
10. The method of claim 9,
setting a waveform type, a communication protocol type and an interface type through a waveform selection interface, a module selection interface and a channel selection interface;
generating the test signal according to the set waveform type, the set communication protocol type and the set interface type, wherein the test signal comprises a waveform selection signal, a module selection signal and a channel selection signal;
and displaying the fault state information of the tested equipment represented by the fault state signal.
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| CN115407184B (en) * | 2021-05-28 | 2024-04-05 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip testing device and method and quantum computer |
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