WO2022052072A1 - Fan-out type packaging structure and production method therefor - Google Patents

Fan-out type packaging structure and production method therefor Download PDF

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Publication number
WO2022052072A1
WO2022052072A1 PCT/CN2020/114904 CN2020114904W WO2022052072A1 WO 2022052072 A1 WO2022052072 A1 WO 2022052072A1 CN 2020114904 W CN2020114904 W CN 2020114904W WO 2022052072 A1 WO2022052072 A1 WO 2022052072A1
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layer
support
chip
fan
package structure
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PCT/CN2020/114904
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French (fr)
Chinese (zh)
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靖向萌
郭茂
耿玉洁
姜青青
洪瑞斌
赵南
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华为技术有限公司
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Priority to CN202080104737.1A priority Critical patent/CN116250081A/en
Priority to PCT/CN2020/114904 priority patent/WO2022052072A1/en
Publication of WO2022052072A1 publication Critical patent/WO2022052072A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present application relates to the technical field of semiconductor packaging, and in particular, to a fan-out packaging structure and a preparation method thereof.
  • the package structure is prone to thermal expansion coefficient mismatch in the environment of temperature change.
  • the problem that the packaging layer such as the underfill (underfill, UF) filled in the region (die gap region) between the two adjacent first chips generates a large stress and breaks, and in severe cases, it will also lead to the re-wiring layer.
  • the insulating layer (the material of the insulating layer may be, for example, polyimide (PI)) has problems such as delamination and breakage of the redistribution layer.
  • the thickness of the redistribution layer is small, the strength in the fan-out package structure is low, and reliability problems such as the rupture of the redistribution layer itself or the rupture of the redistribution layer caused by other failures are prone to occur.
  • forming the first support layer on the redistribution layer includes: first, forming an electroplating seed layer on the redistribution layer; then, forming a photoresist layer on the electroplating seed layer; photoresist The layer is hollowed out in the area where the first support layer is to be formed; after that, the first support layer is formed by electroplating in the hollowed out area of the photoresist layer; finally, the photoresist layer and the electroplating seed layer below it are removed.
  • the first support layer is directly fabricated by electroplating on the redistribution layer, and the fabrication process is simple.
  • 26 is a schematic structural diagram eighteen in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • the metal wire layer 11 in the redistribution layer 1 may further comprise a
  • the conductive contact 111 is close to the side of the first chip 21 , and is in contact with the bonding layer 112 of the first conductive contact 111 , and the first connecting member 3 is in contact with the bonding layer 112 .
  • the first connection member 3 is in contact with the bonding layer 112 , that is, the first connection member 3 is electrically connected to the first conductive contact 111 in the redistribution layer 1 through the bonding layer 112 .
  • step S13 in order to realize the fan-out type structure, it is necessary to further fabricate the second connector 6 and the substrate 7. Based on this, the above-mentioned preparation method of the fan-out type package structure 01 further includes the following steps:
  • the embodiment of the present application controls the fan-out package structure 01 by adjusting the thickness of the first support layer 4A.
  • the thickness of the extruded package structure 01 is simple, the process flow is simple, and the cost is low.

Abstract

Embodiments of the present application relate to the technical field of semiconductor packaging, and provide a fan-out packaging structure and a production method therefor, used for solving the problem of cracking of a packaging layer provided around a first die and the problem of delamination and cracking of a re-distribution layer. The fan-out packaging structure comprises a re-distribution layer, a first die, a first connector, a first support layer, and a packaging layer. The first die is electrically connected to the re-distribution layer by means of the first connector. The first support layer is provided between the first die and the re-distribution layer and is in contact with the re-distribution layer. The packaging layer is provided around the first die, and the packaging layer wraps the first die, the first connector, and the first support layer.

Description

一种扇出型封装结构及其制备方法A kind of fan-out package structure and preparation method thereof 技术领域technical field
本申请涉及半导体封装技术领域，尤其涉及一种扇出型封装结构及其制备方法。The present application relates to the technical field of semiconductor packaging, and in particular, to a fan-out packaging structure and a preparation method thereof.
背景技术Background technique
近年来，集成电路的发展已经进入超大规模集成电路时代。集成电路的封装向更高密度、更高速度、更低成本和更可靠的方向发展。目前的封装方法包括叠层封装(package on package，POP)、倒装第一芯片(flip chip)以及扇出型封装(fan out package，FOP)等。其中，扇出型封装结构中第一芯片(die)与基板之间通过重新布线层(re-distribution layer，RDL)互连，可以实现互连密度的更大化和更高带宽。In recent years, the development of integrated circuits has entered the era of very large-scale integrated circuits. The packaging of integrated circuits is developing towards higher density, higher speed, lower cost and more reliability. Current packaging methods include package on package (POP), flip chip (flip chip), and fan out package (FOP). Among them, in the fan-out package structure, the first chip (die) and the substrate are interconnected through a re-distribution layer (RDL), which can achieve greater interconnection density and higher bandwidth.
然而，由于扇出型封装结构中第一芯片的热膨胀系数(coefficient of thermal expansion，CTE)低，基板的热膨胀系数高，因而在温度变化的环境中，该封装结构容易出现因热膨胀系数失配导致的填充在相邻两个第一芯片之间的区域(die gap区域)的封装层例如底部填充胶(under fill，UF)产生较大应力而断裂的问题，严重时还会导致重新布线层中绝缘层(绝缘层的材料例如可以为聚酰亚胺(polyimide，PI))出现脱层(delamination)现象以及重新布线层断裂等问题。此外，重新布线层的厚度较小，在扇出型封装结构中的强度较低，易发生重新布线层自身断裂或因其他失效而导致的重新布线层断裂等可靠性问题。However, due to the low coefficient of thermal expansion (CTE) of the first chip and the high thermal expansion coefficient of the substrate in the fan-out package structure, the package structure is prone to thermal expansion coefficient mismatch in the environment of temperature change. The problem that the packaging layer such as the underfill (underfill, UF) filled in the region (die gap region) between the two adjacent first chips generates a large stress and breaks, and in severe cases, it will also lead to the re-wiring layer. The insulating layer (the material of the insulating layer may be, for example, polyimide (PI)) has problems such as delamination and breakage of the redistribution layer. In addition, the thickness of the redistribution layer is small, the strength in the fan-out package structure is low, and reliability problems such as the rupture of the redistribution layer itself or the rupture of the redistribution layer caused by other failures are prone to occur.
发明内容SUMMARY OF THE INVENTION
本申请实施例提供一种扇出型封装结构及其制备方法，用于解决填充在第一芯片周围的封装层因热膨胀系数失配导致的断裂的问题以及重新布线层脱层、断裂的问题。Embodiments of the present application provide a fan-out package structure and a manufacturing method thereof, which are used to solve the problem of breakage of the package layer filled around the first chip due to thermal expansion coefficient mismatch and the problems of delamination and breakage of the rewiring layer.
为达到上述目的，本申请采用如下技术方案：To achieve the above object, the application adopts the following technical solutions:
第一方面，提供一种扇出型封装结构。该扇出型封装结构包括：重新布线层；第一芯片；第一连接件；第一芯片通过第一连接件与重新布线层电连接；设置在第一芯片与重新布线层之间，且与重新布线层接触的第一支撑层；填充于第一芯片周围的封装层；封装层包裹第一芯片、第一连接件以及第一支撑层。由于第一芯片和重新布线层之间设置有第一支撑层，而第一支撑层可以增加局部区域的结构强度，降低填充在第一芯片周围的封装层因扇出型封装结构中不同部分的热膨胀系数不匹配产生的应力，从而避免了填充在第一芯片周围的封装层断裂，且避免了重新布线层断裂以及重新布线层出现脱层现象，提升了扇出型封装结构的整体可靠性。In a first aspect, a fan-out package structure is provided. The fan-out package structure includes: a rewiring layer; a first chip; a first connecting member; the first chip is electrically connected to the rewiring layer through the first connecting member; A first support layer contacted by the redistribution layer; an encapsulation layer filled around the first chip; the encapsulation layer wraps the first chip, the first connector and the first support layer. Since the first support layer is arranged between the first chip and the rewiring layer, the first support layer can increase the structural strength of the local area, and reduce the impact of the packaging layer filled around the first chip due to different parts of the fan-out packaging structure. The stress generated by the mismatch of thermal expansion coefficients avoids the breakage of the package layer filled around the first chip, and avoids the breakage of the rewiring layer and the delamination phenomenon of the rewiring layer, which improves the overall reliability of the fan-out package structure.
在一种可能的实现方式中，扇出型封装结构中设置的第一支撑层的材料强度大于封装层的材料强度。这样可以确保第一支撑层能够起到支撑作用。此外，相对于扇出型封装结构不包括第一支撑层时，第一芯片和重新布线层之间通过封装层起支撑作用，由于本申请实施例中设置有第一支撑层，因而可以降低填充在第一芯片和重新布线层之间的封装层的厚度，即降低整个封装层的厚度，且可以通过调整第一支撑层的厚度来控制扇出型封装结构的厚度。相对于通过其它方法调整扇出型封装结构的厚度例如通过调整第一芯片的厚度来调整扇出型封装结构的厚度，本申请实施例通过调整第一支撑层的厚度来控制扇出型封装结构的厚度，工艺流程简单，成本较低。In a possible implementation manner, the material strength of the first support layer provided in the fan-out package structure is greater than the material strength of the package layer. This ensures that the first support layer can play a supporting role. In addition, when the fan-out package structure does not include the first support layer, the package layer plays a supporting role between the first chip and the rewiring layer. Since the first support layer is provided in the embodiment of the present application, the filling can be reduced. The thickness of the encapsulation layer between the first chip and the rewiring layer, ie, the thickness of the entire encapsulation layer is reduced, and the thickness of the fan-out package structure can be controlled by adjusting the thickness of the first support layer. Compared with adjusting the thickness of the fan-out package structure by other methods, such as adjusting the thickness of the fan-out package structure by adjusting the thickness of the first chip, the embodiment of the present application controls the fan-out package structure by adjusting the thickness of the first support layer The thickness is simple, the process is simple, and the cost is low.
在一种可能的实施方式中，扇出型封装结构还包括第二芯片；第一支撑层包括第一支撑部分，第一支撑部分位于第一芯片和第二芯片之间的区域。由于随着温度变化，扇出型封装结构中不同部分热膨胀系数失配会导致填充在第一芯片和第二芯片之间的区域的封装层产生较大的应力，因而在位于第一芯片和第二芯片之间的区域设置第一支撑部分，可以增加第一芯片和第二芯片之间的区域的结构强度和抗拉能力，降低第一芯片和第二芯片之间的区域的应力，提升封装结构的可靠性。In a possible implementation manner, the fan-out package structure further includes a second chip; the first support layer includes a first support portion, and the first support portion is located in a region between the first chip and the second chip. As the temperature changes, the thermal expansion coefficient mismatch of different parts in the fan-out package structure will lead to greater stress on the package layer filled in the area between the first chip and the second chip. The first support part is arranged in the area between the two chips, which can increase the structural strength and tensile strength of the area between the first chip and the second chip, reduce the stress in the area between the first chip and the second chip, and improve the packaging. structural reliability.
在一种可能的实施方式中，第一支撑层包括第一支撑部分，第一支撑部分包围第一芯片。由于第一支撑部分包围第一芯片，因而可以增加第一芯片周围的区域的结构强度和抗拉能力，降低第一芯片周围填充的封装层因扇出型封装结构中不同部分热膨胀系数失配产生的应力。In a possible implementation, the first support layer includes a first support portion, and the first support portion surrounds the first chip. Since the first support part surrounds the first chip, the structural strength and tensile strength of the area around the first chip can be increased, and the packaging layer filled around the first chip can be reduced due to the mismatch of thermal expansion coefficients of different parts in the fan-out package structure. stress.
在一种可能的实施方式中，第一支撑层还包括第二支撑部分；第二支撑部分包括多个平行排布的第一支撑条和多个平行排布的第二支撑条；多个第一支撑条和多个第二支撑条相交；第二支撑部分位于第一芯片的正下方，且第一连接件在重新布线层上的正投影与第二支撑部分在重新布线层上的正投影无重叠区域。由于第一支撑层包括第二支撑部分，第二支撑部分位于第一芯片的正下方，因而可以增加第一芯片正下方的结构强度和抗拉能力，降低第一芯片正下方填充的封装层因扇出型封装结构中不同部分热膨胀系数失配产生的应力，进一步提升封装结构的可靠性。In a possible embodiment, the first support layer further includes a second support portion; the second support portion includes a plurality of first support bars arranged in parallel and a plurality of second support bars arranged in parallel; a plurality of first support bars A support bar intersects with a plurality of second support bars; the second support portion is located directly under the first chip, and the orthographic projection of the first connector on the redistribution layer and the orthographic projection of the second support portion on the redistribution layer No overlapping areas. Since the first support layer includes the second support portion, and the second support portion is located directly under the first chip, the structural strength and tensile strength directly under the first chip can be increased, and the encapsulation layer filled directly under the first chip can be reduced. The stress caused by the mismatch of thermal expansion coefficients of different parts in the fan-out package structure further improves the reliability of the package structure.
在一种可能的实施方式中，扇出型封装结构还包括设置在第一支撑层远离重新布线层一侧，且与第一支撑层接触的第二支撑层；第二支撑层包括第三支撑部分，第三支撑部分位于第一芯片和第二芯片之间的区域。由于位于第一芯片和第二芯片之间的区域设置有第一支撑部分和第三支撑部分，因而可以进一步增加位于第一芯片和第二芯片之间的区域的结构强度，更有利于降低第一芯片和第二芯片之间的区域填充的封装层因扇出型封装结构中不同部分热膨胀系数失配产生的应力。In a possible implementation, the fan-out package structure further includes a second support layer disposed on the side of the first support layer away from the redistribution layer and in contact with the first support layer; the second support layer includes a third support layer part, the third support part is located in the area between the first chip and the second chip. Since the region between the first chip and the second chip is provided with the first support portion and the third support portion, the structural strength of the region between the first chip and the second chip can be further increased, which is more conducive to reducing the The area between one chip and the second chip fills the encapsulation layer due to the stress caused by the mismatch of thermal expansion coefficients of different parts in the fan-out package structure.
在一种可能的实施方式中，扇出型封装结构还包括设置在第一支撑层远离重新布线层一侧，且与第一支撑层接触的第二支撑层；第二支撑层包括第三支撑部分，第三支撑部分包围第一芯片。由于层叠的第一支撑部分和第三支撑部分包围第一芯片，因而可以进一步增加第一芯片周围的区域的结构强度。In a possible implementation, the fan-out package structure further includes a second support layer disposed on the side of the first support layer away from the redistribution layer and in contact with the first support layer; the second support layer includes a third support layer part, the third support part surrounds the first chip. Since the laminated first support part and the third support part surround the first chip, the structural strength of the area around the first chip can be further increased.
在一种可能的实施方式中，扇出型封装结构还包括设置在第一支撑层远离重新布线层一侧，且与第一支撑层接触的第二支撑层；第二支撑层包括第四支撑部分，第四支撑部分包括多个平行排布的第三支撑条和多个平行排布的第四支撑条；多个第三支撑条和多个第四支撑条相交；第四支撑部分位于第一芯片的正下方，且第一连接件在重新布线层上的正投影与第四支撑部分在重新布线层上的正投影无重叠区域。由于扇出型封装结构包括层叠的第二支撑部分和第四支撑部分，因而可以进一步增加第一芯片正下方的结构强度和抗拉能力。In a possible implementation manner, the fan-out package structure further includes a second support layer disposed on the side of the first support layer away from the redistribution layer and in contact with the first support layer; the second support layer includes a fourth support layer part, the fourth support part includes a plurality of third support bars arranged in parallel and a plurality of fourth support bars arranged in parallel; the plurality of third support bars and the plurality of fourth support bars intersect; the fourth support part is located in the Right under a chip, and the orthographic projection of the first connection member on the redistribution layer and the orthographic projection of the fourth support portion on the redistribution layer have no overlapping area. Since the fan-out package structure includes the stacked second support portion and the fourth support portion, the structural strength and tensile strength directly under the first chip can be further increased.
在一种可能的实施方式中，重新布线层包括第一导电接点；第一连接件与第一导电接点电连接；第一支撑层与第一导电接点同层同材料。此处，可以同时制作第一支撑层和第一导电接点，从而简化了扇出型封装结构的制作工艺。In a possible implementation manner, the redistribution layer includes a first conductive contact; the first connector is electrically connected to the first conductive contact; the first support layer and the first conductive contact are of the same layer and the same material. Here, the first support layer and the first conductive contact can be fabricated at the same time, thereby simplifying the fabrication process of the fan-out package structure.
在一种可能的实施方式中，扇出型封装结构还包括设置在第一支撑层与重新布线层之间的粘着层。此处，可以通过粘着层将第一支撑层与重新布线层固定。In a possible implementation, the fan-out package structure further includes an adhesive layer disposed between the first support layer and the redistribution layer. Here, the first support layer and the redistribution layer may be fixed by the adhesive layer.
在一种可能的实施方式中，第一支撑层导电；重新布线层包括接地端子；第一支撑层与重新布线层中的接地端子电连接。第一支撑层通过重新布线层互连接地，第一支撑层相当于一个地平面，可以将第一芯片的信号与重新布线层的信号有效隔离，这样一来，可以提高信号质量，提升扇出型封装结构的电性能。In a possible implementation, the first support layer is electrically conductive; the redistribution layer includes a ground terminal; and the first support layer is electrically connected to the ground terminal in the redistribution layer. The first support layer is connected to the ground through the rewiring layer. The first support layer is equivalent to a ground plane, which can effectively isolate the signal of the first chip from the signal of the rewiring layer. In this way, the signal quality can be improved and the fan-out can be improved. electrical properties of the package structure.
在一种可能的实施方式中，扇出型封装结构还包括设置在重新布线层远离第一芯片一侧的第二连接件以及基板；第二连接件将重新布线层与基板电连接，这样一来可以实现扇出型封装。In a possible implementation manner, the fan-out package structure further includes a second connection member and a substrate disposed on the side of the redistribution layer away from the first chip; the second connection member electrically connects the redistribution layer and the substrate, so that a to achieve fan-out packaging.
在一种可能的实施方式中，封装层的材料包括模塑化合物；或者，封装层包括第一子封装层和第二子封装层；第一子封装层包围第一芯片，第二子封装层包围第一子封装层；第一子封装层的材料为底胶化合物，第二子封装层的材料为模塑化合物。In a possible implementation, the material of the encapsulation layer includes a molding compound; or, the encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer; the first sub-encapsulation layer surrounds the first chip, and the second sub-encapsulation layer Surrounding the first sub-encapsulation layer; the material of the first sub-encapsulation layer is a primer compound, and the material of the second sub-encapsulation layer is a molding compound.
第二方面，提供一种电子设备。该电子设备包括前述的扇出型封装结构和印刷电路板；扇出型封装结构包括基板和第三连接件，第三连接件设置在基板远离重新布线层的一侧，基板通过第三连接件与印刷电路板电连接。该电子设备具有与前述实施例相同的技术效果，此处不再赘述。In a second aspect, an electronic device is provided. The electronic device includes the aforementioned fan-out package structure and a printed circuit board; the fan-out package structure includes a substrate and a third connector, the third connector is disposed on the side of the substrate away from the redistribution layer, and the substrate passes through the third connector Electrically connected to the printed circuit board. The electronic device has the same technical effects as the foregoing embodiments, which will not be repeated here.
第三方面，提供一种扇出型封装结构的制备方法。该扇出型封装结构的制备方法包括如下流程：首先，在重新布线层上形成第一支撑层；然后，通过第一连接件将第一芯片绑定到重新布线层上，以使第一芯片与重新布线层电连接；最后，填充封装层；封装层包裹第一芯片、第一连接件以及第一支撑层。由于第一芯片和重新布线层之间形成有第一支撑层，而第一支撑层可以增加局部区域的结构强度，降低填充在第一芯片周围的封装层因扇出型封装结构中不同部分的热膨胀系数不匹配产生的应力，从而避免了填充在第一芯片周围的封装层断裂，且避免了重新布线层断裂以及重新布线层出现脱层现象。In a third aspect, a method for fabricating a fan-out package structure is provided. The preparation method of the fan-out package structure includes the following steps: first, forming a first support layer on the redistribution layer; then, binding the first chip to the redistribution layer through a first connector, so that the first chip It is electrically connected with the redistribution layer; finally, the encapsulation layer is filled; the encapsulation layer wraps the first chip, the first connector and the first support layer. Since the first support layer is formed between the first chip and the rewiring layer, the first support layer can increase the structural strength of the local area and reduce the impact of the package layer filled around the first chip due to different parts of the fan-out package structure. The stress generated by the mismatch of the thermal expansion coefficients prevents the package layer filled around the first chip from being broken, and avoids the breakage of the redistribution layer and the delamination phenomenon of the redistribution layer.
在一种可能的实施方式中，在重新布线层上形成第一支撑层，包括：首先，在重新布线层上形成电镀种子层；然后，在电镀种子层上形成光刻胶层；光刻胶层在待形成第一支撑层的区域镂空；之后，在光刻胶层的镂空区域内电镀形成第一支撑层；最后，去除光刻胶层及其下方的电镀种子层。此处，直接在重新布线层上电镀制作第一支撑层，制作工艺简单。In a possible implementation manner, forming the first support layer on the redistribution layer includes: first, forming an electroplating seed layer on the redistribution layer; then, forming a photoresist layer on the electroplating seed layer; photoresist The layer is hollowed out in the area where the first support layer is to be formed; after that, the first support layer is formed by electroplating in the hollowed out area of the photoresist layer; finally, the photoresist layer and the electroplating seed layer below it are removed. Here, the first support layer is directly fabricated by electroplating on the redistribution layer, and the fabrication process is simple.
在一种可能的实施方式中，在重新布线层上形成第一支撑层，包括：首先，在载板上形成支撑薄膜；然后，在支撑薄膜上贴附胶膜；之后，对支撑薄膜和胶膜进行构图，形成第一支撑层和粘着层；第一支撑层和粘着层在载板上的正投影重叠；最后，将第一支撑层和粘着层移动到重新布线层上，并移除载板；其中，第一支撑层通过粘着层粘贴在重新布线层上。通过粘着层将第一支撑层粘贴在重新布线层上，避免了在重新布线层上直接制作第一支撑层导致的重新布线层受到破坏。In a possible implementation manner, forming the first support layer on the redistribution layer includes: first, forming a support film on the carrier; then, attaching an adhesive film on the support film; The film is patterned to form the first support layer and the adhesion layer; the orthographic projections of the first support layer and the adhesion layer on the carrier plate overlap; finally, the first support layer and the adhesion layer are moved to the redistribution layer, and the carrier is removed. board; wherein the first support layer is pasted on the redistribution layer through an adhesive layer. The first support layer is pasted on the redistribution layer through the adhesive layer, so as to avoid damage to the redistribution layer caused by directly fabricating the first support layer on the redistribution layer.
在一种可能的实施方式中，在重新布线层上形成第一支撑层，包括：在重新布线层上形成第一支撑层，并同步形成重新布线层的第一导电接点，第一连接件与第一导电接点电连接。第一支撑层与第一导电接点同步制作，从而可以简化扇出型封装结构的制备方法。In a possible implementation manner, forming the first support layer on the redistribution layer includes: forming the first support layer on the redistribution layer, and simultaneously forming a first conductive contact of the redistribution layer, and the first connection member is connected to the redistribution layer. The first conductive contact is electrically connected. The first support layer and the first conductive contact are fabricated simultaneously, so that the fabrication method of the fan-out package structure can be simplified.
在一种可能的实施方式中，填充封装层，包括：通过塑模底部填充工艺填充封装层；或者，通过毛细底部填充工艺填充第一子封装层；第一子封装层包围第一芯片； 通过塑模底部填充工艺填充第二子封装层；第二子封装层包围第一子封装层；其中，封装层包括第一子封装层和第二子封装层。In a possible implementation manner, filling the encapsulation layer includes: filling the encapsulation layer through a molding underfill process; or, filling the first sub-encapsulation layer through a capillary underfill process; the first sub-encapsulation layer surrounds the first chip; The mold underfill process fills the second sub-encapsulation layer; the second sub-encapsulation layer surrounds the first sub-encapsulation layer; wherein the encapsulation layer includes the first sub-encapsulation layer and the second sub-encapsulation layer.
在一种可能的实施方式中，在填充封装层之后，扇出型封装结构的制备方法还包括：在重新布线层远离第一芯片的一侧形成与重新布线层电连接的第二连接件，并将第二连接件与基板电连接，这样一来可以实现扇出型封装。In a possible implementation manner, after the encapsulation layer is filled, the preparation method of the fan-out encapsulation structure further includes: forming a second connector electrically connected to the redistribution layer on the side of the redistribution layer away from the first chip, The second connector is electrically connected to the substrate, so that a fan-out package can be realized.
附图说明Description of drawings
图1为本申请的实施例提供的一种扇出型封装结构的俯视图；1 is a top view of a fan-out package structure according to an embodiment of the present application;
图2为本申请的实施例提供的图1中AA向的剖视示意图；2 is a schematic cross-sectional view of the AA direction in FIG. 1 provided for an embodiment of the application;
图3为本申请的另一实施例提供的图1中AA向的剖视示意图；FIG. 3 is a schematic cross-sectional view along the AA direction in FIG. 1 provided for another embodiment of the application;
图4a为本申请的又一实施例提供的图1中AA向的剖视示意图；FIG. 4a is a schematic cross-sectional view along the AA direction in FIG. 1 provided by another embodiment of the application;
图4b为本申请的再一实施例提供的图1中AA向的剖视示意图；FIG. 4b is a schematic cross-sectional view along the AA direction in FIG. 1 provided by yet another embodiment of the application;
图5为本申请的另一实施例提供的一种扇出型封装结构的俯视图；5 is a top view of a fan-out package structure according to another embodiment of the present application;
图6为本申请的另一实施例提供的图1中AA向的剖视示意图；FIG. 6 is a schematic cross-sectional view along the AA direction in FIG. 1 provided for another embodiment of the application;
图7为本申请的实施例提供的一种第一芯片与第一支撑层的结构示意图；7 is a schematic structural diagram of a first chip and a first support layer according to an embodiment of the present application;
图8为本申请的另一实施例提供的一种第一芯片与第一支撑层的结构示意图；8 is a schematic structural diagram of a first chip and a first support layer according to another embodiment of the present application;
图9为本申请的实施例提供的一种第一芯片、第一支撑层与第一连接件的结构示意图；FIG. 9 is a schematic structural diagram of a first chip, a first support layer and a first connector according to an embodiment of the present application;
图10为本申请的又一实施例提供的图1中AA向的剖视示意图；FIG. 10 is a schematic cross-sectional view along the AA direction in FIG. 1 provided for another embodiment of the application;
图11为本申请的再一实施例提供的图1中AA向的剖视示意图；FIG. 11 is a schematic cross-sectional view along the AA direction in FIG. 1 provided by yet another embodiment of the application;
图12为本申请的实施例提供的一种扇出型封装结构的制备方法的流程示意图；12 is a schematic flowchart of a method for fabricating a fan-out package structure provided by an embodiment of the present application;
图13为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图一；13 is a first structural schematic diagram in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图14a为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图二；14a is a second structural schematic diagram in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图14b为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图三；FIG. 14b is a third structural schematic diagram in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图14c为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图四；14c is a fourth schematic structural diagram during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图15为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图五；FIG. 15 is a schematic structural diagram V during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图16a为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图六；16a is a sixth schematic structural diagram in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图16b为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图七；16b is a seventh structural schematic diagram during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图16c为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图八；16c is a schematic structural diagram eight in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图17为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图九；17 is a schematic structural diagram 9 in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图18为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示 意图十；Figure 18 is a schematic structural diagram ten in the process of a preparation method of a fan-out package structure provided by an embodiment of the application;
图19为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十一；FIG. 19 is a schematic structural diagram eleven in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图20为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十二；FIG. 20 is a schematic structural diagram 12 during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图21为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十三；21 is a schematic structural diagram thirteen during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the application;
图22为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十四；FIG. 22 is a schematic structural diagram fourteen during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图23为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十五；FIG. 23 is a fifteenth schematic structural diagram in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图24为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十六；24 is a schematic structural diagram sixteen during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图25为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十七；FIG. 25 is a schematic structural diagram seventeen during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图26为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十八；26 is a schematic structural diagram eighteen in the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图27为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图十九；27 is a nineteenth structural schematic diagram during the process of a method for manufacturing a fan-out package structure provided by an embodiment of the present application;
图28为本申请的实施例提供的一种扇出型封装结构的制备方法过程中的结构示意图二十。FIG. 28 is a schematic structural diagram 20 during the process of a method for fabricating a fan-out package structure provided by an embodiment of the present application.
附图标记：Reference number:
01-扇出型封装结构；1-重新布线层；21-第一芯片；22-第二芯片；23-第三芯片；24-第四芯片；3-第一连接件；4A-第一支撑层；4B-第二支撑层；5-封装层；6-第二连接件；7-基板；8-第三连接件；9-粘着层；10-底板；11-金属线层；12-绝缘层；13-电镀种子层；14-光刻胶层；15-载板；16-支撑薄膜；17-胶膜；31a-第一金属柱；31b-第一凸点下金属层；32-第一凸块；41-第一支撑部分；42-第二支撑部分；43-第三支撑部分；51-第一子封装层；52-第二子封装层；61a-第二金属柱；61b-第二凸点下金属层；62-第二凸块；111-第一导电接点；112-键合层；113-第二导电接点；114-接地端子；421-第一支撑条；422-第二支撑条。01-fan-out package structure; 1-rewiring layer; 21-first chip; 22-second chip; 23-third chip; 24-fourth chip; 3-first connector; 4A-first support layer; 4B-second support layer; 5-encapsulation layer; 6-second connection piece; 7-substrate; 8-third connection piece; 9-adhesion layer; 10-base plate; 11-metal wire layer; 12-insulation layer; 13-electroplating seed layer; 14-photoresist layer; 15-carrier plate; 16-support film; 17-adhesive film; 31a-first metal post; 31b-first metal layer under bump; A bump; 41-first support part; 42-second support part; 43-third support part; 51-first sub-package layer; 52-second sub-package layer; 61a-second metal pillar; 61b- 62-second bump; 111-first conductive contact; 112-bonding layer; 113-second conductive contact; 114-ground terminal; 421-first support bar; 422-th Two support bars.
具体实施方式detailed description
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。Hereinafter, the terms "first", "second", etc. are only used for convenience of description, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second", etc., may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more.
此外，本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相 对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。In addition, in the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to be defined relative to the schematic placement of components in the drawings, and it should be understood that these directional terms may be relative concept, they are used for relative description and clarification, which may change accordingly according to the change in the orientation in which the components are placed in the drawings.
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。In this application, unless otherwise expressly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary. In addition, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
本申请实施例提供一种扇出型封装结构，如图1和图2所示，该扇出型封装结构01主要包括重新布线层1、第一芯片(芯片也可以称为裸芯片)21、第一连接件3、第一支撑层(supporting layer)4A以及封装层5。其中，第一芯片21通过第一连接件3与重新布线层1电连接。第一支撑层4A设置在第一芯片21和重新布线层1之间，且与重新布线层1接触。封装层5填充于第一芯片21周围，且封装层5包裹第一芯片21、第一连接件3以及第一支撑层4A。An embodiment of the present application provides a fan-out package structure. As shown in FIG. 1 and FIG. 2 , the fan-out package structure 01 mainly includes a rewiring layer 1 , a first chip (the chip may also be referred to as a bare chip) 21 , The first connector 3 , the first supporting layer 4A and the encapsulation layer 5 . The first chip 21 is electrically connected to the redistribution layer 1 through the first connecting member 3 . The first support layer 4A is provided between the first chip 21 and the rewiring layer 1 and is in contact with the rewiring layer 1 . The encapsulation layer 5 is filled around the first chip 21 , and the encapsulation layer 5 wraps the first chip 21 , the first connector 3 and the first support layer 4A.
在一些实施例中，为了实现扇出型封装，上述扇出型封装结构01还包括第二连接件6和基板7，重新布线层1通过第二连接件6与基板7电连接，以将第一芯片21与基板7电连接。In some embodiments, in order to implement a fan-out package, the above-mentioned fan-out package structure 01 further includes a second connector 6 and a substrate 7 , and the redistribution layer 1 is electrically connected to the substrate 7 through the second connector 6 to connect the first connector 6 to the substrate 7 . A chip 21 is electrically connected to the substrate 7 .
本申请实施例还提供一种电子设备，该电子设备包括上述的扇出型封装结构01和印刷电路板(printed circuit board，PCB)。在需要将上述基板7与印刷电路板电连接时，参考图2所示，扇出型封装结构01还包括设置在基板7远离重新布线层1一侧的第三连接件8，基板7通过第三连接件8与印刷电路板电连接。An embodiment of the present application further provides an electronic device, which includes the above-mentioned fan-out package structure 01 and a printed circuit board (printed circuit board, PCB). When it is necessary to electrically connect the above-mentioned substrate 7 to the printed circuit board, as shown in FIG. 2 , the fan-out package structure 01 further includes a third connector 8 disposed on the side of the substrate 7 away from the redistribution layer 1 , and the substrate 7 passes through the The three connectors 8 are electrically connected to the printed circuit board.
可选的，该电子设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备。Optionally, the electronic device is different types of user equipment or terminal equipment such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device.
附图1中部分层例如重新布线层1、第二连接件6以及第三连接件8因被遮挡未示意出。附图1和图2中均未示意出印刷电路板。In FIG. 1 , some layers such as the redistribution layer 1 , the second connecting member 6 and the third connecting member 8 are not shown because they are blocked. A printed circuit board is not shown in both Figures 1 and 2 .
此处，上述重新布线层1包括一层或多层金属线层11和一层或多层绝缘层12。示例的，金属线层11的材料包括但不限于铜、铝、镍、金、银、钛中的一种材料或两种及两种以上的组合材料。绝缘层12的材料包括但不限于氧化硅、氮化硅、氮氧化硅、硅胶、聚酰亚胺中的一种材料或两种及两种以上的组合材料。Here, the above-mentioned redistribution layer 1 includes one or more metal wire layers 11 and one or more insulating layers 12 . Exemplarily, the material of the metal wire layer 11 includes, but is not limited to, one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials. The material of the insulating layer 12 includes, but is not limited to, one of silicon oxide, silicon nitride, silicon oxynitride, silica gel, and polyimide, or a combination of two or more materials.
上述“第一芯片21通过第一连接件3与重新布线层1电连接”即第一芯片21通过第一连接件3与重新布线层1中的金属线层11电连接。上述“重新布线层1通过第二连接件6与基板7电连接”即重新布线层1中的金属线层11通过第二连接线6与基板7电连接。The above-mentioned “the first chip 21 is electrically connected to the redistribution layer 1 through the first connecting member 3 ” means that the first chip 21 is electrically connected to the metal wire layer 11 in the redistribution layer 1 through the first connecting member 3 . The above-mentioned “the redistribution layer 1 is electrically connected to the substrate 7 through the second connecting member 6 ” means that the metal wire layer 11 in the redistribution layer 1 is electrically connected to the substrate 7 through the second connection wire 6 .
在此基础上，在重新布线层1包括一层金属线层11的情况下，金属线层11的上表面露出于绝缘层12的上表面，金属线层11的下表面露出于绝缘层12的下表面。在重新布线层1包括多层金属线层11和多层绝缘层12的情况下，位于顶层的金属线层11的上表面露出于顶层的绝缘层12的上表面，位于底层的金属线层11的下表面露出于底层的绝缘层12的下表面。此外，“金属线层11的上表面露出于绝缘层12的上表面”可以是金属线层11的上表面与绝缘层12的上表面平齐；也可以是金属线层11的上表面高出于绝缘层12的上表面；当然还可以是，金属线层11的上表面低于绝缘层12的上表面。“金属线层11的下表面露出于绝缘层12的下表面”可以是金属线层 11的下表面与绝缘层12的下表面平齐；也可以是金属线层11的下表面高出于绝缘层12的下表面；当然还可以是，金属线层11的下表面低于绝缘层12的下表面。本申请实施例附图中金属线层11的上表面露出于绝缘层12的上表面均以金属线层11的上表面高于绝缘层12的上表面为例进行示意，金属线层11的下表面露出于绝缘层12的下表面均以金属线层11的下表面与绝缘层12的下表面平齐为例进行示意。On this basis, when the redistribution layer 1 includes a metal wire layer 11 , the upper surface of the metal wire layer 11 is exposed to the upper surface of the insulating layer 12 , and the lower surface of the metal wire layer 11 is exposed to the insulating layer 12 . lower surface. In the case where the redistribution layer 1 includes the multi-layer metal wire layer 11 and the multi-layer insulating layer 12, the upper surface of the metal wire layer 11 on the top layer is exposed to the upper surface of the insulating layer 12 on the top layer, and the metal wire layer 11 on the bottom layer is exposed. The lower surface of the bottom layer is exposed to the lower surface of the insulating layer 12 of the bottom layer. In addition, "the upper surface of the metal wire layer 11 is exposed on the upper surface of the insulating layer 12" may mean that the upper surface of the metal wire layer 11 is flush with the upper surface of the insulating layer 12; or the upper surface of the metal wire layer 11 may be higher than the upper surface of the insulating layer 12. On the upper surface of the insulating layer 12 ; of course, the upper surface of the metal wire layer 11 may be lower than the upper surface of the insulating layer 12 . "The lower surface of the metal wire layer 11 is exposed to the lower surface of the insulating layer 12" may mean that the lower surface of the metal wire layer 11 is flush with the lower surface of the insulating layer 12; it may also be that the lower surface of the metal wire layer 11 is higher than the insulating layer 12. The lower surface of the layer 12 ; of course, the lower surface of the metal wire layer 11 may be lower than the lower surface of the insulating layer 12 . In the drawings of the embodiments of the present application, the upper surface of the metal wire layer 11 is exposed to the upper surface of the insulating layer 12, and the upper surface of the metal wire layer 11 is higher than the upper surface of the insulating layer 12 for illustration. The surfaces exposed to the lower surface of the insulating layer 12 are all illustrated by taking an example that the lower surface of the metal wire layer 11 is flush with the lower surface of the insulating layer 12 .
在一些示例中，如图2和图3所示，重新布线层1中的金属线层11包括露出于绝缘层12上表面的第一导电接点(under bump metallization pad，UBM pad或μpad)111；第一连接件3与第一导电接点111电连接。上述“第一芯片21通过第一连接件3与重新布线层1电连接”即第一芯片21通过第一连接件3与重新布线层1中的第一导电接点111电连接。为了确保第一连接件3与第一导电接点111连接的更牢靠，在一些实施例中，如图4a和图4b所示，重新布线层1中的金属线层11还可以包括设置在第一导电接点111靠近第一芯片21一侧，且与第一导电接点111接触的键合层112，第一连接件3与键合层112接触。第一连接件3与键合层112接触，即第一连接件3通过键合层112与重新布线层1中的第一导电接点111电连接。In some examples, as shown in FIGS. 2 and 3 , the metal wire layer 11 in the redistribution layer 1 includes a first conductive contact (under bump metallization pad, UBM pad or μpad) 111 exposed on the upper surface of the insulating layer 12; The first connector 3 is electrically connected to the first conductive contact 111 . The above-mentioned “the first chip 21 is electrically connected to the redistribution layer 1 through the first connection member 3 ” means that the first chip 21 is electrically connected to the first conductive contact 111 in the redistribution layer 1 through the first connection member 3 . In order to ensure a more reliable connection between the first connector 3 and the first conductive contact 111, in some embodiments, as shown in FIG. 4a and FIG. 4b, the metal wire layer 11 in the redistribution layer 1 may further comprise a The conductive contact 111 is close to the side of the first chip 21 , and is in contact with the bonding layer 112 of the first conductive contact 111 , and the first connecting member 3 is in contact with the bonding layer 112 . The first connection member 3 is in contact with the bonding layer 112 , that is, the first connection member 3 is electrically connected to the first conductive contact 111 in the redistribution layer 1 through the bonding layer 112 .
在一些示例中，如图2和图3所示，重新布线层1中的金属线层11还包括露出于绝缘层12下表面的第二导电接点113，第二连接件6与第二导电接点113接触。上述“重新布线层1通过第二连接件6与基板7电连接”即重新布线层1中的第二导电接点113通过第二连接件6与基板7电连接。In some examples, as shown in FIG. 2 and FIG. 3 , the metal wire layer 11 in the redistribution layer 1 further includes a second conductive contact 113 exposed on the lower surface of the insulating layer 12 , and the second connection member 6 is connected to the second conductive contact 113 contacts. The above-mentioned “the redistribution layer 1 is electrically connected to the substrate 7 through the second connecting member 6 ” means that the second conductive contact 113 in the redistribution layer 1 is electrically connected to the substrate 7 through the second connecting member 6 .
对于上述第一连接件3的结构，例如，如图4a所示，第一连接件3包括第一金属柱31a以及设置在第一金属柱31a靠近重新布线层1一侧，且与第一金属柱31a接触的第一凸块(bump)32。又例如，如图4b所示，第一连接件3包括第一凸点下金属层(或者称作第一焊盘)31b以及设置在第一凸点下金属层31b靠近重新布线层1一侧，且与第一凸点下金属层31b接触的第一凸块32。基于此，第一连接件3与重新布线层1电连接，即第一凸块32与重新布线层1电连接，例如第一凸块32与重新布线层1中的键合层112接触。其中，第一金属柱31a或第一凸点下金属层31b作为第一芯片21内部集成的功能电路的引脚，与第一芯片21内部集成的功能电路电连接。此外，设置的第一金属柱31a或第一凸点下金属层31b还可以起到提高第一凸块32与第一芯片21内部集成的功能电路连接的可靠性的作用。For the structure of the first connecting member 3, for example, as shown in FIG. 4a, the first connecting member 3 includes a first metal pillar 31a and is disposed on the side of the first metal pillar 31a close to the redistribution layer 1 and is connected to the first metal pillar 31a. The first bump 32 that the pillar 31a contacts. For another example, as shown in FIG. 4b, the first connector 3 includes a first under-bump metal layer (or called a first pad) 31b and a side of the first under-bump metal layer 31b close to the redistribution layer 1 , and the first bump 32 in contact with the first under-bump metal layer 31b. Based on this, the first connector 3 is electrically connected to the redistribution layer 1 , that is, the first bump 32 is electrically connected to the redistribution layer 1 , for example, the first bump 32 is in contact with the bonding layer 112 in the redistribution layer 1 . The first metal pillar 31 a or the first metal layer under bump 31 b is used as a pin of the functional circuit integrated inside the first chip 21 , and is electrically connected to the functional circuit integrated inside the first chip 21 . In addition, the provided first metal pillar 31 a or the first metal layer 31 b under the bump can also play a role in improving the reliability of the connection between the first bump 32 and the functional circuit integrated inside the first chip 21 .
对于上述第二连接件6的结构，例如，如图4a所示，第二连接件6包括第二金属柱61a以及设置在第二金属柱61a远离重新布线层1一侧，且与第二金属柱61a接触的第二凸块62。第二凸块62也可以称为可控坍塌第一芯片互连结构凸块(controlled collapse chip connect bump，C4bump)。又例如，如图4b所示，第二连接件6包括第二凸点下金属层(或者称作第二焊盘)61b以及设置在第二凸点下金属层61b远离重新布线层1一侧，且与第二凸点下金属层61b接触的第二凸块62。基于此，重新布线层1通过第二连接件6与基板7电连接，即第二金属柱61a或第二凸点下金属层61b与重新布线层1电连接，例如第二金属柱61a或第二凸点下金属层61b与第二导电接点113电连接，第二凸块62与基板7电连接。其中，第二金属柱61a或第二凸点下金属层61b用于起到提高第二凸块62与重新布线层1连接的可靠性的作用。For the structure of the second connecting member 6, for example, as shown in FIG. 4a, the second connecting member 6 includes a second metal pillar 61a and is disposed on the side of the second metal pillar 61a away from the redistribution layer 1 and is connected to the second metal pillar 61a. The second bump 62 to which the pillar 61a contacts. The second bump 62 may also be referred to as a controlled collapse first chip interconnect bump (controlled collapse chip connect bump, C4 bump). For another example, as shown in FIG. 4b , the second connector 6 includes a second under-bump metal layer (or referred to as a second pad) 61b and is disposed on the side of the second under-bump metal layer 61b away from the redistribution layer 1 , and the second bump 62 in contact with the second under bump metal layer 61b. Based on this, the redistribution layer 1 is electrically connected to the substrate 7 through the second connecting member 6, that is, the second metal pillar 61a or the second under-bump metal layer 61b is electrically connected to the redistribution layer 1, for example, the second metal pillar 61a or the second metal pillar 61a or the second metal layer 61b under the bump is electrically connected The two under-bump metal layers 61 b are electrically connected to the second conductive contacts 113 , and the second bumps 62 are electrically connected to the substrate 7 . The second metal pillar 61a or the second under-bump metal layer 61b is used to improve the reliability of the connection between the second bump 62 and the redistribution layer 1 .
基于上述，在一些实施例中，第一凸块32和第二凸块62为焊球。第一凸块32 和第二凸块62的材料可以为锡、铜、银、铝等金属中的一种材料或两种及两种以上的组合材料。上述的第一金属柱31a、第一凸点下金属层31b、第二金属柱61a以及第二凸点下金属层61b的材料均可以为铜、铝、镍、金、银、钛等金属中的一种材料或两种及两种以上的组合材料。Based on the above, in some embodiments, the first bump 32 and the second bump 62 are solder balls. The materials of the first bumps 32 and the second bumps 62 may be one kind of metals such as tin, copper, silver, and aluminum, or a combination of two or more kinds of materials. The above-mentioned first metal pillars 31a, first under-bump metal layer 31b, second metal pillars 61a and second under-bump metal layer 61b can be made of copper, aluminum, nickel, gold, silver, titanium and other metals. of one material or a combination of two or more materials.
对于上述第三连接件8的结构可以与第一连接件3或第二连接件6的结构类似，具体可以参考上述第一连接件3或第二连接件6的结构，此处不再赘述。在一些示例中，参考图4a和图4b，上述的第三连接件8还可以为焊球(solder ball)。The structure of the third connecting piece 8 may be similar to that of the first connecting piece 3 or the second connecting piece 6 . For details, refer to the structure of the first connecting piece 3 or the second connecting piece 6 , which will not be repeated here. In some examples, referring to FIGS. 4a and 4b , the above-mentioned third connector 8 may also be a solder ball.
此外，上述的扇出型封装结构01可以包括一个芯片即第一芯片21，也可以包括两个或两个以上芯片，即除第一芯片21外，还有其它芯片。附图1以扇出型封装结构01包括两个芯片，即第一芯片21和第二芯片22为例进行示意。附图5以扇出型封装结构01包括四个芯片，即第一芯片21、第二芯片22、第三芯片23和第四芯片24为例进行示意。In addition, the above-mentioned fan-out package structure 01 may include one chip, that is, the first chip 21 , or may include two or more chips, that is, in addition to the first chip 21 , there are other chips. FIG. 1 takes a fan-out package structure 01 including two chips, namely a first chip 21 and a second chip 22 as an example for illustration. FIG. 5 illustrates by taking the fan-out package structure 01 including four chips, namely, a first chip 21 , a second chip 22 , a third chip 23 and a fourth chip 24 as an example.
作为一种可能的实施方式，如图2、图3、图4a以及图4b所示，封装层5的材料包括模塑化合物(molding compound)。在此情况下，封装层5可以通过塑模底部填充工艺(moldable under fill，MUF)形成。塑模底部填充工艺也可以称为模制重叠注塑工艺(over molding)。模塑化合物例如可以包括环氧树脂胶粘剂(epoxy molding compound，EMC)。作为另一种可能的实现方式，如图6所示，封装层5包括第一子封装层51和第二子封装层52；第一子封装层51包围第一芯片21，第二子封装层52包围第一子封装层51；第一子封装层51的材料为底胶化合物(也可以称为底部填充胶)，第二子封装层52的材料为模塑化合物。此处，第一子封装层51可以通过毛细底部填充工艺(capillary underfill，CUF)填充于第一芯片21的周围形成。第二子封装层52可以通过塑模底部填充工艺填充于第一子封装层51的周围形成。As a possible embodiment, as shown in FIG. 2 , FIG. 3 , FIG. 4 a and FIG. 4 b , the material of the encapsulation layer 5 includes a molding compound. In this case, the encapsulation layer 5 may be formed through a moldable underfill (MUF) process. The mold underfill process may also be referred to as overmolding. The molding compound can include, for example, an epoxy molding compound (EMC). As another possible implementation, as shown in FIG. 6 , the encapsulation layer 5 includes a first sub-encapsulation layer 51 and a second sub-encapsulation layer 52 ; the first sub-encapsulation layer 51 surrounds the first chip 21 , and the second sub-encapsulation layer 52 surrounds the first sub-encapsulation layer 51 ; the material of the first sub-encapsulation layer 51 is a primer compound (also called underfill), and the material of the second sub-encapsulation layer 52 is a molding compound. Here, the first sub-package layer 51 may be formed by filling around the first chip 21 through a capillary underfill process (capillary underfill, CUF). The second sub-encapsulation layer 52 may be formed by filling around the first sub-encapsulation layer 51 through a mold underfill process.
在此基础上，在一些示例中，如图2所示，封装层5覆盖第一芯片21远离重新布线层1的表面。在另一些示例中，如图3、图4a、图4b以及图6所示，第一芯片21远离重新布线层1的表面露出于封装层5。一方面，通常第一芯片21远离重新布线层1的表面设有关于第一芯片21的型号、功能等标记，第一芯片21远离重新布线层1的表面露出于封装层5，这样便于识别第一芯片21；另一方面，将第一芯片21远离重新布线层1的表面露出于封装层5，这样有利于第一芯片21散热，或者，为了在第一芯片21远离重新布线层1的表面贴装散热器。On this basis, in some examples, as shown in FIG. 2 , the encapsulation layer 5 covers the surface of the first chip 21 away from the redistribution layer 1 . In other examples, as shown in FIGS. 3 , 4 a , 4 b and 6 , the surface of the first chip 21 away from the redistribution layer 1 is exposed to the encapsulation layer 5 . On the one hand, usually the surface of the first chip 21 away from the redistribution layer 1 is provided with marks related to the model and function of the first chip 21, and the surface of the first chip 21 away from the redistribution layer 1 is exposed to the packaging layer 5, which is convenient for identifying the first chip 21. A chip 21; on the other hand, the surface of the first chip 21 away from the rewiring layer 1 is exposed to the encapsulation layer 5, which is conducive to the heat dissipation of the first chip 21, or, in order to prevent the surface of the first chip 21 away from the rewiring layer 1 Mount the heatsink.
第一支撑层4A设置在第一芯片21与重新布线层1之间，且与重新布线层1接触，针对第一支撑层4A的设置位置，以下提供几种具体的实施例。The first support layer 4A is disposed between the first chip 21 and the redistribution layer 1, and is in contact with the redistribution layer 1. Several specific embodiments are provided below for the disposition of the first support layer 4A.
在本申请的一些实施例中，如图7所示，扇出型封装结构01还包括第二芯片22，第一支撑层4A包括第一支撑部分41，第一支撑部分41位于第一芯片21和第二芯片22之间的区域。In some embodiments of the present application, as shown in FIG. 7 , the fan-out package structure 01 further includes a second chip 22 , the first support layer 4A includes a first support portion 41 , and the first support portion 41 is located on the first chip 21 . and the area between the second chip 22 .
参考图7，第一支撑部分41还可以位于第一芯片21和第三芯片23之间的区域、第二芯片22和第四芯片24之间的区域以及第三芯片23和第四芯片24之间的区域。Referring to FIG. 7 , the first support portion 41 may also be located in an area between the first chip 21 and the third chip 23 , an area between the second chip 22 and the fourth chip 24 , and between the third chip 23 and the fourth chip 24 area between.
由于随着温度变化，扇出型封装结构01中不同部分例如第一芯片21与基板7热膨胀系数失配会导致填充在第一芯片21和第二芯片22之间的区域的封装层5产生较大的应力，因而在位于第一芯片21和第二芯片22之间的区域设置第一支撑部分41， 可以增加第一芯片21和第二芯片22之间的区域的结构强度和抗拉能力，降低第一芯片21和第二芯片22之间的区域的应力，提升封装结构的可靠性。Due to the thermal expansion coefficient mismatch between different parts of the fan-out package structure 01 , such as the first chip 21 and the substrate 7 , as the temperature changes, the encapsulation layer 5 filled in the area between the first chip 21 and the second chip 22 may be relatively weak. Therefore, arranging the first support portion 41 in the area between the first chip 21 and the second chip 22 can increase the structural strength and tensile strength of the area between the first chip 21 and the second chip 22, The stress of the region between the first chip 21 and the second chip 22 is reduced, and the reliability of the package structure is improved.
在本申请的另一些实施例中，如图8所示，第一支撑层4A包括第一支撑部分41，第一支撑部分41包围第一芯片21。In other embodiments of the present application, as shown in FIG. 8 , the first support layer 4A includes a first support portion 41 , and the first support portion 41 surrounds the first chip 21 .
参考图8，第一支撑部分41还可以包围第二芯片22、第三芯片23和第四芯片24。Referring to FIG. 8 , the first support portion 41 may also surround the second chip 22 , the third chip 23 and the fourth chip 24 .
由于第一支撑部分41包围第一芯片21，因而可以增加第一芯片21周围的区域的结构强度和抗拉能力，降低第一芯片21周围填充的封装层5因扇出型封装结构01中不同部分热膨胀系数失配产生的应力，提升封装结构的可靠性。Since the first support portion 41 surrounds the first chip 21 , the structural strength and tensile strength of the area around the first chip 21 can be increased, and the encapsulation layer 5 filled around the first chip 21 can be reduced due to the difference in the fan-out package structure 01 The stress caused by the mismatch of some thermal expansion coefficients improves the reliability of the package structure.
在本申请的又一实施例中，如图9所示，第一支撑层4A包括第二支撑部分42；第二支撑部分42包括多个平行排布的第一支撑条421和多个平行排布的第二支撑条422；多个第一支撑条421和多个第二支撑条422相交；第二支撑部分42位于第一芯片21的正下方，且第一连接件3在重新布线层1上的正投影与第二支撑部分42在重新布线层1上的正投影无重叠区域，第一连接件3位于第一支撑条421和第二支撑条422构成的网格内。In yet another embodiment of the present application, as shown in FIG. 9 , the first support layer 4A includes a second support portion 42 ; the second support portion 42 includes a plurality of first support bars 421 and a plurality of parallel rows arranged in parallel The second support bar 422 of the cloth; the plurality of first support bars 421 and the plurality of second support bars 422 intersect; the second support portion 42 is located directly under the first chip 21 , and the first connector 3 is on the redistribution layer 1 There is no overlapping area between the orthographic projection of the second support portion 42 and the orthographic projection of the second support portion 42 on the redistribution layer 1 , and the first connector 3 is located in the grid formed by the first support bar 421 and the second support bar 422 .
参考图9，第二支撑部分42还可以位于第二芯片22、第三芯片23和第四芯片24的正下方。Referring to FIG. 9 , the second support part 42 may also be located directly under the second chip 22 , the third chip 23 and the fourth chip 24 .
由于第一支撑层4A包括第二支撑部分42，第二支撑部分42位于第一芯片21的正下方，因而可以增加第一芯片21正下方的结构强度和抗拉能力，降低第一芯片21正下方填充的封装层5因扇出型封装结构01中不同部分热膨胀系数失配产生的应力，进一步提升封装结构的可靠性。Since the first support layer 4A includes the second support portion 42 , and the second support portion 42 is located directly under the first chip 21 , the structural strength and tensile strength directly under the first chip 21 can be increased, and the The encapsulation layer 5 filled below is caused by the stress caused by the mismatch of thermal expansion coefficients of different parts in the fan-out package structure 01, which further improves the reliability of the package structure.
基于上述，在上述第一支撑层4A包括第一支撑部分41和第二支撑部分42的情况下，在一些示例中，如图9所示，第二支撑部分42与第一支撑部分41相连接，即第一支撑条421和第二支撑条422均与第一支撑部分41相连接。由于第一支撑部分41与第二支撑部分42相连接，因而可以避免第一支撑部分41与第二支撑部分42相连接位置处，填充的封装层5因扇出型封装结构01中不同部分热膨胀系数失配产生的应力，导致的该位置处的封装层5断裂或该位置处的重新布线层1断裂或脱层。此外，由于位于相邻芯片例如第一芯片21和第二芯片22之间的区域的第一支撑部分41承受的封装层5的应力较大，第二支撑部分42与第一支撑部分41相连接，因而第一支撑部分41承受的部分应力可以释放到第二支撑部分42上，从而可以分散第一支撑部分41承受的应力。Based on the above, in the case where the first support layer 4A described above includes the first support portion 41 and the second support portion 42 , in some examples, as shown in FIG. 9 , the second support portion 42 is connected to the first support portion 41 . , that is, both the first support bar 421 and the second support bar 422 are connected with the first support portion 41 . Since the first support portion 41 and the second support portion 42 are connected, it can be avoided that the filled encapsulation layer 5 at the connection position of the first support portion 41 and the second support portion 42 is thermally expanded due to the thermal expansion of different parts in the fan-out package structure 01 The stress generated by the coefficient mismatch results in the breakage of the encapsulation layer 5 at this position or the breakage or delamination of the redistribution layer 1 at this position. In addition, since the first support portion 41 in the region between adjacent chips such as the first chip 21 and the second chip 22 bears a large stress on the encapsulation layer 5 , the second support portion 42 is connected to the first support portion 41 . Therefore, part of the stress borne by the first supporting part 41 can be released to the second supporting part 42 , so that the stress borne by the first supporting part 41 can be dispersed.
在一些实施例中，如图2、图3、图4a、图4b以及图6所示，在重新布线层1上直接制作上述第一支撑层4A。在另一些实施例中，如图10所示，扇出型封装结构01还包括设置在第一支撑层4A与重新布线层1之间的粘着层9，粘着层9将第一支撑层4A与重新布线层1粘贴在一起。In some embodiments, as shown in FIGS. 2 , 3 , 4 a , 4 b and 6 , the above-mentioned first support layer 4A is directly fabricated on the redistribution layer 1 . In other embodiments, as shown in FIG. 10 , the fan-out package structure 01 further includes an adhesive layer 9 disposed between the first support layer 4A and the redistribution layer 1 , and the adhesive layer 9 connects the first support layer 4A with the redistribution layer 1 . Rewiring layer 1 glued together.
在将第一支撑层4A制作于重新布线层1上的情况下，在一些示例中，第一支撑层4A单独制作。在另一些示例中，第一支撑层4A和扇出型封装结构01中的其它层同步制作。例如第一支撑层4A与第一导电接点111同层同材料，即第一支撑层4A与第一导电接点111同步制作。第一支撑层4A和扇出型封装结构01中的其它层同步制作，可以简化扇出型封装结构的制作工艺。Where the first support layer 4A is fabricated on the redistribution layer 1, in some examples, the first support layer 4A is fabricated separately. In other examples, the first support layer 4A and other layers in the fan-out package structure 01 are fabricated simultaneously. For example, the first support layer 4A and the first conductive contact 111 are made of the same layer and material, that is, the first support layer 4A and the first conductive contact 111 are fabricated simultaneously. The first support layer 4A and other layers in the fan-out package structure 01 are fabricated simultaneously, which can simplify the fabrication process of the fan-out package structure.
在此基础上，在一些实施例中，如图2、图3、图4a、图4b、图6以及图10所示，扇出型封装结构01仅包括第一支撑层4A。在另一些实施例中，如图11所示，扇出型封装结构01包括第一支撑层4A，第一支撑层4A包括第一支撑部分41。扇出型封装结构01还包括设置在第一支撑层4A远离重新布线层1一侧，且与第一支撑层4A接触的第二支撑层4B；第二支撑层4B包括第三支撑部分43。在一些示例中，第三支撑部分43位于第一芯片21和第二芯片22之间的区域，在此情况下，第一支撑部分41可以位于第一芯片21和第二芯片22之间的区域，第一支撑部分41也可以包围第一芯片21。在另一些示例中，第三支撑部分43包围第一芯片21，在此情况下，第一支撑部分41包围第一芯片211。On this basis, in some embodiments, as shown in FIGS. 2 , 3 , 4 a , 4 b , 6 and 10 , the fan-out package structure 01 only includes the first support layer 4A. In other embodiments, as shown in FIG. 11 , the fan-out package structure 01 includes a first support layer 4A, and the first support layer 4A includes a first support portion 41 . The fan-out package structure 01 further includes a second support layer 4B disposed on the side of the first support layer 4A away from the redistribution layer 1 and in contact with the first support layer 4A; the second support layer 4B includes a third support portion 43 . In some examples, the third support portion 43 is located in the region between the first chip 21 and the second chip 22 , in which case the first support portion 41 may be located in the region between the first chip 21 and the second chip 22 , the first support portion 41 may also surround the first chip 21 . In other examples, the third support portion 43 surrounds the first chip 21 , in which case the first support portion 41 surrounds the first chip 211 .
考虑到封装层5位于第一芯片21和第二芯片22之间的区域产生的应力较大，位于第一芯片21和第二芯片22之间的区域的封装层5以及重新布线层1容易断裂，因此在本申请的一些实施例中，扇出型封装结构01还包括第二支撑层4B，第二支撑层4B包括位于第一芯片21和第二芯片22之间的区域的第三支撑部分，由于位于第一芯片21和第二芯片22之间的区域设置有第一支撑部分41和第三支撑部分43第一支撑层4A，因而可以进一步增加位于第一芯片21和第二芯片22之间的区域的结构强度，更有利于降低第一芯片21和第二芯片22之间的区域填充的封装层5因扇出型封装结构01中不同部分热膨胀系数失配产生的应力，进而可以更进一步地提升封装结构的可靠性。Considering that the stress generated in the area between the first chip 21 and the second chip 22 of the encapsulation layer 5 is relatively large, the encapsulation layer 5 and the rewiring layer 1 in the area between the first chip 21 and the second chip 22 are easily broken , so in some embodiments of the present application, the fan-out package structure 01 further includes a second support layer 4B, and the second support layer 4B includes a third support portion located in a region between the first chip 21 and the second chip 22 , since the region between the first chip 21 and the second chip 22 is provided with the first support portion 41 and the third support portion 43, the first support layer 4A can be further increased between the first chip 21 and the second chip 22 The structural strength of the area between the first chip 21 and the second chip 22 is more conducive to reducing the stress caused by the mismatch of thermal expansion coefficients of different parts in the fan-out package structure 01 in the encapsulation layer 5 filled in the area between the first chip 21 and the second chip 22, which can further improve the The reliability of the package structure is further improved.
在第一支撑部分41和第三支撑部分43包围第一芯片21时，可以进一步增加第一芯片21周围的区域的结构强度，更有利于降低第一芯片21周围填充的封装层5因扇出型封装结构01中不同部分热膨胀系数失配产生的应力，提升封装结构的可靠性。When the first support portion 41 and the third support portion 43 surround the first chip 21 , the structural strength of the area around the first chip 21 can be further increased, which is more conducive to reducing the fan-out caused by the encapsulation layer 5 filled around the first chip 21 . The stress caused by the mismatch of thermal expansion coefficients of different parts in the type package structure 01 improves the reliability of the package structure.
在又一些实施例中，扇出型封装结构01还包括设置在第一支撑层4A远离重新布线层1一侧，且与第一支撑层4A接触的第二支撑层4B；第二支撑层4B包括第四支撑部分，第四支撑部分包括多个平行排布的第三支撑条和多个平行排布的第四支撑条；多个第三支撑条和多个第四支撑条相交；第四支撑部分位于第一芯片21的正下方，且第一连接件3在重新布线层1上的正投影与第四支撑部分在重新布线层1上的正投影无重叠区域。In still other embodiments, the fan-out package structure 01 further includes a second support layer 4B disposed on the side of the first support layer 4A away from the redistribution layer 1 and in contact with the first support layer 4A; the second support layer 4B including a fourth support part, the fourth support part includes a plurality of third support bars arranged in parallel and a plurality of fourth support bars arranged in parallel; the plurality of third support bars and the plurality of fourth support bars intersect; the fourth The supporting portion is located directly under the first chip 21 , and the orthographic projection of the first connecting member 3 on the redistribution layer 1 does not overlap with the orthographic projection of the fourth supporting portion on the redistribution layer 1 .
应当理解到，第四支撑部分在重新布线层1上的正投影位于第二支撑部分42在重新布线层1上的正投影内。在一些示例中，第四支撑部分在重新布线层1上的正投影与第二支撑部分42在重新布线层1上的正投影重叠。It should be understood that the orthographic projection of the fourth support portion on the redistribution layer 1 is located within the orthographic projection of the second support portion 42 on the redistribution layer 1 . In some examples, the orthographic projection of the fourth support portion on the redistribution layer 1 overlaps the orthographic projection of the second support portion 42 on the redistribution layer 1 .
由于扇出型封装结构01包括第二支撑部分42和第四支撑部分，因而可以进一步增加第一芯片21正下方的结构强度和抗拉能力，降低第一芯片21正下方填充的封装层5因扇出型封装结构01中不同部分热膨胀系数失配产生的应力，进一步提升封装结构的可靠性。Since the fan-out package structure 01 includes the second support portion 42 and the fourth support portion, the structural strength and tensile strength directly under the first chip 21 can be further increased, and the encapsulation layer 5 filled directly under the first chip 21 can be reduced. The stress caused by the mismatch of thermal expansion coefficients of different parts in the fan-out package structure 01 further improves the reliability of the package structure.
在此基础上，可以是第一支撑层4A和第二支撑层4B的材料都为金属材料；也可以是第一支撑层4A和第二支撑层4B的材料都为非金属材料；当然还可以是，第一支撑层4A和第二支撑层4B中其中一层的材料为金属材料，另一层的材料为非金属材料。On this basis, the materials of the first support layer 4A and the second support layer 4B may be both metallic materials; it may also be that the materials of the first support layer 4A and the second support layer 4B are both non-metallic materials; of course, you can also Yes, the material of one of the first supporting layer 4A and the second supporting layer 4B is a metal material, and the material of the other layer is a non-metallic material.
需要说明的是，由于第一支撑层4A和第二支撑层4B用于降低填充在第一芯片21周围的封装层5因扇出型封装结构01中不同部分热膨胀系数失配产生的应力，因而选 取的第一支撑层4A和第二支撑层4B的材料强度应大于封装层5的材料强度。例如，第一支撑层4A和第二支撑层4B的材料为铜、银、铝、钛中的一种材料或两种及两种以上的组合材料。又例如，第一支撑层4A和第二支撑层4B的材料为氮化硅、氧化硅或氮氧化硅等。It should be noted that, since the first support layer 4A and the second support layer 4B are used to reduce the stress of the packaging layer 5 filled around the first chip 21 due to the mismatch of thermal expansion coefficients of different parts in the fan-out package structure 01, therefore The selected material strength of the first support layer 4A and the second support layer 4B should be greater than the material strength of the encapsulation layer 5 . For example, the materials of the first support layer 4A and the second support layer 4B are one of copper, silver, aluminum, and titanium, or a combination of two or more materials. For another example, the materials of the first support layer 4A and the second support layer 4B are silicon nitride, silicon oxide, silicon oxynitride, or the like.
此外，应当理解到，如图11所示，重新布线层1包括接地端子114，接地端子114与地线电连接。在第一支撑层4A导电的情况下，在一些实施例中，第一支撑层4A与重新布线层1中的接地端子114电连接，即第一支撑层4A通过重新布线层1互连接地。Furthermore, it should be understood that, as shown in FIG. 11 , the rewiring layer 1 includes a ground terminal 114 that is electrically connected to the ground wire. In the case where the first support layer 4A is conductive, in some embodiments, the first support layer 4A is electrically connected to the ground terminal 114 in the redistribution layer 1 , that is, the first support layer 4A is interconnected to ground through the redistribution layer 1 .
由于第一支撑层4A通过重新布线层1互连接地，因而第一支撑层4A相当于一个地平面，从而可以将第一芯片21的信号与重新布线层1的信号有效隔离，这样一来，可以提高信号质量，提升扇出型封装结构01的电性能。Since the first support layer 4A is connected to the ground through the redistribution layer 1, the first support layer 4A is equivalent to a ground plane, so that the signal of the first chip 21 can be effectively isolated from the signal of the redistribution layer 1. In this way, The signal quality can be improved, and the electrical performance of the fan-out package structure 01 can be improved.
本申请实施例提供一种扇出型封装结构01，该扇出型封装结构01包括重新布线层1、第一芯片21、第一连接件3、第一支撑层4A以及封装层5。第一芯片21通过第一连接件3与重新布线层1电连接，第一支撑层4A设置在第一芯片21和重新布线层1之间，且与重新布线层1接触，封装层5填充于第一芯片21周围，且封装层5包裹第一芯片21、第一连接件3以及第一支撑层4A。由于第一芯片21和重新布线层1之间设置有第一支撑层4A，而第一支撑层4A可以增加局部区域的结构强度，降低填充在第一芯片21周围的封装层5因扇出型封装结构01中不同部分的热膨胀系数不匹配产生的应力，从而避免了填充在第一芯片21周围的封装层5断裂，且避免了重新布线层1断裂以及重新布线层1出现脱层现象，提升了扇出型封装结构01的整体可靠性。An embodiment of the present application provides a fan-out package structure 01 , and the fan-out package structure 01 includes a rewiring layer 1 , a first chip 21 , a first connector 3 , a first support layer 4A, and a packaging layer 5 . The first chip 21 is electrically connected to the redistribution layer 1 through the first connector 3, the first support layer 4A is disposed between the first chip 21 and the redistribution layer 1, and is in contact with the redistribution layer 1, and the encapsulation layer 5 is filled with the redistribution layer 1. Around the first chip 21 , the packaging layer 5 wraps the first chip 21 , the first connector 3 and the first support layer 4A. Since the first support layer 4A is disposed between the first chip 21 and the redistribution layer 1, the first support layer 4A can increase the structural strength of the local area and reduce the fan-out type of the packaging layer 5 filled around the first chip 21. The stress caused by the mismatch of thermal expansion coefficients of different parts in the package structure 01 avoids the breakage of the package layer 5 filled around the first chip 21, and avoids the breakage of the rewiring layer 1 and the delamination phenomenon of the rewiring layer 1. The overall reliability of the fan-out package structure 01 is improved.
此外，为了确保第一支撑层4A能够起到支撑作用，在一些实施例中，扇出型封装结构01中设置的第一支撑层4A的材料强度大于封装层5的材料强度。这样一来，相对于扇出型封装结构01不包括第一支撑层4A时，第一芯片21和重新布线层1之间通过封装层5起支撑作用，由于本申请实施例中设置有第一支撑层4A，因而可以降低填充在第一芯片21和重新布线层1之间的封装层5的厚度，即降低整个封装层5的厚度，且可以通过调整第一支撑层4A的厚度来控制扇出型封装结构01的厚度。相对于通过其它方法调整扇出型封装结构01的厚度例如通过调整第一芯片21的厚度来调整扇出型封装结构01的厚度，本申请实施例通过调整第一支撑层4A的厚度来控制扇出型封装结构01的厚度，工艺流程简单，成本较低。In addition, in order to ensure that the first support layer 4A can play a supporting role, in some embodiments, the material strength of the first support layer 4A provided in the fan-out package structure 01 is greater than the material strength of the package layer 5 . In this way, when the fan-out package structure 01 does not include the first support layer 4A, the package layer 5 plays a supporting role between the first chip 21 and the rewiring layer 1 . The supporting layer 4A can thus reduce the thickness of the encapsulation layer 5 filled between the first chip 21 and the rewiring layer 1, that is, the thickness of the entire encapsulation layer 5 can be reduced, and the fan can be controlled by adjusting the thickness of the first supporting layer 4A. The thickness of the out-molded package structure 01 . Compared to adjusting the thickness of the fan-out package structure 01 by other methods, such as adjusting the thickness of the fan-out package structure 01 by adjusting the thickness of the first chip 21 , the embodiment of the present application controls the fan-out package structure 01 by adjusting the thickness of the first support layer 4A. The thickness of the extruded package structure 01 is simple, the process flow is simple, and the cost is low.
本申请实施例还提供一种扇出型封装结构01的制备方法，可以用于制备上述的扇出型封装结构01。如图12所示，该扇出型封装结构01的制备方法包括：Embodiments of the present application further provide a method for manufacturing the fan-out package structure 01 , which can be used to prepare the fan-out package structure 01 described above. As shown in FIG. 12 , the preparation method of the fan-out package structure 01 includes:
S10、如图13所示，在重新布线层1上形成第一支撑层4A。S10 , as shown in FIG. 13 , a first support layer 4A is formed on the redistribution layer 1 .
其中，在一种实施例中，如图13所示，重新布线层1制作在底板10上。Wherein, in an embodiment, as shown in FIG. 13 , the redistribution layer 1 is fabricated on the base plate 10 .
此处，底板10的材质例如可以为玻璃、氧化硅、氮化硅、金属、塑料或陶瓷等。Here, the material of the base plate 10 may be, for example, glass, silicon oxide, silicon nitride, metal, plastic, ceramic, or the like.
需要说明的是，重新布线层1包括一层或多层金属线层11和一层或多层绝缘层12，具体可以参考上述的实施例，此处不再赘述。It should be noted that the redistribution layer 1 includes one or more layers of metal wire layers 11 and one or more layers of insulating layers 12 . For details, reference may be made to the above-mentioned embodiments, which will not be repeated here.
在一些实施例中，如图14a所示，重新布线层1包括露出于绝缘层12的第一导电接点111。在另一些实施例中，如图14b所示，重新布线层1包括露出于绝缘层12的 第一导电接点111和键合层112，键合层112相对于第一导电接点111远离底板10，且键合层112与第一导电接点111接触。在又一些实施例中，如图14c所示，重新布线层1不包括第一导电接点111。In some embodiments, as shown in FIG. 14 a , the redistribution layer 1 includes a first conductive contact 111 exposed on the insulating layer 12 . In other embodiments, as shown in FIG. 14b, the redistribution layer 1 includes a first conductive contact 111 exposed on the insulating layer 12 and a bonding layer 112, and the bonding layer 112 is away from the base plate 10 relative to the first conductive contact 111, And the bonding layer 112 is in contact with the first conductive contact 111 . In still other embodiments, as shown in FIG. 14c , the redistribution layer 1 does not include the first conductive contact 111 .
基于上述，在重新布线层1如图14c所示，不包括第一导电接点111时，在一些实施例中，在S10之前，该扇出型封装结构01的制备方法包括：Based on the above, when the redistribution layer 1 does not include the first conductive contact 111 as shown in FIG. 14c, in some embodiments, before S10, the preparation method of the fan-out package structure 01 includes:
S100、如图14a所示，形成重新布线层1中的第一导电接点111。S100 , as shown in FIG. 14 a , the first conductive contact 111 in the redistribution layer 1 is formed.
此处，示例的，可以采用化学气相沉积法或溅射法结合光刻工艺形成第一导电接点111，也可以采用电镀法形成第一导电接点111。Here, for example, chemical vapor deposition method or sputtering method combined with photolithography process may be used to form the first conductive contact 111 , or electroplating method may be used to form the first conductive contact 111 .
S101、如图14b所示，在第一导电接点111远离底板10的一侧形成键合层112，键合层112与第一导电接点111接触。S101 , as shown in FIG. 14 b , a bonding layer 112 is formed on the side of the first conductive contact 111 away from the base plate 10 , and the bonding layer 112 is in contact with the first conductive contact 111 .
在另一些实施例中，步骤S10也可以参考如下步骤S102和S103制作。In other embodiments, step S10 can also be produced by referring to the following steps S102 and S103.
S102、在重新布线层1上形成第一支撑层4A，并同步形成重新布线层1的第一导电接点111。S102 , forming the first support layer 4A on the redistribution layer 1 , and simultaneously forming the first conductive contact 111 of the redistribution layer 1 .
此处，示例的，可以采用化学气相沉积法或溅射法结合光刻工艺形成第一导电接点111和第一支撑层4A，也可以采用电镀法形成第一导电接点111和第一支撑层4A。Here, by way of example, the first conductive contact 111 and the first supporting layer 4A may be formed by chemical vapor deposition or sputtering combined with a photolithography process, or the first conductive contact 111 and the first supporting layer 4A may be formed by electroplating .
S103、如图14b所示，在第一导电接点111远离底板10的一侧形成键合层112，键合层112与第一导电接点111接触。S103 , as shown in FIG. 14 b , a bonding layer 112 is formed on the side of the first conductive contact 111 away from the base plate 10 , and the bonding layer 112 is in contact with the first conductive contact 111 .
需要说明的是，上述步骤S101和步骤S103为可选的步骤，例如在一些实施例中也可以省略。It should be noted that, the above-mentioned steps S101 and S103 are optional steps, and may also be omitted, for example, in some embodiments.
S12、如图15所示，通过第一连接件3将第一芯片21绑定到重新布线层1上，以使第一芯片21与重新布线层1电连接。S12 , as shown in FIG. 15 , the first chip 21 is bound to the rewiring layer 1 through the first connector 3 , so that the first chip 21 is electrically connected to the rewiring layer 1 .
此处，第一连接件3的结构和材料可以参考上述实施例，此处不再赘述。Here, the structure and material of the first connecting member 3 may refer to the above-mentioned embodiments, which will not be repeated here.
对于第一连接件3的制备方法，以第一连接件3包括第一金属柱31a和第一凸块32，或者第一连接件3包括第一凸点下金属层31b和第一凸块32为例，第一金属柱31和第一凸点下金属层31b可以通过化学气相沉积法或溅射法结合光刻工艺形成，或者通过电镀工艺形成，第一凸块32可以通过植球回流工艺形成。For the manufacturing method of the first connector 3 , the first connector 3 includes the first metal pillar 31 a and the first bump 32 , or the first connector 3 includes the first under-bump metal layer 31 b and the first bump 32 For example, the first metal pillars 31 and the first under bump metal layer 31b can be formed by chemical vapor deposition or sputtering combined with a photolithography process, or formed by an electroplating process, and the first bumps 32 can be formed by a ball reflow process form.
S13、填充封装层5；封装层5包裹第一芯片21、第一连接件3以及第一支撑层4A。S13 , filling the encapsulation layer 5 ; the encapsulation layer 5 wraps the first chip 21 , the first connector 3 and the first support layer 4A.
需要说明的是，在一些实施例中，步骤S13可以采用方式一制作：如图16a所示，通过塑模底部填充工艺填充封装层5。It should be noted that, in some embodiments, step S13 may be fabricated in a first manner: as shown in FIG. 16a , the encapsulation layer 5 is filled through a mold underfill process.
或者，步骤S13也可以采用方式二制作：如图16b所示，先通过毛细底部填充第一子封装层51，第一子封装层51包围第一芯片21；如图16c所示，再通过塑模底部填充工艺填充第二子封装层52；第二子封装层52包围第一子封装层51；其中，封装层5包括第一子封装层51和第二子封装层52。Alternatively, step S13 can also be produced in the second method: as shown in FIG. 16b, the first sub-encapsulation layer 51 is first filled with the capillary bottom, and the first sub-encapsulation layer 51 surrounds the first chip 21; as shown in FIG. 16c, the first sub-encapsulation layer 51 is The mold underfill process fills the second sub-encapsulation layer 52 ; the second sub-encapsulation layer 52 surrounds the first sub-encapsulation layer 51 ; wherein the encapsulation layer 5 includes the first sub-encapsulation layer 51 and the second sub-encapsulation layer 52 .
在步骤S13之后，为了实现扇出型结构，还需要进一步制作第二连接件6和基板7，基于此，上述该扇出型封装结构01的制备方法还包括如下步骤：After step S13, in order to realize the fan-out type structure, it is necessary to further fabricate the second connector 6 and the substrate 7. Based on this, the above-mentioned preparation method of the fan-out type package structure 01 further includes the following steps:
S14、如图17所示，在重新布线层1远离第一芯片21的一侧形成与重新布线层1电连接的第二连接件6。S14 . As shown in FIG. 17 , a second connecting member 6 electrically connected to the redistribution layer 1 is formed on the side of the redistribution layer 1 away from the first chip 21 .
此处，第二连接件6的结构和材料可以参考上述实施例，此处不再赘述。Here, the structure and material of the second connecting member 6 may refer to the above-mentioned embodiments, which will not be repeated here.
对于第二连接件6的制备方法，以第二连接件6包括第二金属柱61a和第二凸块62，或者第二连接件6包括第二凸点下金属层61b和第二凸块62为例，第二金属柱61a和第二凸点下金属层61b可以通过化学气相沉积法或溅射法结合光刻工艺形成，或者通过电镀工艺形成，第二凸块62可以通过植球回流工艺形成。For the preparation method of the second connecting member 6, the second connecting member 6 includes the second metal pillar 61a and the second bump 62, or the second connecting member 6 includes the second under-bump metal layer 61b and the second bump 62 For example, the second metal pillars 61a and the second under bump metal layer 61b can be formed by chemical vapor deposition or sputtering combined with photolithography, or formed by electroplating, and the second bumps 62 can be formed by a ball reflow process form.
应当理解到，若重新布线层1制作于底板10上，则在步骤S14之前还需要将底板10去除。It should be understood that if the rewiring layer 1 is fabricated on the base plate 10, the base plate 10 needs to be removed before step S14.
S15、如图18所示，对封装层5进行减薄，以露出第一芯片21远离重新布线层1的表面。S15 , as shown in FIG. 18 , the encapsulation layer 5 is thinned to expose the surface of the first chip 21 away from the redistribution layer 1 .
需要说明的是，该步骤为可选的步骤，例如在一些实施例中也可以省略。It should be noted that this step is an optional step, and may be omitted, for example, in some embodiments.
此处，通常第一芯片21远离重新布线层1的表面设有关于第一芯片21的型号、功能等标记，因而对封装层5进行减薄，将第一芯片21远离重新布线层1的表面露出于封装层5，这样便于识别第一芯片21。此外，将第一芯片21远离重新布线层1的表面露出于封装层5，有利于第一芯片散热，或者，便于后续在第一芯片21远离重新布线层1的表面贴装散热器。Here, usually, the surface of the first chip 21 away from the redistribution layer 1 is provided with marks related to the model, function, etc. of the first chip 21 , so the packaging layer 5 is thinned, and the first chip 21 is far away from the surface of the redistribution layer 1 . It is exposed to the encapsulation layer 5 so as to facilitate the identification of the first chip 21 . In addition, exposing the surface of the first chip 21 away from the redistribution layer 1 to the packaging layer 5 facilitates heat dissipation of the first chip, or facilitates subsequent mounting of a heat sink on the surface of the first chip 21 away from the redistribution layer 1 .
在此基础上，可以通过研磨法、化学机械抛光法、切割法、其它适用方法或上述的组合对封装层5进行减薄。On this basis, the encapsulation layer 5 can be thinned by grinding, chemical mechanical polishing, dicing, other suitable methods, or a combination of the above.
S16、如图19所示，将第二连接件6与基板7电连接。S16 , as shown in FIG. 19 , electrically connect the second connector 6 to the substrate 7 .
需要说明的是，当上述绑定到重新布线层1上的多个芯片包括可以实现相同功能的多个芯片组，每个芯片组包括至少一个芯片时，在一些实施例中，在步骤S14之后，在步骤S16之前，上述该扇出型封装结构01的制备方法还包括：对步骤S14之后，步骤S16之前形成的结构进行切割，切割后的每个结构包括一个芯片组。It should be noted that when the above-mentioned multiple chips bound to the rewiring layer 1 include multiple chipsets that can implement the same function, and each chipset includes at least one chip, in some embodiments, after step S14 Before step S16, the above-mentioned preparation method of the fan-out package structure 01 further includes: cutting the structures formed after step S14 and before step S16, and each structure after cutting includes a chip set.
此处，在封装层5包括第一子封装层51和第二子封装层52的情况下，切割后的每个结构中的封装层5均包括第一子封装层51和第二子封装层52，且第二子封装层52包围第一子封装层51。Here, in the case where the encapsulation layer 5 includes the first sub-encapsulation layer 51 and the second sub-encapsulation layer 52, the encapsulation layer 5 in each structure after cutting includes the first sub-encapsulation layer 51 and the second sub-encapsulation layer 52 , and the second sub-encapsulation layer 52 surrounds the first sub-encapsulation layer 51 .
在S16之后，为了使基板7与印刷电路板电连接，上述该扇出型封装结构01的制备方法还包括如下步骤：After S16, in order to electrically connect the substrate 7 with the printed circuit board, the above-mentioned preparation method of the fan-out package structure 01 further includes the following steps:
S17、如图6所示，在基板7远离重新布线层1的一侧形成第三连接件8。第三连接件8用于将基板7和印刷电路板电连接在一起。S17 , as shown in FIG. 6 , the third connecting member 8 is formed on the side of the substrate 7 away from the redistribution layer 1 . The third connector 8 is used to electrically connect the substrate 7 and the printed circuit board together.
此处，第三连接件8的结构和材料可以参考上述实施例，此处不再赘述。Here, the structure and material of the third connecting member 8 may refer to the above-mentioned embodiments, which will not be repeated here.
对于第三连接件8的制备方法，以第三连接件8为焊球为例，第三连接件8可以通过植球回流工艺形成。For the preparation method of the third connecting member 8, taking the third connecting member 8 as a solder ball as an example, the third connecting member 8 may be formed by a ball reflow process.
本申请实施例提供一种扇出型封装结构01的制备方法，该制备方法包括在重新布线层1上形成第一支撑层4A，通过第一连接件3将第一芯片21绑定到重新布线层1上，以使第一芯片21与重新布线层1电连接，填充封装层5；封装层5包裹第一芯片21、第一连接件3以及第一支撑层4A。由于第一芯片21和重新布线层1之间形成有第一支撑层4A，而第一支撑层4A可以增加局部区域的结构强度，降低填充在第一芯片21周围的封装层5因扇出型封装结构01中不同部分的热膨胀系数不匹配产生的应力，从而避免了填充在第一芯片21周围的封装层5断裂，且避免了重新布线层1断裂以及重新布线层1出现脱层现象，提升了扇出型封装结构01的整体可靠性。The embodiment of the present application provides a method for fabricating a fan-out package structure 01 . The fabrication method includes forming a first support layer 4A on the rewiring layer 1 , and binding the first chip 21 to the rewiring through the first connector 3 . layer 1, so that the first chip 21 is electrically connected to the redistribution layer 1, and the encapsulation layer 5 is filled; the encapsulation layer 5 wraps the first chip 21, the first connector 3 and the first support layer 4A. Since the first support layer 4A is formed between the first chip 21 and the redistribution layer 1, the first support layer 4A can increase the structural strength of the local area, and reduce the fan-out type of the packaging layer 5 filled around the first chip 21. The stress caused by the mismatch of thermal expansion coefficients of different parts in the package structure 01 avoids the breakage of the package layer 5 filled around the first chip 21, and avoids the breakage of the rewiring layer 1 and the delamination phenomenon of the rewiring layer 1. The overall reliability of the fan-out package structure 01 is improved.
此外，为了确保第一支撑层4A能够起到支撑作用，在一些实施例中，扇出型封装结构01中形成的第一支撑层4A的材料强度大于封装层5的材料强度。这样一来，相对于扇出型封装结构01不包括第一支撑层4A时，第一芯片21和重新布线层1之间通过封装层5起支撑作用，由于本申请实施例中形成有第一支撑层4A，因而可以降低填充在第一芯片21和重新布线层1之间的封装层5的厚度，即降低整个封装层5的厚度，且可以通过调整第一支撑层4A的厚度来控制扇出型封装结构01的厚度。相对于通过其它方法调整扇出型封装结构01的厚度例如通过调整第一芯片21的厚度来调整扇出型封装结构01的厚度，本申请实施例通过调整第一支撑层4A的厚度来控制扇出型封装结构01的厚度，工艺流程简单，成本较低。In addition, in order to ensure that the first support layer 4A can play a supporting role, in some embodiments, the material strength of the first support layer 4A formed in the fan-out package structure 01 is greater than that of the package layer 5 . In this way, when the fan-out package structure 01 does not include the first support layer 4A, the package layer 5 plays a supporting role between the first chip 21 and the redistribution layer 1 . The supporting layer 4A can thus reduce the thickness of the encapsulation layer 5 filled between the first chip 21 and the rewiring layer 1, that is, the thickness of the entire encapsulation layer 5 can be reduced, and the fan can be controlled by adjusting the thickness of the first supporting layer 4A. The thickness of the out-molded package structure 01 . Compared with adjusting the thickness of the fan-out package structure 01 through other methods, such as adjusting the thickness of the fan-out package structure 01 by adjusting the thickness of the first chip 21 , the embodiment of the present application controls the fan-out package structure 01 by adjusting the thickness of the first support layer 4A. The thickness of the extruded package structure 01 is simple, the process flow is simple, and the cost is low.
以下通过三个实施例对上述步骤S10的具体实现方式进行说明。The specific implementation manner of the foregoing step S10 will be described below through three embodiments.
实施例一：Example 1:
S20、如图20所示，在重新布线层1上形成电镀种子层13。S20 , as shown in FIG. 20 , a plating seed layer 13 is formed on the redistribution layer 1 .
示例的，可以采用溅射法形成电镀种子层13。For example, the electroplating seed layer 13 may be formed by a sputtering method.
此处，电镀种子层13的材料例如可以为钛铜种子层。Here, the material of the plating seed layer 13 may be, for example, a titanium copper seed layer.
S21、如图21所示，在电镀种子层13上形成光刻胶层14；光刻胶层14在待形成第一支撑层4A的区域镂空。S21 , as shown in FIG. 21 , a photoresist layer 14 is formed on the electroplating seed layer 13 ; the photoresist layer 14 is hollowed out in the area where the first support layer 4A is to be formed.
此处，可以在电镀种子层13上先形成光刻胶薄膜，再对光刻胶薄膜进行掩膜曝光、显影等工艺，形成光刻胶层14。Here, a photoresist film may be formed on the electroplating seed layer 13 first, and then processes such as mask exposure and development are performed on the photoresist film to form the photoresist layer 14 .
示例的，可以采用涂覆法形成光刻胶层薄膜。Illustratively, the photoresist layer thin film may be formed by a coating method.
S22、如图22所示，在光刻胶层14的待形成第一支撑层4A的区域内电镀形成第一支撑层4A。S22 , as shown in FIG. 22 , electroplating to form the first support layer 4A in the region of the photoresist layer 14 where the first support layer 4A is to be formed.
S23、如图23所示，去除光刻胶层14及其下方的电镀种子层13。S23 , as shown in FIG. 23 , remove the photoresist layer 14 and the electroplating seed layer 13 below it.
此处，光刻胶层14下方的电镀种子层13指的是电镀种子层13中与光刻胶层14在其上的正投影重叠的部分。Here, the electroplating seed layer 13 under the photoresist layer 14 refers to a portion of the electroplating seed layer 13 that overlaps with the orthographic projection of the photoresist layer 14 thereon.
需要说明的是，在第一导电接点111与第一支撑层4A同步制作的情况下，步骤S21中光刻胶层14还在待形成第一导电接点111的区域镂空。步骤S22可以按照如下步骤制作：在光刻胶层14的待形成第一支撑层4A的区域内电镀形成第一支撑层4A，并同步在光刻胶层14的待形成第一导电接点111的区域内电镀形成第一导电接点111。It should be noted that, in the case where the first conductive contacts 111 and the first support layer 4A are simultaneously fabricated, the photoresist layer 14 in step S21 is still hollowed out in the regions where the first conductive contacts 111 are to be formed. Step S22 can be made according to the following steps: electroplating to form the first support layer 4A in the area of the photoresist layer 14 where the first support layer 4A is to be formed, and simultaneously on the photoresist layer 14 where the first conductive contact 111 is to be formed. The first conductive contact 111 is formed by electroplating in the area.
实施例二 Embodiment 2
S30、如图24所示，在载板15上形成支撑薄膜16。S30 , as shown in FIG. 24 , the support film 16 is formed on the carrier plate 15 .
此处，可以采用键合方法在载板15上键合形成支撑薄膜16；也可以在载板15上通过涂覆或溅射等方式形成支撑薄膜16。Here, the support film 16 may be formed by bonding on the carrier board 15 by using a bonding method; the support film 16 may also be formed on the carrier board 15 by coating or sputtering.
此外，载板15的材质例如可以为玻璃、氧化硅、氮化硅、金属、塑料或陶瓷等。In addition, the material of the carrier plate 15 can be, for example, glass, silicon oxide, silicon nitride, metal, plastic or ceramics.
S31、如图25所示，在支撑薄膜16上贴附胶膜(die attached film)17。S31 , as shown in FIG. 25 , attach a die attached film 17 on the support film 16 .
S32、如图26所示，对支撑薄膜16和胶膜17进行构图，形成第一支撑层4A和粘着层9；第一支撑层4A和粘着层9在载板15上的正投影重叠。S32 , as shown in FIG. 26 , pattern the support film 16 and the adhesive film 17 to form the first support layer 4A and the adhesive layer 9 ;
此处，对支撑薄膜16和胶膜17进行构图，例如可以是对支撑薄膜16和胶膜17进行切割形成第一支撑层4A和粘着层9，又例如，也可以是对支撑薄膜16和胶膜17进行刻蚀形成第一支撑层4A和粘着层9。Here, patterning the support film 16 and the adhesive film 17, for example, may be to cut the support film 16 and the adhesive film 17 to form the first support layer 4A and the adhesive layer 9, or, for example, may also be to the support film 16 and the adhesive film. The film 17 is etched to form the first support layer 4A and the adhesive layer 9 .
S33、如图27所示，将第一支撑层4A和粘着层9移动到重新布线层1上，并剥离载板15。其中，第一支撑层4A通过粘着层9粘贴在重新布线层1上。S33 , as shown in FIG. 27 , move the first support layer 4A and the adhesive layer 9 onto the redistribution layer 1 , and peel off the carrier board 15 . Among them, the first support layer 4A is pasted on the redistribution layer 1 through the adhesive layer 9 .
需要说明的是，可以先将第一支撑层4A和粘着层9移动到重新布线层1上，再剥离载板15；也可以先剥离载板15，即将第一支撑层4A与载板15分离，再将第一支撑层4A和粘着层9移动到重新布线层1上。It should be noted that the first support layer 4A and the adhesive layer 9 can be moved to the redistribution layer 1 first, and then the carrier board 15 can be peeled off; the carrier board 15 can also be peeled off first, that is, the first support layer 4A and the carrier board 15 can be separated. , and then move the first support layer 4A and the adhesive layer 9 to the redistribution layer 1 .
此处，可以根据支撑薄膜16的材料以及形成在载板15上的方式，采用适当的方法剥离载板15。示例的，支撑薄膜16以键合的方式形成在载板15上，可以采用解键合的方式剥离载板15。解键合的方式例如可以为热滑动剥离(thermal slide-off debonding)、机械剥离(mechanical debonding)或紫外激光剥离(UV laser debonding)。其中，热滑动剥离利用了热塑材料的可逆热特性，在较高的温度下，该材料的粘度会下降，从而能通过简单地滑动两边的晶圆来完成剥离。机械剥离要在临时键合材料与晶圆间产生低粘附力才能成功剥离。紫外激光剥离是利用紫外光照射载板15，使载板15与第一支撑层4A分离。剥离原理是将光吸收并转化为热能，从而在键合界面内产生高温。紫外激光剥离通常依靠化学过程使用光吸收的能量来破坏化学键，并导致原始聚合物进行分解，分解物中含气体，可以增加键合界面的压力帮助剥离。Here, the carrier plate 15 may be peeled off by an appropriate method according to the material of the support film 16 and the manner in which it is formed on the carrier plate 15 . Exemplarily, the support film 16 is formed on the carrier board 15 in a bonding manner, and the carrier board 15 can be peeled off in a debonding manner. The way of debonding can be, for example, thermal slide-off debonding, mechanical debonding or UV laser debonding. Among them, thermal slip peeling takes advantage of the reversible thermal properties of thermoplastic materials, which decrease in viscosity at higher temperatures, allowing peeling to be accomplished by simply sliding the wafers on both sides. Mechanical debonding requires low adhesion between the temporary bonding material and the wafer for successful debonding. In the UV laser lift-off, the carrier 15 is irradiated with ultraviolet light to separate the carrier 15 from the first support layer 4A. The principle of exfoliation is the absorption and conversion of light into thermal energy, resulting in a high temperature within the bonding interface. UV laser lift-off usually relies on a chemical process that uses the energy absorbed by light to break chemical bonds and cause the original polymer to decompose. The decomposed gas contains gas that can increase the pressure at the bonding interface to help the peeling.
需要说明的是，在第一导电接点111与第一支撑层4A同步制作的情况下，支撑薄膜16和胶膜17的材料均为导电材料，步骤S32可以按照如下步骤制作：对支撑薄膜16和胶膜17进行构图，形成层叠的第一支撑层4A和粘着层9以及层叠的第一导电接点111和粘着层9；层叠的第一支撑层4A和粘着层9在载板15上的正投影重叠，层叠的第一导电接点111和粘着层9在载板15上的正投影重叠。步骤S33可以按照如下步骤制作：将层叠的第一导电接点111和粘着层9以及层叠的第一导电接点111和粘着层9移动到重新布线层1上，并剥离载板15。It should be noted that, in the case where the first conductive contacts 111 and the first support layer 4A are fabricated simultaneously, the materials of the support film 16 and the adhesive film 17 are both conductive materials, and step S32 can be fabricated according to the following steps: The adhesive film 17 is patterned to form the laminated first support layer 4A and the adhesive layer 9 and the laminated first conductive contacts 111 and the adhesive layer 9; the orthographic projection of the laminated first support layer 4A and the adhesive layer 9 on the carrier board 15 Overlapping, the orthographic projections of the laminated first conductive contacts 111 and the adhesive layer 9 on the carrier board 15 overlap. Step S33 can be made as follows: the laminated first conductive contact 111 and the adhesive layer 9 and the laminated first conductive contact 111 and the adhesive layer 9 are moved to the redistribution layer 1 , and the carrier board 15 is peeled off.
实施例三 Embodiment 3
S40、如图28所示，在重新布线层1上形成支撑薄膜16。S40 , as shown in FIG. 28 , the support film 16 is formed on the redistribution layer 1 .
此处，可以利用溅射、沉积、涂覆等工艺在重新布线层1上形成支撑薄膜16。Here, the support film 16 may be formed on the redistribution layer 1 by sputtering, deposition, coating, or the like.
S41、如图13所示，对支撑薄膜16进行构图，形成第一支撑层4A。S41 , as shown in FIG. 13 , patterning the support film 16 to form the first support layer 4A.
此处，构图包括涂覆光刻胶层、掩膜曝光、显影以及刻蚀工艺。Here, patterning includes coating a photoresist layer, mask exposure, development, and etching processes.
需要说明的是，在第一导电接点111与第一支撑层4A同步制作的情况下，支撑薄膜16的材料为导电材料，步骤S41可以按照如下步骤制作：对支撑薄膜16进行构图，形成第一支撑层4A和第一导电接点111。It should be noted that, in the case where the first conductive contacts 111 and the first supporting layer 4A are produced simultaneously, the material of the supporting film 16 is a conductive material, and the step S41 can be produced according to the following steps: patterning the supporting film 16 to form a first The support layer 4A and the first conductive contact 111 .
基于上述步骤S10的三种具体实现方式，在第一支撑层4A的材料为金属材料的情况下，可以按照实施例一、实施例二或实施例三形成第一支撑层4A。在第一支撑层4A的材料为非金属材料的情况下，可以按照实施例二或实施例三形成第一支撑层4A。Based on the three specific implementation manners of the above step S10, when the material of the first support layer 4A is a metal material, the first support layer 4A may be formed according to Embodiment 1, Embodiment 2 or Embodiment 3. When the material of the first support layer 4A is a non-metallic material, the first support layer 4A can be formed according to the second embodiment or the third embodiment.
在此基础上，在扇出型封装结构01还包括第二支撑层4B的情况下，可以按照步骤S20～S23、S30～S33或S40～S41来制备第二支撑层4B。此外，第一支撑层4A和第二支撑层4B的制备方法可以相同，也可以不相同。以制备如图11所示的第一支撑层4A和第二支撑层4B为例，例如可以重复步骤S20～S23两次，以形成第一支撑层4A和第二支撑层4B。又例如，可以先按照步骤S20～S23形成第一支撑层4A，再按照步骤S30～S33形成第二支撑层4B。On this basis, when the fan-out package structure 01 further includes the second support layer 4B, the second support layer 4B may be prepared according to steps S20 to S23 , S30 to S33 or S40 to S41 . In addition, the preparation methods of the first support layer 4A and the second support layer 4B may be the same or different. Taking the preparation of the first support layer 4A and the second support layer 4B as shown in FIG. 11 as an example, for example, steps S20 to S23 may be repeated twice to form the first support layer 4A and the second support layer 4B. For another example, the first support layer 4A may be formed first according to steps S20 to S23, and then the second support layer 4B may be formed according to steps S30 to S33.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (20)

  1. 一种扇出型封装结构，其特征在于，包括：A fan-out package structure, characterized in that it includes:
    重新布线层；rewiring layer;
    第一芯片；the first chip;
    第一连接件；所述第一芯片通过所述第一连接件与所述重新布线层电连接；a first connector; the first chip is electrically connected to the redistribution layer through the first connector;
    设置在所述第一芯片与所述重新布线层之间，且与所述重新布线层接触的第一支撑层；a first support layer disposed between the first chip and the redistribution layer and in contact with the redistribution layer;
    填充于所述第一芯片周围的封装层；所述封装层包裹所述第一芯片、所述第一连接件以及所述第一支撑层。An encapsulation layer filled around the first chip; the encapsulation layer wraps the first chip, the first connection member and the first support layer.
  2. 根据权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括第二芯片；The fan-out package structure according to claim 1, wherein the fan-out package structure further comprises a second chip;
    所述第一支撑层包括第一支撑部分，所述第一支撑部分位于所述第一芯片和所述第二芯片之间的区域。The first support layer includes a first support portion located in a region between the first chip and the second chip.
  3. 根据权利要求1所述的扇出型封装结构，其特征在于，所述第一支撑层包括第一支撑部分，所述第一支撑部分包围所述第一芯片。The fan-out package structure of claim 1, wherein the first support layer comprises a first support portion, and the first support portion surrounds the first chip.
  4. 根据权利要求1～3任一项所述的扇出型封装结构，其特征在于，所述第一支撑层还包括第二支撑部分；所述第二支撑部分包括多个平行排布的第一支撑条和多个平行排布的第二支撑条；多个所述第一支撑条和多个所述第二支撑条相交；The fan-out package structure according to any one of claims 1 to 3, wherein the first support layer further comprises a second support part; the second support part comprises a plurality of first support parts arranged in parallel a support bar and a plurality of second support bars arranged in parallel; a plurality of the first support bars and a plurality of the second support bars intersect;
    所述第二支撑部分位于所述第一芯片的正下方，且所述第一连接件在所述重新布线层上的正投影与所述第二支撑部分在所述重新布线层上的正投影无重叠区域。The second support portion is located directly under the first chip, and the orthographic projection of the first connector on the redistribution layer and the orthographic projection of the second support portion on the redistribution layer No overlapping areas.
  5. 根据权利要求2所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括设置在所述第一支撑层远离所述重新布线层一侧，且与所述第一支撑层接触的第二支撑层；The fan-out package structure according to claim 2, wherein the fan-out package structure further comprises a side of the first support layer that is away from the redistribution layer, and is connected to the first support layer. a second support layer in layer contact;
    所述第二支撑层包括第三支撑部分，所述第三支撑部分位于所述第一芯片和所述第二芯片之间的区域。The second support layer includes a third support portion located in an area between the first chip and the second chip.
  6. 根据权利要求3所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括设置在所述第一支撑层远离所述重新布线层一侧，且与所述第一支撑层接触的第二支撑层；The fan-out package structure according to claim 3, wherein the fan-out package structure further comprises a side of the first support layer away from the redistribution layer, and is connected to the first support layer. a second support layer in layer contact;
    所述第二支撑层包括第三支撑部分，所述第三支撑部分包围所述第一芯片。The second support layer includes a third support portion surrounding the first chip.
  7. 根据权利要求4～6任一项所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括设置在所述第一支撑层远离所述重新布线层一侧，且与所述第一支撑层接触的第二支撑层；The fan-out package structure according to any one of claims 4 to 6, wherein the fan-out package structure further comprises a side of the first support layer away from the redistribution layer, and is arranged on a side of the first support layer away from the redistribution layer a second support layer in contact with the first support layer;
    所述第二支撑层包括第四支撑部分，所述第四支撑部分包括多个平行排布的第三支撑条和多个平行排布的第四支撑条；多个所述第三支撑条和多个所述第四支撑条相交；The second support layer includes a fourth support portion, and the fourth support portion includes a plurality of third support bars arranged in parallel and a plurality of fourth support bars arranged in parallel; a plurality of the third support bars and a plurality of the fourth support bars intersect;
    所述第四支撑部分位于所述第一芯片的正下方，且所述第一连接件在所述重新布线层上的正投影与所述第四支撑部分在所述重新布线层上的正投影无重叠区域。The fourth support portion is located directly under the first chip, and the orthographic projection of the first connector on the redistribution layer is the same as the orthographic projection of the fourth support portion on the redistribution layer No overlapping areas.
  8. 根据权利要求1所述的扇出型封装结构，其特征在于，所述重新布线层包括第一导电接点；所述第一连接件与所述第一导电接点电连接；The fan-out package structure according to claim 1, wherein the redistribution layer comprises a first conductive contact; the first connector is electrically connected to the first conductive contact;
    所述第一支撑层与所述第一导电接点同层同材料。The first support layer and the first conductive contacts are of the same layer and the same material.
  9. 根据权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括设置在所述第一支撑层与所述重新布线层之间的粘着层。The fan-out package structure according to claim 1, wherein the fan-out package structure further comprises an adhesive layer disposed between the first support layer and the redistribution layer.
  10. 根据权利要求1所述的扇出型封装结构，其特征在于，所述第一支撑层导电；所述重新布线层包括接地端子；The fan-out package structure according to claim 1, wherein the first support layer is conductive; the redistribution layer comprises a ground terminal;
    所述第一支撑层与所述重新布线层中的所述接地端子电连接。The first support layer is electrically connected to the ground terminal in the redistribution layer.
  11. 根据权利要求1所述的扇出型封装结构，其特征在于，所述第一支撑层的材料强度大于所述封装层的材料强度。The fan-out package structure according to claim 1, wherein the material strength of the first support layer is greater than the material strength of the package layer.
  12. 根据权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包括设置在所述重新布线层远离所述第一芯片一侧的第二连接件以及基板；所述第二连接件将所述重新布线层与所述基板电连接。The fan-out package structure according to claim 1, wherein the fan-out package structure further comprises a second connector and a substrate disposed on the side of the redistribution layer away from the first chip; the The second connector electrically connects the redistribution layer with the substrate.
  13. 根据权利要求1所述的扇出型封装结构，其特征在于，所述封装层的材料包括模塑化合物；The fan-out package structure of claim 1, wherein the material of the package layer comprises a molding compound;
    或者，所述封装层包括第一子封装层和第二子封装层；所述第一子封装层包围所述第一芯片，所述第二子封装层包围所述第一子封装层；所述第一子封装层的材料为底胶化合物，所述第二子封装层的材料为模塑化合物。Alternatively, the encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer; the first sub-encapsulation layer surrounds the first chip, and the second sub-encapsulation layer surrounds the first sub-encapsulation layer; the The material of the first sub-encapsulation layer is a primer compound, and the material of the second sub-encapsulation layer is a molding compound.
  14. 一种电子设备，其特征在于，包括如权利要求1～13任一项所述的扇出型封装结构和印刷电路板；An electronic device, characterized by comprising the fan-out package structure and a printed circuit board according to any one of claims 1 to 13;
    所述扇出型封装结构包括基板和第三连接件，所述第三连接件设置在所述基板远离重新布线层的一侧，所述基板通过所述第三连接件与所述印刷电路板电连接。The fan-out package structure includes a substrate and a third connection member, the third connection member is disposed on a side of the substrate away from the redistribution layer, and the substrate is connected to the printed circuit board through the third connection member electrical connection.
  15. 一种扇出型封装结构的制备方法，其特征在于，包括：A method for preparing a fan-out package structure, comprising:
    在重新布线层上形成第一支撑层；forming a first support layer on the redistribution layer;
    通过第一连接件将第一芯片绑定到所述重新布线层上，以使所述第一芯片与所述重新布线层电连接；Binding a first chip to the redistribution layer through a first connector, so as to electrically connect the first chip and the redistribution layer;
    填充封装层；所述封装层包裹所述第一芯片、所述第一连接件以及所述第一支撑层。Filling the encapsulation layer; the encapsulation layer wraps the first chip, the first connection member and the first support layer.
  16. 根据权利要求15所述的扇出型封装结构的制备方法，其特征在于，所述在重新布线层上形成第一支撑层，包括：The method for manufacturing a fan-out package structure according to claim 15, wherein the forming the first support layer on the redistribution layer comprises:
    在所述重新布线层上形成电镀种子层；forming a plating seed layer on the redistribution layer;
    在所述电镀种子层上形成光刻胶层；所述光刻胶层在待形成所述第一支撑层的区域镂空；forming a photoresist layer on the electroplating seed layer; the photoresist layer is hollowed out in the area where the first support layer is to be formed;
    在所述光刻胶层的镂空区域内电镀形成所述第一支撑层；forming the first support layer by electroplating in the hollow area of the photoresist layer;
    去除所述光刻胶层及其下方的所述电镀种子层。The photoresist layer and the plating seed layer below it are removed.
  17. 根据权利要求15所述的扇出型封装结构的制备方法，其特征在于，所述在重新布线层上形成第一支撑层，包括：The method for manufacturing a fan-out package structure according to claim 15, wherein the forming the first support layer on the redistribution layer comprises:
    在载板上形成支撑薄膜；forming a support film on the carrier;
    在所述支撑薄膜上贴附胶膜；attaching an adhesive film on the support film;
    对所述支撑薄膜和所述胶膜进行构图，形成第一支撑层和粘着层；所述第一支撑层和所述粘着层在所述载板上的正投影重叠；patterning the supporting film and the adhesive film to form a first supporting layer and an adhesive layer; the orthographic projections of the first supporting layer and the adhesive layer on the carrier plate overlap;
    将所述第一支撑层和所述粘着层移动到所述重新布线层上，并移除所述载板；其中，所述第一支撑层通过所述粘着层粘贴在所述重新布线层上。moving the first support layer and the adhesive layer onto the redistribution layer, and removing the carrier board; wherein the first support layer is pasted on the redistribution layer through the adhesive layer .
  18. 根据权利要求15所述的扇出型封装结构的制备方法，其特征在于，所述在重新布线层上形成第一支撑层，包括：The method for manufacturing a fan-out package structure according to claim 15, wherein the forming the first support layer on the redistribution layer comprises:
    在所述重新布线层上形成所述第一支撑层，并同步形成所述重新布线层的第一导电接点，所述第一连接件与所述第一导电接点电连接。The first support layer is formed on the redistribution layer, and a first conductive contact of the redistribution layer is simultaneously formed, and the first connection member is electrically connected to the first conductive contact.
  19. 根据权利要求15所述的扇出型封装结构的制备方法，其特征在于，所述填充封装层，包括：The method for preparing a fan-out package structure according to claim 15, wherein the filling the package layer comprises:
    通过塑模底部填充工艺填充所述封装层；filling the encapsulation layer by a mold underfill process;
    或者，通过毛细底部填充工艺填充第一子封装层；所述第一子封装层包围所述第一芯片；Alternatively, filling the first sub-package layer through a capillary underfill process; the first sub-package layer surrounds the first chip;
    通过塑模底部填充工艺填充第二子封装层；所述第二子封装层包围所述第一子封装层；其中，所述封装层包括所述第一子封装层和所述第二子封装层。The second sub-encapsulation layer is filled through a mold underfill process; the second sub-encapsulation layer surrounds the first sub-encapsulation layer; wherein the encapsulation layer includes the first sub-encapsulation layer and the second sub-encapsulation Floor.
  20. 根据权利要求15所述的扇出型封装结构的制备方法，其特征在于，在所述填充封装层之后，所述扇出型封装结构的制备方法还包括：The method for preparing a fan-out package structure according to claim 15, wherein after the filling of the packaging layer, the method for preparing the fan-out package structure further comprises:
    在所述重新布线层远离所述第一芯片的一侧形成与所述重新布线层电连接的第二连接件，并将所述第二连接件与基板电连接。A second connection member electrically connected to the redistribution layer is formed on a side of the redistribution layer away from the first chip, and the second connection member is electrically connected to the substrate.
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