CN115966476A - Wafer-level chip packaging method and packaging structure - Google Patents
Wafer-level chip packaging method and packaging structure Download PDFInfo
- Publication number
- CN115966476A CN115966476A CN202310016592.5A CN202310016592A CN115966476A CN 115966476 A CN115966476 A CN 115966476A CN 202310016592 A CN202310016592 A CN 202310016592A CN 115966476 A CN115966476 A CN 115966476A
- Authority
- CN
- China
- Prior art keywords
- chip
- packaging
- carrier plate
- layer
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The embodiment of the disclosure provides a wafer-level chip packaging method and a packaging structure, wherein the packaging method comprises the following steps: respectively providing a carrier plate, a chip and a radiating fin; wherein, the first surface of the chip is provided with a conductive bump; forming a circuit layer on the first surface of the carrier plate; fixing the first surface of the chip on the first surface of the carrier plate so that the conductive bump is electrically connected with the circuit layer; forming a plastic package layer on the first surface of the carrier plate and the second surface of the chip; fixing a heat sink on the second surface of the chip to form a package body; and cutting the packaging body to form a plurality of independent chip packaging structures. The cooling fins are fixed on the chip by adopting a wafer-level packaging process at one time, so that the mounting efficiency is high, the warpage generated in the mounting process is reduced, and the yield of chip packaging is increased; the radiating fin is fixed on the chip, so that the packaging structure can quickly radiate heat, the radiating effect is good, the radiating problem of the packaging structure is solved, and the reliability of the packaging structure is improved; no additional heat dissipation device is needed, and the structure is simple.
Description
Technical Field
The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a wafer-level chip packaging method and a wafer-level chip packaging structure.
Background
The heat dissipation method of the traditional chip package mainly adopts polymer and metal materials as heat dissipation and conduction tools or ways, and the heat dissipation and conduction of the traditional package methods have the defects that: most polymer materials have poor moisture resistance, chemical stability resistance and thermal conductivity; when the metal radiating fins are mounted, the metal radiating fins are required to be mounted on each chip one by one, the mounting efficiency is low, and the problem of warping can be caused; for a chip with high calorific value, an additional heat dissipation structure needs to be added, and the chip packaging structure is complex.
In view of the above problems, there is a need for a wafer level chip packaging method and a packaging structure with a reasonable design and capable of effectively solving the above problems.
Disclosure of Invention
The embodiments of the present disclosure are directed to at least one of the technical problems in the prior art, and provide a wafer level chip packaging method and a wafer level chip packaging structure.
An aspect of the embodiments of the present disclosure provides a wafer level chip packaging method, which
The packaging method comprises the following steps:
respectively providing a carrier plate, a chip and a radiating fin; the first surface of the chip is provided with a conductive bump;
forming a circuit layer on the first surface of the carrier plate;
fixing the first surface of the chip on the first surface of the carrier plate so that the conductive bump is electrically connected with the circuit layer;
forming a plastic package layer on the first surface of the carrier plate and the second surface of the chip;
fixing the heat sink on the second surface of the chip to form a package body;
and cutting the packaging body to form a plurality of independent chip packaging structures.
Optionally, the fixing the heat sink to the second surface of the chip includes:
fixing a radiating fin on a temporary carrier plate, wherein the mounting position of the radiating fin on the temporary carrier plate is consistent with the mounting position of the chip on the carrier plate;
forming a heat dissipation glue layer on the second surface of the chip;
fixing the radiating fins on the second surfaces of the corresponding chips at one time through the radiating adhesive layers by a wafer-to-wafer process;
and removing the temporary carrier plate.
Optionally, the material of the heat sink is a metal material or an organic material.
Optionally, the material of the heat sink is indium metal.
Optionally, the forming a circuit layer on the first surface of the carrier includes:
forming a dielectric layer on the first surface of the carrier plate;
patterning the dielectric layer to form a plurality of openings, and filling a conductive material in the plurality of openings to form a metal pad;
forming an interconnection conductive convex column on the surface of the metal bonding pad facing the chip; wherein a first end of the interconnecting conductive post is electrically connected to the metal pad, and a second end of the interconnecting conductive post is electrically connected to the conductive bump.
Optionally, before the fixing the heat sink to the second surface of the chip to form the package structure, the method further includes:
and thinning the surface of the plastic packaging layer deviating from the carrier plate to expose the second surface of the chip.
Optionally, before the package body is cut to form a plurality of independent chip package structures, the method further includes:
and removing the carrier plate to expose the circuit layer.
Optionally, each of the heat sinks corresponds to one of the chips, and the package body is cut to form a plurality of independent chip package structures, including:
and cutting along the gap between two adjacent radiating fins to form a plurality of independent chip packaging structures.
Optionally, the forming a molding compound layer on the first surface of the carrier and the second surface of the chip includes:
and forming a plastic package layer on the first surface of the carrier plate and the second surface of the chip by adopting a compression molding process, wherein the plastic package layer wraps the chip and the circuit layer.
Another aspect of the embodiments of the present disclosure provides a wafer level chip package structure, which is formed by the package method described above.
According to the wafer-level chip packaging method and the packaging structure, in the packaging method, the rapid heat dissipation effect of plastic solder ball array packaging and the high integration level of wafer-level chip packaging are combined, and the first surface of a chip is fixed on the first surface of a carrier plate; then forming a plastic packaging layer on the first surface of the carrier plate and the second surface of the chip; fixing the radiating fin on the second surface of the chip at one time by adopting a wafer-level packaging process to form a packaging body; and finally, cutting the packaging body to form a plurality of independent chip packaging structures. The cooling fins are fixed on the chip by adopting a wafer-level packaging process at one time, so that the mounting efficiency is high, the warpage generated in the mounting process is reduced, and the yield of chip packaging is increased; the radiating fin is fixed on the second surface of the chip, so that the packaging structure can quickly radiate heat, the radiating effect is good, the radiating problem of the packaging structure is solved, and the reliability of the packaging structure is improved; no additional heat dissipation device is needed, and the structure is simple.
Drawings
Fig. 1 is a schematic flow chart illustrating a wafer level chip packaging method according to an embodiment of the disclosure;
fig. 2 to 11 are schematic views illustrating a packaging process of a wafer level chip packaging method according to another embodiment of the disclosure;
fig. 12 is a schematic view of a wafer level chip package structure according to another embodiment of the disclosure.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and the detailed description.
As shown in fig. 1, an aspect of the embodiments of the present disclosure provides a wafer level chip packaging method S100, where the packaging method S100 includes:
s110, respectively providing a carrier plate, a chip and a radiating fin; the first surface of the chip is provided with a conductive bump.
Specifically, as shown in fig. 2, 3 and 8, a carrier board 110, a chip 120 and a heat sink 130 are provided, respectively. The first surface of the chip 120 is provided with a conductive bump 121. In this embodiment, the number of the chips 120 and the number of the heat sinks 130 are multiple, and the specific number is not specifically limited in this embodiment.
It should be understood that the first surface 122 of the chip 120 may be a front surface of the chip 120, or may be a back surface of the chip 120, and the details may be selected according to actual needs. In the present embodiment, the first surface of the chip 120 is taken as the front surface of the chip 120, and the second surface 123 of the chip 120 is taken as the back surface, that is, in the embodiment, the conductive bump 121 is formed on the front surface of the chip 120.
It should be noted that the carrier 110 may be a glass carrier or a silicon wafer, or may be a carrier made of other materials, and may be selected according to actual needs. In this embodiment, the carrier substrate 110 may be a silicon wafer.
It should be noted that in the present embodiment, the material of the conductive bump 121 is copper, but may be other conductive metals, and the present embodiment is not limited in particular. The conductive bumps 121 may lead out signals of the chip 120.
And S120, forming a circuit layer on the first surface of the carrier plate.
As shown in fig. 2, a circuit layer 140 is formed on the first surface of the carrier substrate 110. It should be understood that the first surface of the carrier substrate 110 may be a front surface of the carrier substrate 110, or may be a back surface of the carrier substrate 110, which may be selected according to actual needs. In the present embodiment, the first surface of the carrier 110 is taken as a front surface of the carrier 110 for an exemplary description. That is, the circuit layer 140 is formed on the front surface of the carrier substrate 110.
In order to form the circuit layer 140 shown in fig. 2 on the first surface of the carrier substrate 110, the following two patterning processes may be used.
The first patterning composition process comprises the following steps:
a dielectric layer 141 is formed on the front surface of the carrier 110, a photoresist layer is formed on the dielectric layer 141, and a mask is placed on the photoresist layer.
And exposing and developing the photoresist layer by using the mask as a mask to form a first opening on the photoresist layer.
The dielectric layer 141 is etched along the first openings using an etching process to form a plurality of openings.
A deposition process, such as electroplating or sputtering, is used to deposit a metal material at the plurality of openings to form the metal pads 142, and the photoresist layer is removed. The metal material can be copper metal or other metal materials, and can be selected according to actual needs.
Deposition processes, such as electroplating or sputtering, are continued to form interconnect conductive pillars 133 on the surface of metal pad 142 facing chip 120. A first end of the interconnection conductive pillar 143 is electrically connected to the metal pad 142, and a second end of the interconnection conductive pillar 143 is electrically connected to the conductive bump 121.
The second graphical composition process comprises the following steps:
a metal layer is formed on the front surface of the carrier substrate 110. The metal layer may be a copper layer or a metal layer made of other materials, and this embodiment is not particularly limited.
And forming a photoresist layer on the metal layer, and placing the mask plate on the photoresist layer.
And exposing and developing the photoresist layer by using the mask as a mask to form a plurality of second openings on the photoresist layer.
And etching the metal layer along the second opening by using an etching process to form the metal pad 142, and removing the photoresist layer.
A deposition process is used to form a dielectric layer 141 on the metal pad 142, and the dielectric layer 141 protects the metal pad 142.
Deposition processes, such as electroplating or sputtering, are continued to form interconnect conductive pillars 143 on the surface of metal pad 142 facing chip 120. A first end of the interconnection conductive pillar 143 is electrically connected to the metal pad 142, and a second end of the interconnection conductive pillar 143 is electrically connected to the conductive bump 121.
In this embodiment, the material of the dielectric layer 141 may be Polyimide (PI), polybenzoxazole (PBO), or the like, and the coating method is usually chip spin coating, which is not particularly limited in this embodiment.
It should be noted that, besides the two patterning processes described above for forming the circuit layer 140, a person skilled in the art may select other patterning methods according to actual needs, and the embodiment is not limited thereto.
S130, fixing the first surface of the chip on the first surface of the carrier plate, so that the conductive bump is electrically connected with the circuit layer.
As shown in fig. 3, the front surfaces of the chips 120 are fixed to the top surface of the carrier substrate 110, so that the conductive bumps 121 are electrically connected to the circuit layer 140. Specifically, as shown in fig. 4, a plurality of chips 120 are mounted one by one on the top surface of the carrier board 110. The plurality of chips 120 are distributed in a matrix on the top surface of the carrier plate 110. That is, the conductive bump 121 is electrically connected with the second end of the interconnection conductive pillar 143.
S140, forming a plastic package layer on the first surface of the carrier plate and the second surface of the chip.
Specifically, as shown in fig. 5, a molding layer 150 is formed on the top surface of the carrier substrate 110 and the back surface of the chip 120 by using a molding process, and the molding layer 150 wraps the chip 120 and the circuit layer 140. The molding layer 150 may protect the chip 120 and the circuit layer 140.
It should be noted that other plastic package processes may also be adopted to form the plastic package layer 150 on the first surface of the carrier plate 110 and the second surface of the chip 120, which is not specifically limited in this embodiment and may be selected according to actual situations. In addition, the molding compound may be an epoxy molding compound, such as epoxy resin, or may be another molding compound, which is not limited in this embodiment. Can be selected according to actual needs.
And S150, fixing the heat sink on the second surface of the chip to form a package body.
Before the heat sink 130 is fixed to the second surface of the chip 120 to form a package, the packaging method S100 further includes:
as shown in fig. 6, the surface of the molding compound layer 150 away from the carrier 110 is thinned by grinding and chemical mechanical polishing to expose the back surface of the chip 120.
To form a package as shown in fig. 9, the following packaging process may be employed.
First, as shown in fig. 7, the plurality of heat sinks 130 are fixed to the temporary boat 160. Wherein, the mounting positions of the plurality of heat sinks 130 are consistent with the mounting positions of the plurality of chips 120 on the carrier board 110.
Next, as shown in fig. 8, a heat dissipation adhesive layer 170 is formed on the second surface of the chip 120. That is, the thermal adhesive layer 170 is drawn and adhered to the back surfaces of the plurality of chips 120.
In the embodiment, the heat dissipation adhesive layer 170 is coated on the back surfaces of the plurality of chips 120 by blade coating, so that the process time can be greatly shortened, the uniformity in appearance is good, and no adhesive overflow occurs, thereby providing a good foundation for subsequently fixing the heat dissipation plate 130 on the back surface of the chip 120. So that the heat sink 130 is neatly arranged and substantially in the middle position without significant deviation.
The heat spreader 130 is fixed to the second surface of the chip 120 by the heat spreader adhesive layer 170. Specifically, as shown in fig. 7 and 9, a wafer to wafer (W2W) packaging process is adopted to fix a plurality of heat sinks 130 to the back surfaces of corresponding chips 120 at one time through a heat sink adhesive layer 170.
Finally, as shown in fig. 9, the temporary carrier 160 is removed, and the mounting of the heat sink 130 is completed.
In the embodiment, the cooling fin is fixed on the chip by adopting a wafer-level packaging process at one time, so that the mounting efficiency is high, the warpage generated in the mounting process is reduced, and the yield of chip packaging is increased.
For example, the material of the heat sink 130 may be a metal material or an organic material. Further preferably, in the present embodiment, the heat sink 130 is a metal indium plate.
And S160, cutting the packaging body to form a plurality of independent chip packaging structures.
For example, before the package body 100 is cut to form a plurality of independent chip package structures 100, the packaging method S100 further includes:
as shown in fig. 10, the carrier substrate 110 is removed to expose the circuit layer 140. Specifically, if the carrier 110 is a silicon wafer, the back surface of the silicon wafer may be ground by a grinding process or the like to expose the circuit layer 140. If the carrier plate 110 is a glass carrier plate, a carrier plate separation technique can be used to remove glass on the carrier plate, and the separation method can be thermal separation, laser separation, ultraviolet light separation, mechanical separation, and the like. The carrier plate 110 can be removed by a suitable process according to actual requirements.
Illustratively, each heat sink 130 corresponds to one chip 120, and the package is cut to form a plurality of independent chip package structures 100, which specifically include:
as shown in fig. 11, a plurality of independent chip package structures 100 are formed by cutting along the gap between two adjacent heat sinks 130. That is, a cutting street exists between two adjacent heat sinks 130, and the package is cut along the cutting street to form a plurality of independent chip package structures 100.
The wafer level chip packaging method disclosed by the embodiment of the invention combines the rapid heat dissipation effect of the plastic solder ball array package with the high integration level of the wafer level chip package, and fixes the first surface of the chip on the first surface of the carrier plate; then forming a plastic packaging layer on the first surface of the carrier plate and the second surface of the chip; fixing the radiating fin on the second surface of the chip at one time by adopting a wafer level packaging process to form a packaging body; and finally, cutting the packaging body to form a plurality of independent chip packaging structures. The cooling fins are fixed on the chip by adopting a wafer-level packaging process at one time, so that the mounting efficiency is high, the warpage generated in the mounting process is reduced, and the yield of chip packaging is increased; the radiating fin is fixed on the second surface of the chip, so that the packaging structure can quickly radiate heat, the radiating effect is good, the radiating problem of the packaging structure is solved, and the reliability of the packaging structure is improved; no additional heat dissipation device is needed, and the structure is simple.
Another aspect of the present disclosure provides a wafer-level chip package structure 100, where the package structure 100 is formed by the package method S100. The specific packaging steps of the packaging method S100 have been described in detail above, and are not described again.
The wafer level chip package structure 100 includes a chip 120, a heat spreader 130, a circuit layer 140 and a molding layer 150. The first surface of the chip 120 is provided with a conductive bump 121.
The circuit layer 140 is disposed on the first surface of the chip 120. That is, in the present embodiment, the circuit layer 140 is disposed on the front surface of the chip 120, and the circuit layer 140 is electrically connected to the conductive bump 121.
Further, in the present embodiment, the circuit layer 140 includes a dielectric layer 141, a metal pad 142, and an interconnection conductive pillar 143. The dielectric layer 141 is disposed on the front surface of the chip 120, the metal pad 142 is disposed on the dielectric layer 141, and the interconnection conductive pillar 143 is disposed on a side of the metal pad 142 facing the chip 120, wherein a first end of the interconnection conductive pillar 143 is electrically connected to the metal pad 142, and a second end of the interconnection conductive pillar 143 is electrically connected to the chip 120.
The molding layer 150 wraps the chip 120 and the circuit layer 140, and protects the chip 120 and the circuit layer 140.
The heat spreader 130 is disposed on the second surface of the chip 120. That is, the heat sink 130 is disposed on the back surface of the chip 120, and dissipates heat to the chip 120. The heat dissipation adhesive layer 170 is sandwiched between the heat dissipation plate 130 and the chip 120, the heat dissipation adhesive layer 170 plays a role in fixing, and the heat dissipation plate 130 can be fixed on the back surface of the chip 120 through the heat dissipation adhesive layer 170.
According to the wafer-level chip packaging structure disclosed by the embodiment of the disclosure, the radiating fins are fixed on the second surface of the chip through the radiating adhesive layer, so that the radiating effect is good and the structure is simple.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the disclosed embodiments, which are not limiting. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the embodiments of the present disclosure, and such modifications and improvements are also considered to be within the scope of the embodiments of the present disclosure.
Claims (10)
1. A wafer level chip packaging method is characterized by comprising the following steps:
respectively providing a carrier plate, a chip and a radiating fin; the first surface of the chip is provided with a conductive bump;
forming a circuit layer on the first surface of the carrier plate;
fixing the first surface of the chip on the first surface of the carrier plate so that the conductive bump is electrically connected with the circuit layer;
forming a plastic packaging layer on the first surface of the carrier plate and the second surface of the chip;
fixing the heat sink on the second surface of the chip to form a package body;
and cutting the packaging body to form a plurality of independent chip packaging structures.
2. The method of packaging of claim 1, wherein the securing the heat spreader to the second surface of the chip comprises:
fixing a radiating fin on a temporary carrier plate, wherein the mounting position of the radiating fin on the temporary carrier plate is consistent with the mounting position of the chip on the carrier plate;
forming a heat dissipation glue layer on the second surface of the chip;
fixing the radiating fins on the second surfaces of the corresponding chips at one time through the radiating adhesive layers by a wafer-to-wafer process;
and removing the temporary carrier plate.
3. The method of claim 2, wherein the material of the heat sink is a metal material or an organic material.
4. The method of claim 3, wherein the heat spreader is formed of indium metal.
5. The method for encapsulating according to any of claims 1 to 4, wherein the forming a circuit layer on the first surface of the carrier includes:
forming a dielectric layer on the first surface of the carrier plate;
patterning the dielectric layer to form a plurality of openings, and filling a conductive material in the plurality of openings to form a metal pad;
forming an interconnection conductive convex column on the surface of the metal pad facing the chip; wherein a first end of the interconnecting conductive post is electrically connected to the metal pad, and a second end of the interconnecting conductive post is electrically connected to the conductive bump.
6. The method of packaging according to any of claims 1 to 4, wherein before the step of attaching the heat sink to the second surface of the chip to form a package, the method further comprises:
and thinning the surface of the plastic packaging layer deviating from the carrier plate to expose the second surface of the chip.
7. The packaging method according to any one of claims 1 to 4, wherein before the step of cutting the package body to form a plurality of independent chip package structures, the method further comprises:
and removing the carrier plate to expose the circuit layer.
8. The packaging method according to any one of claims 1 to 4, wherein each of the heat sinks corresponds to one of the chips, and the cutting of the package body to form a plurality of independent chip package structures comprises:
and cutting along the gap between two adjacent radiating fins to form a plurality of independent chip packaging structures.
9. The method for packaging according to any one of claims 1 to 4, wherein forming a molding layer on the first surface of the carrier and the second surface of the chip comprises:
and forming a plastic package layer on the first surface of the carrier plate and the second surface of the chip by adopting a compression molding process, wherein the plastic package layer wraps the chip and the circuit layer.
10. A wafer level chip package structure, wherein the package structure is formed by the packaging method of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310016592.5A CN115966476A (en) | 2023-01-06 | 2023-01-06 | Wafer-level chip packaging method and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310016592.5A CN115966476A (en) | 2023-01-06 | 2023-01-06 | Wafer-level chip packaging method and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115966476A true CN115966476A (en) | 2023-04-14 |
Family
ID=87360036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310016592.5A Pending CN115966476A (en) | 2023-01-06 | 2023-01-06 | Wafer-level chip packaging method and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115966476A (en) |
-
2023
- 2023-01-06 CN CN202310016592.5A patent/CN115966476A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11387217B2 (en) | Semiconductor device and method of manufacture | |
| US11189603B2 (en) | Semiconductor packages and methods of forming same | |
| KR102197780B1 (en) | Semiconductor device and method of manufacture | |
| KR101677364B1 (en) | Semiconductor device and method of manufactures | |
| US8264085B2 (en) | Semiconductor device package interconnections | |
| US20030199121A1 (en) | Wafer scale thin film package | |
| WO2015183959A1 (en) | Structure and method for integrated circuits packaging with increased density | |
| JP6669586B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| KR102192014B1 (en) | Electronics card including multi-chip module | |
| US11532582B2 (en) | Semiconductor device package and method of manufacture | |
| KR20130054115A (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| KR102238309B1 (en) | Semiconductor device and method of manufacture | |
| CN113410144B (en) | Semiconductor device and method of forming the same | |
| US20230109128A1 (en) | Heat Dissipation in Semiconductor Packages and Methods of Forming Same | |
| US9842827B2 (en) | Wafer level system in package (SiP) using a reconstituted wafer and method of making | |
| CN115966476A (en) | Wafer-level chip packaging method and packaging structure | |
| KR20220051780A (en) | Semiconductor devices and methods of manufacture | |
| WO2022052072A1 (en) | Fan-out type packaging structure and production method therefor | |
| CN110660751A (en) | Chip package | |
| CN114914196B (en) | Local interposer 2.5D fan-out packaging structure and process based on core-grain concept | |
| CN117750784A (en) | Fan-out type packaging structure of high-density multi-chip and manufacturing method thereof | |
| CN115881558A (en) | Fan-out type embedded chip packaging method and packaging structure | |
| TW202312374A (en) | Stiffener frame for semiconductor device packages |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |