TWI416700B - Chip-stacked package structure and method for manufacturing the same - Google Patents

Chip-stacked package structure and method for manufacturing the same Download PDF

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Publication number
TWI416700B
TWI416700B TW099107660A TW99107660A TWI416700B TW I416700 B TWI416700 B TW I416700B TW 099107660 A TW099107660 A TW 099107660A TW 99107660 A TW99107660 A TW 99107660A TW I416700 B TWI416700 B TW I416700B
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wafer
substrate
relay substrate
substrate module
relay
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TW099107660A
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Chinese (zh)
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TW201123402A (en
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Yutang Pan
Shihwen Chou
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Chipmos Technologies Inc
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Publication of TWI416700B publication Critical patent/TWI416700B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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Abstract

The invention provides a chip-stacked package structure and a method for manufacturing the same.The chip-stacked package structure comprises a main substrate module, a first baseboard substrate module and a molding resin.The main substrate module comprises a substrate and a first chip.The substrate comprises a first surface and a second surface opposite to the first surface.The first chip disposed on the first surface is electrically connected with the substrate via first bumps.The first baseboard substrate module comprises a first baseboard substrate and a second chip.The first baseboard substrate comprises a core layer equipped with a plurality of first through holes and a first accommodation space in which the first chip is received.The second chip is disposed on the first baseboard substrate.The molding resin is used to encapsulate the main substrate module and the first baseboard substrate module.

Description

晶片堆疊封裝結構及其製造方法Wafer stacked package structure and manufacturing method thereof

本發明是有關於一種半導體封裝結構，且特別是有關於一種堆疊封裝結構。The present invention relates to a semiconductor package structure, and more particularly to a stacked package structure.

隨著電子產品功能與應用之需求的急遽增加，封裝技術亦朝著高密度微小化、單晶片封裝到多晶片封裝、二維尺度到三維尺度的方向發展。其中系統化封裝技術(System In Package)係一種可整合不同電路功能晶片的較佳方法，其利用表面黏著(Surface Mount Technology；SMT)製程將不同的晶片堆疊整合於同一基板上，藉以有效縮減封裝面積，具有體積小、高頻、高速、生產週期短與低成本之優點。As the demand for electronic product functions and applications increases rapidly, packaging technology is also moving toward high-density miniaturization, single-chip packaging to multi-chip packaging, and from two-dimensional to three-dimensional. System In Package is a preferred method for integrating different circuit function chips. It uses a Surface Mount Technology (SMT) process to integrate different wafer stacks on the same substrate, thereby effectively reducing the package. The area has the advantages of small size, high frequency, high speed, short production cycle and low cost.

請參照第4圖，第4圖係根據一習知的晶片堆疊封裝結構700所繪示的結構剖面圖。晶片堆疊封裝結構700包括基板510、第一晶片520、第二晶片530以及複數條打線540和550。其中第一晶片520固設於基材510之上，並藉由打線540與基材510電性連接。第二晶片530堆疊於第一晶片520之上，且藉由打線550與基板510電性連接。Please refer to FIG. 4, which is a cross-sectional view of a structure according to a conventional wafer stack package structure 700. The wafer stack package structure 700 includes a substrate 510, a first wafer 520, a second wafer 530, and a plurality of wires 540 and 550. The first wafer 520 is fixed on the substrate 510 and electrically connected to the substrate 510 by the wire 540. The second wafer 530 is stacked on the first wafer 520 and electrically connected to the substrate 510 by the bonding wires 550.

然而，由於疊設於上層的晶片，例如第二晶片530，必須遷就下層晶片(第一晶片520)的打線(打線540)配置，因此上層晶片(第二晶片530)尺寸必須小於下層晶片。同時也限制了晶片堆疊的數量與整體厚度的彈性。又因為上層晶片的尺寸較小，必須延長打線550的配線長度並擴大其線弧，方能使其與基材510電性連接。當後續進行壓模製程時，該些被延長的打線容易受到沖移，而出現短路的現象，影響製程良率。However, since the wafer stacked on the upper layer, for example, the second wafer 530, must be placed in the wire bonding (wire bonding 540) configuration of the lower wafer (first wafer 520), the upper wafer (second wafer 530) must be smaller in size than the lower wafer. It also limits the flexibility of the number of wafer stacks and the overall thickness. Moreover, since the size of the upper layer wafer is small, it is necessary to extend the wiring length of the wire 550 and expand the line arc to electrically connect it to the substrate 510. When the subsequent molding process is performed, the extended wire is easily subjected to the displacement, and a short circuit occurs, which affects the process yield.

請參照第5圖，第5圖係根據另一種晶片堆疊封裝結構800所繪示的結構剖面圖。晶片堆疊封裝結構800包括基板610、第一晶片620、第二晶片630、複數條打線640和650以及位於第一晶片620和第二晶片630之間的虛擬晶片660。其中第一晶片620疊設於基板610上，並藉由打線640使第一銲墊670與基材610電性連接。虛擬晶片660疊設於第一晶片620之上。第二晶片則疊設於虛擬晶片660之上，並藉由打線650使第二銲墊680與基材610電性連接。藉由尺寸小於第一晶片620的虛擬晶片660的設置，不僅可在第一晶片620和第二晶片630之間，提供足夠的佈線空間與線弧高度，以容納打線640，而且不會限制上層晶片(第二晶片630)的堆疊尺寸。因此第二晶片630之尺寸實質等於第一晶片620之尺寸。Please refer to FIG. 5, which is a cross-sectional view of the structure according to another wafer stack package structure 800. The wafer stack package structure 800 includes a substrate 610, a first wafer 620, a second wafer 630, a plurality of wires 640 and 650, and a dummy wafer 660 between the first wafer 620 and the second wafer 630. The first wafer 620 is stacked on the substrate 610 , and the first pad 670 is electrically connected to the substrate 610 by the wire 640 . The dummy wafer 660 is stacked on the first wafer 620. The second wafer is stacked on the dummy wafer 660, and the second bonding pad 680 is electrically connected to the substrate 610 by the bonding wire 650. By the arrangement of the dummy wafer 660 having a smaller size than the first wafer 620, not only a sufficient wiring space and a line arc height can be provided between the first wafer 620 and the second wafer 630 to accommodate the wire 640, and the upper layer is not limited. The stack size of the wafer (second wafer 630). Therefore, the size of the second wafer 630 is substantially equal to the size of the first wafer 620.

然而虛擬晶片的設置，不僅會增加晶片堆疊的厚度，且徒增製程成本，更限制了結構微小化與高密度的趨勢。However, the setting of the virtual chip not only increases the thickness of the wafer stack, but also increases the process cost, and further limits the trend of miniaturization and high density.

因此有需要提供一種良率高、製程低廉且不會限制封裝密度的晶片堆疊封裝結構。Therefore, there is a need to provide a wafer stack package structure that has high yield, low process, and does not limit package density.

本發明的一目的在提供一種晶片堆疊封裝結構。該晶片堆疊封裝結構包含一主要基板模組、一第一中繼基板模組以及一封膠樹脂。主要基板模組包含一基板以及一第一晶片。基板具有一第一表面與相對的第二表面，第一表面上設置有一第一晶片接合區以及複數個第一銲墊。第一晶片具有一第一主動面與一第一晶背，第一主動面上係具有複數個第一凸塊，並以其第一凸塊覆晶接合於基板之第一晶片接合區。第一中繼基板模組包含一第一中繼基板以及一第二晶片，第一中繼基板更包含一核心層、一圖案化線路層以及一銲罩層。核心層係具有複數個第一開孔(through hole)與一第一容置空間，第一容置空間係容置第一晶片，而複數個第一開孔內係設置有至少一第一介層導通材(via plug)以與基板之第一銲墊接合。圖案化線路層形成於核心層上且與至少一介層導通材電性連接。銲罩層覆蓋設置於該少一圖案化線路層上，且第一銲罩層具有至少一開口以暴露部分至少一圖案化線路層以形成一第二晶片接合區。第二晶片具有一第二主動面與一第二晶背，第二主動面上設置有複數個第二凸塊，並以第二凸塊覆晶接合於該第一中繼基板上銲罩層之第二晶片接合區中。封膠樹脂包覆主要基板模組以及第一中繼基板模組。It is an object of the present invention to provide a wafer stack package structure. The wafer stack package structure comprises a main substrate module, a first relay substrate module and a glue resin. The main substrate module includes a substrate and a first wafer. The substrate has a first surface and an opposite second surface. The first surface is provided with a first wafer bonding region and a plurality of first pads. The first wafer has a first active surface and a first crystal back. The first active surface has a plurality of first bumps and is flip-chip bonded to the first wafer bonding region of the substrate by the first bump. The first relay substrate module includes a first relay substrate and a second wafer. The first relay substrate further includes a core layer, a patterned circuit layer, and a solder mask layer. The core layer has a plurality of first through holes and a first accommodating space. The first accommodating space houses the first wafer, and the plurality of first openings are provided with at least one first medium. A via plug is bonded to the first pad of the substrate. The patterned circuit layer is formed on the core layer and electrically connected to the at least one via conductive material. The solder mask layer is disposed on the one less patterned circuit layer, and the first solder mask layer has at least one opening to expose a portion of the at least one patterned wiring layer to form a second wafer bonding region. The second wafer has a second active surface and a second crystal back. The second active surface is provided with a plurality of second bumps, and the second bump is flip-chip bonded to the solder mask layer on the first relay substrate. In the second wafer junction region. The sealant resin covers the main substrate module and the first relay substrate module.

在本發明之一實施例中，該第一中繼基板之銲罩層上設有複數個第二開孔，以暴露出部份之圖案化線路層形成有至少一第二銲墊。In an embodiment of the invention, the solder mask layer of the first relay substrate is provided with a plurality of second openings to expose a portion of the patterned circuit layer to form at least one second pad.

在本發明之一實施例中，更包含一第二中繼基板模組，其具有與第一中繼基板相同之構件，第二中繼基板係垂向堆疊於第一中繼基板模組之第一中繼基板上以形成上下層堆疊結構，且該第二中繼基板模組之該些第二銲墊電性連接至該第一中繼基板。在本發明之一實施例中，該第一中繼基板之第一介層導通材與基板之第一銲墊之間係設有第一銲鍚，以提供較佳之結合性，其中該第一銲錫之材質較佳的可為鍚鉛或無鉛等銲料材質。In an embodiment of the invention, the second relay substrate module has the same component as the first relay substrate, and the second relay substrate is vertically stacked on the first relay substrate module. The first relay substrate is formed to form an upper and lower layer stack structure, and the second pads of the second relay substrate module are electrically connected to the first relay substrate. In one embodiment of the present invention, a first solder fillet is disposed between the first via conductive material of the first relay substrate and the first solder pad of the substrate to provide better bonding, wherein the first The solder material is preferably a solder material such as lead-lead or lead-free.

在本發明之一實施例中，更包含該複數個銲球(solder bump)設置於該基板之該第二表面。In an embodiment of the invention, the plurality of solder bumps are further disposed on the second surface of the substrate.

在本發明之一實施例中，更包含一黏著層(adhesive)設置於至少一圖案化線路層與第一晶片的第一晶背之間。In an embodiment of the invention, an adhesive layer is further disposed between the at least one patterned circuit layer and the first crystal back of the first wafer.

在本發明之一實施例中，更包括一充填膠(underfill material)，包覆該些第一凸塊與第二凸塊。In an embodiment of the invention, an underfill material is further included to cover the first bumps and the second bumps.

本發明的再一目的在提供一種晶片堆疊封裝結構的製造方法。此方法包含下列步驟，首先，先提供一主要基板模組，該主要基板模組包含一基板與一第一晶片。基板具有一第一表面與相對的第二表面，基板之第一表面上具有一第一晶片接合區及至少一第一銲墊。第一晶片具有一第一主動面與一第一晶背，其中第一主動面上設置有複數個第一凸塊，並覆晶接合且電性連接於該基板的第一晶片接合區上。接著，提供一第一中繼基板模組疊設於該主要基板模組之基板上，該第一中繼基板模組包含一第一中繼基板及一第二晶片。第一中繼基板更包含一核心層、一圖案化線路層以及一銲罩層。核心層具有複數個第一開孔以及一第一容置空間容置該第一晶片。而複數個第一開孔內係設置有至少一第一介層導通材(via plug)以與主要基板之第一銲墊接合。圖案化線路層形成於核心層上且與至少一第一介層導通材電性連接。銲罩層(solder mask)覆蓋設置於至少一圖案化線路層上，且銲罩層具有至少一開口以暴露部分至少一圖案化線路層，以形成一第二晶片接合區。第二晶片具有一第二主動面與一第二晶背，第二主動面上設置有複數個第二凸塊，並藉由第二凸塊覆晶接合且電性連接於該第一中繼基板之銲罩層之第二晶片接合區中。最後，使用一封膠樹脂以封裝該主要基板模組與該第一中繼基板模組。It is still another object of the present invention to provide a method of fabricating a wafer stack package structure. The method includes the following steps. First, a main substrate module is provided. The main substrate module includes a substrate and a first wafer. The substrate has a first surface and an opposite second surface, and the first surface of the substrate has a first wafer bonding region and at least one first bonding pad. The first wafer has a first active surface and a first crystal back. The first active surface is provided with a plurality of first bumps, and is flip-chip bonded and electrically connected to the first wafer bonding region of the substrate. Then, a first relay substrate module is stacked on the substrate of the main substrate module, and the first relay substrate module includes a first relay substrate and a second wafer. The first relay substrate further includes a core layer, a patterned circuit layer, and a solder mask layer. The core layer has a plurality of first openings and a first receiving space for receiving the first wafer. And a plurality of first vias are provided with at least one first via plug to be bonded to the first pad of the main substrate. The patterned circuit layer is formed on the core layer and electrically connected to the at least one first via conductive material. A solder mask cover is disposed on the at least one patterned wiring layer, and the solder mask layer has at least one opening to expose a portion of the at least one patterned wiring layer to form a second wafer bonding region. The second wafer has a second active surface and a second crystal back. The second active surface is provided with a plurality of second bumps, and is flip-chip bonded by the second bump and electrically connected to the first relay. The second wafer bonding region of the solder mask layer of the substrate. Finally, a glue resin is used to encapsulate the main substrate module and the first relay substrate module.

在本發明之一實施例中，在該提供主要基板模組之步驟更包含提供複數個銲球設置於該基板之該第二表面。In an embodiment of the invention, the step of providing the main substrate module further includes providing a plurality of solder balls disposed on the second surface of the substrate.

在本發明之一實施例中，在使用該封膠樹脂以封裝該主要基板模組與該中繼基板模組的步驟之前，更包含提供另一與構件與第一中繼基板模組相同之第二中繼基板模組垂向堆疊且電性連接於該第一中繼基板模組之第一中繼基板上，以形成上下堆疊型態。In an embodiment of the present invention, before the step of using the sealant resin to encapsulate the main substrate module and the relay substrate module, the method further includes providing the same component as the first relay substrate module. The second relay substrate module is vertically stacked and electrically connected to the first relay substrate of the first relay substrate module to form an upper and lower stacked type.

根據以上所述之實施例，本發明的技術特徵係在覆晶堆疊的下層晶片之晶背上，設置一具圖案化線路層之中繼基板模組，藉由圖案化線路層的佈線(或開孔)和後續堆疊於其上的上層晶片之銲墊(或銲錫)電性匹配。藉此，在連接上層晶片與基板時不需要延長打線長度或加大打線弧度，以解決習知技術中，線弧過大的缺點。According to the embodiments described above, the technical feature of the present invention is to provide a patterned substrate layer relay substrate module on the crystal back of the underlying wafer of the flip chip stack, by patterning the wiring of the circuit layer (or The opening is electrically matched to the pads (or solder) of the upper wafer that is subsequently stacked thereon. Therefore, when the upper layer wafer and the substrate are connected, it is not necessary to extend the wire length or increase the wire arc to solve the disadvantage that the wire arc is too large in the prior art.

在堆疊晶片至封裝結構上時，介層導通材及晶片覆晶方式取代打線以電性連接晶片堆疊封裝結構中的晶片與基板。本發明之實施例具有增加散熱、改善基板與晶片的電性連接，以及降低晶片堆疊封裝結構整體厚度的優點。When stacking the wafer onto the package structure, the via conductive material and the wafer flip-chip method replace the bonding wires to electrically connect the wafer and the substrate in the wafer stacked package structure. Embodiments of the present invention have the advantage of increasing heat dissipation, improving the electrical connection of the substrate to the wafer, and reducing the overall thickness of the wafer stack package structure.

可以了解的是上述內容和後附之說明書內容，將藉由實施例以更明顯易懂並作進一步的說明。It is to be understood that the foregoing and the subject matter of the appended claims will

為更進一步闡述本發明為達成預定發明目的所採取的技術手段及功效，以下結合附圖及實施例，對依據本發明提出的具體實施方式、結構、特徵及其功效，詳細說明如後，其中：In order to further explain the technical means and functions of the present invention for achieving the intended purpose of the present invention, the specific embodiments, structures, features and functions according to the present invention will be described in detail below with reference to the accompanying drawings and embodiments. :

請參照第1圖，第1圖係根據本發明的第一實施例所繪示之晶片堆疊封裝結構400的剖面示意圖。晶片堆疊封裝結構400包含一主要基板模組400a、一第一中繼基板模組400b以及一封膠樹脂421。該主要基板模組400a包含一基板401以及一第一晶片402，其中：基板401具有一第一表面416及相對於第一表面416的第二表面417。基板401之第一表面416上係設置有一內具導電線路之晶片接合區452及複數個設置於晶片接合區452周圍之第一銲墊420c，在一實施例中，該第一銲墊420c上亦可設置有一第一銲錫420a，藉以提供一較佳之黏合性，其中，該第一銲錫420a之材質較佳的可為鍚鉛或無鉛等銲料材質。在本發明一些實施例中，基板401可係由導線架、印刷電路板或晶粒承載器所構成。而在本實施例之中，基板401係一晶粒承載器，其材質例如是BT或者是FR4、FR5電路板或者是其他軟性電路板。Please refer to FIG. 1 , which is a cross-sectional view of a wafer stack package structure 400 according to a first embodiment of the present invention. The wafer stack package structure 400 includes a main substrate module 400a, a first relay substrate module 400b, and a glue resin 421. The main substrate module 400a includes a substrate 401 and a first wafer 402. The substrate 401 has a first surface 416 and a second surface 417 opposite to the first surface 416. The first surface 416 of the substrate 401 is provided with a wafer bonding region 452 having a conductive line and a plurality of first pads 420c disposed around the wafer bonding region 452. In an embodiment, the first bonding pad 420c is disposed on the first bonding pad 420c. A first solder 420a may be disposed to provide a better adhesion. The material of the first solder 420a may preferably be a lead-based or lead-free solder material. In some embodiments of the invention, the substrate 401 may be constructed of a leadframe, a printed circuit board, or a die carrier. In the present embodiment, the substrate 401 is a die carrier, and the material thereof is, for example, BT or FR4, FR5 circuit board or other flexible circuit board.

第一晶片402具有一第一主動面403、一第一晶背404以及複數個凸塊409a設置於第一主動面403上。並以該複數個凸塊409a面對基板401的晶片接合區452覆晶接合，藉由第一凸塊409a電性連接至基板401，並利用一充填膠414包覆第一凸塊409a，以密封該第一晶片402與基板401之間隙。The first wafer 402 has a first active surface 403, a first crystal back 404, and a plurality of bumps 409a disposed on the first active surface 403. And the plurality of bumps 409a are flip-chip bonded to the wafer bonding region 452 of the substrate 401, the first bumps 409a are electrically connected to the substrate 401, and the first bumps 409a are covered by a filling adhesive 414. The gap between the first wafer 402 and the substrate 401 is sealed.

第一中繼基板模組400b包含一第一中繼基板450及第二晶片407。該第一中繼基板450更進一步的包含下列構件：一第一核心層413、一圖案化線路層405以及一銲罩層422。第一核心層413上具有複數個第一開孔426及一第一容置空間437，且該第一開孔426內係設置有第一介層導通材406，該第一介層導通材406為一種導電材料，例如為銅、鋁或銀等導電材質形成於第一開孔426之內孔壁或填充於第一開孔426內，並以其二端部顯露於該第一核心層413之上、下表面。圖案化線路層405為導電材料而設置於第一核心層413上，且與該第一介層導通材406電性連接。如第1圖所示，第一容置空間437暴露出部分之圖案化線路層405。銲罩層422是覆蓋設置在圖案化線路層405上，並具有一開口以暴露出部分的圖案化線路層405(同時參照第3B圖)，並形成中繼基板450上供第二晶片407接合之晶片接合區451，於一實施例中，該銲罩層422上更設置有第二開孔425以暴露出部分的圖案化線路層405，並於對應第二開孔425內之圖案化線路層405形成一第二銲墊424a。The first relay substrate module 400b includes a first relay substrate 450 and a second wafer 407. The first relay substrate 450 further includes the following components: a first core layer 413, a patterned wiring layer 405, and a solder mask layer 422. The first core layer 413 has a plurality of first openings 426 and a first receiving space 437, and the first opening 426 is provided with a first via conductive material 406. The first dielectric conductive material 406 is disposed. A conductive material, such as copper, aluminum or silver, is formed in the inner wall of the first opening 426 or filled in the first opening 426, and is exposed at the first core layer 413 at both ends thereof. Upper and lower surfaces. The patterned wiring layer 405 is disposed on the first core layer 413 as a conductive material, and is electrically connected to the first via conductive material 406. As shown in FIG. 1, the first accommodating space 437 exposes a portion of the patterned wiring layer 405. The solder mask layer 422 is a patterned wiring layer 405 disposed on the patterned wiring layer 405 and having an opening to expose a portion (see also FIG. 3B), and is formed on the relay substrate 450 for bonding the second wafer 407. In the embodiment, the solder mask layer 422 is further provided with a second opening 425 to expose a portion of the patterned circuit layer 405 and patterned lines corresponding to the second opening 425. Layer 405 forms a second pad 424a.

藉此，第一核心層413、一圖案化線路層405、一銲罩層422予以構成一第一中繼基板450，而以第一核心層413暴露出第一介層導通材406之下表面為整個第一中繼基板450之第四表面417a，而銲罩層422之上表面為整個第一中繼基板450之第三表面416a，並以該第一中繼基板450 之第四表面417a面對該基板401，且該第一核心層403上所顯露之第一介層導通材406端部與基板401之第一銲墊420c接合；於另一較佳之實施例中，第一中繼基板400b的圖案化線路層405與第一晶片402的第一晶背404之間更設置有一黏著層419，以提供第一中繼基板450黏結於主要基板模組400a上形成上下堆疊型態，其中，該黏著層419之材質可為B-Stage、銀膠、散熱膠等膠材。Thereby, the first core layer 413, the patterned circuit layer 405, and the solder mask layer 422 constitute a first relay substrate 450, and the first core layer 413 exposes the lower surface of the first via conductive material 406. The fourth surface 417a of the entire first relay substrate 450, and the upper surface of the solder mask layer 422 is the third surface 416a of the entire first relay substrate 450, and the first relay substrate 450 The fourth surface 417a faces the substrate 401, and the end of the first via conductive material 406 exposed on the first core layer 403 is bonded to the first solder pad 420c of the substrate 401; in another preferred embodiment An adhesive layer 419 is disposed between the patterned wiring layer 405 of the first relay substrate 400b and the first crystal back 404 of the first wafer 402 to provide a first relay substrate 450 bonded to the main substrate module 400a. The upper and lower stacking patterns, wherein the adhesive layer 419 can be made of B-Stage, silver glue, heat-dissipating glue or the like.

第二晶片407具有一第二主動面408、第二晶背431與複數個設置於第二主動面408上的第二凸塊409b。第二晶片407以其第二凸塊409b覆晶接合於中繼基板450之晶片接合區451，且藉由第二凸塊409b電性連接至圖案化線路層405。最後再利用一充填膠414包覆密封該些第二凸塊409b。The second wafer 407 has a second active surface 408, a second crystal back 431 and a plurality of second bumps 409b disposed on the second active surface 408. The second wafer 407 is flip-chip bonded to the wafer bonding region 451 of the relay substrate 450 by its second bump 409b, and is electrically connected to the patterned wiring layer 405 by the second bump 409b. Finally, the second bumps 409b are covered by a filling adhesive 414.

封膠樹脂421是用來封裝主要基板模組400a以及第一中繼模組400b，以密封形成一堆疊封裝體400。The encapsulating resin 421 is used to encapsulate the main substrate module 400a and the first relay module 400b to form a stacked package 400.

最後，在基板401的第二表面417上形成複數個外部端子，例如複數個銲球411，以使基板401與至少一外部電子裝置(未繪示)電性連接。在一實施例中，基板401與第一中繼基板450之底部均設置有銲罩層412。其中，第一中繼基板450在第三表面417a的銲罩層412具有複數個開口以暴露出部份的第一介層導通材406。而基板401底部的銲罩層412具有複數個開口以提供複數個銲球411電性連接至基板401。Finally, a plurality of external terminals, such as a plurality of solder balls 411, are formed on the second surface 417 of the substrate 401 to electrically connect the substrate 401 to at least one external electronic device (not shown). In an embodiment, a solder mask layer 412 is disposed on both the substrate 401 and the bottom of the first relay substrate 450. The first relay substrate 450 has a plurality of openings in the solder mask layer 412 of the third surface 417a to expose a portion of the first via conductive material 406. The solder mask layer 412 at the bottom of the substrate 401 has a plurality of openings to provide a plurality of solder balls 411 electrically connected to the substrate 401.

雖然第1圖所示只述及特定數目及類型的元件，例如圖案化線路層、介層導通材或銲墊，這些數目及類型僅僅 只是作為舉例而並非是用以限制本發明，也就是其他實施例可能包含其他圖式未繪示的元件，以及可能包含超過所繪示的一種以上的元件。此技術領域中熟悉此技藝者應可知道的是圖案化線路層405可具有複數個電路(未繪示)以及電性連接端子(未繪示)。Although only a specific number and type of components are described in Figure 1, such as patterned circuit layers, vias or pads, these numbers and types are only The invention is not limited by the following description, and other embodiments may include other elements not shown in the drawings, and may include more than one of the elements illustrated. It should be understood by those skilled in the art that the patterned circuit layer 405 can have a plurality of circuits (not shown) and electrical connection terminals (not shown).

請參照第2圖，第2圖係根據本發明的第二實施例所繪示之晶片堆疊封裝結構500的剖面示意圖。晶片堆疊封裝結構500與晶片堆疊封裝結構400大致上相同，相異之處在於晶片堆疊封裝結構500更包含一第二中繼基板模組400c，該第二中繼基板模組400c係包含一第二中繼基板460及第三晶片430，該二中繼基板模組400c係垂向堆疊於第一中繼基板模組400b之第一中繼基板450上，透過該第一中繼基板450上第一開孔426內之第一銲墊420c電性連接。值得注意的是，該第二中繼基板460具有與第一中繼基板450相同的結構，亦包含核心層441、一圖案化線路層438以及一銲罩層442等構件，且該第三晶片430電性連接於第二中繼基板400c之方式亦與前述實施例相同，因此，於此不再贅述其構件型態及接合方式。Referring to FIG. 2, FIG. 2 is a cross-sectional view of a wafer stack package structure 500 according to a second embodiment of the present invention. The wafer stack package structure 500 is substantially the same as the wafer stack package structure 400. The wafer stack package structure 500 further includes a second relay substrate module 400c, and the second relay substrate module 400c includes a first The second relay substrate 460 and the third wafer 430 are vertically stacked on the first relay substrate 450 of the first relay substrate module 400b, and are transmitted through the first relay substrate 450. The first pads 420c in the first openings 426 are electrically connected. It should be noted that the second relay substrate 460 has the same structure as the first relay substrate 450, and also includes a core layer 441, a patterned circuit layer 438, and a solder mask layer 442, and the third wafer. The manner in which the 430 is electrically connected to the second relay substrate 400c is also the same as that of the foregoing embodiment. Therefore, the component type and the bonding mode will not be described herein.

雖然第2圖所示只述及特定數目及類型的元件，例如圖案化線路層、介層導通材或銲墊，這些數目及類型僅僅只是作為舉例而並非是用以限制本發明，也就是其他實施例可能包含其他圖式未繪示的元件，以及可能包含超過所繪示的一種以上的元件；然而，具有三個或更多晶片的封裝結構也應在本發明實施例的範圍與精神內。此技術領域中熟悉此技藝者應可知道的是圖案化線路層438可具有複 數個電路(未繪示)以及電性連接端子(未繪示)。Although only a specific number and type of components are illustrated in FIG. 2, such as patterned circuit layers, vias, or pads, these numbers and types are by way of example only and are not intended to limit the invention, that is, other The embodiments may include other elements not shown in the drawings, and may include more than one of the illustrated elements; however, a package structure having three or more wafers should also be within the scope and spirit of the embodiments of the present invention. . It will be appreciated by those skilled in the art that patterned circuit layer 438 can have complex Several circuits (not shown) and electrical connection terminals (not shown).

請參照第3A至3E圖，第3A至3E圖係繪示依據本發明第五實施例之晶片堆疊封裝結構500的製造流程，其結構構件型態均與前述實施例相同，因此不再贅述。Referring to FIGS. 3A to 3E, FIGS. 3A to 3E are diagrams showing a manufacturing process of the wafer stack package structure 500 according to the fifth embodiment of the present invention, and the structural member patterns are the same as those of the foregoing embodiment, and thus will not be described again.

參照第3A圖，首先，提供一主要基板模組400a。該基板401之晶片接合區452上係以覆晶方式設置一第一晶片402，使該第一晶片402之第一凸塊409a與基板401電性連接後，再以充填膠414密封該些第一凸塊409a，如此一來，即形成一主要基板模組400a；參照第3B圖，提供一第一中繼基板模組400b。第一中繼基板模組400b包含如前所述的第一中繼基板450以及第二晶片407，其中第一中繼基板450包含了第一核心層413、圖案化線路層405、銲罩層422、第一介層導通材406；並於該第一中繼基板400b之晶片接合區451上覆晶設置一第二晶片407，並透過第二凸塊409b與第一中繼基板400a電性導通，再以充填膠414密封該些第二凸塊409b。在一實施例中，可在第一核心層413下方形成一層銲罩層412，並暴露出至少二開口以暴露出第一介層導通材406。Referring to FIG. 3A, first, a main substrate module 400a is provided. A first wafer 402 is formed on the wafer bonding region 452 of the substrate 401 in a flip chip manner, and the first bumps 409a of the first wafer 402 are electrically connected to the substrate 401, and then sealed by the filling adhesive 414. A bump 409a is formed to form a main substrate module 400a. Referring to FIG. 3B, a first relay substrate module 400b is provided. The first relay substrate module 400b includes the first relay substrate 450 and the second wafer 407 as described above, wherein the first relay substrate 450 includes the first core layer 413, the patterned circuit layer 405, and the solder mask layer. 422, the first via conductive material 406; and a second wafer 407 is flip-chip mounted on the wafer bonding region 451 of the first relay substrate 400b, and is electrically connected to the first relay substrate 400a through the second bump 409b. After being turned on, the second bumps 409b are sealed with a filling glue 414. In one embodiment, a layer of solder mask 412 may be formed under the first core layer 413 and expose at least two openings to expose the first via conductive material 406.

參照第3C圖，接著將第一中繼基板400b以其第四表面408面對該主要基板模組400a之基板401堆疊接合，而該第一介層導通材406係相對位於基板401上之第一銲墊420c接合。並利用一黏著層419塗佈於第一中繼基板450的圖案化線路層405與第一晶片402的第一晶背404之間，以將主要基板模組400a與第一中繼基板450結合一起。藉由第一介層導通材406將第二晶片407經由第一中 繼基板400b上之圖案化線路層405與主要基板模組400a電性連接。於另一較佳之實施例中，該第一銲墊420c上係可設置一第一銲鍚420a，藉以提供第一中繼基板模組400b與主要基板模組400a間較佳之黏合性。Referring to FIG. 3C, the first relay substrate 400b is stacked and bonded to the substrate 401 of the main substrate module 400a with the fourth surface 408 thereof, and the first via conductive material 406 is opposite to the substrate 401. A pad 420c is bonded. And an adhesive layer 419 is applied between the patterned circuit layer 405 of the first relay substrate 450 and the first crystal back 404 of the first wafer 402 to combine the main substrate module 400a with the first relay substrate 450. together. Passing the second wafer 407 through the first medium through the first via conductive material 406 The patterned circuit layer 405 on the substrate 400b is electrically connected to the main substrate module 400a. In another preferred embodiment, a first solder pad 420a can be disposed on the first pad 420c to provide better adhesion between the first relay substrate module 400b and the main substrate module 400a.

請參照第3D圖，在堆疊接合上，係使用與前述相同的製程進一步將第二中繼基板模組400c以相同之方式堆疊至第一中繼基板模組400b之第一中繼基板450上，藉以製造一具有三晶片堆疊的封裝結構。值得一提的是，該第二中繼基板460與第一中繼基板450具有相同的結構，且該第三晶片430電性接合於第二中繼基板460之方式亦與前述實施相同。Referring to FIG. 3D, on the stack bonding, the second relay substrate module 400c is further stacked on the first relay substrate 450 of the first relay substrate module 400b in the same manner as the foregoing process. In order to manufacture a package structure having a three-wafer stack. It should be noted that the second relay substrate 460 has the same structure as the first relay substrate 450, and the third wafer 430 is electrically bonded to the second relay substrate 460 in the same manner as the foregoing embodiment.

參照第3E圖，於堆疊完成後，再利用一封膠樹脂421予以封裝主要基板模組400a、第一中繼基板模組400b以及第二中繼基板模組400c。接著，將複數個外部端子，例如複數個銲球411，形成在基板401的第二表面417上，以將基板401電性連接至至少一個外部電子裝置(未繪示)。在一實施例中，可在形成外部端子前，例如複數個銲球411，在基板401底部形成一銲罩層412並暴露出複數個開口以提供複數個銲球411電性連接至基板401。Referring to FIG. 3E, after the stacking is completed, the main substrate module 400a, the first relay substrate module 400b, and the second relay substrate module 400c are packaged by a single resin 421. Next, a plurality of external terminals, for example, a plurality of solder balls 411, are formed on the second surface 417 of the substrate 401 to electrically connect the substrate 401 to at least one external electronic device (not shown). In an embodiment, before the external terminals are formed, for example, a plurality of solder balls 411, a solder mask layer 412 is formed on the bottom of the substrate 401 and a plurality of openings are exposed to provide a plurality of solder balls 411 electrically connected to the substrate 401.

值得注意的是，這裡的晶片堆疊封裝結構利用晶片覆晶及介層導通材(via)電性連接方式取代傳統打線接合以電性連接晶片至基板，藉此縮短第一晶片與第二晶片之間的距離，也就是說可以大幅度的降低晶片堆疊封裝結構的厚度。本發明之實施例具有增加散熱、改善基板與晶片的電性連接，以及降低晶片堆疊封裝結構整體體積的優點。It should be noted that the wafer stack package structure uses wafer flip-chip and via conductive connection to replace the conventional wire bonding to electrically connect the wafer to the substrate, thereby shortening the first wafer and the second wafer. The distance between them means that the thickness of the wafer stack package structure can be greatly reduced. Embodiments of the present invention have the advantages of increased heat dissipation, improved electrical connection of the substrate to the wafer, and reduced overall bulk of the wafer stack package structure.

雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

400‧‧‧晶片堆疊封裝結構400‧‧‧ wafer stacking structure

400a‧‧‧主要基板400a‧‧‧ main substrate

400b‧‧‧第一中繼基板模組400b‧‧‧First Relay Substrate Module

400c‧‧‧第二中繼基板模組400c‧‧‧Second relay substrate module

401‧‧‧基板401‧‧‧Substrate

402‧‧‧第一晶片402‧‧‧First chip

403‧‧‧第一主動面403‧‧‧First active surface

404‧‧‧第一晶背404‧‧‧The first crystal back

405‧‧‧圖案化線路層405‧‧‧ patterned circuit layer

406‧‧‧第一介層導通材406‧‧‧First vias

407‧‧‧第二晶片407‧‧‧second chip

408‧‧‧第二主動面408‧‧‧second active surface

409a‧‧‧第一凸塊409a‧‧‧first bump

409b‧‧‧第二凸塊409b‧‧‧second bump

411‧‧‧銲球413核心層411‧‧‧ solder ball 413 core layer

412‧‧‧銲罩層412‧‧‧welding layer

416‧‧‧第一表面416‧‧‧ first surface

414‧‧‧充填膠414‧‧‧ Filling glue

416a‧‧‧第三表面416a‧‧‧ third surface

417‧‧‧第二表面417‧‧‧ second surface

419‧‧‧黏著層419‧‧‧Adhesive layer

417a‧‧‧第四表面417a‧‧‧Fourth surface

420c‧‧‧第一銲墊420c‧‧‧First pad

420a‧‧‧第一銲錫420a‧‧‧first solder

422‧‧‧銲罩層422‧‧‧welding layer

421‧‧‧封膠樹脂421‧‧‧ Sealing resin

425‧‧‧第二開孔425‧‧‧Second opening

424a‧‧‧第二銲墊424a‧‧‧second solder pad

430‧‧‧第三晶片430‧‧‧ Third chip

426‧‧‧第一開孔426‧‧‧First opening

437‧‧‧第一容置空間437‧‧‧First accommodation space

431‧‧‧第二晶背431‧‧‧Second crystal back

439‧‧‧第三凸塊439‧‧‧ Third bump

438‧‧‧圖案化線路層438‧‧‧ patterned circuit layer

441‧‧‧核心層441‧‧‧ core layer

440‧‧‧第二容置空間440‧‧‧Second accommodating space

450‧‧‧第一中繼基板450‧‧‧First relay substrate

442‧‧‧銲罩層442‧‧‧welding layer

452‧‧‧晶片接合區452‧‧‧ wafer junction area

451‧‧‧晶片接合區451‧‧‧ wafer bonding area

500‧‧‧晶片堆疊封裝結構500‧‧‧ wafer stacking structure

460‧‧‧第二中繼基板460‧‧‧second relay substrate

700‧‧‧晶片堆疊封裝結構700‧‧‧ Wafer Stacking Structure

510‧‧‧基板510‧‧‧Substrate

520‧‧‧第一晶片520‧‧‧First chip

530‧‧‧第二晶片530‧‧‧second chip

540‧‧‧打線540‧‧‧Line

550‧‧‧打線550‧‧‧Line

800‧‧‧晶片堆疊封裝結構800‧‧‧ Wafer Stacking Structure

610‧‧‧基板610‧‧‧Substrate

620‧‧‧第一晶片620‧‧‧First chip

630‧‧‧第二晶片630‧‧‧second chip

640‧‧‧打線640‧‧‧Line

650‧‧‧打線650‧‧‧Line

660‧‧‧虛擬晶片660‧‧‧Virtual Wafer

670‧‧‧銲墊670‧‧‧ solder pads

680‧‧‧銲墊680‧‧‧ solder pads

為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1圖係根據本發明的第一實施例所繪示之晶片堆疊封裝結構400的剖面示意圖。The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. The description of the drawings is as follows: FIG. 1 is a wafer stacking package structure according to a first embodiment of the present invention. A schematic view of the profile of 400.

第2圖係根據本發明的第二實施例所繪示之晶片堆疊封裝結構500的剖面示意圖。2 is a cross-sectional view of a wafer stack package structure 500 in accordance with a second embodiment of the present invention.

第3A-3E圖係根據本發明第二實施例之晶片堆疊封裝結構500的製造流程圖。3A-3E is a manufacturing flow diagram of a wafer stack package structure 500 in accordance with a second embodiment of the present invention.

第4圖係根據一習知的晶片堆疊封裝結構700所繪示的結構剖面圖。4 is a cross-sectional view of the structure depicted in a conventional wafer stack package structure 700.

第5圖係根據另一種晶片堆疊封裝結構800所繪示的結構剖面圖。Figure 5 is a cross-sectional view of the structure depicted in accordance with another wafer stack package structure 800.

400．．．晶片堆疊封裝結構400. . . Wafer stack package structure

400a．．．主要基板模組400a. . . Main substrate module

400b．．．第一中繼基板模組400b. . . First relay substrate module

402．．．第一晶片402. . . First wafer

401．．．基板401. . . Substrate

404．．．第一晶背404. . . First crystal back

403．．．第一主動面403. . . First active surface

406．．．第一介層導通材406. . . First interlayer conductive material

405．．．圖案化線路層405. . . Patterned circuit layer

408．．．第二主動面408. . . Second active surface

407．．．第二晶片407. . . Second chip

409b．．．第二凸塊409b. . . Second bump

409a．．．第一凸塊409a. . . First bump

411．．．銲球411. . . Solder ball

412．．．銲罩層412. . . Welding mask

413．．．第一核心層413. . . First core layer

414．．．充填膠414. . . Filling glue

416．．．第一表面416. . . First surface

417．．．第二表面417. . . Second surface

416a．．．第三表面416a. . . Third surface

417a．．．第四表面417a. . . Fourth surface

419．．．黏著層419. . . Adhesive layer

420a．．．第一銲錫420a. . . First solder

420c．．．第一銲墊420c. . . First pad

421．．．封膠樹脂421. . . Sealing resin

422．．．銲罩層422. . . Welding mask

424a．．．第二銲墊424a. . . Second pad

425．．．第二開孔425. . . Second opening

426．．．第一開孔426. . . First opening

431．．．第二晶背431. . . Second crystal back

437．．．第一容置空間437. . . First accommodation space

450．．．第一中繼基板450. . . First relay substrate

451．．．晶片接合區451. . . Wafer bonding area

452．．．晶片接合區452. . . Wafer bonding area

Claims (10)

一種晶片堆疊封裝結構，包括：一主要基板模組，其包含：一基板，該基板具有一第一表面與相對的第二表面，該第一表面上設置有一第一晶片接合區以及複數個第一銲墊；以及一第一晶片，具有一第一主動面與一第一晶背，該第一主動面上係具有複數個第一凸塊，並以該些第一凸塊覆晶接合於且電性連接於該基板之該第一晶片接合區；一第一中繼基板模組，其包含：一第一中繼基板，其包含：一核心層，係具有複數個第一開孔(through hole)與一第一容置空間，該第一容置空間係容置該第一晶片，而複數個第一開孔內係設置有至少一第一介層導通材以與該基板之該些第一銲墊接合，以及；一圖案化線路層，形成於該核心層上且與該至少一介層導通材電性連接，其中該第一容置空間暴露部分之該圖案化線路層；以及一銲罩層(solder mask)，覆蓋設置於該圖案化線路層上，且該銲罩層具有一開口以暴露另一部分之該圖案化線路層形成一第二晶片接合區；以及一第二晶片，具有一第二主動面與一第二晶背， 該第二主動面上設置有複數個第二凸塊，並以該些第二凸塊覆晶接合於該第一中繼基板上該銲罩層之該開口中之該第二晶片接合區中；以及一封膠樹脂(molding compound)，封裝該主要基板模組以及該第一中繼基板模組。 A wafer stack package structure includes: a main substrate module comprising: a substrate having a first surface and an opposite second surface, the first surface being provided with a first wafer bonding region and a plurality of a first pad having a first active surface and a first crystal back, the first active surface having a plurality of first bumps, and the first bumps are flip-chip bonded to the first bumps And electrically connected to the first die bond region of the substrate; a first relay substrate module comprising: a first relay substrate comprising: a core layer having a plurality of first openings ( And a first accommodating space, the first accommodating space is configured to receive the first wafer, and the plurality of first openings are provided with at least one first via material to be associated with the substrate a first pad bonding, and a patterned circuit layer formed on the core layer and electrically connected to the at least one via conductive material, wherein the first receiving space exposes a portion of the patterned circuit layer; a solder mask, the cover is disposed in the figure A circuit layer, and the solder mask layer having an opening to expose the patterned wiring layer is formed a further part of the second wafer bonding region; and a second wafer having a second active surface and a second crystal back, The second active surface is provided with a plurality of second bumps, and the second bumps are flip-chip bonded to the second wafer bonding region in the opening of the solder mask layer on the first relay substrate. And a molding compound that encapsulates the main substrate module and the first relay substrate module. 如請求項1所述之堆疊封裝結構，其中該第一中繼基板之該銲罩層上形有複數個第二開孔，以暴露又一部份之該圖案化線路層以形成一第二銲墊。 The stacked package structure of claim 1, wherein the solder mask layer of the first relay substrate has a plurality of second openings formed thereon to expose a further portion of the patterned circuit layer to form a second Solder pad. 如請求項2所述之堆疊封裝結構，更包含：一第二中繼基板模組，其具有與該第一中繼基板模組相同之構件，該第二中繼基板模組係垂向堆疊於該第一中繼基板模組之該第一中繼基板上，且該第二中繼基板模組之該些第二銲墊電性連接至該第一中繼基板。 The stacked package structure of claim 2, further comprising: a second relay substrate module having the same component as the first relay substrate module, the second relay substrate module being vertically stacked The second relay pads of the second relay substrate module are electrically connected to the first relay substrate. 如請求項1所述之堆疊封裝結構，其中該第一中繼基板之該第一介層導通材與該基板之該些第一銲墊之間係設有至少一第一銲鍚。 The stacked package structure of claim 1, wherein at least one first solder fillet is disposed between the first via conductive material of the first relay substrate and the first solder pads of the substrate. 如請求項1所述之堆疊封裝結構，更包含：複數個銲球(solder bump)，設置於該基板之該第二表面。 The stacked package structure of claim 1, further comprising: a plurality of solder bumps disposed on the second surface of the substrate. 如請求項1所述之堆疊封裝結構，更包含：一黏著層(adhesive)，設置於該至少一圖案化線路層與該第一晶片的該第一晶背之間。 The stacked package structure of claim 1, further comprising: an adhesive layer disposed between the at least one patterned circuit layer and the first crystal back of the first wafer. 如請求項1所述之堆疊封裝結構，更包含：一充填膠(underfill material)，包覆該些第一與第二凸塊。 The stacked package structure of claim 1, further comprising: an underfill material covering the first and second bumps. 一種晶片堆疊封裝結構的製造方法，該方法包括：提供一主要基板模組，該主要基板模組包含：一基板，具有一第一表面與相對的第二表面，該基板之第一表面上具有一第一晶片接合區及至少一第一銲墊；以及一第一晶片，具有一第一主動面與一第一晶背，其中該第一主動面上設置有複數個第一凸塊，並覆晶且電性連接於該基板的該第一晶片接合區上；提供一第一中繼基板模組疊設於該主要基板模組之該基板上，該第一中繼基板模組包含：一第一中繼基板，其包含：一核心層，具有複數個第一開孔以及一第一容置空間容置該第一晶片；而複數個第一開孔內係設置有至少一第一介層導通材(via plug)以與該主要基板模組之該些第一銲墊接合；一圖案化線路層，形成於該核心層上且與該 至少一第一介層導通材電性連接，其中該第一容置空間暴露部分之該圖案化線路層；以及一銲罩層(solder mask)，覆蓋設置於該圖案化線路層上，且該銲罩層具有至少一開口以暴露另一部分之該圖案化線路層形成一第二晶片接合區；以及一第二晶片，具有一第二主動面與一第二晶背，該第二主動面上設置有複數個第二凸塊，並以該第二凸塊覆晶接合於該第一中繼基板上該銲罩層之該開口中並與暴露出之該圖案化線路層之該另一部分電性連接；以及使用一封膠樹脂以封裝該主要基板模組與該第一中繼基板模組。 A method of manufacturing a wafer stack package structure, the method comprising: providing a main substrate module, the main substrate module comprising: a substrate having a first surface and an opposite second surface, the first surface of the substrate having a first wafer bonding region and at least one first bonding pad; and a first wafer having a first active surface and a first crystal back, wherein the first active surface is provided with a plurality of first bumps, and The first relay substrate module is stacked on the substrate of the main substrate module, and the first relay substrate module comprises: a first relay substrate, comprising: a core layer having a plurality of first openings and a first accommodating space for accommodating the first wafer; and the plurality of first openings are provided with at least one first a via plug is bonded to the first pads of the main substrate module; a patterned circuit layer is formed on the core layer and The at least one first via conductive material is electrically connected, wherein the first accommodating space exposes the portion of the patterned circuit layer; and a solder mask is disposed on the patterned circuit layer, and the The solder mask layer has at least one opening to expose another portion of the patterned wiring layer to form a second wafer bonding region; and a second wafer having a second active surface and a second crystal back surface, the second active surface a plurality of second bumps are disposed, and the second bump is flip-chip bonded to the opening of the solder mask layer on the first relay substrate and electrically connected to the exposed portion of the patterned circuit layer Sexual connection; and using a glue resin to encapsulate the main substrate module and the first relay substrate module. 如請求項8所述之方法，其中該提供主要基板模組之步驟更包含：提供複數個銲球設置於該基板之該第二表面。 The method of claim 8, wherein the step of providing the main substrate module further comprises: providing a plurality of solder balls disposed on the second surface of the substrate. 如請求項8所述之方法，在使用該封膠樹脂封裝該主要基板模組與該第一中繼基板模組的步驟之前，更包含：提供一第二中繼基板模組，其中該第二中繼基板模組係具有與該第一中繼基板模組相同構件，該第二中繼基板係垂向堆疊且彼此電性連接於該第一中繼基板模組之該第一中繼基板上。 The method of claim 8, before the step of encapsulating the main substrate module and the first relay substrate module by using the sealing resin, further comprising: providing a second relay substrate module, wherein the The second relay substrate module has the same components as the first relay substrate module, and the second relay substrate is vertically stacked and electrically connected to the first relay of the first relay substrate module. On the substrate.
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