WO2022021800A1 - 半导体封装方法及半导体封装结构 - Google Patents

半导体封装方法及半导体封装结构 Download PDF

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Publication number
WO2022021800A1
WO2022021800A1 PCT/CN2020/141972 CN2020141972W WO2022021800A1 WO 2022021800 A1 WO2022021800 A1 WO 2022021800A1 CN 2020141972 W CN2020141972 W CN 2020141972W WO 2022021800 A1 WO2022021800 A1 WO 2022021800A1
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WIPO (PCT)
Prior art keywords
lead frame
chip
packaged
chips
encapsulation
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PCT/CN2020/141972
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English (en)
French (fr)
Inventor
霍炎
涂旭峰
Original Assignee
矽磐微电子(重庆)有限公司
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Publication of WO2022021800A1 publication Critical patent/WO2022021800A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
  • a lead frame 30' and a wiring layer 40' are often used to implement a double-sided interconnect package of two chips 10'.
  • the backsides of the two chips 10' are attached to the upper surface of the lead frame 30' through the conductive adhesive 20' to realize the backside electrical connection, and the wiring layer 40' realizes the connection with the front side of the chip 10' through the copper pillars 50'. Since the copper pillars need to be implanted by ultrasonic bonding, the cost of this process is extremely high, but the efficiency is extremely low.
  • arranging the lead frame 30' on the backside of the chip 10' results in a thicker product, which will be limited when applied to wearable equipment or other scenarios that have higher requirements on product thickness.
  • the present application provides a semiconductor packaging method and a semiconductor packaging structure.
  • One aspect of the present application provides a semiconductor packaging method, which includes: mounting a lead frame and a plurality of chips to be packaged on a carrier board, the front surfaces of the chips to be packaged face the carrier board, and the lead frame is provided with a hollow area , the hollow area runs through the lead frame along the thickness direction, and a plurality of the chips to be packaged are located in the hollow area; by covering the chips to be packaged, the lead frame and the carrier board with an encapsulation layer The exposed part is filled in the hollow area of the lead frame to form an encapsulation structure.
  • the encapsulation structure includes a first surface and a second surface opposite to the first surface.
  • the front surface of the packaged chip and the first surface of the lead frame are exposed on the first surface of the encapsulation structure; a first redistribution structure is formed on the first surface of the encapsulation structure, and the first redistribution The structure is electrically connected to the front surface of the chip to be packaged and the first surface of the lead frame; and a second redistribution structure is formed on the second surface of the encapsulation structure, and the second redistribution structure is connected to The back surface of the chip to be packaged and the second surface of the lead frame disposed relative to the first surface are both electrically connected.
  • a second aspect of the present application provides a semiconductor package structure including an encapsulation structure having opposing first and second surfaces, the encapsulation structure including a lead frame assembly, a plurality of chips, and a an encapsulation layer that encapsulates the lead frame assembly and the plurality of chips, the lead frame assembly is disposed on the periphery of each of the chips to define the respective accommodating spaces of the plurality of chips, and the accommodating space is The space runs through the lead frame assembly in the thickness direction, the encapsulation layer is filled in the accommodating space defined by the lead frame assembly, and the front surface of the chip and the first surface of the lead frame assembly are exposed to the package the first surface of the encapsulation structure; the first redistribution structure, the first redistribution structure is formed on the first surface of the encapsulation structure, the first redistribution structure and the front surface of the chip and the The first surfaces of the lead frame components are all electrically connected; the second redistribution structure is formed on the second surface of the encapsulation structure, and
  • the above-mentioned semiconductor packaging method and semiconductor packaging structure provided by the embodiments of the present application realize the double-sided interconnection packaging of the chip through the lead frame and the double-sided re-wiring interconnection process, which improves the thinning of the product and enhances the electrical reliability of the product. sex.
  • the lead frame is provided with a hollow area that penetrates the lead frame in the thickness direction, and a plurality of chips to be packaged are located in the hollow area, that is, the chips to be packaged are embedded in the lead frame, thereby greatly reducing the size of the lead frame.
  • the thickness of the product is reduced, and the product is effectively thinned.
  • the technical solution in this application directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillars, thereby increasing the interconnection area, realizing the multi-layer wiring process, increasing the degree of freedom of product design, and enhancing the product At the same time, it saves the production cost and improves the overall production efficiency.
  • the lead frame in the semiconductor packaging method of the present application does not need a lead frame portion located under the chip, it can be applied to chips with a larger area, and can discharge more chips, and has excellent applicability.
  • FIG. 1 is a cross-sectional view of a semiconductor package structure in the prior art.
  • FIG. 2 is a flowchart of a semiconductor packaging method according to Embodiment 1 of the present application.
  • FIG. 3 is a schematic diagram of the front structure of the lead frame according to the first embodiment of the present application.
  • FIG. 4 is a schematic view of the front structure of the lead frame according to Embodiment 1 of the present application.
  • 5A-5N are process flow diagrams of the semiconductor packaging method proposed according to Embodiment 1 of the present application.
  • FIG. 6 is a schematic structural diagram of a semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIG. 7A is a schematic diagram of front connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIG. 7B is a schematic diagram of the backside connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIG. 8 is a schematic structural diagram of another embodiment of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIGS. 9A-9G are process flow diagrams of a semiconductor packaging method in Embodiment 2 according to the present application.
  • FIG. 10 is a schematic structural diagram of a semiconductor package structure proposed according to Embodiment 2 of the present application.
  • This embodiment provides a semiconductor packaging method and a semiconductor packaging structure.
  • FIG. 2 is a flowchart of the semiconductor packaging method proposed in this embodiment. As shown in FIG. 2, the semiconductor packaging method includes the following steps:
  • Step 100 Mount the lead frame and a plurality of chips to be packaged on the carrier board.
  • the front side of the chip to be packaged faces the carrier board;
  • the lead frame is provided with a hollow area, and the hollow area penetrates the lead frame along the thickness direction; a plurality of the chips to be packaged are located in the hollow area .
  • Step 200 forming an encapsulation structure by covering an encapsulation layer on the to-be-packaged chip, the lead frame and the exposed part of the carrier, and filling the hollow area.
  • the encapsulating structural member includes a first surface and a second surface disposed opposite to each other. The front surface of the chip to be packaged and the first surface of the lead frame are exposed on the first surface of the packaging structure.
  • Step 300 forming a first redistribution structure on the first surface of the encapsulation structure, and the first redistribution structure is electrically connected to the front surface of the to-be-packaged chip and the first surface of the lead frame; and forming a second redistribution structure on the second surface of the encapsulation structure, the second redistribution structure and the back surface of the chip to be packaged and the second surface of the lead frame disposed opposite to the first surface All electrical connections.
  • the semiconductor packaging method of this embodiment improves the thinning of the product and can enhance the electrical reliability of the product.
  • the lead frame is provided with a hollow area that penetrates the lead frame in the thickness direction, and a plurality of chips to be packaged are located in the hollow area, that is, the chips to be packaged are embedded in the lead frame, which greatly reduces the thickness of the lead frame.
  • the thickness of the product effectively realizes the thinning of the product.
  • the technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillars, which increases the interconnection area, realizes the multi-layer wiring process, increases the degree of freedom of product design, and enhances the product At the same time, it saves the production cost and improves the overall production efficiency.
  • the lead frame in the semiconductor packaging method of this embodiment does not need the lead frame portion located under the chip, it can be applied to a chip with a larger area, and more chips can be discharged, which has excellent applicability.
  • the specific structure of the lead frame 20 in this embodiment may be shown in FIG. 3 and FIG. 4 .
  • Each final semiconductor package structure after packaging and dicing corresponds to one lead frame 20 .
  • the lead frame 2 is composed of a plurality of interconnected lead frames 20 arranged in an array.
  • the lead frame 2 can also consist of only one lead frame 20 .
  • Each lead frame 20 includes a frame body 22 .
  • the frame body 22 is provided with a hollow area 21 which penetrates the frame body 22 along the thickness direction T. As shown in FIG.
  • the number of hollow regions 21 in one lead frame 20 may be one or more.
  • the lead frame 20 also includes a connection portion 24 .
  • Two ends of the connecting portion 24 are respectively connected to two opposite sides of the frame body 22 , and the connecting portion 24 separates the inner space of the frame body 22 into a plurality of hollow areas. That is, adjacent hollow regions 21 are separated by connecting portions 24 , and adjacent hollow regions 21 in the same lead frame 20 are separated by connecting portions 24 .
  • each lead frame 20 is separated into two hollow regions by the connecting portion 24 , that is, the number of hollow regions 21 provided in each lead frame 20 is Two, two hollow regions 21 are separated by connecting parts 24 .
  • the connecting portion 24 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence.
  • the first portion 241 and the middle portion 242 form a first angle ⁇
  • the second portion 243 and the middle portion 242 form a second angle ⁇
  • the first portion 241 and the second portion 243 are on opposite sides of the frame body 22 respectively. connect.
  • the first included angle ⁇ and the second included angle ⁇ are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are approximately parallel to each other, so that the structure of the connecting portion 24 can be more stable.
  • one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 can be more compact.
  • the lead frame 20 further includes a plurality of mutually isolated edge portions 23 .
  • One end of the edge portion 23 is connected to the frame body 22 and the other end extends toward the hollow area 21 ; each hollow area 21 is provided with a plurality of mutually isolated edge portions 23 .
  • the edge portion 23 includes a main body 231 and a support portion 232 , and the support portion 232 is connected between the frame body 22 and the main body 231 .
  • the number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals.
  • the main body 231 may be square, bar-shaped or L-shaped.
  • the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
  • the chips to be packaged respectively located in the different hollow regions are electrically connected through the connection portion.
  • the front side of one of the chips to be packaged and the back side of the other chip to be packaged can be electrically connected; or, the front side of one of the chips to be packaged and the front side of the other chip to be packaged can be electrically connected;
  • the backside of the chip to be packaged is in electrical communication with the backside of another chip to be packaged.
  • each lead frame 20 includes a first surface 20a and a second surface 20b disposed opposite to each other.
  • the first surface 20a may be provided with several first electrical connection points
  • the second surface 20b may be provided with several second electrical connection points.
  • the semiconductor packaging method of this embodiment includes:
  • step 100 the chip 11 to be packaged and the lead frame 20 are mounted on the carrier board 3 through an adhesive layer.
  • the backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 .
  • the chip 11 to be packaged includes a front side 11a with solder pads, and a back side 11b opposite to the front side 11a.
  • the back side 11b is provided with a metal layer 111, so that the front side 11a and the back side 11b of the chip 11 to be packaged are electrically led out.
  • the lead frame 20 is provided with a hollow area 21 , and the hollow area 21 penetrates the lead frame 20 along the thickness direction T. As shown in FIG. A plurality of chips 11 to be packaged are located in the hollow area 21 .
  • the thickness of the lead frame 20 may be greater than the thickness of the chip 11 to be packaged, so as to protect the chip 11 to be packaged.
  • the adhesive layer is used to bond the chip 11 to be packaged and the lead frame 20 to the carrier board 3 .
  • the adhesive layer can be made of an easily peelable material, so that the carrier board 3 can be peeled off from the chip to be packaged 11 and the lead frame 20 in a subsequent process.
  • the adhesive layer may be a thermally detachable material that can be debonded by heating.
  • the adhesive layer may adopt a two-layer structure, including a thermal separation material layer and a die attach layer.
  • the thermal separation material layer is pasted on the carrier plate 3 , and loses its viscosity during heating, and can be peeled off from the carrier plate 3 .
  • the chip attach layer adopts an adhesive material layer, which can be used to stick the chip 11 to be packaged. After the packaged chip 11 is peeled off from the carrier board 3 , the chip attach layer thereon may be removed by chemical cleaning.
  • an adhesive layer may be formed on the carrier board 3 by means of lamination, printing, or the like.
  • the number of chips 11 to be packaged is multiple.
  • the number of chips 11 to be packaged can be adjusted according to design requirements, which is not limited herein.
  • the lead frame 20 is integrally formed, that is, the frame body of the lead frame, the connection portion 24 , and the edge portion 23 are integrally formed, the respective parts of the frame body, the connection portion 24 , and the edge portion 23 of the lead frame are formed in one piece. It is fixed on the carrier board at one time, which greatly saves the production cost and improves the overall production efficiency.
  • the encapsulation layer 14 covers the entire carrier 3 (ie, covers the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3), and fills the In the hollow area 21 of the lead frame 20 , the to-be-packaged chip 11 and the lead frame 20 are encapsulated to form the encapsulation structure 10 .
  • the encapsulation structure 10 is a flat structure, and after the carrier board 3 is peeled off, rewiring and packaging can be continued on the flat structure.
  • the encapsulation structure 10 includes a first surface 10a and a second surface 10b which are disposed opposite to each other. Wherein, the second surface 10 b of the encapsulation structure 10 is disposed opposite to the carrier plate 3 , is substantially flat, and is substantially parallel to the surface of the carrier plate 3 .
  • the encapsulation layer 14 may be formed by laminating an epoxy resin film or a molding film, or by performing injection molding, compression molding, or compression molding on the epoxy resin compound. molding) or transfer molding (Transfer molding).
  • the packaging method further includes mounting the first support plate 41 on the second surface 10 b of the packaging structural member 10 .
  • the first support plate 41 is mounted on at least a partial area of the second surface 10 b of the encapsulation structure 10 . As shown in FIG. 5C , in one embodiment, the first support plate 41 covers the entire area of the second surface 10 b of the encapsulation structure 10 .
  • the material strength of the first support plate 41 is greater than the material strength of the encapsulation layer 14, so that the mechanical strength of the encapsulation structure during the encapsulation process can be effectively improved and guaranteed, and the adverse effects caused by the deformation of each structure can be effectively suppressed, thereby improving the product encapsulation quality. Effect.
  • the first support plate 41 may also be formed on the second surface 10b of the encapsulation structure 10 by spraying, printing, coating, or the like.
  • the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 .
  • the first surface 10 a of the encapsulation structure 10 exposes the front surface of the chip 11 to be packaged and the first surface 20 a of the lead frame 20 .
  • the adhesive layer between the carrier board 3 and the chip to be packaged and the lead frame 20 is a thermal separation film
  • the adhesive layer can be heated to reduce the viscosity after being heated, and then the carrier board 3 can be peeled off.
  • the carrier plate 3 can also be directly mechanically peeled off.
  • the carrier board 3 After the carrier board 3 is peeled off, the first surface 10 a of the encapsulation structure 10 , the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 are exposed. After peeling off the carrier board 3 , an encapsulation structure 10 including the chip to be packaged 11 , the lead frame 20 , and the encapsulation layer 14 encapsulating the chip to be packaged 11 and the lead frame 20 is obtained. On the encapsulation structure 10 , rewiring and the like may be performed according to the actual situation, so that the chip 11 to be encapsulated is electrically connected to the outside world.
  • the step of attaching the first support plate 41 may also be performed after peeling off the carrier plate 3 .
  • a protective layer 30 is formed on the first surface 10 a of the encapsulation structure 10 .
  • the positions corresponding to the pads on the front side of the chip 11 to be packaged and the first electrical connection points on the first side 20 a of the lead frame 20 correspond to A protective layer opening 31 is formed at the position.
  • the lead frame 20 and the chip 11 to be packaged are basically arranged on the same level, when the protective layer 30 is punched to form the protective layer opening 31, the protective layer 30 is a transparent film layer, and the protective layer can be used 30 transparency for positioning. In addition, positioning can be assisted by the lead frame 20 to improve the positional accuracy of the laser drilling.
  • a first redistribution structure 50 is formed on the first surface 10a of the encapsulation structure 10, and the first redistribution structure 50 is electrically connected to the pads on the front side of the chip 11 to be packaged, And it is electrically connected to the first electrical connection point of the first surface 20 a of the lead frame 20 .
  • the first redistribution structure 50 includes at least one first redistribution layer 51 .
  • the first redistribution structure 50 includes a first redistribution layer 51 .
  • the first redistribution structure 50 may also include multiple layers of the first redistribution layer 51 according to design requirements, that is, repeated redistribution is performed on the front surface of the chip to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the protective layer opening 31 has been formed on the protective layer 30 , when the first redistribution layer 51 is formed, at least the protective layer opening 31 can be directly seen, so when the first redistribution structure 50 is formed, it can be more accurately aligned. bit.
  • a conductive medium may be filled in the protective layer openings 31 of the protective layer 30 at the same time to form the conductive pillars 52 . That is, the first redistribution layer 51 and the conductive pillar 52 are formed in the same conductive layer forming process.
  • the conductive pillars 52 form substantially vertical connection structures in the protective layer openings 31 .
  • the bonding pads on the front surface 11 a of the chip 11 to be packaged are electrically led out through the conductive pillars 52 and the first redistribution layer 51 .
  • a dielectric layer 60 is formed.
  • the dielectric layer 60 is formed on the first redistribution structure 50 and the exposed portion of the first surface 10 a of the encapsulation structure 10 .
  • the dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing.
  • the dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
  • the packaging method further includes peeling off the first support plate 41 .
  • the first support plate 41 can be peeled off mechanically directly, or can be peeled off by other methods. This application does not limit this, and can be set according to a specific application environment.
  • the packaging method further includes attaching a second support plate 42 on a side of the dielectric layer 60 away from the first surface 10 a of the encapsulation structure 10 .
  • the second support plate 42 is mounted on at least a partial area of the side of the dielectric layer 60 away from the encapsulation structure 10 . As shown in FIG. 5J , in one embodiment, the second support plate 42 is mounted on the dielectric layer 60 , and the second support plate 42 is mounted on the entire side of the dielectric layer 60 away from the encapsulation structure 10 . area.
  • the material strength of the second support plate 42 can be greater than the material strength of the dielectric layer 60, so that the mechanical strength of the packaging structure during the packaging process can be effectively improved and guaranteed, the adverse effects caused by the deformation of each structure can be effectively suppressed, and the effect of product packaging can be improved.
  • the second support plate 42 may also be formed on the dielectric layer 60 by spraying, printing, coating, or the like.
  • the step of attaching the second support plate 42 may also be performed before peeling off the first support plate 41 .
  • the packaging method further includes grinding the second surface 10b of the encapsulation structure 10 , so as to reduce the thickness of the encapsulating structural member 10 . Preferably, it is thinned to expose the second surface 20b of the lead frame 20 .
  • the thickness of the lead frame 20 is greater than the thickness of the chip 11 to be encapsulated, a certain thickness of encapsulation layer 14 will remain on the back of the chip 11 to be encapsulated to protect the chip 11 to be encapsulated effect.
  • the received chip to be packaged may be an ultra-thin chip.
  • the chip In order to ensure that the chip is not damaged, the chip cannot be further processed by grinding and other processes. thin.
  • the chip 11 is an ultra-thin chip, the lead frame 20 cannot be ground to a thickness consistent with the chip 11, because if the lead frame 20 is ground too thin, there is a risk of breakage. Therefore, it is necessary to keep a certain thickness of the encapsulation layer 14 on the backside of the chip and realize the connection between the backside of the chip 11 and the second redistribution structure 70 by drilling.
  • the present application can be applied to the overall package of ultra-thin multi-chips.
  • ultra-thin multi-chip refers to chips with a thickness of less than 200 microns.
  • a plurality of openings 15 are formed on the second surface 10 b of the encapsulation structure 10 , and the openings 15 are disposed corresponding to the chips 11 to be packaged to expose the backside of the chips 11 to be packaged. That is, holes are formed on the encapsulation layer 14 on the backside of the chip 11 to be packaged to form the openings 15 .
  • a second redistribution structure 70 is formed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 is electrically connected to both the metal layer 111 on the backside of the chip 11 to be packaged and the second electrical connection point of the second side 20b of the lead frame 20 .
  • the thickness of the redistribution structure (including the second redistribution structure 70) can be much smaller than the thickness of the lead frame 30' in the prior art (as shown in FIG. 1).
  • the thickness of the rewiring structure is 15um-45um, and the thickness of the lead frame 30' is generally 150um-450um. Therefore, the rewiring structure not only realizes the function of wiring, but also improves the thinning of the product.
  • the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection of the front surface and the back surface of the chip 11 to be packaged is realized. That is, the first redistribution structure 50 located on the first surface 10a of the encapsulation structure 10 and the second redistribution structure 70 located on the second surface 10b of the encapsulation structure 10 are connected through the lead frame 20 .
  • the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction.
  • the layout of the rewiring structure is more free and flexible.
  • the electrical lead-out of the front side 11a of the chip 11 to be packaged is realized by the electrical connection of the pads on the front side 11a of the chip 11 to be packaged, the first rewiring structure 50 , the lead frame 20 and the second rewiring structure 70 in sequence.
  • the electrical lead-out of the backside 11b of the chip 11 to be packaged is achieved by being directly electrically connected to the second rewiring structure 70;
  • the interconnection of different chips to be packaged 11 includes the interconnection of the same side or the interconnection of different sides ( For example, the interconnection between the front side of one of the chips 11 to be packaged and the back side of the other chip 11 to be packaged) can be achieved through the electrical connection of the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 .
  • the second redistribution structure may include at least one second redistribution layer and a pin layer.
  • the pin layer is located on the side of the second redistribution layer away from the encapsulation structure.
  • the second redistribution structure includes only one pin layer according to design requirements.
  • the number of layers of the second rewiring layer may be one layer, or may be adjusted to multiple layers according to design requirements, that is, repeated rewiring is performed on the backside of the chip to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the semiconductor package structure 1 is electrically connected to the outside through the pin layer, and is installed in the next step through the pin layer.
  • the material of the pin layer can be tin, nickel-gold alloy or other metals.
  • the second redistribution structure 70 includes a lead layer 71 .
  • a conductive medium may be filled in the openings 15 of the encapsulation layer 14 at the same time to form the conductive bumps 72 . That is, the pin layers 71 and the conductive bumps 72 are formed in the same conductive layer forming process.
  • the conductive bumps 72 form substantially vertical connection structures in the openings 15 .
  • the bonding pads on the backside 11 b of the chip 11 to be packaged are electrically drawn out through the conductive bumps 72 and the lead layer 71 .
  • the second support plate 42 is peeled off, as shown in FIG. 5N .
  • the second support plate 42 can be peeled off mechanically directly, or can be peeled off by other methods. This application does not limit this, and can be set according to a specific application environment.
  • a step of cutting off the frame body of the lead frame 20 by means of laser or mechanical cutting is also included, and the illustration of this step is omitted.
  • the entire package structure may be cut into multiple semiconductor package structures by laser or mechanical cutting.
  • the structure of the formed semiconductor package structure 1 may be as shown in FIG. 6 .
  • FIG. 6 it is a schematic structural diagram of a semiconductor packaging structure 1 obtained by using the above-mentioned semiconductor packaging method according to the present embodiment.
  • the semiconductor package structure 1 includes an encapsulation structure 10 , a first redistribution structure 50 and a second redistribution structure 70 .
  • the encapsulation structure 10 includes opposing first surfaces 10a and second surfaces 10b, and the encapsulation structure 10 includes a lead frame assembly (mainly corresponding to the connection portion 24 and the edge portion 23 in the lead frame 20 in the aforementioned semiconductor packaging method) , a plurality of chips 11 and an encapsulation layer 14 for encapsulating the lead frame assembly and the plurality of chips 11, the lead frame assembly is arranged on the periphery of each chip 11 to define the respective accommodating spaces of the chips, the accommodating spaces along the thickness The direction T runs through the lead frame assembly, the plurality of chips 11 are located in the accommodating space, and the encapsulation layer 14 is filled in the accommodating space defined by the lead frame assembly. It can be seen that the respective accommodating spaces of the plurality of chips 11 defined by the lead frame assembly may correspond to the hollow regions 21 in the lead frame 20 in the aforementioned semiconductor packaging method.
  • the number of chips 11 is plural.
  • the number of chips 11 can be adjusted according to design requirements, which is not limited here.
  • the number of chips 11 is two.
  • the number of hollow regions 21 of one lead frame 20 may be one or more.
  • each lead frame 20 is provided with two hollow regions 21 in number. But not limited to this, the number of hollow regions 21 can be other numbers according to design requirements.
  • a plurality of chips 11 may be placed in different hollow areas 21 , or a plurality of chips 11 may be placed in the same hollow area 21 .
  • the lead frame 20 also includes a connection portion 24 .
  • the connecting portion 24 divides the inner space of the lead frame 20 into a plurality of hollow areas.
  • the chips 11 respectively located in the different hollow regions are electrically connected through the connecting portions 24 .
  • each lead frame 20 is separated into two hollow regions by the connecting portion 24 . That is, each lead frame 20 is provided with two hollow regions 21 , and the two hollow regions 21 are separated by the connecting portion 24 . The two chips 11 are respectively located in two different hollow regions.
  • the chip 11 includes a front side provided with bonding pads, and a back side opposite to the front side.
  • the back side is provided with a metal layer 111 , so that both the front side and the back side of the chip 11 are electrically led out.
  • the first surface 20a of the lead frame 20 is exposed to the first surface 10a of the encapsulation structure.
  • the first redistribution structure 50 corresponds to the front surface of the chip 11 and is formed on the first surface 10 a of the encapsulation structure 10 .
  • the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 and is connected to the first surface of the lead frame 20 .
  • the first electrical connection point of one side 20a is electrically connected.
  • the first redistribution structure 50 includes at least one first redistribution layer 51 .
  • the first redistribution structure 50 includes a first redistribution layer 51 .
  • the first redistribution structure 50 may also include multiple layers of first redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front side of the chip. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • a protection layer 30 may be provided on the first surface 10 a of the encapsulation structure 10 , and the protection layer 30 is located between the first redistribution structure 50 and the encapsulation structure 10 .
  • a protective layer opening 31 is formed on the protective layer 30 , and a conductive column 52 formed by filling a conductive medium is arranged in the protective layer opening 31 .
  • the first redistribution layer 51 and the conductive pillar 52 may be formed in the same conductive layer forming process.
  • the second redistribution structure 70 corresponds to the back surface of the chip 11 and is formed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 is electrically connected to both the metal layer 111 on the backside of the chip 11 and the second electrical connection point of the second side 20b of the lead frame 20 .
  • the second redistribution structure 70 includes at least one second redistribution layer 71 .
  • the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection of the front surface and the back surface of the chip 11 is realized. That is, the first redistribution structure 50 located on the first surface 10a of the encapsulation structure 10 and the second redistribution structure 70 located on the second surface 10b of the encapsulation structure 10 are connected through the lead frame 20 .
  • the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction; and, because the electrical connection does not need to be finally concentrated on the leads of the lead frame, and then wiring
  • the layout of the structure is more free and flexible.
  • the electrical lead-out on the front side of the chip 11 is realized through the electrical connection of the pads on the front side of the chip 11, the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70 in sequence;
  • the electrical lead-out is realized by directly connecting with the second redistribution structure 70;
  • the interconnection of different chips 11 includes the interconnection on the same plane or the interconnection on different planes (such as the front side of one chip 11 and the other chip 11). 11), which can be achieved by the electrical connection of the first redistribution structure 50, the lead frame 20, and the second redistribution structure 70.
  • the second redistribution structure may include at least one second redistribution layer and a pin layer, and the pin layer is located on a side of the second redistribution layer away from the encapsulation structure.
  • the second redistribution structure includes only one pin layer according to design requirements.
  • the number of layers of the second redistribution layer may be one layer, or may be adjusted to multiple layers according to design requirements, that is, repeated redistribution is performed on the front side of the chip. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the orthographic projection of the pin layer is located within the orthographic projection of the second redistribution layer.
  • the spacing between adjacent pin layers is greater than the spacing between adjacent second redistribution layers corresponding to the adjacent pin layers, so that the final semiconductor package product is formed using tin or other materials. It is not easy to short-circuit during welding, which improves the electrical performance of the product.
  • the semiconductor package structure 1 is electrically connected to the outside through the pin layer, and is installed in the next step through the pin layer.
  • the material of the pin layer can be tin, nickel-gold alloy or other metals.
  • the second redistribution structure 70 includes a pin layer 71 .
  • the thickness of the lead frame 20 is greater than that of the chip 11 .
  • the second surface 20b of the lead frame 20 is exposed to the second surface 10b of the encapsulation structure 10 , that is, the thickness of the encapsulation structure 10 is equal to the thickness of the lead frame 20 , thereby achieving the thinnest semiconductor package structure 1 .
  • the thickness of the lead frame 20 is greater than the thickness of the chip 11 , a certain thickness of the encapsulation layer 14 will remain on the backside of the chip 11 to protect the chip 11 .
  • the received chip to be packaged may be an ultra-thin chip.
  • the chip In order to ensure that the chip is not damaged, the chip cannot be further reduced by grinding and other processes. Thin.
  • the lead frame 20 cannot be ground to a thickness consistent with that of the chip 11 . Because if the lead frame 20 is ground too thin, there is a risk of breakage. Therefore, it is necessary to keep a certain thickness of the encapsulation layer 14 on the backside of the chip and realize the connection between the backside of the chip 11 and the second redistribution structure 70 by drilling.
  • the present application can be applied to the overall package of ultra-thin multi-chips.
  • ultra-thin multi-chip refers to chips with a thickness of less than 200 microns.
  • the second redistribution structure 70 further includes conductive bumps 72 .
  • the conductive bumps 72 are formed by filling the openings 15 with a conductive medium, and the conductive bumps 72 are electrically connected to the backside of the chip 11 .
  • the pin layers 71 and the conductive bumps 72 may be formed in the same conductive layer forming process.
  • the encapsulation structure 10 further includes a dielectric layer 60 formed on the first redistribution structure 50 and the exposed portion of the first surface 10 a of the encapsulation structure 10 .
  • the dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing.
  • the dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
  • PBO Polybenzoxazole
  • the connection portion 24 of the lead frame 20 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence.
  • the first portion 241 and the middle portion 242 form a first angle ⁇
  • the second portion 243 and the middle portion 242 form a second angle ⁇ .
  • the first included angle ⁇ and the second included angle ⁇ are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are approximately parallel to each other, so that the structure of the connecting portion 24 can be more stable.
  • one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 can be more compact.
  • the lead frame 20 further includes a plurality of mutually isolated edge portions 23, one end of the edge portion 23 is exposed on the surface of the encapsulation structure 10, and the other end extends toward the hollow area 21; each hollow area 21 is provided with a plurality of mutually isolated edges Section 23.
  • the edge portion 23 includes a main body 231 and a supporting portion 232 . One end of the supporting portion away from the main body 231 is exposed on the surface of the encapsulation structure 10 , and the other end is connected to the main body 231 .
  • the number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals.
  • the main body 231 may be square, bar-shaped or L-shaped.
  • the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
  • the lead frame 20 is integrally formed, positioned and encapsulated in the encapsulation structure 10 , the production cost is greatly saved and the overall production efficiency is improved.
  • FIG. 7A a schematic diagram of the front side connection of the semiconductor package structure (as shown in FIG. 7A ) and the back side are given.
  • FIG. 7B A schematic diagram of the connection (shown in Figure 7B). In the figure, only a schematic connection is made to the rewiring structure to illustrate the connection relationship.
  • the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 to realize the interconnection between the front and back of the chip 11; and the double-sided interconnection of different chips 11 (for example, one of the The interconnection between the front side of the chip 11 and the back side of the other chip 11 ) can be realized by the electrical connection of the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , and the second redistribution structure 70 .
  • the lead frame 20 shown in FIGS. 7A and 7B includes two upper and lower hollow regions 21 along the vertical direction of the paper surface, and each hollow region 21 is respectively placed with a chip 11 .
  • the front side of the chip 11 in the upper hollow area 21 is electrically connected to the connecting portion 24 and one of the edge portions 23 of the upper hollow area 21 through the first redistribution structure 50 respectively;
  • the front surface of the chip 11 in the hollow area 21 is electrically connected to the two edge portions 23 of the hollow area 21 located below through the first redistribution structure 50 respectively.
  • the backside of the chip 11 in the upper hollow region 21 is electrically connected to the other two edge portions 23 of the upper hollow region 21 through the second redistribution structure 70 ;
  • the back surface is electrically connected to the connection portion 24 through the second redistribution structure 70 . That is, the front surface of the chip 11 in the upper hollow region 21 is electrically connected to the back surface of the chip 11 in the lower hollow region 21 through the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , the second redistribution structure 70 and the lower hollow region 21 in sequence. connect.
  • the lead frame 20 includes the first part 27 and the first part 27 and the first part 27 in turn from the first surface of the encapsulation structure part 10 to the second surface of the encapsulation structure part 10 along the thickness direction T. II part 28.
  • the width w21 of the first portion 27 is greater than the width w22 of the second portion 28 , that is, the lead frame 20 having a stepped structure in cross section is formed.
  • the relatively wide contact surface of the first portion 27 can facilitate the formation of the first redistribution structure 50 over the lead frame 20, and can provide a relatively large area of support for the first redistribution structure 50;
  • the bonding force between the lead frame 20 and the encapsulation layer is enhanced, and the strength of the lead layer 80 of the semiconductor package structure on the PCB is enhanced, thereby enhancing the board-level reliability performance of the product.
  • the semiconductor package structure of this embodiment improves the thinning of the product by providing the overall structure, and can enhance the electrical reliability of the product.
  • the lead frame is provided with a hollow area that penetrates the lead frame in the thickness direction, and a plurality of chips are located in the hollow area, that is, the chips are embedded in the lead frame, which greatly reduces the thickness of the product. Thickness, effectively realize the thinning of the product.
  • the technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillars, thereby increasing the interconnection area, realizing the multi-layer wiring process, increasing the degree of freedom of product design, and enhancing the The electrical reliability of the product; at the same time, the production cost is saved and the overall production efficiency is improved.
  • the lead frame assembly in the semiconductor package structure of this embodiment does not need a lead portion located under the chip, it can be applied to a chip with a larger area, and more chips can be discharged, which has excellent applicability.
  • the content of the semiconductor packaging method of this embodiment is basically the same as that of the semiconductor packaging method of Embodiment 1, the difference is that in the semiconductor packaging method of this embodiment, the step of forming the protective layer 12 is placed on the chip to be packaged. 11 and the lead frame 20 are mounted before the carrier board 3 , and the first redistribution structure 50 directly forms the first surface 10 a of the encapsulation structure 10 .
  • a protective layer 12 is formed on the front surface of the chip 11 to be packaged.
  • the chip 11 to be packaged includes a front side 11a with solder pads, and a back side 11b opposite to the front side 11a.
  • the back side 11b is provided with a metal layer 111, so that the front side 11a and the back side 11b of the chip 11 to be packaged are electrically led out.
  • protective layer openings 121 are formed on the protective layer 12 at positions corresponding to the bonding pads on the front side 11a of the chip 11 to be packaged, and each protective layer opening 121 at least faces the bonding pads located on the chip 11 to be packaged or The lines drawn from the bonding pads make the bonding pads on the front side of the chip 11 to be packaged or the lines drawn from the bonding pads exposed from the protective layer opening 121 .
  • step 100 as shown in FIG. 9C , the chip to be packaged 11 and the lead frame 20 with the protective layer 12 formed on the front side are mounted on the carrier board 3 through the adhesive layer.
  • the backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 .
  • the lead frame 20 is provided with a hollow area 21 , the hollow area 21 penetrates the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .
  • step 200 as shown in FIG. 9D, by covering the encapsulation layer 14 on the entire carrier 3 (ie, covering the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3), and filling the In the hollow area 21 of the lead frame 20 , the to-be-packaged chip 11 and the lead frame 20 are encapsulated to form the encapsulation structure 10 .
  • the encapsulation structure 10 is a flat structure, and after the carrier board 3 is peeled off, rewiring and packaging can be continued on the flat structure.
  • the surface of the protective layer 12 is exposed.
  • the chip attachment layer in the adhesive layer still exists on the surface of the protective layer 12 , which can protect the surface of the chip 11 to be packaged from being damaged. destroy.
  • chemical cleaning or grinding can be used to make the surface smooth, which is beneficial for subsequent wiring.
  • the surface of the chip 11 to be packaged cannot be processed by chemical methods or grinding methods, so as not to damage the circuit on the front side of the chip 11 to be packaged.
  • a first redistribution structure 50 is formed on the first surface 10a of the encapsulation structure 10, and the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 to be packaged, And it is electrically connected to the first electrical connection point of the first surface 20 a of the lead frame 20 .
  • the first redistribution structure 50 includes at least one first redistribution layer 51 .
  • the first redistribution structure 50 includes a first redistribution layer 51 .
  • the first redistribution structure 50 may include multiple layers of first redistribution layers 51, that is, repeated redistribution is performed on the front surface of the chip to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the protective layer opening 121 has been formed on the protective layer 12 , when the first redistribution layer 51 is formed, at least the protective layer opening 121 can be directly seen, so the first redistribution structure 50 can be formed more accurately. bit.
  • a conductive medium may be filled in the protective layer openings 121 of the chip 11 to be packaged at the same time to form the conductive pillars 52 . That is, the first redistribution layer 51 and the conductive pillar 52 are formed in the same conductive layer forming process.
  • the conductive pillars 52 form substantially vertical connection structures in the protective layer openings 121 .
  • the bonding pads on the front surface 11 a of the chip 11 to be packaged are electrically led out through the conductive pillars 52 and the first redistribution layer 51 .
  • a dielectric layer 60 is formed.
  • the dielectric layer 60 is formed on the first redistribution structure 50 and the exposed portion of the first surface 10 a of the encapsulation structure 10 .
  • the dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing.
  • the dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
  • the present embodiment also provides a semiconductor structure 1 fabricated by the above-mentioned semiconductor packaging method.
  • the overall structure of the semiconductor structure 1 of this embodiment is basically the same as that of the first embodiment, the difference is that the protective layer 12 is provided on the front side of the chip 11 , and the orthographic projection of the protective layer 12 is the same as the orthographic projection of the chip 11 . , and the side of the protective layer 12 away from the chip 11 is substantially flush with the first surface 10 a of the encapsulation structure 10 .
  • the protective layer 12 is formed on the front surface of the chip 11 before the chip 11 is mounted on the carrier 3, so that after the carrier is peeled off, when the residual adhesive layer is chemically removed, the protective layer 12 It is also possible to protect the surface of the chip 11 from damage. After the adhesive layer is completely removed, if the encapsulation material has penetrated before, chemical cleaning or grinding can be used to make the surface smooth, which is beneficial for subsequent wiring. However, if there is no protective layer 12 , the surface of the encapsulation structure 10 cannot be processed by chemical methods or grinding methods, so as to avoid damaging the circuits on the front side of the chip 11 .

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Abstract

本申请提供一种半导体封装方法及半导体封装结构。根据一示例，该半导体封装方法包括：将引线框与多个待封装芯片贴装于载板上，且多个待封装芯片位于引线框的镂空区域中；通过将包封层覆盖在待封装芯片、引线框以及载板露出的部分上，且填充于引线框的镂空区域内，形成包封结构件；在包封结构件的第一表面形成与待封装芯片的正面以及引线框的第一面均电连接的第一再布线结构；以及，在包封结构件的第二表面形成与待封装芯片的背面以及引线框的第二面均电连接的第二再布线结构。

Description

半导体封装方法及半导体封装结构 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体封装方法及半导体封装结构。
背景技术
如图1所示，现有技术中常采用引线框30’与布线层40’配合实现两个芯片10’的双面互连封装。其中，两个芯片10’的背面通过导电胶20’贴于引线框30’上表面实现背面电连接，布线层40’通过铜柱50’实现与芯片10’的正面的连接。由于铜柱需要通过超声键和的方式植出，该工艺的成本极高，效率却极低。另外，将引线框30’布置在芯片10’的背面，导致所形成产品的厚度较厚，在应用于穿戴装备或其他对产品厚度有较高要求的场景时，将受到限制。
发明内容
有鉴于此，本申请提供了一种半导体封装方法和一种半导体封装结构。
本申请的一个方面提供半导体封装方法，其包括：将引线框与多个待封装芯片贴装于载板上，所述待封装芯片的正面朝向所述载板，所述引线框设有镂空区域，所述镂空区域沿厚度方向贯穿所述引线框，多个所述待封装芯片位于所述镂空区域中；通过将包封层覆盖在所述待封装芯片、所述引线框以及所述载板露出的部分上，且填充于所述引线框的镂空区域内，形成包封结构件，所述包封结构件包括第一表面以及与所述第一表面相对设置的第二表面，所述待封装芯片的正面和所述引线框的第一面露出于所述包封结构件的第一表面；在所述包封结构件的第一表面形成第一再布线结构，所述第一再布线结构与所述待封装芯片的正面以及所述引线框的第一面均电连接；以及，在所述包封结构件的第二表面形成第二再布线结构，所述第二再布线结构与所述待封装芯片的背面以及所述引线框相对所述第一面设置的第二面均电连接。
本申请的第二个方面提供一种半导体封装结构，其包括：包封结构件，具有相对的第一表面和第二表面，所述包封结构件包括引线架组件、多个芯片以及用于包封所述引线架组件和所述多个所述芯片的包封层，所述引线架组件设置在各所述芯片的外周以限定所述多个芯片各自的容置空间，所述容置空间沿厚度方向贯穿所述引线架组件，所述包封层填充于所述引线架组件限定的容置空间内，所述芯片的正面和所述引线架组件的 第一面露出于所述包封结构件的第一表面；第一再布线结构，所述第一再布线结构形成于所述包封结构件的第一表面，所述第一再布线结构与所述芯片的正面以及所述引线架组件的第一面均电连接；第二再布线结构，所述第二再布线结构形成于所述包封结构件的第二表面，所述第二再布线结构与所述芯片的背面以及所述引线架组件相对所述第一面设置的第二面均电连接。
本申请实施例提供的上述半导体封装方法及半导体封装结构，通过引线框和双面重布线互连工艺，实现了芯片的双面互连封装，提升了产品的薄型化，可增强产品的电学信赖性。
具体的，通过在引线框设有沿厚度方向贯穿所述引线框的镂空区域，并将多个待封装芯片位于所述镂空区域中，即，将待封装芯片嵌入在引线框中，从而大大地减薄了产品的厚度，有效实现了产品轻薄化。
本申请中的技术方案直接通过引线框实现芯片的双面互连，而不再需要铜柱，从而提升了互连面积，可实现多层布线工艺，增加了产品设计的自由度，并增强产品的电学信赖性；同时，节省了生产成本，提高了整体生产效率。现有技术中，如果设置多个铜柱，由于要设置多个各自独立的铜柱，不仅定位工艺复杂，且定位误差会产生累加；而在本申请中，由于引线框是一体成型，因此引线框上的各部分是一次定位就固定在载板上，从而包封在包封结构件中，大大地节省了生产成本，提高了整体生产效率。
通过将多个待封装芯片设置于引线框的镂空区域中，并将待封装芯片和引线框一起进行包封，避免了使用导电胶进行芯片的固定，从而提高了导入效率。
本申请的半导体封装方法中的引线框，由于不需要位于芯片下方的引线框部分，从而能够适用于面积更大的芯片，并可以排放更多的芯片，具有优异的适用性。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1为现有技术中的半导体封装结构的剖面图。
图2是根据本申请的实施例1提出的半导体封装方法的流程图。
图3是根据本申请的实施例1提出的引线框架的正面结构示意图。
图4是根据本申请的实施例1提出的引线框的正面结构示意图。
图5A-图5N是根据本申请的实施例1提出的中半导体封装方法的工艺流程图。
图6是根据本申请的实施例1提出的半导体封装结构的结构示意图。
图7A是根据本申请的实施例1提出的半导体封装结构的正面连接的示意图。
图7B是根据本申请的实施例1提出的半导体封装结构的背面连接的示意图。
图8是根据本申请的实施例1提出的半导体封装结构的另一实施方式的结构示意图。
图9A-图9G是根据本申请的实施例2中半导体封装方法的工艺流程图。
图10是根据本申请的实施例2提出的半导体封装结构的结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。事实上，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”表示两个或两个以上。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“上”和/或“下”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
实施例1
本实施例提供一种半导体封装方法及半导体封装结构。
图2是本实施例提出的半导体封装方法的流程图。如图2所示，所述半导体封装方法包括下述步骤：
步骤100：将引线框与多个待封装芯片贴装于载板上。其中，所述待封装芯片的正面朝向所述载板；所述引线框设有镂空区域，所述镂空区域沿厚度方向贯穿所述引线框；多个所述待封装芯片位于所述镂空区域中。
步骤200：通过将包封层覆盖在所述待封装芯片、所述引线框以及所述载板露出的部分上，且填充于所述镂空区域内，形成包封结构件。其中，所述包封结构件包括相对设置的第一表面和第二表面。所述待封装芯片的正面和所述引线框的第一面露出于所述包封结构件的第一表面。
步骤300：在所述包封结构件的第一表面形成第一再布线结构，所述第一再布线结构与所述待封装芯片的正面以及所述引线框的第一面均电连接；以及，在所述包封结构件的第二表面形成第二再布线结构，所述第二再布线结构与所述待封装芯片的背面以及所述引线框相对所述第一面设置的第二面均电连接。
本实施例的半导体封装方法提升了产品的薄型化，可增强产品的电学信赖性。
具体的，通过在引线框设有沿厚度方向贯穿所述引线框的镂空区域，并将多个待封装芯片位于所述镂空区域中，即将待封装芯片嵌入在引线框中，大大地减薄了产品的厚度，有效实现了产品轻薄化。
本实施例中的技术方案直接通过引线框实现芯片的双面互连，而不再需要铜柱，提升了互连面积，可实现多层布线工艺，增加了产品设计的自由度，并增强产品的电学信赖性；同时，节省了生产成本，提高了整体生产效率。现有技术中，如果设置多个铜柱，由于要设置多个各自独立的铜柱，不仅定位工艺复杂，且定位误差会产生累加；而在本申请中，由于引线框是一体成型，因此引线框上的各部分是一次定位就固定在载板上，从而包封在包封结构件中，大大地节省了生产成本，提高了整体生产效率。
通过将多个待封装芯片设置于引线框的镂空区域中，并将待封装芯片和引线框一起进行包封，避免了使用导电胶进行芯片的固定，从而提高了导入效率。
本实施例的半导体封装方法中的引线框，由于不需要位于芯片下方的引线框部分，从而能够适用于面积更大的芯片，并可以排放更多的芯片，具有优异的适用性。
本实施例中的引线框20的具体结构可如图3和图4所示。每一个完成封装后且进行切割后的最终半导体封装结构对应一个引线框20。多个呈阵列排列的相互连接的引线框 20组成引线框架2。引线框架2也可以仅由一个引线框20组成。
每一引线框20均包括框体22。框体22内设有沿厚度方向T贯穿框体22的镂空区域21。一个引线框20内的镂空区域21的数量可以为一个或者多个。
引线框20还包括连接部24。连接部24的两端分别与框体22相对的两侧连接，且连接部24将框体22的内部空间间隔为多个镂空区域。即，相邻的镂空区域21通过连接部24隔断，在同一引线框20内的相邻的镂空区域21之间通过连接部24隔断。
具体的，在本实施例中，如图4所示，每一引线框20的内部空间通过连接部24间隔为两个镂空区域，即，每一引线框20设有的镂空区域21的数量为两个，两个镂空区域21通过连接部24隔断。
连接部24包括依次连接的第一部分241、中间部分242和第二部分243。其中，第一部分241与中间部分242形成有第一夹角α，第二部分243与中间部分242形成有第二夹角β，第一部分241与第二部分243分别与框体22相对的两侧连接。这样，通过设置连接部24的具体结构，能够通过第一部分241和第二部分243实现更大的连接面积。较佳的，第一夹角α与第二夹角β均约等于90度，以使得第一部分241与第二部分243大致相互平行，这样，连接部24的结构可更为稳定。较佳的，第一部分241远离连接部24的一端与第二部分243远离连接部24的一端，均位于连接部24的同一侧，这样，连接部24的结构可更为紧凑。
引线框20还包括若干相互隔离的边缘部23，边缘部23的一端与框体22连接，另一端向镂空区域21延伸；每一镂空区域21内均设有若干相互隔离的边缘部23。具体的，边缘部23包括主体231和支撑部232，支撑部232连接于框体22和主体231之间。支撑部232的数量可以是一个，也可以是多个。当支撑部232的数量是多个时，多个支撑部232间隔设置。主体231可以是方形、条形或者L字形。较佳的，主体231为L字形的边缘部23设置于镂空区域21中远离连接部24的一角部。
进一步，分别位于不同的所述镂空区域中的所述待封装芯片通过所述连接部进行电连接。例如，可以将其中一待封装芯片的正面与另一待封装芯片的背面进行电气连通；或者，将其中一待封装芯片的正面与另一待封装芯片的正面进行电气连通；或者，将其中一待封装芯片的背面与另一待封装芯片的背面进行电气连通。
每一引线框20沿厚度方向T包括相对设置的第一面20a和第二面20b。其中，第一面20a上可设有若干第一电连接点，第二面20b上可设有若干第二电连接点。
具体地，如图5A-图5N所示，本实施例的半导体封装方法包括：
在步骤100中，如图5A所示，将待封装芯片11和引线框20通过粘接层贴装在载板3上。其中，待封装芯片11的背面朝上，正面朝向载板3。待封装芯片11包括设有焊垫的正面11a、以及相对于正面11a设置的背面11b，背面11b设有金属层111，从而待封装芯片11的正面11a及背面11b均有电气引出。引线框20设有镂空区域21，镂空区域21沿厚度方向T贯穿引线框20。多个待封装芯片11位于镂空区域21中。
在本实施例中，引线框20的厚度可大于待封装芯片11的厚度，以能够对待封装芯片11起到保护作用。
粘接层用以粘结待封装芯片11和引线框20至载板3。粘接层可采用易剥离的材料，以便在后续工序中，将载板3与待封装芯片11以及引线框20剥离开来。例如，粘接层可采用通过加热能够使其失去粘性的热分离材料。
在其他实施例中，粘接层可采用两层结构，包括热分离材料层和芯片附着层。其中，热分离材料层粘贴在载板3上，在加热时会失去黏性，进而能够从载板3上剥离下来。而芯片附着层采用具有粘性的材料层，可以用于粘贴待封装芯片11。待封装芯片11从载板3剥离开来后，可以通过化学清洗方式去除其上的芯片附着层。在一实施例中，可通过层压、印刷等方式，在载板3上形成粘接层。
待封装芯片11的数量为多个。待封装芯片11的数量根据设计要求可以调整，在此不做限定。
如前所述，由于引线框20是一体成型，即引线框的框体、连接部24、和边缘部23为一体成型，因此引线框的框体、连接部24、和边缘部23的各部分是一次定位就固定在载板上，从而大大地节省了生产成本，提高了整体生产效率。
在步骤200中，如图5B所示，通过将包封层14覆盖在整个载板3上(即，覆盖在待封装芯片11、引线框20以及载板3露出的部分上)，且填充于引线框20的镂空区域21内，对待封装芯片11和引线框20进行包封形成包封结构件10。包封结构件10为一平板结构，在将载板3剥离后，能够继续在该平板结构上进行再布线和封装。
包封结构件10包括相对设置的第一表面10a和第二表面10b。其中，包封结构件10的第二表面10b与载板3相对设置，基本上呈平板状，且与载板3的表面大致平行。
在一实施例中，包封层14可采用层压环氧树脂膜或塑封膜(Molding film)的方式形成，也可以通过对环氧树脂化合物进行注塑成型(Injection molding)、压模成型 (Compression molding)或转移成型(Transfer molding)的方式形成。
可选的，在进入步骤300前，所述封装方法还包括在包封结构件10的第二表面10b贴装第一支撑板41。
第一支撑板41至少贴装在包封结构件10的第二表面10b的至少部分区域。如图5C所示，在一实施例中，第一支撑板41覆盖包封结构件10的第二表面10b的全部区域。
第一支撑板41的材料强度大于所述包封层14的材料强度，使得能够有效提高并保证封装过程中封装结构的机械强度，有效抑制各结构变形带来的不利影响，从而提高产品封装的效果。在另一些实施例中，第一支撑板41也可通过喷涂(Spraying)、印刷(Printing)、涂覆(Coating)等方式形成于包封结构件10的第二表面10b上。
接续，在进入步骤300前，如图5D所示，所述封装方法还包括剥离所述载板3，露出包封结构件10的第一表面10a。包封结构件10的第一表面10a露出有待封装芯片11的正面、以及引线框20的第一面20a。
在载板3与待封装芯片以及引线框20之间的粘接层为热分离膜的情况下，可以通过加热的方式，使得粘接层在遇热后降低黏性，进而剥离载板3。通过加热粘接层剥离载板3的方式，能够将在剥离过程中对待封装芯片11的损害降至最低。在其他实施例中，也可直接机械的剥离载板3。
载板3剥离后，暴露出了包封结构件10的第一表面10a、待封装芯片11的正面、以及引线框20的第一面20a。剥离载板3后，得到了包括待封装芯片11、引线框20以及包封待封装芯片11和引线框20的包封层14的包封结构件10。在包封结构件10上，可以根据实际情况进行再布线等，使待封装芯片11与外界形成电连接。
需要说明的是，贴装第一支撑板41的步骤也可以放在剥离载板3之后。
接续，在进入步骤300之前，如图5E所示，在包封结构件10的第一表面10a形成保护层30。之后，如图5F所示，在保护层30上与待封装芯片11的正面的焊垫相对应的位置、以及与引线框20的第一面20a的所述第一电连接点的相对应的位置处形成保护层开口31。
在本实施例中，由于引线框20与待封装芯片11基本上布置在同一水平面上，在对保护层30进行打孔形成保护层开口31时，保护层30为透明膜层，可利用保护层30的透明度进行定位。此外，还可通过引线框20辅助定位，提高镭射钻孔的位置精确度。
在步骤300中，如图5G所示，在包封结构件10的第一表面10a上形成第一再布线结构50，第一再布线结构50与待封装芯片11的正面的焊垫电连接、且与引线框20的第一面20a的第一电连接点电连接。第一再布线结构50包括至少一层第一再布线层51。在本实施例中，第一再布线结构50包括一层第一再布线层51。但不限于此，第一再布线结构50也可以根据设计需要，包括多层第一再布线层51，即在待封装芯片的正面进行重复再布线。比如可以以同样的方式形成更多的再布线结构，可以根据设计要求进行调整。
其中，由于在保护层30上已经形成有保护层开口31，在形成第一再布线层51时，至少可以直接看到保护层开口31，因此形成第一再布线结构50时能够更加准确的对位。
在形成第一再布线结构50时，可以同时在保护层30的保护层开口31内填充导电介质以形成导电柱52。即，在同一导电层形成工艺中形成第一再布线层51和导电柱52。导电柱52在保护层开口31中形成大致竖直的连接结构。通过导电柱52、以及第一再布线层51将待封装芯片11的正面11a的焊垫电气引出。
接续，如图5H所示，形成介电层60。其中，介电层60形成于第一再布线结构50、以及包封结构件10的第一表面10a露出的部分上。介电层60可采用塑封膜(Molding film)的方式形成，或者介电层60可通过层压(Lamination)或印刷(Printing)的方式形成。介电层60可采用绝缘材料，如聚酰亚胺、环氧树脂、以及PBO(Polybenzoxazole)等中的一种或多种，优选采用环氧化合物。
如图5I所示，在形成介电层60后，所述封装方法还包括剥离第一支撑板41。可直接机械的剥离第一支撑板41，也可通过其他方法进行剥离。本申请对此不做限定，可根据具体应用环境进行设置。
可选的，在剥离第一支撑板41之后，所述封装方法还包括在介电层60远离包封结构件10的第一表面10a的一面贴装第二支撑板42。
第二支撑板42至少贴装在介电层60远离包封结构件10的一面的至少部分区域。如图5J所示，在一实施例中，在介电层60之上贴装第二支撑板42，且第二支撑板42贴装在介电层60远离包封结构件10的一面的全部区域。
第二支撑板42的材料强度可大于介电层60的材料强度，使得能够有效提高并保证封装过程中封装结构的机械强度，有效抑制各结构变形带来的不利影响，从而提高产品封装的效果。在另一些实施例中，第二支撑板42也可通过喷涂(Spraying)、印刷(Printing)、 涂覆(Coating)等方式形成于介电层60上。
需要说明的是，贴装第二支撑板42的步骤也可以放在剥离第一支撑板41之前。
可选的，如图5K所示，在包封结构件10的第二表面10b形成第二再布线结构70之前，所述封装方法还还包括对包封结构件10的第二表面10b进行研磨，以减薄包封结构件10的厚度。较佳的，减薄至露出引线框20的第二面20b。
减薄后的包封结构件10中，由于引线框20的厚度大于待封装芯片11的厚度，待封装芯片11的背面会保留有一定厚度的包封层14，以对待封装芯片11起到保护作用。
需要说明的是，在进行封装时，由于芯片生产段的工艺等的考虑，接收到的待封装芯片有可能为超薄芯片，为了保证芯片不被损坏，往往不能再通过研磨等工序对芯片进一步减薄。同时，当芯片11为超薄芯片时，引线框20也无法研磨到跟芯片11一致的厚度，因为引线框20若磨得过薄，会有断裂的风险。因此，需要保留一定厚度的包封层14在芯片的背面并通过钻孔方式实现芯片11的背面与第二再布线结构70的连通。通过上述设置，本申请即可适用于超薄型多芯片的整体封装。其中超薄型多芯片指厚度低于200微米的芯片。
接续，如图5L所示，在包封结构件10的第二表面10b形成多个开口15，开口15对应于待封装芯片11设置，以露出待封装芯片11的背面。即，在位于待封装芯片11背面的包封层14上开孔，以形成开口15。
接续，如图5M所示，在包封结构件10的第二表面10b形成第二再布线结构70。第二再布线结构70与待封装芯片11的背面的金属层111以及引线框20的第二面20b的第二电连接点均电连接。
需要说明的是，再布线结构(包括第二再布线结构70)的厚度可远小于现有技术中(如图1中)的引线框30’的厚度。一般再布线结构的厚度为15um-45um，引线框30’的厚度一般为150um-450um。因此，通过再布线结构不仅实现了布线的功能，还提升了产品的薄型化。
在本实施例中，由于引线框20与第一再布线结构50以及第二再布线结构70均电连接，实现待封装芯片11的正面以及背面的双面互连。即，通过引线框20连通了位于包封结构件10的第一表面10a上的第一再布线结构50和位于包封结构件10的第二表面10b上的第二再布线结构70。
这样，通过第一再布线结构50、引线框20、第二再布线结构70来实现待封装芯片 11的正面11a和背面11b的电气引出、以及半导体封装结构1内部各电子元件(不同的多个待封装芯片11)的电气连接，相对于通过引线完成电气连接，本实施例的半导体封装结构需要的空间更小，特别是厚度方向的空间。并且，由于不用再将电气连接最后集中于引线框架的引脚引出，再布线结构的布局更自由灵活。
具体地，待封装芯片11的正面11a的电气引出，是依次通过待封装芯片11的正面11a的焊垫、第一再布线结构50、引线框20、第二再布线结构70的电连接实现的；待封装芯片11的背面11b的电气引出，是通过直接与第二再布线结构70电连接实现的；不同的待封装芯片11的互连，包括同面的互连或者不同面的互连(如其中一个待封装芯片11的正面和另一个待封装芯片11的背面的互连)，可以通过第一再布线结构50、引线框20、第二再布线结构70的电连接实现的。
第二再布线结构可以包括至少一层第二再布线层和引脚层。其中，引脚层位于所述第二再布线层远离包封结构件的一侧。或者，第二再布线结构根据设计需要，仅包括一层引脚层。第二再布线层的层数可以是一层，也可以根据设计需要进行调整为多层，即在待封装芯片的背面进行重复再布线。比如可以以同样的方式形成更多的再布线结构，可以根据设计要求进行调整。
半导体封装结构1通过引脚层实现和外部的电气连接，并通过引脚层进行下一步安装。
引脚层的材料可为锡，也可以是镍金合金或者其他金属。
在本实施例中，请复参阅图5M，第二再布线结构70包括一层引脚层71。
在形成第二再布线结构70时，可以同时在包封层14的开口15内填充导电介质以形成导电凸柱72。即，在同一导电层形成工艺中形成引脚层71和导电凸柱72。导电凸柱72在开口15中形成大致竖直的连接结构。通过导电凸柱72、以及引脚层71将待封装芯片11的背面11b的焊垫电气引出。
接续，剥离第二支撑板42，如图5N所示。可直接机械的剥离第二支撑板42，也可通过其他方法进行剥离。本申请对此不做限定，可根据具体应用环境进行设置。
可选的，在剥离第二支撑板42之前或之后，还包括通过激光或机械切割的方式将引线框20的框体切除的步骤，该步骤的图示省略。
如果是多个半导体封装结构一起封装，在完成封装后，可通过激光或机械切割方式将整个封装结构切割成多个半导体封装结构。形成的半导体封装结构1的结构可如图6 所示。
如图6所示，是根据本实施例提供的利用上述半导体封装方法得到的半导体封装结构1的结构示意图。半导体封装结构1包括包封结构件10、第一再布线结构50和第二再布线结构70。
包封结构件10包括相对的第一表面10a和第二表面10b，包封结构件10包括引线架组件(主要对应于前述半导体封装方法中的引线框20中的连接部24和边缘部23)、多个芯片11以及用于包封引线架组件和多个芯片11的包封层14，引线架组件设置在各芯片11的外周以限定芯片各自的容置空间，所述容置空间沿厚度方向T贯穿引线架组件，多个芯片11位于所述容置空间中，包封层14填充于引线架组件限定的容置空间内。可见，引线架组件限定的多个芯片11各自的容置空间，可对应于前述半导体封装方法中的引线框20内的镂空区域21。
芯片11的数量为多个。芯片11的数量根据设计要求可以调整，在此不做限定。在本实施例中，芯片11的数量为两个。一个引线框20的镂空区域21的数量可以为一个或者多个。在本实施例中，每一引线框20设有的镂空区域21的数量为两个。但不限于此，镂空区域21的数量可以根据设计需要为其他数量。
根据设计要求，可以是将多个芯片11放置于不同的镂空区域21，也可以是将多个芯片11放置于相同的镂空区域21。
引线框20还包括连接部24。连接部24将所述引线框20的内部空间间隔为多个镂空区域。分别位于不同的所述镂空区域中的芯片11通过连接部24进行电连接。
具体的，在本实施例中，每一引线框20通过连接部24间隔为两个镂空区域。即，每一引线框20设有的镂空区域21的数量为两个，两个镂空区域21通过连接部24隔断。两个芯片11分别位于两个不同的所述镂空区域中。
芯片11包括设有焊垫的正面、以及相对于正面设置的背面，背面设有金属层111，从而芯片11的正面及背面均有电气引出。引线框20的第一面20a露出于包封结构件的第一表面10a。
第一再布线结构50对应于芯片11的正面并形成于包封结构件10的第一表面10a，第一再布线结构50与芯片11的正面的焊垫电连接、且与引线框20的第一面20a的第一电连接点电连接。
第一再布线结构50包括至少一层第一再布线层51。在本实施例中，第一再布线结 构50包括一层第一再布线层51。但不限于此，也可以根据设计需要，第一再布线结构50包括多层第一再布线层51，即在芯片的正面进行重复再布线。比如可以以同样的方式形成更多的再布线结构，可以根据设计要求进行调整。
包封结构件10的第一表面10a上可设有保护层30，保护层30位于第一再布线结构50和包封结构件10之间。保护层30上开设有保护层开口31，保护层开口31内设有通过填充导电介质而形成的导电柱52。可以在同一导电层形成工艺中形成第一再布线层51和导电柱52。
第二再布线结构70对应于芯片11的背面并形成于包封结构件10的第二表面10b。第二再布线结构70与芯片11的背面的金属层111以及引线框20的第二面20b的第二电连接点均电连接。第二再布线结构70包括至少一层第二再布线层71。
在本实施例中，由于引线框20与第一再布线结构50以及第二再布线结构70均电连接，实现芯片11的正面以及背面的双面互连。即，通过引线框20连通了位于包封结构件10的第一表面10a上的第一再布线结构50和位于包封结构件10的第二表面10b上的第二再布线结构70。
这样，通过第一再布线结构50、引线框20、第二再布线结构70来实现芯片11的正面和背面的电气引出、以及半导体封装结构1内部各电子元件(不同的多个芯片11)的电气连接，相对于通过引线完成电气连接，本实施例的半导体封装结构需要的空间更小，特别是厚度方向的空间；并且，由于不用将电气连接最后集中于引线框架的引脚引出，再布线结构的布局更自由灵活。
具体地，芯片11的正面的电气引出，是依次通过芯片11的正面的焊垫、第一再布线结构50、引线框20、第二再布线结构70的电连接实现的；芯片11的背面的电气引出，是通过直接与第二再布线结构70电连接实现的；不同的芯片11的互连，包括同面的互连或者不同面的互连(如其中一个芯片11的正面和另一个芯片11的背面的互连)，可以通过第一再布线结构50、引线框20、第二再布线结构70的电连接实现的。
第二再布线结构可以包括至少一层第二再布线层和引脚层，引脚层位于所述第二再布线层远离包封结构件的一侧。或者，第二再布线结构根据设计需要，仅包括一层引脚层。第二再布线层的层数可以是一层，也可以根据设计需要进行调整为多层，即在芯片的正面进行重复再布线。比如可以以同样的方式形成更多的再布线结构，可以根据设计要求进行调整。当所述第二再布线结构包括至少一层第二再布线层和引脚层时，所 述引脚层的正投影位于所述第二再布线层的正投影之内。即，相邻的引脚层之间的间距大于对应于该相邻的引脚层的相邻第二再布线层之间的间距，以使最终形成的半导体封装产品在使用锡或其他材料进行焊接时不易短路，提升了产品的电学性能。
半导体封装结构1通过引脚层实现和外部的电气连接，并通过引脚层进行下一步安装。
引脚层的材料可为锡，也可以是镍金合金或者其他金属。
在本实施例中，第二再布线结构70包括一层引脚层71。
引线框20的厚度大于芯片11的厚度。引线框20的第二面20b露出于包封结构件10的第二表面10b，即包封结构件10的厚度等于引线框20的厚度，从而实现半导体封装结构1的最薄化。
由于引线框20的厚度大于芯片11的厚度，芯片11的背面会保留有一定厚度的包封层14，以对芯片11起到保护作用。
如上所述，在进行封装时，由于芯片生产段的工艺等的考虑，接收到的待封装芯片有可能为超薄芯片，为了保证芯片不被损坏，往往不能再通过研磨等工序对芯片进一步减薄。同时，当芯片11为超薄芯片时，引线框20也无法研磨到跟芯片11一致的厚度。因为引线框20若磨得过薄，会有断裂的风险。因此，需要保留一定厚度的包封层14在芯片的背面并通过钻孔方式实现芯片11的背面与第二再布线结构70的连通。通过上述设置，本申请即可适用于超薄型多芯片的整体封装。其中超薄型多芯片指厚度低于200微米的芯片。
包封结构件10的第二表面10b开设有开口15，开口15对应于芯片11设置，以露出芯片11的背面。即，通过在位于芯片11的背面的包封层14上开孔，以形成开口15。第二再布线结构70还包括导电凸柱72，通过在开口15内填充导电介质形成导电凸柱72，导电凸柱72与芯片11的背面电连接。可以在同一导电层形成工艺中形成引脚层71和导电凸柱72。
包封结构件10还包括介电层60，介电层60形成于第一再布线结构50、以及包封结构件10的第一表面10a露出的部分上。介电层60可采用塑封膜(Molding film)的方式形成，或者介电层60可通过层压(Lamination)或印刷(Printing)的方式形成。介电层60可采用绝缘材料，如聚酰亚胺、环氧树脂、以及PBO(Polybenzoxazole)等中的一种或多种，优选采用环氧化合物。当芯片的正面进行重复再布线时，也可以以同 样的方式形成更多的介电层，可以根据设计要求进行调整。
如图7A和图7B所示，引线框20的连接部24包括依次连接的第一部分241、中间部分242和第二部分243。其中，第一部分241与中间部分242形成有第一夹角α，第二部分243与中间部分242形成有第二夹角β。这样，通过设置连接部24的具体结构，能够通过第一部分241和第二部分243实现更大的连接面积。较佳的，第一夹角α与第二夹角β均约等于90度，以使得第一部分241与第二部分243大致相互平行，这样，连接部24的结构可更为稳定。较佳的，第一部分241远离连接部24的一端与第二部分243远离连接部24的一端，均位于连接部24的同一侧，这样，连接部24的结构可更为紧凑。
引线框20还包括若干相互隔离的边缘部23，边缘部23的一端露出于包封结构件10的表面，另一端向镂空区域21延伸；每一镂空区域21内均设有若干相互隔离的边缘部23。具体的，边缘部23包括主体231和支撑部232，支撑部远离主体231的一端露出于包封结构件10的表面，另一端与主体231连接。支撑部232的数量可以是一个，也可以是多个。当支撑部232的数量是多个时，多个支撑部232间隔设置。主体231可以是方形、条形或者L字形。较佳的，主体231为L字形的边缘部23设置于镂空区域21中远离连接部24的一角部。
如前所述，由于引线框20是一体成型、并一体定位以及包封在包封结构件10中，从而大大地节省了生产成本，提高了整体生产效率。
进一步的，为了示意芯片11的正面与引线框20的连接关系、以及芯片11的背面与引线框20的连接关系，给出了半导体封装结构的正面连接的示意图(如图7A所示)和背面连接的示意图(如图7B所示)。在图中，仅是对于再布线结构做了一个示意性连接，以说明连接关系。可以看出，引线框20与第一再布线结构50以及第二再布线结构70均电连接，实现芯片11的正面与背面的互连；而且不同的芯片11的双面互连(例如其中一个芯片11的正面和另一个芯片11的背面的互连)，可通过第一再布线结构50、引线框20的连接部24、第二再布线结构70的电连接实现。
具体地，图7A和图7B中所示引线框20沿纸面垂直方向包括上下两个镂空区域21，每个镂空区域21分别放置了一个芯片11。其中，在图7A中，位于上面的镂空区域21的芯片11的正面通过第一再布线结构50分别与连接部24、以及位于上面的镂空区域21的其中一个边缘部23实现电连接；位于下面的镂空区域21的芯片11的正面通过第一再布线结构50分别与位于下面的镂空区域21的两个边缘部23实现电连接。 在图7B中，位于上面的镂空区域21的芯片11的背面通过第二再布线结构70与位于上面的镂空区域21的另外两个边缘部23电连接；位于下面的镂空区域21的芯片11的背面通过第二再布线结构70与连接部24电连接。即，位于上面的镂空区域21的芯片11的正面依次通过第一再布线结构50、引线框20的连接部24、第二再布线结构70与位于下面的镂空区域21的芯片11的背面实现电连接。
在另一实施方式中，如图8所示，引线框20沿厚度方向T由包封结构件10的第一表面至所述包封结构件10的第二表面，依次包括第一部分27和第二部分28。其中，第一部分27的宽度w21大于第二部分28的宽度w22，即形成剖面为阶梯形状的结构的引线框20。这样，第一部分27的相对较宽的接触面可以利于在引线框20上方形成第一再布线结构50时，能为第一再布线结构50提供较为大面积的支持；而且，阶梯形状的结构可以提升引线框20与包封层之间的结合力并提升半导体封装结构的引脚层80在PCB板上的强度，从而提升产品的板级可靠性能。
本实施例的半导体封装结构通过设置整体结构提升了产品的薄型化，可增强产品的电学信赖性。
具体的，通过在引线框设有沿厚度方向贯穿所述引线框的镂空区域，并将多个芯片位于所述镂空区域中，即，将芯片嵌入在引线框中，大大地减薄了产品的厚度，有效实现了产品轻薄化。
本实施例中的技术方案直接通过引线框实现芯片的双面互连，而不再需要铜柱，从而提升了互连面积，可实现多层布线工艺，增加了产品设计的自由度，并增强产品的电学信赖性；同时，节省了生产成本，提高了整体生产效率。需要说明的是，现有技术中，如果设置多个铜柱，由于要设置多个各自独立的铜柱，不仅定位工艺复杂，且定位误差会产生累加；而在本申请中，由于引线框是一体成型，因此引线框上的各部分是一次定位就固定在载板上，从而包封在包封结构件中，大大地节省了生产成本，提高了整体生产效率。
通过将多个芯片设置于引线框的镂空区域中，并将芯片和引线框一起进行包封，避免了使用导电胶进行芯片的固定，从而提高了导入效率。
本实施例的半导体封装结构中的引线架组件，由于不需要位于芯片下方的引线部分，从而能够适用于面积更大的芯片，并可以排放更多的芯片，具有优异的适用性。
实施例2
本实施例的半导体封装方法的内容和实施例1中的半导体封装方法基本相同，不同的之处在于，在本实施例的半导体封装方法中，形成保护层12的步骤放在了将待封装芯片11和引线框20贴装在载板3之前，而第一再布线结构50直接形成包封结构件10的第一表面10a。
具体地，在步骤100前，如图9A所示，在待封装芯片11的正面形成保护层12。待封装芯片11包括设有焊垫的正面11a、以及相对于正面11a设置的背面11b，背面11b设有金属层111，从而待封装芯片11的正面11a及背面11b均有电气引出。
如图9B所示，在保护层12上与待封装芯片11的正面11a的焊垫相对应的位置处形成保护层开口121，每个保护层开口121至少对位于待封装芯片11的焊垫或者从焊垫引出的线路，使得待封装芯片11正面的焊垫或者从焊垫引出的线路从保护层开口121暴露出来。
在步骤100中，如图9C所示，将正面形成保护层12的待封装芯片11和引线框20通过粘接层贴装在载板3上。其中，待封装芯片11的背面朝上，正面朝向载板3。引线框20设有镂空区域21，镂空区域21沿厚度方向T贯穿引线框20，多个待封装芯片11位于镂空区域21中。
在步骤200中，如图9D所示，通过将包封层14覆盖在整个载板3上(即，覆盖在待封装芯片11、引线框20以及载板3露出的部分上)，且填充于引线框20的镂空区域21内，对待封装芯片11和引线框20进行包封形成包封结构件10。包封结构件10为一平板结构，在将载板3剥离后，能够继续在该平板结构上进行再布线和封装。
在剥离了载板3之后，如图9E所示，暴露出保护层12的表面，此时粘接层中芯片附着层还存在于保护层12的表面，能够保护待封装芯片11的表面不受破坏。在完全去除粘接层后，如果之前渗入了包封材料，还可以采用化学清洗或研磨的方式使得表面平整，有利于后面布线。而如果没有保护层12，则无法通过化学方式或者研磨的方式处理待封装芯片11的表面，以免破坏待封装芯片11的正面的电路。
在步骤300中，如图9F所示，在包封结构件10的第一表面10a上形成第一再布线结构50，第一再布线结构50与待封装芯片11的正面的焊垫电连接、且与引线框20的第一面20a的第一电连接点电连接。第一再布线结构50包括至少一层第一再布线层51。在本实施例中，第一再布线结构50包括一层第一再布线层51。但不限于此，也可以根据设计需要，第一再布线结构50可包括多层第一再布线层51，即在待封装芯片 的正面进行重复再布线。比如可以以同样的方式形成更多的再布线结构，可以根据设计要求进行调整。
其中，由于在保护层12上已经形成有保护层开口121，在形成第一再布线层51时，至少可以直接看到保护层开口121，因此形成第一再布线结构50时能够更加准确的对位。
在形成第一再布线结构50时，可以同时在待封装芯片11的保护层开口121内填充导电介质以形成导电柱52。即，在同一导电层形成工艺中形成第一再布线层51和导电柱52。导电柱52在保护层开口121中形成大致竖直的连接结构。通过导电柱52、以及第一再布线层51将待封装芯片11的正面11a的焊垫电气引出。
接续，如图9G所示，形成介电层60，介电层60形成于第一再布线结构50、以及包封结构件10的第一表面10a露出的部分上。介电层60可采用塑封膜(Molding film)的方式形成，或者介电层60可通过层压(Lamination)或印刷(Printing)的方式形成。介电层60可采用绝缘材料，如聚酰亚胺、环氧树脂、以及PBO(Polybenzoxazole)等中的一种或多种，优选采用环氧化合物。
如图10所示，本实施例还提供由上述半导体封装方法制得的半导体结构1。本实施例的半导体结构1的整体结构基本上和实施例1中的结构相同，不同的之处在于，保护层12设于芯片11的正面，保护层12的正投影与芯片11的正投影相同，且保护层12远离所述芯片11的一侧与所述包封结构件10的第一表面10a基本上平齐。即，在封装过程中，在将芯片11贴装在载板3之前就在芯片11的正面形成保护层12，从而在剥离载板之后，在通过化学方式去除残留粘接层时，保护层12还能够保护芯片11的表面不受破坏。在完全去除粘接层后，如果之前渗入了包封材料，还可以采用化学清洗或研磨的方式使得表面平整，有利于后面布线。而如果没有保护层12，则无法通过化学方式或者研磨的方式处理包封结构件10的表面，以免破坏芯片11的正面的电路。
在本申请中，所述结构实施例与方法实施例在不冲突的情况下，可以互为补充。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (12)

  1. 一种半导体封装方法，包括：
    将引线框与多个待封装芯片贴装于载板上，其中
    所述待封装芯片的正面朝向所述载板，
    所述引线框设有镂空区域，所述镂空区域沿厚度方向贯穿所述引线框，
    多个所述待封装芯片位于所述镂空区域中；
    通过将包封层覆盖在所述待封装芯片、所述引线框以及所述载板露出的部分上，且填充于所述引线框的镂空区域内，形成包封结构件，其中
    所述包封结构件包括第一表面和以及与所述第一表面相对设置的第二表面，
    所述待封装芯片的正面和所述引线框的第一面露出于所述包封结构件的第一表面；
    在所述包封结构件的第一表面形成第一再布线结构，所述第一再布线结构与所述待封装芯片的正面以及所述引线框的第一面均电连接；以及，
    在所述包封结构件的第二表面形成第二再布线结构，所述第二再布线结构与所述待封装芯片的背面以及所述引线框相对所述第一面设置的第二面均电连接。
  2. 如权利要求1所述的半导体封装方法，其特征在于，
    所述引线框包括连接部，
    所述连接部将所述引线框的内部空间间隔为多个所示镂空区域，
    分别位于不同的所述镂空区域中的所述待封装芯片通过所述连接部进行电连接。
  3. 如权利要求2所述的半导体封装方法，其特征在于，
    所述引线框还包括框体，所述镂空区域沿所述厚度方向贯穿所述框体；
    所述连接部的两端分别与所述框体相对的两侧连接。
  4. 如权利要求3所述的半导体封装方法，其特征在于，
    所述引线框还包括若干相互隔离的边缘部，
    所述边缘部的一端与所述框体连接，另一端向镂空区域延伸；
    每一所述镂空区域内均设有若干相互隔离的边缘部。
  5. 如权利要求1所述的半导体封装方法，其特征在于，
    所述引线框的厚度大于所述待封装芯片的厚度，
    在形成所述第一再布线结构之前，所述半导体封装方法还包括：对所述包封结构件进行减薄至从所述包封结构件的第一表面露出所述引线框的第一面。
  6. 如权利要求1所述的半导体封装方法，其特征在于，
    在形成所述第二再布线结构之前，所述半导体封装方法还包括：在所述包封结构件的第二表面形成多个开口，所述开口对位于所述待封装芯片以露出所述待封装芯片的背面；
    在形成所述第二再布线结构中，所述第二再布线结构包括在所述开口中形成的导电凸柱，所述导电凸柱与所述待封装芯片的背面电连接。
  7. 如权利要求1所述的半导体封装方法，其特征在于，
    所述引线框沿厚度方向由所述包封结构件的第一表面至所述包封结构件的第二表面，依次包括第一部分和第二部分，
    所述引线框的第一部分的宽度大于所述引线框的第二部分的宽度。
  8. 一种半导体封装结构，包括：
    包封结构件，具有相对的第一表面和第二表面，包括：
    多个芯片；
    引线架组件，设置在各所述芯片的外周，用于限定所述多个芯片各自的容置空间；以及，
    用于包封所述引线架组件以及所述多个所述芯片的包封层，所述包封层填充于所述引线架组件限定的容置空间内，
    其中，所述芯片的正面和所述引线架组件的第一面露出于所述包封结构件的第一表面；
    第一再布线结构，所述第一再布线结构形成于所述包封结构件的第一表面，所述第一再布线结构与所述芯片的正面以及所述引线架组件的第一面均电连接；
    第二再布线结构，所述第二再布线结构形成于所述包封结构件的第二表面，所述第二再布线结构与所述芯片的背面以及所述引线架组件相对所述第一面设置的第二面均电连接。
  9. 如权利要求8所述的半导体封装结构，其特征在于，
    所述引线架组件包括连接部，
    所述连接部用于至少将所述多个芯片相互间隔开，
    不同的所述容置空间中的所述待封装芯片通过所述连接部进行电连接。
  10. 如权利要求8所述的半导体封装结构，其特征在于，
    所述引线架组件还包括若干相互隔离的边缘部，
    所述边缘部沿所述包封结构件的内周缘设置，
    所述边缘部的一端露出于所述包封结构件的表面，另一端向所述芯片的容置空间延 伸；
    每一所述芯片的容置空间内均设有若干相互隔离的边缘部。
  11. 如权利要求8所述的半导体封装结构，其特征在于，
    所述包封结构件的第二表面形成多个开口，所述开口对应于所述芯片设置，
    所述第二再布线结构包括导电凸柱，所述导电凸柱形成于所述开口中，且与所述芯片的背面电连接。
  12. 如权利要求8所述的半导体封装结构，其特征在于，
    所述引线架组件沿厚度方向由所述包封结构件的第一表面至所述包封结构件的第二表面，依次包括第一部分和第二部分，
    所述引线架组件的第一部分的宽度大于所述引线架组件的第二部分的宽度。
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