WO2021258845A1 - Led显示***及其控制方法 - Google Patents

Led显示***及其控制方法 Download PDF

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Publication number
WO2021258845A1
WO2021258845A1 PCT/CN2021/089987 CN2021089987W WO2021258845A1 WO 2021258845 A1 WO2021258845 A1 WO 2021258845A1 CN 2021089987 W CN2021089987 W CN 2021089987W WO 2021258845 A1 WO2021258845 A1 WO 2021258845A1
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Prior art keywords
drive circuit
clock signal
parameter value
display system
led display
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PCT/CN2021/089987
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English (en)
French (fr)
Inventor
孔令军
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杭州视芯科技有限公司
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Priority to US18/007,767 priority Critical patent/US11967270B2/en
Publication of WO2021258845A1 publication Critical patent/WO2021258845A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication

Definitions

  • the invention relates to the field of display technology, in particular to a display system of an LED display screen and a control method thereof.
  • the LED display system 100 usually includes a control card 110 and a plurality of driving circuits 120.
  • the control card 110 provides multiple signals, and each signal controls a corresponding plurality of drive circuits 120 serially connected in sequence. As the number of drive circuits 120 connected in series in the system increases, the signal provided by the control card 110 will gradually attenuate due to the increase in the load, and the attenuation of the clock signal is particularly noticeable during the transmission process.
  • the clock signal is a signal that switches back and forth between a high level and a low level. When the clock signal decays, the duty cycle of the clock signal will change. If the clock signal, which is the basis of data sampling, has been attenuated, eventually other digital signals will not be read correctly, which will affect the display effect of the LED display.
  • the purpose of the present invention is to provide an LED display system and a control method thereof, so as to avoid excessive attenuation of the clock signal and ensure the display effect of the LED display screen.
  • an LED display system which includes: a control card that outputs multiple clock signals and data signals; at least one drive circuit group is connected to the control card, and each drive circuit group includes multiple stages Connected drive circuits, each of the drive circuit groups receives a channel of the clock signal and the data signal and transmits them in the plurality of drive circuits, at least one drive circuit in each drive circuit group includes an inverter, The inverter performs inversion processing on the clock signal received by the driving circuit of the current stage to obtain an inverted clock signal.
  • each of the driving circuits further includes: a communication unit connected to the control card or the upper-level driving circuit to receive the clock signal and the data signal, and perform processing on the data signal according to the clock signal Decode and transmit the data signal to the next-level drive circuit.
  • each of the driving circuits of the at least one driving circuit group includes the inverter.
  • the data signal includes display data, parameter values, and the ID of the driving circuit.
  • each of the drive circuits further includes: a comparison and selection unit, connected to the communication unit to receive the decoded data signal, and select the inverted clock signal or the original according to the ID and parameter value of the drive circuit
  • the clock signal received by the stage drive circuit is provided to the next stage drive circuit, and the parameter value is a positive integer.
  • the comparison selection unit includes: a comparator connected to the communication unit to receive the parameter value and the ID of the drive circuit at the current level, and provide a comparison result of the parameter value and the ID of the drive circuit; the selector, first One input terminal is connected to the inverter to receive the inverted clock signal, the second input terminal is to receive the clock signal of the drive circuit of this stage, the control terminal is connected to the output terminal of the comparator to receive the comparison result, and the output terminal is to the next stage of drive circuit Output the inverted clock signal or the clock signal of the drive circuit of this level.
  • the IDs of the driving circuits in each group of driving circuit groups are sequentially 1, 2, 3...X or a cycle of 1 to N, where X is a positive integer and N is the parameter value.
  • the selector uses the inverted clock signal as the clock signal of the next-stage drive circuit
  • the selector uses the clock signal of the driving circuit of the current level as the clock signal of the driving circuit of the next level.
  • the communication unit includes a decoder.
  • the inverter is a NOT gate.
  • each of the driving circuits further includes: a driving unit connected to the communication unit to receive the decoded display data.
  • a control method of a display system including: providing multiple channels of clock signals and data signals; each drive circuit group receives one channel of the clock signal and the data signal and distributes them in multiple drive circuits In transmission, at least one drive circuit in each drive circuit group performs inversion processing on the clock signal received by the drive circuit at the current level to obtain an inverted clock signal, wherein each drive circuit group includes a plurality of cascaded drive circuits.
  • the method further includes: each of the driving circuits decodes the data signal according to the received clock signal, and transmits the data signal to the next-stage driving circuit.
  • each drive circuit in each drive circuit group performs inversion processing on the clock signal received by the drive circuit at the current level to obtain an inverted clock signal.
  • the data signal includes display data, parameter values, and the ID of the driving circuit.
  • each driving circuit selects to provide the inverted clock signal or the clock signal received by the driving circuit of the current level to the driving circuit of the next level according to the ID and parameter value of the driving circuit, and the parameter value is Positive integer.
  • the IDs of the driving circuits in each group of driving circuit groups may be 1, 2, 3...X or 1 to N cycles in sequence, where X is a positive integer and N is the parameter value.
  • the inverted clock signal is used as the clock signal of the next-stage drive circuit; the ID of the drive circuit is not equal to the parameter value or When the parameter value is an integer multiple, the clock signal of the driving circuit of the current stage is used as the clock signal of the driving circuit of the next stage.
  • an inverter is provided in at least one of the multiple cascaded drive circuits in each group to invert the clock signal and provide the inverted clock to the next drive circuit.
  • this embodiment can effectively avoid excessive attenuation of the clock signal in the cascaded drive circuit, ensure the accuracy of data sampling based on the clock signal, and ensure the display effect of the LED display screen.
  • an inverter is added to each drive circuit to invert the clock signal of the current stage to obtain the inverted clock signal and provide it to the next-stage drive circuit, which can effectively prevent the clock signal from being cascaded. Excessive attenuation in the drive circuit can also improve the designability of the drive circuit and enhance the flexibility of the LED display system.
  • each drive circuit is also provided with a comparison and selection unit, and the comparison and selection unit of each drive circuit will, based on the parameter value provided by the control card and the ID of each drive circuit, reverse the clock signal of the drive circuit at this level or
  • the inverted clock signal obtained by the phaser is provided to the next-stage drive circuit, so that in the LED display system, the inverted clock is provided to the next-stage drive circuit after each transmission through the drive circuit of the set parameter value Signal, and provide the drive circuit of the remaining stage with the clock signal of the previous drive circuit.
  • the parameter values set above can be flexibly adjusted according to the attenuation rate of the clock signal of the actual circuit, so as to be suitable for a variety of application environments.
  • Figure 1 shows a structural block diagram of an LED display system according to the prior art
  • Figure 2 shows a structural block diagram of the LED display system according to the first embodiment of the present invention
  • Figure 3 shows a schematic structural diagram of an LED display system according to a second embodiment of the present invention.
  • FIG. 4 shows a schematic diagram of the working principle of the driving circuit in the LED display system according to the second embodiment of the present invention.
  • Fig. 2 shows a structural block diagram of the LED display system according to the first embodiment of the present invention.
  • the LED display system 200 includes a control card 110 and a plurality of driving circuit groups respectively connected to the control card 110, and each driving circuit group includes a plurality of cascaded driving circuits 220.
  • the LED display system 200 also includes a plurality of LED lamp groups connected to the driving circuit 220, wherein the plurality of lamp groups constitute an LED display screen.
  • the control card 110 provides multiple control signals. Each control signal controls a corresponding plurality of cascaded drive circuits 220.
  • Each control signal includes a data signal for driving the LED lamp group and a clock signal for indicating sequential logic.
  • the data signal contains at least display data.
  • the at least one driving circuit 220 includes a driving unit 221, an inverter 222, and a communication unit 223.
  • the communication unit 223 is connected to the control card 110 or the upper-level driving circuit 220 to receive the clock signal and the data signal, decode the data signal with the cooperation of the clock signal, and then send the display data required by the current-level driving circuit 220 to Drive unit 221.
  • the communication unit 324 further transmits the data signal to the communication unit of the driving circuit 220 at the next stage.
  • the inverter 223 is connected to the control card 110 or the upper-level driving circuit 220 to receive the clock signal, and performs inversion processing on the received clock signal to obtain the inverted clock signal to provide the next-level driving circuit 220.
  • the LED display system 200 includes at least one drive circuit 220 provided with an inverter 222, and the drive circuit 220 can be any level of drive circuit in the LED display system 200.
  • the remaining driving circuits in the LED display system 200 that do not have the inversion processing capability only include a communication unit 223 and a driving unit 222, wherein the communication unit 223 is connected to the control card 110 or the upper-level driving circuit to receive clock signals and data The signal and the clock signal and the data signal are transmitted to the next-level driving circuit, and the data signal is decoded with the cooperation of the clock signal, and then the display data required by the current-level driving circuit is sent to the driving unit 221.
  • each level of driving circuit in the LED display system 200 is a driving circuit 220 with inverting processing capability.
  • the above-mentioned LED display system 200 can effectively prevent the clock signal from continuously attenuating in multiple cascaded drive circuits. For example, when a 50% duty cycle clock signal passes through one or more stages of drive circuits, the duty cycle attenuates to 40%. At this time, the clock signal with a duty cycle of 40% is inverted, the high and low levels are reversed, and the duty cycle becomes 60%, to avoid excessive attenuation of the duty cycle, and to ensure that the clock signal is used as the basis for data sampling The data sampling can accurately sample to ensure that the LED display system reads the data signal correctly, solves the attenuation problem, and guarantees the display effect of the LED display. In the driving circuit of this embodiment, less hardware is used to implement efficient attenuation processing, which saves costs.
  • Fig. 3 shows a schematic structural diagram of an LED display system according to a second embodiment of the present invention.
  • the LED display system 300 includes a control card 310 and a plurality of driving circuit groups respectively connected to the control card 310, and each driving circuit group includes a plurality of cascaded driving circuits 320.
  • the LED display system 300 also includes a plurality of LED lamp groups connected to the driving circuit 320, wherein the plurality of lamp groups constitute an LED display screen.
  • at least one stage of the drive circuit performs inversion processing on the received clock signal and outputs the inverted clock signal to the next stage of the drive circuit.
  • each Each drive circuit 320 in each drive circuit group performs inversion processing on the received clock signal and selects the received clock signal or the inverted clock signal as the clock signal received by the next-stage drive circuit 320, specifically, After the clock signal is transmitted through the driving circuit 320 of the set parameter value, the inverted clock signal is used as the clock signal received by the driving circuit 320 of the next stage.
  • the control card 310 provides multiple control signals, and each control signal controls a plurality of cascaded drive circuits 320 in each drive circuit group.
  • Each control signal includes a data signal for driving the LED lamp group and a clock signal for indicating sequential logic.
  • the control card 310 sets a parameter value N and configures an ID (Identity document, identity identification number) for each level of the driving circuit 320.
  • the parameter value N determines that when the ID of the drive circuit is N or a multiple of N, the inverted clock signal is output as the clock signal received by the next-stage drive circuit, where the parameter value N is a positive integer.
  • the ID of the driving circuit 320 is used to indicate the relative position of the driving circuit 320 in the LED display system. For example, when the driving circuit 320 is at the third level in the driving circuit group that receives the control signal output by a certain routing control card 310 , The ID assigned to it by the control card 310 is 3.
  • the driving circuit 320 includes a driving unit 321, an inverter 322, a communication unit 324, and a comparison and selection unit 323.
  • the comparison selection unit 323 includes a comparator 3231 and a selector 3232.
  • the inverter 322 is connected to the control card 310 or the upper-level driving circuit 320 to receive the clock signal, and performs inversion processing on the received clock signal to obtain an inverted clock signal.
  • the communication unit 324 is connected to the control card 310 or the upper-level drive circuit 320 to receive a clock signal and a data signal.
  • the data signal includes at least display data, the ID of each level of the drive circuit 320, and the parameter value N.
  • the data signal is decoded with the cooperation of the clock signal, and then the display data required by the driving circuit 320 of the current level is sent to the driving unit 321.
  • the communication unit 324 further transmits the control signal including the data signal to the communication unit of the driving circuit 320 at the next stage.
  • the communication unit 324 provides the parameter value N obtained by decoding the data signal and the ID assigned to the driving circuit 320 of the current stage to the comparison and selection unit 323 of the driving circuit 320 of the current stage.
  • the comparator 3231 of the comparison selection unit 323 is connected to the communication unit 324 to receive the decoded ID of the driving circuit 320 of the current level and the parameter value N set by the control card 310, and output the comparison between the ID of the driving circuit 320 of the current level and the parameter value N result.
  • the first input terminal of the selector 3232 of the comparison selection unit 323 is connected to the inverter 322, the second input terminal receives the clock signal, the control terminal of the selector 3232 is connected to the output terminal of the comparator 3231 to receive the comparison result, and the selector 3232
  • the output end of the driver circuit 320 of the next stage provides the clock signal inverted by the inverter 322 or the clock signal received by the driver circuit 320 of the current stage as the clock signal received by the driver circuit 320 of the next stage.
  • the selector 3232 outputs the inverted clock signal, otherwise, the received clock signal is provided to the next stage.
  • each stage of the drive circuit 320 performs inversion processing on the received clock signal to obtain the inverted clock signal, and compares the received clock signal according to the comparison result of its own ID and the parameter value N Or the inverted clock signal is provided to the next-stage drive circuit 320, where each time the clock signal passes through the N-stage drive circuit, an inverted clock signal is provided to the next stage.
  • the parameter value N can be selected according to the actual circuit
  • the attenuation rate of the clock signal is determined by the attenuation rate of the clock signal, and the value of the parameter value N is determined by the control card 310. It is not an immutable fixed value and can be flexibly adjusted to be suitable for a variety of application environments.
  • FIG. 4 shows a schematic diagram of the working principle of the driving circuit in the LED display system according to the second embodiment of the present invention.
  • the control card sets the parameter value N and configures an ID for each level of drive circuit.
  • N is a positive integer.
  • the inverter of each level of drive circuit outputs an inverted clock signal.
  • the inverter 322 of the driving circuit 320 of this stage performs inversion processing on the received time signal to obtain an inverted clock signal.
  • the inverter 322 can select a simple logic element NOT gate.
  • S03 Compare the ID of the drive circuit with the size of the parameter value N.
  • the comparator 3231 receives the ID and the parameter value N decoded by the communication unit 324.
  • the communication unit 324 implements decoding by, for example, setting a decoder.
  • S04 Determine whether the ID of the drive circuit is equal to the parameter value N or an integer multiple of the parameter value N. The above scheme is executed by the comparator 3231.
  • the inverted clock signal is provided to the next-stage drive circuit.
  • the comparison result of the comparator 3231 is that the ID of the driving circuit is equal to the parameter value N or an integer multiple of the parameter value N, and the selector 3232 provides the inverted clock signal of the inverter 322 to the next-stage driving circuit 320.
  • ID configuration scheme 1 it is judged whether ID is equal to an integer multiple of parameter value N; according to ID configuration scheme 2, it is judged whether ID is equal to parameter value N.
  • the LED display system of the embodiment of the present invention can effectively avoid the continuous attenuation of the clock signal.
  • the 50% duty cycle of the clock signal passes through the one-stage or multi-stage driving circuit and the duty cycle attenuates to 40%.
  • the clock signal with 40% duty cycle is inverted, the high and low levels are reversed, and the duty cycle becomes 60%, avoiding excessive attenuation of the duty cycle, and ensuring effective data sampling based on the clock signal.
  • To ensure that the system correctly reads the digital signal guarantees the display effect of the LED display, and solves the attenuation problem.
  • the LED display system of this embodiment is equipped with a comparison selection unit and an inverter for each level of driving circuit.
  • the comparison selection unit and the inverter can also be connected in the cascaded driving circuit. Interval setting to reduce hardware cost.
  • the interval can be reasonably designed according to the attenuation rate.
  • a comparison selection unit and inverter are set with a drive circuit with one or ten levels of attenuation. The lower the attenuation rate of the system, the The interval can be larger, and the design of the smaller interval is suitable for the system with high attenuation rate and also for the system with low attenuation rate.
  • the present application also provides a control method, which is applied to the above-mentioned display system.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Control Of El Displays (AREA)
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Abstract

一种LED显示***及其控制方法，显示***包括：控制卡（110），输出多路时钟信号和数据信号；至少一个驱动电路组，与控制卡（110）连接，每个驱动电路组包括多个级联的驱动电路（220），每个驱动电路组接收一路时钟信号和数据信号并在多个驱动电路（220）中传输，每个驱动电路组中的至少一个驱动电路（220）包括反相器（222），反相器（222）对本级驱动电路（220）接收的时钟信号进行反相处理以得到反相后的时钟信号。该LED显示***能够有效避免时钟信号在级联的驱动电路中过度衰减，保障以该时钟信号为采样基础的数据采样的正确性，确保LED显示屏的显示效果。

Description

LED显示***及其控制方法
本申请要求了申请日为2020年6月24日、申请号为202010587425.2、名称为“LED显示***及其控制方法”的中国发明申请的优先权，并且通过参照上述中国发明申请的全部说明书、权利要求、附图和摘要的方式，将其引用于本申请。
技术领域
本发明涉及显示技术领域，特别涉及一种LED显示屏的显示***及其控制方法。
背景技术
传统的LED(Light Emitting Diode，发光二极管)显示***如图1所示，LED显示***100通常包括控制卡110和多个驱动电路120。控制卡110提供多路信号，每一路信号控制相应的多个依次串接的驱动电路120。随着***中串接的驱动电路120的数量的增加，控制卡110提供的信号会因负载的增加而逐渐衰减，其中在传输过程中，时钟信号的衰减尤其明显。
时钟信号是一种在高电平和低电平之间来回切换的信号。当时钟信号衰减时，时钟信号的占空比将会发生变化。如果作为数据采样基础的时钟信号一直衰减，最后将导致其他数字信号无法被正确读取，影响LED显示屏的显示效果。
发明内容
鉴于上述问题，本发明的目的在于提供一种LED显示***及其控制方法，从而避免时钟信号的过度衰减，保障LED显示屏的显示效果。
根据本发明的一方面，提供一种LED显示***，包括：控制卡，输出多路时钟信号和数据信号；至少一个驱动电路组，与所述控制卡连接， 每个驱动电路组包括多个级联的驱动电路，每个所述驱动电路组接收一路所述时钟信号和所述数据信号并在所述多个驱动电路中传输，每个驱动电路组中的至少一个驱动电路包括反相器，所述反相器对本级驱动电路接收的时钟信号进行反相处理以得到反相后的时钟信号。
可选地，每个所述驱动电路还包括：通信单元，连接所述控制卡或者上一级驱动电路以接收所述时钟信号和所述数据信号，根据所述时钟信号对所述数据信号进行解码，并传输数据信号至下一级驱动电路。
可选地，所述至少一个驱动电路组的每个所述驱动电路包括所述反相器。
可选地，所述数据信号包含显示数据、参数值和驱动电路的ID。
可选地，每个所述驱动电路还包括：比较选择单元，连接所述通信单元接收解码后的数据信号，根据驱动电路的ID和参数值，选择将所述反相后的时钟信号或者本级驱动电路接收的时钟信号提供至下一级驱动电路，参数值为正整数。
可选地，所述比较选择单元包括：比较器，连接所述通信单元以接收参数值和本级驱动电路的ID，并提供所述参数值和驱动电路的ID的比较结果；选择器，第一输入端连接反相器接收所述反相后的时钟信号，第二输入端接收本级驱动电路的时钟信号，控制端连接比较器的输出端接收比较结果，输出端向下一级驱动电路输出反相后的时钟信号或者本级驱动电路的时钟信号。
可选地，每组驱动电路组中的驱动电路的ID依次为1、2、3…X或1～N的循环，其中，X为正整数，N为所述参数值。
可选地，所述比较器的比较结果为所述驱动电路的ID与参数值或者参数值的整数倍相等时，所述选择器将反相后的时钟信号作为下一级驱动电路的时钟信号；所述比较器的比较结果为所述驱动电路的ID不等于参数值或参数值的整数倍时，所述选择器将本级驱动电路的时钟信号作为下一级驱动电路的时钟信号。
可选地，所述通信单元包含解码器。
可选地，所述反相器为非门。
可选地，每个所述驱动电路还包括：驱动单元，连接所述通信单元以接收解码后的显示数据。
根据本发明的一方面，提供一种显示***的控制方法，包括：提供多路时钟信号和数据信号；每个驱动电路组接收一路所述时钟信号和所述数据信号并在多个驱动电路中传输，每个驱动电路组中的至少一个驱动电路对本级驱动电路接收的时钟信号进行反相处理以得到反相后的时钟信号，其中，每个驱动电路组包括多个级联的驱动电路。
可选地，还包括：每个所述驱动电路根据接收的所述时钟信号对所述数据信号进行解码，并传输数据信号至下一级驱动电路。
可选地，每个驱动电路组中的每个驱动电路对本级驱动电路接收的时钟信号进行反相处理以得到反相后的时钟信号。
可选地，所述数据信号包含显示数据、参数值和驱动电路的ID。
可选地，还包括：每个驱动电路根据驱动电路的ID和参数值，选择将所述反相后的时钟信号或者本级驱动电路接收的时钟信号提供至下一级驱动电路，参数值为正整数。
可选地，每组驱动电路组中的驱动电路的ID可以依次为1、2、3…X或1～N的循环，其中，X为正整数，N为所述参数值。
可选地，所述驱动电路的ID与参数值或者参数值的整数倍相等时，将反相后的时钟信号作为下一级驱动电路的时钟信号；所述驱动电路的ID不等于参数值或参数值的整数倍时，将本级驱动电路的时钟信号作为下一级驱动电路的时钟信号。
本发明提供的LED显示***通过在每组级联的多个驱动电路中的至少一个驱动电路中设置反相器，以将时钟信号反相处理并向下一级驱动电路提供反相后的时钟信号。本实施例通过简单的硬件设计，能够有效避免时钟信号在级联的驱动电路中过度衰减，保障以该时钟信号为采样基础的数据采样的正确性，确保LED显示屏的显示效果。
优选地，在每个驱动电路中皆增设反相器以对本级时钟信号进行反相处理以得到反相后的时钟信号并提供至下一级驱动电路，既能有效避免时钟信号在级联的驱动电路中过度衰减，还可以提升驱动电路的可设 计性，提升LED显示***的灵活性。进一步地，在每个驱动电路中还设置有比较选择单元，每个驱动电路的比较选择单元基于控制卡提供的参数值和每个驱动电路的ID，将本级驱动电路的时钟信号或者经反相器处理后得到的反相后的时钟信号提供至下一级驱动电路，使得在LED显示***中，每经由设定参数值的驱动电路传输后向下一级驱动电路提供反相后的时钟信号，而向其余级的驱动电路提供上一级驱动电路的时钟信号。上述设定的参数值可以根据实际电路的时钟信号衰减率来灵活调控，以适用于多种应用环境。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了根据现有技术的LED显示***的结构框图；
图2示出了根据本发明第一实施例的LED显示***的结构框图；
图3示出了根据本发明第二实施例的LED显示***的结构示意图；
图4示出了根据本发明第二实施例的LED显示***中驱动电路的工作原理示意图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。
图2示出了根据本发明第一实施例的LED显示***的结构框图。
如图2所示，LED显示***200包括控制卡110、分别与控制卡110连接的多个驱动电路组，每个驱动电路组包括多个级联的驱动电路220。LED显示***200还包括与驱动电路220连接的多个LED灯组，其中，多个灯组构成LED显示屏。控制卡110提供多路控制信号，每一路控制 信号控制相应的多个级联的驱动电路220，每一路控制信号中包括用于驱动LED灯组的数据信号和用于指示时序逻辑的时钟信号，数据信号至少包含显示数据。
至少一个驱动电路220包括驱动单元221、反相器222、通信单元223。
通信单元223连接控制卡110或者上一级驱动电路220，以接收时钟信号和数据信号，并在时钟信号的配合下对数据信号进行解码，然后将本级驱动电路220所需的显示数据发送至驱动单元221。通信单元324将数据信号进一步传送至下一级驱动电路220的通信单元。反相器223连接控制卡110或者上一级驱动电路220以接收时钟信号，并对接收的时钟信号做反相处理得到反相后的时钟信号以提供至下一级驱动电路220。
其中，LED显示***200中包括至少一个设置有反相器222的驱动电路220，该驱动电路220可以为LED显示***200中的任一级驱动电路。进一步地，LED显示***200中其余未具备反相处理能力的驱动电路中仅包含通信单元223和驱动单元222，其中，通信单元223连接控制卡110或者上一级驱动电路以接收时钟信号和数据信号并将时钟信号和数据信号传输至下一级驱动电路，并在时钟信号的配合下对数据信号进行解码，然后将本级驱动电路所需的显示数据发送至驱动单元221。
优选地，如图2所示，LED显示***200中的每级驱动电路均为具有反相处理能力的驱动电路220。
上述LED显示***200可以有效避免时钟信号在多个级联的驱动电路中持续衰减，例如，当50％占空比的时钟信号经过一级或者多级驱动电路后占空比衰减至40％，在此时对占空比为40％的时钟信号进行反相处理，高低电平反转，其占空比变为60％，规避占空比的过度衰减，确保以该时钟信号为数据采样基础的数据采样能够准确采样，确保LED显示***正确读取数据信号，解决了衰减问题，保障LED显示屏的显示效果。本实施例的驱动电路中使用较少的硬件实现高效的衰减处理，节约成本。
图3示出了根据本发明第二实施例的LED显示***的结构示意图。
如图3所示，LED显示***300包括控制卡310、分别与控制卡310连接的多个驱动电路组，每个驱动电路组包括多个级联的驱动电路320。LED显示***300还包括与驱动电路320连接的多个LED灯组，其中，多个灯组构成LED显示屏。相较于LED显示***200中至少一级驱动电路将接收的时钟信号做反相处理，并将反相后的时钟信号输出至下一级驱动电路，本实施例的LED显示***300中，每个驱动电路组中的每个驱动电路320将接收的时钟信号进行反相处理并选择将接收的时钟信号或者反相后的时钟信号作为下一级驱动电路320所接收的时钟信号，具体地，在时钟信号经由设定参数值个驱动电路320传输后将反相后的时钟信号作为下一级驱动电路320接收的时钟信号。
控制卡310提供多路控制信号，每一路控制信号控制每个驱动电路组中多个级联的驱动电路320。每一路控制信号中包括用于驱动LED灯组的数据信号和用于指示时序逻辑的时钟信号。控制卡310设定参数值N以及为每一级驱动电路320配置一个ID(Identity document，身份标识号)。参数值N决定了驱动电路的ID为N或者N的倍数时，输出反相后的时钟信号作为下一级驱动电路接收的时钟信号，其中，参数值N为正整数。进一步地，驱动电路320的ID用于指示驱动电路320位于LED显示***中的相对位置，例如，驱动电路320在接收某一路由控制卡310输出的控制信号的驱动电路组中位于第三级时，控制卡310为其分配的ID为3。
驱动电路320中包括驱动单元321、反相器322、通信单元324、以及比较选择单元323。比较选择单元323包括比较器3231、选择器3232。
反相器322连接控制卡310或者上一级驱动电路320以接收时钟信号，并对接收的时钟信号做反相处理得到反相后的时钟信号。
通信单元324连接控制卡310或者上一级驱动电路320，以接收时钟信号和数据信号，数据信号至少包含显示数据、各级驱动电路320的ID以及参数值N。并在时钟信号的配合下对数据信号进行解码，然后将 本级驱动电路320所需的显示数据发送至驱动单元321。通信单元324将包含数据信号的控制信号进一步传送至下一级驱动电路320的通信单元。通信单元324将解码数据信号得到的参数值N以及分配至本级驱动电路320的ID提供至本级驱动电路320的比较选择单元323中。
比较选择单元323的比较器3231连接通信单元324以接收解码得到的本级驱动电路320的ID和控制卡310设定的参数值N，并输出本级驱动电路320的ID与参数值N的比较结果。
比较选择单元323的选择器3232的第一输入端连接反相器322，第二输入端接收时钟信号，选择器3232的控制端连接比较器3231的输出端以接收比较结果，并由选择器3232的输出端向下一级驱动电路320提供经由反相器322反相后的时钟信号或者由本级驱动电路320接收的时钟信号作为下一级驱动电路320接收的时钟信号。其中，比较结果指示驱动电路320的ID为参数值N或者参数值N的倍数时，选择器3232输出反相后的时钟信号，否则将接收的时钟信号提供至下一级。
本实施例的LED显示***300中，每一级驱动电路320对接收的时钟信号进行反相处理得到反相后的时钟信号，并根据自身的ID和参数值N的比较结果将接收的时钟信号或反相后的时钟信号提供至下一级驱动电路320，其中，时钟信号每经过N级驱动电路后向下一级提供一个反相后的时钟信号，参数值N的取值可以根据实际电路的时钟信号衰减率来确定，并且参数值N的取值由控制卡310确定，并非为不可变的固定值，可以灵活调控，以适用于多种应用环境。
具体地，图4示出了根据本发明第二实施例的LED显示***中驱动电路的工作原理示意图。
如图4所示，包括如下步骤，需要说明的是，驱动电路的工作原理以流程图的方式描述，此行为仅为更详细的阐述本实施例。
S01：控制卡设定参数值N且为每级驱动电路配置一个ID。N为正整数。驱动电路的ID配置方案包括两种，方案一：假设控制卡310每一路信号提供至由X个驱动电路级联组成的驱动电路组，则为每组驱动电路组中的每一级驱动电路320依次配置ID为1、2、3…X；方案二： 假设控制卡310每一路信号提供至由X个驱动电路级联组成的驱动电路组，则为每组驱动电路组中的每一级驱动电路320依次循环配置ID为1～N。其中，X为正整数。
S02：每级驱动电路的反相器输出反相后的时钟信号。本级驱动电路320的反相器322将接收的时信号做反相处理以得到反相后的时钟信号。反相器322可以选择简单逻辑元件非门。
S03：比较驱动电路的ID与参数值N的大小。比较器3231接收由通信单元324解码得到的ID和参数值N。其中，通信单元324例如采用设置解码器的方式实现解码。
S04：判断驱动电路的ID是否等于参数值N或等于参数值N的整数倍。通过比较器3231执行上述方案。
S05：如果驱动电路的ID等于参数值N或等于参数值N的整数倍，则将反相后的时钟信号提供至下一级驱动电路。比较器3231的比较结果为驱动电路的ID等于参数值N或等于参数值N的整数倍，则选择器3232将反相器322反相后的时钟信号提供至下一级驱动电路320。
S06：如果驱动电路的ID不等于参数值N也不等于参数值N的整数倍，则将本级接收的时钟信号提供至下一级驱动电路。比较器3231的比较结果为ID不等于参数值N也不等于参数值N的整数倍，选择器3232将本级驱动电路320接收的时钟信号直接提供至下一级驱动电路320。
按照ID配置方案一，判断ID是否等于参数值N的整数倍；按照ID配置方案二，判断ID是否等于参数值N。
本发明实施例的LED显示***可以有效的避免时钟信号的持续衰减，例如，50％占空比的时钟信号经过一级或者多级驱动电路后占空比衰减至40％，在此时对该40％占空比的时钟信号进行反相处理，高低电平反转，其占空比变为60％，规避占空比的过度衰减，确保以该时钟信号为数据采样基础的数据采样有效工作，确保***正确读取数字信号，保障LED显示屏的显示效果，解决衰减问题。
本实施例的LED显示***对每一级驱动电路都设置了比较选择单 元和反相器，在实际设备中，驱动电路级数很多，比较选择单元和反相器还可以在级联的驱动电路中间隔设置，以降低硬件成本，同时，还可以根据衰减率合理设计间隔，例如间隔一级或十级等数量的驱动电路设置一个比较选择单元和反相器，衰减率越低的***，其间隔可以越大，间隔小的设计适用于衰减率高的***同时也可以适用于衰减率低的***。
本申请还提供一种控制方法，应用于上述显示***中。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (18)

  1. 一种LED显示***，其特征在于，包括：
    控制卡，输出多路时钟信号和数据信号；
    至少一个驱动电路组，与所述控制卡连接，每个驱动电路组包括多个级联的驱动电路，每个所述驱动电路组接收一路所述时钟信号和所述数据信号并在所述多个驱动电路中传输，每个驱动电路组中的至少一个驱动电路包括反相器，所述反相器对本级驱动电路接收的时钟信号进行反相处理以得到反相后的时钟信号。
  2. 根据权利要求1所述的LED显示***，其特征在于，每个所述驱动电路还包括：
    通信单元，连接所述控制卡或者上一级驱动电路以接收所述时钟信号和所述数据信号，根据所述时钟信号对所述数据信号进行解码，并传输数据信号至下一级驱动电路。
  3. 根据权利要求2所述的LED显示***，其特征在于，所述至少一个驱动电路组的每个所述驱动电路包括所述反相器。
  4. 根据权利要求2所述的LED显示***，其特征在于，所述数据信号包含显示数据、参数值和驱动电路的ID。
  5. 根据权利要求4所述的LED显示***，其特征在于，每个所述驱动电路还包括：
    比较选择单元，连接所述通信单元接收解码后的数据信号，根据驱动电路的ID和参数值，选择将所述反相后的时钟信号或者本级驱动电路接收的时钟信号提供至下一级驱动电路，参数值为正整数。
  6. 根据权利要求5所述的LED显示***，其特征在于，所述比较选择单元包括：
    比较器，连接所述通信单元以接收参数值和本级驱动电路的ID，并提供所述参数值和驱动电路的ID的比较结果；
    选择器，第一输入端连接反相器接收所述反相后的时钟信号，第二输入端接收本级驱动电路的时钟信号，控制端连接比较器的输出端接收 比较结果，输出端向下一级驱动电路输出反相后的时钟信号或者本级驱动电路的时钟信号。
  7. 根据权利要求4所述的LED显示***，其特征在于，每组驱动电路组中的驱动电路的ID依次为1、2、3…X或1～N的循环，其中，X为正整数，N为所述参数值。
  8. 根据权利要求6所述的LED显示***，其特征在于，所述比较器的比较结果为所述驱动电路的ID与参数值或者参数值的整数倍相等时，所述选择器将反相后的时钟信号作为下一级驱动电路的时钟信号；所述比较器的比较结果为所述驱动电路的ID不等于参数值或参数值的整数倍时，所述选择器将本级驱动电路的时钟信号作为下一级驱动电路的时钟信号。
  9. 根据权利要求2所述的LED显示***，其特征在于，所述通信单元包含解码器。
  10. 根据权利要求1所述的LED显示***，其特征在于，所述反相器为非门。
  11. 根据权利要求2所述的LED显示***，其特征在于，每个所述驱动电路还包括：
    驱动单元，连接所述通信单元以接收解码后的显示数据。
  12. 一种显示***的控制方法，其特征在于，包括：
    提供多路时钟信号和数据信号；
    每个驱动电路组接收一路所述时钟信号和所述数据信号并在多个驱动电路中传输，每个驱动电路组中的至少一个驱动电路对本级驱动电路接收的时钟信号进行反相处理以得到反相后的时钟信号，
    其中，每个驱动电路组包括多个级联的驱动电路。
  13. 根据权利要求12所述的控制方法，其特征在于，还包括：
    每个所述驱动电路根据接收的所述时钟信号对所述数据信号进行解码，并传输数据信号至下一级驱动电路。
  14. 根据权利要求13所述的控制方法，其特征在于，每个驱动电路组中的每个驱动电路对本级驱动电路接收的时钟信号进行反相处理以得 到反相后的时钟信号。
  15. 根据权利要求13所述的控制方法，其特征在于，所述数据信号包含显示数据、参数值和驱动电路的ID。
  16. 根据权利要求15所述的控制方法，其特征在于，还包括：
    每个驱动电路根据驱动电路的ID和参数值，选择将所述反相后的时钟信号或者本级驱动电路接收的时钟信号提供至下一级驱动电路，参数值为正整数。
  17. 根据权利要求15所述的控制方法，其特征在于，每组驱动电路组中的驱动电路的ID可以依次为1、2、3…X或1～N的循环，其中，X为正整数，N为所述参数值。
  18. 根据权利要求16所述的控制方法，其特征在于，所述驱动电路的ID与参数值或者参数值的整数倍相等时，将反相后的时钟信号作为下一级驱动电路的时钟信号；所述驱动电路的ID不等于参数值或参数值的整数倍时，将本级驱动电路的时钟信号作为下一级驱动电路的时钟信号。
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