WO2021254062A1 - 过流保护电路、显示装置及其驱动电路、过流保护方法 - Google Patents

过流保护电路、显示装置及其驱动电路、过流保护方法 Download PDF

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Publication number
WO2021254062A1
WO2021254062A1 PCT/CN2021/094150 CN2021094150W WO2021254062A1 WO 2021254062 A1 WO2021254062 A1 WO 2021254062A1 CN 2021094150 W CN2021094150 W CN 2021094150W WO 2021254062 A1 WO2021254062 A1 WO 2021254062A1
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Prior art keywords
signal
circuit
gate input
output
gate
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PCT/CN2021/094150
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English (en)
French (fr)
Inventor
袁先锋
***
刘晓石
许俊波
王睿
刘媛媛
乔玄玄
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/781,288 priority Critical patent/US11875713B2/en
Publication of WO2021254062A1 publication Critical patent/WO2021254062A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/86—Generating pulses by means of delay lines and not covered by the preceding subgroups

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an overcurrent protection circuit, a drive circuit of a display device, a display device, and an overcurrent protection method.
  • the function of the timing controller is to receive the display signal input by the system board, process the display signal, and generate the working timing of the source drive circuit and the gate drive circuit, so that the source drive circuit and the gate drive
  • the circuit drives the display panel to display according to the received signal.
  • the display signal is abnormal, the working sequence of the source drive circuit and the gate drive circuit generated by the timing controller according to the display signal will also be abnormal, thereby affecting The normal display of the display device will cause damage to the display panel.
  • an overcurrent protection circuit configured to continuously detect a plurality of gate input signals input to a gate drive circuit; the overcurrent protection circuit includes: a sampling sub-circuit, Delay judgment sub-circuit and counting control sub-circuit.
  • the sampling sub-circuit is configured to obtain the plurality of gate input signals, and filter out a gate input signal of the plurality of gate input signals whose voltage value is greater than a first preset voltage value, as a sampling gate Input signal; and, generating and outputting a first control signal according to the sampling gate input signal; wherein, the first preset voltage value is the threshold voltage value of the voltage normal state and the overcurrent state of the gate input signal.
  • the delay judging sub-circuit is coupled to the sampling sub-circuit, and the delay judging sub-circuit is configured to receive the first control signal output by the sampling sub-circuit, and perform a first preset on the first control signal With the time delay, it is judged whether the voltage value of the first control signal after the delay has decreased compared with that before the delay, and if not, the counting signal is output.
  • the counting control sub-circuit is coupled to the delay judging sub-circuit, and the counting control sub-circuit is configured to receive the counting signal output by the delay judging sub-circuit, and perform counting according to the counting signal; When the preset number of times is reached, the second control signal is output, and the second control signal is used to cut off the signal input of the system board of the display device to the drive circuit of the display device.
  • the sampling sub-circuit includes: a signal screening unit; the signal screening unit is configured to receive the plurality of gate input signals, and filter out that the voltage value of the plurality of gate input signals is greater than all the gate input signals.
  • a gate input signal of the first preset voltage value is used as a sampling gate input signal.
  • the sampling sub-circuit further includes: a signal processing unit coupled to the signal filtering unit; the signal processing unit is configured to receive the sampling gate input signal output by the signal filtering unit, The sampling gate input signal is subjected to interference removal and amplification processing, a first control signal is generated according to the sampling gate input signal subjected to the interference removal and amplification processing and a second preset voltage value, and the first control signal is output; wherein , The second preset voltage value is related to the magnification factor for performing interference removal and amplifying processing on the sampling gate input signal.
  • the signal processing unit includes: a noise reduction subunit, an amplification subunit, and a comparison subunit.
  • the noise reduction subunit is configured to receive the sampling gate input signal output by the signal filtering unit, perform interference removal processing on the sampling gate input signal, and output the sampling gate input signal subjected to the interference removal processing.
  • the amplifying subunit is coupled to the noise reduction subunit, and the amplifying subunit is configured to receive the de-interference processed sampling gate input signal output by the noise reduction sub-unit, and perform sampling on the de-interference processed sample
  • the gate input signal is amplified, and the sampling gate input signal after interference removal and amplification is output.
  • the comparing subunit is coupled to the amplifying subunit, and the comparing subunit is configured to receive the de-interference and amplifying processing sampling gate input signal output by the amplifying subunit, and according to the de-interference and amplifying processing
  • the sampling gate input signal and the second preset voltage value generate a first control signal, and output the first control signal.
  • the signal screening unit is configured to receive the plurality of gate input signals, filter out the gate input signal with the largest voltage value among the plurality of gate input signals, and filter the selected gate input signal The voltage value of the gate input signal is compared with the first preset voltage value; in the case where the voltage value of the gate input signal filtered out is greater than the first preset voltage value, the gate input signal is used as Sampling the gate input signal.
  • the number of the plurality of gate input signals is x
  • the signal screening unit 2511 includes an n-level filter group
  • the i-th level filter group includes 2 (ni) filters; where x Is a positive integer greater than or equal to 3, n is a positive integer greater than or equal to 2, and i takes values in sequence within the set of positive integers [1, n].
  • a filter has two input terminals and one output terminal; the two input terminals of one filter in the (i+1)-th level filter group and the output terminals of the two filters in the i-th level filter group are respectively Coupling.
  • the first-stage filter group is configured to obtain the plurality of gate input signals, and each filter in the first-stage filter group is configured to receive two gate input signals of the plurality of gate input signals , And output the gate input signal with the larger voltage value among the two received gate input signals.
  • the i+1 level filter group is configured to receive the gate input signal output by the i level filter group, and each filter in the i+1 level filter group is configured to receive the i level filter Two of the gate input signals output by the device group are output, and one of the two received gate input signals has a larger voltage value.
  • the filters in the n-th stage filter group are configured to receive the two gate input signals output by the n-1 stage filter group, and filter out the gate input with the larger voltage value among the two gate input signals Signal and compare the filtered voltage value of the gate input signal with the first preset voltage value, and if the voltage value of the gate input signal is greater than the first preset voltage value, the The gate input signal is used as the sampling gate input signal.
  • the signal screening unit further includes a switch control subunit.
  • the switch control subunit is coupled to the first-level filter group, and is configured to control the opening or closing of each filter in the first-level filter group.
  • the delay judgment sub-circuit includes: a delay unit and a judgment unit.
  • the delay unit is configured to receive the first control signal output by the sampling sub-circuit, delay the first control signal for a first preset time, and output the delayed first control signal.
  • the judging unit is coupled to the delay unit, and the judging unit is configured to receive the first control signal output by the sampling sub-circuit and the delayed first control signal output by the delay unit to determine the delay Whether the voltage value of the first control signal before and after the delay is equal, if so, output the counting signal.
  • the first preset time is 3 ⁇ s to 5 ⁇ s.
  • the counting control sub-circuit is further configured to determine whether the counting number has increased within a second preset time after the counting number does not reach the preset number of times, if If not, clear the number of counts.
  • the overcurrent protection circuit detects multiple gate input signals once in each clock cycle under the control of the detection timing signal; the second preset time is one clock cycle .
  • the counting control sub-circuit is further configured to output a third control signal when the counting number reaches a preset number, and the third control signal is used to cut off the signal source to the system The signal input of the board.
  • the counting control sub-circuit includes: a counting unit and a control unit.
  • the counting unit is configured to receive the counting signal output by the delay judging sub-circuit, and perform counting according to the counting signal.
  • the control unit is coupled to the counting unit, and the control unit is configured to store count times, and output a second control signal when the count times reach the preset times.
  • a driving circuit of a display device includes: a power supply circuit, a timing controller, and the above-mentioned overcurrent protection circuit.
  • the power supply circuit is coupled to the system board of the display device, the timing controller, and the overcurrent protection circuit, and the power supply circuit is configured to receive the power signal input by the system board, and according to the power signal Provide electrical energy for the timing controller and the overcurrent protection circuit.
  • the timing controller is also coupled to the system board, and the timing controller is configured to receive a display signal input from the system board, and generate a signal input to the gate drive circuit of the display device according to the display signal. A gate input signal.
  • the overcurrent protection circuit is also coupled with the timing controller.
  • the power supply circuit is further configured to receive a second control signal output by the overcurrent protection circuit, and under the control of the second control signal, stop receiving the power supply signal input by the system board.
  • the driving circuit further includes: a source driving circuit.
  • the source driving circuit is coupled to the power supply circuit and the timing controller.
  • the timing controller is further configured to generate a plurality of source input signals for input to the source driving circuit according to the display signal.
  • the source driving circuit is configured to receive the plurality of source input signals and generate data signals according to the plurality of source input signals.
  • a display device including: the above-mentioned driving circuit, a system board, and a display panel.
  • the system board is coupled to the power supply circuit and the timing controller in the drive circuit, and is configured to output a power supply signal and a display signal.
  • the display panel is coupled with the driving circuit.
  • the display panel includes a gate drive circuit, the gate drive circuit is coupled to a timing controller and a power supply circuit in the drive circuit; the gate drive circuit is configured to receive the timing controller output According to the plurality of gate input signals, a gate scan signal is generated and output.
  • the system board is also coupled to the overcurrent protection circuit in the driving circuit.
  • the system board is further configured to receive the third control signal, and under the control of the third control signal, stop receiving the video signal input by the video signal source.
  • an overcurrent protection method is provided, which is applied to the display device as described above, and the overcurrent protection method includes: a system board of the display device outputs a power signal and a display signal to a drive circuit of the display device.
  • the power circuit in the drive circuit receives the power signal, and provides electrical energy to the timing controller and the overcurrent protection circuit in the drive circuit according to the power signal.
  • the timing controller receives the display signal, and generates a plurality of gate input signals for input to the gate driving circuit of the display device according to the display signal.
  • the overcurrent protection circuit acquires the plurality of gate input signals, continuously detects the plurality of gate input signals, and sends to the power supply circuit when an overcurrent occurs in the gate input signal is detected Output the second control signal.
  • the power circuit receives the second control signal, and under the control of the second control signal, stops receiving the power signal input by the system board.
  • the overcurrent protection method further includes: the overcurrent protection circuit continuously detects the plurality of gate input signals, and in the case of detecting that the gate input signals are abnormal, The system board outputs the third control signal. The system board receives the third control signal, and under the control of the third control signal, stops receiving the signal input by the signal source.
  • Fig. 1A is a timing diagram of generating CLK signal and STV signal according to DE signal with normal phase
  • Fig. 1B is a timing diagram of generating CLK signal and STV signal according to DE signal with abnormal phase
  • FIG. 2 is a structural diagram of a display device according to some embodiments.
  • Figure 3 is a structural diagram of an overcurrent protection circuit according to some embodiments.
  • 4A is a detection timing diagram of an overcurrent protection circuit according to some embodiments.
  • 4B is a detection timing diagram of an overcurrent protection circuit according to some embodiments.
  • FIG. 5A is another structural diagram of an overcurrent protection circuit according to some embodiments.
  • FIG. 5B is another structural diagram of an overcurrent protection circuit according to some embodiments.
  • Fig. 6 is a structural diagram of a sampling sub-circuit in an over-current protection circuit according to some embodiments.
  • FIG. 7 is another structural diagram of an overcurrent protection circuit according to some embodiments.
  • Fig. 8A is a structural diagram of a sampling and screening unit according to some embodiments.
  • Fig. 8B is another structural diagram of a sampling and screening unit according to some embodiments.
  • Figure 9 is a structural diagram of a judging unit according to some embodiments.
  • Fig. 10A is a flowchart of an overcurrent protection method according to some embodiments.
  • FIG. 10B is another flowchart of an overcurrent protection method according to some embodiments.
  • Fig. 11 is still another flowchart of an overcurrent protection method according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • the term “if” is optionally interpreted to mean “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • the display device 100 includes: a system board 1, a driving circuit 2 and a display panel 3.
  • the system board 1 is coupled to the driving circuit 2 and is configured to output a power signal c2 and a display signal c1 to the driving circuit 2 to control the display panel 3 through the driving circuit 2 to realize display.
  • the system board 1 is coupled to the video signal source 1', receives the video signal c7 output by the video signal source 1', and generates the power signal c2 and the display signal c1 according to the received video signal c7.
  • the display panel 3 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of sub-pixels P.
  • the plurality of sub-pixels P are arranged in the display area of the display panel 3.
  • the plurality of sub-pixels P are arrayed. Arrangement, each sub-pixel P is provided with a pixel driving circuit 2, the sub-pixels P arranged in a row along the row direction are coupled to the same gate line GL, and the sub-pixels P arranged in a column along the column direction are coupled to the same data line DL .
  • the above-mentioned driving circuit 2 includes: a power supply circuit 21, a timing controller 22 and a source driving circuit 23.
  • the power circuit 21 is coupled to the system board 1 of the display device 100 and the timing controller 22.
  • the power circuit 21 is configured to receive the power signal c2 input by the system board 1, and provide power to the timing controller 22 according to the power signal c2.
  • the power supply circuit 21 generates the power supply voltage required for the operation of the timing controller 22 according to the received power signal c2, and then transmits the corresponding power supply voltage to the timing controller 22.
  • the timing controller 22 is also coupled to the gate driving circuit 31 and the source driving circuit 23.
  • the timing controller 22 is configured to receive the display signal c1 input by the system board 1, and generate the display signal c1 for input to the display device 100 according to the display signal c1.
  • a plurality of gates of the gate driving circuit 31 input signals c3.
  • the timing controller 22 is also configured to generate a plurality of source input signals c4 for input to the source driving circuit 23 according to the display signal c1.
  • the gate driving circuit 31 is coupled to the power supply circuit 21 and the timing controller 22, and is configured to receive a plurality of gate input signals c3, and generate a gate scan signal according to the plurality of gate input signals c3.
  • the source driving circuit 23 is coupled to the power supply circuit 21 and the timing controller 22, and is configured to receive the plurality of source input signals c4 and generate data signals according to the plurality of source input signals c4.
  • the display signal c1 from the system board 1 received by the timing controller 22 is an LVDS signal, including a DE (Data Enable) signal, an HS (Hsync, horizontal synchronization) signal, and a VS (Vsync, vertical synchronization) signal.
  • the timing controller 22 generates multiple gate input signals c3 required by the gate drive circuit 31 and multiple source input signals c4 required by the source drive circuit 23 based on these signals.
  • the multiple gate input signals c3 refer to the control signals output by the timing controller 22 to control the operation of the gate drive circuit 31, and are usually called GOA (gate on array).
  • the gate drive circuit is integrated on the array substrate.
  • the multiple gate input signals c3 include but are not limited to STV signal (Start Vertical, scan-on signal), CPV signal (Clock Pulse Vertical, gate driver clock signal), that is, CLK signal, and also include VDD signal and VSS Signal etc.
  • the above signals include more than one signal.
  • the STV signal includes STV1, STV2...STVn
  • the CLK signal includes CLK1, CLK2...CLKn
  • the VDD signal also includes VDD1, VDD2, etc., depending on the specifics of the gate drive circuit 31.
  • the structure, the number of gate input signals c3 required will also be different.
  • the multiple source input signals c4 refer to control signals output by the timing controller 22 for controlling the operation of the source drive circuit 23.
  • the multiple gate input signals c3 include but are not limited to STH (Start Horizontal, data start signal), CPH (Clock Pulse Horizontal, source driver clock signal), that is, the CLK signal, and also includes the VDD signal.
  • the gate driving circuit 31 may be bonded to the display panel 3 in the form of a gate driving IC.
  • the source driving circuit 23 may also be bonded to the display panel 3 in the form of a source driving IC.
  • the drive circuit 2 includes a gate drive circuit 31 in addition to the power supply circuit 21, the timing controller 22, and the source drive circuit 23.
  • the gate driving circuit 31 may be a GOA circuit, that is, the above-mentioned gate driving circuit 31 is directly integrated in the array substrate of the display panel 3. Based on this arrangement, the display panel 3 includes a gate line, a data line, and a plurality of sub-pixels, and further includes a gate driving circuit 31, and the driving circuit 2 does not include the gate driving circuit 31.
  • the gate driving circuit 31 has a plurality of output terminals, one output terminal is coupled to a gate line GL in the display panel 3, and the gate driving circuit 31 generates a gate scanning signal according to the gate input signal c3.
  • the gate lines GL output gate scanning signals, so that the pixel driving circuit 2 in the display panel 3 is turned on under the control of the gate scanning signals transmitted by the gate lines GL, and receives the data signals transmitted by the data lines DL, thereby realizing display.
  • the above-mentioned power supply circuit 21 is also coupled to the gate driving circuit 31, the source driving circuit 23 and the display panel 3.
  • the power supply circuit 21 is also configured to receive the power signal c2 input by the system board 1, and according to The power signal c2 provides power to the gate driving circuit 31, the source driving circuit 23, and the display panel 3.
  • the power supply circuit 21 generates the power supply voltages required by the gate driving circuit 31, the source driving circuit 23, and the display panel 3 according to the received power signal c2, and then transmits the corresponding power supply voltages to the gates respectively.
  • the driving circuit 31, the source driving circuit 23 and the display panel 3 supply power to the gate driving circuit 31, the source driving circuit 23 and the display panel 3.
  • the display signal c1 input from the system board 1 to the timing controller 22 may be abnormal, and the gate input signal c3 is generated based on the display signal c1, which will cause one of the gate input signals c3 Or the voltage (or current) of a few gate input signals c3 is greater than the voltage (or current) value in the normal state, that is, the gate input signal c3 has abnormal conditions such as overcurrent.
  • the timing controller 22 generates multiple gate input signals c3 required by the gate drive circuit 31 and multiple source input signals c4 required by the source drive circuit 23 according to the display signal c1, for example, timing control
  • the device 22 generates the STV signal and the CLK signal in the plurality of gate input signals c3 according to the DE signal.
  • the DE signal in the display signal c1 transmitted from the system board 1 to the timing controller 22 has an abnormal phase width, refer to the DE signal
  • the generated STV signal and CLK signal will have phase disturbances.
  • the DE signal maintains a normal phase width
  • the timing controller 22 generates the STV signal and the CLK signal according to the DE signal.
  • the logic of the CLK signal is: the STV signal refers to the second rising edge (rising) of the DE signal, and the STV signal generates the first rising edge at the second rising edge (rising) of the DE signal, thereby continuing a period of effective electricity flat.
  • the CLK signal refers to the first rising edge (rising) of the DE signal.
  • the CLK signal is a fixed number of 1843 pixel clocks from the first rising edge of the DE signal. Level.
  • the appearance time of the rising edge of the STV signal is earlier than the appearance time of the rising edge of the CLK signal.
  • the phase width of the DE signal is abnormal, as shown in FIG. 1B, the low-level width of the DE signal is too long, and the timing controller 22 generates the STV signal and the CLK signal according to the DE signal. The logic of the signal remains unchanged. As a result, the appearance time of the rising edge of the STV signal is relatively close to the appearance time of the rising edge of the CLK signal, resulting in a phase disorder, that is, multiple gate input signals c3 are abnormal.
  • the gate driving circuit 31 will have a MultiGate (multi-gate abnormal opening) phenomenon under the control of a plurality of abnormal gate input signals c3.
  • This MultiGate phenomenon will cause abnormal output of the gate driving circuit 31 to generate excessive current.
  • the excessive current is fed back to the gate input signal c3 through the loop formed by the connection between the driving circuit 2 and the display panel 3, resulting in an abnormal overcurrent of the gate input signal c3.
  • the display panel 3 When the output of the gate drive circuit 31 is abnormal and the MultiGate phenomenon occurs, the display panel 3 will be scanned abnormally and an abnormal display screen will appear, and the display panel 3 will display abnormally for a long time under the abnormal scanning drive, which will cause hard-to-recover damage. For example, damages such as liquid crystal polarization or TFT (Thin Film Transistor) characteristic drift occur, which reduces the service life of the display panel 3.
  • TFT Thin Film Transistor
  • the driving circuit 2 provided by some embodiments of the present disclosure further includes an overcurrent protection circuit 25, the overcurrent protection circuit 25 is coupled to the power supply circuit 21 and the timing controller 22, and the overcurrent protection circuit 25 is configured to obtain a plurality of gate input signals c3 output by the timing controller 22, and to continuously detect the plurality of gate input signals c3, and when an overcurrent occurs in the gate input signal c3 is detected ,
  • the second control signal c5 is output to the power supply circuit 21.
  • the second control signal c5 is used to cut off the signal input of the system board 1 of the display device 100 to the drive circuit 2 of the display device 100.
  • the power supply circuit 21 is also coupled to the overcurrent protection circuit 25.
  • the power supply circuit 21 is also configured to receive the second control signal c5 output by the overcurrent protection circuit 25, and under the control of the second control signal c5, stop receiving the system board 1.
  • the power supply circuit 21 is configured to provide the timing controller 22, the overcurrent protection circuit 25, the source drive circuit 23 and other devices included in the drive circuit 2, as well as the display panel 3 and the gate drive circuit 31 Once the power is cut off, the multiple devices included in the driving circuit 2 and the display panel 3 cannot operate and cannot realize their functions. Therefore, after the power supply circuit 21 receives the second control signal c5, under the control of the second control signal c5, it stops receiving the power signal c2 input by the system board 1, so that the power supply circuit 21 cannot generate the required work of each device according to the power signal c2.
  • the power supply voltage is unable to provide power to the timing controller 22, etc., so that the timing controller 22, overcurrent protection circuit 25, source drive circuit 23 and other devices included in the drive circuit 2 all stop working, for example, the timing controller 22 stops working.
  • the gate input signal c3 is output to the gate drive circuit 31, and the input of the source input signal c4 to the source drive circuit 23 is stopped.
  • the display device 100 provided by some embodiments of the present disclosure includes a system board 1, a driving circuit 2 and a display panel 3.
  • the driving circuit 2 is provided with an overcurrent protection circuit 25.
  • the The current protection circuit 25 starts the detection process.
  • the overcurrent protection circuit 25 obtains a plurality of gate input signals c3 output by the timing controller 22, and performs processing on the plurality of gate input signals c3.
  • the power supply circuit 21 stops supplying electric energy to the timing controller 22, the gate drive circuit 31, the source drive circuit 23, and the display panel 3, so that the drive circuit 2 and the display panel 3 stop working, which is specifically represented by the timing controller 22 stopping Generate the gate input signal c3, and stop outputting the gate input signal c3 to the gate drive circuit 31, so that the abnormal gate input signal c3 can be cut off in time and will not be input to the gate drive circuit 31, avoiding abnormal gates.
  • the polar input signal c3 has an adverse effect on the gate drive circuit 31, avoiding the abnormal output of the gate drive circuit 31 and the occurrence of the MultiGate phenomenon, which in turn leads to abnormal scanning of the display panel 3 and abnormal display images, and avoids the display panel 3 from being abnormally scanned and driven Damages that are difficult to recover due to long-term display, such as damages such as liquid crystal polarization or TFT characteristic drift, can protect the display panel 3 and prolong the service life of the display panel 3.
  • the overcurrent protection circuit 25 is provided in the driving circuit 2 to continuously detect the gate input signal c3 to ensure that the gate input is caused by the abnormality of the display signal c1.
  • the over-current abnormality of the signal c3 can be detected in time, and the second control signal c5 is output at the moment the abnormality is detected, the input of the power signal c2 is cut off, and the power supply of the display device 100 is stopped, thereby protecting the display panel 3 and the whole
  • the driving circuit 2 prevents the display device 100 from continuing to operate, which may have adverse effects on the display panel 3 and the driving circuit 2.
  • the above-mentioned system board 1 is further coupled to an overcurrent protection circuit 25 in the driving circuit 2, and the above-mentioned overcurrent protection circuit 25 is further configured to continuously detect the plurality of gate input signals c3, In the case where an overcurrent of the gate input signal c3 is detected, the third control signal c6 is output to the system board 1. Wherein, the third control signal c6 is used to cut off the signal input of the signal source to the system board 1.
  • the system board 1 is also configured to receive the third control signal c6, and under the control of the third control signal c6, stop receiving the video signal c7 input by the video signal source 1'.
  • the display signal c1 output by the system board 1 to the timing controller 22 is abnormal, which causes the grid input signal c3 to be abnormal.
  • the abnormality of the display signal c1 output by the system board 1 may be caused by the video signal c7 from the video signal source 1'received by the system board 1.
  • the overcurrent protection circuit 25 detects that the gate input signal c3 has overcurrent In the case of an abnormality, the second control signal c5 is output to the power circuit 21, so that the power circuit 21 stops receiving the power signal c2 input by the system board 1, and on the basis of cutting off the power, the overcurrent protection circuit 25 also outputs a third control signal to the system board 1.
  • Control signal c6 so that the system board 1 stops receiving the video signal c7 input by the video signal source 1'under the control of the third control signal c6, so that the system board 1 can intercept the input of the original signal source at the source and improve the entire display device 100
  • the reliability of the over-current protection system can reduce the invalid drive of the system board 1, and avoid the possible abnormal source signal from causing adverse effects on the system board 1.
  • the overcurrent protection circuit 25 will be specifically introduced below.
  • some embodiments of the present disclosure provide an overcurrent protection circuit 25 configured to continuously detect a plurality of gate input signals c3 input to the gate driving circuit 31 .
  • the overcurrent protection circuit 25 detects multiple gate input signals c3 once in each clock cycle to achieve continuous detection. Measurement. For example, when the falling edge or rising edge of the detection timing signal comes, the detection is performed again in the next clock cycle T (square wave period).
  • T square wave period
  • the present disclosure starts detection when the falling edge of the detection timing signal comes. Take it as an example.
  • the over-current protection circuit 25 includes a sampling sub-circuit 251, a delay judgment sub-circuit 252, and a counting control sub-circuit 253.
  • the sampling sub-circuit 251 is configured to obtain the plurality of gate input signals c3, and filter out a gate input signal c3 of the plurality of gate input signals c3 whose voltage value is greater than a first preset voltage value, as a sample A gate input signal; and, generating and outputting a first control signal according to the sampling gate input signal.
  • the first predetermined voltage value is the threshold voltage value of the voltage normal state and the overcurrent state of the gate input signal c3.
  • the voltage normal state of the gate input signal c3 refers to the multiple gate input signals generated by the timing controller 22 according to the display signal c1 when the display signal c1 of the system board 1 input to the timing controller 22 is not abnormal.
  • c3 is a normal signal, and there will be no phase disorder, so that the gate input signal c3 will not have an overcurrent abnormality, and the voltage of the gate input signal c3 is in a normal state.
  • the voltage overcurrent state of the gate input signal c3 means that, as described above, when the system board 1 inputs the display signal c1 of the timing controller 22 to be abnormal, the timing controller 22 generates multiple gates according to the display signal c1.
  • the phase of the pole input signal c3 will be turbulent, so that the gate drive circuit 31 will have a MultiGate phenomenon under the control of the abnormal gate input signal c3. This will cause the gate drive circuit 31 to generate excessive current in abnormal output, which will lead to The voltage (or current) of one or several of the gate input signals c3 is too large, and the voltage of the gate input signal c3 is in an overcurrent state.
  • the selected gate input signal c3 is used as the sampling gate input signal.
  • a gate input signal c3 with a current value greater than a first preset current value among the plurality of gate input signals c3 can also be selected as a sampling gate input signal; wherein, the first The preset current value is the critical current value of the current normal state and the overcurrent state of the gate input signal c3.
  • the first preset current value refer to the above-mentioned explanation of the first preset voltage value. Since there is a corresponding relationship between the current and the voltage of the signal, they can be converted to each other, so by detecting the current or voltage of the gate input signal c3, it can be judged whether it is in an overcurrent abnormality.
  • the present disclosure exemplifies the voltage detection of the voltage of the gate input signal c3 as an example.
  • the first preset voltage value is a threshold that can be set according to actual conditions.
  • the abnormal gate input signal c3 will cause the gate driving circuit 31 to output abnormally and cause the MultiGate phenomenon to occur, which in turn causes the display panel 3 to appear.
  • An abnormal display screen appears due to abnormal scanning, and the display panel 3 will damage its internal structure under abnormal display for a long time. Therefore, the first preset voltage value can be set accordingly according to the size and resolution of the display panel 3.
  • the delay judgment sub-circuit 252 is coupled to the sampling sub-circuit 251.
  • the delay determination sub-circuit 252 is configured to receive the first control signal output by the sampling sub-circuit 251, delay the first control signal for a first preset time, and determine the voltage value of the delayed first control signal. Whether there is a decrease before the delay time, if not, output the counting signal.
  • the delay judging sub-circuit 252 judges whether the voltage value of the first control signal after the delay has decreased compared with that before the delay, and if so, no signal is output, and when the next clock comes, the detection of the next clock cycle is entered.
  • the gate input signal c3 may be affected by some factors, and the voltage (or current) becomes high at the moment when the sampling sub-circuit 251 is input.
  • the current is called inrush (surge) current, that is, a sudden peak current.
  • surge surge current
  • the current input to the power circuit 21 of the driving circuit 2 will have a peak value, which will cause other signals to also appear. There is a peak.
  • the peak current is much larger than the steady-state input current.
  • the following situation may occur.
  • a spike current of a certain gate input signal c3 whose voltage value is less than the first preset voltage value (the current and voltage of a signal are related)
  • its voltage value Increase to greater than the first preset voltage value, so that the gate input signal c3 is used as the sampling gate input signal, so that the selected sampling gate input signal is not a true voltage value greater than the first preset voltage value
  • the gate input signal c3 is the sampling gate input signal selected in the presence of a spike current, so the first control signal generated according to the wrong sampling gate input signal will also have inaccuracy. , Resulting in inaccurate detection results.
  • the sampling gate input signal obtained in the presence of a spike current is referred to as the wrong sampling gate input signal, and the sampling gate input signal obtained in the steady state is the correct sampling gate input signal.
  • the peak current only lasts for a short period of time. After this period of time, the peak current will drop from a higher current value (or voltage value) to the original value.
  • the delay judgment sub-circuit 252 responds to the first control signal. Do the delay processing to determine whether the voltage value of the first control signal after the delay has decreased compared with that before the delay. If the voltage value has decreased, it means that the received first control signal is based on the wrong sampling gate input signal However, the sampling gate input signal is not really in an overcurrent state, so the delay judgment sub-circuit 252 does not output a signal in this situation. If the voltage value does not drop, it means that the first control signal is generated according to the correct sampling gate input signal. The steady-state voltage value of the sampling gate input signal is greater than the first preset voltage value, so it is really over Flow status.
  • the first control signal since the first control signal is generated according to the sampling gate input signal, the first control signal can reflect the situation of the sampling gate input signal, and the first control signal is delayed and judged before and after the delay. Whether the voltage value of is decreased can tell whether the selected sampling gate input signal is accurate.
  • the first preset time may be 3 ⁇ s to 5 ⁇ s.
  • the delay judging sub-circuit 252 By setting the delay judging sub-circuit 252 to delay and judge the first control signal output by the sampling sub-circuit 251, the accuracy of the obtained first control signal can be ensured, and the sampling grid obtained in the presence of peak currents is discarded. Polar input signal, thus ensuring the accuracy of the sampling grid input signal, thereby improving the accuracy of detection.
  • the counting control sub-circuit 253 is coupled to the delay judging sub-circuit 252, and the counting control sub-circuit 253 is configured to receive the counting signal output by the delay judging sub-circuit 252 and perform counting according to the counting signal.
  • the second control signal c5 is output, and the second control signal c5 is used to cut off the signal input of the system board 1 of the display device 100 to the drive circuit 2 of the display device 100.
  • the counting control sub-circuit 253 After the delay judging sub-circuit 252 outputs the counting signal, the counting control sub-circuit 253 starts counting.
  • the counting number reaches the preset number of times, for example, the preset number is 3, it means that within three consecutive clock cycles T, At least one case where the voltage value of the gate input signal c3 is greater than the first preset voltage value is detected. In this way, it means that the gate input signal c3 has an overcurrent abnormality that lasts for at least three clock cycles T.
  • the second control signal c5 is output to cut off the signal input of the system board 1 of the display device 100 to the drive circuit 2 of the display device 100, so that the drive circuit 2 and the display panel 3 stop working and protect the gate drive circuit 31 and Display panel 3.
  • the second input signal is configured to cause the power circuit 21 to stop receiving the power signal c2 input by the system board 1 to stop supplying power to the driving circuit 2 and the display panel 3.
  • the counting control sub-circuit 253 is further configured to determine whether the counting number has increased within a second preset time after the counting number has not reached the preset number of times, if not , Then the number of counts is cleared.
  • the preset number of times is 3, if the number of counts at the current moment is 2, that is, the gate input signal c3 is detected to have an overcurrent abnormality within two consecutive clock cycles T, if in the next clock cycle The count in T does not increase, that is, there is no over-current abnormality in the gate input signal c3 in the third clock cycle T, and the count times are cleared. For example, if the duration of one clock cycle T is 50 ⁇ s, if the counting times do not meet the preset times, it is determined whether the counting times increase within 50 ⁇ s thereafter, and if not, the counting times are cleared to zero.
  • the over-current abnormality of the gate input signal c3 is detected and only lasts for one clock cycle T, it may be because the gate input signal c3 is disturbed and a temporary voltage rise or current rise occurs, rather than because The over-current abnormality caused by the abnormality of the display signal c1 (for example, the abnormal phase width of the display signal c1), if the over-current abnormality of the gate input signal c3 is detected, the second control signal c5 is directly output, which will lead to detection The result is not accurate, and unnecessary second control signal c5 is output, which affects the normal operation of the display device 100.
  • the second control signal c5 is output when the count number reaches the preset number, and the signal input from the system board 1 of the display device 100 to the drive circuit 2 of the display device 100 is cut off, that is, the gate input
  • the second control signal c5 is output, which can ensure that the current detected gate input signal c3 over-current abnormality is due to the abnormality of the display signal c1 As a result, the accuracy of the detected overcurrent abnormality of the gate input signal c3 is improved, and the unnecessary second control signal c5 is prevented from being output.
  • the over-current protection circuit 25 includes a sampling sub-circuit 251, a delay judgment sub-circuit 252, and a counting control sub-circuit 253 that are sequentially coupled.
  • the sampling sub-circuit 251, the delay judgment sub-circuit 252, and the The counting control sub-circuit 253 continuously detects the multiple gate input signals c3 input to the gate driving circuit 31, so as to realize real-time detection of the gate input signal c3, and overcurrent occurs in the gate input signal c3 In the case of an abnormality, it can be accurately detected, and when an abnormality is detected, the second control signal c5 is output, the input of the power signal c2 is cut off, and the power supply of the display device 100 is stopped, thereby protecting the display panel 3 And the entire drive circuit 2.
  • the delay judgment sub-circuit 252 discards the spike current in the gate input signal c3, and the counter control sub-circuit 253 is set to output the second control signal c5 when the preset number of times is reached, so as to prevent the gate output signal from being temporarily In the case of receiving disturbances, the wrong response is made to improve the accuracy of the detection results.
  • the sampling sub-circuit 251 includes a signal screening unit 2511.
  • the signal filtering unit 2511 is configured to receive the plurality of gate input signals c3, and filter out a gate input signal c3 of the plurality of gate input signals c3 whose voltage value is greater than a first preset voltage value, as a sampling gate Polar input signal.
  • the signal filter unit 2511 selects a gate input signal c3 whose voltage value is greater than the first preset voltage value among the plurality of gate input signals c3 as the sampling gate input signal, and the sampling The gate input signal is output as the first control signal.
  • the signal screening unit 2511 is coupled to the delay judging sub-circuit 252, and the delay judging sub-circuit 252 judges to delay the sampling gate input signal, and judges that the voltage value of the delayed sampling gate input signal is relatively delayed Whether there is a previous drop, so that it can be determined whether the voltage value of the sampling gate input signal is greater than the first preset voltage value for longer than the first preset time, so as to know whether the obtained sampling gate input signal is accurate.
  • the sampling sub-circuit 251 further includes: a signal processing unit 2512 coupled to the signal filtering unit 2511.
  • the signal processing unit 2512 is configured to receive the sampling gate input signal output by the signal filtering unit 2511, perform interference removal and amplification processing on the sampling gate input signal, and perform interference removal and amplification processing on the sampling gate input signal after the interference removal and amplification processing.
  • Two preset voltage values generate a first control signal, and output the first control signal.
  • the second preset voltage value is obtained according to the magnification in the magnification processing step.
  • the sampling gate input signal output by the signal filtering unit 2511 is a gate input signal c3 of a plurality of gate input signals c3, which is a signal that is directly output without any processing, and may be unstable.
  • the sampling sub-circuit 251 includes a signal filtering unit 2511 and a signal processing unit 2512. After the signal filtering unit 2511 selects the sampling gate input signal, the signal processing unit 2512 receives the sampling gate input
  • the sampling grid input signal is processed to remove the interference information in the sampling grid input signal, and the sampling grid input signal is amplified to make the sampling grid input signal more stable, according to the processed sampling grid input
  • the signal and the second preset voltage value generate the first control signal.
  • the first control signal is a constant voltage signal, which is more stable, so that in subsequent operations, it can improve Stability and accuracy of the entire detection process.
  • the signal processing unit 2512 includes: a noise reduction subunit 2512a, an amplification subunit 2512b, and a comparison subunit 2512c.
  • the noise reduction sub-unit 2512a is coupled to the signal screening unit 2511.
  • the noise reduction sub-unit 2512a is configured to receive the sampling gate input signal output by the signal screening unit 2511, perform interference removal processing on the sampling gate input signal, and output after interference removal The processed sampling gate input signal. In this way, the interference information in the input signal of the sampling grid can be removed, and the noise can be filtered out, so that the input signal of the sampling grid is purer and more accurate.
  • the noise reduction subunit 2512a includes a first resistor R1, a second resistor R2, a light-emitting diode D, and a capacitor C, wherein the first end of the first resistor R1 is connected to the noise reduction subunit 2512a.
  • the signal input terminal is coupled, the second terminal of the first resistor R1 is coupled to the first terminal of the second resistor R2, and also to the first voltage signal terminal VCC, and the second terminal of the second resistor R2 is connected to the noise reduction sub-unit
  • the signal output end of 2512a is coupled, the cathode of the light emitting diode D is coupled to the second end of the second resistor R2, the anode of the light emitting diode D is grounded, and the first end of the capacitor C is coupled to the second end of the second resistor R2, The second end of the capacitor C is grounded.
  • the combination of the first resistor R1, the second resistor R2, the light-emitting diode D, and the capacitor C has a filter-like function and can perform interference removal processing on the input signal of the sampling gate.
  • the amplifying subunit 2512b is coupled to the noise reduction subunit 2512a, and the amplifying subunit 2512b is configured to receive the de-interference processed sampling gate input signal output by the noise reduction sub-unit 2512a.
  • the input signal of the sampling gate is amplified, and the input signal of the sampling gate after interference removal and amplification is output.
  • the amplifying sub-circuit 2512b amplify the input signal of the sampling gate after the interference removal process, which can increase the signal strength and convert the relatively weak signal into a relatively strong and stable signal, which is convenient for the subsequent sub-circuit to input the sampling gate. Signal acquisition and processing.
  • the amplifying sub-circuit 2512b includes a first operational amplifier S1, a third resistor R3, and a fourth resistor R4.
  • the first operational amplifier S1 has an inverting input terminal, a non-inverting input terminal, and an output terminal.
  • the inverting input terminal of the first operational amplifier S1 is the signal input terminal of the amplifying sub-circuit 2512b
  • the output terminal of the first operational amplifier S1 is the signal output terminal of the amplifying sub-circuit 2512b
  • the non-inverting input terminal of the first operational amplifier S1 is
  • the three resistors R3 are coupled, the other end of the third resistor R3 is grounded, and the fourth resistor R4 is coupled between the non-inverting input terminal and the output terminal of the first operational amplifier S1.
  • the fourth resistor R4 is a variable resistor, and the amplification factor of the amplifying sub-circuit 2512b can be adjusted as needed by adjusting the resistance of the fourth resistor R4.
  • the comparison subunit 2512c is coupled to the amplification subunit 2512b, and the comparison subunit 2512c is configured to receive the de-interference and amplification processing sampling gate input signal output by the amplifying sub-unit 2512b.
  • the amplified sampling gate input signal and the second preset voltage value generate a first control signal, and output the first control signal.
  • the above comparison subunit 2512c is set to: compare the sampling gate input signal with the second preset voltage value, and generate the first control when the sampling gate input signal is greater than the second preset voltage value.
  • Signal Since the sampling gate input signal is the filtered gate input signal c3 whose voltage value is greater than the first preset voltage value, the signal processing sub-circuit only processes the sampling gate input signal to make it more stable. Therefore, The second preset voltage value needs to be determined according to the amplification factor of the amplifying subunit 2512b to ensure that the sampling gate input signal is greater than the second preset voltage value, so as to ensure that the comparing subunit 2512c can output the first control signal.
  • the comparison subunit 2512c is set to compare the sampling gate input signal with the second preset voltage value, and when the sampling gate input signal is less than the second preset voltage value, generate the first control signal, Then, the second preset voltage value needs to be determined according to the amplification factor of the amplifying subunit 2512b to ensure that the sampling gate input signal is less than the second preset voltage value, so that the comparing subunit 2512c can output the first control signal.
  • the comparison subunit 2512c includes a second operational amplifier S2, a fifth resistor R5, and a sixth resistor R6.
  • the second operational amplifier S2 has an inverting input terminal, a non-inverting input terminal and an output terminal.
  • the inverting input terminal of the second operational amplifier S2 is the signal input terminal of the comparison subunit 2512c, and the output terminal of the second operational amplifier S2
  • the second operational amplifier S2 is also coupled to the second preset voltage signal terminal IA2 and is grounded.
  • the first terminal of the fifth resistor R5 is coupled to the first voltage signal terminal, and the second terminal is coupled to the non-inverting input terminal of the second operational amplifier S2.
  • the first end of the sixth resistor R6 is coupled to the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is grounded. After the voltage division of the fifth resistor R5 and the sixth resistor R6, it is input to the second operation
  • the voltage of the signal at the non-inverting input terminal of the amplifier S2 is a reference voltage, and the reference voltage is smaller than the voltage at which the first voltage signal terminal transmits the first voltage signal.
  • the inverting input terminal of the second operational amplifier S2 receives the de-interference and amplification processing sampling gate input signal output by the amplifying sub-circuit 2512b. Illustratively, the de-interference and amplification processing sampling gate input signal is greater than the reference voltage. , And greater than the second preset voltage value, the second operational amplifier S2 outputs the first control signal.
  • the first control signal is a constant voltage signal that is compared and output by the comparison subunit 2512c, for example, a high voltage signal. Compared with the sampling gate input signal, the constant first control signal is more stable and is more convenient for the subsequent delay judgment sub-circuit 252 operates it to output a counting signal to the counting sub-circuit, so that the counting control sub-circuit 253 counts.
  • the signal screening unit 2511 is configured to receive the plurality of gate input signals c3, and respectively compare the plurality of gate input signals c3 with a first preset voltage value, and obtain a certain gate input signal c3. When the voltage value of the input signal c3 is greater than the first preset voltage value, the gate input signal c3 is used as the sampling gate input signal.
  • the signal filtering unit 2511 is configured to receive the plurality of gate input signals c3, filter out the gate input signal c3 with the largest voltage value among the plurality of gate input signals c3, and combine all the gate input signals c3.
  • the filtered voltage value of the gate input signal c3 is compared with the first preset voltage value. In the case where the voltage value of the gate input signal c3 selected is greater than the first preset voltage value, the gate input signal c3 is used as the sampling gate input signal.
  • the gate input signal c3 with the largest voltage value among the plurality of gate input signals c3 is filtered out, hereinafter referred to as the largest gate input signal c3, and then the largest gate is input
  • the signal c3 is compared with the first preset voltage value. If the voltage value of the largest gate input signal c3 is less than the first preset voltage value, it means that none of the gate input signals c3 has an overcurrent abnormality. If the voltage value of the largest gate input signal c3 is greater than the first preset voltage value, it means that one or several gate input signals c3 has an overcurrent abnormality, and the largest gate input signal c3 is taken as Sampling grid input signal output. In this way, the screening steps can be saved, the screening time can be saved, and the accuracy of the obtained results is higher.
  • the specific structure of the signal screening unit 2511 is: the number of the plurality of gate input signals c3 is x, the signal screening unit 2511 includes an n-level filter group, and the i-th level filter group includes 2 (ni ) Filters; where x is a positive integer greater than or equal to 3, n is a positive integer greater than or equal to 2, and i takes a value in sequence within the set of positive integers of [1, n].
  • the required multiple gate input signals c3 include at least the CLK signal, the STV signal, and the VDD signal, so the number of the multiple gate input signals c3 is at least three.
  • a filter has two input terminals and one output terminal.
  • the two input terminals of one filter in the (i+1)-th level filter group are respectively coupled to the output terminals of the two filters in the i-th level filter group.
  • the number of the multiple gate input signals c3 is 8 (for example, the multiple gate input signals c3 include CLK1, CLK2, CLK3, CLK4, STV1, STV2, VDD1, and VDD2), and the signal is filtered Unit 2511 includes a 3-level filter group, the first-level filter group includes 4 filters (AMP1, AMP2, AMP3, AMP4), the second-level filter group includes 2 filters (AMP5 and AMP3), the first level The filter group includes 1 filter (AMP7).
  • Two input terminals of one filter in the second-level filter group are respectively coupled to the output terminals of two filters in the third-level filter group, and two of one filter in the first-level filter group The input terminal is respectively coupled to the output terminals of the two filters in the second-level filter group.
  • the first-stage filter group is configured to obtain the plurality of gate input signals c3, and each filter in the first-stage filter group is configured to receive two gates of the plurality of gate input signals c3 Input signal c3, and output one of the two received gate input signals c3 with a larger voltage value.
  • each filter in the first-stage filter group is configured to receive two gate input signals c3 of the plurality of gate input signals c3, for example, the filter AMP1 receives two gate input signals c3. Two gate input signals STV0 and STV1.
  • the first-stage filter group includes 4 filters, each of the 4 filters receives one of the 8 gate input signals c3 Two gate input signals c3, and a gate input signal c3 with a larger voltage value among the received two gate input signals c3 is output.
  • the first stage filter group includes 2 (n-1) filters, and each filter is configured to accept two gates Input signal c3, therefore, the relationship between the number of stages of filters included in the screening sub-circuit and the number of gate input signals c3 is: in the case that the signal screening unit 2511 includes n-stage filter groups, the first-stage filter group is the largest Able to receive 2 n gate input signals c3. For example, in the case where the signal screening unit 2511 includes a 3-level filter group, the first-level filter group includes 4 filters, and the first-level filter group can receive a maximum of 8 gate input signals c3. In the case where the signal screening unit 2511 includes a 4-level filter group, the first-level filter group includes 8 filters, and the first-level filter group can receive a maximum of 16 gate input signals c3.
  • the plurality of gate input signals c3 is a group of two, and is input to the plurality of filters in the first-stage filter group for comparison.
  • each group includes two gate input signals c3, which are respectively input to the three filters in the first stage filter group, and the remaining one gate input signal c3 among the seven gate input signals c3 is input to the first A filter in the first-stage filter group, the remaining one of the gate input signals c3 directly enters the second-pole filter group through the filter, and thus enters the second-pole filter group with the above 6 gate input signals c3 A certain gate input signal c3 is compared.
  • the i+1th stage filter group is configured to receive the gate input signal c3 output by the i-th stage filter group, and each filter in the i+1th stage filter group is configured to receive the i-th stage
  • the two gate input signals c3 of the gate input signals c3 output by the filter group are output, and the one of the two received gate input signals c3 with a larger voltage value is output.
  • the second-level filter group is configured to receive the gate input signal c3 output by the first-level filter group, and the two filters in the second-level filter group are both configured to receive the first-level filter group.
  • Two gate input signals c3 among the gate input signals c3 output by the first-stage filter group, and one gate input signal c3 with a larger voltage value among the two received gate input signals c3 is output.
  • the filters in the n-th stage filter group are configured to receive two gate input signals c3 output by the n-1th stage filter group, and filter out the gate with the larger voltage value of the two gate input signals c3. Input signal c3, and compare the filtered voltage value of the gate input signal c3 with the first preset voltage value, where the voltage value of the gate input signal c3 is greater than that of the first preset voltage value In this case, the gate input signal c3 is used as the sampling gate input signal.
  • the nth level filter group is the last level filter group.
  • the third level filter group is coupled to the first preset voltage terminal IA1 and is configured to receive two output from the second level filter group.
  • the gate input signal c3 with the larger voltage value of the two gate input signals c3 is screened out, so that the gate input signal c3 with the largest voltage value among the multiple gate input signals c3 is screened out Input signal c3.
  • the selected voltage value of the gate input signal c3 is compared with the first preset voltage value, and when the voltage value of the gate input signal c3 is greater than the first preset voltage value, the gate input signal c3 is As a sampling grid input signal.
  • each filter includes: an operational amplifier S and two screening resistors R, wherein the two screening resistors R are respectively coupled to the inverting input terminal and the non-inverting input terminal of the operational amplifier S, The other ends of the two screening resistors R are respectively coupled to the two signal input ends of the filter, and the output end of the operational amplifier is the output end of the filter.
  • the above-mentioned signal screening unit 2511 filters the received multiple gate input signals c3 layer by layer by setting a multi-stage filter group, and finally selects the gate input signal c3 with the largest voltage value. If the gate input signal c3 is If the voltage value of is greater than the first preset voltage value, it is used as the sampling gate input signal. In the above-mentioned filter group, the filters in the same level of filter group work at the same time, which can shorten the screening time and improve efficiency.
  • the signal screening unit 2511 further includes a switch control sub-unit 25111.
  • the switch control sub-unit 25111 is coupled to the first-level filter group, and is configured to control the opening or closing of each filter in the first-level filter group.
  • the signal screening unit 2511 includes a 3-level filter group, and the first-level filter group includes 4 filters, then the switch control subunit 25111 includes 4 switch modules K and 1 switch.
  • a signal output module H, a switch module K is coupled to a filter in the first-stage filter group, a switch signal output module H is coupled to the four switch modules, and a switch signal output module H is configured to a plurality of switches
  • the modules K respectively output corresponding control signals to control the on and off of the plurality of switch modules K, so as to control the opening or closing of the filter coupled to each switch module K.
  • the switch module K includes a switch transistor, the control pole of the switch transistor is coupled to the output terminal of the switch signal output module, the first pole of the switch transistor is coupled to the input terminal of the signal screening unit, and the second pole of the switch transistor is coupled to the output terminal of the switch signal output module.
  • the input terminal of one filter in the first-pole filter group is coupled.
  • the switching transistor is configured to be turned on or off under the action of the control signal output by the switching signal output module to control the opening or closing of the filter group to which it is coupled.
  • the control signal is a high-level signal or a low-level signal.
  • the first-level filter group includes 4 filters, and the 6 gates
  • the input signal c3 requires three filters, and the switch control sub-circuit controls three of the filters to open and control the other four filters to close, thereby saving unnecessary power consumption.
  • a multi-stage filter group can be set in the signal filtering unit 2511 to support the detection of a larger number of gate input signals c3, and the switch control subunit controls the first-stage filter group.
  • Each filter is turned on or off, the filter that needs to be worked is turned on, and the idle filter is turned off, which can save power consumption.
  • circuit structure of the signal screening unit 2511 provided in the present disclosure is only an illustration, and the specific implementation of the delay unit is not limited to the above-described manner, and it can be any implementation manner used, such as this
  • the conventional connection methods well known to those skilled in the art only need to ensure that the corresponding functions are realized, and the above examples cannot limit the protection scope of the present disclosure.
  • the delay judgment sub-circuit 252 includes a delay unit 2521 and a judgment unit 2522.
  • the delay unit 2521 is configured to receive the first control signal output by the sampling sub-circuit 251, delay the first control signal for a first preset time, and output the delayed first control signal.
  • the delay unit 2521 includes a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a first transistor TR1, a second transistor TR2, a first capacitor C1, and a second capacitor C2.
  • the first terminal of the first delay resistor R11 is coupled to the first input terminal IN1, and the second terminal is coupled to the first node N1.
  • the first resistor is coupled between the first node N1 and the second node N2, the second resistor is coupled between the first node N1 and the second node N2, and the second node N2 is grounded.
  • the control electrode of the first transistor TR1 is coupled to the first node N1, the first electrode is coupled to the second node N2, the second electrode is coupled to the first end of the second delay resistor R12, The second end is coupled to the fourth node N4.
  • the third capacitor C3 is coupled between the third node N3 and the fourth node N4, and the second input terminal IN2 is coupled to the third node N3.
  • the third delay resistor R13 is coupled between the third node N3 and the fourth node N4.
  • the first end of the fourth delay resistor R14 is coupled to the third node N3, and the second end is coupled to the fifth node N5.
  • the control electrode of the second transistor TR2 is coupled to the fourth node N4, the first electrode of the second transistor TR2 is coupled to the third node N3, and the second electrode of the second transistor TR2 is coupled to the fifth node N5.
  • the first terminal of the fourth capacitor C4 is coupled to the fifth node N5, and the second terminal is grounded.
  • the fifth node N5 is coupled to the sixth node N6, and the sixth node N6 is coupled to the test point TEST and the output terminal OUT.
  • the test point TEST is configured to test the delayed first control signal.
  • the first transistor TR1 is a PNP-type N-channel enhancement metal-oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the first transistor TR1 has the following parameters: turn-on delay time is 7ns (maximum Wie14ns), turn-on rise time is 15ns (maximum 30ns) , The turn-off delay (urn-off delay time) is 38ns (the maximum value is 76ns), and the turn-off fall time is 3ns (the maximum value is 6ns).
  • the second transistor TR2 is a PNP-type metal-oxide semiconductor field effect transistor, and the second transistor TR2 can be used for voltage signal processing or current signal processing.
  • the first pole of the second transistor TR2 is coupled to the third node N3 through the three input channels labeled 1, 2, and 3, and the second pole of the second transistor TR2 is coupled to the third node N3 through the three input channels labeled 5, 6, 7, 8, and 9.
  • the output channel is coupled to the fifth node N5, and the channel labeled 4 is configured to transmit a reference voltage signal, so that the signal input through the channel labeled 4 can be used as a reference delay voltage control.
  • the first transistor TR1 has the following parameters: the turn-on delay is 5.6 ns, the turn-on rise time is 18.4 ns, the turn-off delay is 46.6 ns, and the turn-off fall time is 12 ns.
  • the capacitances of the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be set according to the circuit ripple of the delay unit 2521, which is not limited in the present disclosure.
  • the first capacitor C1, the second capacitor C1, and the second capacitor C3 The capacitance values of the capacitor C2 and the third capacitor C3 are both 10 uf, so as to cope with the ripple of 150 mV.
  • the resistance range of the first delay resistor R11 is 0K-50K, such as 30K
  • the resistance range of the second delay resistor R12 is 10K-25K, such as 22.1K.
  • the first input terminal IN1 and the second input terminal IN2 receive the first control signal, which is transmitted to the sixth node N6 after the delay processing, and the delayed output terminal OUT and the test point TEST are output from the output terminal OUT and the test point TEST.
  • the first control signal by testing the delayed first control signal from the test point TEST, it can be known that the comprehensive test result of the delayed first control signal satisfies pulse width (pulse width) ⁇ 300us, duty cycle (accounting for Empty ratio) ⁇ 2%.
  • the delayed first control signal is delayed by about 3 ⁇ s compared to the undelayed first control signal.
  • the circuit structure of the delay unit 2521 provided in the present disclosure is only an illustration, and, in practical applications, the parameters of the first transistor TR1 and the second transistor TR2, as well as the capacitance and resistance of the capacitor The resistance value can be set accordingly according to the actual situation.
  • the specific implementation manner of the delay unit 2521 is not limited to the manner described above, it can be an implementation manner that can be used arbitrarily, such as a conventional connection manner well known to those skilled in the art, and only needs to ensure that the corresponding function is implemented. The above example does not Limit the scope of protection of the present disclosure.
  • the judging unit 2522 is coupled to the delay unit 2521.
  • the judging unit 2522 is configured to receive the first control signal output by the sampling sub-circuit 251 and the delayed first control signal output by the delay unit 2521. Whether the voltage value of the first control signal is equal after the delay, if so, output the count signal.
  • the judging unit 2522 has two input ports and one output port, and the two input ports are configured to receive the first control signal output by the sampling sub-circuit 251 and the delayed output of the delay unit 2521.
  • the counting signal is output from the output port.
  • the counting control sub-circuit 253 is further configured to output a third control signal c6 when the number of counts reaches a preset number of times, and the third control signal c6 is used to cut off the signal source direction.
  • the system board 1 can intercept the input of the original signal source at the source, improve the reliability of the over-current protection system of the entire display device 100, and can reduce the invalid drive of the system board 1, avoiding possible abnormal source signals to cause the system board 1 Adverse effects.
  • the counting control sub-circuit 253 includes a counting unit 2531 and a control unit 2532.
  • the counting unit 2531 is configured to receive the counting signal output by the delay judging sub-circuit 252 and perform counting according to the counting signal.
  • the control unit 2532 is coupled to the counting unit 2531, and the control unit 2532 is configured to store the number of counts, and when the number of counts reaches a preset number, output the second control signal c5.
  • the second control signal c5 is used to cut off the signal input of the system board 1 of the display device 100 to the drive circuit 2 of the display device 100.
  • the control unit 2532 is also configured to determine whether the number of counts has increased within a second preset time after the count number has not reached the preset number of times, and if not, reset the number of counts to zero.
  • the second preset time is a clock period T of the detection timing signal, for example, 50 ⁇ s.
  • control unit 2532 is further configured to output the third control signal c6 when the number of counts reaches a preset number of times.
  • the third control signal c6 is used to cut off the signal input of the video signal source 1'to the system board 1.
  • the counting function can be realized, and when the preset number of times is reached, the second control signal c5 and the third control signal c6 are output, thereby cutting off the driving circuit 2 of the system board 1 to the display device 100
  • the signal input of protects the drive circuit 2 and the display panel 3, cuts off the signal input of the signal source to the system board 1, thereby protecting the system board 1.
  • the display device 100 may be any device that displays images regardless of motion (for example, video) or fixed (for example, still image), and regardless of text or image. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, and handheld devices.
  • GPS receivers/navigators cameras
  • MP4 video players camcorders
  • game consoles watches, clocks, calculators
  • TV monitors flat panel displays
  • computer monitors car monitors (e.g., odometer monitors) Etc.)
  • navigator cockpit controller and/or display
  • camera view display for example, the display of a rear-view camera in a vehicle
  • electronic photos electronic billboards or signs
  • projectors building structures
  • packaging and aesthetic structures For example, for a display of an image of a piece of jewelry
  • the display device 100 provided in the present disclosure may be a liquid crystal display device 100 (Liquid Crystal Display, LCD for short); the display device 100 may also be an electroluminescence display device 100 or a photoluminescence display device 100.
  • the electroluminescent display device 100 may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device 100 (Quantum Dot Light Emitting Diodes, QLED for short).
  • the photoluminescence display device 100 may be a quantum dot photoluminescence display device 100.
  • Some embodiments of the present disclosure also provide an overcurrent protection method, which is applied to the display device 100 shown in FIG. 2 provided by the present disclosure. As shown in FIGS. 10A and 10B, the overcurrent protection method includes:
  • the system board 1 of the display device 100 outputs a power supply signal c2 and a display signal c1 to the drive circuit 2 of the display device 100.
  • the power supply circuit 21 in the drive circuit 2 receives the power signal c2, and according to the power signal c2, provides electrical energy to the timing controller 22 and the overcurrent protection circuit 25 in the drive circuit 2.
  • the power circuit 21 also provides power to the display panel 3, the gate driving circuit 31, and the source driving circuit 23 according to the power signal c2.
  • the timing controller 22 receives the display signal c1, and generates a plurality of gate input signals c3 for input to the gate driving circuit 31 of the display device 100 according to the display signal c1.
  • the timing controller 22 further generates a plurality of source input signals c4 for input to the source driving system of the display device 100 according to the display signal c1.
  • the overcurrent protection circuit 25 obtains the plurality of gate input signals c3, and continuously detects the plurality of gate input signals c3.
  • the second control signal c5 When detecting that the multiple gate input signals c3 have overcurrent, the second control signal c5 is output to the power supply circuit 21.
  • the second control signal c5 is used to cut off the signal input of the system board 1 of the display device 100 to the drive circuit 2 of the display device 100.
  • the overcurrent protection circuit 25 When it is detected that no overcurrent occurs in the plurality of gate input signals c3, the overcurrent protection circuit 25 does not output a signal.
  • S4 further includes:
  • the third control signal c6 is output to the system board 1.
  • the third control signal c6 is used to cut off the signal input of the video signal source 1'to the system board 1.
  • the overcurrent protection circuit 25 detects multiple gate input signals c3 once in each clock period T to achieve continuous Detection. For example, when the falling edge or rising edge of the detection timing signal comes, in the next clock cycle T (square wave cycle), another detection is performed.
  • the specific detection process of the over-current protection circuit 25 in S4 includes:
  • the display device 100 works normally, the overcurrent protection circuit 25 continuously detects the multiple gate input signals c3, and the overcurrent protection circuit 25 does not output a signal at this time.
  • the driving circuit 2 and the display panel 3 enter the working state, and the overcurrent protection circuit 25 continuously detects the multiple gate input signals c3 output by the timing controller.
  • the overcurrent protection circuit 25 does not output a signal, that is, the overcurrent protection circuit 25 does not detect that the multiple gate input signals c3 have overcurrent, and the display device is in a normal working state.
  • S402 to S411 are the detection process of the multiple gate input signals c3 by the internal devices included in the overcurrent protection circuit 25 in one clock period T.
  • the sampling sub-circuit 251 obtains a plurality of gate input signals c3 and performs screening.
  • the sampling sub-circuit 251 determines whether the voltage value of the gate input signal c3 screened is greater than a first preset voltage value.
  • the signal filtering unit 2511 in the sampling sub-circuit 251 receives the plurality of gate input signals c3, and filters out the gate with the largest voltage value among the plurality of gate input signals c3.
  • Input signal c3, compare the filtered voltage value of the gate input signal c3 with the first preset voltage value, and determine whether the filtered voltage value of the gate input signal c3 is greater than the first preset voltage value.
  • the sampling sub-circuit 251 uses a gate input signal c3 with a voltage value greater than a first preset voltage value among the plurality of gate input signals c3 as a sampling gate input signal; generates and outputs according to the sampling gate input signal The first control signal.
  • the sampling sub-circuit 251 includes a signal screening unit 2511, and the signal screening unit 2511 screens out a gate input signal c3 whose voltage value is greater than the first preset voltage value among the plurality of gate input signals c3, As a sampling gate input signal, and output the sampling gate input signal as a first control signal.
  • the sampling sub-circuit 251 includes a signal screening unit 2511 and a signal processing unit 2512.
  • the signal screening unit 2511 filters out one of the plurality of gate input signals c3 whose voltage value is greater than the first preset voltage value.
  • the gate input signal c3 is used as a sampling gate input signal.
  • the signal processing unit 2512 receives the sampling gate input signal output by the signal filtering unit 2511, and performs interference removal and amplification processing on the sampling gate input signal, according to the sampling gate input signal after the interference removal and amplification processing and the second preset voltage value A first control signal is generated, and the first control signal is output.
  • the delay judgment sub-circuit 252 is configured to receive the first control signal output by the sampling sub-circuit 251, and delay the first control signal for a first preset time.
  • the delay judging sub-circuit 252 judges whether the voltage value of the first control signal after the delay has decreased compared with that before the delay.
  • the sampling sub-circuit 251 includes a signal filtering unit 2511, and outputs the filtered sampling gate input signal as the first control signal, in this step, it is actually judged that the sampling gate input signal is Whether the duration of the voltage value greater than the first preset voltage value is greater than the first preset time.
  • the selected sampling gate input signal is not the real gate input signal c3 whose voltage value is greater than the first preset voltage value, but the sample selected in the presence of a spike current The gate input signal, and thus the first control signal generated according to the wrong sampling gate input signal is not accurate.
  • the multiple gate input signals c3 have not really over-current, so return to S401 and wait for the next clock Periodic detection.
  • the delay judgment sub-circuit 252 outputs a counting signal.
  • the counting control sub-circuit 253 receives the counting signal output by the delay judging sub-circuit 252, and performs counting according to the counting signal.
  • the counting control sub-circuit 253 judges whether the counting number reaches a preset number.
  • the preset number of times is 3 times. If the result is yes, it means that at least one gate input signal c3 has a voltage value greater than the first preset voltage value in three consecutive clock cycles T. In this case, it means that the overcurrent abnormality of the gate input signal c3 has lasted for at least three clock cycles T, and the process proceeds to S412: the counting control sub-circuit 253 outputs the second control signal c5 to the power supply circuit 21. Alternatively, the counting control sub-circuit 253 outputs the second control signal c5 to the power supply circuit 21 and outputs the third control signal c6 to the system board 1.
  • the result is no, it means that there are not enough times when the voltage value of at least one gate input signal c3 is greater than the first preset voltage value. For example, if the preset number is 3 times, if the number of times is counted at this time If it is 2, enter S410 at this time.
  • the counting control sub-circuit 253 determines whether the number of counting increases within a second preset time after this.
  • the second preset time is one clock period T, for example, 50 ⁇ s.
  • T time period
  • the number of counts is less than the preset number of times, it is determined whether the number of counts has increased in a clock period T thereafter, so as to determine whether the occurrence of multiple gate input signals c3 is detected again in the clock period T
  • the overcurrent is abnormal.
  • the counting control sub-circuit 253 clears the number of counting times, and returns to S401, the plurality of gate input signals c3 does not have an overcurrent abnormality, and waits for detection in the next clock cycle.
  • the overcurrent protection method further includes: S5 and S5'.
  • the power circuit 21 receives the second control signal c5, and under the control of the second control signal c5, stops receiving the power signal c2 input by the system board 1.
  • the power supply circuit 21 stops supplying power to the timing controller 22, the gate drive circuit 31, the source drive circuit 23, and the display panel 3, so that the drive circuit 2 and the display panel 3 stop working, so that the timing controller 22 cannot generate more power.
  • the gate input signal c3 cannot provide multiple gate input signals c3 with overcurrent abnormality to the gate driving circuit 31, so that the abnormal multiple gate input signals c3 can be cut off in time and will not be input to the gate drive
  • the circuit 31 prevents the abnormal multiple gate input signals c3 from causing adverse effects on the gate driving circuit 31, which in turn causes adverse effects on the display panel 3.
  • the system board 1 receives the third control signal c6, and under the control of the third control signal c6, stops receiving the signal input by the signal source. Therefore, the system board 1 cuts off the input at the source of the signal, further avoiding the adverse effect of the abnormal signal on the display device 100.
  • the overcurrent protection method of the display device 100 provided in the present disclosure can continuously detect the gate input signal c3 through the overcurrent protection circuit 25, and ensure that the gate input signal c3 is over-current due to the abnormality of the display signal c1.
  • the flow abnormality can be detected in time, and the second control signal c5 is output at the moment the abnormality is detected, so that the power supply circuit 21, under the control of the second control signal c5, stops receiving the power supply signal c2 input by the system board 1, and cuts off
  • the input of the power signal c2 of the system board 1 to the power circuit 21 stops the power supply of the display device 100, thereby protecting the display panel 3 and the entire driving circuit 2, and avoiding the display device 100 from continuing to run and causing defects to the display panel 3 and the driving circuit 2 Influence.
  • the third control signal c6 is output at the moment an abnormality is detected, and the system board 1 stops receiving the signal input by the signal source under the control of the third control signal c6, which further avoids possible abnormal signal source input signal pairs
  • the adverse effects of the display device 100 can also protect the system board 1.

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Abstract

提供一种过流保护电路，被配置为对输入至栅极驱动电路的多个栅极输入信号进行连续侦测，包括：采样子电路、延时判断子电路和计数控制子电路。采样子电路获取多个栅极输入信号，筛选出多个栅极输入信号中电压值大于第一预设电压值的一个栅极输入信号，生成并输出第一控制信号。延时判断子电路与采样子电路耦接，被配置为对第一控制信号进行第一预设时间的延时，判断经过延时的第一控制信号的电压值相较延时前是否有下降，若否，则输出计数信号。计数控制子电路与延时判断子电路耦接，被配置为根据计数信号进行计数；在计数次数达到预设次数的情况下，输出用于切断显示装置的***板向显示装置的驱动电路的信号输入的第二控制信号。

Description

过流保护电路、显示装置及其驱动电路、过流保护方法
本申请要求于2020年6月17日提交的、申请号为202010555560.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种过流保护电路、显示装置的驱动电路、显示装置、过流保护方法。
背景技术
在显示装置中，时序控制器的功能为，接收***板所输入的显示信号，对显示信号进行处理，生成源极驱动电路和栅极驱动电路的工作时序，从而源极驱动电路和栅极驱动电路根据所接收的信号，驱动显示面板进行显示，在显示信号出现异常的情况下，时序控制器根据显示信号所生成的源极驱动电路和栅极驱动电路的工作时序也会出现异常，从而影响显示装置的正常显示，且会对显示面板产生损坏。
发明内容
一方面，提供一种过流保护电路，该过流保护电路被配置为对输入至栅极驱动电路的多个栅极输入信号进行连续侦测；所述过流保护电路包括：采样子电路、延时判断子电路和计数控制子电路。
所述采样子电路被配置为，获取所述多个栅极输入信号，筛选出所述多个栅极输入信号中电压值大于第一预设电压值的一个栅极输入信号，作为采样栅极输入信号；及，根据所述采样栅极输入信号生成并输出第一控制信号；其中，所述第一预设电压值为，栅极输入信号的电压正常状态与过流状态的临界电压值。
延时判断子电路与所述采样子电路耦接，所述延时判断子电路被配置为，接收所述采样子电路输出的第一控制信号，对所述第一控制信号进行第一预设时间的延时，判断经过延时的第一控制信号的电压值相较延时前是否有下降，若否，则输出计数信号。
计数控制子电路与所述延时判断子电路耦接，所述计数控制子电路被配置为，接收所述延时判断子电路输出的计数信号，并根据所述计数信号进行计数；在计数次数达到预设次数的情况下，输出第二控制信号，所述第二控制信号用于切断显示装置的***板向显示装置的驱动电路的信号输入。
在一些实施例中，所述采样子电路包括：信号筛选单元；所述信号筛选单元被配置为接收所述多个栅极输入信号，筛选出所述多个栅极输入信号中 电压值大于所述第一预设电压值的一个栅极输入信号，作为采样栅极输入信号。
在一些实施例中，所述采样子电路还包括：与所述信号筛选单元耦接的信号处理单元；所述信号处理单元被配置为接收所述信号筛选单元输出的采样栅极输入信号，对所述采样栅极输入信号进行去干扰和放大处理，根据经过去干扰和放大处理的采样栅极输入信号和第二预设电压值生成第一控制信号，并输出所述第一控制信号；其中，所述第二预设电压值与对所述采样栅极输入信号进行去干扰和放大处理的放大倍数有关。
在一些实施例中，所述信号处理单元包括：降噪子单元、放大子单元和比较子单元。所述降噪子单元被配置为接收所述信号筛选单元输出的采样栅极输入信号，对所述采样栅极输入信号进行去干扰处理，并输出经过去干扰处理的采样栅极输入信号。放大子单元与所述降噪子单元耦接，所述放大子单元被配置为接收所述降噪子单元输出的经过去干扰处理的采样栅极输入信号，对所述经过去干扰处理的采样栅极输入信号进行放大处理，并输出经过去干扰和放大处理的采样栅极输入信号。比较子单元与所述放大子单元耦接，所述比较子单元被配置为接收所述放大子单元输出的经过去干扰和放大处理的采样栅极输入信号，根据所述经过去干扰和放大处理的采样栅极输入信号和所述第二预设电压值生成第一控制信号，并输出所述第一控制信号。
在一些实施例中，所述信号筛选单元被配置为接收所述多个栅极输入信号，筛选出所述多个栅极输入信号中电压值最大的一个栅极输入信号，将所筛选出的栅极输入信号的电压值与所述第一预设电压值比较；在所筛选出的栅极输入信号的电压值大于所述第一预设电压值的情况下，将该栅极输入信号作为采样栅极输入信号。
在一些实施例中，所述多个栅极输入信号的数量为x，所述信号筛选单元2511包括n级筛选器组，第i级筛选器组包括2 (n-i)个筛选器；其中，x为大于或等于3的正整数，n为大于或等于2的正整数，i在[1，n]的正整数的集合内依次取值。
一个筛选器具有两个输入端和一个输出端；第(i+1)级筛选器组中的一个筛选器的两个输入端与第i级筛选器组中的两个筛选器的输出端分别耦接。第1级筛选器组被配置为获取所述多个栅极输入信号，第1级筛选器组中的各筛选器被配置为接收所述多个栅极输入信号中的两个栅极输入信号，并将所接收的两个栅极输入信号中电压值较大的一个栅极输入信号输出。
第i+1级筛选器组被配置为接收第i级筛选器组所输出的栅极输入信号， 第i+1级筛选器组中的各筛选器被配置为，接收所述第i级筛选器组所输出的栅极输入信号中的两个栅极输入信号，并将所接收的两个栅极输入信号中电压值较大的一个栅极输入信号输出。第n级筛选器组中的筛选器被配置为接收第n-1级筛选器组输出的两个栅极输入信号，筛选出该两个栅极输入信号中电压值较大的一个栅极输入信号，并将所筛选出的栅极输入信号的电压值与所述第一预设电压值比较，在该栅极输入信号的电压值大于所述第一预设电压值的情况下，将该栅极输入信号作为采样栅极输入信号。
在一些实施例中，所述信号筛选单元还包括开关控制子单元。所述开关控制子单元与所述第1级筛选器组耦接，被配置为控制所述第1级筛选器组中的各筛选器打开或关闭。
在一些实施例中，所述延时判断子电路包括：延时单元和判断单元。
所述延时单元被配置为接收所述采样子电路输出的第一控制信号，对所述第一控制信号进行第一预设时间的延时，输出经过延时的第一控制信号。判断单元与所述延时单元耦接，所述判断单元被配置为接收所述采样子电路输出的第一控制信号，和所述延时单元输出的经过延时的第一控制信号，判断延时前与延时后第一控制信号的电压值是否相等，若是，则输出计数信号。
在一些实施例中，所述第一预设时间为3μs～5μs。
在一些实施例中，所述计数控制子电路还被配置为，在计数次数没有达到所述预设次数的情况下，判断在此之后的第二预设时间之内计数次数是否有增加，若否，则将所述计数次数清零。
在一些实施例中，所述过流保护电路在侦测时序信号的控制下，在每个时钟周期内对多个栅极输入信号进行一次侦测；所述第二预设时间为一个时钟周期。
在一些实施例中，所述计数控制子电路还被配置为在所述计数次数达到预设次数的情况下，输出第三控制信号，所述第三控制信号用于切断信号源向所述***板的信号输入。
在一些实施例中，所述计数控制子电路包括：计数单元和控制单元。
所述计数单元被配置为接收所述延时判断子电路输出的计数信号，并根据所述计数信号进行计数。控制单元与所述计数单元耦接，所述控制单元被配置为存储计数次数，在所述计数次数达到所述预设次数的情况下，输出第二控制信号。
另一方面，通过一种显示装置的驱动电路，包括：电源电路、时序控制器和如上所述的过流保护电路。
所述电源电路与显示装置的***板、所述时序控制器和所述过流保护电路耦接，所述电源电路被配置为接收所述***板所输入的电源信号，并根据所述电源信号为所述时序控制器和所述过流保护电路提供电能。
所述时序控制器还与所述***板耦接，所述时序控制器被配置为接收***板所输入的显示信号，根据所述显示信号生成用于输入至显示装置的栅极驱动电路的多个栅极输入信号。
所述过流保护电路还与所述时序控制器耦接。所述电源电路还被配置为接收所述过流保护电路输出的第二控制信号，并在所述第二控制信号的控制下，停止接收所述***板输入的电源信号。
在一些实施例中，驱动电路还包括：源极驱动电路。所述源极驱动电路与所述电源电路和所述时序控制器耦接。所述时序控制器还被配置为根据所述显示信号生成用于输入至所述源极驱动电路的多个源极输入信号。所述源极驱动电路被配置为接收所述多个源极输入信号，并根据多个源极输入信号生成数据信号。
再一方面，提供一种显示装置，包括：如上所述的驱动电路、***板和显示面板。所述***板与所述驱动电路中的电源电路和时序控制器耦接，被配置为输出电源信号和显示信号。
显示面板与所述驱动电路耦接。其中，所述显示面板包括栅极驱动电路，所述栅极驱动电路与所述驱动电路中的时序控制器和电源电路耦接；所述栅极驱动电路被配置为接收所述时序控制器输出的多个栅极输入信号，根据所述多个栅极输入信号，生成并输出栅极扫描信号。
在一些实施例中，在所述驱动电路中的过流保护电路还被配置为输出第三控制信号的情况下，所述***板还与所述驱动电路中的过流保护电路耦接。所述***板还被配置为接收所述第三控制信号，并在所述第三控制信号的控制下，停止接收视频信号源输入的视频信号。
又一方面，提供一种过流保护方法，应用于如上所述的显示装置，所述过流保护方法包括：显示装置的***板向显示装置的驱动电路输出电源信号和显示信号。所述驱动电路中的电源电路接收所述电源信号，并根据所述电源信号为所述驱动电路中的时序控制器和过流保护电路提供电能。所述时序控制器接收所述显示信号，根据所述显示信号生成用于输入至显示装置的栅极驱动电路的多个栅极输入信号。所述过流保护电路获取所述多个栅极输入信号，对所述多个栅极输入信号进行连续侦测，在侦测到栅极输入信号出现过流的情况下，向所述电源电路输出第二控制信号。所述电源电路接收所述 第二控制信号，并在所述第二控制信号的控制下，停止接收所述***板输入的电源信号。
在一些实施例中，过流保护方法还包括：所述过流保护电路对所述多个栅极输入信号进行连续侦测，在侦测到栅极输入信号出现异常的情况下，向所述***板输出第三控制信号。所述***板接收所述第三控制信号，并在所述第三控制信号的控制下，停止接收信号源输入的信号。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据相位正常的DE信号产生CLK信号和STV信号的时序图；
图1B为根据相位异常的DE信号产生CLK信号和STV信号的时序图；
图2为根据一些实施例的显示装置的结构图；
图3为根据一些实施例的过流保护电路的一种结构图；
图4A为根据一些实施例的过流保护电路的侦测时序图；
图4B为根据一些实施例的过流保护电路的侦测时序图；
图5A为根据一些实施例的过流保护电路的另一种结构图；
图5B为根据一些实施例的过流保护电路的又一种结构图；
图6为根据一些实施例的过流保护电路中采样子电路的结构图；
图7为根据一些实施例的过流保护电路的又一种结构图；
图8A为根据一些实施例的采样筛选单元的一种结构图；
图8B为根据一些实施例的采样筛选单元的另一种结构图；
图9为根据一些实施例的判断单元的一种结构图；
图10A根据一些实施例的过流保护方法的一种流程图；
图10B根据一些实施例的过流保护方法的另一种流程图；
图11根据一些实施例的过流保护方法的又一种流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地 描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或 超出所述的值。
本公开的一些实施例提供了一种显示装置100，如图2所示，该显示装置100包括：***板1、驱动电路2和显示面板3。
其中，***板1与驱动电路2耦接，被配置为向驱动电路2输出电源信号c2和显示信号c1，以通过驱动电路2控制显示面板3实现显示。在一些实施例中，***板1与视频信号源1’耦接，接收视频信号源1’输出的视频信号c7，根据所接收的视频信号c7生成电源信号c2和显示信号c1。
在一些示例中，显示面板3包括多条栅线GL、多条数据线DL和多个子像素P，多个子像素P设置在显示面板3的显示区，示例性地，多个子像素P呈阵列式布置，每个子像素P设置有像素驱动电路2，沿行方向排列成一排的子像素P与同一条栅线GL耦接，沿列方向排列成一列的子像素P与同一条数据线DL耦接。
在一些实施例中，如图2所示，上述驱动电路2包括：电源电路21、时序控制器22和源极驱动电路23。
电源电路21与显示装置100的***板1和时序控制器22耦接，电源电路21被配置为接收***板1所输入的电源信号c2，并根据电源信号c2为时序控制器22提供电能。
示例性地，电源电路21根据所接收的电源信号c2，生成时序控制器22工作所需要的电源电压，进而将对应的电源电压传输给时序控制器22。
时序控制器22还与栅极驱动电路31和源极驱动电路23耦接，时序控制器22被配置为接收***板1所输入的显示信号c1，根据显示信号c1生成用于输入至显示装置100的栅极驱动电路31的多个栅极输入信号c3。时序控制器22还被配置为根据显示信号c1生成用于输入至源极驱动电路23的多个源极输入信号c4。
栅极驱动电路31与电源电路21和时序控制器22耦接，被配置为接收多个栅极输入信号c3，根据多个栅极输入信号c3生成栅极扫描信号。
源极驱动电路23与电源电路21和时序控制器22耦接，被配置为接收所述多个源极输入信号c4，并根据多个源极输入信号c4生成数据信号。
示例性地，时序控制器22所接收的来自***板1的显示信号c1为LVDS信号，包括DE(Data Enable，数据使能)信号、HS(Hsync，行同步)信号和VS(Vsync，场同步)信号，时序控制器22根据这些信号，生成栅极驱动电路31所需要的多个栅极输入信号c3，以及源极驱动电路23所需要的多个源极输入信号c4。
其中，所述多个栅极输入信号c3是指时序控制器22所输出的控制栅极驱动电路31进行工作的控制信号，通常称为GOA(gate on array，栅极驱动电路集成在阵列基板上)信号。示例性地，多个栅极输入信号c3包括但不限于STV信号(Start Vertical，扫描开启信号)、CPV信号(Clock Pulse Vertical，栅驱动器的时钟信号)，即CLK信号，还包括VDD信号和VSS信号等。在一些示例中，上述信号都不只包括一路信号，例如STV信号包括STV1、STV2…STVn，CLK信号包括CLK1、CLK2…CLKn，VDD信号也同样包括VDD1、VDD2等，根据栅极驱动电路31的具体结构，所需要的栅极输入信号c3的数量也会不同。
其中，所述多个源极输入信号c4是指时序控制器22所输出的控制源极驱动电路23进行工作的控制信号，示例性地，多个栅极输入信号c3包括但不限于STH(Start Horizontal，数据开始信号)、CPH(Clock Pulse Horizontal，源驱动器的时钟信号)，即CLK信号，还包括VDD信号等。
在一些示例中，栅极驱动电路31可以以栅极驱动IC的形式，与显示面板3进行绑定，同样，源极驱动电路23也以源极驱动IC的形式，与显示面板3进行绑定，基于这种设置，驱动电路2在包括电源电路21、时序控制器22和源极驱动电路23的基础上，还包括栅极驱动电路31。
在另一些示例中，栅极驱动电路31可以为GOA电路，也即将上述栅极驱动电路31直接集成在显示面板3的阵列基板中。基于这种设置，显示面板3在包括栅线、数据线和多个子像素的基础上，还包括栅极驱动电路31，驱动电路2不包括栅极驱动电路31。
示例性地，栅极驱动电路31具有多个输出端，一个输出端与显示面板3中的一条栅线GL耦接，栅极驱动电路31根据栅极输入信号c3生成栅极扫描信号，向多条栅线GL输出栅极扫描信号，从而显示面板3中的像素驱动电路2在栅线GL传输的栅极扫描信号的控制下打开，接收数据线DL所传输的数据信号，从而实现显示。
如图2所示，上述电源电路21还与栅极驱动电路31、源极驱动电路23和显示面板3耦接，电源电路21还被配置为接收***板1所输入的电源信号c2，并根据电源信号c2为栅极驱动电路31、源极驱动电路23和显示面板3提供电能。
示例性地，电源电路21根据所接收的电源信号c2，生成栅极驱动电路31、源极驱动电路23和显示面板3各自工作所需要的电源电压，进而将对应的电源电压分别传输给栅极驱动电路31、源极驱动电路23和显示面板3，为 栅极驱动电路31、源极驱动电路23和显示面板3供电。
在一些情况下，***板1输入至时序控制器22的显示信号c1可能会出现异常，而栅极输入信号c3是根据显示信号c1生成的，这样就会导致栅极输入信号c3中的某一个或者某几个栅极输入信号c3的电压(或电流)大于其正常状态下的电压(或电流)值，即栅极输入信号c3出现过流等异常情况。
示例性地，时序控制器22根据显示信号c1生成栅极驱动电路31所需要的多个栅极输入信号c3，以及源极驱动电路23所需要的多个源极输入信号c4，例如，时序控制器22根据DE信号生成多个栅极输入信号c3中的STV信号和CLK信号，在***板1传输至时序控制器22的显示信号c1中的DE信号出现相位宽度异常的情况下，参照DE信号所生成的STV信号和CLK信号会出现相位紊乱。
如图1A所示，以多个栅极输入信号c3中的STV信号和CLK信号为例，在正常情况下，DE信号保持正常的相位宽度，时序控制器22根据DE信号所生成的STV信号和CLK信号的逻辑为：STV信号参考DE信号的第二个上升沿(rising)，STV信号在DE信号的第二个上升沿(rising)处产生的首个上升沿，从而持续一段时间的有效电平。CLK信号参考参考DE信号的第一个上升沿(rising)，CLK信号为从DE信号的第一个上升沿处固定数1843个pixel clock(像素时钟)敲出上升沿，从而持续一段时间的有效电平。这样，如图1A所示，STV信号的上升沿的出现时间早于CLK信号的上升沿的出现时间。
而在DE信号相位宽度异常的情况下，如图1B所示，DE信号的低电平宽度过长，而时序控制器22根据DE信号生成STV信号和CLK信号的逻辑不变，这样，就会造成STV信号的上升沿的出现时间与CLK信号的上升沿的出现时间比较相近，从而出现相位紊乱，即多个栅极输入信号c3出现了异常。
从而，栅极驱动电路31在出现异常的多个栅极输入信号c3的控制下会出现MultiGate(多门异常开启)现象，这种MultiGate现象会使得栅极驱动电路31异常输出产生过高电流，该过高电流经过驱动电路2和显示面板3连接形成的回路反馈给栅极输入信号c3，导致栅极输入信号c3出现过流异常。
在栅极驱动电路31输出异常，出现MultiGate现象的情况下，会导致显示面板3出现异常扫描而出现异常的显示画面，而显示面板3在异常扫描驱动下长时间显示会造成难以恢复的损伤，例如出现液晶极化或者TFT(Thin Film Transistor，薄膜晶体管)特性漂移等损伤，降低显示面板3的使用寿命。
基于此，如图2所示，本公开的一些实施例所提供的驱动电路2还包括 过流保护电路25，过流保护电路25与电源电路21和时序控制器22耦接，过流保护电路25被配置为获取时序控制器22所输出的多个栅极输入信号c3，对所述多个栅极输入信号c3进行连续侦测，在侦测到栅极输入信号c3出现过流的情况下，向电源电路21输出第二控制信号c5。
其中，第二控制信号c5用于切断显示装置100的***板1向显示装置100的驱动电路2的信号输入。
电源电路21还与过流保护电路25耦接，电源电路21还被配置为接收过流保护电路25输出的第二控制信号c5，并在第二控制信号c5的控制下，停止接收***板1输入的电源信号c2。
由于在驱动电路2中，电源电路21被配置为向时序控制器22、过流保护电路25、源极驱动电路23等驱动电路2所包括的器件，以及显示面板3和栅极驱动电路31提供电能，一旦断电，则驱动电路2所包括的多个器件、以及显示面板3均无法运转，无法实现其功能。因此，电源电路21在接收第二控制信号c5后，在第二控制信号c5的控制下，停止接收***板1输入的电源信号c2，这样电源电路21无法根据电源信号c2生成各器件工作所需要的电源电压，无法为时序控制器22等提供电能，从而时序控制器22、过流保护电路25、源极驱动电路23等驱动电路2所包括的器件均停止工作，例如，时序控制器22停止向栅极驱动电路31输出栅极输入信号c3，停止向源极驱动电路23输入源极输入信号c4。
基于上述介绍，本公开的一些实施例所提供的显示装置100包括***板1、驱动电路2和显示面板3，驱动电路2中设置有过流保护电路25，在显示装置100开始工作后，过流保护电路25开启侦测流程，在显示装置100的工作过程中，过流保护电路25获取时序控制器22所输出的多个栅极输入信号c3，对所述多个栅极输入信号c3进行连续侦测，在侦测到栅极输入信号c3出现过流的情况下，向电源电路21输出第二控制信号c5，从而电源电路21接收过流保护电路25输出的第二控制信号c5，并在第二控制信号c5的控制下，停止接收***板1输入的电源信号c2。
这样，电源电路21停止向时序控制器22以及栅极驱动电路31、源极驱动电路23、显示面板3提供电能，从而使得驱动电路2以及显示面板3停止工作，具体表现为时序控制器22停止生成栅极输入信号c3，并停止向栅极驱动电路31输出栅极输入信号c3，从而出现异常的栅极输入信号c3能够被及时截断，不会输入栅极驱动电路31，避免了异常的栅极输入信号c3对栅极驱动电路31造成不良影响，避免栅极驱动电路31输出异常而出现MultiGate现 象，进而导致显示面板3出现异常扫描而出现异常的显示画面，避免显示面板3在异常扫描驱动下长时间显示而造成难以恢复的损伤，例如出现液晶极化或者TFT特性漂移等损伤，能够保护显示面板3，延长显示面板3的使用寿命。
也就是说，本公开所提供的显示装置100，通过在驱动电路2中设置过流保护电路25，对栅极输入信号c3进行连续侦测，确保由于显示信号c1出现异常而造成的栅极输入信号c3的过流异常能够及时被侦测到，并在侦测到异常的瞬间输出第二控制信号c5，切断电源信号c2的输入，停止显示装置100的电能供应，从而保护显示面板3和整个驱动电路2，避免显示装置100继续运行，对显示面板3及驱动电路2产生不良影响。
在一些实施例中，上述***板1还与驱动电路2中的过流保护电路25耦接，上述过流保护电路25还被配置为对所述多个栅极输入信号c3进行连续侦测，在侦测到栅极输入信号c3出现过流的情况下，向***板1输出第三控制信号c6。其中，第三控制信号c6用于切断信号源向所述***板1的信号输入。
***板1还被配置为接收第三控制信号c6，并在第三控制信号c6的控制下，停止接收视频信号源1’输入的视频信号c7。
***板1向时序控制器22输出的显示信号c1出现异常，而导致栅极输入信号c3出现异常。***板1输出的显示信号c1出现异常可能是由于***板1所接收的来自视频信号源1’的视频信号c7所导致的，在过流保护电路25侦测到栅极输入信号c3出现过流异常的情况下，向电源电路21输出第二控制信号c5，使电源电路21停止接收***板1输入的电源信号c2，切断电能的基础上，过流保护电路25还向***板1输出第三控制信号c6，从而***板1在第三控制信号c6的控制下，停止接收视频信号源1’输入的视频信号c7，这样***板1能够在源头截断原始信号源的输入，提高整个显示装置100的过流保护***的可靠性，且能减少***板1的无效驱动，避免可能出现异常的源信号对***板1造成不良影响。
基于上述显示装置100和驱动电路2，以下对过流保护电路25进行具体介绍。
如图3所示，本公开的一些实施例提供一种过流保护电路25，该过流保护电路25被配置为对输入至栅极驱动电路31的多个栅极输入信号c3进行连续侦测。示例性地，过流保护电路25在如图4A和图4B所示的侦测时序信号的控制下，在每个时钟周期内对多个栅极输入信号c3进行一次侦测，以实现 连续侦测。例如，在侦测时序信号的下降沿或者上升沿来临时，在下一个时钟周期T(方波周期)内，进行再一次侦测，本公开以在侦测时序信号的下降沿来临时开启侦测为例进行说明。
如图3所示，该过流保护电路25包括：采样子电路251、延时判断子电路252和计数控制子电路253。
采样子电路251被配置为，获取所述多个栅极输入信号c3，筛选出所述多个栅极输入信号c3中电压值大于第一预设电压值的一个栅极输入信号c3，作为采样栅极输入信号；及，根据采样栅极输入信号生成并输出第一控制信号。其中，所述第一预设电压值为，栅极输入信号c3的电压正常状态与过流状态的临界电压值。
在一个时钟周期T的侦测过程中，在所述多个栅极输入信号c3的每个栅极输入信号c3的电压值均小于或等于第一预设电压值的情况下，采样子电路251不输出信号，在侦测时序信号的下一个下降沿来临时，进入下一个时钟周期T的侦测。
其中，栅极输入信号c3的电压正常状态是指，在***板1输入时序控制器22的显示信号c1没有出现异常的情况下，时序控制器22根据显示信号c1生成的多个栅极输入信号c3为正常的信号，不会出现相位紊乱，从而栅极输入信号c3不会出现过流异常，栅极输入信号c3的电压处于正常状态。
栅极输入信号c3的电压过流状态是指，如前所述，在***板1输入时序控制器22的显示信号c1出现异常的情况下，时序控制器22根据显示信号c1生成的多个栅极输入信号c3会出现相位紊乱，从而栅极驱动电路31在出现异常的栅极输入信号c3的控制下会出现MultiGate现象，这种会使得栅极驱动电路31异常输出产生过高电流，进而导致栅极输入信号c3中的某一个或者某几个栅极输入信号c3的电压(或电流)过大，栅极输入信号c3的电压处于过流状态。
设置第一预设电压值，一旦侦测到多个栅极输入信号c3中有一个栅极输入信号c3的电压值大于第一预设电压值，即认为栅极输入信号c3出现过流异常，将所筛选出的栅极输入信号c3作为采样栅极输入信号。
作为一种可能的设计，还可以通过筛选出所述多个栅极输入信号c3中电流值大于第一预设电流值的一个栅极输入信号c3，作为采样栅极输入信号；其中，第一预设电流值为栅极输入信号c3的电流正常状态与过流状态的临界电流值，关于第一预设电流值的具体解释可参照上述对于第一预设电压值的解释。由于信号的电流与电压之间存在对应关系，可以相互转换，因此通过 侦测栅极输入信号c3的电流或者电压都可以判断其是否处于过流异常。本公开以电压侦测栅极输入信号c3的电压为例进行示例性说明。
在一些示例中，第一预设电压值为可根据实际情况进行设定的阈值，由于异常的栅极输入信号c3会使栅极驱动电路31输出异常而出现MultiGate现象，进而导致显示面板3出现异常扫描而出现异常的显示画面，显示面板3在长时间非正常显示下会对其内部结构造成损伤，因此，可以根据显示面板3的尺寸及分辨率，对第一预设电压值进行相应设定。
延时判断子电路252与采样子电路251耦接。延时判断子电路252被配置为，接收采样子电路251输出的第一控制信号，对第一控制信号进行第一预设时间的延时，判断经过延时的第一控制信号的电压值相较延时前是否有下降，若否，则输出计数信号。
延时判断子电路252判断经过延时的第一控制信号的电压值相较延时前是否有下降，若是，则不输出信号，在下一个时钟来临时，进入下一个时钟周期的侦测。
采样子电路251在对多个栅极输入信号c3进行侦测时，栅极输入信号c3有可能会受到一些因素的影响，在输入至采样子电路251的瞬间出现电压(或电流)瞬间变高的情况，该电流称为inrush(浪涌)电流，即突然的尖峰电流，例如在显示装置100启动的瞬间，输入至驱动电路2的电源电路21的电流会出现一个峰值，进而导致其他信号也出现峰值。该尖峰电流远远大于稳态输入电流。
从而，有可能出现以下情况，在本身电压值小于第一预设电压值的某个栅极输入信号c3(一个信号的电流与电压是相关联的)在出现尖峰电流的情况下，其电压值升高至大于第一预设电压值，从而将该栅极输入信号c3作为采样栅极输入信号，这样，所选出的采样栅极输入信号并不是真正的电压值大于第一预设电压值的栅极输入信号c3，而是在出现尖峰电流的情况下所选出的采样栅极输入信号，从而根据该错误的采样栅极输入信号所生成的第一控制信号也会出现不准确的问题，从而导致侦测结果不准确。以下称在出现尖峰电流的情况下得到的采样栅极输入信号为错误的采样栅极输入信号，在稳态下得到的采样栅极输入信号为正确的采样栅极输入信号。
一般尖峰电流仅会持续很短的时间，在这段时间之后，尖峰电流就会由较高的电流值(或电压值)下降为原本的值，通过延时判断子电路252对第一控制信号做延时处理，判断经过延时的第一控制信号的电压值相较延时前是否有下降，若电压值有下降，则说明所接收的第一控制信号为根据错误的 采样栅极输入信号而生成的，该采样栅极输入信号并非真正处于过流状态，因此延时判断子电路252在该情况下不输出信号。若电压值没有下降，则说明该第一控制信号是根据正确的采样栅极输入信号生成的，该采样栅极输入信号在稳态下的电压值大于第一预设电压值，因此真正处于过流状态。
需要说明的是，由于第一控制信号是根据采样栅极输入信号生成的，因此第一控制信号能够反映采样栅极输入信号的情况，对第一控制信号做延时处理并判断其延时前后的电压值是否下降可以得知所选出的采样栅极输入信号是否准确。
根据尖峰电流所能持续的时长，示例性地，第一预设时间可以为3μs～5μs。
通过设置延时判断子电路252对采样子电路251输出的第一控制信号做延时以及判断，能够保证所得到的第一控制信号的准确性，摒弃在出现尖峰电流的情况下得到的采样栅极输入信号，从而保证了采样栅极输入信号的准确性，从而提高了侦测的准确度。
计数控制子电路253与延时判断子电路252耦接，计数控制子电路253被配置为，接收延时判断子电路252输出的计数信号，根据计数信号进行计数。在计数次数达到预设次数的情况下，输出第二控制信号c5，第二控制信号c5用于切断显示装置100的***板1向显示装置100的驱动电路2的信号输入。
在延时判断子电路252输出计数信号后，计数控制子电路253开始计数，在计数次数达到预设次数的情况下，例如预设次数为3次，则说明在连续三个时钟周期T内，均侦测到至少有一个栅极输入信号c3的电压值大于第一预设电压值的情况，这样，就说明栅极输入信号c3出现了过流异常至少持续了三个时钟周期T，在这种情况下，输出第二控制信号c5，切断显示装置100的***板1向显示装置100的驱动电路2的信号输入，从而使得驱动电路2以及显示面板3停止工作，保护栅极驱动电路31和显示面板3。示例性地，第二输入信号被配置为使电源电路21停止接收***板1输入的电源信号c2，以停止向驱动电路2及显示面板3提供电能。
在一些实施例中，计数控制子电路253还被配置为，在计数次数没有达到所述预设次数的情况下，判断在此之后的第二预设时间之内计数次数是否有增加，若否，则将所述计数次数清零。
示例性地，在预设次数为3次的情况下，若当前时刻计数次数为2，即在连续两个时钟周期T内侦测到栅极输入信号c3出现过流异常，若在下一个时 钟周期T内计数没有增加，即在第三个时钟周期T内栅极输入信号c3没有出现过流异常，则将计数次数清零。例如，一个时钟周期T的时长为50μs，在计数次数不满足预设次数的情况下，判断在此之后的50μs之内计数次数是否有增加，若否，则将计数次数清零。
若侦测到栅极输入信号c3出现过流异常仅持续一个时钟周期T，则有可能是因为栅极输入信号c3受到扰动出现了暂时的电压升高或者电流升高的情况，而并非是由于显示信号c1的异常(例如显示信号c1的相位宽度异常)导致的过流异常，若在侦测到栅极输入信号c3出现过流异常的瞬间就直接输出第二控制信号c5，会导致侦测结果不准确，输出不必要的第二控制信号c5而影响显示装置100的正常工作。通过设置计数控制子电路253，在计数次数达到预设次数的情况下输出第二控制信号c5，切断显示装置100的***板1向显示装置100的驱动电路2的信号输入，即在栅极输入信号c3出现过流异常的时长至少维持特定的时间的情况下，输出第二控制信号c5，这样能够确保当前所侦测到的栅极输入信号c3出现过流异常是由于显示信号c1的异常而导致的，提高了所侦测到的栅极输入信号c3出现过流异常的准确性，避免输出不必要的第二控制信号c5。
本公开的一些实施例所提供的过流保护电路25包括依次耦接的采样子电路251、延时判断子电路252和计数控制子电路253，通过采样子电路251、延时判断子电路252和计数控制子电路253对输入至栅极驱动电路31的多个栅极输入信号c3进行连续侦测，从而能够实现对栅极输入信号c3的实时侦测，并在栅极输入信号c3出现过流异常的情况下，能够被准确地侦测到，并在侦测到出现异常的情况下输出第二控制信号c5，切断电源信号c2的输入，停止显示装置100的电能供应，从而保护显示面板3和整个驱动电路2。并且，通过延时判断子电路252摒弃栅极输入信号c3出现尖峰电流的情况，通过设置计数控制子电路253，在达到预设次数的情况下输出第二控制信号c5，避免栅极输出信号暂时收到扰动的情况下做出错误的响应，提高侦测结果的准确性。
在一些实施例中，如图5A所示，采样子电路251包括：信号筛选单元2511。信号筛选单元2511被配置为接收所述多个栅极输入信号c3，筛选出所述多个栅极输入信号c3中电压值大于第一预设电压值的一个栅极输入信号c3，作为采样栅极输入信号。
在上述实施例中，通过信号筛选单元2511选出多个栅极输入信号c3中电压值大于第一预设电压值的一个栅极输入信号c3，作为采样栅极输入信号， 并且，将该采样栅极输入信号作为第一控制信号输出。信号筛选单元2511与延时判断子电路252耦接，通过延时判断子电路252判断对该采样栅极输入信号进行延时，判断经过延时的采样栅极输入信号的电压值相较延时前是否有下降，从而能够判断该采样栅极输入信号的电压值大于第一预设电压值的时长是否超过第一预设时间，得知所得到的采样栅极输入信号是否准确。
在一些实施例中，如图5B所示，采样子电路251还包括：与信号筛选单元2511耦接的信号处理单元2512。信号处理单元2512被配置为接收所述信号筛选单元2511输出的采样栅极输入信号，对采样栅极输入信号进行去干扰和放大处理，根据经过去干扰和放大处理的采样栅极输入信号和第二预设电压值生成第一控制信号，并输出第一控制信号。其中，第二预设电压值为根据放大处理步骤中的放大倍数得到的。
信号筛选单元2511输出的采样栅极输入信号为多个栅极输入信号c3中的某一个栅极输入信号c3，该信号为没有经过任何处理而被直接输出的信号，可能会存在不稳定，信号强度较微弱的问题，在上述实施例中，采样子电路251包括信号筛选单元2511和信号处理单元2512，信号筛选单元2511选出采样栅极输入信号之后，信号处理单元2512接收该采样栅极输入信号，并对采样栅极输入信号进行处理，以去除采样栅极输入信号中的干扰信息，并将采样栅极输入信号放大，使得采样栅极输入信号更稳定，根据经过处理的采样栅极输入信号和第二预设电压值生成第一控制信号，相较没有经过任何处理的采样栅极输入信号，该第一控制信号为恒定的电压信号，更加稳定，从而在后续的操作中，能够提高整个侦测流程的稳定性和准确性。
在一些示例中，如图6所示，信号处理单元2512包括：降噪子单元2512a、放大子单元2512b和比较子单元2512c。
降噪子单元2512a与信号筛选单元2511耦接，降噪子单元2512a被配置为接收信号筛选单元2511输出的采样栅极输入信号，对采样栅极输入信号进行去干扰处理，并输出经过去干扰处理的采样栅极输入信号。这样，能够去除采样栅极输入信号中的干扰信息，滤除杂讯，使得采样栅极输入信号更加纯净，更加准确。
示例性的，如图7所示，降噪子单元2512a包括第一电阻R1、第二电阻R2、发光二极管D和电容器C，其中，第一电阻R1的第一端与降噪子单元2512a的信号输入端耦接，第一电阻R1的第二端与第二电阻R2的第一端耦接，还与第一电压信号端VCC耦接，第二电阻R2的第二端与降噪子单元2512a的信号输出端耦接，发光二极管D的阴极与第二电阻R2的第二端耦接，发光 二极管D的阳极接地，电容器C的第一端的第二电阻R2的第二端耦接，电容器C的第二端接地。上述第一电阻R1、第二电阻R2、发光二极管D和电容器C的组合，具有类似滤波器的功能，能够对采样栅极输入信号进行去干扰处理。
如图6所示，放大子单元2512b与降噪子单元2512a耦接，放大子单元2512b被配置为接收降噪子单元2512a输出的经过去干扰处理的采样栅极输入信号，对经过去干扰处理的采样栅极输入信号进行放大处理，并输出经过去干扰和放大处理的采样栅极输入信号。
通过放大子电路2512b，对经过去干扰处理的采样栅极输入信号进行放大处理，能够增大信号强度，将比较微弱的信号转化为比较强且稳定的信号，便于后续子电路对采样栅极输入信号的获取和处理。
示例性的，如图7所示，放大子电路2512b包括第一运算放大器S1、第三电阻R3和第四电阻R4，第一运算放大器S1具有反相输入端、同相输入端和输出端，其中，第一运算放大器S1的反相输入端为放大子电路2512b的信号输入端，第一运算放大器S1的输出端为放大子电路2512b的信号输出端，第一运算放大器S1的同相输入端与第三电阻R3耦接，第三电阻R3的另一端接地，第四电阻R4耦接于第一运算放大器S1的同相输入端和输出端之间。其中第四电阻R4为可变电阻，通过调节第四电阻R4的阻值可以根据需要调整放大子电路2512b的放大倍数。
如图6所示，比较子单元2512c与放大子单元2512b耦接，比较子单元2512c被配置为接收放大子单元2512b输出的经过去干扰和放大处理的采样栅极输入信号，根据经过去干扰和放大处理的采样栅极输入信号和第二预设电压值生成第一控制信号，并输出第一控制信号。
示例性地，将上述比较子单元2512c设定为：将采样栅极输入信号与第二预设电压值作比较，在采样栅极输入信号大于第二预设电压值得情况下，生成第一控制信号。由于采样栅极输入信号为所筛选出的电压值大于第一预设电压值的栅极输入信号c3，通过信号处理子电路仅是对采样栅极输入信号做处理，使其更稳定，因此，需要根据放大子单元2512b的放大倍数确定第二预设电压值，以保证采样栅极输入信号大于第二预设电压值，从而确保比较子单元2512c能够输出第一控制信号。
同理，在比较子单元2512c设定为：将采样栅极输入信号与第二预设电压值作比较，在采样栅极输入信号小于第二预设电压值得情况下，生成第一控制信号，那么需要根据放大子单元2512b的放大倍数确定第二预设电压值， 以保证采样栅极输入信号小于第二预设电压值，从而比较子单元2512c能够输出第一控制信号。
示例性的，如图7所示，比较子单元2512c包括第二运算放大器S2、第五电阻R5和第六电阻R6。其中，第二运算放大器S2具有反相输入端、同相输入端和输出端，其中，第二运算放大器S2的反相输入端为比较子单元2512c的信号输入端，第二运算放大器S2的输出端为比较子单元2512c的信号输出端，第二运算放大器S2还与第二预设电压信号端IA2耦接，以及接地。第五电阻R5的第一端与第一电压信号端耦接，第二端与第二运算放大器S2的同相输入端耦接。第六电阻R6的第一端与第五电阻R5的第二端耦接，第六电阻R6的第二端接地，经过第五电阻R5和第六电阻R6的分压作用，输入至第二运算放大器S2的同相输入端的信号的电压为参考电压，该参考电压小于第一电压信号端传输第一电压信号的电压。第二运算放大器S2的反相输入端接收放大子电路2512b输出的经过去干扰和放大处理的采样栅极输入信号，示例性地，在经过去干扰和放大处理的采样栅极输入信号大于参考电压，且大于第二预设电压值的情况下，第二运算放大器S2输出第一控制信号。
第一控制信号为比较子单元2512c进行比较输出的一个恒定的电压信号，例如为高电压信号，相比采样栅极输入信号，恒定的第一控制信号更加稳定，更便于后续延时判断子电路252对其进行操作，以输出计数信号至计数子电路，使计数控制子电路253计数。
在一些实施例中，信号筛选单元2511被配置为接收所述多个栅极输入信号c3，并分别将多个栅极输入信号c3与第一预设电压值作比较，在得到某一栅极输入信号c3的电压值大于第一预设电压值时，将该栅极输入信号c3作为采样栅极输入信号。
在另一些实施例中，信号筛选单元2511被配置为接收所述多个栅极输入信号c3，筛选出所述多个栅极输入信号c3中电压值最大的一个栅极输入信号c3，将所筛选出的栅极输入信号c3的电压值与第一预设电压值比较。在所筛选出的栅极输入信号c3的电压值大于第一预设电压值的情况下，将该栅极输入信号c3作为采样栅极输入信号。
在上述信号筛选单元2511中，先将多个栅极输入信号c3中电压值最大的一个栅极输入信号c3筛选出，以下称为最大的栅极输入信号c3，再将该最大的栅极输入信号c3与第一预设电压值比较，若最大的栅极输入信号c3的电压值小于第一预设电压值，则说明多个栅极输入信号c3均没有出现过流异常。若该最大的栅极输入信号c3的电压值大于第一预设电压值，则说明由一个或 某几个栅极输入信号c3出现了了过流异常，将该最大的栅极输入信号c3作为采样栅极输入信号输出。这样，可以节省筛选步骤，节省筛选时间，并且，所得到的结果的准确性较高。
在一些实施例中，信号筛选单元2511的具体结构为：所述多个栅极输入信号c3的数量为x，信号筛选单元2511包括n级筛选器组，第i级筛选器组包括2 (n-i)个筛选器；其中，x为大于或等于3的正整数，n为大于或等于2的正整数，i在[1，n]的正整数的集合内依次取值。
由于栅极驱动电路31在驱动时，所需要的多个栅极输入信号c3至少包括CLK信号、STV信号和VDD信号，因此多个栅极输入信号c3的数量为至少3个。
一个筛选器具有两个输入端和一个输出端。第(i+1)级筛选器组中的一个筛选器的两个输入端与第i级筛选器组中的两个筛选器的输出端分别耦接。
示例性地，如图8A所示，多个栅极输入信号c3的数量为8(例如多个栅极输入信号c3包括CLK1、CLK2、CLK3、CLK4、STV1、STV2、VDD1和VDD2)，信号筛选单元2511包括3级筛选器组，第1级筛选器组包括4个筛选器(AMP1、AMP2、AMP3、AMP4)，第2级筛选器组包括2个筛选器(AMP5和AMP3)，第1级筛选器组包括1个筛选器(AMP7)。第2级筛选器组中的一个筛选器的两个输入端与第3级筛选器组中的两个筛选器的输出端分别耦接，第1级筛选器组中的一个筛选器的两个输入端与第2级筛选器组中的两个筛选器的输出端分别耦接。
第1级筛选器组被配置为获取所述多个栅极输入信号c3，第1级筛选器组中的各筛选器被配置为接收所述多个栅极输入信号c3中的两个栅极输入信号c3，并将所接收的两个栅极输入信号c3中电压值较大的一个栅极输入信号c3输出。
示例性地，如图8A所示，第1级筛选器组中的各筛选器被配置为接收所述多个栅极输入信号c3中的两个栅极输入信号c3，例如筛选器AMP1接收两个栅极输入信号STV0和STV1。在多个栅极输入信号c3的数量为8，第1级筛选器组包括4个筛选器的情况下，该4个筛选器中的每个筛选器接收该8个栅极输入信号c3中的两个栅极输入信号c3，并将所接收的两个栅极输入信号c3中电压值较大的一个栅极输入信号c3输出。
由于每个筛选器具有两个输入端，能够接收两个栅极输入信号c3，第1级筛选器组包括2 (n-1)个筛选器，每个筛选器被配置为接受两个栅极输入信号c3，因此筛选子电路所包括的筛选器的级数与栅极输入信号c3的数量的关系 为：在信号筛选单元2511包括n级筛选器组的情况下，第1级筛选器组最多能够接收2 n个栅极输入信号c3。例如在信号筛选单元2511包括3级筛选器组的情况下，第1级筛选器组包括4个筛选器，第1级筛选器组最多能够接收8个栅极输入信号c3。在信号筛选单元2511包括4级筛选器组的情况下，第1级筛选器组包括8个筛选器，第1级筛选器组最多能够接收16个栅极输入信号c3。
在多个栅极输入信号c3的数量为偶数的情况下，多个栅极输入信号c3以每两个为一组，分别输入第一级筛选器组中的多个筛选器，以进行比较。
在多个栅极输入信号c3的数量为奇数的情况下，例如多个栅极输入信号c3的数量为7个，该7个栅极输入信号c3中的6个栅极输入信号c3分为3组，每组包括两个栅极输入信号c3，分别输入至第一级筛选器组中的三个筛选器，该7个栅极输入信号c3中剩余的一个栅极输入信号c3输入至第一级筛选器组中的一个筛选器，该剩余的一个栅极输入信号c3通过该筛选器直接进入第二极筛选器组，从而与上述6个栅极输入信号c3中进入第二极筛选器组的某一个栅极输入信号c3作比较。
第i+1级筛选器组被配置为接收第i级筛选器组所输出的栅极输入信号c3，第i+1级筛选器组中的各筛选器被配置为，接收所述第i级筛选器组所输出的栅极输入信号c3中的两个栅极输入信号c3，并将所接收的两个栅极输入信号c3中电压值较大的一个栅极输入信号c3输出。
如图8A所示，第2级筛选器组被配置为接收第1级筛选器组所输出的栅极输入信号c3，第2级筛选器组中的2个筛选器均被配置为，接收第1级筛选器组所输出的栅极输入信号c3中的两个栅极输入信号c3，并将所接收的两个栅极输入信号c3中电压值较大的一个栅极输入信号c3输出。
第n级筛选器组中的筛选器被配置为接收第n-1级筛选器组输出的两个栅极输入信号c3，筛选出该两个栅极输入信号c3中电压值较大的一个栅极输入信号c3，并将所筛选出的栅极输入信号c3的电压值与所述第一预设电压值比较，在该栅极输入信号c3的电压值大于所述第一预设电压值的情况下，将该栅极输入信号c3作为采样栅极输入信号。
第n级筛选器组为最后一级筛选器组，如图8A所示，第3级筛选器组与第一预设电压端IA1耦接，被配置为接收第2级筛选器组输出的两个栅极输入信号c3，筛选出该两个栅极输入信号c3中电压值较大的一个栅极输入信号c3，这样就筛选出来多个栅极输入信号c3中的电压值最大的一个栅极输入信号c3。将所筛选出的栅极输入信号c3的电压值与第一预设电压值比较， 在该栅极输入信号c3的电压值大于第一预设电压值的情况下，将该栅极输入信号c3作为采样栅极输入信号。
示例性的，如图8A所示，每个筛选器包括：运算放大器S和两个筛选电阻R，其中，两个筛选电阻R分别与运算放大器S的反相输入端和同相输入端耦接，两个筛选电阻R的另一端分别与该筛选器的两个信号输入端耦接，运算放大器的输出端为该筛选器的输出端。
上述信号筛选单元2511通过设置多级筛选器组，对所接收的多个栅极输入信号c3进行层层筛选，最终选出电压值最大的一个栅极输入信号c3，若该栅极输入信号c3的电压值大于第一预设电压值，则将其作为采样栅极输入信号。上述筛选器组中，同一级筛选器组中各筛选器是同时工作的，这样能够缩短筛选时长，提高效率。
在一些实施例中，信号筛选单元2511还包括开关控制子单元25111。开关控制子单元25111与第1级筛选器组耦接，被配置为控制第1级筛选器组中的各筛选器打开或关闭。
示例性地，如图8B所示，在信号筛选单元2511包括3级筛选器组，第1级筛选器组包括4个筛选器，则开关控制子单元25111包括4个开关模块K和1个开关信号输出模块H，一个开关模块K与第1级筛选器组中的一个筛选器耦接，开关信号输出模块H与所述4个开关模块耦接，开关信号输出模块H被配置向多个开关模块K分别输出相应的控制信号，以控制所述多个开关模块K的通断，从而控制各开关模块K所耦接的筛选器打开或者关闭。
示例性地，开关模块K包括开关晶体管，开关晶体管的控制极与开关信号输出模块的输出端耦接，开关晶体管的第一极与信号筛选单元的输入端耦接，开关晶体管的第二极与第一极筛选器组中的一个筛选器的输入端耦接。开关晶体管被配置为在开关信号输出模块输出的控制信号的作用下导通或者关闭，以控制其所耦接的筛选器组的打开或关闭。其中，控制信号为高电平信号或者低电平信号。
例如，在所述多个栅极输入信号c3的数量为6个，而信号筛选单元2511包括.级筛选器组的情况下，第1级筛选器组包括4个筛选器，该6个栅极输入信号c3需要三个筛选器，通过开关控制子电路控制其中三个筛选器打开，控制另外四个筛选器关闭，从而能够节省不必要的功耗。
通过这样设置，可以在信号筛选单元2511中设置多级筛选器组，以能够支持对较大数量范围的栅极输入信号c3的侦测，通过开关控制子单元控制第1级筛选器组中的各筛选器打开或关闭，将需要工作的筛选器打开，将闲置的 筛选器关闭，能够节省功耗。
需要说明的是，本公开所提供的信号筛选单元2511的电路结构仅是一种示意，延时单元的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可，上述示例并不能限制本公开的保护范围。
在一些实施例中，如图5B所示，延时判断子电路252包括延时单元2521和判断单元2522。
延时单元2521被配置为接收采样子电路251输出的第一控制信号，对第一控制信号进行第一预设时间的延时，输出经过延时的第一控制信号。
示例性地，如图9所示，延时单元2521包括第一输入端IN1、第二输入端IN2、输出端OUT，第一晶体管TR1、第二晶体管TR2、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第一延时电阻R11、第二延时电阻R12、第三延时电阻R13和第四延时电阻R14。其中，第一延时电阻R11的第一端与第一输入端IN1耦接，第二端第一节点N1耦接。第一电阻耦接于第一节点N1和第二节点N2之间，第二电阻耦接于第一节点N1和第二节点N2之间，第二节点N2接地。第一晶体管TR1的控制极与第一节点N1耦接，第一极与第二节点N2耦接，第二极与第二延时电阻R12的第一端耦接，第二延时电阻R12的第二端与第四节点N4耦接。
第三电容C3耦接于第三节点N3和第四节点N4之间，第二输入端IN2与第三节点N3耦接。第三延时电阻R13耦接于第三节点N3与第四节点N4之间。第四延时电阻R14的第一端与第三节点N3耦接，第二端与第五节点N5耦接。第二晶体管TR2的控制极与第四节点N4耦接，第二晶体管TR2的第一极与第三节点N3耦接，第二晶体管TR2的第二极与第五节点N5耦接。第四电容C4的第一端与第五节点N5耦接，第二端接地。第五节点N5与第六节点N6耦接，第六节点N6与测试点TEST和输出端OUT耦接。其中，测试点TEST被配置为对经过延时的第一控制信号进行测试。
在一些示例中，第一晶体管TR1为PNP型N沟道增强型金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。示例性地，第一晶体管TR1具有如下参数：导通延时(Turn-on delay time)为7ns(最大值Wie14ns),导通上升时长(turn-on rise time)为15ns(最大值为30ns)，关断延时(urn-off delay time)为38ns(最大值为76ns)，关断下降时长(turn-off fall time)为3ns(最大值为6ns)。
第二晶体管TR2为PNP型金属-氧化物半导体场效应晶体管，第二晶体 管TR2可作用电压信号处理，也可针对电流信号处理。第二晶体管TR2的第一极通过标号为1、2、3的三个输入通道与第三节点N3耦接，第二晶体管TR2的第二极通过标号为5、6、7、8、9的输出通道与第五节点N5耦接，标号为4的通道被配置为传输参考电压信号，可以使得经过标号4的通道输入的信号作为参考延迟电压控制。示例性地，第一晶体管TR1具有如下参数：导通延时为5.6ns，导通上升时长为18.4ns，关断延时为46.6ns，关断下降时长为12ns。
第一电容C1、第二电容C2和第三电容C3的容值大小可以根据延时单元2521的电路纹波大小设定，本公开对此并不设限，例如，第一电容C1、第二电容C2和第三电容C3的电容值均为10uf，以应对150mV的纹波。
示例性地，第一延时电阻R11的阻值范围为0K～50K，例如为30K，第二延时电阻R12的阻值范围为10K～25K，例如为22.1K。
在上述延时单元2521中，第一输入端IN1和第二输入端IN2接收第一控制信号，经过延时处理后传输至第六节点N6，从输出端OUT以及测试点TEST输出经过延时的第一控制信号，通过从测试点TEST处对经过延时的第一控制信号进行测试可知，经过延时的第一控制信号的综合测试结果满足puls width(脉冲宽度)≤300us，duty cycle(占空比)≤2％。示例性地，经过延时的第一控制信号相比未经延时的第一控制信号，延后了约3μs。
需要说明的是，本公开所提供的延时单元2521的电路结构仅是一种示意，并且，在实际应用中，上述第一晶体管TR1和第二晶体管TR2的参数、以及电容的容值和电阻的阻值，可以根据实际情况进行相应设置。延时单元2521的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可，上述示例并不能限制本公开的保护范围。
判断单元2522与延时单元2521耦接，判断单元2522被配置为接收采样子电路251输出的第一控制信号，和延时单元2521输出的经过延时的第一控制信号，判断延时前与延时后第一控制信号的电压值是否相等，若是，则输出计数信号。
示例性地，如图5B所示，判断单元2522具有两个输入端口和一个输出端口，两个输入端口被配置为接收采样子电路251输出的第一控制信号和延时单元2521输出的经过延时的第一控制信号，经过判断之后，将计数信号由输出端口输出。
在一些实施例中，如图5A所示，计数控制子电路253还被配置为在计数 次数达到预设次数的情况下，输出第三控制信号c6，第三控制信号c6用于切断信号源向***板1的信号输入。从而***板1根据第三控制信号c6，停止接收视频信号源1’输入的视频信号c7。
这样***板1能够在源头截断原始信号源的输入，提高整个显示装置100的过流保护***的可靠性，且能减少***板1的无效驱动，避免可能出现异常的源信号对***板1造成不良影响。
在一些实施例中，如图5B所示，计数控制子电路253包括：计数单元2531和控制单元2532。
计数单元2531被配置为接收延时判断子电路252输出的计数信号，并根据计数信号进行计数。
控制单元2532与计数单元2531耦接，控制单元2532被配置为存储计数次数，在计数次数达到预设次数的情况下，输出第二控制信号c5。第二控制信号c5用于切断显示装置100的***板1向显示装置100的驱动电路2的信号输入。
控制单元2532还被配置为，在计数次数没有达到预设次数的情况下，判断在此之后的第二预设时间之内计数次数是否有增加，若否，则将计数次数清零。示例性地，第二预设时间为侦测时序信号的一个时钟周期T，例如为50μs。
在一些实施例中，控制单元2532还被配置为在计数次数达到预设次数的情况下，输出第三控制信号c6。第三控制信号c6用于切断视频信号源1’向所述***板1的信号输入。
通过计数单元2531与控制单元2532，可以实现计数功能，并在达到预设次数的情况下，输出第二控制信号c5以及第三控制信号c6，从而切断***板1向显示装置100的驱动电路2的信号输入，保护驱动电路2以及显示面板3，切断信号源向所述***板1的信号输入，从而保护***板1。
需要说明的是，在一些实施例中，本公开所提供的显示装置100可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、 导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些实施例中，本公开所提供的显示装置100可以为液晶显示装置100(Liquid Crystal Display，简称LCD)；该显示装置100也可以为电致发光显示装置100或光致发光显示装置100。在该显示装置100为电致发光显示装置100的情况下，电致发光显示装置100可以为有机电致发光显示装置100(Organic Light-Emitting Diode，简称OLED)或量子点电致发光显示装置100(Quantum Dot Light Emitting Diodes，简称QLED)。在该显示装置100为光致发光显示装置100的情况下，光致发光显示装置100可以为量子点光致发光显示装置100。
本公开的一些实施例还提供了一种过流保护方法，应用于本公开所提供的如图2所示的显示装置100，如图10A和图10B所示，该过流保护方法包括：
S1、显示装置100的***板1向显示装置100的驱动电路2输出电源信号c2和显示信号c1。
S2、驱动电路2中的电源电路21接收电源信号c2，并根据电源信号c2为驱动电路2中的时序控制器22和过流保护电路25提供电能。
在一些实施例中，电源电路21还根据电源信号c2为显示面板3、栅极驱动电路31和源极驱动电路23提供电能。
S3、时序控制器22接收显示信号c1，根据显示信号c1生成用于输入至显示装置100的栅极驱动电路31的多个栅极输入信号c3。
在一些实施例中，时序控制器22还根据显示信号c1生成用于输入至显示装置100的源极驱动***的多个源极输入信号c4。
S4、过流保护电路25获取所述多个栅极输入信号c3，对所述多个栅极输入信号c3进行连续侦测。
在侦测到所述多个栅极输入信号c3出现过流的情况下，向电源电路21输出第二控制信号c5。第二控制信号c5用于切断显示装置100的***板1向显示装置100的驱动电路2的信号输入。
在侦测到所述多个栅极输入信号c3未出现过流的情况下，过流保护电路25不输出信号。
在一些实施例中，如图10B所示，S4还包括：
在侦测到所述多个栅极输入信号c3出现过流的情况下，向***板1输出 第三控制信号c6。第三控制信号c6用于切断视频信号源1’向所述***板1的信号输入。
示例性地，过流保护电路25在如图4A和图4B所示的侦测时序信号的控制下，在每个时钟周期T内对多个栅极输入信号c3进行一次侦测，以实现连续侦测。例如，在侦测时序信号的下降沿或者上升沿来临时，在下一个时钟周期T(方波周期)内，进行再一次侦测。
请参见图11，在一些示例中，S4中过流保护电路25的具体侦测流程包括：
S401、显示装置100正常工作，过流保护电路25对所述多个栅极输入信号c3进行连续侦测，此时过流保护电路25不输出信号。
在显示装置100开启后，驱动电路2和显示面板3进入工作状态，过流保护保护电路25对时序控制器输出的多个栅极输入信号c3进行连续侦测。此步骤中，过流保护电路25不输出信号，即过流保护电路25没有侦测到多个栅极输入信号c3出现过流，显示装置处于正常工作状态下。
以下的S402～S411为在一个时钟周期T内，过流保护电路25所包括的内部器件对多个栅极输入信号c3的侦测流程。
S402、采样子电路251获取多个栅极输入信号c3，并进行筛选。
S403、采样子电路251判断所筛选的栅极输入信号c3的电压值是否大于第一预设电压值。
示例性地，在S402和S403中，采样子电路251中的信号筛选单元2511接收所述多个栅极输入信号c3，筛选出所述多个栅极输入信号c3中电压值最大的一个栅极输入信号c3，将所筛选出的栅极输入信号c3的电压值与第一预设电压值比较，判断所筛选出的栅极输入信号c3的电压值是否大于第一预设电压值。
若结果为否，则说明所述多个栅极输入信号c3没有出现过流异常，返回S401，等待下一个时钟周期的侦测。
若结果为是，则进入S404。
S404、采样子电路251将所述多个栅极输入信号c3中电压值大于第一预设电压值的一个栅极输入信号c3，作为采样栅极输入信号；根据采样栅极输入信号生成并输出第一控制信号。
在一些示例中，采样子电路251包括信号筛选单元2511，信号筛选单元2511筛选出所述多个栅极输入信号c3中电压值大于所述第一预设电压值的一个栅极输入信号c3，作为采样栅极输入信号，并将该采样栅极输入信号作为 第一控制信号输出。
在另一些示例中，采样子电路251包括信号筛选单元2511和信号处理单元2512，信号筛选单元2511筛选出所述多个栅极输入信号c3中电压值大于所述第一预设电压值的一个栅极输入信号c3，作为采样栅极输入信号。信号处理单元2512接收信号筛选单元2511输出的采样栅极输入信号，对采样栅极输入信号进行去干扰和放大处理，根据经过去干扰和放大处理的采样栅极输入信号和第二预设电压值生成第一控制信号，并输出所述第一控制信号。
S405、延时判断子电路252被配置为，接收采样子电路251输出的第一控制信号，对第一控制信号进行第一预设时间的延时。
S406、延时判断子电路252判断经过延时的第一控制信号的电压值相较延时前是否有下降。
示例性地，在采样子电路251包括信号筛选单元2511，将所筛选出的采样栅极输入信号作为第一控制信号输出的情况下，在该步骤中，实际上是判断采样栅极输入信号的电压值大于第一预设电压值的时长是否大于第一预设时间。
若结果为是，则说明所选出的采样栅极输入信号并不是真正的电压值大于第一预设电压值的栅极输入信号c3，而是在出现尖峰电流的情况下所选出的采样栅极输入信号，从而根据该错误的采样栅极输入信号所生成的第一控制信号也不准确，此时多个栅极输入信号c3并没有真正出现过流，因此返回S401，等待下一个时钟周期的侦测。
若结果为否，则进入S407。
S407、延时判断子电路252输出计数信号。
S408、计数控制子电路253接收延时判断子电路252输出的计数信号，并根据计数信号进行计数。
S409、计数控制子电路253判断计数次数是否达到预设次数。
示例性地，预设次数为3次，若结果为是，则说明在连续三个时钟周期T内，均侦测到至少有一个栅极输入信号c3的电压值大于第一预设电压值的情况，这样，就说明栅极输入信号c3出现了过流异常至少持续了三个时钟周期T，进入S412：计数控制子电路253向电源电路21输出第二控制信号c5。或者，计数控制子电路253向电源电路21输出第二控制信号c5，以及，向***板1输出第三控制信号c6。
若结果为否，则说明出现至少有一个栅极输入信号c3的电压值大于第一预设电压值的情况的次数不足，例如，在预设次数为3次的情况下，若此时 计数次数为2，此时进入S410。
S410、计数控制子电路253判断在此之后的第二预设时间之内计数次数是否有增加。
示例性地，第二预设时间为一个时钟周期T，例如为50μs。在计数次数不足预设次数的情况下，判断在此之后的一个时钟周期T内，计数次数是否又增加，以判断在该时钟周期T，是否再一次侦测到多个栅极输入信号c3出现过流异常。
若是，则返回S409，计数控制子电路253判断计数次数是否达到预设次数。
若否，则进入S411。
S411、计数控制子电路253将计数次数清零，并且，返回S401，所述多个栅极输入信号c3没有出现过流异常，等待下一个时钟周期的侦测。
在S4之后，该过流保护方法还包括：S5和S5’。
S5、电源电路21接收第二控制信号c5，并在第二控制信号c5的控制下，停止接收***板1输入的电源信号c2。
从而，电源电路21停止向时序控制器22以及栅极驱动电路31、源极驱动电路23、显示面板3提供电能，从而使得驱动电路2以及显示面板3停止工作，从而时序控制器22无法生成多个栅极输入信号c3，无法向栅极驱动电路31提供出现过流异常的多个栅极输入信号c3，从而出现异常的多个栅极输入信号c3能够被及时截断，不会输入栅极驱动电路31，避免了异常的多个栅极输入信号c3对栅极驱动电路31造成不良影响，进而对显示面板3造成不良影响。
S5’、***板1接收第三控制信号c6，并在第三控制信号c6的控制下，停止接收信号源输入的信号。从而，***板1在信号源头切断输入，进一步避免了可能出现异常的信号对显示装置100的不良影响。
本公开所提供的显示装置100的过流保护方法，能够通过过流保护电路25，对栅极输入信号c3进行连续侦测，确保由于显示信号c1出现异常而造成的栅极输入信号c3的过流异常能够及时被侦测到，并在侦测到异常的瞬间输出第二控制信号c5，从而电源电路21在第二控制信号c5的控制下，停止接收***板1输入的电源信号c2，切断***板1向电源电路21的电源信号c2的输入，停止显示装置100的电能供应，从而保护显示面板3和整个驱动电路2，避免显示装置100继续运行，对显示面板3及驱动电路2产生不良影响。以及，在侦测到异常的瞬间输出第三控制信号c6，***板1在第三控制信号 c6的控制下，停止接收信号源输入的信号，进一步避免了可能出现异常的信号源输入的信号对显示装置100的不良影响，还能保护***板1。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种过流保护电路，被配置为对输入至栅极驱动电路的多个栅极输入信号进行连续侦测；所述过流保护电路包括：
    采样子电路；所述采样子电路被配置为，获取所述多个栅极输入信号，筛选出所述多个栅极输入信号中电压值大于第一预设电压值的一个栅极输入信号，作为采样栅极输入信号；及，根据所述采样栅极输入信号生成并输出第一控制信号；其中，所述第一预设电压值为，栅极输入信号的电压正常状态与过流状态的临界电压值；
    与所述采样子电路耦接的延时判断子电路；所述延时判断子电路被配置为，接收所述采样子电路输出的第一控制信号，对所述第一控制信号进行第一预设时间的延时，判断经过延时的第一控制信号的电压值相较延时前是否有下降，若否，则输出计数信号；
    与所述延时判断子电路耦接的计数控制子电路；所述计数控制子电路被配置为，接收所述延时判断子电路输出的计数信号，并根据所述计数信号进行计数；在计数次数达到预设次数的情况下，输出第二控制信号，所述第二控制信号用于切断显示装置的***板向显示装置的驱动电路的信号输入。
  2. 根据权利要求1所述的过流保护电路，其中，所述采样子电路包括：信号筛选单元；
    所述信号筛选单元被配置为接收所述多个栅极输入信号，筛选出所述多个栅极输入信号中电压值大于所述第一预设电压值的一个栅极输入信号，作为采样栅极输入信号。
  3. 根据权利要求2所述的过流保护电路，其中，所述采样子电路还包括：与所述信号筛选单元耦接的信号处理单元；
    所述信号处理单元被配置为接收所述信号筛选单元输出的采样栅极输入信号，对所述采样栅极输入信号进行去干扰和放大处理，根据经过去干扰和放大处理的采样栅极输入信号和第二预设电压值生成第一控制信号，并输出所述第一控制信号；
    其中，所述第二预设电压值与对所述采样栅极输入信号进行去干扰和放大处理的放大倍数有关。
  4. 根据权利要求3所述的过流保护电路，其中，所述信号处理单元包括：
    降噪子单元，所述降噪子单元被配置为接收所述信号筛选单元输出的采样栅极输入信号，对所述采样栅极输入信号进行去干扰处理，并输出经过去干扰处理的采样栅极输入信号；
    与所述降噪子单元耦接的放大子单元，所述放大子单元被配置为接收所 述降噪子单元输出的经过去干扰处理的采样栅极输入信号，对所述经过去干扰处理的采样栅极输入信号进行放大处理，并输出经过去干扰和放大处理的采样栅极输入信号；
    与所述放大子单元耦接的比较子单元，所述比较子单元被配置为接收所述放大子单元输出的经过去干扰和放大处理的采样栅极输入信号，根据所述经过去干扰和放大处理的采样栅极输入信号和所述第二预设电压值生成第一控制信号，并输出所述第一控制信号。
  5. 根据权利要求2～4中任一项所述的过流保护电路，其中，所述信号筛选单元被配置为接收所述多个栅极输入信号，筛选出所述多个栅极输入信号中电压值最大的一个栅极输入信号，将所筛选出的栅极输入信号的电压值与所述第一预设电压值比较；在所筛选出的栅极输入信号的电压值大于所述第一预设电压值的情况下，将该栅极输入信号作为采样栅极输入信号。
  6. 根据权利要求5所述的过流保护电路，其中，所述多个栅极输入信号的数量为x，所述信号筛选单元包括n级筛选器组，第i级筛选器组包括2 (n-i)个筛选器；其中，x为大于或等于3的正整数，n为大于或等于2的正整数，i在[1，n]的正整数的集合内依次取值；
    一个筛选器具有两个输入端和一个输出端；第i+1级筛选器组中的一个筛选器的两个输入端与第i级筛选器组中的两个筛选器的输出端分别耦接；
    第1级筛选器组被配置为获取所述多个栅极输入信号，第1级筛选器组中的各筛选器被配置为接收所述多个栅极输入信号中的两个栅极输入信号，并将所接收的两个栅极输入信号中电压值较大的一个栅极输入信号输出；
    第i+1级筛选器组被配置为接收第i级筛选器组所输出的栅极输入信号，第i+1级筛选器组中的各筛选器被配置为，接收所述第i级筛选器组所输出的栅极输入信号中的两个栅极输入信号，并将所接收的两个栅极输入信号中电压值较大的一个栅极输入信号输出；
    第n级筛选器组中的筛选器被配置为接收第n-1级筛选器组输出的两个栅极输入信号，筛选出该两个栅极输入信号中电压值较大的一个栅极输入信号，并将所筛选出的栅极输入信号的电压值与所述第一预设电压值比较，在该栅极输入信号的电压值大于所述第一预设电压值的情况下，将该栅极输入信号作为采样栅极输入信号。
  7. 根据权利要求6所述的过流保护电路，其中，所述信号筛选单元还包括开关控制子单元；
    所述开关控制子单元与所述第1级筛选器组耦接，被配置为控制所述第1 级筛选器组中的各筛选器打开或关闭。
  8. 根据权利要求1～7中任一项所述的过流保护电路，其中，所述延时判断子电路包括：
    延时单元，所述延时单元被配置为接收所述采样子电路输出的第一控制信号，对所述第一控制信号进行第一预设时间的延时，输出经过延时的第一控制信号；
    与所述延时单元耦接的判断单元，所述判断单元被配置为接收所述采样子电路输出的第一控制信号，和所述延时单元输出的经过延时的第一控制信号，判断延时前与延时后第一控制信号的电压值是否相等，若是，则输出计数信号。
  9. 根据权利要求1～8中任一项所述的过流保护电路，其中，所述第一预设时间为3μs～5μs。
  10. 根据权利要求1～9中任一项所述的过流保护电路，其中，所述计数控制子电路还被配置为，在计数次数没有达到所述预设次数的情况下，判断在此之后的第二预设时间之内计数次数是否有增加，若否，则将所述计数次数清零。
  11. 根据权利要求10所述的过流保护电路，其中，所述过流保护电路在侦测时序信号的控制下，在每个时钟周期内对多个栅极输入信号进行一次侦测；
    所述第二预设时间为一个时钟周期。
  12. 根据权利要求1～11中任一项所述的过流保护电路，其中，所述计数控制子电路还被配置为在所述计数次数达到预设次数的情况下，输出第三控制信号，所述第三控制信号用于切断信号源向所述***板的信号输入。
  13. 根据权利要求1～12中任一项所述的过流保护电路，其中，所述计数控制子电路包括：
    计数单元，所述计数单元被配置为接收所述延时判断子电路输出的计数信号，并根据所述计数信号进行计数；
    与所述计数单元耦接的控制单元，所述控制单元被配置为存储计数次数，在所述计数次数达到所述预设次数的情况下，输出第二控制信号。
  14. 一种显示装置的驱动电路，包括：电源电路、时序控制器和如权利要求1～13中任一项所述的过流保护电路；
    所述电源电路与显示装置的***板、所述时序控制器和所述过流保护电路耦接，所述电源电路被配置为接收所述***板所输入的电源信号，并根据 所述电源信号为所述时序控制器和所述过流保护电路提供电能；
    所述时序控制器还与所述***板耦接，所述时序控制器被配置为接收***板所输入的显示信号，根据所述显示信号生成用于输入至显示装置的栅极驱动电路的多个栅极输入信号；
    所述过流保护电路还与所述时序控制器耦接；
    所述电源电路还被配置为接收所述过流保护电路输出的第二控制信号，并在所述第二控制信号的控制下，停止接收所述***板输入的电源信号。
  15. 根据权利要求14所述的驱动电路，还包括：源极驱动电路；
    所述源极驱动电路与所述电源电路和所述时序控制器耦接；
    所述时序控制器还被配置为根据所述显示信号生成用于输入至所述源极驱动电路的多个源极输入信号；
    所述源极驱动电路被配置为接收所述多个源极输入信号，并根据多个源极输入信号生成数据信号。
  16. 一种显示装置，包括：
    如权利要求14或15所述的驱动电路；
    ***板，所述***板与所述驱动电路中的电源电路和时序控制器耦接，被配置为输出电源信号和显示信号；
    与所述驱动电路耦接的显示面板；
    其中，所述显示面板包括栅极驱动电路，所述栅极驱动电路与所述驱动电路中的时序控制器和电源电路耦接；所述栅极驱动电路被配置为接收所述时序控制器输出的多个栅极输入信号，根据所述多个栅极输入信号，生成并输出栅极扫描信号。
  17. 根据权利要求16所述的显示装置，其中，在所述驱动电路中的过流保护电路还被配置为输出第三控制信号的情况下，所述***板还与所述驱动电路中的过流保护电路耦接；
    所述***板还被配置为接收所述第三控制信号，并在所述第三控制信号的控制下，停止接收视频信号源输入的视频信号。
  18. 一种过流保护方法，应用于如权利要求16或17所述的显示装置，所述过流保护方法包括：
    显示装置的***板向显示装置的驱动电路输出电源信号和显示信号；
    所述驱动电路中的电源电路接收所述电源信号，并根据所述电源信号为所述驱动电路中的时序控制器和过流保护电路提供电能；
    所述时序控制器接收所述显示信号，根据所述显示信号生成用于输入至 显示装置的栅极驱动电路的多个栅极输入信号；
    所述过流保护电路获取所述多个栅极输入信号，对所述多个栅极输入信号进行连续侦测，在侦测到栅极输入信号出现过流的情况下，向所述电源电路输出第二控制信号；
    所述电源电路接收所述第二控制信号，并在所述第二控制信号的控制下，停止接收所述***板输入的电源信号。
  19. 根据权利要求18所述的过流保护方法，还包括：所述过流保护电路对所述多个栅极输入信号进行连续侦测，在侦测到栅极输入信号出现过流的情况下，向所述***板输出第三控制信号；
    所述***板接收所述第三控制信号，并在所述第三控制信号的控制下，停止接收信号源输入的信号。
PCT/CN2021/094150 2020-06-17 2021-05-17 过流保护电路、显示装置及其驱动电路、过流保护方法 WO2021254062A1 (zh)

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