WO2021244248A1 - 显示面板及其制备方法、显示基板及其制备方法和显示装置 - Google Patents

显示面板及其制备方法、显示基板及其制备方法和显示装置 Download PDF

Info

Publication number
WO2021244248A1
WO2021244248A1 PCT/CN2021/093582 CN2021093582W WO2021244248A1 WO 2021244248 A1 WO2021244248 A1 WO 2021244248A1 CN 2021093582 W CN2021093582 W CN 2021093582W WO 2021244248 A1 WO2021244248 A1 WO 2021244248A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
electrode
opening
light
Prior art date
Application number
PCT/CN2021/093582
Other languages
English (en)
French (fr)
Inventor
刘利宾
史世明
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/777,652 priority Critical patent/US20230006009A1/en
Publication of WO2021244248A1 publication Critical patent/WO2021244248A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a preparation method thereof, a display substrate and a preparation method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED display devices have the advantages of self-luminescence, high luminous efficiency, short response time, high definition and contrast, and flexible display, so they are used in more and more occasions.
  • a display panel in one aspect, includes a substrate, a first electrode, a pixel defining layer, and a first light-emitting function layer.
  • the first electrode is arranged on one side of the substrate.
  • the pixel defining layer is disposed on one side of the substrate, and includes a first hollowed-out portion, and the first hollowed-out portion includes a first opening and a second opening that are oppositely disposed; compared with the second opening, The first opening is closer to the substrate, wherein the first opening exposes at least part of the first electrode.
  • the first light-emitting function layer is disposed on the pixel defining layer and the side of the first electrode away from the substrate, and includes a second hollow portion, and the second hollow portion is formed on the pixel defining layer
  • the orthographic projection does not overlap with the first opening.
  • the maximum size of the second hollow portion is smaller than the maximum size of the first hollow portion.
  • the display panel further includes: a second electrode disposed on a side of the first light-emitting function layer away from the substrate, and the second electrode covers the second hollow portion.
  • the display panel further includes a thin film transistor disposed between the substrate and the first electrode, and the source or drain of the thin film transistor is electrically connected to the first electrode .
  • the thin film transistor further includes: an active layer, a first gate insulating layer, a gate layer, a second gate insulating layer, and an interlayer insulating layer stacked in a direction away from the substrate;
  • the source and drain of the transistor are arranged on the side of the interlayer insulating layer away from the substrate, and pass through the via holes that penetrate the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.
  • the active layer contacts.
  • the display panel further includes: a first metal layer disposed between the thin film transistor and the substrate, and the first metal layer and a compensation voltage terminal Electrically connected, the compensation voltage terminal is configured to provide a compensation voltage signal for compensating the threshold voltage of the thin film transistor.
  • the display panel further includes an encapsulation layer including a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked in a direction away from the substrate.
  • a display substrate including: a substrate, a first electrode, a pixel defining layer, a sacrificial pattern, a spacer, and a second light-emitting function layer.
  • the first electrode is arranged on one side of the substrate.
  • the pixel defining layer is disposed on one side of the substrate, and includes a first hollowed-out portion, and the first hollowed-out portion includes a first opening and a second opening that are oppositely disposed; compared with the second opening, the The first opening is closer to the substrate, wherein the first opening exposes at least part of the first electrode.
  • the sacrificial pattern is disposed on a side of the pixel defining layer away from the substrate, and the orthographic projection of the sacrificial pattern on the pixel defining layer does not overlap with the first opening.
  • the spacer is disposed on a side of the sacrificial pattern away from the substrate, and the orthographic projection of the spacer on the pixel defining layer does not overlap with the first opening.
  • the second light-emitting function layer is disposed on a side of the pixel defining layer and the first electrode away from the substrate.
  • the spacer includes a first surface and a second surface disposed opposite to each other in a direction away from the substrate, and the first surface is closer to the substrate relative to the second surface; Wherein, the orthographic projection of the first surface on the pixel defining layer falls within the orthographic projection of the second surface on the pixel defining layer, and the first surface is on the pixel defining layer. There is a gap between the boundary of the orthographic projection and the boundary of the orthographic projection of the second surface on the pixel defining layer.
  • the maximum size of the second surface is smaller than the maximum size of the first hollow portion.
  • the thickness of the sacrificial pattern is greater than the thickness of the second light-emitting function layer.
  • the display substrate further includes a thin film transistor disposed between the substrate and the first electrode, and the source or drain of the thin film transistor is electrically connected to the first electrode .
  • a display device including the display panel as described above.
  • a method for preparing a display substrate including:
  • a first electrode is formed on the substrate.
  • a pixel defining layer is formed on the substrate on which the first electrode is formed; the pixel defining layer includes: a first hollowed-out portion, and the first hollowed-out portion includes a first opening and a second opening that are arranged opposite to each other. The second opening, the first opening is closer to the substrate, and the first opening exposes at least part of the first electrode.
  • a stacked sacrificial pattern and spacer are formed on the pixel defining layer, and the sacrificial pattern is closer to the substrate than the spacer.
  • the substrate on which the spacer is formed is disposed opposite to the mask plate, the spacer is in contact with the mask plate, and the spacer is provided to the substrate through the mask plate
  • a light-emitting functional material is vapor-deposited on one side of the object to form a second light-emitting functional layer.
  • forming laminated sacrificial patterns and spacers on the pixel defining layer includes: forming a first thin film on a substrate on which the pixel defining layer is formed, and patterning the first thin film, To form a sacrificial pattern on the side of the pixel defining layer away from the substrate.
  • a second thin film is formed on the substrate on which the sacrificial pattern is formed, and the second thin film is patterned to form spacers on the side of the sacrificial pattern away from the substrate.
  • forming a laminated sacrificial pattern and spacers on the pixel defining layer includes: forming a first thin film on the substrate on which the pixel defining layer is formed.
  • a second film is formed on the first film.
  • first film and the second film are patterned to form laminated sacrificial patterns and spacers.
  • a method for manufacturing a display panel including:
  • the sacrificial pattern in the display substrate is removed, so that the spacer on the side of the sacrificial pattern away from the substrate in the display substrate is separated from the display substrate to form a first light-emitting function layer through a second light-emitting function layer .
  • the manufacturing method of the display panel further includes:
  • a second electrode is formed on the substrate on which the first light-emitting function layer is formed.
  • a first inorganic encapsulation sublayer is formed on the second electrode.
  • An organic encapsulation sublayer is formed on the first inorganic encapsulation sublayer.
  • a second inorganic encapsulation sublayer is formed on the organic encapsulation sublayer, and the first inorganic encapsulation sublayer, the organic encapsulation sublayer, and the second inorganic encapsulation sublayer constitute an encapsulation layer.
  • FIGS. 1A to 1G are structural diagrams of a display panel provided according to some embodiments of the present disclosure.
  • Fig. 2 is a structural diagram of a first light-emitting functional layer provided according to some embodiments of the present disclosure
  • 3A to 3C are manufacturing process diagrams of a display panel provided according to some embodiments of the present disclosure.
  • FIGS. 4A and 4B are structural diagrams of another display panel provided according to some embodiments of the present disclosure.
  • FIG. 5 is a structural diagram of a pixel driving circuit provided according to some embodiments of the present disclosure.
  • FIG. 6 is a timing diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 7A is a structural diagram of another display panel provided according to some embodiments of the present disclosure.
  • Fig. 7B is a cross-sectional view in the direction of A-A' in Fig. 7A;
  • FIG. 7C is a structural diagram of a first metal layer provided according to some embodiments of the present disclosure.
  • FIG. 7D is a structural diagram of an active layer provided according to some embodiments of the present disclosure.
  • FIG. 7E is a structural diagram of a gate metal layer provided according to some embodiments of the present disclosure.
  • FIG. 7F is a structural diagram of a second metal layer provided according to some embodiments of the present disclosure.
  • FIG. 7G is a structural diagram of a third metal layer provided according to some embodiments of the present disclosure.
  • FIG. 7H is a structural diagram of another display panel provided according to some embodiments of the present disclosure.
  • FIGS. 8A to 8I are structural diagrams of a display substrate provided according to some embodiments of the present disclosure.
  • FIG. 9A is a structural diagram of another display substrate provided according to some embodiments of the present disclosure.
  • Fig. 9B is a cross-sectional view in the direction of B-B' in Fig. 9A;
  • 9C is a structural diagram of a first electrode, a first hollow portion, a sacrificial pattern, and a spacer provided according to some embodiments of the present disclosure
  • FIG. 9D is a structural diagram of another display substrate provided according to some embodiments of the present disclosure.
  • FIG. 10A is a flowchart of a method for manufacturing a display substrate according to some embodiments of the present disclosure
  • FIGS. 10B to 10G are diagrams of a manufacturing process of a display substrate provided according to some embodiments of the present disclosure.
  • Fig. 10H is a cross-sectional view in the direction of C-C′ in Fig. 10G;
  • FIG. 11A is a flowchart of a method for manufacturing a display panel according to some embodiments of the present disclosure
  • FIG. 11B is a manufacturing process diagram of a display panel provided according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing.
  • the etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • An embodiment of the present disclosure provides a display device, which is, for example, an electroluminescence display device.
  • the electroluminescent display device includes, for example, a display panel, and the display panel may be an OLED display panel or a Quantum Dot Light Emitting Diodes (QLED for short) display panel.
  • the display panel may be an OLED display panel or a Quantum Dot Light Emitting Diodes (QLED for short) display panel.
  • QLED Quantum Dot Light Emitting Diodes
  • the display panel 1 includes, for example:
  • the substrate 11 is, for example, a flexible substrate, and the material of the flexible substrate is, for example, polyimide (PI).
  • PI polyimide
  • At least one first electrode 12 is provided on one side of the substrate 11.
  • the first electrode 12 is, for example, a transparent electrode or an anode, and its material includes, for example, indium tin oxide (ITO). In some embodiments, there are multiple first electrodes 12.
  • the pixel defining layer 13 is disposed on one side of the substrate 11 and includes at least one first hollow portion 130.
  • the first hollow portion 130 includes a first opening 1301 and a second opening 1302 disposed oppositely. Compared to the second opening 1302, the first opening 1301 is closer to the substrate 11, wherein the first opening 1301 exposes at least part of the first electrode 12.
  • the size of the first opening 1301 and the size of the second opening 1302 are exactly the same, and the size here includes, for example, length and width.
  • the size of the first opening 1301 and the size of the second opening 1302 are different, for example, at least one of the length and the width are different.
  • the number of the first hollow parts 130 is greater than or equal to the number of the first electrodes 12, and the extra first hollow parts 130 are used, for example, to realize the cross-layer electrical connection between the various film layers in the display panel 1.
  • the first hollow portion 130 exposes a portion of the surface of the first electrode 12 on the side away from the substrate 11.
  • the first hollow portion 130 exposes the entire surface of the first electrode 12 on the side away from the substrate 11.
  • the first light-emitting function layer 14 is disposed on the side of the pixel defining layer 13 and the first electrode 12 away from the substrate 11, and includes a second hollow portion 140.
  • the orthographic projection of the second hollow portion 140 on the pixel defining layer 13 and the first The opening 1301 does not overlap.
  • the first light-emitting functional layer 14 includes at least a light-emitting layer, and the material of the light-emitting layer may include, for example, an organic electroluminescent material.
  • the first light-emitting functional layer 14 may also include an electron transport layer (election transporting layer, ETL) 142, an electron injection layer (election injection layer, EIL) 143, and a hole transport layer (hole).
  • ETL electron transport layer
  • EIL electron injection layer
  • hole hole transport layer
  • HTL transporting layer
  • HIL hole injection layer
  • the first light-emitting functional layer 14 is not limited to only including the light-emitting layer 141 and the combination of ETL142, EIL143, HTL144, and HIL145, and may also include other functional layers.
  • the orthographic projection of the second hollow portion 140 on the pixel defining layer 13 does not overlap with the first opening 1301 and includes:
  • the thickness direction of the substrate is a direction perpendicular to one side of the substrate and the other side of the substrate, and the second hollow portion 140 is There is a gap between the orthographic projection on the pixel defining layer 13 and the first opening 1301, and the first light-emitting function layer 14 covers the gap.
  • the second hollow portion 140 is immediately between the orthographic projection on the pixel defining layer 13 and the first opening 1301, that is, there is no gap between the second hollow portion 140 and the first opening 1301. There is a gap; at the same time, the orthographic projection of the second hollow portion 140 on the pixel defining layer 13 and the second opening 1302 are also close to each other.
  • the second hollow portion 140 has a gap between the orthographic projection on the pixel defining layer 13 and the first opening 1301, while the second hollow portion 140 is on the pixel defining layer 13. There is a partial overlap between the projection and the second opening 1302.
  • the first light-emitting functional layer 14 When making the first light-emitting functional layer 14, it is necessary to use a fine metal mask (Fine metal mask, FFM) to evaporate the material used to form the first light-emitting functional layer 14, but in order to avoid scratches on the fine metal mask
  • FFM fine metal mask
  • the film layers that have been fabricated before the first light-emitting function layer 14 are fabricated, such as the pixel defining layer 13 and the first electrode 12, etc., so that spacers 17 are provided on the pixel defining layer 13 to support the FMM, so that the FMM and the fabricated There is a certain distance between good film layers, and there is no direct contact, so as to protect the film layers that have been made.
  • a stacked sacrificial pattern 18 and spacers 17 are arranged on the pixel defining layer 13, and the sacrificial pattern 18 is located between the spacers 17 and the pixel defining layer 13.
  • the sacrificial pattern 18 will be removed later (for example, it can be removed by dissolving), so that the spacer 17 can be separated from the display panel 1.
  • a second light-emitting functional layer 24 is formed on the side of the first electrode 12, the pixel defining layer 13 and the spacer 17 away from the substrate 11.
  • the second light-emitting functional layer 24 covers the first electrode 12 and the pixel defining layer 13. In the embodiment, the second light-emitting functional layer 24 also covers the spacer 17.
  • the second light-emitting function layer 24 will be formed A hollow part is formed, and the hollow part can be understood as the second hollow part 140.
  • the process can be understood as forming the first light-emitting function layer 14 with the second hollow part 140 through the second light-emitting function layer 24.
  • the second light-emitting functional layer 24 covers the pixel defining layer 13, spacers 17, and the first electrode 12; referring to FIG. 3C, the second light-emitting functional layer 24 covers the pixel defining layer 13 and the first electrode 12; 1A to 1G, the first light-emitting functional layer 14 covers the pixel defining layer 13 and the first electrode 12, that is to say, the structure of the second light-emitting functional layer 24 may be different from that of the first light-emitting functional layer 14.
  • the first light-emitting functional layer 14 and the second light-emitting functional layer 24 are used to distinguish, and those skilled in the art can understand that the first light-emitting functional layer 14 passes through the second light-emitting function.
  • the layer 24 is prepared, or, it can also be understood that the first light-emitting functional layer 14 is at least part of the second light-emitting functional layer 24.
  • the spacer 17 Since the spacer 17 is present in the manufacturing process of the display panel 1, it can not only support the FMM, so that the second light-emitting functional layer 24 can be prepared smoothly, and after the second light-emitting functional layer 24 is prepared, the first The sacrificial pattern 18 is removed, so that the spacer 17 is separated from the display panel 1, and foreign particles generated by the spacer 17 in the process of removing the FMM can be removed, so as to provide a better support surface for the subsequent preparation of the encapsulation layer .
  • the sacrificial pattern 18 can be removed by, for example, wet etching, dry etching, etc.; the wet etching, for example, uses a stripping solution to dissolve the sacrificial pattern 18, and the dry etching, for example, uses a gas to react with the sacrificial pattern 18, thereby Etch away the sacrificial pattern 18.
  • the spacer 17 loses support, so that it can be detached from the display panel 1 (also referred to as falling).
  • the FMM since the material of the spacer 17 is an organic material, when the FMM is used, the FMM may scratch the spacer 17 during the installation or disassembly process of the FMM, thereby generating foreign particles.
  • the density of the spacer 17 and the foreign particles produced therefrom will affect the quality of the film layer prepared after the first light-emitting functional layer 14.
  • the film layer prepared after the first light-emitting functional layer 14 includes, for example, packaging.
  • the encapsulation layer includes at least an organic encapsulation sublayer.
  • the organic encapsulation sublayer can be formed by inkjet printing (IJP), for example. Since the material of the organic encapsulation sublayer has certain fluidity, the spacer 17 The density will affect its fluidity.
  • the fluidity of the material in the organic encapsulation sub-layer is reduced, thereby forming a part of the organic encapsulation sub-layer with a larger thickness, while in other areas In the area where the spacer 17 has a lower density, the fluidity of the material of the organic encapsulation sublayer increases, thereby forming a part of the organic encapsulation layer with a smaller thickness. Therefore, the film thickness of the organic encapsulation sublayer is different. Thickness uniformity is poor, and foreign particles may cause defects in the organic encapsulation sublayer, which affects the encapsulation effect of the organic encapsulation sublayer.
  • the display panel 1 due to the difference in the height of the spacer 17 of the display panel 1, for example, along the length of the display panel 1, if the height of the spacer 17 on the left and right sides is different, the edge brightness of the display panel 1 will be different from that of other areas. Therefore, the display panel 1 produces a color shift phenomenon, which affects the display effect. Therefore, in the related art, the presence of the spacer 17 will affect the quality of the film prepared after the first light-emitting function layer 14 and also affect the display effect of the display panel 1.
  • sacrificial patterns 18 and spacers 17 are formed on the pixel defining layer 13 to support the FMM, and after the second light-emitting function layer 24 is prepared, The spacer 17 is removed or removed by removing the sacrificial pattern 18, so that the first light-emitting function layer 14 with the second hollow portion 140 is prepared from the second light-emitting function layer 24. Therefore, on the one hand, when the organic encapsulation sublayer in the present disclosure is prepared, since there is no barrier by the spacer 17, the film thickness of the prepared organic encapsulation sublayer is close to each other, and the thickness uniformity is good, which can improve the display The encapsulation effect of the panel 1.
  • the foreign particles generated by the spacer 17 being scratched by the FMM will also be removed, so that the prepared organic encapsulation sub-layer will not be defective due to foreign particles, and the quality of the film It is also better, which can further improve the packaging effect of the display panel 1.
  • the display panel 1 since there is no spacer 17, the display panel 1 will not produce color shift due to the height difference of the spacer 17, so that the display panel 1 The display effect is also better; on the other hand, due to the absence of spacers 17, the thickness of the display panel 1 can be reduced, so that the display panel 1 with a smaller thickness can be prepared, which is more in line with the development of the display panel 1 towards lightness and thinness. Trend, and improve the market competitiveness of the display panel 1.
  • the second hollow portion 140 has a gap between the orthographic projection on the pixel defining layer 13 and the second opening 1302.
  • the formed first light-emitting functional layer 14 will cover the gap, thereby ensuring that the first light-emitting functional layer 14 is completely covered
  • the first opening 1301 further ensures that the contact area between the first light-emitting function layer 14 and the first electrode 12 is relatively large.
  • the first light-emitting function layer 14 does not completely cover the first opening 1301, the first light-emitting function layer 14 does not completely cover the part of the first electrode 12 exposed by the first opening 1301, that is, the part of the first electrode 12 exposed by the first opening 1301 Only part of the area of one electrode 12 is covered with the first light-emitting functional layer 14, and the remaining part of the area is not covered by the first light-emitting functional layer 14, so that the contact area between the first light-emitting functional layer 14 and the first electrode 12 is small Finally, the light-emitting area of the organic light-emitting diode is small, and the present disclosure can ensure that the contact area between the first light-emitting functional layer 14 and the first electrode 12 is large, and thus the light-emitting area of the organic light-emitting diode is large.
  • the length of the first opening 1301 is less than or equal to the length of the second opening 1302.
  • the length directions of the first opening 1301 and the second opening 1302 are, for example, the length direction of the display panel 1.
  • the length direction of the display panel 1 is from left to right or from right to left, referring to FIGS. 1A to 1G, for example.
  • the length of the first opening 1301 is equal to the length of the second opening 1302, and it is convenient to form the first opening 1301 and the second opening 1302 at this time.
  • the length of the first opening 1301 is less than the length of the second opening 1302, so that the side wall of the first hollow portion 130 is inclined, which is convenient for the first light-emitting function layer 14 prepared subsequently to be attached to the first hollow On the sidewall of the portion 130, it is further ensured that the first light-emitting function layer 14 completely covers at least part of the first electrode 12 exposed by the first opening 1301.
  • the maximum size of the first hollow portion 130 is the maximum distance between any two points on the boundary of the orthographic projection of the first hollow portion 130 on the substrate 11, and the maximum size of the second hollow portion 140 is the first hollow portion. The maximum distance between any two points on the boundary of the orthographic projection of the two hollow portions 140 on the substrate 11.
  • the maximum size of the first hollow portion 130 is, for example, the maximum length
  • the maximum size of the second hollow portion 140 is, for example, the maximum length. The following analyzes the factors affecting the length of the first hollow portion 130 and the second hollow portion 140:
  • the length of the second hollow portion 140 is related to the length of the sacrificial pattern 18 and the spacer 17.
  • the length of the second hollow portion 140 is equal to the length of the sacrificial pattern 18.
  • the length of the second hollow portion 140 is equal to the length of the side surface of the spacer 17 away from the substrate 11. Therefore, adjusting the length of the second hollow portion 140 can be achieved by changing the length of the sacrificial pattern 18 and/or the side surface of the spacer 17 away from the substrate 11.
  • the maximum size (for example, its length) of the second hollow portion 140 and the maximum size (for example, its length) of the first hollow portion 130 have the following relationship:
  • the length of the second hollow part 140 is smaller than the length of the first hollow part 130.
  • the length of the second hollow portion 140 is equal to the length of the first hollow portion 130.
  • the length of the second hollow portion 140 is greater than the length of the first hollow portion 130.
  • the overall size of the second hollow portion 140 is smaller, which facilitates the formation of the second hollow portion 140 on the first light-emitting function layer 14, and As a result, there is a gap between the second hollow portion 140 and the second opening 1302.
  • the display panel 1 further includes: a second electrode 15 disposed on a side of the first light-emitting function layer 14 away from the substrate 11, and the second electrode 15 covers the second hollow portion 140.
  • the second electrode 15 covers the second hollow part 140, that is, the material used to form the second electrode 15 is filled in the second hollow part 140.
  • the material of the second electrode 15 is, for example, silver, and the second electrode 15 is, for example, a semi-transparent electrode, so that the light generated by the organic light emitting diode passes through the second electrode 15 and exits.
  • the first electrode 12 is, for example, an anode
  • the second electrode 15 is, for example, a cathode.
  • the organic light-emitting diode includes a first electrode 12, a second electrode 15, and a part of the first light-emitting function layer 14 between the first electrode 12 and the second electrode 15.
  • the organic light-emitting diode may also It is called a light-emitting device D, and the light-emitting device D is used to provide a light source for the display panel 1.
  • the display panel 1 further includes an encapsulation layer 111, and the encapsulation layer 111 includes a first inorganic encapsulation sublayer 1111, an organic encapsulation sublayer 1113, and a second inorganic encapsulation layer stacked along the thickness direction of the substrate 11.
  • the material of the first inorganic encapsulation sublayer 1111 and the second inorganic encapsulation sublayer 1112 is, for example, at least one of silicon nitride and silicon oxide.
  • magnetron sputtering may be used for forming the first inorganic encapsulation sublayer 1111 and the second inorganic encapsulation sublayer 1112 .
  • the organic encapsulation sub-layer 1113 is formed by inkjet printing.
  • the spacer 17 is no longer present on the display panel 1, so when the organic encapsulation sub-layer is formed
  • the fluidity of the material used to make the organic encapsulation sublayer 1113 is better, so that the film quality and thickness of the organic encapsulation sublayer 1113 are better.
  • an embodiment of the present disclosure provides a pixel driving circuit 3, the pixel driving circuit 3 includes: a reset sub-circuit 31, a data writing sub-circuit 32, a driving sub-circuit 33, and a light-emitting control sub-circuit 34.
  • the reset sub-circuit 31 is electrically connected to the reset signal terminal Reset, the initialization signal terminal Vint, the node N and the first pole of the light emitting device D. In other embodiments, the reset sub-circuit 31 may also be electrically connected to the gate drive signal terminal Gate.
  • the reset sub-circuit 31 is configured to transmit the initialization signal provided by the initialization signal terminal Vint to the node N under the control of the reset signal terminal Reset, and reset the node N; it is also configured to reset or the gate drive signal terminal at the reset signal terminal. Under the control of the gate, the initialization signal provided by the initialization signal terminal Vint is transmitted to the first pole of the light-emitting device D, and the first pole of the light-emitting device D is reset.
  • the data writing sub-circuit 32 is electrically connected to the data signal terminal Data, the gate driving signal terminal Gate, and the driving sub-circuit 33.
  • the data writing sub-circuit 32 is configured to write the data signal provided by the data signal terminal Data into the driving sub-circuit 33 under the control of the gate driving signal terminal Gate.
  • the driving sub-circuit 33 is electrically connected to the gate driving signal terminal Gate, the node N, and the first power supply voltage signal terminal VDD.
  • the driving sub-circuit 33 is configured to, under the control of the gate driving signal, write the data signal and the threshold voltage of the driving transistor to the first node to charge the capacitor C; and to control the first power supply voltage signal terminal VDD and the node N Next, a drive signal is output to the light emitting device D, and the drive signal is, for example, a drive current signal.
  • the light emitting control sub-circuit 34 is electrically connected to the first power supply voltage signal terminal VDD, the light emitting control signal terminal EM, the driving sub-circuit 33 and the first pole of the light emitting device D.
  • the light emission control sub-circuit 34 is configured to electrically connect the first electrode of the driving transistor to the first power supply voltage signal terminal VDD, and the second electrode of the driving transistor to the light emitting device D under the control of the light emitting control signal terminal EM.
  • the aforementioned pixel driving circuit 3 may be, for example, a 7T1C type pixel driving circuit.
  • the 7T1C type pixel driving circuit includes, for example, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C; wherein the third transistor T3 is the driving transistor.
  • Some or all of the first transistor T1 to the seventh transistor T7 may be, for example, P-type thin film transistors.
  • the first electrode of the thin film transistor is, for example, the source electrode
  • the second electrode is, for example, the drain electrode
  • the gate of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode is electrically connected to the initialization signal terminal Vint, and the second electrode is electrically connected to the node N.
  • the gate of the second transistor T2 is electrically connected to the gate drive signal terminal Gate, the first electrode is electrically connected to the second electrode of the third transistor T3, and the second electrode is electrically connected to the node N.
  • the second transistor T2 is a compensation transistor, which enables the sum of the threshold voltage and the data signal of the third transistor T3 to be written to the node N.
  • the gate of the third transistor T3 is electrically connected to the node N, and the first electrode is electrically connected to the second electrode of the fourth transistor T4.
  • the gate of the fourth transistor T4 is electrically connected to the gate driving signal terminal Gate, and the first electrode is electrically connected to the data signal terminal Data.
  • the gate of the fifth transistor T5 is electrically connected to the light emission control signal terminal EM, the first electrode is electrically connected to the first power supply voltage signal terminal VDD, and the second electrode is electrically connected to the first electrode of the third transistor T3.
  • the gate of the sixth transistor T6 is electrically connected to the light emission control signal terminal EM, the first electrode is electrically connected to the second electrode of the third transistor T3, and the second electrode is electrically connected to the first electrode of the light emitting device D.
  • the gate of the seventh transistor T7 is electrically connected to the gate driving signal terminal Gate, the first electrode is electrically connected to the initialization signal terminal Vint, and the second electrode is electrically connected to the first electrode of the light emitting device D.
  • the gate of the seventh transistor T7 may also be electrically connected to the reset signal terminal Reset, so as to control the working state of the seventh transistor T7 through the reset signal.
  • One end of the capacitor C is electrically connected to the node N, and the other end is electrically connected to the first power supply voltage signal terminal VDD.
  • one end of the capacitor C is its first plate C 1 , and the other end is its second plate C 2 .
  • the second pole of the light emitting device D is electrically connected to the second power supply voltage signal terminal VSS.
  • the first power supply voltage signal terminal VDD is electrically connected to the first electrode 12 in the display panel 1
  • the second power supply voltage signal terminal VSS is electrically connected to the second electrode 15 in the display panel 1, for example.
  • the working phases of the pixel driving circuit 3 include, for example, a reset phase D1, a data writing phase D2, and a light emitting phase D3.
  • the first transistor T1 is turned on, and the initial signal provided by the initialization signal terminal Vint is transmitted to the node N, and the node N is reset.
  • the gate of the seventh transistor T7 When the gate of the seventh transistor T7 is electrically connected to the reset signal terminal Reset: under the control of the reset signal terminal Reset, the seventh transistor T7 is turned on, and the initial signal provided by the initialization signal terminal Vint is transmitted to the first light emitting device D. The first pole of the light-emitting device D is reset.
  • the fourth transistor T4 and the second transistor T2 are turned on, and the data signal provided by the data signal terminal Data and the threshold voltage of the third transistor T3 are written into the node N.
  • the seventh transistor T7 When the gate of the seventh transistor T7 is electrically connected to the gate drive signal terminal Gate: under the control of the gate drive signal terminal Gate, the seventh transistor T7 is turned on to transmit the initialization signal provided by the initialization signal terminal Vint To the first pole of the light emitting device D, the first pole of the light emitting device D is reset.
  • the fifth transistor T5 and the sixth transistor T6 are turned on; wherein, the fifth transistor T5 makes the first electrode of the third transistor T3 and the first power supply voltage signal terminal VDD electrically connected.
  • the sixth transistor T6 electrically connects the second pole of the third transistor T3 with the first pole of the light emitting device D, so that the third transistor T3 can drive the light emitting device D to emit light.
  • the gate of the seventh transistor T7 is electrically connected to the gate drive signal terminal Gate or the reset signal terminal Reset, when the seventh transistor T7 is turned on, it can be used for the light emitting device.
  • the first pole of D is reset.
  • the gate drive signal is valid only in the data writing stage D2, so that the reset process of the light emitting device D is in the data writing stage In D2
  • the reset signal is an effective signal in the reset phase D1, so that the reset process of the light-emitting device D is in the reset phase D1, but the two This embodiment does not affect the function of the reset sub-circuit 31. Therefore, the seventh transistor T7 is included in the reset sub-circuit 31 in the embodiment of the present disclosure.
  • each thin film transistor (the first transistor T1 to the seventh transistor T7) in the pixel driving circuit 3 in the display panel 1 can be referred to FIG. 7A; wherein, the gate of the seventh transistor T7 is electrically connected to the reset signal terminal Reset. connect.
  • the first electrode of the third transistor T3 in the pixel driving circuit 3 is electrically connected to the first electrode 12, and the first hollow portion 130 exposes at least a part of the first electrode 12.
  • the gate layer of the third transistor T3 serves as the first electrode plate C 1 of the capacitor C, and the second electrode plate C 2 of the capacitor C and the first electrode plate C 1 are arranged opposite to each other along the thickness direction of the substrate 11.
  • the second plate C 2 of the capacitor C has the same layer and the same material as the initialization signal line Vint.
  • the first transistor T1 and the second transistor T2 may also be double-gate thin film transistors, and the two gate layers of the double-gate thin film transistor are of the same layer and the same material.
  • the display panel 1 includes a first metal layer 191, a buffer layer 192, an active layer 193, a first gate insulating layer 194, and a gate metal layer that are sequentially away from the substrate 11 195, the second gate insulating layer 196, the second metal layer 197, the interlayer insulating layer 198, the third metal layer 199, and the planarization layer 16.
  • the buffer layer 192, the first gate insulating layer 194, the second gate insulating layer 196, and the interlayer insulating layer 198 are all insulating layers, which play an insulating role.
  • the material of these insulating layers is, for example, silicon oxide and silicon nitride. At least one.
  • the active layer 193, the first gate insulating layer 194, the gate layer, the second gate insulating layer 196, the interlayer insulating layer 198, the source electrode and the drain electrode constitute a thin film transistor.
  • the thin film transistor may further include a buffer layer 192.
  • the planarization layer 16 has a planarization effect, and its material is, for example, an organic material, such as at least one of photoresist and resin.
  • the first metal layer 191 may serve as a light shielding layer and a second gate layer of the thin film transistor T7 of the first transistors T1 to T7.
  • the material of the first metal layer 191 is, for example, a metal or alloy such as silver and aluminum.
  • the first metal layer 191 is used as a light shielding layer, the leakage current of the first transistors T1 to T7 thin film transistor T7 can be reduced; when the first metal layer 191 is used as the second gate layer, it needs to be electrically connected to a compensation voltage terminal
  • the compensation voltage terminal can provide a compensation voltage signal, and the compensation voltage signal is used to compensate the threshold voltage of the thin film transistor.
  • each of the first transistor T1 to the seventh transistor T7 includes at least two gate layers arranged opposite to each other along the thickness direction of the substrate 11; For any thin film transistor of the first transistor T1 and the second transistor T2 of the two gate layers, there are three gate layers.
  • the threshold voltage Vth of the thin film transistor deviates from the preset value due to the influence of the process of making each film layer in the thin film transistor, the deviation of the threshold voltage Vth can be compensated by the compensation voltage signal provided by the compensation voltage terminal.
  • the threshold voltage Vth of the thin film transistor is less than 0, and the compensation voltage signal provided by the compensation voltage terminal is greater than 0.
  • the compensation voltage signal provided by the compensation voltage terminal increases, the thin film transistor's The threshold voltage Vth decreases. Therefore, when the threshold voltage Vth is too large due to process reasons, compensation can be performed by increasing the compensation voltage signal provided by the compensation voltage terminal, so that the too large threshold voltage Vth is reduced to a preset value.
  • the threshold voltage Vth of the thin film transistor is preset to -3.0V.
  • the threshold voltage can be increased by increasing the compensation voltage signal provided by the compensation voltage terminal.
  • Vth is reduced from -2.5V to -3.0V, so as to realize the function of compensating the threshold voltage of the thin film transistor.
  • the gate metal layer 195 is used to form the gate layer of the thin film transistor, the gate line Gate, the reset signal line Vint, and the light emission control signal line EM; wherein, the gate layer of the driving transistor can also be used as the first plate C 1 of the capacitor C .
  • the material of the gate metal layer 195 is, for example, metals or alloys such as silver, aluminum, and molybdenum.
  • the gate line Gate is electrically connected to the gate drive signal terminal Gate, and is used to provide the gate drive signal for the gate drive signal terminal Gate;
  • the reset signal line Reset is electrically connected to the reset signal terminal Reset, and is used to provide the reset signal terminal Reset.
  • the light-emission control signal line EM is electrically connected to the light-emission control signal terminal EM, and is used to provide the light-emission control signal to the light-emission control signal terminal EM.
  • the second metal layer 197 is used to form the initialization signal line Vint and the second plate C 2 of the capacitor C.
  • the material of the second metal layer 197 is, for example, metals or alloys such as silver, aluminum, and molybdenum.
  • the third metal layer 199 is used to form the source and drain of the thin film transistor, the data signal line Data, the first power supply voltage signal line VDD, the compensation voltage signal line, and the connection electrode.
  • the data signal line Data is electrically connected to the data signal terminal Data, and is used to provide data signals for the data signal terminal Data
  • the first power supply voltage signal line VDD is electrically connected to the first power supply voltage signal terminal VDD, and is used to provide the first power supply voltage
  • the signal terminal VDD provides the first power supply voltage signal
  • the compensation voltage signal line is electrically connected to the compensation voltage signal terminal, and is used to provide the compensation voltage signal to the compensation voltage signal terminal
  • the connection electrode is used to make the film layer (such as the first metal The layer 191 and the third metal layer 199) are electrically connected.
  • the material of the second metal layer 197 is, for example, metals or alloys such as silver, aluminum, and molybdenum.
  • FIG. 7C which is a structural diagram of the first metal layer 191
  • a through hole 1910 is provided on the first metal layer 191.
  • the through hole 1910 is used, for example, to electrically connect the first metal layer 191 to the compensation voltage signal line. , That is, the first metal layer 191 is electrically connected to a compensation voltage terminal.
  • the magnitude of the voltage provided by the compensation voltage signal line is equal to the first power supply voltage signal provided by the first power supply voltage signal line VDD.
  • the first power supply voltage signal line VDD is also a compensation voltage signal line, that is, the first power supply voltage signal line VDD is multiplexed as a compensation voltage signal line.
  • the voltage provided by the compensation voltage signal line is different from the first power supply voltage signal provided by the first power supply voltage signal line VDD, and the compensation voltage signal line and the first power supply voltage signal line VDD are two in the same layer. Signal wires of the same material.
  • the compensation voltage signal provided by the compensation voltage signal line is a fixed value, for example, equal to the magnitude of the power supply voltage signal; in different display panels 1, due to the influence of the process, the film in the different display panels 1
  • the threshold voltage of the transistor may deviate from the preset value in different degrees, so the magnitude of the compensation voltage signal provided by the compensation voltage terminal in different display panels 1 may be different.
  • the thin film transistors in the pixel driving circuit are, for example, P-type transistors
  • the first power supply voltage signal terminal VDD provides, for example, a high-level fixed voltage, so that the thin film transistors work more stably, and the thin film transistors
  • the interaction between the middle active layer and the first metal layer 191 adjusts the threshold voltage of the thin film transistor.
  • the material of the active layer 193 is, for example, polysilicon (P-si).
  • FIG. 7E it is a structural diagram of the gate metal layer 195, in which the gate layer of the driving transistor (the third transistor T3) also serves as the first plate C 1 of the capacitor C.
  • FIG. 7F it is a structural diagram of the second metal layer 197, in which a through hole 1910 is provided on the second plate C 2 of the capacitor C, and the through hole 1910 is used to make the capacitor C and the third metal layer 199 realizes electrical connection.
  • FIG. 7G it is a structural diagram of the third metal layer 199, in which the first power supply voltage signal line VDD and the through hole 1910 provided on the connecting electrode 1990 are used to implement various thin film transistors and signal lines (for example, including data signal lines).
  • Line Data the first power supply voltage signal line VDD, the light emission control signal line EM, the gate line Gate, the initialization signal line Vint, etc.
  • the overlapping portions of the data signal line Data and the first power supply voltage signal line VDD with the thin film transistor serve as the source and drain of the thin film transistor.
  • the display panel 1 further includes a barrier layer 110 disposed on the substrate 11, and the barrier layer 110 is used to isolate the substrate 11 from the thin film transistor to avoid the influence of substances in the substrate 11.
  • the active layer 193 in a thin film transistor is used to isolate the substrate 11 from the thin film transistor to avoid the influence of substances in the substrate 11.
  • the overall structure of the display panel 1 is, for example, refer to FIG. 7H.
  • an embodiment of the present disclosure further provides a display substrate 1 ′, including a substrate 11.
  • the first electrode 12 is arranged on one side of the substrate 11.
  • the pixel defining layer 13 is disposed on one side of the substrate 11 and includes a first hollow portion 130.
  • the first hollow portion 130 includes a first opening 1301 and a second opening 1302 disposed oppositely; compared to the second opening 1302, the first hollow The opening 1301 is closer to the substrate 11, wherein the first opening 1301 exposes at least part of the first electrode 12.
  • the substrate 11 For the explanation of the substrate 11, the first electrode 12 and the pixel defining layer 13, reference can be made to the explanation of the substrate 11, the first electrode 12 and the pixel defining layer 13 in the display panel 1, and therefore will not be repeated.
  • the sacrificial pattern 18 is disposed on a side of the pixel defining layer 13 away from the substrate 11, and the orthographic projection of the sacrificial pattern 18 on the pixel defining layer 13 does not overlap with the first opening 1301.
  • the material of the sacrificial pattern 18 is, for example, an organic material, or, for example, an organic material containing a fluorine element.
  • the material of the sacrificial pattern 18 is, for example, a metal material, such as metals or alloys such as silver (Ag), aluminum (Al), molybdenum (Mo), and titanium (Ti).
  • a metal material such as metals or alloys such as silver (Ag), aluminum (Al), molybdenum (Mo), and titanium (Ti).
  • the selected material of the sacrificial pattern 18 corresponds to the peeling liquid phase, for example, and different materials correspond to different peeling liquids.
  • the selected peeling liquid can dissolve the sacrificial pattern 18, but cannot react with other film layers in the display substrate 1'.
  • the sacrificial pattern 18 of the metal material can be an acidic or alkaline stripping liquid
  • the sacrificial pattern 18 of the negative photoresist material can be, for example, hydrofluoroethers as the stripping liquid.
  • the orthographic projection of the sacrificial pattern 18 on the pixel defining layer 13 does not overlap with the first opening 1301, including: referring to FIGS. 8E and 8I, the orthographic projection of the sacrificial pattern 18 on the pixel defining layer 13 coincides with one side of the first opening 1301 , And referring to FIGS. 8A to 8D and 8F to 8H, there is a gap between the orthographic projection of the sacrificial pattern 18 on the pixel defining layer 13 and the first opening 1301.
  • the orthographic projection of the sacrificial pattern 18 on the pixel defining layer 13 does not overlap with the first opening 1301, and is used to prevent the material (such as luminescent material) used to form the second light-emitting functional layer 24 from being blocked by the sacrificial pattern 18 from being completely covered At least part of the first electrode 12 is located in the first opening 1301.
  • the spacer 17 is disposed on a side of the sacrificial pattern 18 away from the substrate 11, and the orthographic projection of the spacer 17 on the pixel defining layer 13 does not overlap with the first opening 1301.
  • the second light-emitting function layer 24 is disposed on the side of the pixel defining layer 13 and the first electrode 12 away from the substrate 11.
  • the material of the spacer 17 is, for example, an organic material, or a photosensitive organic material, such as photoresist. In some embodiments, the material of the spacer 17 is a negative photoresist.
  • the spacer 17 includes a first surface and a second surface disposed opposite to each other along the thickness direction of the substrate 11. Compared with the second surface, the first surface is closer to the substrate 11;
  • the orthographic projection on the defining layer 13 falls within the orthographic projection of the second surface on the pixel defining layer 13, and the boundary between the orthographic projection of the first surface on the pixel defining layer 13 and the orthographic projection of the second surface on the pixel defining layer 13 There are gaps between the projected boundaries.
  • the center point of the orthographic projection of the first surface on the pixel defining layer 13 and the center point of the orthographic projection of the second surface on the pixel defining layer 13 coincide.
  • the orthographic projection of the first surface on the pixel defining layer 13 falls within the orthographic projection of the second surface on the pixel defining layer 13, indicating that the area of the first surface is smaller than the area of the second surface.
  • the first surface is, for example, a lower surface (a side surface close to the substrate 11 in the thickness direction of the substrate 11), and the second surface is, for example, an upper surface (a side surface away from the substrate 11 in the thickness direction of the substrate 11).
  • the longitudinal cross-sectional shape of the spacer 17 is, for example, an inverted trapezoid, and the length of the bottom side of the inverted trapezoid is smaller than the length of the top side.
  • the three-dimensional structure of the spacer 17 is, for example, a pyramid, the upper surface and the lower surface (opposite to the upper surface) of the pyramid, for example, are rectangular, and the upper surface The area of the rectangle is larger than the area of the bottom rectangle; or the three-dimensional structure of the spacer 17 can also be a circular truncated cone.
  • the upper and lower surfaces of the circular truncated cone can be round or oval, and the upper surface area is larger than The area of the lower surface.
  • the spacer 17 having an inverted trapezoidal longitudinal section can be formed through a patterning process (for example, including exposure, development, and etching).
  • the longitudinal cross-sectional shape of the spacer 17 may also be a "T" shape.
  • the T-shaped spacer 17 can be formed according to the principle that the same peeling liquid has different etching rates for different metals.
  • the height of the spacer 17 is, for example, 0.5 ⁇ m to 3 ⁇ m.
  • the second light-emitting function layer 24 that is subsequently vapor-deposited on the pixel defining layer 13 and the first electrode 12 can be sacrificed on the side wall of the spacer 17
  • the sidewalls of the pattern 18 are broken, that is, the second light-emitting function layer 24 cannot completely cover the sidewalls of the spacer 17 and the sidewalls of the sacrificial pattern 18. For example, referring to FIG.
  • the second light-emitting functional layer 24 covers part of the sidewalls of the sacrificial pattern 18, the remaining part of the sidewalls of the sacrificial pattern 18 is exposed, and the second light-emitting functional layer 24 also covers the upper surface of the spacer 17. , The side wall of the spacer 17 is exposed.
  • the second light-emitting function layer 24 covers a part of the upper surface of the spacer 17, and the side walls of the sacrificial pattern 18 and the side walls of the spacer 17 are exposed.
  • Exposure of the sidewalls of the sacrificial pattern 18 can facilitate the stripping liquid to enter the sacrificial pattern 18 to quickly dissolve the sacrificial pattern 18, and the sidewalls of the spacers 17 are exposed to facilitate subsequent removal of the spacers 17.
  • the peeling liquid can also penetrate the second The light-emitting function layer 24 enters the sacrificial pattern 18, thereby dissolving the sacrificial pattern; and when the sacrificial pattern 18 is dissolved, because the thickness of the second light-emitting function layer 24 is small, the stress in the film layer is not enough to block the spacer 17 and separate The cushion 17 can still fall off from the display substrate 1'.
  • the orthographic projection of the spacer 17 on the pixel defining layer 13 does not overlap with the first opening 1301, including: referring to FIGS. 8D and 8E, the orthographic projection of the spacer 17 on the pixel defining layer 13 is close to an area of the first opening 1301. The side coincides with the edge of the first opening 1301, and referring to FIGS. 8A to 8C and FIGS. 8F to 8I, there is a gap between the orthographic projection of the spacer 17 on the pixel defining layer 13 and the first opening 1301.
  • the orthographic projection of the spacer 17 on the pixel defining layer 13 does not overlap with the first opening 1301, which can ensure that when the second light-emitting functional layer 24 is subsequently evaporated, the second light-emitting functional layer 24 can completely cover the first opening 1301 At least part of the first electrode 12 in the middle, so as to ensure that the contact area between the second light-emitting function layer 24 and the first electrode 12 is relatively large.
  • the spacer 17 is located on the sacrificial pattern 18, wherein the first surface (lower surface) of the spacer 17 is in contact with the upper surface of the sacrificial pattern 18, and the length of the first surface of the spacer 17 is less than or equal to the length of the sacrificial pattern 18
  • the width of the first surface of the spacer 17 is less than or equal to the width of the sacrificial pattern 18, so as to ensure that the spacer 17 can be separated from the display substrate 1'after the sacrificial pattern 18 is removed.
  • the second light-emitting function layer 24 covers the pixel defining layer 13, the first electrode 12, and the spacer 17, wherein the second light-emitting function
  • the layer 24 completely covers the side surface (the second surface) of the spacer 17 away from the substrate 11.
  • the second light-emitting function layer 24 covers the pixel defining layer 13, the first electrode 12 and the spacer 17, wherein the second light-emitting function layer 24 covers the spacer 17 away from the substrate 11 The part of one side surface (second surface).
  • the second light-emitting function layer 24 covers the pixel defining layer 13 and the first electrode 12, and the second light-emitting function layer 24 does not cover the side surface (the second surface) of the spacer 17 away from the substrate 11.
  • the second light-emitting function layer 24 described above covers the second surface of the spacer 17, that is, whether there is a material for forming the second light-emitting function layer 24 on the second surface of the spacer 17, and the second light-emitting function layer 24 is vapor-deposited
  • the FMM used at this time is related to the shadow generated by the evaporation opening corresponding to each sub-pixel.
  • the material for forming the second light-emitting function layer 24 will be present on the second surface of the spacer 17, and when the vapor deposition opening is generated When the Shadow of ⁇ does not extend to the second surface of the spacer 17, the second surface of the spacer 17 will not have any material for forming the second light-emitting functional layer 24.
  • the second light-emitting functional layer 24 For the introduction of the material and internal layer structure of the second light-emitting functional layer 24 (ie, the layers included in the second light-emitting functional layer 24, such as the light-emitting layer), reference may be made to the introduction of the first light-emitting functional layer 14. After the sacrificial pattern 18 and the spacer 17 are removed, the second light-emitting function layer 24 becomes the first light-emitting function layer 14. After the sacrificial pattern 18 and the spacer 17 are removed, the structure of the second light-emitting function layer 24 may or may not be changed. For example, referring to FIG. 8A, the second light-emitting function layer 24 covers the second surface of the spacer 17.
  • the second light-emitting function layer 24 does not cover the second surface of the spacer 17. After the sacrificial pattern 18 and the spacer 17 are removed, the structure of the second light-emitting function layer 24 does not change.
  • the second light-emitting functional layer 24 is changed after the sacrificial pattern 18 and the spacer 17 are removed, the light-emitting function between the sacrificial pattern 18 and the spacer 17 will not be removed.
  • the layer is referred to as the second light-emitting functional layer 24, and the light-emitting functional layer after removing the sacrificial pattern 18 and the spacers 17 is referred to as the first light-emitting functional layer 14.
  • the display substrate 1'of the present disclosure is provided with sacrificial patterns 18 and spacers 17, wherein the spacers 17 are used to support the FMM used when the second light-emitting function layer 24 is evaporated, and the second light-emitting function layer is formed.
  • the sacrificial pattern 18 is removed, so that the spacer 17 is separated from the display substrate 1'.
  • the structure of the display substrate 1'after removing the sacrificial pattern 18 and the spacers 17 is the same as the structure of the display panel 1 described above, so for the advantages of the display substrate 1'after removing the sacrificial pattern 18 and the spacers 17, please refer to The foregoing description in the display panel 1 will not be repeated here.
  • the maximum size of the second surface in the spacer 17 is smaller than the maximum size of the first hollow portion 130.
  • the maximum size of the first hollow portion 130 may be the maximum size of the first opening 1301 or the maximum size of the second opening 1302. For example, if the maximum size of the second opening 1302 is greater than the maximum size of the first opening 1301, the maximum size of the second surface in the spacer 17 is smaller than the maximum size of the first hollow part 130, that is, the second in the spacer 17 The maximum size of the surface is smaller than the maximum size of the second opening 1302.
  • the maximum size of the second surface of the spacer 17 is the maximum distance between any two points on the boundary of the second surface of the spacer 17, and the maximum size of the second opening 1302 is between any two points on the boundary of the second opening 1302 The maximum distance.
  • the second surface of the spacer 17 and the second opening 1302 are both rectangular, the maximum size of the second surface of the spacer 17 is the length of the diagonal, and the maximum size of the second opening 1302 is The length of the diagonal.
  • the second surface of the spacer 17 is, for example, a rectangle, and the second opening 1302 is, for example, a hexagon.
  • the size of the spacer 17 is also at the sub-pixel level. Therefore, the size of the spacer 17 can be made smaller, which facilitates the subsequent removal of the spacer 17 by removing the sacrificial pattern 18.
  • the second light-emitting functional layer 24 can cover the gap, thereby ensuring that the second light-emitting functional layer 24 can completely cover the first opening 1302. At least part of the first electrode 12 exposed by the opening 1301. The larger the contact area between the second light-emitting function layer 24 and the first electrode 12, the larger the light-emitting area of the light-emitting diode.
  • the length of the first opening 1301 is smaller than the length of the second opening 1302.
  • the length of the first opening 1301 is smaller than the length of the second opening 1302, which can make the sidewall of the first hollow portion 130 bevel, thereby causing the pixel defining layer 13 to form an obtuse angle ⁇ .
  • the thickness of the sacrificial pattern 18 is greater than the thickness of the second light-emitting function layer 24.
  • the thickness of the sacrificial pattern 18 is, for example, 0.1 ⁇ m to 2 ⁇ m.
  • the thickness of the sacrificial pattern 18 is greater than the thickness of the second light-emitting functional layer 24, the sidewalls of the sacrificial pattern 18 (along its thickness direction) are not covered by the second light-emitting functional layer 24, thereby facilitating the increase of the sacrificial pattern 18
  • the area in contact with the stripping liquid in turn reduces the time required to remove the sacrificial pattern 18.
  • the display substrate 1'further includes a thin film transistor, which is disposed between the substrate 11 and the first electrode 12, and the source or drain of the thin film transistor is connected to the first electrode 12. Electric connection.
  • the structure of the thin film transistor included in the display substrate 1 ′ is the same as the structure of the thin film transistor included in the display panel 1, and therefore, the explanation of the thin film transistor in the display panel 1 can be referred to above.
  • the top view of the sacrificial pattern 18 and the spacer 17 is, for example, a rectangle, and the top view of the first hollow portion 130 is, for example, a hexagon.
  • the display substrate 1 ′ further includes a substrate 10 disposed on the side of the substrate 11 away from the thin film transistor.
  • the substrate 10 is, for example, a glass substrate.
  • the substrate 11 is formed on the substrate 10.
  • the overall structure of the display substrate 1' is, for example, refer to FIG. 9D.
  • the display substrate 1' has the same beneficial effects as the display panel 1, so it will not be repeated.
  • an embodiment of the present disclosure also provides a method for preparing a display substrate 1', including:
  • a first electrode 12 is formed on the substrate 11.
  • the material of the first electrode 12 is, for example, ITO.
  • ITO indium gallium oxide
  • a pixel defining layer 13 is formed on the substrate 11 on which the first electrode 12 is formed; the pixel defining layer 13 includes a first hollow portion 130, and the first hollow portion 130 includes a first opening 1301 and The second opening 1302 is closer to the substrate 11 than the second opening 1302, wherein the first opening 1301 exposes at least part of the first electrode 12.
  • An organic thin film is formed on the first electrode 12, and the first hollow portion 130 is formed through a patterning process, thereby forming the pixel defining layer 13.
  • the material of the organic film is, for example, polyimide.
  • a stacked sacrificial pattern 18 and spacers 17 are formed on the pixel defining layer 13, and the sacrificial pattern 18 is closer to the substrate 11 than the spacers 17.
  • both the sacrificial patterns 18 and the spacers 17 are multiple, and the sizes of the sacrificial patterns 18 and the spacers 17 are both small.
  • the maximum sizes of the sacrificial patterns 18 and the spacers 17 are both smaller than the first The maximum size of a hollow portion 130. In this structure, since the size of the spacer 17 is small, it is easier to detach from the display substrate 1'.
  • both the sacrificial patterns 18 and the spacers 17 are multiple, and the sizes of the sacrificial patterns 18 and the spacers 17 are both larger.
  • the maximum sizes of the sacrificial patterns 18 and the spacers 17 are both larger than The maximum size of the first hollow portion 130. In this structure, it is convenient to make the sacrificial pattern 18 and the spacer 17 through the process of drawing.
  • both the sacrificial pattern 18 and the spacer 17 are one, and the sizes of the sacrificial pattern 18 and the spacer 17 are both larger.
  • the maximum sizes of the sacrificial pattern 18 and the spacer 17 are both larger than the first The maximum size of a hollow portion 130.
  • the spacer 17 has better support stability for the FMM.
  • the substrate 11 on which the spacers 17 are formed and the mask plate 2 are placed opposite to each other.
  • the light-emitting functional material is vapor-deposited on the side where the spacer 17 is provided to form the second light-emitting functional layer 24.
  • the spacer 17 plays a role of supporting the mask plate 2.
  • the mask plate 2 is, for example, an FMM.
  • a plurality of evaporation openings 20 corresponding to the first hollow portion 130 are provided on the mask plate 2 to emit light.
  • the functional material is vapor-deposited on the first electrode 12 and the pixel defining layer 13 through the vapor deposition opening 20 to form the second light-emitting functional layer 24.
  • the light-emitting functional material includes all the materials used to form each film layer in the second light-emitting functional layer 24, for example, the organic electroluminescent material that forms the light-emitting layer and the material that forms the electron transport layer.
  • the material of the electron transport layer is, for example, Including materials such as cesium, lithium and silicon monoxide.
  • the structure of the second hollow portion 140 formed after the sacrificial pattern 18 and the spacer 17 are removed will be affected.
  • the length of the sacrificial pattern 18 is smaller than the width of the display substrate 1'.
  • the structure of the second hollow portion 140 is similar to the structure of the sacrificial pattern 18 The same or substantially the same, therefore, the first light-emitting function layer 14 formed by the second light-emitting function layer 24 is connected as a whole, and the second hollow portions 140 are arranged on the first light-emitting function layer 14 at intervals.
  • the first light-emitting function layer 14 formed by the second light-emitting function layer 24 is divided into multiple parts. There are two unconnected light-emitting functional patterns, but the gap between adjacent light-emitting functional patterns can still be understood as the second hollow portion 140 in the disclosure.
  • the preparation method of the above-mentioned display substrate 1' has the same beneficial effects as the above-mentioned display substrate 1', so it will not be repeated.
  • the stacked sacrificial patterns 18 and spacers 17 are formed on the pixel defining layer 13, including:
  • the first thin film is formed at a low temperature of 90° C., where the low temperature is beneficial to protect the characteristics of the organic material, thereby forming the quality of the first thin film better.
  • the patterning of the sacrificial patterns 18 and spacers 17 during the preparation process of the above-mentioned display substrate 1' is relatively low.
  • the stacked sacrificial patterns 18 and spacers 17 are formed on the pixel defining layer 13, including:
  • the process of patterning the sacrificial patterns 18 and spacers 17 in the preparation process of the display substrate 1' is relatively simple.
  • an embodiment of the present disclosure also provides a method for manufacturing the display panel 1, including:
  • the process of forming the first electrode 12 please refer to the process of forming the first electrode 12 in the above-mentioned display substrate 1'.
  • a pixel defining layer 13 is formed on the substrate 11 on which the first electrode 12 is formed; the pixel defining layer 13 includes: a first hollow portion 130, and the first hollow portion 130 includes a first opening 1301 and a second opening 1302 disposed oppositely Compared with the second opening 1302, the first opening 1301 is closer to the substrate 11, wherein the first opening 1301 exposes at least part of the first electrode 12.
  • a light-emitting functional material is vapor-deposited on one side to form the second light-emitting functional layer 24.
  • the process of forming the second light-emitting function layer 24 please refer to the process of forming the second light-emitting function layer 24 in the above-mentioned display substrate 1'.
  • the sacrificial pattern 18 is removed, so that the spacer 17 on the side of the sacrificial pattern 18 away from the substrate 11 is separated from the display panel 1 to form the first light-emitting functional layer 14 through the second light-emitting functional layer 24.
  • the sacrificial pattern 18 is dissolved by the peeling liquid, so that the spacer 17 falls by itself, so as to achieve the purpose of removing the spacer 17.
  • the manufacturing process of the above-mentioned display panel 1 has the same beneficial effects as the above-mentioned display substrate 1', so it will not be repeated here.
  • the manufacturing method of the display panel 1 further includes:
  • the manufacturing method of the display panel 1 further includes:
  • forming the encapsulation layer 111 includes, for example:
  • the introduction of the first inorganic encapsulation sublayer 1111, the organic encapsulation layer 111, and the second inorganic encapsulation sublayer 1112 can refer to the above description of the first inorganic encapsulation sublayer 1111, the organic encapsulation layer 111, and the second inorganic encapsulation layer in the display panel 1.
  • the introduction of the sub-layer 1112 will not be repeated here.
  • the manufacturing method of the display panel 1 before forming the first electrode 12, the manufacturing method of the display panel 1 further includes:
  • a substrate 11 is formed on the substrate 10, and the material of the substrate 11 is, for example, polyimide.
  • the manufacturing method of the display panel 1 further includes: forming a thin film transistor on the substrate.
  • At least an active layer film, a first gate insulating layer 194, a gate metal film, a second gate insulating layer 196, and a third metal film are formed on one side of the substrate 11, and the active layer is formed by a patterning process 193.
  • the same reference signs can be understood as signal terminals, and can also be understood as signal lines and signals.
  • Data can be understood as both data signal terminals and data signal lines and data signals.
  • “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form a patterning process.
  • the same patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板（1）及其制备方法、显示基板及其制备方法和显示装置。一种显示面板（1），包括：衬底（11）、第一电极（12）、像素界定层（13）和第一发光功能层（14）。其中，第一电极（12），设置于衬底（11）的一侧；像素界定层（13），设置于衬底（11）的一侧，包括第一镂空部（130），第一镂空部（130）包括相对设置的第一开口（1301）和第二开口（1302）；相比于第二开口（1302），第一开口（1301）更靠近衬底（11），且第一开口（1301）露出第一电极（12）的至少部分；第一发光功能层（14），设置于像素界定层（13）和第一电极（12）远离衬底（11）的一侧，包括第二镂空部（140），第二镂空部（140）在像素界定层（13）上的正投影与第一开口（1301）不重叠。

Description

显示面板及其制备方法、显示基板及其制备方法和显示装置
本申请要求于2020年6月4日提交的、申请号为202010501773.3的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制备方法、显示基板及其制备方法和显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)是一种通过有机薄膜电致发光的器件，常用于显示装置中。OLED显示装置具有自发光、发光效率高、响应时间短、清晰度和对比度高、可实现柔性显示等优点，从而被应用在越来越多的场合中。
发明内容
一方面，提供一种显示面板。所述显示面板包括衬底、第一电极、像素界定层和第一发光功能层。
所述第一电极设置于所述衬底的一侧。
所述像素界定层，设置于所述衬底的一侧，包括第一镂空部，所述第一镂空部包括相对设置的第一开口和第二开口；相比于所述第二开口，所述第一开口更靠近所述衬底，其中所述第一开口露出所述第一电极的至少部分。
所述第一发光功能层，设置于所述像素界定层和所述第一电极远离所述衬底的一侧，包括第二镂空部，所述第二镂空部在所述像素界定层上的正投影与所述第一开口不重叠。
在一些实施例中，所述第二镂空部在所述像素界定层上的正投影与所述第二开口之间具有间隙。
在一些实施例中，所述第二镂空部的最大尺寸小于所述第一镂空部的最大尺寸。
在一些实施例中，所述显示面板还包括：第二电极，设置于所述第一发光功能层远离所述衬底的一侧，且所述第二电极覆盖所述第二镂空部。
在一些实施例中，所述显示面板还包括：薄膜晶体管，设置于所述衬底与所述第一电极之间，且所述薄膜晶体管的源极或漏极与所述第一电极电连接。
在一些实施例中，所述薄膜晶体管还包括：沿远离衬底一侧方向层叠的有源层、第一栅绝缘层、栅极层、第二栅绝缘层、层间绝缘层；所述薄膜晶 体管的源极和漏极设置于所述层间绝缘层远离所述衬底的一侧，且通过贯穿所述层间绝缘层、第二栅绝缘层和第一栅绝缘层的过孔与所述有源层接触。
在一些实施例中，所述显示面板还包括：第一金属层，所述第一金属层设置于所述薄膜晶体管与所述衬底之间，且所述第一金属层与一补偿电压端电连接，所述补偿电压端被配置为提供用于补偿所述薄膜晶体管的阈值电压的补偿电压信号。
在一些实施例中，所述显示面板还包括：封装层，所述封装层包括沿远离衬底一侧方向层叠的第一无机封装子层、有机封装子层和第二无机封装子层。
另一方面，提供一种显示基板，包括：衬底、第一电极、像素界定层、牺牲图案、隔垫物和第二发光功能层。
所述第一电极设置于所述衬底的一侧。
所述像素界定层设置于所述衬底的一侧，包括第一镂空部，所述第一镂空部包括相对设置的第一开口和第二开口；相比于所述第二开口，所述第一开口更靠近所述衬底，其中所述第一开口露出所述第一电极的至少部分。
所述牺牲图案设置于像素界定层远离所述衬底的一侧，且所述牺牲图案在所述像素界定层上的正投影与所述第一开口不重叠。
所述隔垫物设置于所述牺牲图案远离所述衬底的一侧，所述隔垫物在所述像素界定层上的正投影与所述第一开口不重叠。
所述第二发光功能层设置于所述像素界定层和所述第一电极远离所述衬底的一侧。
在一些实施例中，所述隔垫物包括沿远离衬底一侧方向相对设置的第一表面和第二表面，相对于所述第二表面，所述第一表面更靠近所述衬底；其中，所述第一表面在所述像素界定层上的正投影落在所述第二表面在所述像素界定层上的正投影以内，且所述第一表面在所述像素界定层上的正投影的边界与所述第二表面在所述像素界定层上的正投影的边界之间存在间隙。
在一些实施例中，所述第二表面的最大尺寸小于所述第一镂空部的最大尺寸。
在一些实施例中，所述隔垫物在所述像素界定层上的正投影与所述第二开口之间具有间隙。
在一些实施例中，所述牺牲图案的厚度大于所述第二发光功能层的厚度。
在一些实施例中，所述显示基板还包括：薄膜晶体管，设置于所述衬底与所述第一电极之间，且所述薄膜晶体管的源极或漏极与所述第一电极电连 接。
又一方面，提供一种显示装置，包括如上所述的显示面板。
又一方面，提供一种显示基板的制备方法，包括：
在衬底上形成第一电极。
在形成有第一电极的衬底上形成像素界定层；所述像素界定层包括：第一镂空部，所述第一镂空部包括相对设置的第一开口和第二开口，相比于所述第二开口，所述第一开口更靠近所述衬底，其中所述第一开口露出所述第一电极的至少部分。
在所述像素界定层上形成层叠的牺牲图案和隔垫物，相对于所述隔垫物，所述牺牲图案更靠近所述衬底。
将形成有所述隔垫物的衬底与掩膜板相对设置，所述隔垫物与所述掩膜板抵接，透过所述掩膜板向所述衬底设置有所述隔垫物的一侧蒸镀发光功能材料，以形成第二发光功能层。
在一些实施例中，在所述像素界定层上形成层叠的牺牲图案和隔垫物，包括：在形成有所述像素界定层的衬底上形成第一薄膜，并将第一薄膜图案化，以形成位于所述像素界定层远离衬底一侧的牺牲图案。
在形成有牺牲图案的衬底上形成第二薄膜，并将第二薄膜图案化，以形成位于所述牺牲图案远离所述衬底一侧的隔垫物。
在另一些实施例中，在所述像素界定层上形成层叠的牺牲图案和隔垫物，包括：在形成有所述像素界定层的衬底上形成第一薄膜。
在第一薄膜上形成第二薄膜。
同时将第一薄膜和第二薄膜图案化，以形成层叠的牺牲图案和隔垫物。
又一方面，提供一种显示面板的制备方法，包括：
如上所述的显示基板的制备方法。
去除所述显示基板中的牺牲图案，以使得所述显示基板中位于所述牺牲图案远离衬底一侧的隔垫物脱离所述显示基板，以通过第二发光功能层形成第一发光功能层。
在一些实施例中，所述显示面板的制备方法还包括：
在形成有第一发光功能层的衬底上形成第二电极。
在所述第二电极上形成第一无机封装子层。
在所述第一无机封装子层上形成有机封装子层。
在所述有机封装子层上形成第二无机封装子层，所述第一无机封装子层、所述有机封装子层和所述第二无机封装子层构成封装层。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A～1G为根据本公开的一些实施例提供的一种显示面板的结构图；
图2为根据本公开的一些实施例提供的一种第一发光功能层的结构图；
图3A～图3C为根据本公开的一些实施例提供的一种显示面板的制备过程图；
图4A和图4B为根据本公开的一些实施例提供的另一种显示面板的结构图；
图5为根据本公开的一些实施例提供的一种像素驱动电路的结构图；
图6为根据本公开的一些实施例提供的一种像素驱动电路的时序图；
图7A为根据本公开的一些实施例提供的另一种显示面板的结构图；
图7B为图7A中A-A′向的截面图；
图7C为根据本公开的一些实施例提供的一种第一金属层的结构图；
图7D为根据本公开的一些实施例提供的一种有源层的结构图；
图7E为根据本公开的一些实施例提供的一种栅极金属层的结构图；
图7F为根据本公开的一些实施例提供的一种第二金属层的结构图；
图7G为根据本公开的一些实施例提供的一种第三金属层的结构图；
图7H为根据本公开的一些实施例提供的另一种显示面板的结构图；
图8A～8I为根据本公开的一些实施例提供的一种显示基板的结构图；
图9A为根据本公开的一些实施例提供的另一种显示基板的结构图；
图9B为图9A中B-B′向的截面图；
图9C为根据本公开的一些实施例提供的一种第一电极、第一镂空部、牺牲图案和隔垫物的结构图；
图9D为根据本公开的一些实施例提供的另一种显示基板的结构图；
图10A为根据本公开的一些实施例提供的一种显示基板的制备方法的流程图；
图10B～10G为根据本公开的一些实施例提供的一种显示基板的制备过程图；
图10H为图10G中C-C′向的截面图；
图11A为根据本公开的一些实施例提供的一种显示面板的制备方法的流程图；
图11B为根据本公开的一些实施例提供的一种显示面板的制备过程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术 语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量***的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供一种显示装置，该显示装置例如为电致发光显示装置。
在一些实施例中，电致发光显示装置例如包括显示面板，显示面板可以为OLED显示面板或者量子点电致发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板。
参考图1A～图1G，显示面板1例如包括：
衬底11，该衬底11例如为柔性衬底，该柔性衬底的材料例如为聚酰亚胺(Polyimide，PI)。
至少一个第一电极12，设置于衬底11的一侧。第一电极12例如为透明电极，又例如为阳极，其材料例如包括氧化铟锡(Indium Tin Oxide，ITO)。在一些实施例中，第一电极12为多个。
像素界定层13，设置于衬底11的一侧，包括至少一个第一镂空部130，第一镂空部130包括相对设置的第一开口1301和第二开口1302。相比于第二开口1302，第一开口1301更靠近衬底11，其中第一开口1301露出第一电极12的至少部分。
在一些实施例中，参考图1A～图1E，第一开口1301的尺寸和第二开口1302的尺寸完全相同，此处的尺寸例如包括长度和宽度。
在另一些实施例中，参考图1F和图1G，第一开口1301的尺寸和第二开口1302的尺寸不同，例如长度和宽度中的至少一个不同。
在一些实施例中，第一镂空部130的数量例如大于等于第一电极12的数量，多余的第一镂空部130例如用于实现显示面板1中各膜层之间的跨层电连接。
在一些实施例中，参考参考图1A～图1D、图1F和图1G，第一镂空部130露出第一电极12远离衬底11一侧的表面的部分。
在另一些实施例中，参考图1E，第一镂空部130露出第一电极12远离衬底11的一侧的表面的全部。
第一发光功能层14，设置于像素界定层13和第一电极12远离衬底11的一侧，包括第二镂空部140，第二镂空部140在像素界定层13上的正投影与第一开口1301不重叠。
其中，第一发光功能层14至少包括发光层，发光层的材料例如可以包括有机电致发光材料。
参考图2，第一发光功能层14除包括发光层141外，还可以包括电子传输层(election transporting layer，ETL)142、电子注入层(election injection layer，EIL)143、空穴传输层(hole transporting layer，HTL)144以及空穴注入层(hole injection layer，HIL)145。需要说明的是，第一发光功能层14并不限于仅包括发光层141和ETL142、EIL143、HTL144、HIL145的组合，其还可以包括其它功能层别。
第二镂空部140在像素界定层13上的正投影与第一开口1301不重叠包 括：
参考图1A～图1C、图1E和图1F，沿衬底11的厚度方向，衬底的厚度方向为与衬底的一侧和衬底的另一侧垂直的方向，第二镂空部140在像素界定层13上的正投影与第一开口1301之间具有间隙，且第一发光功能层14覆盖该间隙。
参考图1D，沿衬底11的厚度方向，第二镂空部140在像素界定层13上的正投影与第一开口1301之间紧挨，即第二镂空部140与第一开口1301之间不具有间隙；同时第二镂空部140在像素界定层13上的正投影与第二开口1302之间也紧挨。
参考图1G，沿衬底11的厚度方向，第二镂空部140在像素界定层13上的正投影与第一开口1301之间具有间隙，同时第二镂空部140在像素界定层13上的正投影与第二开口1302之间部分重叠。
在制作第一发光功能层14时，需要使用精细金属掩膜板(Fine metal mask，FFM)来蒸镀用于形成第一发光功能层14的材料，但是为了避免精细金属掩膜板划伤在制作第一发光功能层14前已制作好的膜层，例如像素界定层13和第一电极12等，从而会在像素界定层13上设置隔垫物17用于支撑FMM，使得FMM与已制作好的膜层之间具有一定距离，不会直接接触，从而保护已制作好的膜层。
参考图3A～图3C，在显示面板1的制备过程中，会在像素界定层13上设置层叠的牺牲图案18和隔垫物17，牺牲图案18位于隔垫物17和像素界定层13之间，牺牲图案18后续会被去除(例如可以通过溶解的方式去除)，从而使得隔垫物17可以脱离显示面板1。在第一电极12、像素界定层13和隔垫物17远离衬底11的一侧形成有第二发光功能层24，第二发光功能层24覆盖第一电极12和像素界定层13，在一些实施例中，第二发光功能层24还覆盖隔垫物17。在去除牺牲图案18和隔垫物17后，或者在去除牺牲图案18、隔垫物17以及位于隔垫物17上的部分第二发光功能层24后，会在第二发光功能层24上形成了一个镂空部，该镂空部可以理解为第二镂空部140，此时过程可以理解为通过第二发光功能层24形成了具有第二镂空部140的第一发光功能层14。
参考图3A和图3B，第二发光功能层24覆盖像素界定层13、隔垫物17和第一电极12；参考图3C，第二发光功能层24覆盖像素界定层13和第一电极12；参考图1A～图1G，第一发光功能层14覆盖像素界定层13和第一电极12，也就是说第二发光功能层24的结构可能和第一发光功能层14的不同， 因此本公开中为了区分发光功能层不同阶段的结构，从而使用第一发光功能层14和第二发光功能层24进行区分，而本领域技术人员可以理解的是，第一发光功能层14是通过第二发光功能层24制备的，或者，也可以理解为第一发光功能层14是第二发光功能层24的至少部分。
由于隔垫物17存在于显示面板1的制备过程中，其不仅可以起到支撑FMM的作用，使得第二发光功能层24顺利制备，且在第二发光功能层24制备完成后，可以通过先去除牺牲图案18，以使得隔垫物17脱离显示面板1，以及可以去除在移除FMM的过程中导致隔垫物17所产生的异物颗粒，从而为后续制备封装层提供一个较好的支撑面。
去除牺牲图案18例如可以采用湿法刻蚀、干法刻蚀等方式；其中的湿法刻蚀例如采用剥离液溶解牺牲图案18，干法刻蚀例如采用气体与牺牲图案18发生反应，从而刻蚀掉牺牲图案18。
牺牲图案18被去除后，隔垫物17失去了支撑，从而便可以从显示面板1上脱离(也可称为掉落)下来。
在相关技术中，由于隔垫物17的材料为有机材料，而在使用FMM时，在FMM的安装或者拆卸过程中，FMM可能会划伤隔垫物17，从而产生异物颗粒。一方面，隔垫物17的密度和其所产生的异物颗粒会影响在第一发光功能层14后所制备的膜层的品质，在第一发光功能层14后所制备的膜层例如包括封装层，封装层至少包括有机封装子层，有机封装子层例如可以通过喷墨打印(Ink jet printing，IJP)的方式形成，由于有机封装子层的材料具有一定的流动性，从而隔垫物17的密度会影响其流动性，例如在一些隔垫物17密度较大的区域，有机封装子层中的材料的流动性减小，从而形成厚度较大的部分有机封装子层，而在另一些隔垫物17密度较小的区域，有机封装子层的材料的流动性增加，从而形成厚度较小的部分有机层封装层，因此，最终导致有机封装子层各处的膜层厚度不同，膜厚均一性较差，且异物颗粒可能导致有机封装子层存在缺陷，影响有机封装子层的封装效果。另一方面，显示面板1还会因为隔垫物17的高度差异，例如沿显示面板1的长度方向，若左右两侧隔垫物17的高度不同，则导致显示面板1的边缘亮度与其它区域的不同，从而导致显示面板1产生色偏现象，影响显示效果。因此，在该相关技术中，隔垫物17的存在会影响在第一发光功能层14后所制备的膜层的品质，还会影响显示面板1的显示效果。
而在本公开中，在显示面板1的制备过程中，会在像素界定层13上形成牺牲图案18和隔垫物17，用以支撑FMM，而在第二发光功能层24制备完成 后，又会通过去除牺牲图案18去除或移除隔垫物17，从而通过第二发光功能层24制备出了具有第二镂空部140的第一发光功能层14。所以，一方面，在制备本公开中的有机封装子层时，由于无隔垫物17的阻挡，制备的有机封装子层各处的膜层厚度接近，膜厚均一性较好，可以改善显示面板1的封装效果；另一方面，隔垫物17由于被FMM刮伤所产生的异物颗粒也会被去除，从而制备出的有机封装子层不会因异物颗粒而出现缺陷，膜层的品质也较好，可以进一步改善显示面板1的封装效果；再一方面，由于不存在隔垫物17，显示面板1便不会因为隔垫物17的高度差异而产生色偏现象，从而显示面板1的显示效果也较好；又一方面，由于无隔垫物17，还可以使得显示面板1的厚度减小，从而制备出厚度更小的显示面板1，更符合显示面板1向着轻薄化发展的趋势，以及提高显示面板1的市场竞争力。
在一些实施例中，参考图1A～图1C、图1E和图1F，第二镂空部140在像素界定层13上的正投影与第二开口1302之间具有间隙。当第二镂空部140在像素界定层13上的正投影与第二开口1302之间具有间隙时，形成的第一发光功能层14会覆盖该间隙，从而可以保证第一发光功能层14完全覆盖第一开口1301，进而保证了第一发光功能层14与第一电极12之间的接触面积较大。若第一发光功能层14未完全覆盖第一开口1301，则第一发光功能层14也未完全覆盖第一开口1301所露出部分第一电极12，也就是说，第一开口1301露出的部分第一电极12中仅部分区域覆盖有第一发光功能层14，剩余部分区域未被第一发光功能层14所覆盖，从而使得第一发光功能层14与第一电极12之间的接触面积较小，最终导致有机发光二极管的发光面积较小，而本公开可以保证第一发光功能层14与第一电极12之间的接触面积较大，进而保证有机发光二极管的发光面积较大。
在一些实施例中，在第一镂空部130在衬底11上的正投影为矩形时，参考图1A～图1G，第一开口1301的长度小于等于第二开口1302的长度。
第一开口1301和第二开口1302的长度方向例如为显示面板1的长度方向，显示面板1的长度方向例如参考图1A～图1G，沿从左向右或者从右向左的方向。
其中，参考图1A～图1E，第一开口1301的长度等于第二开口1302的长度，此时便于形成第一开口1301和第二开口1302。
参考图1F和图1G，第一开口1301的长度小于第二开口1302的长度，从而使得第一镂空部130的侧壁为斜面，便于让后续制备的第一发光功能层14附着在第一镂空部130的侧壁上，进一步保证第一发光功能层14完全覆盖 第一开口1301所露出的第一电极12的至少部分。
在一些实施例中，第一镂空部130的最大尺寸为第一镂空部130在衬底11上的正投影的边界上任意两点之间的最大距离，第二镂空部140的最大尺寸为第二镂空部140在衬底11上的正投影的边界上任意两点之间的最大距离。
示例的，第一镂空部130的最大尺寸例如为其最大长度，第二镂空部140的最大尺寸例如为其最大长度。下面对影响第一镂空部130和第二镂空部140长度的因素进行分析：
参考图3A～图3C，第二镂空部140的长度与牺牲图案18和隔垫物17的长度相关。
示例的，参考图3A和图3C，第二镂空部140的长度等于牺牲图案18的长度。
又示例的，参考图3B，第二镂空部140的长度等于隔垫物17远离衬底11的一侧表面的长度。因此，调整第二镂空部140的长度可以通过改变牺牲图案18和/或隔垫物17远离衬底11的一侧表面的长度来实现。
在此基础上，第二镂空部140的最大尺寸(例如其长度)与第一镂空部130的最大尺寸(例如其长度)存在以下关系：
示例的，参考图1A、图1D，图1E、图1F和图1G，第二镂空部140的长度小于第一镂空部130的长度。
参考图1B，第二镂空部140的长度等于第一镂空部130的长度。
参考图1C，第二镂空部140的长度大于第一镂空部130的长度。
其中，当第二镂空部140的最大尺寸小于第一镂空部130的最大尺寸时，第二镂空部140的整体尺寸较小，便于在第一发光功能层14上形成第二镂空部140，以及使得第二镂空部140与第二开口1302之间存在间隙。
在一些实施例中，参考图4A，显示面板1还包括：第二电极15，设置于第一发光功能层14远离衬底11的一侧，且第二电极15覆盖第二镂空部140。
第二电极15覆盖第二镂空部140，即用于形成第二电极15的材料填充在第二镂空部140中。
第二电极15的材料例如为银，第二电极15例如为半透明电极，以使得有机发光二极管所产生的光线透过第二电极15出射。上述，第一电极12例如为阳极，第二电极15例如为阴极。
本领域技术人员可以理解的是，有机发光二极管包括第一电极12、第二电极15，以及位于第一电极12和第二电极15之间的部分第一发光功能层14， 有机发光二极管也可称为发光器件D，发光器件D用于为显示面板1提供光源。
在一些实施例中，参考图4B，显示面板1还包括封装层111，封装层111包括沿衬底11厚度方向层叠的第一无机封装子层1111、有机封装子层1113和第二无机封装子层1112。
第一无机封装子层1111和第二无机封装子层1112的材料例如为氮化硅、氧化硅中的至少一种。形成第一无机封装子层1111和第二无机封装子层1112例如可采用磁控溅射的方式。
有机封装子层1113采用喷墨打印的方式形成，而在本公开的实施例中，在形成有机封装子层1113时，显示面板1上已不存在隔垫物17，所以在形成机封装子层1113的过程中，用于制作有机封装子层1113的材料的流动性较好，从而制作的有机封装子层1113的膜层质量和膜厚均一性较好。
参考图5，本公开的实施例提供一种像素驱动电路3，该像素驱动电路3包括：复位子电路31、数据写入子电路32、驱动子电路33、发光控制子电路34。
复位子电路31与复位信号端Reset、初始化信号端Vint、节点N和发光器件D的第一极电连接。在另一些实施例中，复位子电路31还可以与栅极驱动信号端Gate电连接。复位子电路31被配置为在复位信号端Reset的控制下，将初始化信号端Vint提供的初始化信号传输至节点N，对节点N复位；还被配置为在复位信号端Reset或栅极驱动信号端Gate的控制下，将初始化信号端Vint提供的初始化信号传输至发光器件D的第一极，对发光器件D的第一极复位。
数据写入子电路32与数据信号端Data、栅极驱动信号端Gate和驱动子电路33电连接。数据写入子电路32被配置为，在栅极驱动信号端Gate的控制下，将数据信号端Data提供的数据信号写入驱动子电路33中。
驱动子电路33与栅极驱动信号端Gate、节点N和第一电源电压信号端VDD电连接。驱动子电路33配置为，在栅极驱动信号的控制下，将数据信号和驱动晶体管的阈值电压写入第一节点，对电容C充电；以及在第一电源电压信号端VDD和节点N的控制下，向发光器件D输出驱动信号，驱动信号例如为驱动电流信号。
发光控制子电路34与第一电源电压信号端VDD、发光控制信号端EM、驱动子电路33和发光器件D的第一极电连接。发光控制子电路34被配置为在发光控制信号端EM的控制下，使得驱动晶体管的第一极与第一电源电压 信号端VDD电连接，驱动晶体管的第二极与发光器件D电连接。
示例的，上述的像素驱动电路3例如可以为7T1C型像素驱动电路。7T1C型像素驱动电路例如包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和电容C；其中第三晶体管T3为驱动晶体管。
第一晶体管T1至第七晶体管T7中的部分或者全部例如可以为P型薄膜晶体管。
示例的，薄膜晶体管的第一极例如为源极，第二极例如为漏极。
参考图5，第一晶体管T1的栅极与复位信号端Reset电连接，第一极与初始化信号端Vint电连接，第二极与节点N电连接。
第二晶体管T2的栅极与栅极驱动信号端Gate电连接，第一极与第三晶体管T3的第二极电连接，第二极与节点N电连接。第二晶体管T2为补偿晶体管，可以使得第三晶体管T3的阈值电压和数据信号之和被写入节点N。
第三晶体管T3的栅极与节点N电连接，第一极与第四晶体管T4的第二极电连接。
第四晶体管T4的栅极与栅极驱动信号端Gate电连接，第一极与数据信号端Data电连接。
第五晶体管T5的栅极与发光控制信号端EM电连接，第一极与第一电源电压信号端VDD电连接，第二极与第三晶体管T3的第一极电连接。
第六晶体管T6的栅极与发光控制信号端EM电连接，第一极与第三晶体管T3的第二极电连接，第二极与发光器件D的第一极电连接。
第七晶体管T7的栅极与栅极驱动信号端Gate电连接，第一极与初始化信号端Vint电连接，第二极与发光器件D的第一极电连接。在另一些实施例中，第七晶体管T7的栅极还可以与复位信号端Reset电连接，以通过复位信号控制第七晶体管T7的工作状态。
电容C的一端与节点N电连接，另一端与第一电源电压信号端VDD电连接。示例的，电容C的一端为其第一极板C 1，另一端为其第二极板C 2。
发光器件D的第二极与第二电源电压信号端VSS电连接。
示例的，第一电源电压信号端VDD例如与显示面板1中的第一电极12电连接，第二电源电压信号端VSS例如与显示面板1中的第二电极15电连接。
结合图5和图6，像素驱动电路3的工作阶段例如包括复位阶段D1、数据写入阶段D2和发光阶段D3。
在复位阶段D1，在复位信号端Reset的控制下，第一晶体管T1开启，将 初始化信号端Vint提供的初始信号传输至节点N，对节点N复位。
在第七晶体管T7的栅极与复位信号端Reset电连接的情况下：在复位信号端Reset的控制下，第七晶体管T7开启，初始化信号端Vint提供的初始信号传输至发光器件D的第一极，对发光器件D的第一极进行复位。
在数据写入阶段D2：在栅极驱动信号的控制下，第四晶体管T4和第二晶体管T2开启，将数据信号端Data提供的数据信号和第三晶体管T3的阈值电压写入节点N。
在第七晶体管T7的栅极与栅极栅极驱动信号端Gate电连接的情况下：在栅极驱动信号端Gate的控制下，第七晶体管T7开启，将初始化信号端Vint提供的初始化信号传输至发光器件D的第一极，对发光器件D的第一极进行复位。
在发光阶段D3：在发光控制信号端EM的控制下，第五晶体管T5和第六晶体管T6开启；其中，第五晶体管T5使得第三晶体管T3的第一极与第一电源电压信号端VDD电连接，第六晶体管T6使得第三晶体管T3的第二极与发光器件D的第一极电连接，从而使得第三晶体管T3可以驱动发光器件D发光。
本领域技术人员可以理解的是，在上述过程中，无论第七晶体管T7的栅极与栅极驱动信号端Gate还是复位信号端Reset电连接，当第七晶体管T7开启时，均可以对发光器件D的第一极进行复位。其中，当第七晶体管T7的栅极与栅极驱动信号端Gate电连接时，栅极驱动信号在数据写入阶段D2才为有效信号，从而使得对发光器件D的复位过程处于数据写入阶段D2中，而当第七晶体管T7的栅极与复位信号端Reset电连接时，复位信号在复位阶段D1即为有效信号，从而使得对发光器件D的复位过程处于复位阶段D1中，但是该两种实施方式并不会影响复位子电路31的功能，因此，本公开的实施例中将第七晶体管T7归入了复位子电路31中。
基于上述，像素驱动电路3中各个薄膜晶体管(第一晶体管T1～第七晶体管T7)在显示面板1中的具体结构可以参考图7A；其中，第七晶体管T7的栅极与复位信号端Reset电连接。
其中，像素驱动电路3中的第三晶体管T3的第一极与第一电极12电连接，第一镂空部130露出了至少部分第一电极12。第三晶体管T3的栅极层作为了电容C的第一极板C 1，电容C的第二极板C 2与第一极板C 1沿衬底11厚度方向相对设置。电容C的第二极板C 2与初始化信号线Vint同层同材料。
示例的，第一晶体管T1和第二晶体管T2例如还可以为双栅型薄膜晶体 管，且该双栅型薄膜晶体管的两个栅极层同层同材料。
示例的，参考图7B，沿衬底11厚度方向，显示面板1包括依次远离衬底11的第一金属层191、缓冲层192、有源层193、第一栅绝缘层194、栅极金属层195、第二栅绝缘层196、第二金属层197、层间绝缘层198、第三金属层199和平坦层16。
其中，缓冲层192、第一栅绝缘层194、第二栅绝缘层196和层间绝缘层198均为绝缘层，起绝缘作用，该些绝缘层的材质例如为氧化硅、氮化硅中的至少一种。
其中，有源层193、第一栅绝缘层194、栅极层、第二栅绝缘层196、层间绝缘层198、源极和漏极构成了薄膜晶体管。在另一些实施例中，薄膜晶体管还可以包括缓冲层192。
其中，平坦层16起平坦化作用，其材料例如为有机材料，例如光刻胶和树脂中的至少一种。
第一金属层191可以作为遮光层和第一晶体管T1～T7薄膜晶体管T7的第二栅极层。第一金属层191的材料例如为银、铝等金属或合金。当第一金属层191作为遮光层时，可以降低第一晶体管T1～T7薄膜晶体管T7的漏电流大小；当第一金属层191作为第二栅极层时，其需要与一补偿电压端电连接，该补偿电压端可以提供补偿电压信号，该补偿电压信号用于补偿薄膜晶体管的阈值电压。当第一金属层191作为第二栅极层时，第一晶体管T1～第七晶体管T7均至少包括两个沿衬底11厚度方向相对设置的栅极层；对于还可以包括同层同材料的两个栅极层的第一晶体管T1和第二晶体管T2中的任一个薄膜晶体管而言，则具有了3个栅极层。
当薄膜晶体管的阈值电压Vth因制作薄膜晶体管中各膜层的工艺影响而偏离预设值时，可通过补偿电压端提供的补偿电压信号来补偿阈值电压Vth的偏差值。在薄膜晶体管为P型管的情况下，薄膜晶体管的阈值电压Vth小于0，补偿电压端提供的补偿电压信号大于0，其中，随着补偿电压端提供的补偿电压信号的增大，薄膜晶体管的阈值电压Vth减小。所以，当阈值电压Vth因工艺原因而偏大时，可通过增大补偿电压端提供的补偿电压信号来进行补偿，以使得偏大的阈值电压Vth减小至预设值。
示例的，薄膜晶体管的阈值电压Vth的预设值为-3.0V，当因工艺原因导致阈值电压Vth的实际值为-2.5V时，可以通过增大补偿电压端提供的补偿电压信号使得阈值电压Vth从-2.5V降低至-3.0V，从而实现补偿薄膜晶体管的阈值电压的作用。
栅极金属层195用于形成薄膜晶体管的栅极层、栅线Gate、复位信号线Vint、发光控制信号线EM；其中，驱动晶体管的栅极层还可以作为电容C的第一极板C 1。栅极金属层195的材料例如为银、铝、钼等金属或合金。
上述，栅线Gate与栅极驱动信号端Gate电连接，用于为栅极驱动信号端Gate提供栅极驱动信号；复位信号线Reset与复位信号端Reset电连接，用于为复位信号端Reset提供复位信号；发光控制信号线EM与发光控制信号端EM电连接，用于为发光控制信号端EM提供发光控制信号。
第二金属层197用于形成初始化信号线Vint和电容C的第二极板C 2。第二金属层197的材料例如为银、铝、钼等金属或合金。
第三金属层199用于形成薄膜晶体管的源极和漏极、数据信号线Data、第一电源电压信号线VDD、补偿电压信号线以及连接电极。其中，数据信号线Data与数据信号端Data电连接，用于为数据信号端Data提供数据信号；第一电源电压信号线VDD与第一电源电压信号端VDD电连接，用于为第一电源电压信号端VDD提供第一电源电压信号；补偿电压信号线与补偿电压信号端电连接，用于为补偿电压信号端提供补偿电压信号；连接电极用于使得需要电连接的膜层(例如第一金属层191和第三金属层199)实现电连接。第二金属层197的材料例如为银、铝、钼等金属或合金。
示例的，参考图7C，为第一金属层191的结构图，在第一金属层191上设有通孔1910，该通孔1910例如用于使得第一金属层191与补偿电压信号线电连接，即使得第一金属层191与一补偿电压端电连接。
在一些实施例中，补偿电压信号线提供的电压大小等于第一电源电压信号线VDD提供的第一电源电压信号。此时，参考图7A和图7G，第一电源电压信号线VDD也是补偿电压信号线，即第一电源电压信号线VDD复用为补偿电压信号线。
在另一些实施例中，补偿电压信号线提供的电压大小于第一电源电压信号线VDD提供的第一电源电压信号不同，则补偿电压信号线与第一电源电压信号线VDD为两条同层同材料的信号线。
在同一显示面板1中，补偿电压信号线提供的补偿电压信号为一固定值，例如等于电源电压信号的大小；在不同的显示面板1中，由于工艺的影响，不同的显示面板1中的薄膜晶体管的阈值电压偏离预设值的程度可能不同，从而不同显示面板1中的补偿电压端所提供的补偿电压信号的大小可能不同。
在一些实施例中，像素驱动电路中的薄膜晶体管例如均为P型晶体管，第一电源电压信号端VDD例如提供高电平的固定电压，从而使得薄膜晶体管 的工作更为稳定，以及通过薄膜晶体管中有源层与第一金属层191之间的相互作用，调节薄膜晶体管的阈值电压。
示例的，参考图7D，为像素驱动电路3中有源层193的结构图，有源层193的材料例如为多晶硅(P-si)。
示例的，参考图7E，为栅极金属层195的结构图，其中，驱动晶体管(第三晶体管T3)的栅极层也作为了电容C的第一极板C 1。
示例的，参考图7F，为第二金属层197的结构图，其中，在电容C的第二极板C 2上设置有通孔1910，该通孔1910用于使得电容C与第三金属层199实现电连接。
示例的，参考图7G，为第三金属层199的结构图，其中第一电源电压信号线VDD和连接电极1990上设置的通孔1910，用于实现各个薄膜晶体管与信号线(例如包括数据信号线Data、第一电源电压信号线VDD、发光控制信号线EM、栅线Gate、初始化信号线Vint等)之间的电连接。本领域技术人员可以理解的是，数据信号线Data和第一电源电压信号线VDD与薄膜晶体管重叠的部分作为了薄膜晶体管中的源极和漏极。
在一些实施例中，参考图7B和图7H，显示面板1还包括设置于衬底11上的阻挡层110，阻挡层110用于隔离衬底11与薄膜晶体管，避免衬底11中的物质影响薄膜晶体管中的有源层193。
基于上述，当在像素界定层13和第一电极12上形成第一发光功能层14后，显示面板1的整体结构例如参考图7H。
参考图8A～图8I，本公开的实施例还提供一种显示基板1′，包括：衬底11。
第一电极12，设置于衬底11的一侧。
像素界定层13，设置于衬底11的一侧，包括第一镂空部130，第一镂空部130包括相对设置的第一开口1301和第二开口1302；相比于第二开口1302，第一开口1301更靠近衬底11，其中第一开口1301露出第一电极12的至少部分。
对于衬底11、第一电极12和像素界定层13的解释，可以参照对显示面板1中的衬底11、第一电极12和像素界定层13的解释，因此不再赘述。
牺牲图案18，设置于像素界定层13远离衬底11的一侧，且牺牲图案18在像素界定层13上的正投影与第一开口1301不重叠。
在一些实施例中，牺牲图案18的材料例如为有机材料，又例如为含氟元素的有机材料。
在另一些实施例中，牺牲图案18的材料例如为金属材料，例如银(Ag)、铝(Al)、钼(Mo)和钛(Ti)等金属或合金。
选择的牺牲图案18的材料例如与剥离液相对应，不同材料对应不同的剥离液，选择的剥离液除了能溶解牺牲图案18外，不能与显示基板1′中的其它膜层发生反应。示例的，金属材料的牺牲图案18可以选择酸性或者碱性的剥离液，负性光刻胶材料的牺牲图案18例如可以选择氢氟醚类作为剥离液。
牺牲图案18在像素界定层13上的正投影与第一开口1301不重叠，包括：参考图8E和图8I，牺牲图案18在像素界定层13上的正投影与第一开口1301的一侧重合，以及参考图8A～图8D、图8F～图8H，牺牲图案18在像素界定层13上的正投影与第一开口1301之间存在间距。
牺牲图案18在像素界定层13上的正投影与第一开口1301不重叠，用于避免因牺牲图案18的遮挡，导致用于形成第二发光功能层24的材料(例如发光材料)无法完全覆盖位于第一开口1301中的至少部分第一电极12。
隔垫物17，设置于牺牲图案18远离衬底11的一侧，隔垫物17在像素界定层13上的正投影与第一开口1301不重叠。
第二发光功能层24，设置于像素界定层13和第一电极12远离衬底11的一侧。
上述隔垫物17的材料例如为有机材料，又例如为感光型的有机材料，例如光刻胶。在一些实施例中，隔垫物17的材料为负性的光刻胶。
在一些实施例中，隔垫物17包括沿衬底11厚度方向相对设置的第一表面和第二表面，相对于第二表面，第一表面更靠近衬底11；其中，第一表面在像素界定层13上的正投影落在第二表面在像素界定层13上的正投影以内，且第一表面在像素界定层13上的正投影的边界与第二表面在像素界定层13上的正投影的边界之间存在间隙。
在一些实施例中，第一表面在像素界定层13上的正投影的中心点和第二表面在像素界定层13上的正投影的中心点重合。
第一表面在像素界定层13上的正投影落在第二表面在像素界定层13上的正投影以内，则说明第一表面的面积小于第二表面的面积。第一表面例如为下表面(沿衬底11厚度方向靠近衬底11的一侧表面)，第二表面例如为上表面(沿衬底11厚度方向远离衬底11的一侧表面)。
参考图8A～图8I，隔垫物17的纵截面形状例如为倒梯形，该倒梯形的底边长度小于其顶边长度。当隔垫物17的纵截面形状为倒梯形时，隔垫物17的三维立体结构例如为棱台，该棱台的上表面和下表面(与上表面相对)例 如均为矩形，且上表面矩形的面积大于下表面矩形的面积；或者隔垫物17的三维立体结构还可以为圆台，圆台的上表面和下表面可以均为圆形，也可以均为椭圆形，且上表面的面积大于下表面的面积。当隔垫物17的材料为负性的光刻胶时，可以通过构图工艺(例如包括曝光、显影和刻蚀)形成纵截面为倒梯形的隔垫物17。
在另一些实施例中，隔垫物17的纵截面形状还可以为“T”型。当隔垫物17的材料为两层材质不同的金属时，根据同一种剥离液对不同金属的刻蚀速率不同的原理，可以形成T型的隔垫物17。
示例的，隔垫物17的高度例如为0.5μm～3μm。
在隔垫物17的纵截面形状为倒梯形和T型时，可以使得后续蒸镀在像素界定层13和第一电极12上的第二发光功能层24在隔垫物17的侧壁和牺牲图案18的侧壁上断开，即，使得第二发光功能层24无法完全覆盖隔垫物17的侧壁和牺牲图案18的侧壁。示例的，参考图8A，第二发光功能层24覆盖了牺牲图案18的部分侧壁，剩余部分的牺牲图案18的侧壁暴露，第二发光功能层24还覆盖了隔垫物17的上表面，隔垫物17的侧壁暴露。又示例的，参考图8B，第二发光功能层24覆盖了隔垫物17的部分上表面，牺牲图案18的侧壁和隔垫物17的侧壁暴露。牺牲图案18的侧壁暴露可以便于剥离液进入牺牲图案18中，快速溶解牺牲图案18，隔垫物17的侧壁暴露可以便于后续移除隔垫物17。
需要说明的是，即使隔垫物17的纵截面形状不为倒梯形和T型，第二发光功能层24覆盖了隔垫物17和牺牲图案18的侧壁，剥离液也可以透过第二发光功能层24进入牺牲图案18中，从而溶解牺牲图案；而当牺牲图案18被溶解后，由于第二发光功能层24的厚度较小，膜层中的应力不足以阻拦隔垫物17，隔垫物17仍然可以从显示基板1′中脱落下来。
隔垫物17在像素界定层13上的正投影与第一开口1301不重叠，包括：参考图8D和图8E，隔垫物17在像素界定层13上的正投影靠近第一开口1301的一侧与第一开口1301的边缘重合，以及参考图8A～图8C，图8F～图8I，隔垫物17在像素界定层13上的正投影与第一开口1301之间存在间距。
隔垫物17在像素界定层13上的正投影与第一开口1301不重叠，可以保证在后续在蒸镀第二发光功能层24时，第二发光功能层24能完全覆盖位于第一开口1301中的至少部分第一电极12，从而保证第二发光功能层24与第一电极12之间的接触面积较大。
隔垫物17位于牺牲图案18上，其中隔垫物17的第一表面(下表面)与 牺牲图案18的上表面接触，而隔垫物17的第一表面的长度小于等于牺牲图案18的长度，隔垫物17的第一表面的宽度小于等于牺牲图案18的宽度，从而用于保证在牺牲图案18被去除后，隔垫物17可以脱离显示基板1′。
示例的，参考图8A、图8C、图8D、图8E、图8H和图8I，第二发光功能层24覆盖像素界定层13、第一电极12和隔垫物17，其中，第二发光功能层24完全覆盖隔垫物17远离衬底11的一侧表面(第二表面)。
又示例的，参考图8B和图8G，第二发光功能层24覆盖像素界定层13、第一电极12和隔垫物17，其中，第二发光功能层24覆盖隔垫物17远离衬底11的一侧表面(第二表面)的部分。
参考图8F，第二发光功能层24覆盖像素界定层13和第一电极12，第二发光功能层24未覆盖隔垫物17远离衬底11的一侧表面(第二表面)。
上述第二发光功能层24是否覆盖隔垫物17的第二表面，即隔垫物17的第二表面是否存在用于形成第二发光功能层24的材料，和蒸镀第二发光功能层24时所使用的FMM中与每个亚像素对应的蒸镀开口所产生的阴影(Shadow)有关。当蒸镀开口所产生的Shadow延伸至隔垫物17的第二表面时，则隔垫物17的第二表面上将存在用于形成第二发光功能层24的材料，当蒸镀开口所产生的Shadow未延伸至隔垫物17的第二表面时，则隔垫物17的第二表面将没有用于形成第二发光功能层24的材料。
对于第二发光功能层24的材料和内部层别结构(即第二发光功能层24所包括的层别，例如发光层)的介绍可以参考对第一发光功能层14的介绍。在去除牺牲图案18和隔垫物17后，第二发光功能层24便成为了第一发光功能层14。在去除牺牲图案18和隔垫物17后，第二发光功能层24的结构可能发生了变化，也可能未发生变化。示例的，参考图8A，第二发光功能层24覆盖了隔垫物17的第二表面，在去除牺牲图案18和隔垫物17后，隔垫物17第二表面的部分第二发光功能层24也被移除，从而使得第二发光功能层24的结构发生了变化。又示例的，参考图8F，第二发光功能层24未覆盖隔垫物17的第二表面，在去除牺牲图案18和隔垫物17后，第二发光功能层24的结构并未发生改变。因此，在本公开的实施例中，无论去除牺牲图案18和隔垫物17后，第二发光功能层24的结构是否改变，均将未去除牺牲图案18和隔垫物17之间的发光功能层称为第二发光功能层24，将去除牺牲图案18和隔垫物17之后的发光功能层称为第一发光功能层14。
在本公开的显示基板1′中设置有牺牲图案18和隔垫物17，其中，隔垫物17用于支撑蒸镀第二发光功能层24时所使用的FMM，在形成第二发光功能 层24后，通过去除牺牲图案18，以使得隔垫物17脱离显示基板1′。对于去除牺牲图案18和隔垫物17的方式可参照前文在显示面板1中对去除牺牲图案18和隔垫物17的解释。去除牺牲图案18和隔垫物17后的显示基板1′的结构与上述的显示面板1的结构相同，从而对于去除牺牲图案18和隔垫物17后显示基板1′所具有的优点，请参照前文在显示面板1中的描述，在此不再赘述。
在一些实施例中，参考图8A～图8I，隔垫物17中的第二表面的最大尺寸小于第一镂空部130的最大尺寸。第一镂空部130的最大尺寸可能是第一开口1301的最大尺寸，也可能是第二开口1302的最大尺寸。示例的，第二开口1302的最大尺寸大于第一开口1301的最大尺寸，则隔垫物17中的第二表面的最大尺寸小于第一镂空部130的最大尺寸，即隔垫物17中第二表面的最大尺寸小于第二开口1302的最大尺寸。隔垫物17中第二表面的最大尺寸为隔垫物17的第二表面边界上任意两点之间的最大距离，第二开口1302的最大尺寸为第二开口1302边界上任意两点之间的最大距离。又示例的，隔垫物17的第二表面和第二开口1302均为矩形，则隔垫物17的第二表面的最大尺寸为其对角线的长度，第二开口1302的最大尺寸为其对角线的长度。
在另一些实施例中，隔垫物17的第二表面例如为矩形，而第二开口1302例如为六边形。
由于第一镂空部130的尺寸为亚像素级别的，而隔垫物17的第二表面的最大尺寸小于第一镂空部130的最大尺寸，此时隔垫物17的尺寸也为亚像素级别的，从而隔垫物17的尺寸可以做的较小，便于后续通过去除牺牲图案18去除隔垫物17。
在一些实施例中，参考图8A～图8C、图8F和图8G、隔垫物17在像素界定层13上的正投影与第二开口1302之间具有间隙。当隔垫物17在像素界定层13上的正投影与第二开口1302之间具有间隙时，第二发光功能层24可以覆盖该间隙，从而可以保证第二发光功能层24能够完全覆盖第一开口1301所露出的至少部分第一电极12。第二发光功能层24与第一电极12的接触面积越大，发光二极管的发光面积则越大。
在一些实施例中，参考图8G～图8I，在第一开口1301和第二开口1302均为矩形的情况下，第一开口1301的长度小于第二开口1302的长度。第一开口1301的长度小于第二开口1302的长度，可以使得第一镂空部130的侧壁为斜面，进而使得像素界定层13形成一个钝角α，α越大，第二发光功能层24越不容易在α处产生裂痕，膜层质量越好。
在一些实施例中，参考图8A～图8I，牺牲图案18的厚度大于第二发光功能层24的厚度。示例的，牺牲图案18的厚度例如为0.1μm～2μm。
牺牲图案18的厚度大于第二发光功能层24的厚度时，牺牲图案18的侧壁(沿其厚度方向)未被第二发光功能层24覆盖的部分越多，从而有利于增大牺牲图案18与剥离液接触的面积，进而减小去除牺牲图案18所需的时间。
在一些实施例中，参考图9A和图9B，显示基板1′还包括：薄膜晶体管，设置于衬底11与第一电极12之间，且薄膜晶体管的源极或漏极与第一电极12电连接。
显示基板1′所包括薄膜晶体管的结构与显示面板1所包括薄膜晶体管的结构相同，因此可以参照前文对显示面板1中的薄膜晶体管的解释。
参考图9A和图9C，牺牲图案18和隔垫物17的俯视图例如均为矩形，第一镂空部130的俯视图例如为六边形。
在另一些实施例中，参考图9B，显示基板1′还包括：基板10，设置于衬底11远离薄膜晶体管的一侧。基板10例如为玻璃基板，在显示基板1′的制备过程中，衬底11形成于基板10上。
在此基础上，当在像素界定层13和第一电极12上形成第二发光功能层24后，显示基板1′的整体结构例如参考图9D。
显示基板1′具有与显示面板1相同的有益效果，因此不再赘述。
参考图10A，本公开的实施例还提供一种显示基板1′的制备方法，包括：
S1、参考图10B，在衬底11上形成第一电极12。
第一电极12的材料例如为ITO。首先，在衬底11上形成ITO薄膜，然后再通过构图工艺中的涂胶、曝光、显影和刻蚀等工艺，将ITO薄膜制作为多个第一电极12。
S2、参考图10C，在形成有第一电极12的衬底11上形成像素界定层13；像素界定层13包括：第一镂空部130，第一镂空部130包括相对设置的第一开口1301和第二开口1302，相比于第二开口1302，第一开口1301更靠近衬底11，其中第一开口1301露出第一电极12的至少部分。
在第一电极12上形成有机薄膜，通过构图工艺，形成第一镂空部130，从而形成像素界定层13。有机薄膜的材料例如聚酰亚胺。
S3、参考图10D～图10F，在像素界定层13上形成层叠的牺牲图案18和隔垫物17，相对于隔垫物17，牺牲图案18更靠近衬底11。
示例的，参考图10D，牺牲图案18和隔垫物17均为多个，且牺牲图案18和隔垫物17的尺寸均较小，例如牺牲图案18和隔垫物17的最大尺寸均小 于第一镂空部130的最大尺寸。在该种结构中，由于隔垫物17的尺寸较小，从而更易脱离显示基板1′。
又示例的，参考图10E，牺牲图案18和隔垫物17均为多个，且牺牲图案18和隔垫物17的尺寸均较大，例如牺牲图案18和隔垫物17的最大尺寸均大于第一镂空部130的最大尺寸。在该种结构中，便于通过工图工艺，制作牺牲图案18和隔垫物17。
再示例的，参考图10F，牺牲图案18和隔垫物17均为一个，且牺牲图案18和隔垫物17的尺寸均较大，例如牺牲图案18和隔垫物17的最大尺寸均大于第一镂空部130的最大尺寸。在该种结构中，隔垫物17对于FMM的支撑稳定性较好。
S4、参考图10G和图10H，将形成有隔垫物17的衬底11与掩膜板2相对设置，隔垫物17与掩膜板2抵接，透过掩膜板2向衬底11设置有隔垫物17的一侧蒸镀发光功能材料，以形成第二发光功能层24。
将形成有隔垫物17的衬底11与掩膜板2相对设置，隔垫物17与掩膜板2抵接，即将掩膜板2放置在隔垫物17远离衬底11的一侧上，隔垫物17起支撑掩膜板2的作用，该掩膜板2例如为FMM，在该掩膜板2上设置有多个与第一镂空部130一一对应的蒸镀开口20，发光功能材料通过蒸镀开口20蒸镀在第一电极12和像素界定层13上，从而形成第二发光功能层24。其中，发光功能材料包括用于形成第二发光功能层24中各个膜层的所有材料，例如包括形成发光层的有机电致发光材料和形成电子传输层的材料，其中，电子传输层的材料例如包括铯、锂和一氧化硅等材料。
参考图10D～图10F，由于牺牲图案18和隔垫物17的结构不同，会影响去除牺牲图案18和隔垫物17后所形成的第二镂空部140的结构。示例的，在图10E所示的显示基板1′的结构中，牺牲图案18的长度小于显示基板1′的宽度，在去除牺牲图案18后，第二镂空部140的结构与牺牲图案18的结构相同或大致相同，因此，通过第二发光功能层24所形成的第一发光功能层14整体是相连，第二镂空部140间隔设置在第一发光功能层14上。又示例的，参考图10E，当牺牲图案18的长度等于显示基板1′的长度时，在去除牺牲图案18后，通过第二发光功能层24所形成的第一发光功能层14被分割为多个未相连的发光功能图案，但是相邻的发光功能图案之间的间隙仍然可以理解为本公开中的第二镂空部140。
上述显示基板1′的制备方法，与上述的显示基板1′具有相同的有益效果，因此不再赘述。
在另一些实施例中，在像素界定层13上形成层叠的牺牲图案18和隔垫物17，包括：
S300、在形成有像素界定层13的衬底11上形成第一薄膜，并将第一薄膜图案化，以形成位于像素界定层13远离衬底11一侧的牺牲图案18。
示例的，在第一薄膜的材料为含氟元素的有机材料时，在低温90℃的环境下形成第一薄膜，其中低温有利于保护有机材料的特性，从而形成的第一薄膜的膜层质量较好。
S301、在形成有牺牲图案18的衬底11上形成第二薄膜，并将第二薄膜图案化，以形成位于牺牲图案18远离衬底11一侧的隔垫物17。
上述显示基板1′制备过程中牺牲图案18和隔垫物17图案化的难度较低。
在另一些实施例中，在像素界定层13上形成层叠的牺牲图案18和隔垫物17，包括：
S300′、在形成有像素界定层13的衬底11上形成第一薄膜。
S301′、在第一薄膜上形成第二薄膜。
S302′、同时将第一薄膜和第二薄膜图案化，以形成层叠的牺牲图案18和隔垫物17。
上述显示基板1′制备过程中牺牲图案18和隔垫物17图案化的过程较为简单。
参考图11A，本公开的实施例还提供一种显示面板1的制备方法，包括：
S10、在衬底11上形成第一电极12。
形成第一电极12的过程请参照在上述显示基板1′中形成第一电极12的过程。
S20、在形成有第一电极12的衬底11上形成像素界定层13；像素界定层13包括：第一镂空部130，第一镂空部130包括相对设置的第一开口1301和第二开口1302，相比于第二开口1302，第一开口1301更靠近衬底11，其中第一开口1301露出第一电极12的至少部分。
形成像素界定层13的过程请参照在上述显示基板1′中形成像素界定层13的过程。
S30、在像素界定层13上形成层叠的牺牲图案18和隔垫物17，相对于隔垫物17，牺牲图案18更靠近衬底11。
形成牺牲图案18和隔垫物17的过程请参照在上述显示基板1′中形成牺牲图案18和隔垫物17的过程。
S40、将形成有隔垫物17的衬底11与掩膜板2相对设置，隔垫物17与 掩膜板2抵接，透过掩膜板2向衬底11设置有隔垫物17的一侧蒸镀发光功能材料，以形成第二发光功能层24。
形成第二发光功能层24的过程请参照在上述显示基板1′中形成第二发光功能层24的过程。
S50、参考图11B，去除牺牲图案18，以使得位于牺牲图案18远离衬底11一侧的隔垫物17脱离显示面板1，以通过第二发光功能层24形成第一发光功能层14。
示例的，通过剥离液溶解牺牲图案18，从而使得隔垫物17自行掉落，以实现去除隔垫物17的目的。
上述显示面板1的制备过程具有与上述的显示基板1′相同的有益效果，因此不再赘述。
在一些实施例中，结合图4A和图11A，显示面板1的制备方法还包括：
S51、在形成有第一发光功能层14的衬底11上形成第二电极15。
在一些实施例中，结合图4B和图11A，显示面板1的制备方法还包括：
S52、在第二电极15上形成封装层111。
参考图4B，形成封装层111例如包括：
S520、在第二电极15上形成第一无机封装子层1111。
S521、在第一无机封装子层1111上形成有机封装子层1113。
S522、在有机封装子层1113上形成第二无机封装子层1112。
其实，对第一无机封装子层1111、有机封装层111和第二无机封装子层1112的介绍可以参照上述对显示面板1中第一无机封装子层1111、有机封装层111和第二无机封装子层1112的介绍，因此不再赘述。
在一些实施例中，参考图7B，在形成第一电极12之前，显示面板1的制备方法还包括：
在基板10上形成衬底11，衬底11的材料例如为聚酰亚胺。
在此基础上，在一些实施例中，参考图7B，在形成衬底11之后，形成第一电极12之前，显示面板1的制备方法还包括：在衬底上形成薄膜晶体管。
示例的，例如在衬底11的一侧至少形成有源层薄膜、第一栅绝缘层194、栅极金属薄膜、第二栅绝缘层196和第三金属薄膜，并通过构图工艺形成有源层193、栅极层、源极和漏极，以构成薄膜晶体管。
在本公开中，相同的附图标记即可以理解为信号端，还可以理解为信号线和信号，例如Data既可以理解为数据信号端，也可以理解为数据信号线和数据信号。
本领域技术人员可以理解的是，一个第一电极与显示基板中的一个亚像素对，本公开实施例中提供的附图仅为示意，其中所体现的第一电极的数量仅为示意，并不因此而限定本公开中第一电极的数量，同样的，附图中所体现的多个隔垫物和多个牺牲图案的数量，也并不因此而被限定。
本领域技术人可以理解的是，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，同一构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示面板，包括：
    衬底；
    第一电极，设置于所述衬底的一侧；
    像素界定层，设置于所述衬底的一侧，包括第一镂空部，所述第一镂空部包括相对设置的第一开口和第二开口；相比于所述第二开口，所述第一开口更靠近所述衬底，其中所述第一开口露出所述第一电极的至少部分；
    第一发光功能层，设置于所述像素界定层和所述第一电极远离所述衬底的一侧，包括第二镂空部，所述第二镂空部在所述像素界定层上的正投影与所述第一开口不重叠。
  2. 根据权利要求1所述的显示面板，其中，所述第二镂空部在所述像素界定层上的正投影与所述第二开口之间具有间隙。
  3. 根据权利要求1或2所述的显示面板，其中，所述第二镂空部的最大尺寸小于所述第一镂空部的最大尺寸。
  4. 根据权利要求1～3任一项所述的显示面板，还包括：第二电极，设置于所述第一发光功能层远离所述衬底的一侧，且所述第二电极覆盖所述第二镂空部。
  5. 根据权利要求1～4任一项所述的显示面板，还包括：薄膜晶体管，设置于所述衬底与所述第一电极之间，且所述薄膜晶体管的源极或漏极与所述第一电极电连接。
  6. 根据权利要求5所述的显示面板，所述薄膜晶体管还包括：沿远离衬底一侧方向层叠的有源层、第一栅绝缘层、栅极层、第二栅绝缘层、层间绝缘层；所述薄膜晶体管的源极和漏极设置于所述层间绝缘层远离所述衬底的一侧，且通过贯穿所述层间绝缘层、第二栅绝缘层和第一栅绝缘层的过孔与所述有源层接触。
  7. 根据权利要求5所述的显示面板，还包括：第一金属层，所述第一金属层设置于所述薄膜晶体管与所述衬底之间，且所述第一金属层与一补偿电压端电连接，所述补偿电压端被配置为提供用于补偿所述薄膜晶体管的阈值电压的补偿电压信号。
  8. 根据权利要求1～7任一项所述的显示面板，还包括：封装层，所述封装层包括沿远离衬底一侧方向层叠的第一无机封装子层、有机封装子层和第二无机封装子层。
  9. 一种显示基板，包括：
    衬底；
    第一电极，设置于所述衬底的一侧；
    像素界定层，设置于所述衬底的一侧，包括第一镂空部，所述第一镂空部包括相对设置的第一开口和第二开口；相比于所述第二开口，所述第一开口更靠近所述衬底，其中所述第一开口露出所述第一电极的至少部分；
    牺牲图案，设置于像素界定层远离所述衬底的一侧，且所述牺牲图案在所述像素界定层上的正投影与所述第一开口不重叠；
    隔垫物，设置于所述牺牲图案远离所述衬底的一侧，所述隔垫物在所述像素界定层上的正投影与所述第一开口不重叠；
    第二发光功能层，设置于所述像素界定层和所述第一电极远离所述衬底的一侧。
  10. 根据权利要求9所述的显示基板，其中，所述隔垫物包括沿远离衬底一侧方向相对设置的第一表面和第二表面，相对于所述第二表面，所述第一表面更靠近所述衬底；其中，所述第一表面在所述像素界定层上的正投影落在所述第二表面在所述像素界定层上的正投影以内，且所述第一表面在所述像素界定层上的正投影的边界与所述第二表面在所述像素界定层上的正投影的边界之间存在间隙。
  11. 根据权利要求10所述的显示基板，其中，所述第二表面的最大尺寸小于所述第一镂空部的最大尺寸。
  12. 根据权利要求9～11任一项所述的显示基板，其中，所述隔垫物在所述像素界定层上的正投影与所述第二开口之间具有间隙。
  13. 根据权利要求9～12任一项所述的显示基板，其中，所述牺牲图案的厚度大于所述第二发光功能层的厚度。
  14. 根据权利要求9～13任一项所述的显示基板，还包括：薄膜晶体管，设置于所述衬底与所述第一电极之间，且所述薄膜晶体管的源极或漏极与所述第一电极电连接。
  15. 一种显示装置，包括如权利要求1～8任一项所述的显示面板。
  16. 一种显示基板的制备方法，包括：
    在衬底上形成第一电极；
    在形成有第一电极的衬底上形成像素界定层；所述像素界定层包括：第一镂空部，所述第一镂空部包括相对设置的第一开口和第二开口，相比于所述第二开口，所述第一开口更靠近所述衬底，其中所述第一开口露出所述第一电极的至少部分；
    在所述像素界定层上形成层叠的牺牲图案和隔垫物，相对于所述隔垫物，所述牺牲图案更靠近所述衬底；
    将形成有所述隔垫物的衬底与掩膜板相对设置，所述隔垫物与所述掩膜板抵接，透过所述掩膜板向所述衬底设置有所述隔垫物的一侧蒸镀发光功能材料，以形成第二发光功能层。
  17. 根据权利要求16所述的显示基板的制备方法，其中，在所述像素界定层上形成层叠的牺牲图案和隔垫物，包括：
    在形成有所述像素界定层的衬底上形成第一薄膜，并将第一薄膜图案化，以形成位于所述像素界定层远离衬底一侧的牺牲图案；
    在形成有牺牲图案的衬底上形成第二薄膜，并将第二薄膜图案化，以形成位于所述牺牲图案远离所述衬底一侧的隔垫物；
    或者，
    在形成有所述像素界定层的衬底上形成第一薄膜；
    在第一薄膜上形成第二薄膜；
    同时将第一薄膜和第二薄膜图案化，以形成层叠的牺牲图案和隔垫物。
  18. 一种显示面板的制备方法，包括：
    如权利要求16或17所述的显示基板的制备方法；
    去除所述显示基板中的牺牲图案，以使得所述显示基板中位于所述牺牲图案远离衬底一侧的隔垫物脱离所述显示基板，以通过第二发光功能层形成第一发光功能层。
  19. 根据权利要求18所述的显示面板的制备方法，还包括：
    在形成有第一发光功能层的衬底上形成第二电极；
    在所述第二电极上形成第一无机封装子层；
    在所述第一无机封装子层上形成有机封装子层；
    在所述有机封装子层上形成第二无机封装子层，所述第一无机封装子层、所述有机封装子层和所述第二无机封装子层构成封装层。
PCT/CN2021/093582 2020-06-04 2021-05-13 显示面板及其制备方法、显示基板及其制备方法和显示装置 WO2021244248A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/777,652 US20230006009A1 (en) 2020-06-04 2021-05-13 Display panel and manufacturing method therefor, display substrate and manufacturing method therefor, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010501773.3A CN111628105B (zh) 2020-06-04 2020-06-04 显示面板及其制备方法、显示基板及其制备方法和显示装置
CN202010501773.3 2020-06-04

Publications (1)

Publication Number Publication Date
WO2021244248A1 true WO2021244248A1 (zh) 2021-12-09

Family

ID=72272717

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/093582 WO2021244248A1 (zh) 2020-06-04 2021-05-13 显示面板及其制备方法、显示基板及其制备方法和显示装置

Country Status (3)

Country Link
US (1) US20230006009A1 (zh)
CN (1) CN111628105B (zh)
WO (1) WO2021244248A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4277450A1 (en) * 2022-05-09 2023-11-15 Samsung Display Co., Ltd. Display device and method for manufacturing the same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111628105B (zh) * 2020-06-04 2023-05-26 京东方科技集团股份有限公司 显示面板及其制备方法、显示基板及其制备方法和显示装置
CN114730796A (zh) * 2020-09-29 2022-07-08 京东方科技集团股份有限公司 显示面板及显示装置
WO2022193316A1 (zh) * 2021-03-19 2022-09-22 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115413369A (zh) * 2021-03-26 2022-11-29 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN117133190A (zh) * 2023-01-18 2023-11-28 荣耀终端有限公司 折叠屏和可折叠电子设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101626029A (zh) * 2008-07-11 2010-01-13 三星移动显示器株式会社 有机发光二极管显示器及其制造方法
CN103219354A (zh) * 2012-01-19 2013-07-24 三星显示有限公司 有机发光二极管显示器及其制造方法
US20140084257A1 (en) * 2012-09-21 2014-03-27 Samsung Display Co., Ltd. Organic light emitting display panel and method of manufacturing the same
CN206250196U (zh) * 2016-11-09 2017-06-13 昆山国显光电有限公司 Oled触控显示面板及触控显示装置
CN107240599A (zh) * 2017-06-23 2017-10-10 京东方科技集团股份有限公司 显示装置、oled显示面板及其制造方法
CN110112175A (zh) * 2018-02-01 2019-08-09 三星显示有限公司 显示设备及其制造方法
CN111628105A (zh) * 2020-06-04 2020-09-04 京东方科技集团股份有限公司 显示面板及其制备方法、显示基板及其制备方法和显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321175B (zh) * 2018-01-31 2021-02-12 京东方科技集团股份有限公司 基板及其制造方法、显示装置
CN110707095A (zh) * 2019-09-04 2020-01-17 深圳市华星光电半导体显示技术有限公司 显示面板
CN110706655B (zh) * 2019-10-21 2021-03-30 京东方科技集团股份有限公司 可拉伸显示面板、晶体管的阈值电压的补偿方法及计算机可读存储介质
CN110911466B (zh) * 2019-11-29 2022-08-19 京东方科技集团股份有限公司 一种基板及其制备方法、母板的制备方法、掩膜版和蒸镀装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101626029A (zh) * 2008-07-11 2010-01-13 三星移动显示器株式会社 有机发光二极管显示器及其制造方法
CN103219354A (zh) * 2012-01-19 2013-07-24 三星显示有限公司 有机发光二极管显示器及其制造方法
US20140084257A1 (en) * 2012-09-21 2014-03-27 Samsung Display Co., Ltd. Organic light emitting display panel and method of manufacturing the same
CN206250196U (zh) * 2016-11-09 2017-06-13 昆山国显光电有限公司 Oled触控显示面板及触控显示装置
CN107240599A (zh) * 2017-06-23 2017-10-10 京东方科技集团股份有限公司 显示装置、oled显示面板及其制造方法
CN110112175A (zh) * 2018-02-01 2019-08-09 三星显示有限公司 显示设备及其制造方法
CN111628105A (zh) * 2020-06-04 2020-09-04 京东方科技集团股份有限公司 显示面板及其制备方法、显示基板及其制备方法和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4277450A1 (en) * 2022-05-09 2023-11-15 Samsung Display Co., Ltd. Display device and method for manufacturing the same

Also Published As

Publication number Publication date
US20230006009A1 (en) 2023-01-05
CN111628105B (zh) 2023-05-26
CN111628105A (zh) 2020-09-04

Similar Documents

Publication Publication Date Title
WO2021244248A1 (zh) 显示面板及其制备方法、显示基板及其制备方法和显示装置
WO2020207124A1 (zh) 显示基板及其制造方法、显示装置
JP4879478B2 (ja) 平板表示装置
WO2016074554A1 (zh) 一种像素单元及其制备方法、发光器件、显示装置
CN107689390B (zh) 像素界定层及其制造方法、显示基板、显示面板
KR100643404B1 (ko) 디스플레이장치 및 그 제조방법
JP2007280963A (ja) フルカラー有機電界発光表示素子
US20190044077A1 (en) Substrate for an organic light-emitting device, manufacturing method thereof and display device
WO2021012312A1 (zh) Oled显示面板
WO2020164528A1 (zh) 显示基板及其制备方法、显示装置
WO2020154875A1 (zh) 像素单元及其制造方法和双面oled显示装置
WO2021238645A1 (zh) 显示用基板及其制备方法、显示装置
TW201349615A (zh) 發光元件及電晶體
JP2008091071A (ja) 電気光学装置、およびその製造方法
US20210134905A1 (en) Display substrate and method of manufacturing the same, and display panel
CN109599430B (zh) Oled基板及其制备方法、oled显示装置
WO2021164132A1 (zh) 有机发光二极管显示器及其制造方法
KR20090021442A (ko) 유기전계발광표시장치 및 그 제조방법
JP2008066054A (ja) 電気光学装置およびその製造方法
KR100768715B1 (ko) 유기 전계 발광 소자 및 그 제조방법
JP2015143375A (ja) メタルマスクおよびその製造方法、ならびに表示装置の製造方法
WO2019242384A1 (zh) 显示面板背板结构、其制备方法及顶发射型显示面板
KR102593461B1 (ko) 유기 발광 표시 장치
JP2008004378A (ja) デバイス、薄膜形成方法及びデバイスの製造方法並びに電子機器
KR100731536B1 (ko) 유기 전계 발광 소자의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21816983

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21816983

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 30.06.23)