WO2021223080A9 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021223080A9
WO2021223080A9 PCT/CN2020/088673 CN2020088673W WO2021223080A9 WO 2021223080 A9 WO2021223080 A9 WO 2021223080A9 CN 2020088673 W CN2020088673 W CN 2020088673W WO 2021223080 A9 WO2021223080 A9 WO 2021223080A9
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WO
WIPO (PCT)
Prior art keywords
dummy
line
sub
circuits
test
Prior art date
Application number
PCT/CN2020/088673
Other languages
English (en)
French (fr)
Other versions
WO2021223080A1 (zh
Inventor
姜晓峰
韩林宏
杨慧娟
张猛
代洁
张鑫
李慧君
王予
杨路路
白露
王思雨
和玉鹏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/416,558 priority Critical patent/US11751464B2/en
Priority to EP20900755.8A priority patent/EP4148786A4/en
Priority to CN202080000679.8A priority patent/CN113939912B/zh
Priority to PCT/CN2020/088673 priority patent/WO2021223080A1/zh
Publication of WO2021223080A1 publication Critical patent/WO2021223080A1/zh
Publication of WO2021223080A9 publication Critical patent/WO2021223080A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • the present application relates to the field of display technology, and in particular, to a display substrate and a display device.
  • tiny cracks that are difficult to observe may appear on the edge of the display substrate, which affects the quality of the display substrate.
  • the present application provides a display substrate and a display device, and the technical solutions are as follows:
  • a display substrate comprising:
  • a base substrate having a display area and a peripheral area surrounding the display area
  • a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels
  • a plurality of data transmission lines located in the peripheral area and electrically connected with the plurality of data lines;
  • a plurality of electrostatic discharge circuits located in the peripheral area and electrically connected to the plurality of data transmission lines, the plurality of electrostatic discharge circuits are arranged along the extension direction of the boundary of the display area;
  • a panel crack detection trace located in the peripheral area and surrounding the display area
  • At least one electrostatic discharge dummy circuit in the plurality of electrostatic discharge dummy circuits is electrically connected to the panel crack detection trace for discharging static electricity on the panel crack detection trace.
  • the boundary of the display area includes a first boundary, a second boundary, a third boundary and a fourth boundary connected in sequence, and the plurality of electrostatic discharge circuits and the plurality of electrostatic discharge dummy circuits are located close to the the peripheral region of the first boundary;
  • the plurality of electrostatic discharge dummy circuits include a plurality of first electrostatic discharge dummy sub-circuits and a plurality of second electrostatic discharge dummy sub-circuits;
  • the plurality of first electrostatic discharge dummy sub-circuits and the plurality of second electrostatic discharge dummy sub-circuits are located on two sides of the plurality of electrostatic discharge circuits, respectively.
  • the panel crack detection wiring includes: a first wiring segment, a second wiring segment and a third wiring segment;
  • the first line segment is a discontinuous line, located in the peripheral area close to the first boundary of the display area, and the first line segment extends along the extension direction of the first boundary;
  • the second line segment is a continuous line and is located near the first boundary, the second boundary and the peripheral region of the third boundary, and two end points of the second line segment are located close to the first boundary, the second boundary and the third boundary. the peripheral region of the first boundary;
  • the third line segment is a continuous line, located close to the third boundary, the fourth boundary and the peripheral area of the first boundary, and two end points of the third line segment are located close to the the peripheral area of the first boundary, the second routing segment and the third routing segment are respectively connected to the first routing segment;
  • the plurality of electrostatic discharge dummy circuits are electrically connected to the first wiring segment.
  • the first line segment includes: a first sub-line extending along the extending direction of the first boundary, a second sub-line and a third sub-line, the first sub-line and all the second sub-routing is located on a side of the third sub-routing close to the display area;
  • the first sub-line and the third sub-line are respectively connected to two end points of the second line segment, and the second sub-line and the third sub-line are respectively connected to the third sub-line.
  • the two endpoints of the line segment are connected;
  • the plurality of electrostatic discharge dummy circuits are electrically connected to the third sub-wires.
  • the display substrate further includes: a plurality of data transmission dummy lines, and the plurality of electrostatic discharge dummy circuits are electrically connected to the third sub-wires through the plurality of data transmission dummy lines.
  • the display substrate further includes: a plurality of first test circuits, located on a side of the plurality of electrostatic discharge circuits away from the display area, and the plurality of first test circuits are along the first boundary The extension direction of the extension is arranged;
  • At least one of the plurality of first test circuits includes: a first thin film transistor, a first control line, a first test data line and a second test data line, the first control line, the the first test data line and the second test data line are located in the peripheral region and extend along the extending direction of the first boundary;
  • the first thin film transistor includes: a first source electrode, a first drain electrode and a first gate electrode, the first gate electrode is electrically connected to the first control line, and the first source electrode is connected to the first A test data line, a second test data line, the first sub-line and one of the second sub-lines are electrically connected, and the first drain is electrically connected to one of the plurality of data transmission lines .
  • the display substrate further includes: a plurality of first test dummy circuits, the plurality of first test dummy circuits are located in the extension direction of the plurality of first test circuits along the extending direction of the first boundary. two sides and between the plurality of electrostatic discharge dummy circuits and the third sub-wires, the plurality of first test dummy circuits pass through the plurality of data transmission dummy wires and the third sub-wires and The electrostatic discharge dummy circuit is electrically connected.
  • At least one of the plurality of first test dummy circuits includes: a first dummy thin film transistor and a second control line, the second control line is located in the peripheral region and along the The extension direction of the first boundary extends, and the first dummy thin film transistor includes: a first dummy source electrode, a first dummy drain electrode and a first dummy gate electrode;
  • the first dummy gate is electrically connected to the second control line, and the first dummy drain is electrically connected to one of the plurality of data transmission dummy lines.
  • the number of the electrostatic discharge dummy circuits is the same as the number of the first test dummy circuits, and each of the electrostatic discharge dummy circuits is electrically connected to the third sub-wire through one of the first test dummy circuits. connect.
  • the display substrate further includes: a plurality of second test circuits, the plurality of second test circuits are located between the plurality of electrostatic discharge circuits and the plurality of first test circuits, and the plurality of second test circuits are located between the plurality of electrostatic discharge circuits and the plurality of first test circuits.
  • a plurality of second test circuits are electrically connected to the plurality of electrostatic discharge circuits and the plurality of first test circuits through the plurality of data transmission lines.
  • At least one of the plurality of second test circuits includes: a first sub-circuit, a second sub-circuit and a third sub-circuit, the second sub-circuit is located in the first sub-circuit Between the sub-circuit and the third sub-circuit, the first sub-circuit is located on a side of the second sub-circuit away from the plurality of sub-pixels.
  • the plurality of data transmission lines include: a plurality of first data transmission lines and a plurality of second data transmission lines, and the plurality of first data transmission lines and the plurality of second data transmission lines are alternately arranged one by one;
  • the first sub-circuit includes: a second thin film transistor, a third control line, and a third test data line, the third control line and the third test data line extending along the extending direction of the first boundary;
  • the second thin film transistor includes: a second source electrode, a second drain electrode and a second gate electrode, the second source electrode is electrically connected to the third test data line, the second drain electrode is connected to the multiple One of the first data transmission lines is electrically connected, and the second gate is electrically connected to the third control line.
  • the second sub-circuit includes: a third thin film transistor, a fourth thin film transistor, a fourth control line, a fourth test data line, and a fifth test data line, the third control line, the first four test data lines, and the fifth test data line extends along the extending direction of the first boundary;
  • the third thin film transistor includes: a third source electrode, a third drain electrode and a third gate electrode, the third source electrode is electrically connected to the fourth test data line, and the third drain electrode is connected to the multiple one of the second data transmission lines is electrically connected, the third gate is electrically connected to the fourth control line;
  • the fourth thin film transistor includes a fourth source electrode, a fourth drain electrode and a fourth gate electrode, the fourth source electrode is electrically connected to the fifth test data line, and the fourth drain electrode is electrically connected to the multiple test data lines.
  • One of the second data transmission lines is electrically connected, and the fourth gate is electrically connected to the fourth control line.
  • the third sub-circuit includes: a fifth thin film transistor, a sixth thin film transistor, a fifth control line, a sixth test data line, and a seventh test data line; the fifth control line, the Six test data lines and the seventh test data line extend along the extending direction of the first boundary;
  • the fifth thin film transistor includes: a fifth source electrode, a fifth drain electrode and a fifth gate electrode, the fifth source electrode is electrically connected to the sixth test data line, and the fifth drain electrode is connected to the multiple one of the second data transmission lines is electrically connected, and the fifth gate is electrically connected to the fifth control line;
  • the sixth thin film transistor includes: a sixth source electrode, a sixth drain electrode and a sixth gate electrode, the sixth source electrode is electrically connected to the seventh test data line, and the sixth drain electrode is connected to the multiple One of the second data transmission lines is electrically connected, and the sixth gate is electrically connected to the fifth control line.
  • the display substrate further includes: a plurality of second test dummy circuits, the plurality of second test dummy circuits are located in the extension direction of the plurality of second test circuits along the extension direction of the first boundary. on both sides and between a plurality of electrostatic discharge dummy circuits and the plurality of first test dummy circuits, the plurality of second test dummy circuits communicate with the first test dummy circuits through the plurality of data transmission dummy lines and The electrostatic discharge dummy circuit is electrically connected.
  • At least one of the plurality of second test dummy circuits includes: a first dummy sub-circuit, a second dummy sub-circuit and a third dummy sub-circuit, the second dummy sub-circuit The circuit is located between the first dummy sub-circuit and the third dummy sub-circuit, and the first dummy sub-circuit is located on a side of the second dummy sub-circuit away from the plurality of sub-pixels.
  • the multiple data transmission dummy lines include: multiple first data transmission dummy lines and multiple second data transmission dummy lines, the multiple first data transmission dummy lines and the multiple second data transmission dummy lines The transmission dummy lines are arranged alternately one by one;
  • the first dummy sub-circuit includes: a second dummy thin film transistor, a sixth control line, and an eighth test data line, the sixth control line and the eighth test data line extending along the direction of the first boundary
  • the second dummy thin film transistor includes: a second dummy source, a second dummy drain and a second dummy gate, the second dummy drain and one of the plurality of first data transmission dummy lines electrically connected, the second dummy gate is electrically connected to the sixth control line.
  • the second dummy sub-circuit includes: a third dummy thin film transistor, a fourth dummy thin film transistor, a seventh control line, a ninth test data line, and a tenth test data line, the seventh control line, the ninth test data line and the tenth test data line extend along the extending direction of the first boundary;
  • the third dummy thin film transistor includes: a third dummy source, a third dummy drain and a third dummy gate, the third dummy drain is electrically connected to one of the plurality of second data transmission dummy lines , the third dummy gate is electrically connected to the seventh control line;
  • the fourth dummy thin film transistor includes: a fourth dummy source, a fourth dummy drain and a fourth dummy gate, the fourth dummy drain is electrically connected to one of the plurality of second data transmission lines, and the fourth dummy drain is electrically connected to one of the plurality of second data transmission lines.
  • the fourth dummy gate is electrically connected to the seventh control line.
  • the third dummy subcircuit includes: a fifth dummy thin film transistor, a sixth dummy thin film transistor, an eighth control line, an eleventh test data line, and a twelfth test data line; the eighth control line line, the eleventh test data line and the twelfth test data line extend along the extending direction of the first boundary;
  • the fifth dummy thin film transistor includes: a fifth dummy source, a fifth dummy drain and a fifth dummy gate, the fifth dummy drain is electrically connected to one of the plurality of second data transmission lines, and the fifth dummy drain is electrically connected to one of the plurality of second data transmission lines. the fifth dummy gate is electrically connected to the eighth control line;
  • the sixth dummy thin film transistor includes: a sixth dummy source, a sixth dummy drain and a sixth dummy gate, the sixth dummy drain is electrically connected to one of the plurality of second data transmission lines, and the The sixth dummy gate is electrically connected to the eighth control line.
  • the number of the second test dummy circuits is the same as the number of the electrostatic discharge dummy circuits and the number of the first test dummy circuits, and each of the electrostatic discharge dummy circuits passes one of the second test dummy circuits.
  • the circuit is electrically connected to one of the first test dummy circuits.
  • the display substrate further includes: at least one first signal input end;
  • the at least one first signal input terminal is connected to the third sub-trace in the first trace segment of the panel crack detection trace, and the at least one first signal input terminal is configured to receive a test signal to detect all The display substrate is tested.
  • the at least one first signal input terminal includes two first signal input terminals, and the two first signal input terminals are located on two sides of the first test circuit, respectively.
  • the display substrate further includes: a first detection end and a second detection end;
  • the first detection terminal is connected to a first sub-trace in the first trace segment of the panel crack detection trace, and is used for providing a detection signal for the first sub-trace;
  • the second detection terminal is connected to the second sub-trace in the first trace segment of the panel crack detection trace, and is used for receiving the detection signal to detect the display substrate.
  • At least one of the plurality of electrostatic discharge dummy circuits includes: an electrostatic protection line, at least one first discharge transistor, and at least one second discharge transistor;
  • Both the first pole and the gate of the at least one first discharge transistor are electrically connected to the panel crack detection trace, and the second pole of the at least one first discharge transistor is electrically connected to the electrostatic protection wire;
  • Both the first electrode and the gate of the at least one second discharge transistor are electrically connected to the electrostatic protection line, and the second electrode of the at least one second discharge transistor is electrically connected to the panel crack detection line.
  • the plurality of electrostatic discharge dummy circuits are uniformly distributed in the peripheral area along the boundary of the display area.
  • a display device comprising: the display substrate according to the above aspect.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a first test circuit provided by an embodiment of the present application.
  • FIG. 7 is a partial schematic view of the display substrate shown in FIG. 5;
  • FIG. 8 is a schematic structural diagram of a first test dummy circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another first test dummy circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a second test circuit provided by an embodiment of the present application.
  • FIG. 12 is a cross-sectional view of a display substrate provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a second test dummy circuit provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 15 is a circuit diagram of a wiring for detecting panel cracks provided by an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • 17 is a circuit diagram of an electrostatic discharge dummy circuit provided by an embodiment of the present application.
  • FIG. 18 is a circuit diagram of another electrostatic discharge dummy circuit provided by an embodiment of the present application.
  • FIG. 19 is a schematic diagram of an electrostatic discharge dummy circuit for discharging negative charges according to an embodiment of the present application.
  • FIG. 20 is a schematic diagram of an electrostatic discharge dummy circuit that discharges positive charges according to an embodiment of the present application
  • 21 is a schematic structural diagram of an electrostatic discharge dummy circuit provided by an embodiment of the present application.
  • 22 is a circuit diagram of an electrostatic discharge dummy circuit provided by an embodiment of the present application.
  • FIG. 23 is a circuit diagram of another electrostatic discharge circuit provided by an embodiment of the present application.
  • 24 is a schematic diagram of an electrostatic discharge circuit for discharging negative charges provided by an embodiment of the present application.
  • 25 is a schematic diagram of an electrostatic discharge circuit for discharging positive charges according to an embodiment of the present application.
  • 26 is a schematic structural diagram of an electrostatic discharge circuit provided by an embodiment of the present application.
  • FIG. 27 is a schematic structural diagram of an electrostatic discharge dummy circuit, a first test dummy circuit, and a second test dummy circuit provided by an embodiment of the present application;
  • FIG. 28 is a schematic structural diagram of an electrostatic discharge circuit, a first test circuit, and a second test circuit provided by an embodiment of the present application.
  • a panel crack detection (PCD) trace is usually set in the edge region of the base substrate 001 of the display substrate.
  • the PCD wiring is an annular wiring that surrounds the display area of the base substrate.
  • One end and the other end of the PCD trace are connected with the detection circuit to form a loop.
  • the detection circuit is used for inputting a detection signal to one end of the PCD, and can detect whether the detection signal can be received from the other end of the PCD wiring.
  • the length of the PCD traces is relatively long, which leads to the accumulation of static electricity on the PCD traces during the manufacturing process of the display substrate. As a result, other traces in the display substrate are blown, and the yield of the display substrate is low.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • the display substrate 00 may include: a base substrate 001 , a plurality of sub-pixels 002 , a plurality of data lines 003 , a plurality of data transmission lines 004 , and a plurality of electrostatic discharge (electro-static discharge, ESD) circuits 005 , the panel crack detection trace 006 , and a plurality of electrostatic discharge dummy circuits 007 .
  • ESD electrostatic discharge
  • the base substrate 001 may have a display area 001a and a peripheral area 001b surrounding the display area 001a.
  • the plurality of sub-pixels 002 may be located in a display area 001 a, and a plurality of data lines 003 may be located in the display area 001 a and electrically connected to the plurality of sub-pixels 002 .
  • each data line 003 may be electrically connected to a column of sub-pixels 002 among the plurality of sub-pixels 002 .
  • the plurality of data transmission lines 004 may be located in the peripheral region 001b and electrically connected to the plurality of data lines 003 .
  • each data transmission line 004 may be electrically connected with one data line 003 .
  • the plurality of electrostatic discharge circuits 005 may be located in the peripheral area 001b, the plurality of electrostatic discharge circuits 005 may be electrically connected to the plurality of data transmission lines 004, and the plurality of electrostatic discharge circuits 005 may be arranged along the extending direction of the boundary of the display area 001a . That is, the electrostatic discharge circuit 005 can be electrically connected to the data line 003 through the data transmission line 004 , and can be used to discharge static electricity on the data line 003 .
  • the panel crack detection trace 006 may be located in the peripheral area 001b and surround the display area 001a. That is, the panel crack detection wiring 006 may be a ring-shaped wiring surrounding the display area 001a.
  • the plurality of electrostatic discharge dummy circuits 007 may be located in the peripheral area 001b and arranged along the extension direction of the boundary of the display area 001a, and the plurality of electrostatic discharge dummy circuits 007 may be located in the plurality of electrostatic discharge circuits along the extension direction of the boundary of the display area 001a
  • On at least one side of 005 at least one electrostatic discharge dummy circuit 007 of the plurality of electrostatic discharge dummy circuits 007 is connected to the panel crack detection trace 006 and can be used to discharge static electricity on the panel crack detection trace 006 .
  • an electrostatic discharge circuit 005 needs to be manufactured in the peripheral region 001b of the base substrate 001, and the electrostatic discharge circuit 005 is electrically connected to the data transmission line 004 in the display substrate 00.
  • the data transmission line 004 is electrically connected to the data line 003, and the electrostatic discharge circuit 005 can be used to discharge static electricity in the data line 003.
  • the electrostatic discharge circuit 005 When manufacturing the electrostatic discharge circuit 005, in order to ensure the manufacturing accuracy of the electrostatic discharge circuit 005 that is electrically connected to the data transmission line 004, the electrostatic discharge circuit 005 that is not electrically connected to the data transmission line 004 can be manufactured on the base substrate 001, that is, the electrostatic discharge circuit 005 is not electrically connected to the data transmission line 004. Dummy circuit 007 is released.
  • the electrostatic discharge dummy circuit 007 provided in the display substrate may be connected to the panel crack detection trace 006, thereby discharging static electricity in the panel crack detection trace 006.
  • an embodiment of the present application provides a display substrate, the display substrate includes: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data transmission lines, a plurality of electrostatic discharge circuits, and a panel crack detection line , and a plurality of electrostatic discharge dummy circuits, wherein at least one electrostatic discharge dummy circuit in the plurality of electrostatic discharge dummy circuits can be connected to a panel crack detection trace.
  • the solution provided by the embodiments of the present application can release the static electricity accumulated on the panel crack detection trace through the electrostatic discharge dummy circuit, so as to prevent other traces in the display substrate from being blown due to the static electricity accumulated on the panel crack detection trace, and improve the display performance. substrate yield.
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • the boundary of the display area 001a may include a first boundary 001a1, a second boundary 001a2, a third boundary 001a3 and a fourth boundary 001a4 which are connected in sequence.
  • the plurality of electrostatic discharge circuits 005 and the plurality of electrostatic discharge dummy circuits 007 may be located in the peripheral region 001b1 close to the first boundary 001a1.
  • the plurality of electrostatic discharge dummy circuits 007 may include a plurality of first electrostatic discharge dummy sub-circuits 0071 and a plurality of second electrostatic discharge dummy sub-circuits 0072 , for example, two first electrostatic discharge dummy circuits are shown in FIG. 2 Subcircuit 0071 and two second ESD dummy subcircuits 0072.
  • a plurality of first electrostatic discharge dummy sub-circuits 0071 and a plurality of second electrostatic discharge dummy sub-circuits 0072 may be located on two sides of the plurality of electrostatic discharge circuits 005, respectively. That is, electrostatic discharge dummy circuits 007 are provided on both sides of the plurality of electrostatic discharge circuits 005, so that at least one first electrostatic discharge dummy circuit 007 among the plurality of first electrostatic discharge dummy circuits 007 can be detected with the panel crack.
  • the wiring 006 is connected, and at least one second ESD dummy circuit 007 among the plurality of second ESD dummy circuits 007 is connected to the panel crack detection wiring 006, and the first ESD dummy circuit 0071 and the second ESD dummy circuit 007 are connected.
  • the circuits 0072 are located on both sides of the plurality of electrostatic discharge circuits 005, so the first electrostatic discharge dummy circuit 0071 and the second electrostatic discharge dummy circuit 0072 can respectively discharge static electricity in different areas of the panel crack detection trace 006, and the electrostatic discharge is reliable. The performance is better, and the yield rate of the display substrate is higher.
  • the portion of the panel crack detection trace 006 located in the peripheral region 001b1 close to the first boundary 001a1 is more likely to accumulate static electricity than other regions. Therefore, arranging the electrostatic discharge dummy circuit 007 in the peripheral area 001b1 near the first border 001a1 can easily discharge the static electricity of the panel crack detection trace 006 in the peripheral area 001b1 near the first border 001a1. It is avoided that other wirings in the display substrate are burned off due to a large amount of static electricity accumulated in the panel crack detection wiring 006 , so as to ensure the yield of the display substrate 00 .
  • FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • the panel crack detection wiring 006 includes: a first wiring segment 0061 , a second wiring segment 0062 and a third wiring segment 0063 .
  • the first line segment 0061 is a discontinuous line, the first line segment 0061 is located in the peripheral area 001b close to the first boundary 001a1 of the display area 001a, and the first line segment 0061 extends along the extension direction X of the first boundary 001a1 .
  • the second line segment 0062 is a continuous line, the second line segment 0062 is located in the peripheral area 001b near the first boundary 001a1, the second boundary 001a2 and the third boundary 001a3, and the two end points 0062a and 0062b is located in the peripheral area 001b1 close to the first boundary 001a1, and the second line segment 0062 is connected to the first line segment 0061.
  • the third line segment 0063 is a continuous line, the third line segment 0063 is located near the third boundary 001a3, the fourth boundary 001a4 and the peripheral area 001b of the first boundary 001a1, and the two end points 0063a of the third line segment 0063 and 0063b is located in the peripheral region 001b1 close to the first boundary 001a1, and the third wiring segment 0063 is connected to the first wiring segment 0061.
  • the plurality of electrostatic discharge dummy circuits 007 are electrically connected to the first wiring segment 0061, thereby releasing the first wiring segment 0061, as well as the second wiring segment 0062 and the third wiring segment 0063 connected to the first wiring segment 0061. Static electricity.
  • the first trace segment 0061 may include: a first sub trace 00611 , a second sub trace 00612 and a third sub trace 00613 extending along the extension direction X of the first boundary 001a1 .
  • the first sub-line 00611 and the second sub-line 00612 are located on the side of the third sub-line 00613 close to the display area 001a.
  • the first end 00611a of the first sub-line 00611 can be connected to the first end 0062a of the second line segment 0062, and the first end 00613a of the third sub-line 00613 can be connected to the second line segment 0062
  • the second end 0062b of the second sub-line 00612 can be connected to the first end 0063a of the third line segment 0063, and the second end 00613b of the third sub-line 00613 can be connected to the third line segment 0063 the second end of the 0063b connection.
  • the second end 00611b of the first sub-wire 00611 and the second end 00612b of the second sub-wire 00612 have a gap.
  • a plurality of electrostatic discharge dummy circuits 007 may be connected to the third sub-wires 00613 .
  • first line segment 0061, the second line segment 0062, and the third line segment 0063 may be prepared by the same patterning process, or may be prepared by different patterning processes, which are not made in this embodiment of the present application. limited.
  • lines of different thicknesses are used to indicate the first line segment 0061 , the second line segment 0062 , and the third line segment 0063 , which are only for distinguishing each line segment, and do not represent the actual line width of each line segment.
  • the line widths of the first line segment 0061, the second line segment 0062, and the third line segment 0063 may be the same.
  • FIG. 4 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • the display substrate 00 may further include: a plurality of data transmission dummy lines 008, and a plurality of electrostatic discharge dummy circuits 007 are connected to the third sub-wire 00613 through the plurality of data transmission dummy lines 008, thereby realizing the electrostatic discharge dummy circuit 007 is connected to the third sub-wire 00613 to discharge static electricity.
  • each electrostatic discharge dummy circuit 007 in the plurality of electrostatic discharge dummy circuits 007 may be connected to the third sub-wire 00613 through a data transmission dummy line 008 .
  • the display substrate 00 may further include: a plurality of first test circuits 009 , for example, three first test circuits 009 are shown in FIG. 4 .
  • the plurality of first test circuits 009 may be located on a side of the plurality of electrostatic discharge circuits 005 away from the display area 001a, and the plurality of first test circuits 009 may be extended and arranged along the extending direction X of the first boundary 001a1.
  • FIG. 5 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a first test circuit provided by an embodiment of the present application.
  • the first test circuit 009 may include: a first thin film transistor 0091 , a first control line 0092 , a first test data line 0093 and a second test data line 0094 .
  • the first control line 0092, the first test data line 0093 and the second test data line 0094 may be located in the peripheral region 001b and extend along the extending direction X of the first boundary 001a1.
  • FIG. 7 is a partial schematic view of the display substrate shown in FIG. 5 .
  • the first thin film transistor 0091 may include: a first source electrode 00911 , a first drain electrode 00912 and a first gate electrode 00913 .
  • the first gate 00913 can be electrically connected to the first control line 0092, and the first source 00911 can be connected to the first test data line 0093, the second test data line 0094, the first sub-line 00611 and the second sub-line 00612
  • One of the lines is electrically connected, and the first drain 00912 may be electrically connected to one of the plurality of data transmission lines 004 .
  • the first source electrode 00911 in FIG. 7 may be electrically connected to the second sub-wire 00612.
  • the first control line 0092 can provide a gate driving signal for the first gate 00913 of the first thin film transistor 0091 .
  • the gate driving signal may also be referred to as a panel test switch (cell test switch, CTS) signal. If the first thin film transistor 0091 is a thin film transistor for driving red (red, R) sub-pixels or blue (blue, B) sub-pixels to emit light, the drain of the first thin film transistor 0091 can be the same as the first test data
  • the line 0093 is electrically connected, and the first test data line 0093 is used to provide data signals for the red sub-pixels and the blue sub-pixels.
  • the first drain electrode 00912 of the first thin film transistor 0091 can be connected to the second test data line 0094, the first sub-pixel One of the line 00611 and the second sub-line 00612 is electrically connected, the second test data line 0094, the first sub-line 00611, or the second sub-line 00612 is used to provide data signals for the green sub-pixels.
  • the second test data line 0094 provides the driving signal of the first thin film transistor 0091 of the green sub-pixel
  • the first test data line 0093 provides the first thin film of the red sub-pixel with the driving signal.
  • the driving signals of the transistor 0091 or the first thin film transistor 0091 of the blue sub-pixel are the same.
  • the first test circuit 009 needs to be manufactured in the peripheral region 001b1 of the base substrate 001 close to the first boundary 001a1 , and the first test circuit 009 is connected to the sub-pixels 002 in the display substrate 00 .
  • the electrical connection is used to detect the light-emitting performance of the sub-pixel 002 .
  • a test circuit that is not electrically connected to the sub-pixel 002 can be fabricated on the base substrate 001, that is, the first test circuit 009 is not electrically connected to the sub-pixel 002.
  • a test dummy circuit 010 In this embodiment of the present application, the electrostatic discharge dummy circuit 007 provided in the display substrate 00 can be connected to the panel crack detection trace 006 through the first test dummy circuit 010, which can optimize the trace and circuit arrangement of the backplane.
  • FIG. 8 is a schematic diagram of a first test dummy circuit provided by an embodiment of the present application.
  • the display substrate 00 may further include: a plurality of first test dummy circuits 010, the plurality of first test dummy circuits 010 are located in multiple The two sides of the first test circuit 009 are located between the plurality of electrostatic discharge dummy circuits 007 and the third sub-trace 00613 .
  • the plurality of first test dummy circuits 010 are electrically connected to the third sub-wires 00613 and the electrostatic discharge dummy circuit 007 through a plurality of data transmission dummy lines 008 . That is, the electrostatic discharge dummy circuit 007 can be connected to the third sub-wire 00613 through the first test dummy circuit 010 to discharge static electricity.
  • FIG. 9 is a schematic diagram of another first test dummy circuit provided by an embodiment of the present application.
  • the first test dummy circuits 010 may include: a first dummy thin film transistor 0101 and a second control line 0102 .
  • the second control line 0102 is located in the peripheral region 001b and extends along the extending direction X of the first boundary 001a1.
  • the first dummy thin film transistor 0101 may include: a first dummy source electrode 01011 , a first dummy drain electrode 01012 and a first dummy gate electrode 01013 .
  • the first dummy gate 01013 may be electrically connected to the second control line 0102, and the second control line 0102 may provide a gate driving signal for the first dummy gate 01013.
  • the first dummy drain 01012 may be electrically connected to one of the plurality of data transmission dummy lines 008 .
  • the first control line 0092 may be electrically connected to the second control line 0102, that is, the first control line 0092 and the second control line 0102 may be the same control line, and the first control line
  • the gate driving signal provided by 0092 to the first gate 00913 of the first thin film transistor 0091 may be the same as the gate driving signal provided by the second control line 0102 to the first dummy gate 01013 of the first dummy thin film transistor 0101 .
  • the number of the electrostatic discharge dummy circuits 007 may be the same as the number of the first test dummy circuits 010, and each electrostatic discharge dummy circuit 007 may pass through a first test dummy circuit 010 and a third sub-wire 00613 to be electrically connected. connect.
  • FIG. 5 shows two electrostatic discharge dummy circuits 007 , which are located on both sides of the electrostatic discharge circuit 005 , respectively.
  • Each of the electrostatic discharge dummy circuits 007 may be electrically connected to the first test dummy circuit 010 on the same side.
  • the number of the electrostatic discharge dummy circuits 007 may be smaller than the number of the first test dummy circuits 010 .
  • each ESD dummy circuit 007 is electrically connected to a corresponding first test dummy circuit 010
  • the first test circuit 009 that is not electrically connected to the ESD dummy circuit 007 is still an independent circuit.
  • the number of the electrostatic discharge dummy circuits 007 may be greater than the number of the first test dummy circuits 010 .
  • at least two electrostatic discharge dummy circuits 007 in the plurality of electrostatic discharge dummy circuits 007 are electrically connected to the same first test dummy circuit 010 .
  • FIG. 10 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • the display substrate 00 may further include: a plurality of second test circuits 011, the plurality of second test circuits 011 may be located between the plurality of electrostatic discharge circuits 005 and the plurality of first test circuits 009, And the plurality of second test circuits 011 can be electrically connected to the plurality of electrostatic discharge circuits 005 and the plurality of first test circuits 009 through a plurality of data transmission lines 004 .
  • FIG. 11 is a schematic diagram of a second test circuit provided by an embodiment of the present application.
  • at least one second test circuit 011 of the plurality of second test circuits 011 may include: a first sub-circuit 0111 , a second sub-circuit 0112 and a third sub-circuit 0113 .
  • the second sub-circuit 0112 may be located between the first sub-circuit 0111 and the third sub-circuit 0113, the first sub-circuit 0111 is located on the side of the second sub-circuit 0112 away from the plurality of sub-pixels 002, and the third sub-circuit 0113 It is located on one side of the second sub-circuit 0112 close to the plurality of sub-pixels 002 .
  • the plurality of data transmission lines 004 may include: a plurality of first data transmission lines 0041 and a plurality of second data transmission lines 0042, the plurality of first data transmission lines 0041 and the plurality of second data transmission lines 0042 are alternately arranged one by one For example, three first data transmission lines 0041 and three second data transmission lines 0042 are shown in FIG. 11 .
  • the first sub-circuit 0111 may include: a second thin film transistor 01111, a third control line 01112 and a third test data line 01113, the third control line 01112 and the third test data line 01113 may be along the extending direction of the first boundary 001a1 X extension.
  • the plurality of first data transmission lines 0041 may be disposed in the same layer as the first layer gate G in the thin film transistor, and the plurality of second data transmission lines 0042 may be disposed in the same layer as the second layer gate electrode. That is, the first data transmission line 0041 and the gate G of the first layer can be formed by a single patterning process, and the second data transmission line 0042 can be formed by a patterning process with the gate of the second layer.
  • the second thin film transistor 01111 may include: a second source electrode 011111, a second drain electrode 011112 and a second gate electrode 011113, the second source electrode 011111 can be electrically connected to the third test data line 01113,
  • the second drain 011112 may be electrically connected to one of the plurality of first data transmission lines 0041, and the second gate 011113 may be electrically connected to the third control line 01112.
  • the third test data line 01113 can provide data signals for the second source electrode 011111, and the third control line 01112 can provide gate driving signals for the second gate electrode 011113.
  • the first data transmission line 0041 may be electrically connected to the data line 003 in the display area 001a for providing driving signals for the green sub-pixels 002.
  • the second sub-circuit 0112 may include: a third thin film transistor 01121 , a fourth thin film transistor 01122 , a fourth control line 01123 , a fourth test data line 01124 , and a fifth test data line 01125 .
  • the fourth control line 01123, the fourth test data line 01124, and the fifth test data line 01125 extend along the extending direction X of the first boundary 001a1.
  • the third thin film transistor 01121 may include: a third source electrode 011211, a third drain electrode 011212 and a third gate electrode 011213, the third source electrode 011211 can be electrically connected to the fourth test data line 01124, and the third drain electrode
  • the 011212 may be electrically connected to one of the plurality of second data transmission lines 0042, and the third gate 011213 may be electrically connected to the fourth control line 01123.
  • the fourth test data line 01124 can provide data signals for the third source electrode 011211, and the fourth control line 01123 can provide gate driving signals for the third gate electrode 011213.
  • the fourth thin film transistor 01122 may include: a fourth source electrode 011221, a fourth drain electrode 011222 and a fourth gate electrode 011223, the fourth source electrode 011221 may be electrically connected to the fifth test data line 01125, and the fourth drain electrode 011222 may be In electrical connection with one of the plurality of second data transmission lines 0042, the fourth gate 011223 may be electrically connected with the fourth control line 01123.
  • the fifth test data line 01125 can provide a data signal for the fourth source electrode 011221, and the fourth control line 01123 can also provide a gate driving signal for the fourth gate electrode 011223. That is, the third thin film transistor 01121 and the fourth thin film transistor 01122 may share one control line.
  • the second data transmission line 0042 may be electrically connected to the data line 003 in the display area 001a that provides a driving signal for the red sub-pixel 002 or the blue sub-pixel 002.
  • the third sub-circuit 0113 may include: a fifth thin film transistor 01131 , a sixth thin film transistor 01132 , a fifth control line 01133 , a sixth test data line 01134 , and a seventh test data line 01135 .
  • the sixth test data line 01134 and the seventh test data line 01135 may extend along the extending direction X of the first boundary 001a1.
  • the fifth thin film transistor 01131 may include: a fifth source electrode 011311 , a fifth drain electrode 011312 and a fifth gate electrode 011313 .
  • the fifth source electrode 011311 may be electrically connected to the sixth test data line 01134
  • the fifth drain electrode 011312 may be electrically connected to one of the plurality of second data transmission lines 0042
  • the fifth gate electrode 011313 may be electrically connected to the fifth control line 01133 connect.
  • the sixth test data line 01134 can provide a data signal for the fifth source electrode 011311, and the fifth control line 01133 can provide a gate driving signal for the fifth gate electrode 011313.
  • the sixth thin film transistor 01132 may include: a sixth source electrode 011321, a sixth drain electrode 011322 and a sixth gate electrode 011323, the sixth source electrode 011321 may be electrically connected to the seventh test data line 01135, and the sixth drain electrode 011322 may be In electrical connection with one of the plurality of second data transmission lines 0042, the sixth gate 011323 may be electrically connected with the fifth control line 01133.
  • the seventh test data line 01135 can provide data signals for the sixth source electrode 011321, and the fifth control line 01133 can also provide gate driving signals for the sixth gate electrode 011323. That is, the fifth thin film transistor 01131 and the sixth thin film transistor 01132 may share one control line.
  • the fourth control line 01123 and the fifth control line 01131 are arranged adjacently, and the fourth control line 01123 and the fifth control line 01131 may be one control line.
  • the third thin film transistor 01121, the fourth thin film transistor 01122, the fifth thin film transistor 01131 and the sixth thin film transistor 01132 can share one control line.
  • the display substrate 00 may further include: a plurality of second test dummy circuits 012 .
  • the plurality of second test dummy circuits 012 are located on both sides of the plurality of second test circuits 011 and are located on the plurality of electrostatic discharge dummy circuits 007 and the plurality of first test dummy circuits 010 in the extending direction X along the first boundary 001a1 between.
  • the plurality of second test dummy circuits 012 may be electrically connected to the first test dummy circuit 010 and the electrostatic discharge dummy circuit 007 through a plurality of data transmission dummy lines 008 .
  • FIG. 13 is a schematic diagram of a second test dummy circuit provided by an embodiment of the present application.
  • at least one second test dummy circuit 012 among the plurality of second test dummy circuits 012 may include: a first dummy sub-circuit 0121 , a second dummy sub-circuit 0122 and a third dummy sub-circuit 0123 .
  • the second dummy sub-circuit 0122 may be located between the first dummy sub-circuit 0121 and the third dummy sub-circuit 0123, the first dummy sub-circuit 0121 is located on the side of the second dummy sub-circuit 0122 away from the plurality of sub-pixels 002, the third dummy sub-circuit 0121 The sub-circuit 0123 is located on one side of the second dummy sub-circuit 0122 close to the plurality of sub-pixels 002 .
  • the plurality of data transmission dummy lines 008 may include: a plurality of first data transmission dummy lines 0081 and a plurality of second data transmission dummy lines 0082 .
  • the plurality of first data transmission dummy lines 0081 and the plurality of second data transmission dummy lines 0082 are alternately arranged one by one.
  • the first dummy sub-circuit 0121 may include: a second dummy thin film transistor 01211, a sixth control line 01212, and an eighth test data line 01213.
  • the sixth control line 01212 and the eighth test data line 01213 may extend along the extending direction X of the first boundary 001a1.
  • the second dummy thin film transistor 01211 may include: a second dummy source electrode 012111 , a second dummy drain electrode 012112 and a second dummy gate electrode 012113 .
  • the second dummy drain 012112 is electrically connected to one of the plurality of first data transmission dummy lines 0081
  • the second dummy gate 012113 may be electrically connected to the sixth control line 01212 . That is, the sixth control line 01212 may provide a gate driving signal for the second dummy gate 012113.
  • the first data transmission dummy line 0081 is not connected to the data line 003 in the display area 001a, but is connected to the third sub-line 00613.
  • the second dummy sub-circuit 0122 may include: a third dummy thin film transistor 01221, a fourth dummy thin film transistor 01222, a seventh control line 01223, a ninth test data line 01224, and a tenth test data line 01225.
  • the seventh control line 01223, the ninth test data line 01224, and the tenth test data line 01225 extend along the extending direction X of the first boundary 001a1.
  • the third dummy thin film transistor 01221 may include: a third dummy source electrode 012211, a third dummy drain electrode 012212, a third dummy gate electrode 012213, a third dummy drain electrode 012212 and one of the plurality of second data transmission dummy lines 0082 Electrically connected, the third dummy gate 012213 is electrically connected to the seventh control line 01223.
  • the seventh control line 01223 may provide a gate driving signal for the third dummy gate 012213.
  • the fourth dummy thin film transistor 01222 may include: a fourth dummy source electrode 012221, a fourth dummy drain electrode 012222 and a fourth dummy gate electrode 012223.
  • the fourth dummy drain 012222 may be electrically connected to one of the plurality of second data transmission lines 0042, and the fourth dummy gate 012223 may be electrically connected to the seventh control line 01223.
  • the seventh control line 01223 may provide a gate driving signal for the fourth dummy gate 012223. That is, the third dummy thin film transistor 01221 and the fourth dummy thin film transistor 01222 may share one control line.
  • the second data transmission dummy line 0082 is not connected to the data line 003 in the display area 001a, but is connected to the third sub-wire 00613.
  • the third dummy sub-circuit 0123 includes: the fifth dummy thin film transistor 01231, the sixth dummy thin film transistor 01232, the eighth control line 01233, the eleventh test data line 01234, and the twelfth test Data line 01235.
  • the eleventh test data line 003 and the twelfth test data line 01235 extend along the extending direction X of the first boundary 001a1.
  • the fifth dummy thin film transistor 01231 may include: a fifth dummy source electrode 012311, a fifth dummy drain electrode 012312 and a fifth dummy gate electrode 012313, and the fifth dummy drain electrode 012312 may be electrically connected to one of the plurality of second data transmission lines 0042 connected, the fifth dummy gate 012313 may be electrically connected to the eighth control line 01233.
  • the eighth control line 01233 can provide a gate driving signal for the fifth dummy gate 012313.
  • the sixth dummy thin film transistor 01232 may include: a sixth dummy source electrode 012321, a sixth dummy drain electrode 012322 and a sixth dummy gate electrode 012323, and the sixth dummy drain electrode 012322 may be electrically connected to one of the plurality of second data transmission lines 0042 connected, the sixth dummy gate 012323 may be electrically connected with the eighth control line 01233. That is, the fifth dummy thin film transistor 01231 and the sixth dummy thin film transistor 01232 may share one control line.
  • the seventh control line 01123 and the eighth control line 01233 are arranged adjacently, and the seventh control line 01123 and the eighth control line 01233 may be one control line. Therefore, the third dummy thin film transistor 01221, the fourth dummy thin film transistor 01222, the fifth dummy thin film transistor 01231 and the sixth dummy thin film transistor 01232 can share one control line.
  • the third control line 01112 may be electrically connected to the sixth control line 01212, that is, the third control line 01112 and the sixth control line 01212 may be the same control line.
  • the gate driving signal provided by the third control line 01112 to the second gate 011113 of the second thin film transistor 01111 can be provided with the sixth control line 01212 to the gate of the second dummy gate 012113 of the second dummy thin film transistor 01211 The driving signals are the same.
  • the fourth control line 01123 may be electrically connected to the seventh control line 01223, that is, the fourth control line 01123 and the seventh control line 01223 may be the same control line.
  • the fourth control line 01123 provides gate driving signals to the third gate 011213 of the third thin film transistor 01121 and the fourth gate 011223 of the fourth thin film transistor 01122, and can be provided to the third dummy thin film together with the seventh control line 01223
  • the gate driving signals of the third dummy gate 012213 of the transistor 01221 and the fourth dummy gate 012223 of the fourth dummy thin film transistor 01222 are the same.
  • the fifth control line 01133 may be electrically connected to the eighth control line 01233, that is, the fifth control line 01133 and the eighth control line 01233 may be the same control line.
  • the fifth control line 01133 provides gate driving signals to the fifth gate 011313 of the fifth thin film transistor 01131 and the sixth gate 011323 of the sixth thin film transistor 01132, and can be provided to the fifth dummy thin film together with the eighth control line 01233
  • the gate driving signals of the fifth dummy gate 012313 of the transistor 01231 and the sixth gate 012313 of the sixth dummy thin film transistor 01232 are the same.
  • the third test data line 01113 may be electrically connected to the eighth test data line 01213, that is, the third test data line 01113 and the eighth test data line 01213 may be the same data line.
  • the third test data line 01113 and the eighth test data line 01213 can provide data signals for the second source electrode 01111 of the second thin film transistor 01111.
  • the fourth test data line 01124 may be electrically connected to the ninth test data line 01224, that is, the fourth test data line 01124 and the ninth test data line 01224 may be the same data line.
  • the fourth test data line 01124 and the ninth test data line 01224 can provide data signals for the third source electrode 011211 of the third thin film transistor 01121.
  • the fifth test data line 01125 may be electrically connected to the tenth test data line 01225, that is, the fifth test data line 01125 and the tenth test data line 01225 may be the same data line.
  • the fifth test data line 01125 and the tenth test data line 01225 can provide data signals for the fourth source electrode 011221 of the fourth thin film transistor 01122.
  • the sixth test data line 01134 may be electrically connected to the eleventh test data line 01234, that is, the sixth test data line 01134 and the eleventh test data line 01234 may be the same data line.
  • the sixth test data line 01134 and the eleventh test data line 01234 can provide data signals for the fifth gate 011313 of the fifth thin film transistor 01131 .
  • the seventh test data line 01135 may be electrically connected to the twelfth test data line 01235, that is, the seventh test data line 01135 and the twelfth test data line 01235 may be the same data line.
  • the seventh test data line 01135 and the twelfth test data line 01235 can provide data signals for the sixth source electrode 011321 of the sixth thin film transistor 01132 .
  • the second test circuit 011 needs to be manufactured in the peripheral region 001b of the base substrate 001 between the electrostatic discharge circuit 005 and the first test circuit 009.
  • the second test circuit 011 can be used to connect the electrostatic discharge circuit 005 and the first test circuit 009 .
  • a test circuit that is not electrically connected to the electrostatic discharge circuit 005 and the first test circuit 009 can be manufactured on the base substrate 001, namely, The second test dummy circuit 012 .
  • the electrostatic discharge dummy circuit 007 provided in the display substrate can be connected to the panel crack detection trace 006 through the second test dummy circuit 012 and the first test dummy circuit 010, which can optimize the traces and traces of the backplane. circuit layout.
  • the number of the second test dummy circuits 012 may be the same as the number of the electrostatic discharge dummy circuits 007 and the number of the first test dummy circuits 010 .
  • Each electrostatic discharge dummy circuit 007 may be electrically connected to a first test dummy circuit 010 through a second test dummy circuit 012 .
  • FIG. 10 shows two second test dummy circuits 012 , and the two second test dummy circuits 012 may be located on both sides of the plurality of second test circuits 011 .
  • the second test dummy circuit 012 may be electrically connected to the electrostatic discharge dummy circuit 007 and the first test dummy circuit 010 on the same side.
  • FIG. 14 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • the display substrate 00 may further include: at least one first signal input terminal 013 .
  • the at least one first signal input terminal 013 may be connected to the third sub-wire 00613, and the at least one first signal input terminal 013 may be configured to receive a test signal to test the display substrate.
  • the at least one first signal input terminal 013 may include: two first signal input terminals 013 , and the two first signal input terminals 013 may be located on two sides of the first test circuit 009 respectively.
  • the plurality of sub-pixels 002 may include: at least one column of first sub-pixels 0021 . Only some sub-pixels 002 in each column of sub-pixels 002 are schematically shown in FIG. 14 .
  • the first sub-pixel 0021 can be connected to the first sub-wire 00611 or the second sub-wire 00612, and the at least one first signal input terminal 013 can be used to provide a driving signal to the first sub-pixel 0021, and the driving signal can be used with The first sub-pixel 0021 in each column is driven to emit light of the target color.
  • the driving signal may be a panel test data (cell test data, CTD) signal.
  • the third sub-line 00613 is connected to the second line segment 0062 and the third line segment 0063
  • the second line segment 0062 is connected to the first sub-line 00611
  • the third line segment 0063 is connected to the second sub-line 00612.
  • the first sub-line 00611 may be connected to the first sub-pixel 0021
  • the second sub-line 00612 may be connected to the first sub-pixel 0021 .
  • the first signal input terminal 013 inputs a driving signal to the third sub-line 00613, and the third sub-line 00613 can transmit the driving signal to the second line segment 0062 and the third line segment 0063, and the second line segment 0062
  • the driving signal can be transmitted to the first sub-wire 00611
  • the third wire segment 0063 can transmit the driving signal to the second sub-wire 00612
  • the first sub-line 00611 can transmit the drive signal to the first sub-pixel 0021 connected to the first sub-line 00611
  • the second sub-line 00612 can transmit the drive signal to the second sub-line 00612 Connected first sub-pixel 0021.
  • the driving signal needs to pass through the third sub-line 00613, the second line segment 0062, and the first sub-line 00611 in sequence before being transmitted to the first sub-pixel 0021 connected to the first sub-line 00611. If there are cracks on the edge of the third sub-line 00613, the second line segment 0062, and the area where the first sub-line 00611 is located in the display substrate, that is, the third sub-line 00613, the second line segment 0062 or the first sub-line The line 00611 is broken, the driving signal cannot be transmitted to the first sub-pixel 0021 connected to the first sub-wire 00611, and the first sub-pixel 0021 cannot emit light of the target color.
  • the driving signal can be transmitted to the first sub-pixel 0021 connected to the first sub-wire 00611, and the first sub-pixel 0021 can emit light of the target color.
  • the driving signal needs to pass through the third sub-line 00613, the third line segment 0063, and the second sub-line 00612 in sequence before being transmitted to the first sub-pixel 0021 connected to the second sub-line 00612. If there are cracks on the edge of the area where the third sub-line 00613, the third line segment 0063, and the second sub-line 00612 are located in the display substrate, that is, the third sub-line 00613, the third line segment 0063 or the second sub-line The line 00612 is broken, the driving signal cannot be transmitted to the first sub-pixel 0021 connected to the second sub-line 00612, and the first sub-pixel 0021 cannot emit light of the target color.
  • the driving signal can be transmitted to the first sub-pixel 0021 connected to the second sub wiring 00612, and the first sub-pixel 0021 can emit light of the target color.
  • the target color may be black
  • the first sub-pixel 0021 may be a green sub-pixel 002. If there is a crack on the edge of the display substrate 00, the green sub-pixel 002 cannot receive the driving signal, and the green sub-pixel 002 may be Emits green light.
  • the first sub-pixel 0021 emits light of the target color. That is, if each column of the first sub-pixels 0021 can emit light of the target color, it can be determined that the first sub-pixels 0021 can receive the driving signal, and further it can be determined that there is no crack on the edge of the display substrate 00 . If the first sub-pixels 0021 in a certain row cannot emit light of the target color, it can be determined that the first sub-pixels 0021 in the row cannot receive the driving signal, and then it can be determined that there is a crack on the edge of the display substrate 00 .
  • the panel crack detection trace 006 will not be cracked, and the first sub-pixel 0021 can emit light of the target color.
  • FIG. 15 is a schematic diagram of detection of a panel crack detection trace provided by an embodiment of the present application.
  • the panel crack detection trace 006 can be connected to the source of the target transistor M0, the gate of the target transistor M0 can be connected to the gate line A, and the drain of the target transistor M0 can pass through the data transmission line 004 and The data line 003 is connected to the first sub-pixel 0021 .
  • the current I flowing in the target transistor M0 can satisfy:
  • K is a constant determined by the characteristics of the target transistor M0, which satisfies: ⁇ is the carrier mobility of the target transistor M0, W/L is the channel width to length ratio of the target transistor M0, ⁇ is the dielectric constant of the gate oxide layer of the target transistor M0, and d is the thickness of the gate oxide layer.
  • Vgs is the voltage difference between the gate and source of the target transistor M0
  • Vth is the threshold voltage of the target transistor M0
  • Vdata is the voltage on the data transmission line 004
  • Vs is the source voltage of the target transistor M0.
  • the source voltage of the target transistor M0 provided by the panel crack detection line 006 and the first target drive line B and the second target drive line C are provided to the sources of other transistors
  • the voltage is the same, and may be, for example, 6 volts (V).
  • the green sub-pixel 002 connected to the target transistor M0 will be lit, that is, a green bright line will appear on the black-state picture.
  • FIG. 16 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • the display substrate 00 may further include: a first detection end 014 and a second detection end 015 .
  • the first detection terminal 014 can be connected to the first sub-wire 00611 for providing a detection signal to the first sub-wire 00611 .
  • the second detection terminal 015 can be connected to the second sub-wire 00612 for receiving detection signals to detect the display substrate.
  • the second detection terminal 015 can receive the detection signal, it can be determined that the panel crack detection trace 006 is not broken, that is, there is no crack on the edge of the display substrate 00; if the second detection terminal 015 cannot receive the detection signal, it can be determined that The panel crack detection trace 006 is disconnected, that is, it indicates that there is a crack on the edge of the substrate 00 .
  • the plurality of sub-pixels 002 may further include: multiple columns of second sub-pixels 0022 in addition to at least one column of the first sub-pixels 0021.
  • the display substrate 00 may further include: at least one second signal input terminal 016 and at least one third signal input terminal 017 .
  • the second signal input terminal 016 can be connected to at least one column of second sub-pixels 0022, and is used to provide a driving signal to each column of second sub-pixels 0022 connected thereto, and the driving signal is used to drive each column of second sub-pixels 0022 to emit Target color light.
  • the third signal input terminal 017 can be electrically connected to the first test circuit 009 and the first test dummy circuit 010 .
  • the driving signal can be directly input to the second sub-pixel 0022 . That is, regardless of whether the edge of the display substrate 00 has cracks, the second sub-pixel 0022 can emit light of the target color.
  • the second signal input terminal 016 may be electrically connected to the first test data line 0093 or the second test data line 0094 .
  • the second sub-pixel 0022 may be a red sub-pixel 002 or a blue sub-pixel 002 .
  • the at least one second signal input terminal 016 may include: four second signal input terminals 016 , and the four second signal input terminals 016 may be located on two sides of the first test circuit 009 respectively.
  • each side of the first test circuit 009 may have two second signal input terminals 016, one of the second signal input terminals 016 is electrically connected to the first test data line 0093, and the other second signal input terminal 016 is electrically connected to the first test data line 0093.
  • the second test data line 0094 is electrically connected.
  • FIG. 17 is a circuit diagram of an electrostatic discharge dummy circuit provided by an embodiment of the present application.
  • the electrostatic discharge dummy circuit 007 may include: a first electrostatic protection line 0071 , at least one first discharge transistor 0072 , and at least one second discharge transistor 0073 .
  • the first electrode and the gate of the at least one discharge transistor are both connected to the panel crack detection trace 006
  • the second electrode of the at least one first discharge transistor 0072 can be connected to the first electrostatic protection wire 0071 .
  • the first electrode and the gate of the at least one second discharge transistor 0073 may be connected to the first electrostatic protection line 0071
  • the second electrode of the at least one second discharge transistor 0073 may be connected to the panel crack detection line 006 .
  • the first discharge transistor 0072 If the static electricity accumulated on the panel crack detection line 006 is negative charge, the first discharge transistor 0072 is turned on, and the panel crack detection line 006 is connected to the first electrostatic protection line 0071, and the panel crack detection line 006 can pass the first electrostatic protection line 0071.
  • the discharge transistor 0072 discharges the first electrostatic protection line 0071 . That is, the negative charge accumulated on the panel crack detection trace 006 can be discharged to the first electrostatic protection wire 0071 through the first discharge transistor 0072 .
  • the second discharge transistor 0073 is turned on, and the panel crack detection line 006 is connected to the first electrostatic protection line 0071, and the panel crack detection line 006 can pass through the The two discharge transistors 0073 discharge to the first electrostatic protection line 0071 . That is, the positive charges accumulated on the panel crack detection trace 006 can be discharged to the first electrostatic protection wire 0071 through the second discharge transistor 0073 .
  • the first electrostatic protection line 0071 may include a first discharge line 00711 and a second discharge line 00712 .
  • the electrostatic discharge dummy circuit 007 may include: two first discharge transistors 0072 and two second discharge transistors 0073 .
  • the first pole and gate of the first first discharge transistor 0072a are both connected to the panel crack detection trace 006, and the second pole of the first first discharge transistor 0072a is connected to the second pole of the second first discharge transistor 0072b.
  • the first electrode is connected to the gate, and the second electrode of the second first discharge transistor 0072b is connected to the first discharge line 00711 . That is, the first electrode and gate of the second first discharge transistor 0072b may be connected to the first discharge line 00711 through the first first discharge transistor 0072a.
  • Both the first electrode and the gate of the first second discharge transistor 0073 are connected to the second discharge line 00712, and the second electrode of the first second discharge transistor 0073 is connected to the first electrode of the second second discharge transistor 0073 and The gate is connected, and the second pole of the second second discharge transistor 0073 is connected to the panel crack detection trace 006 . That is, the first electrode and the gate of the second second discharge transistor 0073 may be connected to the second discharge line 00712 through the first second discharge transistor 0073 .
  • the first discharge line 00711 may be a low potential (voltage gate low, VGL) line.
  • the second discharge line 00712 may be a voltage gate high (VGH) line.
  • FIG. 19 is a schematic diagram of an electrostatic discharge dummy circuit for discharging negative charges provided by an embodiment of the present application.
  • the at least one first discharge transistor 0072 is equivalent to a diode D1
  • the at least one second discharge transistor 0073 is equivalent to a diode D1. Also equivalent to a diode D2.
  • the potential Vg1 of the gate of the first discharge transistor 0072 and the potential Vs1 of the source (ie, the first electrode) of the first discharge transistor 0072 are both It is equal to the potential Vpcd of the panel crack detection wiring 006 , and the potential Vpcd is greater than the potential VGL on the first discharge line 00711 .
  • the gate potential Vg1 of each first discharge transistor 0072 and the source potential Vs1 of each first discharge transistor 0072 are equal to the potential of the panel crack detection trace 006 Vpcd, and the potential Vpcd is lower than the potential VGL on the first discharge line 00711 .
  • each of the first discharge transistors 0072 is turned on (ie, the diode D1 is turned on), and the negative charges in the panel crack detection trace 006 can be released to the first discharge line 00711 .
  • the potential VGL on the first discharge line 00711 is -7V
  • the potential Vpcd of the panel crack detection line 006 is 0V
  • the gate potential and source potential are both 0V
  • the drain potential Vd1 of the first discharge transistor 0072 is equal to -7V. At this time, the first discharge transistor 0072 is turned off.
  • the potential on the panel crack detection trace 006 is less than -7V, and the drain potential Vd1 of the first discharge transistor 0072 is equal to -7V. At this time, the first discharge transistor 0072 is turned on.
  • FIG. 20 is a schematic diagram of an electrostatic discharge dummy circuit for discharging positive charges according to an embodiment of the present application.
  • the at least one first discharge transistor 0072 is equivalent to a diode D1
  • the at least one second discharge transistor 0073 is also equivalent to a diode D2.
  • the gate potential Vg2 of each second discharge transistor 0073 and the source (first electrode) potential Vs2 of each second discharge transistor 0073 are both Equal to the potential VGH on the second discharge line 00712.
  • each second discharge transistor 0073 When positive charges are accumulated on the panel crack detection line 006, the gate potential Vg2 of each second discharge transistor 0073 and the source potential Vs2 of each second discharge transistor 0073 are equal to the potential on the second discharge line 00712 VGH.
  • each second discharge transistor 0073 is turned on (ie, the diode is turned on), and the positive charges in the panel crack detection trace 006 can be discharged to the second discharge wire 00712 .
  • the gate potential and the source potential of the second discharge transistor 0073 are both equal to the second discharge line
  • the potential on 00712 is 7V.
  • the drain potential of the second discharge transistor 0073 is equal to the potential Vpcd of the panel crack detection trace 006, that is, 0V. At this time, the second discharge transistor 0073 is turned off.
  • the drain potential of the second discharge transistor 0073 is greater than 7V, and the gate potential and the source potential of the second discharge transistor 0073 are both equal to 7V. At this time, the second discharge transistor 0073 is turned on.
  • the electrostatic discharge dummy circuit 007 included in the display substrate 00 in the embodiment of the present application can discharge the static electricity in the panel crack detection trace 006 to the first electrostatic protection trace 0071 to prevent other traces in the display substrate 00 from being lost due to the panel crack detection.
  • the static electricity accumulated on the lines 006 is blown off, thereby improving the yield of the display substrate 00 .
  • a plurality of electrostatic discharge dummy circuits 007 included in the display substrate 00 may be uniformly distributed in the peripheral area 001b along the boundary of the display area 001a.
  • the plurality of electrostatic discharge dummy circuits 007 may be uniformly distributed in the peripheral region 001b1 close to the first boundary 001a1.
  • FIG. 21 is a schematic structural diagram of an electrostatic discharge dummy circuit provided by an embodiment of the present application.
  • the first pole 00721 and the gate 00722 of the first discharge transistor 0072 in the electrostatic discharge dummy circuit 007 may be electrically connected to one of the plurality of data transmission dummy lines 008, and the second pole 00723 may be electrically connected to
  • the first electrostatic protection line 0071 is electrically connected.
  • the first electrode 00731 and the gate 00732 of the second discharge transistor 0073 may be electrically connected to the first electrostatic protection line 0071
  • the second electrode 00733 may be electrically connected to one of the plurality of data transmission dummy lines 008 .
  • the plurality of data transmission lines 004 are connected to the panel crack detection line 006 , so that the static electricity in the panel crack detection line 006 is discharged to the first electrostatic protection line 0071 through the electrostatic discharge dummy circuit 007 .
  • the first discharge transistor 0072 and the second discharge transistor 0073 included in each electrostatic discharge dummy circuit 007 may be located between the two data transmission dummy lines 008 .
  • it is located between the first data transmission dummy line 0081 and the second data transmission dummy line 0082 .
  • the extension direction of the first electrostatic protection line 0071 may intersect with the extension direction of the data transmission dummy line 008 .
  • the extension direction of the first electrostatic protection line 0071 may be perpendicular to the extension direction of the data transmission dummy line 008 .
  • a plurality of electrostatic discharge dummy circuits 007 arranged parallel to the extending direction of the first discharge line 00711 may share one first discharge line 00711
  • the two electrostatic discharge dummy circuits 007 arranged in the extending direction may share one first discharge line 00711 . That is, the electrostatic discharge dummy circuits 007 included in the display substrate 00 all share one first discharge line 00711 .
  • a plurality of electrostatic discharge dummy circuits 007 arranged parallel to the extending direction of the second discharge lines 00712 may share one second discharge line 00712 .
  • the first discharge line 00711 connected to the first discharge transistor 0072a connected to the first data transmission dummy line 0081 is connected to the first discharge line 00711 of the first discharge transistor 0072b connected to the second data transmission dummy line 0082 It is the same first discharge line 00711.
  • first discharge line 00711 , the second discharge line 00712 , the panel crack detection trace 006 , and the source and drain layers of the transistors may be provided in the same layer. That is, the first discharge line 00711, the second discharge line 00712, the panel crack detection trace 006 and the source and drain layers of the transistor are formed by the same patterning process. Alternatively, at least two structures of the first discharge line 00711, the second discharge line 00712, the panel crack detection trace 006, and the source and drain layers of the transistor may be located in different layers. For example, the first discharge line 00711, the second discharge line 00712, the panel crack detection trace 006, and the source and drain layers of the transistor are all different layers.
  • the first discharge line 00711 , the second discharge line 00712 , the panel crack detection trace 006 , and the source and drain layers of the transistors need to be formed by one patterning process respectively, for a total of four patterning processes.
  • FIG. 22 is a circuit diagram of an electrostatic discharge circuit provided by an embodiment of the present application.
  • the electrostatic discharge circuit 005 may include: a second electrostatic protection line 0051 , at least one third discharge transistor 0052 , and at least one fourth discharge transistor 0053 . Both the first electrode and the gate of the at least one third discharge transistor 0052 are electrically connected to the data transmission line 004 , and the second electrode of the at least one third discharge transistor 0052 may be electrically connected to the second electrostatic protection line 0051 .
  • the first electrode and the gate of the at least one fourth discharge transistor 0053 may be electrically connected to the second electrostatic protection line 0051 , and the second electrode of the at least one fourth discharge transistor 0053 may be electrically connected to the data transmission line 004 .
  • the third discharge transistor 0052 is turned on, and the data transmission line 004 and the second electrostatic protection line 0051 are turned on, and the data transmission line 004 can pass through the first discharge transistor 0052 to the second electrostatic protection line. 0051 discharge. That is, the negative charges accumulated on the data transmission line 004 can be discharged to the second electrostatic protection line 0051 through the third discharge transistor 0052 .
  • the fourth discharge transistor 0053 is turned on, and the data transmission line 004 and the second electrostatic protection line 0051 are turned on, and the data transmission line 004 can pass the fourth discharge transistor 0053 to the second electrostatic protection line. 0051 discharge. That is, the positive charges accumulated on the data transmission line 004 can be discharged to the second electrostatic protection line 0051 through the fourth discharge transistor 0053 .
  • the second electrostatic protection line 0051 may include a third discharge line 00511 and a fourth discharge line 00512 .
  • the electrostatic discharge circuit 005 may include: two third discharge transistors 0052 and two fourth discharge transistors 0053 .
  • the first electrode and the gate of the first third discharge transistor 0052a are connected to the data transmission line 004, the second electrode of the first third discharge transistor 0052a is connected to the first electrode of the second third discharge transistor 0052b It is connected to the gate, and the second electrode of the second third discharge transistor 0052b is connected to the third discharge line 00511. That is, the first electrode and gate of the second third discharge transistor 0052b may be connected to the third discharge line 00511 through the first third discharge transistor 0052a.
  • the first electrode and gate of the first fourth discharge transistor 0053a are both connected to the fourth discharge line 00512, and the second electrode of the first fourth discharge transistor 0053a is connected to the first electrode of the second fourth discharge transistor 0053b and The gate is connected, and the second electrode of the second fourth discharge transistor 0053b is connected to the data transmission line 004 . That is, the first electrode and gate of the second fourth discharge transistor 0053b may be connected to the fourth discharge line 00512 through the first fourth discharge transistor 0053a.
  • the third discharge line 00511 may be a VGL line.
  • the fourth discharge line 00512 may be a VGH line.
  • FIG. 24 is a schematic diagram of an electrostatic discharge circuit for discharging negative charges provided by an embodiment of the present application.
  • the at least one third discharge transistor 0052 is equivalent to a diode D3
  • the at least one fourth discharge transistor 0053 is also Equivalent to a diode D4.
  • the potential Vg3 of the gate of the third discharge transistor 0052 and the potential Vs3 of the source (ie, the first electrode) of the third discharge transistor 0052 are equal to the data transmission line
  • the potential Vc of 004 is greater than the potential VGL on the third discharge line 00511.
  • each third discharge transistor 0052 and the source potential Vs3 of each third discharge transistor 0052 are equal to the potential Vc of the data transmission line 004, and the potential Vc less than the potential VGL on the third discharge line 00511.
  • each of the first discharge transistors 0052 is turned on (ie, the diode D3 is turned on), and the negative charges in the data transmission line 004 can be discharged to the first discharge line 00511 .
  • the potential VGL on the third discharge line 00511 is -7V
  • the potential Vc of the data transmission line 004 is 0V (the gate potential and the source of the third discharge transistor 0052).
  • the pole potentials are all 0V), that is, greater than -7V.
  • the drain potential Vd3 of the third discharge transistor 0052 is equal to -7V. At this time, the third discharge transistor 0052 is turned off.
  • the potential on the data transmission line 004 is less than -7V, and the drain potential Vd3 of the third discharge transistor 0052 is equal to -7V. At this time, the third discharge transistor 0052 is turned on.
  • FIG. 25 is a schematic diagram of an electrostatic discharge circuit for discharging positive charges according to an embodiment of the present application.
  • the at least one third discharge transistor 0052 is equivalent to a diode D3
  • the at least one fourth discharge transistor 0053 is also equivalent to a diode D4.
  • the gate potential Vg4 of each fourth discharge transistor 0053 and the source (first electrode) potential Vs4 of each fourth discharge transistor 0053 are equal to the fourth The potential VGH on the discharge line 00512.
  • each fourth discharge transistor 0053 When positive charges are accumulated on the data transmission line 004 , the gate potential Vg4 of each fourth discharge transistor 0053 and the source potential Vs4 of each fourth discharge transistor 0053 are equal to the potential VGH on the fourth discharge line 00512 .
  • each fourth discharge transistor 0053 is turned on (ie, the diode is turned on), and the positive charges in the data transmission line 004 can be discharged to the fourth discharge line 00512 .
  • the gate potential and the source potential of the fourth discharge transistor 0053 are both equal to the voltage on the fourth discharge line 00512.
  • the drain potential of the fourth discharge transistor 0053 is equal to the potential Vc of the data transmission line 004, that is, 0V. At this time, the fourth discharge transistor 0053 is turned off.
  • the drain potential of the fourth discharge transistor 0053 is greater than 7V, and the gate potential and the source potential of the fourth discharge transistor 0053 are both equal to 7V. At this time, the fourth discharge transistor 0053 is turned on.
  • the electrostatic discharge circuit 005 included in the display substrate 00 in the embodiment of the present application can discharge the static electricity in the data transmission line 004 to the second electrostatic protection line 0051 , and the yield of the display substrate 00 is high.
  • FIG. 26 is a schematic structural diagram of an electrostatic discharge circuit provided by an embodiment of the present application.
  • the first pole 00721 and the gate 00722 of the third discharge transistor 0072 in the electrostatic discharge circuit 005 can be electrically connected to one of the plurality of data transmission lines 004, and the second pole 00523 can be connected to the second electrostatic discharge Guard wire 0051 is electrically connected.
  • the first pole 00531 and the gate 00532 of the fourth discharge transistor 0053 may be electrically connected to the second electrostatic protection line 0051 , and the second pole 00533 may be electrically connected to one of the plurality of data transmission lines 004 .
  • the plurality of data transmission lines 004 are electrically connected to the data lines 003, so that the static electricity in the data lines 003 is discharged to the second electrostatic protection line 0051 through the electrostatic discharge circuit 007.
  • each electrostatic discharge circuit 005 may be located between the two data transmission lines 004 .
  • the extension direction of the second electrostatic protection line 0051 may intersect with the extension direction of the data transmission line 004 .
  • the extension direction of the second electrostatic protection line 0051 may be perpendicular to the extension direction of the data transmission line 004 .
  • a plurality of electrostatic discharge circuits 005 arranged parallel to the extending direction of the second discharge line 00511 may share a third discharge line 00511 , and the extension of the third discharge line 00511 is perpendicular to the third discharge line 00511 .
  • Two electrostatic discharge circuits 005 arranged in a direction may share a first discharge line 00511 . That is, the electrostatic discharge circuits 005 included in the display substrate 00 all share a third discharge line 00511 .
  • a plurality of electrostatic discharge circuits 005 arranged parallel to the extending direction of the fourth discharge line 00512 may share one fourth discharge line 00512 .
  • the third discharge line 00511 connected to the third discharge transistor 0052a connected to the first data transmission line 0041 is the same as the third discharge line 00511 connected to the third discharge transistor 0052b connected to the second data transmission line 0042 Three discharge lines 00511.
  • the third discharge line 00511 , the fourth discharge line 00512 , the panel crack detection trace 006 , and the source and drain layers of the transistors may be provided in the same layer. That is, the third discharge line 00511, the fourth discharge line 00512, the panel crack detection trace 006 and the source and drain layers of the transistor are formed by the same patterning process. Alternatively, at least two structures of the third discharge line 00511, the fourth discharge line 00512, the panel crack detection trace 006, and the source and drain layers of the transistor may be located in different layers. For example, the third discharge line 00511, the fourth discharge line 00512, the panel crack detection trace 006, and the source and drain layers of the transistor are all different layers. That is, the third discharge line 00511, the fourth discharge line 00512, the panel crack detection trace 006, and the source and drain layers of the transistors need to be formed by one patterning process respectively, a total of four patterning processes.
  • first discharge line 00711 may be connected to the third discharge line 00511, that is, the first discharge line 00711 and the third discharge line 00511 may be the same discharge line.
  • the second discharge wire 00712 may be connected to the fourth discharge wire 00512, that is, the second discharge wire 00712 and the fourth discharge wire 00512 may be the same discharge wire.
  • FIG. 27 is a schematic structural diagram of an electrostatic discharge dummy circuit, a first test dummy circuit, and a second test dummy circuit according to an embodiment of the present application.
  • the second test dummy circuit 012 may be located between the electrostatic discharge dummy circuit 007 and the first test dummy circuit 010 .
  • the plurality of electrostatic discharge dummy circuits 007 can be connected to the second test dummy circuit 012 through a plurality of data transmission dummy lines 008, and the second test dummy circuit 012 can be connected to the first test dummy circuit through a plurality of data transmission dummy lines 008 010 Electrical connection.
  • FIG. 28 is a schematic structural diagram of an electrostatic discharge circuit provided by an embodiment of the present application, a first test circuit and a second test circuit.
  • the second test circuit 011 may be located between the electrostatic discharge circuit 005 and the first test circuit 009 .
  • the plurality of electrostatic discharge circuits 005 can be electrically connected to the second test circuit 011 through a plurality of data transmission lines 004
  • the second test circuit 011 can be electrically connected to the first test circuit 009 through a plurality of data transmission lines 004 .
  • the display substrate 00 may further include: a buffer layer 018, an active layer 019, a first gate insulating layer 020, a second gate insulating layer 021, an interlayer dielectric layer 022, a source-drain layer Polar layer 023, passivation layer 024, flat layer 025, anode layer 026, light emitting layer 027, cathode layer 028, pixel definition layer 029, support layer 030, first inorganic encapsulation layer 031, organic encapsulation layer 032, and second inorganic Encapsulation layer 033.
  • the buffer layer 018 may be located on one side of the base substrate 001, the active layer 019 may be located on the side of the buffer layer 018 away from the base substrate 001, and the first gate insulating layer 020 may be located at the active layer 019 away from the buffer
  • the gate layer may be located on the side of the first gate layer away from the active layer 019
  • the second gate insulating layer 021 may be located on the side of the gate layer away from the first gate insulating layer 020
  • the layer The interlayer dielectric layer 022 can be located on the side of the second gate insulating layer 021 away from the gate layer
  • the source and drain layers 023 can be located on the side of the interlayer dielectric layer 022 away from the second gate insulating layer 021
  • the passivation layer 024 can be located on the side of the source and drain layers 023 away from the interlayer dielectric layer 022
  • the flat layer 025 can be located on the side of the passivation layer 024 away from the source and drain layers, and the an
  • the second inorganic encapsulation layer 033 may be located on the side of the organic encapsulation layer 032 away from the first inorganic encapsulation layer 031 .
  • an embodiment of the present application provides a display substrate, which includes: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data transmission lines, a plurality of electrostatic discharge circuits, and a panel crack detection line , and a plurality of electrostatic discharge dummy circuits, wherein at least one electrostatic discharge dummy circuit in the plurality of electrostatic discharge dummy circuits can be connected to a panel crack detection trace.
  • the solution provided by the embodiments of the present application can release the static electricity accumulated on the panel crack detection trace through the electrostatic discharge dummy circuit, so as to avoid other traces in the display substrate from being blown off due to the static electricity accumulated on the panel crack detection trace, thereby improving the display performance. substrate yield.
  • Embodiments of the present application further provide a display device, and the display device may include the display substrate described in the above embodiments.
  • the display device can be a liquid crystal display device, electronic paper, an organic light-emitting diode (organic light-emitting diode, OLED) display device, an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED) display.
  • OLED organic light-emitting diode
  • AMOLED active-matrix organic light-emitting diode
  • Any product or component that has a display function such as a device, mobile phone, tablet, TV, monitor, laptop, digital photo frame or navigator.

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Abstract

一种显示基板（00）及显示装置。显示基板（00）包括：显示基板（00）包括：衬底基板（001），多个子像素（002），多条数据线（003），多条数据传输线（004），多个静电释放电路（005），面板裂纹检测走线（006），以及多个静电释放虚设电路（007），其中多个静电释放虚设电路（007）中的至少一个静电释放虚设电路（007）可以与面板裂纹检测走线（006）连接。通过静电释放虚设电路（007）释放面板裂纹检测走线（006）上积累的静电，避免显示基板（00）中的其他走线由于面板裂纹检测走线（006）上积累的静电而被烧断，提高了显示基板（00）的良率。

Description

显示基板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示基板及显示装置。
背景技术
在显示基板的制造过程中，显示基板的边缘可能会出现难以观察到的微小裂纹，影响显示基板的质量。
发明内容
本申请提供了一种显示基板及显示装置，所述技术方案如下：
一方面，提供了一种显示基板，所述显示基板包括：
衬底基板，所述衬底基板具有显示区域，以及围绕所述显示区域的周边区域；
多个子像素，位于所述显示区域；
多条数据线，位于所述显示区域且与所述多个子像素电连接；
多条数据传输线，位于所述周边区域，且与所述多条数据线电连接；
多个静电释放电路，位于所述周边区域，且与所述多条数据传输线电连接，所述多个静电释放电路沿所述显示区域的边界的延伸方向排布；
面板裂纹检测走线，位于所述周边区域且环绕所述显示区域；
多个静电释放虚设电路，位于所述周边区域，沿所述显示区域的边界的延伸方向排布，所述多个静电释放虚设电路在沿所述显示区域边界的延伸方向上位于所述多个静电释放电路的至少一侧，所述多个静电释放虚设电路中的至少一个静电释放虚设电路与所述面板裂纹检测走线电连接，用于释放所述面板裂纹检测走线上的静电。
可选的，所述显示区域的边界包括依次连接的第一边界，第二边界，第三边界以及第四边界，所述多个静电释放电路和所述多个静电释放虚设电路位于靠近所述第一边界的所述周边区域；
所述多个静电释放虚设电路包括多个第一静电释放虚设子电路和多个第二静电释放虚设子电路；
在沿所述第一边界的延伸方向上，所述多个第一静电释放虚设子电路和所述多个第二静电释放虚设子电路分别位于所述多个静电释放电路的两侧。
可选的，所述面板裂纹检测走线包括：第一走线段，第二走线段以及第三走线段；
所述第一走线段为不连续走线，位于靠近所述显示区域的第一边界的所述周边区域，所述第一走线段沿所述第一边界的延伸方向延伸；
所述第二走线段为连续走线，位于靠近所述第一边界，所述第二边界以及所述第三边界的所述周边区域，所述第二走线段的两个端点位于靠近所述第一边界的所述周边区域；
所述第三走线段为连续走线，位于靠近所述第三边界，所述第四边界以及所述第一边界的所述周边区域，所述第三走线段的两个端点位于靠近所述第一边界的所述周边区域，所述第二走线段和所述第三走线段分别与所述第一走线段连接；
其中，所述多个静电释放虚设电路与所述第一走线段电连接。
可选的，所述第一走线段包括：沿所述第一边界的延伸方向延伸的第一子走线，第二子走线以及第三子走线，所述第一子走线和所述第二子走线位于所述第三子走线靠近所述显示区域的一侧；
所述第一子走线和所述第三子走线分别与所述第二走线段的两个端点连接，所述第二子走线和所述第三子走线分别与所述第三走线段的两个端点连接；
所述多个静电释放虚设电路与所述第三子走线电连接。
可选的，所述显示基板还包括：多条数据传输虚设线，所述多个静电释放虚设电路通过所述多条数据传输虚设线与所述第三子走线电连接。
可选的，所述显示基板还包括：多个第一测试电路，位于所述多个静电释放电路远离所述显示区域的一侧，且所述多个第一测试电路沿所述第一边界的延伸方向延伸排布；
所述多个第一测试电路中的至少一个所述第一测试电路包括：第一薄膜晶体管，第一控制线，第一测试数据线和第二测试数据线，所述第一控制线，所述第一测试数据线和所述第二测试数据线位于所述周边区域且沿所述第一边界的延伸方向延伸；
所述第一薄膜晶体管包括：第一源极，第一漏极和第一栅极，所述第一栅极与所述第一控制线电连接，所述第一源极与所述第一测试数据线，第二测试 数据线，所述第一子走线以及所述第二子走线中的一条线电连接，所述第一漏极与所述多条数据传输线中的一条电连接。
可选的，所述显示基板还包括：多个第一测试虚设电路，所述多个第一测试虚设电路在沿所述第一边界的延伸方向上，位于所述多个第一测试电路的两侧且位于所述多个静电释放虚设电路和所述第三子走线之间，所述多个第一测试虚设电路通过所述多条数据传输虚设线与所述第三子走线以及所述静电释放虚设电路电连接。
可选的，所述多个第一测试虚设电路中的至少一个所述第一测试虚设电路包括：第一虚设薄膜晶体管以及第二控制线，所述第二控制线位于所述周边区域且沿所述第一边界的延伸方向延伸，所述第一虚设薄膜晶体管包括：第一虚设源极，第一虚设漏极以及第一虚设栅极；
所述第一虚设栅极与所述第二控制线电连接，所述第一虚设漏极与所述多条数据传输虚设线中的一条电连接。
可选的，所述静电释放虚设电路的数量与所述第一测试虚设电路的数量相同，每个所述静电释放虚设电路通过一个所述第一测试虚设电路与所述第三子走线电连接。
可选的，所述显示基板还包括：多个第二测试电路，所述多个第二测试电路位于所述多个静电释放电路和所述多个第一测试电路之间，且所述多个第二测试电路通过所述多条数据传输线与所述多个静电释放电路以及所述多个第一测试电路电连接。
可选的，所述多个第二测试电路中的至少一个所述第二测试电路包括：第一子电路，第二子电路和第三子电路，所述第二子电路位于所述第一子电路与所述第三子电路之间，所述第一子电路位于所述第二子电路远离所述多个子像素的一侧。
可选的，所述多条数据传输线包括：多条第一数据传输线和多条第二数据传输线，所述多条第一数据传输线和所述多条第二数据传输线一一交替排布；
所述第一子电路包括：第二薄膜晶体管，第三控制线，以及第三测试数据线，所述第三控制线和所述第三测试数据线沿所述第一边界的延伸方向延伸；
所述第二薄膜晶体管包括：第二源极，第二漏极和第二栅极，所述第二源极与所述第三测试数据线电连接，所述第二漏极与所述多条第一数据传输线中的一条电连接，所述第二栅极与所述第三控制线电连接。
可选的，所述第二子电路包括：第三薄膜晶体管，第四薄膜晶体管，第四控制线，第四测试数据线，以及第五测试数据线，所述第三控制线，所述第四测试数据线，以及所述第五测试数据线沿所述第一边界的延伸方向延伸；
所述第三薄膜晶体管包括：第三源极，第三漏极和第三栅极，所述第三源极与所述第四测试数据线电连接，所述第三漏极与所述多条第二数据传输线中的一条电连接，所述第三栅极与所述第四控制线电连接；
所述第四薄膜晶体管包括：第四源极，第四漏极和第四栅极，所述第四源极与所述第五测试数据线电连接，所述第四漏极与所述多条第二数据传输线中的一条电连接，所述第四栅极与所述第四控制线电连接。
可选的，所述第三子电路包括：第五薄膜晶体管，第六薄膜晶体管，第五控制线，第六测试数据线，以及第七测试数据线；所述第五控制线，所述第六测试数据线和所述第七测试数据线沿所述第一边界的延伸方向延伸；
所述第五薄膜晶体管包括：第五源极，第五漏极和第五栅极，所述第五源极与所述第六测试数据线电连接，所述第五漏极与所述多条第二数据传输线中的一条电连接，所述第五栅极与所述第五控制线电连接；
所述第六薄膜晶体管包括：第六源极，第六漏极和第六栅极，所述第六源极与所述第七测试数据线电连接，所述第六漏极与所述多条第二数据传输线中的一条电连接，所述第六栅极与所述第五控制线电连接。
可选的，所述显示基板还包括：多个第二测试虚设电路，所述多个第二测试虚设电路在沿所述第一边界的延伸方向上，位于所述多个第二测试电路的两侧且位于多个静电释放虚设电路和所述多个第一测试虚设电路之间，所述多个第二测试虚设电路通过所述多条数据传输虚设线与所述第一测试虚设电路以及所述静电释放虚设电路电连接。
可选的，所述多个第二测试虚设电路中的至少一个所述第二测试虚设电路包括：第一虚设子电路，第二虚设子电路和第三虚设子电路，所述第二虚设子电路位于所述第一虚设子电路与所述第三虚设子电路之间，所述第一虚设子电路位于所述第二虚设子电路远离所述多个子像素的一侧。
可选的，所述多条数据传输虚设线包括：多条第一数据传输虚设线和多条第二数据传输虚设线，所述多条第一数据传输虚设线和所述多条第二数据传输虚设线一一交替排布；
所述第一虚设子电路包括：第二虚设薄膜晶体管，第六控制线，以及第八 测试数据线，所述第六控制线和所述第八测试数据线沿所述第一边界的延伸方向延伸，所述第二虚设薄膜晶体管包括：第二虚设源极，第二虚设漏极和第二虚设栅极，所述第二虚设漏极与所述多条第一数据传输虚设线中的一条电连接，所述第二虚设栅极与所述第六控制线电连接。
可选的，所述第二虚设子电路包括：第三虚设薄膜晶体管，第四虚设薄膜晶体管，第七控制线，第九测试数据线，以及第十测试数据线，所述第七控制线，所述第九测试数据线，以及所述第十测试数据线沿所述第一边界的延伸方向延伸；
所述第三虚设薄膜晶体管包括：第三虚设源极，第三虚设漏极和第三虚设栅极，所述第三虚设漏极与所述多条第二数据传输虚设线中的一条电连接，所述第三虚设栅极与所述第七控制线电连接；
所述第四虚设薄膜晶体管包括：第四虚设源极，第四虚设漏极和第四虚设栅极，所述第四虚设漏极与所述多条第二数据传输线中的一条电连接，所述第四虚设栅极与所述第七控制线电连接。
可选的，所述第三虚设子电路包括：第五虚设薄膜晶体管，第六虚设薄膜晶体管，第八控制线，第十一测试数据线，以及第十二测试数据线；所述第八控制线，所述第十一测试数据线和所述第十二测试数据线沿所述第一边界的延伸方向延伸；
所述第五虚设薄膜晶体管包括：第五虚设源极，第五虚设漏极和第五虚设栅极，所述第五虚设漏极与所述多条第二数据传输线中的一条电连接，所述第五虚设栅极与所述第八控制线电连接；
所述第六虚设薄膜晶体管包括：第六虚设源极，第六虚设漏极和第六虚设栅极，所述第六虚设漏极与所述多条第二数据传输线中的一条电连接，所述第六虚设栅极与所述第八控制线电连接。
可选的，所述第二测试虚设电路的数量与所述静电释放虚设电路的数量以及所述第一测试虚设电路的数量相同，每个所述静电释放虚设电路通过一个所述第二测试虚设电路与一个所述第一测试虚设电路电连接。
可选的，所述显示基板还包括：至少一个第一信号输入端；
所述至少一个第一信号输入端与所述面板裂纹检测走线中第一走线段中的第三子走线连接，所述至少一个第一信号输入端被配置为接收测试信号，以对所述显示基板进行检测。
可选的，所述至少一个第一信号输入端包括两个第一信号输入端，所述两个第一信号输入端分别位于所述第一测试电路的两侧。
可选的，所述显示基板还包括：第一检测端和第二检测端；
所述第一检测端与所述面板裂纹检测走线中第一走线段中的第一子走线连接，用于为所述第一子走线提供检测信号；
所述第二检测端与所述面板裂纹检测走线中第一走线段中的第二子走线连接，用于接收所述检测信号，以对所述显示基板进行检测。
可选的，所述多个静电释放虚设电路中的至少一个所述静电释放虚设电路包括：静电防护线，至少一个第一放电晶体管，以及至少一个第二放电晶体管；
所述至少一个第一放电晶体管的第一极和栅极均与所述面板裂纹检测走线电连接，所述至少一个第一放电晶体管的第二极与所述静电防护线电连接；
所述至少一个第二放电晶体管的第一极和栅极均与所述静电防护线电连接，所述至少一个第二放电晶体管的第二极与所述面板裂纹检测走线电连接。
可选的，所述多个静电释放虚设电路沿所述显示区域的边界均匀分布在所述周边区域。
另一方面，提供了一种显示装置，所述显示装置包括：如上述方面所述的显示基板。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示基板的结构示意图；
图2是本申请实施例提供的另一种显示基板的结构示意图；
图3是本申请实施例提供的又一种显示基板的结构示意图；
图4是本申请实施例提供的再一种显示基板的结构示意图；
图5是本申请实施例提供的再一种显示基板的结构示意图；
图6是本申请实施例提供的一种第一测试电路的结构示意图；
图7是图5所示的显示基板的局部示意图；
图8是本申请实施例提供的一种第一测试虚设电路的结构示意图；
图9是本申请实施例提供的另一种第一测试虚设电路的示意图；
图10是本申请实施例提供的再一种显示基板的结构示意图；
图11是本申请实施例提供的一种第二测试电路的结构示意图；
图12是本申请实施例提供的一种显示基板的截面图；
图13是本申请实施例提供的一种第二测试虚设电路的结构示意图；
图14是本申请实施例提供的再一种显示基板的结构示意图；
图15是本申请实施例提供的一种检测面板裂纹检测走线的电路图；
图16是本申请实施例提供的再一种显示基板的结构示意图；
图17是本申请实施例提供的一种静电释放虚设电路的电路图；
图18是本申请实施例提供的另一种静电释放虚设电路的电路图；
图19是本申请实施例提供的一种静电释放虚设电路释放负电荷的原理图；
图20是本申请实施例提供的一种静电释放虚设电路释放正电荷的原理图；
图21是本申请实施例提供的一种静电释放虚设电路的结构示意图；
图22是本申请实施例提供的一种静电释放虚设电路的电路图；
图23是本申请实施例提供的另一种静电释放电路的电路图；
图24是本申请实施例提供的一种静电释放电路释放负电荷的原理图；
图25是本申请实施例提供的一种静电释放电路释放正电荷的原理图；
图26是本申请实施例提供的一种静电释放电路的结构示意图；
图27是本申请实施例提供的一种静电释放虚设电路，第一测试虚设电路，以及第二测试虚设电路的结构示意图；
图28是本申请实施例提供的一种静电释放电路，第一测试电路，以及第二测试电路的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，为了检测显示基板的边缘是否存在裂纹，通常在显示基板的衬底基板001的边缘区域设置面板裂纹检测(panel crack detection，PCD)走线。该PCD走线为环绕衬底基板的显示区域的环状走线。该PCD走线的一端和另一端均与检测电路连接以形成回路。该检测电路用于向该PCD的一端输入检测信号，并可以检测是否能够从该PCD走线的另一端接收到该检测信号。
但是，由于该PCD走线需环绕衬底基板001的显示区域，因此该PCD走线的长度较长，导致在显示基板的制造过程中，该PCD走线上容易积累静电，该积累的静电容易导致该显示基板中的其他走线被烧断，显示基板的良率较低。
图1是本申请实施例提供的一种显示基板的结构示意图。参考图1可以看出，该显示基板00可以包括：衬底基板001，多个子像素002，多条数据线003，多条数据传输线004，多个静电释放(electro-static discharge，ESD)电路005，面板裂纹检测走线006，以及多个静电释放虚设电路007。示例的，图1中示出了6个子像素002，3条数据线003，3条数据传输线004，3个静电释放电路005，以及2个静电释放虚设电路007。其中，该衬底基板001可以具有显示区域001a，以及围绕该显示区域001a的周边区域001b。
参考图1，该多个子像素002可以位于显示区域001a，多条数据线003可以位于该显示区域001a且与多个子像素002电连接。例如，每条数据线003可以与多个子像素002中一列子像素002电连接。
该多条数据传输线004可以位于周边区域001b，且与多条数据线003电连接。例如，每条数据传输线004可以与一条数据线003电连接。
该多个静电释放电路005可以位于周边区域001b，该多个静电释放电路005可以与多条数据传输线004电连接，且该多个静电释放电路005可以沿显示区域001a的边界的延伸方向排布。也即是，该静电释放电路005可以通过数据传输线004与数据线003电连接，可以用于释放数据线003上的静电。
该面板裂纹检测走线006可以位于周边区域001b且环绕显示区域001a。也即是，该面板裂纹检测走线006可以为环绕显示区域001a的环状走线。
该多个静电释放虚设电路007可以位于周边区域001b，沿显示区域001a的边界的延伸方向排布，该多个静电释放虚设电路007在沿显示区域001a边界的延伸方向上位于多个静电释放电路005的至少一侧，该多个静电释放虚设电路007中的至少一个静电释放虚设电路007与面板裂纹检测走线006连接，可以用于释放面板裂纹检测走线006上的静电。
需要说明的是，在显示基板00的制造过程中，需在衬底基板001的周边区域001b制造静电释放电路005，该静电释放电路005与显示基板00中的数据传输线004电连接，该数据传输线004与数据线003电连接，该静电释放电路005可以用于释放数据线003中的静电。由于在制造静电释放电路005时，为了保证与数据传输线004电连接的静电释放电路005的制造精度，可以在该衬底基 板001上制造不与数据传输线004电连接的静电释放电路005，即静电释放虚设电路007。在本申请实施例中，显示基板中设置的静电释放虚设电路007可以与面板裂纹检测走线006连接，由此可以释放该面板裂纹检测走线006中的静电。
综上所述，本申请实施例提供了一种显示基板，该显示基板包括：衬底基板，多个子像素，多条数据线，多条数据传输线，多个静电释放电路，面板裂纹检测走线，以及多个静电释放虚设电路，其中多个静电释放虚设电路中的至少一个静电释放虚设电路可以与面板裂纹检测走线连接。本申请实施例提供的方案可以通过静电释放虚设电路释放面板裂纹检测走线上积累的静电，避免显示基板中的其他走线由于面板裂纹检测走线上积累的静电而被烧断，提高了显示基板的良率。
图2是本申请实施例提供的另一种显示基板的结构示意图。参考图2可以看出，显示区域001a的边界可以包括依次连接的第一边界001a1，第二边界001a2，第三边界001a3以及第四边界001a4。其中多个静电释放电路005和多个静电释放虚设电路007可以位于靠近第一边界001a1的周边区域001b1。
参考图2，该多个静电释放虚设电路007可以包括多个第一静电释放虚设子电路0071和多个第二静电释放虚设子电路0072，例如图2中示出了两个第一静电释放虚设子电路0071和两个第二静电释放虚设子电路0072。
在沿第一边界001a1的延伸方向X上，多个第一静电释放虚设子电路0071和多个第二静电释放虚设子电路0072可以分别位于多个静电释放电路005的两侧。也即是，在多个静电释放电路005的两侧均设置有静电释放虚设电路007，由此可以将多个第一静电释放虚设电路007中至少一个第一静电释放虚设电路007与面板裂纹检测走线006连接，并将多个第二静电释放虚设电路007中至少一个第二静电释放虚设电路007与面板裂纹检测走线006连接，而该第一静电释放虚设电路0071和第二静电释放虚设电路0072分别位于多个静电释放电路005的两侧，因此该第一静电释放虚设电路0071和第二静电释放虚设电路0072可以分别释放面板裂纹检测走线006中不同区域的静电，静电释放的可靠性较好，显示基板的良率较高。
需要说明的是，由于在显示基板00的制造过程中，该面板裂纹检测走线006位于靠近第一边界001a1的周边区域001b1的部分相对于其他区域更容易积累静电。因此将该静电释放虚设电路007设置在靠近第一边界001a1的周边区域001b1，可以便于释放该面板裂纹检测走线006位于靠近第一边界001a1的周边 区域001b1的部分的静电。避免由于该面板裂纹检测走线006中积累的静电较多导致显示基板中的其他走线被烧断，保证显示基板00的良率。
图3是本申请实施例提供的又一种显示基板的结构示意图。参考图3还可以看出，该面板裂纹检测走线006包括：第一走线段0061，第二走线段0062以及第三走线段0063。
该第一走线段0061为不连续走线，该第一走线段0061位于靠近显示区域001a的第一边界001a1的周边区域001b，且该第一走线段0061沿第一边界001a1的延伸方向X延伸。
第二走线段0062为连续走线，该第二走线段0062位于靠近第一边界001a1，第二边界001a2以及第三边界001a3的周边区域001b，且该第二走线段0062的两个端点0062a和0062b位于靠近第一边界001a1的周边区域001b1，该第二走线段0062与第一走线段0061连接。
第三走线段0063为连续走线，该第三走线段0063位于靠近第三边界001a3，第四边界001a4以及第一边界001a1的周边区域001b，且该第三走线段0063的两个端点0063a和0063b位于靠近第一边界001a1的周边区域001b1，该第三走线段0063与第一走线段0061连接。
其中，该多个静电释放虚设电路007与第一走线段0061电连接，从而释放第一走线段0061，以及与该第一走线段0061连接的第二走线段0062以及第三走线段0063中的静电。
参考图3还可以看出，该第一走线段0061可以包括：沿第一边界001a1的延伸方向X延伸的第一子走线00611，第二子走线00612以及第三子走线00613。该第一子走线00611和第二子走线00612位于第三子走线00613靠近显示区域001a的一侧。
其中，参考图3，该第一子走线00611的第一端00611a可以与第二走线段0062的第一端0062a连接，第三子走线00613的第一端00613a可以与第二走线段0062的第二端0062b连接，第二子走线00612的第一端00612a可以与第三走线段0063的第一端0063a连接，第三子走线00613的第二端00613b可以与第三走线段0063的第二端0063b连接。并且，该第一子走线00611的第二端00611b和第二子走线00612的第二端00612b具有间隙。多个静电释放虚设电路007可以与第三子走线00613连接。
需要说明的是，该第一走线段0061，第二走线段0062，以及第三走线段0063 可以采用同一次构图工艺制备得到，也可以采用不同的构图工艺制备得到，本申请实施例对此不作限定。图3中采用不同粗细的线条示意第一走线段0061，第二走线段0062，以及第三走线段0063，只是为了区分各个走线段，并不表示各个走线段的实际线宽。在本申请实施例中，第一走线段0061，第二走线段0062，以及第三走线段0063的线宽可以相同。
图4是本申请实施例提供的再一种显示基板的结构示意图。参考图4，显示基板00还可以包括：多条数据传输虚设线008，多个静电释放虚设电路007通过多条数据传输虚设线008与第三子走线00613连接，由此实现静电释放虚设电路007与第三子走线00613的连接，从而释放静电。示例的，多个静电释放虚设电路007中的每个静电释放虚设电路007可以通过一条数据传输虚设线008与第三子走线00613连接。
参考图4可以看出，该显示基板00还可以包括：多个第一测试电路009，例如，图4中示出了三个第一测试电路009。该多个第一测试电路009可以位于多个静电释放电路005远离显示区域001a的一侧，且多个第一测试电路009可以沿第一边界001a1的延伸方向X延伸排布。
图5是本申请实施例提供的再一种显示基板的结构示意图。图6是本申请实施例提供的一种第一测试电路的结构示意图。结合图5和图6可以看出，该第一测试电路009可以包括：第一薄膜晶体管0091，第一控制线0092，第一测试数据线0093和第二测试数据线0094。该第一控制线0092，第一测试数据线0093和第二测试数据线0094可以位于周边区域001b且沿第一边界001a1的延伸方向X延伸。
图7是图5所示的显示基板的局部示意图。结合图6和图7，该第一薄膜晶体管0091可以包括：第一源极00911，第一漏极00912和第一栅极00913。该第一栅极00913可以与第一控制线0092电连接，第一源极00911可以与第一测试数据线0093，第二测试数据线0094，第一子走线00611以及第二子走线00612中的一条线电连接，第一漏极00912可以与多条数据传输线004中的一条电连接。其中，图7中的第一源极00911可以与第二子走线00612电连接。
其中，该第一控制线0092可以为第一薄膜晶体管0091的第一栅极00913提供栅极驱动信号。其中，该栅极驱动信号还可以称为面板检测开关(cell test switch，CTS)信号。若该第一薄膜晶体管0091为用于驱动红色(red，R)子像素或蓝色(blue，B)子像素发光的薄膜晶体管，则该第一薄膜晶体管0091的漏 极可以与第一测试数据线0093电连接，该第一测试数据线0093用于为红色子像素以及蓝色子像素提供数据信号。若该第一薄膜晶体管0091为用于驱动绿色(green，G)子像素发光的薄膜晶体管，则该第一薄膜晶体管0091的第一漏极00912可以与第二测试数据线0094，第一子走线00611以及第二子走线00612中的一条电连接，该第二测试数据线0094，第一子走线00611，或者第二子走线00612用于为绿色子像素提供数据信号。
需要说明的是，该背板测试过程中，第二测试数据线0094提供给绿色子像素的第一薄膜晶体管0091的驱动信号，与该第一测试数据线0093提供给红色子像素的第一薄膜晶体管0091或蓝色子像素的第一薄膜晶体管0091的驱动信号相同。
需要说明的是，在显示基板的制造过程中，需在衬底基板001靠近第一边界001a1的周边区域001b1制造第一测试电路009，该第一测试电路009与显示基板00中的子像素002电连接，用于检测子像素002的发光性能。由于在制造第一测试电路009时，为了保证与子像素002电连接的第一测试电路009的制造精度，可以在该衬底基板001上制造不与子像素002电连接的测试电路，即第一测试虚设电路010。在本申请实施例中，显示基板00中设置的静电释放虚设电路007可以通过该第一测试虚设电路010与面板裂纹检测走线006连接，可以优化背板的走线和电路排布。
图8是本申请实施例提供的一种第一测试虚设电路的示意图。结合图5和图8可以看出，该显示基板00还可以包括：多个第一测试虚设电路010，该多个第一测试虚设电路010在沿第一边界001a1的延伸方向X上，位于多个第一测试电路009的两侧且位于多个静电释放虚设电路007和第三子走线00613之间。该多个第一测试虚设电路010通过多条数据传输虚设线008与第三子走线00613以及静电释放虚设电路007电连接。也即是，该静电释放虚设电路007可以通过该第一测试虚设电路010与第三子走线00613连接，从而释放静电。
图9本申请实施例提供的另一种第一测试虚设电路的示意图。参考图9可以看出，该第一测试虚设电路010中的至少一个第一测试虚设电路010可以包括：第一虚设薄膜晶体管0101，以及第二控制线0102。该第二控制线0102位于周边区域001b且沿第一边界001a1的延伸方向X延伸。
其中，该第一虚设薄膜晶体管0101可以包括：第一虚设源极01011，第一虚设漏极01012以及第一虚设栅极01013。该第一虚设栅极01013可以与第二控 制线0102电连接，该第二控制线0102可以为第一虚设栅极01013提供栅极驱动信号。第一虚设漏极01012可以与多条数据传输虚设线008中的一条电连接。
在本申请实施例中，第一控制线0092可以与第二控制线0102电连接，也即是，该第一控制线0092和第二控制线0102可以为同一条控制线，该第一控制线0092提供给第一薄膜晶体管0091的第一栅极00913的栅极驱动信号，可以与第二控制线0102提供给第一虚设薄膜晶体管0101的第一虚设栅极01013的栅极驱动信号相同。
在本申请实施例中，静电释放虚设电路007的数量可以与第一测试虚设电路010的数量相同，每个静电释放虚设电路007可以通过一个第一测试虚设电路010与第三子走线00613电连接。
示例的，并且图5示出了两个静电释放虚设电路007，且分别位于静电释放电路005的两侧。其中每个静电释放虚设电路007可以与位于同一侧的第一测试虚设电路010电连接。
或者，静电释放虚设电路007的数量可以小于第一测试虚设电路010的数量。例如，每个静电释放虚设电路007与对应的一个第一测试虚设电路010电连接，未与静电释放虚设电路007电连接的第一测试电路009仍为独立的电路。
又或者，静电释放虚设电路007的数量可以大于第一测试虚设电路010的数量。例如，多个静电释放虚设电路007中的至少两个静电释放虚设电路007与同一个第一测试虚设电路010电连接。
图10是本申请实施例提供的再一种显示基板的结构示意图。参考图10可以看出，该显示基板00还可以包括：多个第二测试电路011，该多个第二测试电路011可以位于多个静电释放电路005和多个第一测试电路009之间，且该多个第二测试电路011可以通过多条数据传输线004与多个静电释放电路005以及多个第一测试电路009电连接。
图11是本申请实施例提供的一种第二测试电路的示意图。参考图11，该多个第二测试电路011中的至少一个第二测试电路011可以包括：第一子电路0111，第二子电路0112和第三子电路0113。并且，该第二子电路0112可以位于第一子电路0111与第三子电路0113之间，该第一子电路0111位于第二子电路0112远离多个子像素002的一侧，第三子电路0113位于第二子电路0112靠近多个子像素002的一侧。
参考图11，该多条数据传输线004可以包括：多条第一数据传输线0041和 多条第二数据传输线0042，该多条第一数据传输线0041和多条第二数据传输线0042一一交替排布，例如图11中示出了三条第一数据传输线0041和三条第二数据传输线0042。该第一子电路0111可以包括：第二薄膜晶体管01111，第三控制线01112以及第三测试数据线01113，该第三控制线01112和第三测试数据线01113可以沿第一边界001a1的延伸方向X延伸。
其中，参考图12，该多条第一数据传输线0041可以与薄膜晶体管中的第一层栅极G同层设置，多条第二数据传输线0042可以与第二层栅极同层设置。也即是，该第一数据传输线0041可以与第一层栅极G采用一次构图工艺形成，第二数据传输线0042可以与第二层栅极采用一次构图工艺形成。
其中，参考图11，该第二薄膜晶体管01111可以包括：第二源极011111，第二漏极011112和第二栅极011113，该第二源极011111可以与第三测试数据线01113电连接，第二漏极011112可以与多条第一数据传输线0041中的一条电连接，第二栅极011113可以与第三控制线01112电连接。该第三测试数据线01113可以为第二源极011111提供数据信号，第三控制线01112可以为第二栅极011113提供栅极驱动信号。
可选的，第一数据传输线0041可以与显示区域001a中用于为绿色子像素002提供驱动信号的数据线003电连接。
参考图11还可以看出，该第二子电路0112可以包括：第三薄膜晶体管01121，第四薄膜晶体管01122，第四控制线01123，第四测试数据线01124，以及第五测试数据线01125。该第四控制线01123，第四测试数据线01124，以及第五测试数据线01125沿第一边界001a1的延伸方向X延伸。
其中，该第三薄膜晶体管01121可以包括：第三源极011211，第三漏极011212和第三栅极011213，该第三源极011211可以与第四测试数据线01124电连接，第三漏极011212可以与多条第二数据传输线0042中的一条电连接，第三栅极011213可以与第四控制线01123电连接。该第四测试数据线01124可以为第三源极011211提供数据信号，第四控制线01123可以为第三栅极011213提供栅极驱动信号。
该第四薄膜晶体管01122可以包括：第四源极011221，第四漏极011222和第四栅极011223，该第四源极011221可以与第五测试数据线01125电连接，第四漏极011222可以与多条第二数据传输线0042中的一条电连接，第四栅极011223可以与第四控制线01123电连接。该第五测试数据线01125可以为第四 源极011221提供数据信号，第四控制线01123还可以为第四栅极011223提供栅极驱动信号。也即是，该第三薄膜晶体管01121和第四薄膜晶体管01122可以共用一条控制线。
可选的，该第二数据传输线0042可以与显示区域001a中为红色子像素002或蓝色子像素002提供驱动信号的数据线003电连接。
参考图11，该第三子电路0113可以包括：第五薄膜晶体管01131，第六薄膜晶体管01132，第五控制线01133，第六测试数据线01134，以及第七测试数据线01135。该第六测试数据线01134和第七测试数据线01135可以沿第一边界001a1的延伸方向X延伸。
其中，第五薄膜晶体管01131可以包括：第五源极011311，第五漏极011312和第五栅极011313。该第五源极011311可以与第六测试数据线01134电连接，第五漏极011312可以与多条第二数据传输线0042中的一条电连接，第五栅极011313可以与第五控制线01133电连接。该第六测试数据线01134可以为第五源极011311提供数据信号，第五控制线01133可以为第五栅极011313提供栅极驱动信号。
该第六薄膜晶体管01132可以包括：第六源极011321，第六漏极011322和第六栅极011323，该第六源极011321可以与第七测试数据线01135电连接，第六漏极011322可以与多条第二数据传输线0042中的一条电连接，第六栅极011323可以与第五控制线01133电连接。该第七测试数据线01135可以为第六源极011321提供数据信号，该第五控制线01133还可以为第六栅极011323提供栅极驱动信号。也即是，该第五薄膜晶体管01131和第六薄膜晶体管01132可以共用一条控制线。
在本申请实施例中，参考图11，第四控制线01123和第五控制线01131相邻设置，该第四控制线01123和第五控制线01131可以为一条控制线。由此，第三薄膜晶体管01121，第四薄膜晶体管01122，第五薄膜晶体管01131以及第六薄膜晶体管01132可以共用一条控制线。
参考图10还可以看出，该显示基板00还可以包括：多个第二测试虚设电路012。该多个第二测试虚设电路012在沿第一边界001a1的延伸方向X上，位于多个第二测试电路011的两侧且位于多个静电释放虚设电路007和多个第一测试虚设电路010之间。该多个第二测试虚设电路012可以通过多条数据传输虚设线008与第一测试虚设电路010以及静电释放虚设电路007电连接。
图13是本申请实施例提供的一种第二测试虚设电路的示意图。参考图13，多个第二测试虚设电路012中至少一个第二测试虚设电路012可以包括：第一虚设子电路0121，第二虚设子电路0122和第三虚设子电路0123。该第二虚设子电路0122可以位于第一虚设子电路0121与第三虚设子电路0123之间，第一虚设子电路0121位于第二虚设子电路0122远离多个子像素002的一侧，第三虚设子电路0123位于第二虚设子电路0122靠近多个子像素002的一侧。
参考图13，该多条数据传输虚设线008可以包括：多条第一数据传输虚设线0081和多条第二数据传输虚设线0082。该多个第一数据传输虚设线0081和多条第二数据传输虚设线0082一一交替排布。该第一虚设子电路0121可以包括：第二虚设薄膜晶体管01211，第六控制线01212，以及第八测试数据线01213。第六控制线01212可以与第八测试数据线01213沿第一边界001a1的延伸方向X延伸。
其中，参考图13，该第二虚设薄膜晶体管01211可以包括：第二虚设源极012111，第二虚设漏极012112和第二虚设栅极012113。第二虚设漏极012112与多条第一数据传输虚设线0081中的一条电连接，第二虚设栅极012113可以与第六控制线01212电连接。也即是，第六控制线01212可以为第二虚设栅极012113提供栅极驱动信号。
在本申请实施例中，第一数据传输虚设线0081不与显示区域001a中的数据线003连接，而与第三子走线00613连接。
参考图13，该第二虚设子电路0122可以包括：第三虚设薄膜晶体管01221，第四虚设薄膜晶体管01222，第七控制线01223，第九测试数据线01224，以及第十测试数据线01225。第七控制线01223，第九测试数据线01224，以及第十测试数据线01225沿第一边界001a1的延伸方向X延伸。
该第三虚设薄膜晶体管01221可以包括：第三虚设源极012211，第三虚设漏极012212和第三虚设栅极012213，第三虚设漏极012212与多条第二数据传输虚设线0082中的一条电连接，第三虚设栅极012213与第七控制线01223电连接。第七控制线01223可以为第三虚设栅极012213提供栅极驱动信号。
该第四虚设薄膜晶体管01222可以包括：第四虚设源极012221，第四虚设漏极012222和第四虚设栅极012223。第四虚设漏极012222可以与多条第二数据传输线0042中的一条电连接，第四虚设栅极012223可以与第七控制线01223电连接。第七控制线01223可以为第四虚设栅极012223提供栅极驱动信号。也 即是，该第三虚设薄膜晶体管01221和第四虚设薄膜晶体管01222可以共用一条控制线。
在本申请实施例中，该第二数据传输虚设线0082不与显示区域001a中的数据线003连接，而与第三子走线00613连接。
参考图13还可以看出，该第三虚设子电路0123包括：第五虚设薄膜晶体管01231，第六虚设薄膜晶体管01232，第八控制线01233，第十一测试数据线01234，以及第十二测试数据线01235。该第十一测试数据线003和第十二测试数据线01235沿第一边界001a1的延伸方向X延伸。
该第五虚设薄膜晶体管01231可以包括：第五虚设源极012311，第五虚设漏极012312和第五虚设栅极012313，第五虚设漏极012312可以与多条第二数据传输线0042中的一条电连接，第五虚设栅极012313可以与第八控制线01233电连接。该第八控制线01233可以为第五虚设栅极012313提供栅极驱动信号。
该第六虚设薄膜晶体管01232可以包括：第六虚设源极012321，第六虚设漏极012322和第六虚设栅极012323，第六虚设漏极012322可以与多条第二数据传输线0042中的一条电连接，第六虚设栅极012323可以与第八控制线01233电连接。也即是，该第五虚设薄膜晶体管01231和第六虚设薄膜晶体管01232可以共用一条控制线。
在本申请实施例中，参考图13，第七控制线01123和第八控制线01233相邻设置，该第七控制线01123和第八控制线01233可以为一条控制线。由此，第三薄膜虚设晶体管01221，第四虚设薄膜晶体管01222，第五虚设薄膜晶体管01231以及第六虚设薄膜晶体管01232可以共用一条控制线。
需要说明的是，第三控制线01112可以与第六控制线01212电连接，也即是，第三控制线01112与第六控制线01212可以为同一条控制线。该第三控制线01112提供给第二薄膜晶体管01111的第二栅极011113的栅极驱动信号，可以与第六控制线01212提供给第二虚设薄膜晶体管01211的第二虚设栅极012113的栅极驱动信号相同。
该第四控制线01123可以与第七控制线01223电连接，也即是，该第四控制线01123与第七控制线01223可以为同一条控制线。该第四控制线01123提供给第三薄膜晶体管01121的第三栅极011213和第四薄膜晶体管01122的第四栅极011223的栅极驱动信号，可以与第七控制线01223提供给第三虚设薄膜晶体管01221的第三虚设栅极012213和第四虚设薄膜晶体管01222的第四虚设栅 极012223的栅极驱动信号相同。
第五控制线01133可以与第八控制线01233电连接，也即是，第五控制线01133与第八控制线01233可以为同一条控制线。该第五控制线01133提供给第五薄膜晶体管01131的第五栅极011313和第六薄膜晶体管01132的第六栅极011323的栅极驱动信号，可以与第八控制线01233提供给第五虚设薄膜晶体管01231的第五虚设栅极012313和第六虚设薄膜晶体管01232的第六栅极012313的栅极驱动信号相同。
第三测试数据线01113可以与第八测试数据线01213电连接，也即是，第三测试数据线01113与第八测试数据线01213可以为同一条数据线。该第三测试数据线01113与第八测试数据线01213可以为提供给第二薄膜晶体管01111的第二源极01111提供数据信号。
第四测试数据线01124可以与第九测试数据线01224电连接，也即是，第四测试数据线01124与第九测试数据线01224可以为同一条数据线。该第四测试数据线01124与第九测试数据线01224可以为第三薄膜晶体管01121的第三源极011211提供数据信号。
第五测试数据线01125可以与第十测试数据线01225电连接，也即是，第五测试数据线01125与第十测试数据线01225可以为同一条数据线。该第五测试数据线01125与第十测试数据线01225可以为第四薄膜晶体管01122的第四源极011221提供数据信号。
第六测试数据线01134可以与第十一测试数据线01234电连接，也即是，第六测试数据线01134与第十一测试数据线01234可以为同一条数据线。该第六测试数据线01134与第十一测试数据线01234可以为第五薄膜晶体管01131的第五栅极011313提供数据信号。
第七测试数据线01135可以与第十二测试数据线01235电连接，也即是，第七测试数据线01135与第十二测试数据线01235可以为同一条数据线。该第七测试数据线01135与第十二测试数据线01235可以为第六薄膜晶体管01132的第六源极011321提供数据信号。
需要说明的是，在显示基板00的制造过程中，需在衬底基板001的周边区域001b中位于静电释放电路005和第一测试电路009之间制造第二测试电路011，该第二测试电路011可以用于连接静电释放电路005和第一测试电路009。由于在制造第二测试电路011时，为了保证该第二测试电路011的制造精度， 可以在该衬底基板001上制造不与静电释放电路005和第一测试电路009电连接的测试电路，即第二测试虚设电路012。在本申请实施例中，显示基板中设置的静电释放虚设电路007可以通过该第二测试虚设电路012以及第一测试虚设电路010与面板裂纹检测走线006连接，可以优化背板的走线和电路排布。
在本申请实施例中，第二测试虚设电路012的数量可以与静电释放虚设电路007的数量以及第一测试虚设电路010的数量相同。每个静电释放虚设电路007可以通过一个第二测试虚设电路012与一个第一测试虚设电路010电连接。
示例的，图10中示出了两个第二测试虚设电路012，且该两个第二测试虚设电路012可以位于多个第二测试电路011的两侧。对于每个第二测试虚设电路012，该第二测试虚设电路012可以与其位于同侧的静电释放虚设电路007以及第一测试虚设电路010电连接。
图14是本申请实施例提供的再一种显示基板的结构示意图。参考图14可以看出，该显示基板00还可以包括：至少一个第一信号输入端013。该至少一个第一信号输入端013可以与第三子走线00613连接，该至少一个第一信号输入端013可以被配置为接收测试信号，以对显示基板进行检测。
可选的，该至少一个第一信号输入端013可以包括：两个第一信号输入端013，该两个第一信号输入端013可以分别位于第一测试电路009的两侧。
参考图14可以看出，多个子像素002可以包括：至少一列第一子像素0021。图14中仅示意性示出了每列子像素002中的部分子像素002。该第一子像素0021可以与第一子走线00611或第二子走线00612连接，该至少一个第一信号输入端013可以用于向第一子像素0021提供驱动信号，该驱动信号可以用于驱动每列第一子像素0021发出目标颜色的光。其中，该驱动信号可以为面板检测数据(cell test data，CTD)信号。
由于第三子走线00613与第二走线段0062以及第三走线段0063连接，第二走线段0062与第一子走线00611连接，第三走线段0063与第二子走线00612连接，该第一子走线00611可以与第一子像素0021连接，第二子走线00612可以与第一子像素0021连接。因此该第一信号输入端013向第三子走线00613输入驱动信号，该第三子走线00613可以将该驱动信号传输至第二走线段0062和第三走线段0063，第二走线段0062可以将该驱动信号传输至第一子走线00611，第三走线段0063可以将驱动信号传输至第二子走线00612。最后，第一子走线00611可以将驱动信号传输至与该第一子走线00611连接的第一子像素0021， 第二子走线00612可以将驱动信号传输至与该第二子走线00612连接的第一子像素0021。
也即是，驱动信号需要依次通过第三子走线00613，第二走线段0062，以及第一子走线00611后才能传输至与该第一子走线00611连接的第一子像素0021。若显示基板中第三子走线00613，第二走线段0062，以及第一子走线00611所在区域的边缘存在裂纹，即该第三子走线00613，第二走线段0062或第一子走线00611存在断裂，该驱动信号无法传输至与该第一子走线00611连接的第一子像素0021，该第一子像素0021无法发出目标颜色的光。若显示基板00中第三子走线00613，第二走线段0062，以及第一子走线00611所在区域的边缘不存在裂纹，即该第三子走线00613，第二走线段0062以及第一子走线00611不存在断裂，则驱动信号可以传输至与该第一子走线00611连接的第一子像素0021，该第一子像素0021可以发出目标颜色的光。
并且，驱动信号需要依次通过第三子走线00613，第三走线段0063，以及第二子走线00612后才能传输至与该第二子走线00612连接的第一子像素0021。若显示基板中第三子走线00613，第三走线段0063，以及第二子走线00612所在区域的边缘存在裂纹，即该第三子走线00613，第三走线段0063或第二子走线00612存在断裂，该驱动信号无法传输至与该第二子走线00612连接的第一子像素0021，该第一子像素0021无法发出目标颜色的光。若显示基板中第三子走线00613，第三走线段0063，以及第二子走线00612所在区域的边缘不存在裂纹，即该第三子走线00613，第三走线段0063以及第二子走线00612不存在断裂，则驱动信号可以传输至与该第二子走线00612连接第一子像素0021，该第一子像素0021可以发出目标颜色的光。
可选的，该目标颜色可以为黑色，该第一子像素0021可以为绿色子像素002，若显示基板00的边缘存在裂纹，该绿色子像素002无法接收到驱动信号，该绿色子像素002可以发出绿色的光。
由此，可以通过判断第一子像素0021是否发出目标颜色的光确定显示基板的边缘是否存在裂纹。也即是，若每列第一子像素0021均能够发出目标颜色的光，即可以确定第一子像素0021能够接收到驱动信号，进而可以确定显示基板00的边缘不存在裂纹。若某列第一子像素0021无法发出目标颜色的光，可以确定该列第一子像素0021无法接收到驱动信号，进而可以确定显示基板00的边缘存在裂纹。
需要说明的是，若显示基板00的边缘存在裂纹，且该裂纹较小，则不会导致面板裂纹检测走线006出现裂纹，该第一子像素0021能够发出目标颜色的光。
图15是本申请实施例提供的一种面板裂纹检测走线的检测原理图。参考图15可以看出，面板裂纹检测走线006可以与目标晶体管M0的源极连接，该目标晶体管M0的栅极可以与栅线A连接，该目标晶体管M0的漏极可以通过数据传输线004以及数据线003与第一子像素0021连接。
该目标晶体管M0中流过的电流I可以满足：
I＝K(Vgs-Vth) 2＝K[(Vdata+Vth-Vs)-Vth] 2＝K(Vdata-Vs) 2。
其中，K是由目标晶体管M0的特性决定的常数，其满足：
Figure PCTCN2020088673-appb-000001
μ为目标晶体管M0的载流子迁移率，W/L为目标晶体管M0的沟道宽长比，ε为目标晶体管M0的栅极氧化层的介电常数，d为栅极氧化层的厚度。
并且，Vgs为目标晶体管M0的栅极与源极之间的电压差，Vth为目标晶体管M0的阈值电压，Vdata为数据传输线004上的电压，Vs为目标晶体管M0的源极电压。
若该面板裂纹检测走线006不存在断裂，该面板裂纹检测走线006提供给的目标晶体管M0的源级电压与第一目标驱动线B以及第二目标驱动线C提供给其他晶体管的源极电压相同，例如可以为6伏(V)。
若面板裂纹检测走线006存在断裂，该面板裂纹检测走线006提供的目标晶体管M0的电压为0V，栅线提供给目标晶体管M0的电压为-7V，则Vgs＝Vg-Vs＝-7V<Vth。Vdata＝0，I＝K(Vs) 2。由此，与该目标晶体管M0连接的绿色子像素002会被点亮，即黑态画面出现绿色亮线。
图16是本申请实施例提供的再一种显示基板的结构示意图。参考图16可以看出，该显示基板00还可以包括：第一检测端014和第二检测端015。该第一检测端014可以与第一子走线00611连接，用于为第一子走线00611提供检测信号。该第二检测端015可以与第二子走线00612连接，用于接收检测信号，以对显示基板进行检测。
若第二检测端015能够接收到检测信号，则可以确定该面板裂纹检测走线006未断裂，即显示基板00的边缘不存在裂纹；若第二检测端015无法接收到检测信号，则可以确定该面板裂纹检测走线006断开，即显示基板00的边缘存在裂纹。
在本申请实施例中，参考图14和图16，多个子像素002还可以包括：除至 少一列第一子像素0021之外的多列第二子像素0022。该显示基板00还可以包括：至少一个第二信号输入端016和至少一个第三信号输入端017。该第二信号输入端016可以与至少一列第二子像素0022连接，用于向与其所连接的各列第二子像素0022提供驱动信号，该驱动信号用于驱动每列第二子像素0022发出目标颜色的光。该第三信号输入端017可以与第一测试电路009和第一测试虚设电路010电连接。
由于第二子像素0022与第二信号输入端016直接电连接，因此驱动信号可以直接输入至第二子像素0022。也即是，无论显示基板00的边缘是否存在裂纹，第二子像素0022均能够发出目标颜色的光。
在本申请实施例中，该第二信号输入端016可以与第一测试数据线0093或第二测试数据线0094电连接。该第二子像素0022可以为红色子像素002或蓝色子像素002。
可选的，该至少一个第二信号输入端016可以包括：四个第二信号输入端016，该四个第二信号输入端016可以分别位于第一测试电路009的两侧。其中，该第一测试电路009的每侧可以具有两个该第二信号输入端016，其中一个第二信号输入端016与第一测试数据线0093电连接，另一个第二信号输入端016与第二测试数据线0094电连接。
图17是本申请实施例提供的一种静电释放虚设电路的电路图。参考图17可以看出，该静电释放虚设电路007可以包括：第一静电防护线0071，至少一个第一放电晶体管0072，以及至少一个第二放电晶体管0073。该至少一个放电晶体管的第一极和栅极均与面板裂纹检测走线006连接，至少一个第一放电晶体管0072的第二极可以与第一静电防护线0071连接。至少一个第二放电晶体管0073的第一极和栅极可以与第一静电防护线0071连接，至少一个第二放电晶体管0073的第二极可以与面板裂纹检测走线006连接。
若面板裂纹检测走线006上积累的静电为负电荷，则第一放电晶体管0072开启，将面板裂纹检测走线006与第一静电防护线0071导通，面板裂纹检测走线006可以通过第一放电晶体管0072向第一静电防护线0071放电。也即是，该面板裂纹检测走线006上积累的负电荷可以通过第一放电晶体管0072释放至第一静电防护线0071。
若该面板裂纹检测走线006上积累的静电为正电荷，则第二放电晶体管0073开启，将面板裂纹检测走线006与第一静电防护线0071导通，面板裂纹检测走 线006可以通过第二放电晶体管0073向第一静电防护线0071放电。也即是，该面板裂纹检测走线006上积累的正电荷可以通过第二放电晶体管0073释放至第一静电防护线0071。
在本申请实施例中，参考图18，该第一静电防护线0071可以包括第一放电线00711和第二放电线00712。并且，该静电释放虚设电路007可以包括：两个第一放电晶体管0072和两个第二放电晶体管0073。
参考图18，第一个第一放电晶体管0072a的第一极和栅极均与面板裂纹检测走线006连接，第一个第一放电晶体管0072a第二极与第二个第一放电晶体管0072b的第一极和栅极连接，第二个第一放电晶体管0072b的第二极与第一放电线00711连接。也即是，该第二个第一放电晶体管0072b的第一极和栅极可以通过第一个第一放电晶体管0072a与该第一放电线00711连接。
第一个第二放电晶体管0073的第一极和栅极均与第二放电线00712连接，第一个第二放电晶体管0073的第二极与第二个第二放电晶体管0073的第一极和栅极连接，第二个第二放电晶体管0073的第二极与面板裂纹检测走线006连接。也即是，该第二个第二放电晶体管0073的第一极和栅极可以通过第一个第二放电晶体管0073与该第二放电线00712连接。
其中，第一放电线00711可以为低电位(voltage gate low，VGL)线。第二放电线00712可以为高电位(voltage gate high，VGH)线。
图19是本申请实施例提供的一种静电释放虚设电路释放负电荷的原理图，图19中将该至少一个第一放电晶体管0072等效为一个二极管D1，将该至少一个第二放电晶体管0073也等效为一个二极管D2。参考图19，在面板裂纹检测走线006上未积累负电荷时，第一放电晶体管0072的栅极的电位Vg1，以及第一放电晶体管0072的源极(即第一极)的电位Vs1，均等于面板裂纹检测走线006的电位Vpcd，该电位Vpcd大于第一放电线00711上的电位VGL。每个第一放电晶体管0072的漏极(即第二极)电位Vd1等于第一放电线00711上的电位VGL。即在面板裂纹检测走线006上未积累负电荷时，Vg1＝Vs1＝Vpcd>VGL，Vd1＝VGL。
在面板裂纹检测走线006上积累有负电荷时，每个第一放电晶体管0072的栅极电位Vg1，以及每个第一放电晶体管0072的源极电位Vs1均等于面板裂纹检测走线006的电位Vpcd，且该电位Vpcd小于第一放电线00711上的电位VGL。每个第一放电晶体管0072的漏极电位Vs1等于第一放电线00711上的电位 VGL。即在面板裂纹检测走线006上积累有负电荷时，Vg1＝Vs1＝Vpcd<VGL，Vd1＝VGL。此时，每个第一放电晶体管0072开启(即二极管D1导通)，面板裂纹检测走线006中的负电荷可以释放至第一放电线00711。
示例的，假设第一放电线00711上的电位VGL为-7V，在面板裂纹检测走线006上未积累负电荷时，即面板裂纹检测走线006的电位Vpcd为0V(该第一放电晶体管0072的栅极电位和源极电位均为0V)，即大于-7V。该第一放电晶体管0072的漏极电位Vd1等于-7V。此时，该第一放电晶体管0072关断。
在面板裂纹检测走线006上积累负电荷时，该面板裂纹检测走线006上的电位小于-7V，该第一放电晶体管0072的漏极电位Vd1等于-7V。此时，第一放电晶体管0072导通。
图20是本申请实施例提供的一种静电释放虚设电路释放正电荷的原理图。图20中将该至少一个第一放电晶体管0072等效为一个二极管D1，将该至少一个第二放电晶体管0073也等效为一个二极管D2。参考图20，在面板裂纹检测走线006上未积累正电荷时，每个第二放电晶体管0073的栅极电位Vg2，以及每个第二放电晶体管0073的源极(第一极)电位Vs2均等于第二放电线00712上的电位VGH。每个第一放电晶体管0072的漏极(第二极)电位Vd2等于面板裂纹检测走线006的电位Vpcd，该电位Vpcd小于第二放电线00712上的电位VGH。即面板裂纹检测走线006上未积累正电荷时，Vg2＝Vs2＝VGH，Vd2＝Vpcd<VGH。
在面板裂纹检测走线006上积累有正电荷时，每个第二放电晶体管0073的栅极电位Vg2，以及每个第二放电晶体管0073的源极电位Vs2均等于第二放电线00712上的电位VGH。每个第二放电晶体管0073的漏极电位Vs2等于面板裂纹检测走线006的电位Vpcd，该电位Vpcd大于第二放电线00712上的电位VGH。即在面板裂纹检测走线006上积累有正电荷时，Vg2＝Vs2＝VGH，Vd2＝Vpcd＞VGH。此时，每个第二放电晶体管0073开启(即二极管导通)，面板裂纹检测走线006中的正电荷可以释放至第二放电线00712。
示例的，假设第二放电线00712上的电位VGH为7V，在面板裂纹检测走线006上未积累正电荷时，该第二放电晶体管0073的栅极电位和源极电位均等于第二放电线00712上的电位7V。该第二放电晶体管0073的漏极电位等于面板裂纹检测走线006的电位Vpcd，即0V。此时，该第二放电晶体管0073关断。
在面板裂纹检测走线006上积累正电荷时，该第二放电晶体管0073的漏极 电位大于7V，而该第二放电晶体管0073的栅极电位和源极电位均等于7V。此时，第二放电晶体管0073导通。
本申请实施例中的显示基板00包括的静电释放虚设电路007可以释放面板裂纹检测走线006中的静电释放至第一静电防护线0071，避免显示基板00中的其他走线由于面板裂纹检测走线006上积累的静电而被烧断，提高显示基板00的良率。
可选的，该显示基板00包括的多个静电释放虚设电路007可以沿显示区域001a的边界均匀分布在周边区域001b。通过将静电释放虚设电路007均匀分布在周边区域001b，可以使得面板裂纹检测走线006上的静电被有效释放，保证显示基板00的良率。示例的，该多个静电释放虚设电路007可以均匀分布靠近第一边界001a1的周边区域001b1。
图21是本申请实施例提供的一种静电释放虚设电路的结构示意图。参考图21可以看出，该静电释放虚设电路007中的第一放电晶体管0072的第一极00721和栅极00722可以与多条数据传输虚设线008中的一条电连接，第二极00723可以与第一静电防护线0071电连接。第二放电晶体管0073的第一极00731和栅极00732可以与第一静电防护线0071电连接，第二极00733可以与多条数据传输虚设线008中的一条电连接。该多条数据传输线004与面板裂纹检测走线006连接，从而将面板裂纹检测走线006中的静电通过静电释放虚设电路007释放至第一静电防护线0071。
参考图21可以看出，每个静电释放虚设电路007包括的第一放电晶体管0072和第二放电晶体管0073可以位于两条数据传输虚设线008之间。例如，位于第一数据传输虚设线0081和第二数据传输虚设线0082之间。该第一静电防护线0071的延伸方向可以与数据传输虚设线008的延伸方向相交。例如，该第一静电防护线0071的延伸方向可以与数据传输虚设线008的延伸方向垂直。
在本申请实施例中，参考图21，沿平行于第一放电线00711的延伸方向排布的多个静电释放虚设电路007可以共用一条第一放电线00711，沿垂直于第一放电线00711的延伸方向排布的两个静电释放虚设电路007可以共用一条第一放电线00711。也即是，该显示基板00中包括的静电释放虚设电路007均共用一条第一放电线00711。沿平行于第二放电线00712的延伸方向排布的多个静电释放虚设电路007可以共用一个第二放电线00712。例如，第一数据传输虚设线0081所连接的第一放电晶体管0072a所连接的第一放电线00711，与第二数据传 输虚设线0082所连接的第一放电晶体管0072b所连接的第一放电线00711为同一条第一放电线00711。
需要说明的是，第一放电线00711，第二放电线00712，面板裂纹检测走线006，以及晶体管的源漏极层可以同层设置。也即是，该第一放电线00711，第二放电线00712，面板裂纹检测走线006以及晶体管的源漏极层采用同一次构图工艺形成。或者，该第一放电线00711，第二放电线00712，面板裂纹检测走线006，以及晶体管的源漏极层中的至少两种结构可以位于不同层。例如，该第一放电线00711，第二放电线00712，面板裂纹检测走线006，以及晶体管的源漏极层均不同层。也即是，该第一放电线00711，第二放电线00712，面板裂纹检测走线006，以及晶体管的源漏极层需分别采用一次构图工艺形成，共四次构图工艺。
图22是本申请实施例提供的一种静电释放电路的电路图。参考图22可以看出，该静电释放电路005可以包括：第二静电防护线0051，至少一个第三放电晶体管0052，以及至少一个第四放电晶体管0053。该至少一个第三放电晶体管0052的第一极和栅极均与数据传输线004电连接，至少一个第三放电晶体管0052的第二极可以与第二静电防护线0051电连接。至少一个第四放电晶体管0053的第一极和栅极可以与第二静电防护线0051电连接，至少一个第四放电晶体管0053的第二极可以与数据传输线004电连接。
若数据传输线004上积累的静电为负电荷，则第三放电晶体管0052开启，将数据传输线004与第二静电防护线0051导通，数据传输线004可以通过第一放电晶体管0052向第二静电防护线0051放电。也即是，数据传输线004上积累的负电荷可以通过第三放电晶体管0052释放至第二静电防护线0051。
若数据传输线004上积累的静电为正电荷，则第四放电晶体管0053开启，将数据传输线004与第二静电防护线0051导通，数据传输线004可以通过第四放电晶体管0053向第二静电防护线0051放电。也即是，该数据传输线004上积累的正电荷可以通过第四放电晶体管0053释放至第二静电防护线0051。
在本申请实施例中，参考图23，该第二静电防护线0051可以包括第三放电线00511和第四放电线00512。并且，该静电释放电路005可以包括：两个第三放电晶体管0052和两个第四放电晶体管0053。
参考图23，第一个第三放电晶体管0052a的第一极和栅极均与数据传输线004连接，第一个第三放电晶体管0052a第二极与第二个第三放电晶体管0052b 的第一极和栅极连接，第二个第三放电晶体管0052b的第二极与第三放电线00511连接。也即是，该第二个第三放电晶体管0052b的第一极和栅极可以通过第一个第三放电晶体管0052a与该第三放电线00511连接。
第一个第四放电晶体管0053a的第一极和栅极均与第四放电线00512连接，第一个第四放电晶体管0053a的第二极与第二个第四放电晶体管0053b的第一极和栅极连接，第二个第四放电晶体管0053b的第二极与数据传输线004连接。也即是，该第二个第四放电晶体管0053b的第一极和栅极可以通过第一个第四放电晶体管0053a与该第四放电线00512连接。
其中，第三放电线00511可以为VGL线。第四放电线00512可以为VGH线。
图24是本申请实施例提供的一种静电释放电路释放负电荷的原理图，图24中将该至少一个第三放电晶体管0052等效为一个二极管D3，将该至少一个第四放电晶体管0053也等效为一个二极管D4。参考图24，在数据传输线004上未积累负电荷时，第三放电晶体管0052的栅极的电位Vg3，以及第三放电晶体管0052的源极(即第一极)的电位Vs3，均等于数据传输线004的电位Vc，该电位Vc大于第三放电线00511上的电位VGL。每个第三放电晶体管0052的漏极(即第二极)电位Vd3等于第三放电线00511上的电位VGL。即在数据传输线004上未积累负电荷时，Vg3＝Vs3＝Vc>VGL，Vd3＝VGL。
在数据传输线004上积累有负电荷时，每个第三放电晶体管0052的栅极电位Vg3，以及每个第三放电晶体管0052的源极电位Vs3均等于数据传输线004的电位Vc，且该电位Vc小于第三放电线00511上的电位VGL。每个第三放电晶体管0052的漏极电位Vs3等于第一放电线00511上的电位VGL。即在数据传输线004上积累有负电荷时，Vg3＝Vs3＝Vc<VGL，Vd3＝VGL。此时，每个第一放电晶体管0052开启(即二极管D3导通)，数据传输线004中的负电荷可以释放至第一放电线00511。
示例的，假设第三放电线00511上的电位VGL为-7V，在数据传输线004上未积累负电荷时，即数据传输线004的电位Vc为0V(该第三放电晶体管0052的栅极电位和源极电位均为0V)，即大于-7V。该第三放电晶体管0052的漏极电位Vd3等于-7V。此时，该第三放电晶体管0052关断。
在数据传输线004上积累负电荷时，该数据传输线004上的电位小于-7V，该第三放电晶体管0052的漏极电位Vd3等于-7V。此时，第三放电晶体管0052 导通。
图25是本申请实施例提供的一种静电释放电路释放正电荷的原理图。图25中将该至少一个第三放电晶体管0052等效为一个二极管D3，将该至少一个第四放电晶体管0053也等效为一个二极管D4。参考图25，在数据传输线004上未积累正电荷时，每个第四放电晶体管0053的栅极电位Vg4，以及每个第四放电晶体管0053的源极(第一极)电位Vs4均等于第四放电线00512上的电位VGH。每个第三放电晶体管0052的漏极(第二极)电位Vd3等于数据传输线004的电位Vc，该电位Vc小于第四放电线00512上的电位VGH。即数据传输线004上未积累正电荷时，Vg4＝Vs4＝VGH，Vd4＝Vc<VGH。
在数据传输线004上积累有正电荷时，每个第四放电晶体管0053的栅极电位Vg4，以及每个第四放电晶体管0053的源极电位Vs4均等于第四放电线00512上的电位VGH。每个第四放电晶体管0053的漏极电位Vs4等于数据传输线004的电位Vc，该电位Vc大于第四放电线00512上的电位VGH。即在数据传输线004上积累有正电荷时，Vg4＝Vs4＝VGH，Vd4＝Vc＞VGH。此时，每个第四放电晶体管0053开启(即二极管导通)，数据传输线004中的正电荷可以释放至第四放电线00512。
示例的，假设第四放电线00512上的电位VGH为7V，在数据传输线004上未积累正电荷时，该第四放电晶体管0053的栅极电位和源极电位均等于第四放电线00512上的电位7V。该第四放电晶体管0053的漏极电位等于数据传输线004的电位Vc，即0V。此时，该第四放电晶体管0053关断。
在数据传输线004上积累正电荷时，该第四放电晶体管0053的漏极电位大于7V，而该第四放电晶体管0053的栅极电位和源极电位均等于7V。此时，第四放电晶体管0053导通。
本申请实施例中的显示基板00包括的静电释放电路005可以释放数据传输线004中的静电释放至第二静电防护线0051，显示基板00的良率较高。
图26是本申请实施例提供的一种静电释放电路的结构示意图。参考图26可以看出，该静电释放电路005中的第三放电晶体管0072的第一极00721和栅极00722可以与多条数据传输线004中的一条电连接，第二极00523可以与第二静电防护线0051电连接。第四放电晶体管0053的第一极00531和栅极00532可以与第二静电防护线0051电连接，第二极00533可以与多条数据传输线004中的一条电连接。该多条数据传输线004与数据线003电连接，从而将数据线 003中的静电通过静电释放电路007释放至第二静电防护线0051。
参考图26可以看出，每个静电释放电路005包括的第三放电晶体管0052和第四放电晶体管0053可以位于两条数据传输线004之间。例如，位于第一数据传输线0041和第二数据传输线0042之间。该第二静电防护线0051的延伸方向可以与数据传输线004的延伸方向相交。例如，该第二静电防护线0051的延伸方向可以与数据传输线004的延伸方向垂直。
在本申请实施例中，参考图26，沿平行于第二放电线00511的延伸方向排布的多个静电释放电路005可以共用一条第三放电线00511，沿垂直于第三放电线00511的延伸方向排布的两个静电释放电路005可以共用一条第一放电线00511。也即是，该显示基板00中包括的静电释放电路005均共用一条第三放电线00511。沿平行于第四放电线00512的延伸方向排布的多个静电释放电路005可以共用一个第四放电线00512。例如，第一数据传输线0041所连接的第三放电晶体管0052a所连接的第三放电线00511，与第二数据传输线0042所连接的第三放电晶体管0052b所连接的第三放电线00511为同一条第三放电线00511。
需要说明的是，第三放电线00511，第四放电线00512，面板裂纹检测走线006，以及晶体管的源漏极层可以同层设置。也即是，该第三放电线00511，第四放电线00512，面板裂纹检测走线006以及晶体管的源漏极层采用同一次构图工艺形成。或者，该第三放电线00511，第四放电线00512，面板裂纹检测走线006，以及晶体管的源漏极层中的至少两种结构可以位于不同层。例如，该第三放电线00511，第四放电线00512，面板裂纹检测走线006，以及晶体管的源漏极层均不同层。也即是，该第三放电线00511，第四放电线00512，面板裂纹检测走线006，以及晶体管的源漏极层需分别采用一次构图工艺形成，共四次构图工艺。
需要说明的是，第一放电线00711可以与第三放电线00511连接，即该第一放电线00711与第三放电线00511可以为同一条放电线。第二放电线00712可以与第四放电线00512连接，即该第二放电线00712与第四放电线00512可以为同一条放电线。
图27是本申请实施例提供的一种静电释放虚设电路，第一测试虚设电路以及第二测试虚设电路的结构示意图。参考图27可以看出，该第二测试虚设电路012可以位于静电释放虚设电路007和第一测试虚设电路010之间。并且，该多 个静电释放虚设电路007可以通过多条数据传输虚设线008与第二测试虚设电路012连接，该第二测试虚设电路012可以通过多条数据传输虚设线008与第一测试虚设电路010电连接。
图28是本申请实施例提供的一种静电释放电路，第一测试电路以及第二测试电路的结构示意图。参考图28可以看出，该第二测试电路011可以位于静电释放电路005和第一测试电路009之间。并且，该多个静电释放电路005可以通过多条数据传输线004与第二测试电路011电连接，该第二测试电路011可以通过多条数据传输线004与第一测试电路009电连接。
参考图12还可以看出，该显示基板00还可以包括：缓冲层018，有源层019，第一栅极绝缘层020，第二栅极绝缘层021，层间介电层022，源漏极层023，钝化层024，平坦层025，阳极层026，发光层027，阴极层028，像素界定层029，支撑层030，第一无机封装层031，有机封装层032，以及第二无机封装层033。
其中，该缓冲层018可以位于衬底基板001的一侧，该有源层019可以位于缓冲层018远离衬底基板001的一侧，第一栅极绝缘层020可以位于有源层019远离缓冲层018的一侧，栅极层可以位于第一栅极层远离有源层019的一侧，第二栅极绝缘层021可以位于栅极层远离第一栅极绝缘层020的一侧，层间介电层022可以位于第二栅极绝缘层021远离栅极层的一侧，源漏极层023可以位于层间介电层022远离第二栅极绝缘层021的一侧，钝化层024可以位于源漏极层023远离层间介电层022的一侧，平坦层025可以位于钝化层024远离源漏极层的一侧，阳极层026可以位于平坦层025远离钝化层024的一侧，像素界定层029可以位于阳极层026远离平坦层025的一侧，支撑层030可以位于像素界定层029远离平坦层025的一侧，发光层027可以位于阳极层026远离平坦层025的一侧，阴极层028可以位于发光层027远离阳极层026的一侧，第一无机封装层031可以位于阴极层028远离发光层027的一侧，有机封装层032可以位于第一无机封装层031远离阴极层028的一侧，第二无机封装层033可以位于有机封装层032远离第一无机封装层031的一侧。
综上所述，本申请实施例提供了一种显示基板，该显示基板包括：衬底基板，多个子像素，多条数据线，多条数据传输线，多个静电释放电路，面板裂纹检测走线，以及多个静电释放虚设电路，其中多个静电释放虚设电路中的至少一个静电释放虚设电路可以与面板裂纹检测走线连接。本申请实施例提供的 方案可以通过静电释放虚设电路释放面板裂纹检测走线上积累的静电，避免显示基板中的其他走线由于面板裂纹检测走线上积累的静电而被烧断，提高了显示基板的良率。
本申请实施例还提供了一种显示装置，该显示装置可以包括上述实施例所述的显示基板。
可选的，该显示装置可以为液晶显示装置、电子纸、有机发光二极管(organic light-emitting diode，OLED)显示装置、有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (26)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板，所述衬底基板具有显示区域，以及围绕所述显示区域的周边区域；
    多个子像素，位于所述显示区域；
    多条数据线，位于所述显示区域且与所述多个子像素电连接；
    多条数据传输线，位于所述周边区域，且与所述多条数据线电连接；
    多个静电释放电路，位于所述周边区域，且与所述多条数据传输线电连接，所述多个静电释放电路沿所述显示区域的边界的延伸方向排布；
    面板裂纹检测走线，位于所述周边区域且环绕所述显示区域；
    多个静电释放虚设电路，位于所述周边区域，沿所述显示区域的边界的延伸方向排布，所述多个静电释放虚设电路在沿所述显示区域边界的延伸方向上位于所述多个静电释放电路的至少一侧，所述多个静电释放虚设电路中的至少一个静电释放虚设电路与所述面板裂纹检测走线电连接，用于释放所述面板裂纹检测走线上的静电。
  2. 根据权利要求1所述的显示基板，其中，所述显示区域的边界包括依次连接的第一边界，第二边界，第三边界以及第四边界，所述多个静电释放电路和所述多个静电释放虚设电路位于靠近所述第一边界的所述周边区域；
    所述多个静电释放虚设电路包括多个第一静电释放虚设子电路和多个第二静电释放虚设子电路；
    在沿所述第一边界的延伸方向上，所述多个第一静电释放虚设子电路和所述多个第二静电释放虚设子电路分别位于所述多个静电释放电路的两侧。
  3. 根据权利要求1或2所述的显示基板，其中，所述面板裂纹检测走线包括：第一走线段，第二走线段以及第三走线段；
    所述第一走线段为不连续走线，位于靠近所述显示区域的第一边界的所述周边区域，所述第一走线段沿所述第一边界的延伸方向延伸；
    所述第二走线段为连续走线，位于靠近所述第一边界，所述第二边界以及所述第三边界的所述周边区域，所述第二走线段的两个端点位于靠近所述第一 边界的所述周边区域；
    所述第三走线段为连续走线，位于靠近所述第三边界，所述第四边界以及所述第一边界的所述周边区域，所述第三走线段的两个端点位于靠近所述第一边界的所述周边区域，所述第二走线段和所述第三走线段分别与所述第一走线段连接；
    其中，所述多个静电释放虚设电路与所述第一走线段电连接。
  4. 根据权利要求3所述的显示基板，其中，所述第一走线段包括：沿所述第一边界的延伸方向延伸的第一子走线，第二子走线以及第三子走线，所述第一子走线和所述第二子走线位于所述第三子走线靠近所述显示区域的一侧；
    所述第一子走线和所述第三子走线分别与所述第二走线段的两个端点连接，所述第二子走线和所述第三子走线分别与所述第三走线段的两个端点连接；
    所述多个静电释放虚设电路与所述第三子走线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述显示基板还包括：多条数据传输虚设线，所述多个静电释放虚设电路通过所述多条数据传输虚设线与所述第三子走线电连接。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括：多个第一测试电路，位于所述多个静电释放电路远离所述显示区域的一侧，且所述多个第一测试电路沿所述第一边界的延伸方向延伸排布；
    所述多个第一测试电路中的至少一个所述第一测试电路包括：第一薄膜晶体管，第一控制线，第一测试数据线和第二测试数据线，所述第一控制线，所述第一测试数据线和所述第二测试数据线位于所述周边区域且沿所述第一边界的延伸方向延伸；
    所述第一薄膜晶体管包括：第一源极，第一漏极和第一栅极，所述第一栅极与所述第一控制线电连接，所述第一源极与所述第一测试数据线，第二测试数据线，所述第一子走线以及所述第二子走线中的一条线电连接，所述第一漏极与所述多条数据传输线中的一条电连接。
  7. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：多个第一测试虚设电路，所述多个第一测试虚设电路在沿所述第一边界的延伸方向上，位于所述多个第一测试电路的两侧且位于所述多个静电释放虚设电路和所述第三子走线之间，所述多个第一测试虚设电路通过所述多条数据传输虚设线与所述第三子走线以及所述静电释放虚设电路电连接。
  8. 根据权利要求7所述的显示基板，其中，所述多个第一测试虚设电路中的至少一个所述第一测试虚设电路包括：第一虚设薄膜晶体管以及第二控制线，所述第二控制线位于所述周边区域且沿所述第一边界的延伸方向延伸，所述第一虚设薄膜晶体管包括：第一虚设源极，第一虚设漏极以及第一虚设栅极；
    所述第一虚设栅极与所述第二控制线电连接，所述第一虚设漏极与所述多条数据传输虚设线中的一条电连接。
  9. 根据权利要求7或8所述的显示基板，其中，所述静电释放虚设电路的数量与所述第一测试虚设电路的数量相同，每个所述静电释放虚设电路通过一个所述第一测试虚设电路与所述第三子走线电连接。
  10. 根据权利要求6至9任一所述的显示基板，其中，所述显示基板还包括：多个第二测试电路，所述多个第二测试电路位于所述多个静电释放电路和所述多个第一测试电路之间，且所述多个第二测试电路通过所述多条数据传输线与所述多个静电释放电路以及所述多个第一测试电路电连接。
  11. 根据权利要求10所述的显示基板，其中，所述多个第二测试电路中的至少一个所述第二测试电路包括：第一子电路，第二子电路和第三子电路，所述第二子电路位于所述第一子电路与所述第三子电路之间，所述第一子电路位于所述第二子电路远离所述多个子像素的一侧。
  12. 根据权利要求11所述的显示基板，其中，所述多条数据传输线包括：多条第一数据传输线和多条第二数据传输线，所述多条第一数据传输线和所述多条第二数据传输线一一交替排布；
    所述第一子电路包括：第二薄膜晶体管，第三控制线，以及第三测试数据线，所述第三控制线和所述第三测试数据线沿所述第一边界的延伸方向延伸；
    所述第二薄膜晶体管包括：第二源极，第二漏极和第二栅极，所述第二源极与所述第三测试数据线电连接，所述第二漏极与所述多条第一数据传输线中的一条电连接，所述第二栅极与所述第三控制线电连接。
  13. 根据权利要求12所述的显示基板，其中，
    所述第二子电路包括：第三薄膜晶体管，第四薄膜晶体管，第四控制线，第四测试数据线，以及第五测试数据线，所述第四控制线，所述第四测试数据线，以及所述第五测试数据线沿所述第一边界的延伸方向延伸；
    所述第三薄膜晶体管包括：第三源极，第三漏极和第三栅极，所述第三源极与所述第四测试数据线电连接，所述第三漏极与所述多条第二数据传输线中的一条电连接，所述第三栅极与所述第四控制线电连接；
    所述第四薄膜晶体管包括：第四源极，第四漏极和第四栅极，所述第四源极与所述第五测试数据线电连接，所述第四漏极与所述多条第二数据传输线中的一条电连接，所述第四栅极与所述第四控制线电连接。
  14. 根据权利要求13所述的显示基板，其中，所述第三子电路包括：第五薄膜晶体管，第六薄膜晶体管，第五控制线，第六测试数据线，以及第七测试数据线；所述第五控制线，所述第六测试数据线和所述第七测试数据线沿所述第一边界的延伸方向延伸；
    所述第五薄膜晶体管包括：第五源极，第五漏极和第五栅极，所述第五源极与所述第六测试数据线电连接，所述第五漏极与所述多条第二数据传输线中的一条电连接，所述第五栅极与所述第五控制线电连接；
    所述第六薄膜晶体管包括：第六源极，第六漏极和第六栅极，所述第六源极与所述第七测试数据线电连接，所述第六漏极与所述多条第二数据传输线中的一条电连接，所述第六栅极与所述第五控制线电连接。
  15. 根据权利要求10至14任一所述的显示基板，其中，所述显示基板还包括：多个第二测试虚设电路，所述多个第二测试虚设电路在沿所述第一边界 的延伸方向上，位于所述多个第二测试电路的两侧且位于多个静电释放虚设电路和所述多个第一测试虚设电路之间，所述多个第二测试虚设电路通过所述多条数据传输虚设线与所述第一测试虚设电路以及所述静电释放虚设电路电连接。
  16. 根据权利要求15所述的显示基板，其中，所述多个第二测试虚设电路中的至少一个所述第二测试虚设电路包括：第一虚设子电路，第二虚设子电路和第三虚设子电路，所述第二虚设子电路位于所述第一虚设子电路与所述第三虚设子电路之间，所述第一虚设子电路位于所述第二虚设子电路远离所述多个子像素的一侧。
  17. 根据权利要求16所述的显示基板，其中，所述多条数据传输虚设线包括：多条第一数据传输虚设线和多条第二数据传输虚设线，所述多条第一数据传输虚设线和所述多条第二数据传输虚设线一一交替排布；
    所述第一虚设子电路包括：第二虚设薄膜晶体管，第六控制线，以及第八测试数据线，所述第六控制线和所述第八测试数据线沿所述第一边界的延伸方向延伸，所述第二虚设薄膜晶体管包括：第二虚设源极，第二虚设漏极和第二虚设栅极，所述第二虚设漏极与所述多条第一数据传输虚设线中的一条电连接，所述第二虚设栅极与所述第六控制线电连接。
  18. 根据权利要求17所述的显示基板，其中，
    所述第二虚设子电路包括：第三虚设薄膜晶体管，第四虚设薄膜晶体管，第七控制线，第九测试数据线，以及第十测试数据线，所述第七控制线，所述第九测试数据线，以及所述第十测试数据线沿所述第一边界的延伸方向延伸；
    所述第三虚设薄膜晶体管包括：第三虚设源极，第三虚设漏极和第三虚设栅极，所述第三虚设漏极与所述多条第二数据传输虚设线中的一条电连接，所述第三虚设栅极与所述第七控制线电连接；
    所述第四虚设薄膜晶体管包括：第四虚设源极，第四虚设漏极和第四虚设栅极，所述第四虚设漏极与所述多条第二数据传输线中的一条电连接，所述第四虚设栅极与所述第七控制线电连接。
  19. 根据权利要求18所述的显示基板，其中，所述第三虚设子电路包括：第五虚设薄膜晶体管，第六虚设薄膜晶体管，第八控制线，第十一测试数据线，以及第十二测试数据线；所述第八控制线，所述第十一测试数据线和所述第十二测试数据线沿所述第一边界的延伸方向延伸；
    所述第五虚设薄膜晶体管包括：第五虚设源极，第五虚设漏极和第五虚设栅极，所述第五虚设漏极与所述多条第二数据传输线中的一条电连接，所述第五虚设栅极与所述第八控制线电连接；
    所述第六虚设薄膜晶体管包括：第六虚设源极，第六虚设漏极和第六虚设栅极，所述第六虚设漏极与所述多条第二数据传输线中的一条电连接，所述第六虚设栅极与所述第八控制线电连接。
  20. 根据权利要求15至19任一所述的显示基板，其中，所述第二测试虚设电路的数量与所述静电释放虚设电路的数量以及所述第一测试虚设电路的数量相同，每个所述静电释放虚设电路通过一个所述第二测试虚设电路与一个所述第一测试虚设电路电连接。
  21. 根据权利要求1至20任一所述的显示基板，其中，所述显示基板还包括：至少一个第一信号输入端；
    所述至少一个第一信号输入端与所述面板裂纹检测走线中第一走线段中的第三子走线连接，所述至少一个第一信号输入端被配置为接收测试信号，以对所述显示基板进行检测。
  22. 根据权利要求21所述的显示基板，其中，所述至少一个第一信号输入端包括两个第一信号输入端，所述两个第一信号输入端分别位于所述第一测试电路的两侧。
  23. 根据权利要求1至22任一所述的显示基板，其中，所述显示基板还包括：第一检测端和第二检测端；
    所述第一检测端与所述面板裂纹检测走线中第一走线段中的第一子走线连 接，用于为所述第一子走线提供检测信号；
    所述第二检测端与所述面板裂纹检测走线中第一走线段中的第二子走线连接，用于接收所述检测信号，以对所述显示基板进行检测。
  24. 根据权利要求1至23任一所述的显示基板，其中，所述多个静电释放虚设电路中的至少一个所述静电释放虚设电路包括：静电防护线，至少一个第一放电晶体管，以及至少一个第二放电晶体管；
    所述至少一个第一放电晶体管的第一极和栅极均与所述面板裂纹检测走线电连接，所述至少一个第一放电晶体管的第二极与所述静电防护线电连接；
    所述至少一个第二放电晶体管的第一极和栅极均与所述静电防护线电连接，所述至少一个第二放电晶体管的第二极与所述面板裂纹检测走线电连接。
  25. 根据权利要求1至24任一所述的显示基板，其中，所述多个静电释放虚设电路沿所述显示区域的边界均匀分布在所述周边区域。
  26. 一种显示装置，其中，所述显示装置包括：如权利要求1至25任一所述的显示基板。
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