WO2021217295A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2021217295A1
WO2021217295A1 PCT/CN2020/086997 CN2020086997W WO2021217295A1 WO 2021217295 A1 WO2021217295 A1 WO 2021217295A1 CN 2020086997 W CN2020086997 W CN 2020086997W WO 2021217295 A1 WO2021217295 A1 WO 2021217295A1
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WIPO (PCT)
Prior art keywords
sub
signal line
power signal
pixel
electrode
Prior art date
Application number
PCT/CN2020/086997
Other languages
English (en)
French (fr)
Inventor
刘彪
都蒙蒙
董向丹
马宏伟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/428,402 priority Critical patent/US20220320247A1/en
Priority to EP20929680.5A priority patent/EP4145526A4/en
Priority to PCT/CN2020/086997 priority patent/WO2021217295A1/zh
Priority to CN202080000606.9A priority patent/CN114097089A/zh
Priority to PCT/CN2020/114559 priority patent/WO2021217993A1/zh
Priority to US17/299,565 priority patent/US11903274B2/en
Priority to CN202080002061.5A priority patent/CN114097090A/zh
Priority to EP20904234.0A priority patent/EP4145519A4/en
Priority to PCT/CN2020/114623 priority patent/WO2021217994A1/zh
Priority to PCT/CN2020/118962 priority patent/WO2021218030A1/zh
Priority to US17/430,675 priority patent/US20220052147A1/en
Priority to EP20931708.0A priority patent/EP4145527A4/en
Priority to CN202080002176.4A priority patent/CN113853684A/zh
Publication of WO2021217295A1 publication Critical patent/WO2021217295A1/zh
Priority to US18/539,847 priority patent/US20240114736A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • Organic light-emitting diodes have the advantages of self-luminescence, high efficiency, bright colors, light weight and power saving, etc., and have been gradually used in large-area display, lighting, and vehicle display fields.
  • a two-layer power signal line structure can be adopted, and the power signal line near the light-emitting layer of the organic light-emitting diode forms a grid pattern to reduce the voltage drop of the power signal line .
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate; a first power signal line located on the base substrate, and the first power signal line includes a plurality of first power signal lines extending in a first direction.
  • the pixel defining layer is located in the first power source
  • the signal line is away from the side of the base substrate, the pixel defining layer includes a plurality of openings to define the effective light-emitting area of a plurality of sub-pixels, and the plurality of sub-pixels includes two sub-pixels arranged along the second direction.
  • a pair of sub-pixels the pair of sub-pixels includes two sub-effective light-emitting regions with a space therebetween.
  • the first sub-power signal line passes through the interval between the two sub-effective light-emitting areas
  • at least one of the second sub-power signal lines includes at least one break
  • the two sub-effective light-emitting areas are located in
  • the intervals between the two sub-effective light-emitting areas are both located at the fracture, so that a virtual straight line extending in the second direction that connects the two end points of the same fracture of the second sub-power signal line penetrates The two sub-effective light-emitting areas and the interval.
  • the second sub-power signal line with the fracture does not overlap with the two sub-effective light-emitting areas and the interval.
  • the display substrate further includes: a plurality of second power signal lines extending along the second direction and located between the first power signal line and the base substrate, and The second power signal line and the second sub-power signal line are electrically connected through a via in an insulating layer between the second sub-power signal line and the second power line.
  • the orthographic projection of the second sub-power signal line on the base substrate and the orthographic projection of the second power signal line on the base substrate at least partially overlap, and the two sub-effective light-emitting areas are in The orthographic projection on the base substrate overlaps the orthographic projection of the second power signal line on the base substrate.
  • the orthographic projection of the first sub-power signal line on the base substrate is the same as the two orthographic projections of the two sub-effective light-emitting areas on the base substrate.
  • the ratio of the distance between the two centers is 0.9 to 1.1.
  • the two centers of the two orthographic projections of the two sub-effective light-emitting regions on the base substrate are located on the front of the second power signal line on the base substrate.
  • the display substrate includes a plurality of repeating units located on the base substrate, and each of the plurality of repeating units includes a first Color sub-pixels, a second color sub-pixel pair, and a third-color sub-pixel, the second-color sub-pixel pair includes two second-color sub-pixels of the same color, and the second color sub-pixels are arranged along the second direction
  • the sub-pixel pair composed of two sub-pixels is the second-color sub-pixel pair;
  • the first-color sub-pixel includes a first effective light-emitting area, and the two sub-effective light-emitting areas are two second effective light-emitting areas,
  • the third color sub-pixel includes a third effective light-emitting area.
  • the size of the interval is smaller than the size of the first effective light-emitting area, and the size of the interval is smaller than the size of the third effective light-emitting area.
  • the first effective light-emitting area in a direction perpendicular to the base substrate, does not overlap with the second sub power signal line and the second power signal line.
  • the first effective light-emitting area is located between the adjacent second sub-power signal lines, and the first effective light-emitting area is located between the adjacent second power signal lines. Between the lines.
  • the center of the orthographic projection of the first effective light-emitting area on the base substrate is located within the orthographic projection of the first sub-power signal line on the base substrate.
  • the display substrate further includes: a plurality of pads extending along the second direction and arranged in the same layer as the first power signal line.
  • the distances between the two second sub-power signal lines located on both sides of the first effective light-emitting area and adjacent to the first effective light-emitting area from the center line of the first effective light-emitting area extending along the second direction are not equal , And the first effective light-emitting area is located between the pad block and the second sub-power signal line that is closer to the center line of the first effective light-emitting area.
  • the center line of the first effective light-emitting area is in contact with the spacer and the second sub-block located on both sides of the first effective light-emitting area.
  • the distance ratio of the power signal line is 0.9 to 1.1.
  • the spacer block and the first sub-power signal line overlap and are electrically connected to each other.
  • the shape of the spacer block is roughly elongated, and the center of the orthographic projection of the spacer block on the base substrate is located where the first sub-power signal line is located. In the orthographic projection on the base substrate.
  • the spacer block is arranged between the first color sub-pixel and the third color sub-pixel arranged along the first direction and adjacent to each other, and the spacer The block is electrically connected to the second sub power signal line located between the first color sub pixel and the third color sub pixel.
  • the display substrate further includes: a connecting portion, which is provided on the same layer as the spacer block and located between the second sub-power signal line and the spacer block.
  • the pad block is connected to the second sub-power signal line through the connecting portion.
  • connection portion is located between the pad block and the second sub power signal line.
  • the connecting portion, the spacer block, and the second sub-power signal line form a ring structure.
  • the plurality of second sub-power signal lines include first sub-signal lines and second sub-signal lines that are alternately arranged along the first direction, and the first sub-signal lines are A continuous signal line, and the second sub-signal line is a signal line with the break.
  • the spacer block is connected to the second sub-signal line through the connecting portion, and the spacer block is opposite to the second sub-signal line connected to the spacer block.
  • the orthographic projection of another adjacent second sub-signal line is located in the fracture of the other second sub-signal line.
  • the size of the spacer is smaller than the size of the first effective light-emitting area.
  • the third effective light-emitting area does not overlap with the second sub power signal line and the second power signal line.
  • the third effective light-emitting area is located between the adjacent second sub-power signal lines, and the third effective light-emitting area is located between the adjacent second power signal lines. Between the lines.
  • the center of the orthographic projection of the third effective light-emitting area on the base substrate is located within the orthographic projection of the first sub-power signal line on the base substrate.
  • the two second sub-power signal lines located on both sides of the third color sub-pixel and immediately adjacent to the third color sub-pixel are directly on the base substrate.
  • the ratio of the distance between the projection and the center of the orthographic projection of the third effective light-emitting area on the base substrate is 0.9-1.1.
  • each of the sub-pixels includes an organic light-emitting element
  • the organic light-emitting element includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence, and at least part of the light-emitting layer is located at the In the opening, and the second electrode is located on the side of the pixel defining layer facing the base substrate, the area of the first effective light-emitting area and the second electrode in the first color sub-pixel
  • the ratio is 53% to 55%; in the second color sub-pixel pair, the area ratio of the two second effective light-emitting regions to the two second electrodes is 43.5% to 48%; the third color sub-pixel Wherein, the area ratio of the third effective light-emitting region to the second electrode is 67.5% to 69%.
  • the shape of the first effective light-emitting area and the third effective light-emitting area includes a hexagon or an ellipse
  • the second color sub-pixel pair includes each of the second
  • the shape of the effective light-emitting area includes a pentagon, a circle, or a drop shape.
  • the second electrode of each color sub-pixel includes a main body electrode and a connection electrode that are connected to each other, and the shape of the main body electrode is approximately the same as the shape of the effective light-emitting area of the corresponding sub-pixel; each In the sub-pixel, the portion where the connection electrode is connected to the main electrode is provided with a notch, and along a direction perpendicular to the base substrate, the display substrate is located in an area corresponding to at least a part of the notch. It is a transparent area.
  • the display substrate further includes: a plurality of data lines extending along the second direction and arranged in the same layer as the second power signal line; and a plurality of scanning signal lines along the It extends in the first direction and is located on the side of the film layer where the data line is located facing the base substrate; a plurality of reset power signal lines extend along the first direction and are located between the film layer where the scan signal line is located and the base substrate. Between the film layers where the data line is located; a plurality of reset control signal lines extending along the first direction and arranged in the same layer as the scan signal line; and a plurality of light emitting control signal lines along the first direction It extends and is arranged on the same layer as the scanning signal line.
  • Each of the sub-pixels further includes a pixel circuit that drives the organic light-emitting element, and the pixel circuit includes a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first light emission control transistor, a second light control transistor, and a first light-emitting control transistor.
  • a reset transistor and a second reset transistor the first electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the data writing transistor is electrically connected to the data line to receive Data signal, the gate of the data writing transistor is electrically connected to the scan signal line to receive the scan signal; the first pole of the storage capacitor is electrically connected to the second power signal line, and the first pole of the storage capacitor is electrically connected to the second power signal line.
  • the two electrodes are electrically connected to the gate of the driving transistor; the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor.
  • the gate of the threshold compensation transistor is electrically connected to the scan signal line to receive the compensation control signal; the first electrode of the first reset transistor is electrically connected to the reset power signal line to receive the first reset Signal, the second electrode of the first reset transistor is electrically connected to the gate of the driving transistor, and the gate of the first reset transistor is electrically connected to the reset control signal line to receive the first sub-reset control signal;
  • the first electrode of the second reset transistor is electrically connected to the reset power signal line to receive a second reset signal, the second electrode of the second reset transistor is electrically connected to the first electrode of the organic light emitting element, so
  • the gate of the second reset transistor is electrically connected to the reset control signal line to receive a second sub-reset control signal; the first pole of the first light-emitting control transistor
  • the display substrate further includes a first connection portion, a second connection portion, and a third connection portion provided on the same layer as the data line, and a fourth connection portion provided on the same layer as the first power signal line.
  • the first connection part is configured to connect the second electrode of the threshold compensation transistor and the gate of the driving transistor
  • the second connection part is configured to connect the reset power signal line and the second reset transistor.
  • the first pole, the third connecting portion is configured to connect the second pole of the second light-emitting control transistor and the fourth connecting portion
  • the fourth connecting portion is configured to connect the third connecting portion and The connection electrode of the second electrode of the organic light emitting element.
  • the transparent area includes the pixel circuit, the first power signal line, the second power signal line, the data line, the scan signal line, and the The reset power supply signal line, the reset control signal line, and the area of the light emission control signal line.
  • the active semiconductor layer including the channel region and the source and drain doped regions of each transistor of each sub-pixel and the area surrounded by the first electrode of the storage capacitor and the second electrode of the first color sub-pixel The notches overlap.
  • the light emission control signal line and the light emission control signal line of the pixel circuit connected to the first sub-pixel of the second color sub-pixel pair A part of the area surrounded by the second power signal line and the first electrode of the storage capacitor close to the light emission control signal line overlaps with the notch of the second electrode of the first sub-pixel.
  • the connection electrode in the second sub-pixel of the second color sub-pixel pair, includes a first portion extending in the second direction and a curved second portion.
  • One part is located on the side of the second part away from the main body electrode, the second part is connected to the main body electrode, and the maximum dimension of the first part along the first direction is larger than that of the second part along the The maximum size in the first direction.
  • connection electrode does not overlap the source and drain doped regions of the first light-emitting control transistor.
  • the light emission control signal line, the second power signal line, and the pixel circuit of the second sub-pixel are connected to A part of the area surrounded by the third connecting portion that is close to the second power signal line and the light emission control signal line overlaps with the notch of the second electrode of the second sub-pixel.
  • the data line of the pixel circuit connected to the second sub-pixel, the active semiconductor layer, and the storage overlaps with the notch of the second electrode of the third color sub-pixel.
  • the first color subpixel is a red subpixel
  • the second color subpixel is a green subpixel
  • the third color subpixel is a blue subpixel
  • At least one embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • 1A is a plan view of the positional relationship between a first power signal line and an effective light-emitting area in a display substrate according to an embodiment of the present disclosure
  • FIG. 1B is a plan view of the positional relationship between the first power signal line, the second power signal line, and the effective light-emitting area in the display substrate shown in FIG. 1A;
  • Fig. 2 is a partial cross-sectional structural diagram taken along the line AA' shown in Figs. 1A and 1B;
  • Fig. 3A is a partial cross-sectional structural diagram taken along BB' shown in Figs. 1A and 1B;
  • Fig. 3B is a schematic partial cross-sectional structure diagram taken along CC' shown in Fig. 1B;
  • Fig. 3C is a cross-sectional view taken along the line BB' shown in Fig. 1B in another example of the embodiment of the disclosure;
  • FIG. 4 is a schematic diagram of a pixel circuit connected to an organic light-emitting element included in each sub-pixel;
  • 5 to 11 are schematic diagrams of a pixel circuit and each layer stack of each signal line provided by some embodiments of the present disclosure.
  • FIG. 12 is a schematic plan view of organic light-emitting elements corresponding to each pixel circuit structure shown in FIG. 11 in a one-to-one manner;
  • FIG. 13 is a schematic diagram of the planar shape of the second electrode of each sub-pixel.
  • FIG. 14 is a schematic diagram of a planar structure of a second electrode of each sub-pixel in a display substrate.
  • the organic light-emitting diode display device includes a pixel defining layer.
  • the pixel defining layer includes an opening for defining the light-emitting area of the sub-pixel, and the opening exposes the anode of the organic light-emitting element.
  • the light-emitting layer of the subsequent organic light-emitting element is formed on the pixel defining layer
  • the light-emitting layer is in contact with the anode, so that this part can drive the light-emitting layer to emit light to form a light-emitting area.
  • the inventor of the present application found that in the organic light emitting diode display, when the power signal line on the side of the light emitting layer of the organic light emitting diode overlaps with the opening, the power signal line located in the light emitting area is likely to cause color shift Phenomenon.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a first power signal line on the base substrate, and a pixel defining layer on a side of the first power signal line away from the base substrate.
  • the first power signal line includes a plurality of first sub power signal lines extending in a first direction and a plurality of second sub power signal lines extending in a second direction, the first sub power signal lines are connected to the second sub power signal lines
  • the pixel defining layer includes a plurality of openings to define the effective light-emitting area of a plurality of sub-pixels, the plurality of sub-pixels include a sub-pixel pair composed of two sub-pixels arranged in a second direction, and the sub-pixel pair includes two sub-effective emission with a space therebetween.
  • the first sub-power signal line passes through the interval between the two sub-effective light-emitting areas, at least one second sub-power signal line includes a break, the two sub-effective light-emitting areas and the interval between the two sub-effective light-emitting areas are equal Located at the fracture, so that the virtual straight line extending in the second direction connecting the two end points of the same fracture of the second sub-power signal line penetrates the two sub-effective light-emitting areas and the interval.
  • a break is provided in the second sub-power signal line to reduce the overlapping area of the two sub-effective light-emitting areas and the first power signal line, so as to avoid the color shift of the sub-pixel pair during display.
  • FIG. 1A is a plan view of the positional relationship between the first power signal line and the effective light-emitting area in the display substrate according to an embodiment of the present disclosure
  • FIG. 1B is the first power signal line and the second power signal line in the display substrate shown in FIG. 1A.
  • FIG. 2 is a schematic partial cross-sectional structure diagram taken along the line AA′ shown in FIG. 1A and FIG. 1B.
  • the display substrate includes a base substrate 100 and a plurality of repeating units 200 on the base substrate 100.
  • Each repeating unit 200 includes a first-color sub-pixel 210, a second-color sub-pixel pair 220, and a third-color sub-pixel 230 arranged along a first direction (the X-direction shown in the figure).
  • the two second-color sub-pixels included in the pixel pair 220 are arranged along a second direction (the Z direction shown in the figure, which is different from the first direction).
  • a plurality of repeating units 200 are arranged along the first direction to form a plurality of repeating unit groups, the plurality of repeating unit groups are arranged along the second direction, and adjacent repeating unit groups in the plurality of repeating unit groups are staggered from each other in the first direction, that is, ,
  • the adjacent repeating unit group has a certain offset along the first direction. Therefore, the sub-pixels of the same color in adjacent repeating unit groups are not aligned in the second direction.
  • the arrangement of pixels in the odd row repeating unit group is the same, and the pixel arrangement in the even row repeating
  • the offset of the adjacent repeating unit group in the first direction is approximately half of the size of the repeating unit 200 in the first direction.
  • the size of the repeating unit 200 in the first direction is the pitch of the repeating unit 200 in the first direction.
  • the pitch here refers to the distance between the centers of the light-emitting areas of two first-color sub-pixels 210 in two adjacent repeating units 200 along the first direction
  • the center of the light-emitting area here refers to the geometric center of the planar shape of the light-emitting area. .
  • the above-mentioned first direction and second direction are respectively two directions perpendicular to each other in the same plane.
  • the plane is a plane where pixels are arranged.
  • the repeating unit here only refers to the repeating of sub-pixels, and other structures may be different or the same.
  • the above-mentioned repetition means that the approximate position, shape, and size are about the same. In some cases, for wiring or opening needs, the shape may be slightly different, such as openings in different positions.
  • the first color subpixel 210 may be a red subpixel
  • the second color subpixel pair 220 may be a green subpixel pair
  • the third color subpixel 230 may be a blue subpixel. But it is not limited to this, and the sub-pixels of each color can be interchanged.
  • the display substrate further includes a first power signal line 400 located on the base substrate 100, and the first power signal line 400 includes a plurality of first sub power signal lines 410 and There are a plurality of second sub-power signal lines 420 extending in the second direction, and the first sub-power signal line 410 is connected to the second sub-power signal line 420.
  • the display substrate further includes a pixel defining layer 130 located on the side of the first power signal line 400 away from the base substrate 100.
  • the pixel defining layer 130 includes a plurality of openings to limit the effective light emission of each sub-pixel. Area.
  • the "effective light-emitting area" herein may refer to a two-dimensional planar area, which is parallel to the base substrate. It should be noted that, due to process reasons, the size of the opening of the pixel defining layer is slightly larger than the size of the part close to the base substrate, or appears from the side close to the base substrate to the side away from the base substrate.
  • the size is gradually increasing, so the size of the effective light-emitting area may be slightly different from the size of the different positions of the pixel defining layer opening, but the overall area shape and size are basically the same.
  • the projection of the effective light-emitting area on the base substrate roughly coincides with the projection of the opening of the corresponding pixel defining layer on the base substrate.
  • the projection of the effective light-emitting area on the base substrate completely falls within the projection of the opening of the corresponding pixel defining layer on the base substrate, and the shapes of the two are similar.
  • the projected area of the effective light-emitting area on the base substrate is compared
  • the projection of the opening of the corresponding pixel defining layer on the base substrate is slightly smaller.
  • each sub-pixel includes an organic light-emitting element
  • the organic light-emitting element includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence, at least part of the light-emitting layer is located in the opening, and the second electrode is located on the pixel defining layer facing the base substrate On the side.
  • the second color sub-pixel includes an organic light-emitting element
  • the organic light-emitting element includes a first electrode 221 and a second electrode 222.
  • the light emitting layer 223 located between the first electrode 221 and the second electrode 222.
  • the opening of the pixel defining layer 130 exposes a part of the second electrode 222.
  • the light emitting layer 223 is formed in the opening of the pixel defining layer 130, the light emitting layer 223 is in contact with the second electrode 222, so that this part can drive the light emitting layer to emit light to form The second effective light-emitting area 2200.
  • the second color sub-pixel pair 220 includes two second effective light-emitting regions 2201 and 2202.
  • the embodiments of the present disclosure are described by taking as an example that the light emitting layers of the two second color sub pixels included in the second color sub pixel pair are integrated.
  • the light emitting layers of the two second color sub pixels of the second color sub pixel pair are The connected overall film layer, that is, the light-emitting layers of the two second-color sub-pixels are a continuous and complete pattern, or the projection of the light-emitting layers of the two second-color sub-pixels on the base substrate is continuous and complete.
  • the light-emitting layer of the second color sub-pixels can be fabricated through an opening. But it is not limited to this.
  • the light-emitting layers of the two second-color sub-pixels included in the second-color sub-pixel pair may also be separated.
  • the first color sub-pixel 210 includes a first effective light-emitting area 2100
  • the second color sub-pixel pair includes two second effective light-emitting areas 2200 (including the first effective light-emitting area) spaced apart from each other.
  • the third color sub-pixel 230 includes the third effective light-emitting area 2300.
  • the part of the light-emitting layer in the opening of the pixel defining layer that is in contact with the second electrode is used as an effective light-emitting area for illustration.
  • the "space" in the above-mentioned "the second color sub-pixel pair includes two second effective light-emitting regions 2200 with an interval between each other” refers to the physical part of the pixel defining layer between the two openings defined by the pixel defining layer.
  • the orthographic projection of the interval S on a straight line extending in the X direction may substantially coincide with the orthographic projection of the second color sub-pixel pair on a straight line extending in the X direction.
  • the projection is located between two orthographic projections of the second color sub-pixel pair on a straight line extending in the Z direction.
  • the first sub-power signal line 410 passes through two second effective light-emitting
  • At least one of the second sub power signal lines 420 includes a break 421 between the areas 2200, and the two second effective light-emitting areas 2200 and the interval are located at the break 421, so that the second sub power signal line 420 does not pass through the two second light emitting areas.
  • the virtual straight line 4210 connecting the end points on both sides of the fracture 421 and extending in the Z direction passes through the two second effective light-emitting areas 2200 and the interval S between the two second effective light-emitting areas 2200.
  • the above-mentioned "break" means that the second sub-power signal line 420 is not a continuous signal line, and the signal line includes a plurality of signal line segments that are disconnected from each other, and the interval between two adjacent signal line segments is the above-mentioned break 421.
  • the second sub-power signal 420 line with the break 421 does not overlap with the two second effective light-emitting regions 2200 and the interval S.
  • the two second effective light-emitting regions 2200 and the first power signal line 400 do not overlap. That is, in the direction perpendicular to the base substrate 100, the two second effective light-emitting regions 2200 overlap with the fracture 421, but do not overlap with the second sub-power signal line 420, and the two second effective light-emitting regions 2200 overlap with each other.
  • the first sub-power signal line 410 also does not overlap. Therefore, along the direction perpendicular to the base substrate, the two second effective light-emitting areas included in the second color sub-pixel pair do not overlap with the first power signal line, so as to increase the first effective light-emitting area located in the two second effective light-emitting areas.
  • the flatness of the film layer on the side of the two electrodes away from the light-emitting layer can try to avoid the color shift of the second color sub-pixel pair during display.
  • the size of the interval between the two second effective light-emitting regions 2200 in the second direction is smaller than the size of the first effective light-emitting region 2100 in the second direction, and the two second effective light-emitting regions The size of the interval between the regions 2200 in the second direction is smaller than the size of the third effective light-emitting region 2300 in the second direction.
  • the size of the first effective light-emitting area 2100 is larger than the size of the third effective light-emitting area 2300.
  • the size of the first effective light-emitting area 2100 may be 45-49 microns, for example, 47 microns;
  • the size of the three effective light-emitting area 2300 may be 38 to 42 microns, for example, it may be 40 microns.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 and the two orthographic projections of the two second effective light-emitting regions 2200 on the base substrate 100 The ratio of the distance between the centers is 0.9 to 1.1.
  • the distance between the orthographic projection of the first sub-power signal line 410 on the base substrate 100 and the two orthographic projections of the two second effective light-emitting regions 2200 on the base substrate 100 is approximately the same.
  • the two second effective light-emitting areas included in the second color sub-pixel pair are symmetrically distributed with respect to the first sub-power signal line, which is beneficial to ensure that the environment of the two second-color sub-pixels included in the second color sub-pixel pair is consistent.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 can also be closer to one of the second color sub-pixel pairs.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 and the projection of the second electrodes of the two second-color sub-pixels in the second-color sub-pixel pair do not overlap.
  • the center of the above-mentioned orthographic projection refers to the geometric center of the shape of the orthographic projection.
  • the shape of the orthographic projection of the effective light-emitting area on the base substrate is determined by the shape of the effective light-emitting area.
  • the shape of the effective light-emitting area and the corresponding shape of the opening of the pixel defining layer are roughly same.
  • each second effective light-emitting area 2200 included in the second color sub-pixel pair 220 includes a pentagon, a circle, or a drop shape.
  • FIGS. 1A and 1B schematically show that the shape of each second effective light-emitting area 2200 is a pentagon, which includes a set of parallel opposite sides (parallel to the second direction) and a vertical side (parallel In the first direction), the vertical side is perpendicular to a set of parallel opposite sides, and the two vertical sides of the two second effective light-emitting regions 2200 in each second color sub-pixel pair 220 are arranged adjacent to each other.
  • the first sub power signal line 410 is located between the two vertical sides and passes through the midpoint of the shortest line between the two vertical sides.
  • the shape of the second effective light-emitting area of the second color sub-pixel in FIGS. 1A and 1B includes a strictly angle formed by two line segments
  • the shape of the effective light-emitting area may be rounded corners, such as a circle or a drop shape. That is, on the basis of the above-mentioned pentagonal shape, the corners of the second effective light-emitting area of the second color sub-pixel are rounded. For example, when the opening of the pixel defining layer is formed, the corners of the opening may be rounded, and the shape of the formed light-emitting area may be rounded.
  • the display substrate further includes: a second power signal line 500 located between the first power signal line 400 and the base substrate 100, and the second power signal line 500 extends along the second direction.
  • the orthographic projection of the second sub-power signal line 420 on the base substrate 100 and the orthographic projection of the second power signal line 500 on the base substrate 100 at least partially overlap, and the two second effective light-emitting areas 2200 are on the base substrate.
  • the orthographic projection on 100 and the orthographic projection of the second power signal line 500 on the base substrate 100 overlap. That is, along the direction perpendicular to the base substrate 100, the break 421 overlaps the second power signal line 500.
  • the orthographic projection of the second sub power signal line 420 on the base substrate 100 is within the orthographic projection of the second power signal line 500 on the base substrate 100.
  • the second power signal line may roughly coincide with the part of the second sub power signal line except for the break, but the line width of the second sub power signal line is partially adjusted without completely overlapping the second power signal line, for example, The area of the overlapping portion of the second power signal line and the second sub-power signal line accounts for more than 70% of the area of the second power signal line.
  • the width of the second sub-power signal line 420 in the first direction is slightly different.
  • the second sub-power signal line 420 corresponds to some The width at the position of the color sub-pixel decreases.
  • the width of the second power signal line 500 in the first direction at different positions in the extending direction thereof is slightly different.
  • two repeating units 200 located in the same repeating unit group and adjacent to each other include a first repeating unit 201 and a second repeating unit 202, and the third color sub-pixel of the first repeating unit 201 230 is adjacent to the first color sub-pixel 210 of the second repeating unit 202, and the repeating unit 200 adjacent to both the first repeating unit 201 and the second repeating unit 202 and located in the adjacent repeating unit group is the third repeating unit 203 .
  • a continuous second sub power signal line 420 that is, a first sub signal line 4201
  • a row of first-color sub-pixels 210 and a row of third-color sub-pixels 230 located on both sides of the continuous second sub-power signal line 420 and adjacent to the second sub-power signal line 420 are on the second sub-power signal line 420
  • the orthographic projections are alternately arranged in the second direction.
  • the width of the second sub power signal line 420 at the orthographic projection position of the first color sub pixel 210 on the continuous second sub power signal line 420 is the first width, the first color sub pixel 210 and the third color sub pixel 230.
  • the width of the second sub-power signal line 420 at the interval between two adjacent orthographic projections on the second sub-power signal line 420 is the second width, and the third color sub-pixel 230 is in the continuous first
  • the width of the second sub-power signal line 420 at the orthographic projection position on the second sub-power signal line 420 is a third width, the first width is smaller than the second width, and the third width is smaller than the second width.
  • the above-mentioned first width and third width may be the same or different, for example, the third width is smaller than the first width.
  • the continuous second sub-power signal line 420 includes a first segment and a second segment corresponding to the first color sub-pixel 210 and the third color sub-pixel 230, respectively, and a connection segment connecting the first segment and the second segment. Along the second direction, the first section and the second section of the continuous second sub power signal line 420 are alternately arranged.
  • the edge of the first segment away from the first center line of the corresponding first color sub-pixel 210 and the edge of the connecting segment away from the first center line are located on the same straight line extending in the second direction, and the edge of the first segment is close to the corresponding
  • the distance between the edge of the first center line of the first color sub-pixel 201 and the first center line is greater than the distance between the edge of the connecting section close to the first center line and the first center line.
  • the edge of the second segment away from the third center line of the corresponding third color sub-pixel and the edge of the connecting segment away from the third center line are located on the same straight line extending in the second direction, and the second segment is close to The distance between the edge of the third center line of the corresponding third color sub-pixel and the third center line is greater than the distance between the edge of the connecting section close to the third center line and the third center line. That is, the first segment and the connecting segments located on both sides of the first segment form a first depression that is recessed toward the first color sub-pixel, and the second segment and the connecting segments located on both sides of the second segment form a third color.
  • the arrangement of the second recessed portion, the first recessed portion and the second recessed portion of the sub-pixel can prevent the first and third effective light-emitting regions from overlapping with the second sub-power signal line, thereby reducing color shift.
  • a second sub-power signal line 420 including a break that is, the second sub-pixel Signal line 4202.
  • the first sub-signal lines 4201 and the second sub-signal lines 4202 are alternately arranged along the first direction, and the numbers are approximately equal.
  • the second sub-signal line 4202 includes a plurality of signal line segments that are disconnected from each other, and each signal line segment can communicate with the second power signal through a via in an insulating layer between the second power signal line and the second sub-signal line. The electrical connection of the wire.
  • the second sub-power signal line 420 (signal line segment) between two adjacent fractures arranged in the second direction includes a third segment, a fourth segment, and a fifth segment that are sequentially connected along the second direction.
  • the width of the third section may be approximately equal to the width of the fifth section, and the width of the third section and the width of the fifth section are both larger than the width of the fourth section.
  • the third segment, the fourth segment, and the fifth segment form a third recessed portion recessed toward the first color sub-pixel 210 in the second repeating unit 202.
  • the orthographic projection of the fourth segment on the base substrate falls within the orthographic projection of the second power signal line on the base substrate to prevent the light transmittance of the display substrate from being affected.
  • the fourth section of the second sub-power signal line is electrically connected to the first sub-power signal line.
  • the second power signal line 500 also has the same characteristics as the second sub-power signal line, which will not be repeated here.
  • the orthographic projection of the first effective light-emitting area 2100 of the first color sub-pixel 210 on the second sub-signal line 4202 does not overlap with the fracture 421, that is, the first effective light-emitting area 2100 of the first color sub-pixel 210 is in the second sub-signal line 4202.
  • the orthographic projection on the sub-signal line 4202 is located within the signal line segment.
  • the orthographic projection of the third effective light-emitting area 2300 of the third color sub-pixel 230 on the second sub-signal line 4202 does not overlap with the fracture 421, that is, the third effective light-emitting area 2300 of the third color sub-pixel 230 is in the second sub-signal line 4202.
  • the orthographic projection on the sub-signal line 4202 is located within the signal line segment.
  • the width of the first section of the second sub power signal line 420 in the first direction may be 2.5 to 3.7 microns, and the width of the connection section of the second sub power signal line 420 in the first direction may be 5.8 to 7 microns.
  • the distance between the connecting section of one of the two second sub-power supply lines 420 adjacent to and on both sides of the third color sub-pixel 230 and the adjacent edge of the third section of the other is approximately 23.4-26 micrometers. .
  • the second sub-power signal line 420 and the second power signal line 500 each have a partial area that has approximately the same width in the first direction and substantially completely overlaps.
  • the positions of the two edges of the fracture are both located in the substantially completely overlapping area of the second sub power signal line 420 and the second power signal line 500.
  • the distance between the edges of two adjacent fractures arranged in the second direction (that is, the length of one signal line segment) is greater than the size of one pixel circuit in the second direction.
  • the size of each fracture along the second direction is smaller than the size of one pixel circuit in the second direction.
  • the distance between the edges of two adjacent fractures arranged in the second direction is approximately 69-75 microns.
  • the size of the pixel circuit along the second direction is approximately 63-65 microns.
  • the size of the fracture along the second direction is approximately 52-57 microns.
  • the ratio of the size of the fracture in the second direction to the size of one pixel circuit in the second direction is 0.8-0.9.
  • the ratio of the distance between the adjacent edges of two adjacent fractures arranged in the second direction (that is, the length of one signal line segment) to the size of one pixel circuit in the second direction is 1.1-1.2.
  • Half of the value D1 can be 1.8 to 6.5 microns.
  • the ratio of the size D3 of the fracture 421 along the second direction to the sum D2 of the two second effective light-emitting regions 2200 and the interval S in the fracture 421 in the second direction may be 1.07-1.25.
  • a first flat layer 121 is provided between the first power signal line 400 and the second electrode of each sub-pixel to achieve a flattening effect.
  • a second flattening layer 122 and a passivation layer 123 are provided between the first power signal line 400 and the second power signal line 500 to achieve a flattening effect.
  • the embodiment of the present disclosure is not limited to the second flat layer 122 and the passivation layer 123 provided between the first power signal line 400 and the second power signal line 500, and only the second flat layer 122 may be provided without the passivation layer 123. .
  • the two orthographic projections of the two second effective light-emitting regions 2200 on the base substrate 100 have two centers located in the orthographic projection of the second power signal line 500 on the base substrate 100 Inside.
  • the second power signal line 500 passes through the center of the two second effective light-emitting areas, which can ensure the first
  • the second effective light-emitting area 2200 has better symmetry along the first direction to improve the color shift.
  • the distance between adjacent second sub-power signal lines 420 along the first direction is greater than the size of the first effective light-emitting area 2100 along the first direction, and the first effective light-emitting area 2100 is located between adjacent second sub-power signal lines 420. In the same way, the first effective light-emitting area 2100 is located between the adjacent second power signal lines 500.
  • the size of the first effective light-emitting area of the first color sub-pixel is smaller than the distance between two adjacent second sub-power signal lines.
  • the first effective light-emitting area By arranging the first effective light-emitting area on the adjacent second sub-power Between the signal lines, the first effective light-emitting area can be prevented from overlapping with the second sub-power signal line and the second power line, and the flatness of the film in the first effective light-emitting area can be improved, and the first effective light-emitting area in the first
  • the symmetry in the direction helps to improve the color cast.
  • the distance between adjacent second sub-power signal lines 420 along the first direction is greater than the size of the third effective light-emitting area 2300 along the first direction, and the third effective light-emitting area 2300 is located between adjacent second sub-power signal lines 420.
  • the width of the second sub-power signal line 420 at the position corresponding to the third color sub-pixel 230 is reduced, so that the edges of adjacent second sub-power signal lines 420 close to each other (corresponding to the position of the third effective light-emitting area)
  • the distance between the two edges at) in the first direction is greater than the size of the third effective light-emitting area 2300 in the first direction.
  • the third effective light-emitting area 2300 is located between the adjacent second power signal lines 500.
  • the size of the third effective light-emitting area of the third color sub-pixel is smaller than the distance between two adjacent second sub-power signal lines.
  • the orthographic projection of the second electrode of the third color sub-pixel 230 on the base substrate 100 and the second sub-power signal line 420 do not substantially overlap.
  • the width of the second sub power signal line 420 at a position corresponding to the third color sub pixel 230 is reduced, so that the edges of adjacent second sub power signal lines 420 close to each other (corresponding to the third color sub pixel).
  • the distance between the two edges at the second electrode position in the first direction is greater than the size of the second electrode of the third color sub-pixel 230 in the first direction.
  • a second sub-power signal line 420 is provided between the effective light-emitting regions of two adjacent sub-pixels arranged in the first direction, that is, the first effective light-emitting region 2100 and the second A second sub power signal line 420 is provided between the effective light-emitting areas 2200, a second sub power signal line 420 is provided between the second effective light-emitting area 2200 and the third effective light-emitting area 2300, and the third effective light-emitting area 2300 is connected to the A second sub-power signal line 420 is arranged between the first effective light-emitting areas 2100.
  • the plurality of second sub power signal lines 420 are evenly distributed in the first direction, that is, the intervals between the plurality of second sub power signal lines 420 are approximately equal.
  • the sides of the two second sub power signal lines 420 that are located on both sides of the first effective light-emitting area 2100 and are adjacent to the first effective light-emitting area 2100 are close to each other
  • the distance between is the first distance d1.
  • the first section of the second sub-power signal line 420 located on one side of the first effective light-emitting area 2100 and the third section of the second sub-power signal line 420 located on the other side of the first effective light-emitting area 2100 are close to each other.
  • the distance between the edges is the first distance for example.
  • the distance between the two second sub-power signal lines 420 located on both sides of the second effective light-emitting area 2200 and adjacent to the second effective light-emitting area 2200 is the second distance d2.
  • the first section of the second sub-power signal line 420 located on one side of the second effective light-emitting area 2200 and the second section of the second sub-power signal line 420 located on the other side of the second effective light-emitting area 220 are close to each other.
  • the distance between the edges is the second distance for example.
  • the distance between the two second sub-power signal lines 420 located on both sides of the third effective light-emitting area 2300 and adjacent to the third effective light-emitting area 2300 is the third distance d3.
  • the second section of the second sub-power signal line 420 located on one side of the third effective light-emitting area 2300 and the third section of the second sub-power signal line 420 located on the other side of the third effective light-emitting area 2300 are close to each other.
  • the distance between the edges is the third distance for example.
  • the ratio of the first distance to the third distance is 0.9-1.1.
  • the first distance and the third distance are approximately equal, and the second distance is approximately twice the first distance.
  • the above-mentioned second sub-power signal line located on both sides of the effective light-emitting area and adjacent to the effective light-emitting area refers to the first direction, and there is no other second sub-power signal line between the second sub-power signal line and the effective light-emitting area.
  • two second sub-power signal lines 420 located on both sides of the second-color sub-pixel pair 220 and adjacent to the second-color sub-pixel pair 220 are separated from the second-color sub-pixel pair 220.
  • the ratio of the distance of the second center line extending along the second direction of the second effective light-emitting area 2200 is 0.9-1.1, for example, two adjacent to the second color sub-pixel pair 220 located on both sides of the second color sub-pixel pair 220
  • the distance between the second sub-power signal line 420 and the second center line extending in the second direction of the second effective light-emitting area 2200 of the second color sub-pixel pair 220 is approximately the same.
  • the two second sub-power signal lines 420 located on both sides of the second effective light-emitting area 2200 and adjacent to the second effective light-emitting area 2200 are approximately symmetrically distributed with respect to the second center line, thereby ensuring the sub-pixel pairs of the second color. Symmetry of the second electrode in the first direction to improve color shift.
  • the two second sub-power signal lines 420 located on both sides of the third color sub-pixel 230 and adjacent to the third color sub-pixel 230 are separated from the third effective line of the third color sub-pixel 230.
  • the ratio of the distance of the third center line extending along the second direction of the light-emitting area 2300 is 0.9-1.1, for example, two second sub-power sources located on both sides of the third color sub-pixel 230 and adjacent to the third color sub-pixel 230
  • the distance between the signal line 420 and the third center line extending in the second direction of the third effective light-emitting region 2300 of the third color sub-pixel 230 is approximately the same.
  • the distance between the second sub power signal line 420 located on both sides of the third color sub-pixel 230 and the third center line may refer to the distance between the edge of the second sub power signal line 420 close to the third center line and the third center line.
  • the width of the second sub-power signal line 420 on the side of the third color sub-pixel 230 corresponds to the position of the third color sub-pixel 230, which is the second section of the second sub-power signal line 420,
  • the second segment forms a second recess with the connecting segment so that the edges of the two second sub power signal lines 420 that are located on both sides of the third color sub-pixel 230 and are adjacent to the third color sub-pixel 230 are respectively connected to each other.
  • the distances between the third center lines extending in the second direction of the third effective light-emitting area 2300 of the third color sub-pixel 230 are approximately equal.
  • the two second sub-power signal lines 420 located on both sides of the third effective light-emitting area 2300 and adjacent to the third effective light-emitting area 2300 are approximately symmetrically distributed with respect to the third center line, thereby ensuring that the second electrode of the third color sub-pixel is Symmetry in the first direction to improve color cast.
  • the two second sub-power signal lines 420 located on both sides of the first color sub-pixel 210 and adjacent to the first color sub-pixel 210 are separated from the first effective distance of the first color sub-pixel 210.
  • the distances of the first center lines extending along the second direction of the light-emitting area 2100 are not equal. That is, the two second sub-power signal lines 420 located on both sides of the first effective light-emitting area 2100 and immediately adjacent to the first effective light-emitting area 2100 are distributed asymmetrically with respect to the first center line.
  • the distance between the edge of the second sub-power signal line 420 located between the first effective light-emitting area 2100 and the second effective light-emitting area 2200 that is close to the first center line and the first center line is the fourth distance.
  • the edge of the first section of the second sub-power signal line 420 between the first effective light-emitting area 2100 and the second effective light-emitting area 2200 in the first repeating unit 201 is close to the first center line and the first center line.
  • the distance between is the fourth distance as an example.
  • the distance between the second sub-power signal line 420 located between the first effective light-emitting area 2100 and the third effective light-emitting area 2300 and the first center line is a fifth distance, and the fifth distance is greater than the fourth distance.
  • the third section of the second sub-power signal line 420 between the third effective light-emitting area 2300 in the first repeating unit 201 and the first effective light-emitting area 2100 in the second repeating unit 202 is close to the first centerline.
  • the distance between the edge of and the first centerline is the fifth distance as an example.
  • the distance between the second effective light-emitting area 2200 and the adjacent second sub-power signal line 420 opposite to each other is greater than the first effective light-emitting area 2100 and the adjacent second sub-power source.
  • the distance (PDL gap) between the light-emitting area boundaries of the sub-pixels of different colors is basically the same, that is, among the sub-pixels arranged in the first direction, the first effective light-emitting area
  • the ratio of the distance between the edges of the second effective light-emitting area 2100 and the second effective light-emitting area 2200 that are close to each other and the distance between the edges of the second effective light-emitting area 2200 and the third effective light-emitting area 2300 that are close to each other is, for example, 0.9-1.1.
  • the distance between the edges of the first effective light-emitting region 2100 and the second effective light-emitting region 2200 that are close to each other is substantially equal to the distance between the edges of the second effective light-emitting region 2200 and the third effective light-emitting region 2300 that are close to each other. Therefore, the distance between the second sub-power signal line located between the first effective light-emitting area and the second effective light-emitting area from the first center line is smaller than the first effective light-emitting area between the first effective light-emitting area and the third effective light-emitting area. The distance between the two sub-power signal lines and the first center line.
  • the display substrate further includes a plurality of pads 430 arranged on the same layer as the first power signal line 400, the pads 430 extend along the second direction, and the first effective light-emitting area 2100 is located on the pad Between the block 430 and the second sub-power signal line 420 which is close to the first center line (in the second sub-power signal line 420 immediately adjacent to the first effective light-emitting area 2100).
  • the distance between the edge of the spacer block 430 close to the first center line and the first center line of the first effective light-emitting area 2100 is the sixth distance, and the sixth distance is smaller than the fifth distance.
  • the ratio of the sixth distance to the fourth distance may be 0.9-1.1 to further improve the symmetry of the second electrode of the first color sub-pixel in the first direction.
  • the spacer 430 does not overlap the first effective light-emitting area 2100 to prevent the display of the first color sub-pixels from being affected.
  • the spacer block 430 and the second sub-power signal line 420 on the side of the first effective light-emitting area 2100 away from the spacer block 430 do not overlap.
  • the spacer 430 does not overlap with the second electrode of the first color sub-pixel, or the overlap area between the two is small, which is beneficial to reduce color shift.
  • the spacer 430 is located on a second sub-power signal line 420 disposed between the first color sub-pixel 210 and the third color sub-pixel 230, which is close to the first color sub-pixel 410. side.
  • the spacers in the embodiments of the present disclosure can reduce the distance between the film pattern of the first power signal line and the first center line, which is arranged on the side of the first effective light-emitting area away from the second effective light-emitting area, and is beneficial to improve the first color. Symmetry of the second electrode of the sub-pixel in the first direction to improve color shift.
  • the spacer 430 may be integrated with the first power signal line disposed on the side of the first effective light-emitting area away from the second effective light-emitting area, which is equivalent to the area where the first power signal line is close to the first color sub-pixel 210
  • the first power signal line is widened in the first direction, so that the distance between the edges on both sides of the first effective light-emitting area of the first color sub-pixel 210 and the film pattern where the first power signal line is located is equivalent, so as to reduce Color cast.
  • the part connected between the first pad 430 and the first power signal line may be a physical structure.
  • the part connected between the first pad 430 and the first power signal line can be a hollow structure, that is, a part of the pattern is removed between the first pad 430 and the first power signal line to reduce the overlap with the area.
  • the line width of the portion of the first pad block 430 close to the first color sub-pixel is not greater than the line width of the portion of the first power signal line close to the first color sub-pixel.
  • the length of the first effective light-emitting area of the first color sub-pixel in the second direction is greater than its width along the first direction, and the length of the first effective light-emitting area is consistent with the extension direction of the second sub-power signal line. Therefore, a pad extending in the second direction is provided on one side of the first effective light-emitting area along the first direction.
  • the length of the third effective light-emitting area of the third color sub-pixel in the second direction is greater than the width of the third effective light-emitting area in the first direction, and the aspect ratio of the first effective light-emitting area is greater than that of the third effective light-emitting area.
  • the first effective light-emitting area may have a large difference in the distance between its first center line and the two second sub-power signal lines located on both sides of the first effective light-emitting area.
  • the above-mentioned spacers are arranged on one side of the effective light-emitting area, which can reduce the color shift.
  • the distance between the center line of the first effective light-emitting area 2100 and the pad 430 and the second sub power signal line 420 located on both sides of the first effective light-emitting area 2100 Roughly equal. That is, the distance between the spacers 430 and the second sub-power signal line located on both sides of the first center line is approximately equal to the first center line, so that the second electrode of the first color sub-pixel can be further improved in the first direction.
  • the symmetry is conducive to improving the color cast.
  • the spacer block 430 is electrically connected to the first power signal line 400 to prevent the spacer block from being in a floating state, which affects the normal operation of the organic light emitting element.
  • the spacer block 430 overlaps with the first sub power signal line 410 and is electrically connected to each other.
  • the first sub power signal line 410 is a pad.
  • Block 430 provides electrical signals.
  • the first sub power signal line 410 can be integrally formed with the spacer block 430 to save process.
  • the shape of the spacer block 430 is approximately a long strip, and the center of the orthographic projection of the spacer block 430 on the base substrate 100 is located within the orthographic projection of the first sub-power signal line 410 on the base substrate 100.
  • the size of the spacer 430 in the second direction is larger than the size of the spacer 430 in the first direction.
  • the size of the spacer 430 is smaller than the size of the first effective light-emitting area 2100.
  • the size of the spacer along the second direction is designed to be smaller than the size of the first effective light-emitting area, for example, the spacer should not overlap the light-transmitting area (described later) as much as possible , Which is beneficial to improve the light transmittance of the display substrate.
  • the display substrate further includes a connecting portion 440 provided on the same layer as the spacer 430.
  • the connecting portion 440 is located between the second sub power signal line 420 (ie, the second sub signal line 4202) and the pad block 430, and the pad block 430 passes through the connecting portion 440 is connected to the second sub-power signal line 420.
  • the size of the connecting portion 440 along the second direction may be 36-40 micrometers, for example, it may be 38 micrometers.
  • the size of the connecting portion 440 is smaller than the sizes of the first effective light-emitting area 2100 and the third effective light-emitting area 2300.
  • the orthographic projection of the connecting portion 440 on a straight line extending in the second direction may be located within the orthographic projection of the third effective light-emitting area 2300 on the straight line.
  • the orthographic projection of the spacer 430 and the connecting portion 440 on a straight line extending in the second direction are both located within the orthographic projection of the third effective light-emitting area 2300 on the straight line.
  • the size of the spacer 430 in the second direction is smaller than the size of the third effective light-emitting area 2300 in the second direction.
  • the distance between the adjacent edges of the second sub power signal line 420 and the pad block 430 located between the connecting portion 440 and the third color sub-pixel 230 may be 11-13 microns, for example, 12 microns.
  • the connecting portion 440, the pad block 430, and the second sub power signal line 420 form a ring structure.
  • the connecting portion 440 includes two sub-connecting portions, and two ends of the spacer block 430 are electrically connected to the second sub-power signal line 420 through the two sub-connecting portions, respectively.
  • the connection part, the spacer block, and the second sub-power signal line connected to the connection part provided by the embodiment of the present disclosure form a circular loop, which is beneficial to the uniformity of the first color sub-pixels.
  • each sub-connection part along the second direction may be 2.5-3.5 micrometers, for example, it may be 3 micrometers.
  • the distance between the edges where the two sub-connections are close to each other may be 32 micrometers.
  • the connecting portion 440, the pad block 430, and the second sub-power signal line 420 are integrally arranged to save process steps.
  • the pad block 430 is connected to the second sub signal line 4202 through the connecting portion 440, and the pad block 430 is connected to the second sub signal line 4202 connected to the pad block 430 on another second sub signal line 4202.
  • the orthographic projection is located in the fracture 421 of the other second sub-signal line 4202.
  • the connecting portion and the transparent area do not overlap, which can ensure that the light transmittance of the display substrate is not affected.
  • FIG. 3A is a partial cross-sectional structural diagram taken along BB' shown in FIGS. 1A and 1B
  • FIG. 3B is a partial cross-sectional structural diagram taken along CC' shown in FIG. 1B.
  • the first effective light-emitting area 2100 does not overlap with the second sub-power signal line 420 and the second power signal line 500, thereby ensuring that the first The effective light-emitting area has good symmetry along the first direction to improve the color shift.
  • the third effective light-emitting area 2300 does not overlap with the second sub-power signal line 420 and the second power signal line 500, so as to ensure that the third effective light-emitting area extends along the first The direction has good symmetry.
  • the first center line of the first effective light-emitting area 2100 overlaps with the data line Vd (described later), so as to ensure that the first effective light-emitting area has a better shape along the first direction. symmetry.
  • the data line Vd penetrates the first effective light-emitting area 2100 along the second direction, so that the first effective light-emitting area 2100 has a certain uniformity along the second direction.
  • the “through” in the embodiments of the present disclosure refers to the positional relationship between the data line, the first power signal line, and other structures and the effective light-emitting area on the plane.
  • the shapes of the first effective light-emitting area 2100 of the first color sub-pixel 210 and the third effective light-emitting area 2300 of the third color sub-pixel 230 each include a hexagon or an ellipse.
  • the shapes of the first effective light-emitting area 2100 and the third effective light-emitting area 2300 are both hexagons, the three sets of opposite sides in the hexagon are all parallel, and the hexagon also includes sides parallel to the second direction.
  • the hexagon includes an axis of symmetry extending in a first direction and an axis of symmetry extending in a second direction.
  • the shape of the first effective light-emitting area and the third effective light-emitting area shown in FIG. 1A includes strictly an angle formed by two line segments, in some embodiments, the shape of the first effective light-emitting area and the third effective light-emitting area They can all be rounded corners, such as elliptical shapes. That is, on the basis of the aforementioned hexagon, the corners of the first effective light-emitting area and the third effective light-emitting area are rounded. For example, when the opening of the pixel defining layer is formed, the corners of the opening may be rounded, so that the first effective light-emitting area and the third effective light-emitting area may be rounded.
  • the center of the orthographic projection of the first effective light-emitting area 2100 on the base substrate 100 is located within the orthographic projection of the first sub-power signal line 410 on the base substrate 100.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 passes through the center of the orthographic projection of the first effective light-emitting area 2100 on the base substrate 100. That is, in a plan view, the first effective light-emitting area 2100 is symmetrically distributed with respect to the first sub-power signal line 410, that is, the first sub-power signal line 410 and the first effective light-emitting area 2100 extend symmetrically in the first direction.
  • the axis coincidence can ensure that the first effective light-emitting area 2100 has better symmetry along the second direction, so as to improve the color shift.
  • the center of the orthographic projection of the third effective light-emitting area 2300 on the base substrate 100 is located within the orthographic projection of the first sub-power signal line 410 on the base substrate 100.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 passes through the center of the orthographic projection of the third effective light-emitting area 2300 on the base substrate 100. That is, in a plan view, the third effective light-emitting area 2300 is approximately symmetrically distributed with respect to the first sub-power signal line 410, that is, the symmetry axis of the third effective light-emitting area 2300 extending in the first direction falls on the first sub-power source. In the signal line 410, it can be ensured that the third effective light-emitting area 2300 has good symmetry along the second direction, so as to improve the color shift.
  • FIG. 4 is a schematic diagram of a pixel circuit connected to an organic light-emitting element included in each sub-pixel.
  • each sub-pixel also includes a pixel circuit 0221 that drives an organic light-emitting element to emit light.
  • the pixel circuit 0221 may include a driving circuit 0222, a first light-emission control circuit 0223, a second light-emission control circuit 0224, a data writing circuit 0226, Storage circuit 0227, threshold compensation circuit 0228, and reset circuit 0229.
  • the driving circuit 0222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide the organic light emitting element 0220 with a driving current for driving the organic light emitting element 0220 to emit light.
  • the first light-emitting control circuit 0223 is electrically connected to the first voltage terminal VDD and the first terminal of the driving circuit 0222, and is configured to realize the conduction or disconnection of the connection between the driving circuit 0222 and the first voltage terminal VDD;
  • the second light-emitting control circuit 0224 is electrically connected to the second end of the driving circuit 0222 and the first electrode of the organic light-emitting element 0220, and is configured to realize the conduction or disconnection of the connection between the driving circuit 0222 and the organic light-emitting element 0220.
  • the data writing circuit 0226 is electrically connected to the first end of the driving circuit 0222, and is configured to write the data signal into the storage circuit 0227 under the control of the scan signal.
  • the storage circuit 0227 is electrically connected to the control terminal of the driving circuit 0222 and the first voltage terminal VDD, and is configured to store data signals.
  • the threshold compensation circuit 0228 is electrically connected to the control terminal and the second terminal of the driving circuit 0222, and is configured to perform threshold compensation on the driving circuit 0222.
  • the reset circuit 0229 is electrically connected to the control terminal of the driving circuit 0222 and the first electrode of the organic light emitting element 0220, and is configured to reset the control terminal of the driving circuit 0222 and the first electrode of the organic light emitting element 0220 under the control of the reset control signal .
  • the driving circuit 0222 includes a driving transistor T1
  • the control terminal of the driving circuit 0222 includes the gate of the driving transistor T1
  • the first terminal of the driving circuit 0222 includes the first electrode of the driving transistor T1.
  • the second terminal includes the second terminal of the driving transistor T1.
  • the data writing circuit 0226 includes a data writing transistor T2, the storage circuit 0227 includes a capacitor C, the threshold compensation circuit 0228 includes a threshold compensation transistor T3, the first light emission control circuit 0223 includes a first light emission control transistor T4, and the second light emission control circuit 0224 includes The second light emission control transistor T5, the reset circuit 0229 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1, and the second pole of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal.
  • the gate of the data writing transistor T2 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the first electrode of the capacitor C is electrically connected to the first power supply terminal VDD, and the second electrode of the capacitor C is electrically connected to the driving transistor
  • the gate of T1 is electrically connected; the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 is electrically connected.
  • the electrode is configured to be electrically connected to the second scan signal line Ga2 to receive the compensation control signal;
  • the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset power terminal Vinit1 to receive the first reset signal, the first reset The second electrode of the transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first sub-reset control signal;
  • the second reset transistor The first electrode of T7 is configured to be electrically connected to the second reset power terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the organic light emitting element 0220, and the second reset transistor T7
  • the gate of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD, and the first light-emitting control transistor T4 is electrically connected to the second reset control signal line Rst2 to receive the second sub-reset
  • the second electrode of the drive transistor T1 is electrically connected to the first electrode, the gate of the first light emission control transistor T4 is configured to be electrically connected to the first light emission control signal line EM1 to receive the first light emission control signal; the second light emission control transistor
  • the first electrode of T5 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the organic light emitting element 0220
  • the gate of the second light emitting control transistor T5 is configured as It is electrically connected to the second light emission control signal line EM2 to receive the second light emission control signal
  • the first electrode of the organic light emitting element 0220 is electrically connected to the second power terminal VSS.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may be electrically connected to the same signal line, such as the first scan signal line Ga1 is used to receive the same signal (for example, a scan signal).
  • the display substrate may not be provided with the second scan signal line Ga2 to reduce the number of signal lines.
  • the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, and the threshold The gate of the compensation transistor T3 is electrically connected to the second scan signal line Ga2, and the first scan signal line Ga1 and the second scan signal line Ga2 transmit the same signal.
  • the scan signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, which increases the flexibility of controlling the pixel circuit.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may be electrically connected to the same signal Lines, such as the first light emission control signal line EM1, to receive the same signal (e.g., the first light emission control signal).
  • the display substrate may not be provided with the second light emission control signal line EM2 to reduce the number of signal lines.
  • the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may also be electrically connected to different signal lines, that is, the gate of the first light emission control transistor T4 is electrically connected to the first light emission.
  • Control signal line EM1 the gate of the second light emission control transistor T5 is electrically connected to the second light emission control signal line EM2, and the first light emission control signal line EM1 and the second light emission control signal line EM2 transmit the same signal.
  • first light-emission control transistor T4 and the second light-emission control transistor T5 are different types of transistors, for example, the first light-emission control transistor T4 is a P-type transistor and the second light-emission control transistor T5 is an N-type transistor
  • the first lighting control signal and the second lighting control signal may also be different, which is not limited in the embodiment of the present disclosure.
  • the first sub-reset control signal and the second sub-reset control signal may be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, for example, the first reset The signal line Rst1 is controlled to receive the same signal (for example, the first sub-reset control signal).
  • the display substrate may not be provided with the second reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal. It should be noted that the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the scan signal line Ga to receive the scan signal as the second sub-reset control signal.
  • the source of the first reset transistor T6 and the source of the second reset transistor T7 are respectively connected to the first reset power terminal Vinit1 and the second reset power terminal Vinit2, the first reset power terminal Vinit1 and the second reset power terminal Vinit2 can be It is the DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same.
  • the source of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the second reset signal to the gate of the driving transistor T1 and the light-emitting element 0220.
  • the first electrode only needs to be reset, which is not limited in the present disclosure.
  • the gate of the first reset transistor T6 and the source of the second reset transistor T7 may both be connected to the reset power signal line Init.
  • the driving circuit 0222, the data writing circuit 0226, the storage circuit 0227, the threshold compensation circuit 0228, and the reset circuit 0229 in the pixel circuit shown in FIG. 4 are only illustrative, and the driving circuit 0222, the data writing circuit
  • the specific structures of the circuits such as the 0226, the storage circuit 0227, the threshold compensation circuit 0228, and the reset circuit 0229 can be set according to actual application requirements, which are not specifically limited in the embodiment of the present disclosure.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to illustrate the details of the present disclosure in detail.
  • the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the first The two reset transistors T7 and so on can all be P-type transistors.
  • the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. .
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the transistors in the embodiments of the present disclosure have the first pole and the second pole.
  • the first pole and the second pole are interchangeable as needed.
  • the pixel circuit of the sub-pixel may not only have the 7T1C (that is, seven transistors and one capacitor) structure shown in FIG. 4, but may also have a structure including other numbers of transistors.
  • a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure which is not limited in the embodiment of the present disclosure.
  • FIGS. 5 to 11 are schematic diagrams of a pixel circuit and each layer stack of each signal line provided by some embodiments of the present disclosure.
  • the following describes each circuit in the pixel circuit and the positional relationship of each signal line on the backplane with reference to FIGS. 5 to 11.
  • the example shown in FIGS. 5 to 11 uses four adjacent pixel circuits 0221 including four sub-pixels.
  • the positions of the transistors of the pixel circuit included in one sub-pixel are used for illustration, and the positions of the components included in the pixel circuit in other sub-pixels are substantially the same as the positions of the transistors included in the sub-pixel.
  • the pixel circuit 0221 of the sub-pixel includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, and a first Reset transistor T6, second reset transistor T7, capacitor C.
  • FIG. 5 shows the active semiconductor layer 310 of the pixel circuit in the display substrate.
  • the active semiconductor layer 310 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 310 can be used to make the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, and second reset transistor T7.
  • the active semiconductor layer 310 includes the active layer pattern (channel region) and doped region pattern (source-drain doped region) of each transistor of each sub-pixel, and the active layer pattern and doped region of each transistor in the same pixel circuit Miscellaneous area patterns are integrated.
  • the active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region may be conductive through doping or the like to realize electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed by p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (that is, a source region and a drain region) and an active layer Pattern, the active layers of different transistors are separated by doped structures.
  • the active semiconductor layer 310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active semiconductor layers in the pixel circuits of the sub-pixels of different colors arranged in the first direction have no connection relationship and are disconnected from each other.
  • the active semiconductor layers in the pixel circuits of the sub-pixels arranged in the second direction may be integrally provided, or may be disconnected from each other.
  • FIGS. 5 to 11 also show the scanning signal line Ga (including the first scanning signal line Ga1 and the second scanning signal line Ga2) and the reset control signal line Rst (including the first scanning signal line Ga2) electrically connected to the pixel circuit 0121 of each color sub-pixel A reset control signal line Rst1 and a second reset control signal line Rst2), the reset power signal line Init of the reset power terminal Vinit (including the first reset power signal line Init1 of the first reset power terminal Vinit1 and the second reset power terminal Vinit2) The second reset power signal line Init2), the light emission control signal line EM (including the first light emission control signal line EM1 and the second light emission control signal line EM2), the data line Vd, and the first power signal line 400 and the second power signal line 500 .
  • the first power signal line 400 and the second power signal line 500 are electrically connected to each other.
  • the first scan signal line Ga1 and the second scan signal line Ga2 are the same signal line Ga
  • the line Init2 is the same signal line Init
  • the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line Rst
  • the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same signal Line EM, but not limited to this.
  • the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer.
  • a gate insulating layer (the gate insulating layer 160 shown in FIG. 2) is formed on the above-mentioned active semiconductor layer 310 for insulating the above-mentioned active semiconductor layer 310 from the gate metal layer formed subsequently.
  • FIG. 6 shows the first conductive layer 320 included in the display substrate. The first conductive layer 320 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 310.
  • the first conductive layer 320 may include the second electrode CC2 of the capacitor C, the scan signal line Ga, the reset control signal line Rst, the light emission control signal line EM, and the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission The gates of the control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7.
  • the gate of the data writing transistor T2 may be the overlapped portion of the scan signal line Ga and the active semiconductor layer 310;
  • the gate of the first light emission control transistor T4 may be the light emission control signal line EM and The first part where the active semiconductor layer 310 overlaps
  • the gate of the second emission control transistor T5 may be the second part where the emission control signal line EM overlaps the active semiconductor layer 310;
  • the gate of the first reset transistor T6 is the reset control The first part where the signal line Rst overlaps the active semiconductor layer 310, the gate of the second reset transistor T7 is the second part where the reset control signal line Rst overlaps the active semiconductor layer 310;
  • the threshold compensation transistor T3 may have a double gate structure
  • the first gate of the threshold compensation transistor T3 may be the part where the scan signal line Ga overlaps the active semiconductor layer 310, and the second gate of the threshold compensation transistor T3 may be protruding from the scan signal line Ga
  • the protruding structure P overlaps the active semiconductor layer 310.
  • each dotted rectangular frame in FIGS. 5 and 6 shows each part where the first conductive layer 320 and the active semiconductor layer 310 overlap.
  • the active semiconductor layers on both sides of each channel region are conductive as the first electrode and the second electrode of each transistor through processes such as ion doping.
  • the scan signal line Ga, the reset control signal line Rst, and the light emission control signal line EM are arranged in the second direction (Z direction).
  • the scanning signal line Ga is located between the reset control signal line Rst and the light emission control signal line EM.
  • the second electrode CC2 of the capacitor C (that is, the gate of the driving transistor T1) is located between the scan signal line Ga and the light emission control signal line EM.
  • the protruding structure P protruding from the scanning signal line Ga is located on the side of the scanning signal line Ga away from the light emission control signal line EM.
  • the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, and the gate of the first reset transistor T6 are all located at the first of the gate of the driving transistor T1.
  • the gate of the first light emission control transistor T4, the gate of the second light emission control transistor T5, and the gate of the second reset transistor T7 are all located on the second side of the gate of the driving transistor T1.
  • the first side and the second side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel are opposite sides of the gate of the driving transistor T1 in the second direction.
  • the first side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel may be the upper side of the gate of the driving transistor T1, and the driving transistor T1 of the pixel circuit of the sub-pixel
  • the second side of the gate of the driving transistor T1 may be the lower side of the gate of the driving transistor T1.
  • the lower side for example, the side of the display substrate for bonding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor T1 is the side closer to the IC of the gate of the driving transistor T1.
  • the upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor T1 farther away from the IC.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1.
  • the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel are opposite sides of the gate of the driving transistor T1 in the first direction X.
  • the third side of the gate of the driving transistor T1 of the pixel circuit may be the left side of the gate of the driving transistor T1 of the pixel circuit
  • the fourth side of the gate of the driving transistor T1 of the pixel circuit may be the driving transistor of the pixel circuit.
  • the left and right sides for example, the data line Vd and the second power signal line 500 connected to the same pixel circuit, the data line Vd is on the left side of the second power signal line 500, and the second power signal line 500 is on the data line Vd.
  • the data line Vd is on the left side of the second power signal line 500
  • the second power signal line 500 is on the data line Vd.
  • each pixel circuit can be a mirror image structure as shown in FIG. The relationship between the left side and the right side can be reversed.
  • a first insulating layer (the first insulating layer 150 shown in FIG. 2) is formed on the above-mentioned first conductive layer 320, which is used to combine the above-mentioned first conductive layer 320 with the second conductive layer 330 to be subsequently formed. insulation.
  • FIG. 7 shows the second conductive layer 330 of the pixel circuit.
  • the second conductive layer 330 includes the first electrode CC1 of the capacitor C, the reset power signal line Init, and the light shielding portion S.
  • the first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.
  • the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T3 is in a floating state when the threshold compensation transistor T3 is turned off, and is susceptible to jumps due to the influence of the surrounding line voltage. Therefore, the leakage current of the threshold compensation transistor T3 will be affected, and the luminous brightness will be affected.
  • the light shielding part S and the active semiconductor layer between the two channels of the threshold compensation transistor T3 are designed to form a capacitance, and the light shielding part S can be connected to the second channel.
  • the second power signal line obtains a constant voltage and a constant voltage, so the voltage of the active semiconductor layer in a floating state can be kept stable.
  • a second insulating layer (the second insulating layer 140 shown in FIG. 2) is formed on the above-mentioned second conductive layer 330, which is used to combine the above-mentioned second conductive layer 330 with the subsequently formed source and drain metal layers. 340 insulation.
  • FIG. 8 shows that vias in the second insulating layer are formed on the aforementioned second conductive layer 330
  • FIG. 9 shows the source and drain metal layers 340 of the pixel circuit.
  • the source-drain metal layer 340 includes a data line Vd and a second power signal line 500.
  • the data line Vd and the second power signal line 500 both extend along the Z direction.
  • the source and drain metal layer 340 further includes a first connection portion 341, a second connection portion 342, and a third connection portion 343. 8 and 9 show exemplary positions of a plurality of via holes.
  • the source and drain metal layer 340 passes through the plurality of via holes shown to interact with the active semiconductor layer 310, the first conductive layer film layer 320, and the second conductive layer 330. connect.
  • the data line Vd is electrically connected to the second electrode of the data writing transistor T2 through a via 381 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the second power signal line 500 is electrically connected to the first electrode of the first light emitting control transistor T4 through a via 382 penetrating the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140.
  • the second power signal line 500 and the data line Vd are alternately arranged along the first direction.
  • the second power signal line 500 is electrically connected to the first electrode CC1 of the capacitor C through a via 3832 penetrating the second insulating layer 140.
  • the second power signal line 500 is electrically connected to the light shielding portion S through a via 3833 penetrating the second insulating layer to provide the light shielding portion S with a constant voltage.
  • One end of the first connecting portion 341 is electrically connected to the second electrode of the threshold compensation transistor T3 through a via 384 penetrating through the gate insulating layer 160, the first insulating layer 150 and the second insulating layer 140, and the other of the first connecting portion 341
  • One end is electrically connected to the gate of the driving transistor T1 (that is, the second electrode CC2 of the capacitor C) through a via 385 penetrating through the first insulating layer 150 and the second insulating layer 140.
  • One end of the second connection portion 342 is electrically connected to the reset power signal line Init through a via 386 in the second insulating layer 140, and the other end of the second connection portion 342 is electrically connected to the reset power signal line Init through the gate insulating layer 160, the first insulating layer 150, and The via 387 in the second insulating layer 140 is electrically connected to the first electrode of the second reset transistor T7.
  • the third connection portion 343 is electrically connected to the second electrode of the second light emitting control transistor T5 through a via 352 penetrating through the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140.
  • a passivation layer 123 and a second flat layer 122 are formed on the source and drain metal layer 340 to protect the source and drain metal layer 340.
  • the passivation layer 123 and the second flat layer 122 include via holes 351 and via holes 354.
  • Fig. 3C is a cross-sectional view taken along the line BB' shown in Fig. 1B in another example of the embodiment of the disclosure.
  • the second flat layer 122 may be formed on the above-mentioned source and drain metal layer 340 without forming the passivation layer 123.
  • FIG. 11 shows a third conductive layer 350 of the pixel circuit.
  • the third conductive layer 350 includes a fourth connection portion 450 and first power signal lines 400 intersecting along the X direction and the Y direction.
  • FIG. 11 also shows exemplary positions of a plurality of via holes 351 and 354, and the third conductive layer 350 is connected to the source and drain metal layer 340 through the plurality of via holes 351 and 354 as shown.
  • the first flat layer 121 is provided on the side of the third conductive layer 350 away from the base substrate 100, and the second electrode of the organic light emitting element of each sub-pixel may be provided on the side of the first flat layer 121 away from the base substrate 100, and The second electrode of the organic light emitting diode is electrically connected to the fourth connecting portion 450 through the via 1210 provided in the first flat layer 121 to achieve electrical connection with the second electrode of the second light emitting control transistor T5.
  • the third conductive layer 350 includes a plurality of fourth connecting portions 450, and a row of fourth connecting portions 450 is provided between two adjacent second sub power signal lines 420.
  • the pixel circuit of each sub-pixel includes one fourth connecting portion 450, and the plurality of fourth connecting portions 450 included in the plurality of sub-pixels are arranged in an array along the first direction and the second direction.
  • the plurality of fourth connecting portions 450 are arranged at equal intervals along the first direction, and the plurality of fourth connecting portions 450 are also arranged at equal intervals along the second direction.
  • each effective light-emitting area does not overlap with the fourth connecting portion 450.
  • the center line of the orthographic projection of the third effective light-emitting region 2300 on the base substrate 100 passes through the orthographic projection of a row of the fourth connecting portions 450 on the base substrate 100.
  • a straight line extending in the second direction where the spacer 430 is located passes through a row of fourth connecting portions 450.
  • the distance between the edges of two adjacent fourth connecting portions 450 that are arranged along the first direction is greater than the size of the second effective light-emitting area 2200 along the first direction.
  • the distance between the edges of two adjacent fourth connecting portions 450 arranged in the second direction is greater than the size of each effective light-emitting area in the second direction.
  • the distance between the edges of two adjacent fourth connecting portions 450 arranged in the second direction is smaller than the size of the fracture 421 in the second direction.
  • a first flat layer 121 (shown in FIG. 2) is provided between the second electrode included in each color sub-pixel and the third conductive layer 350, and the second electrode is connected to the fourth through a via hole provided in the first flat layer.
  • the portion 450 is connected to realize the connection with the second electrode of the second light-emitting control transistor T5.
  • FIG. 12 is a schematic plan view of an organic light-emitting element corresponding to the circuit structure of each pixel shown in FIG. 11, and FIG. 13 is a schematic plan view of a second electrode of each sub-pixel.
  • the first effective light-emitting area 2100 is connected to the data line Vd of the second electrode of the data writing transistor T2 of the first color sub-pixel 210. overlap.
  • the second effective light-emitting area 2201 is connected to the second electrode of the first light-emitting control transistor T4 of the second color sub-pixel 220.
  • the power signal line 500, the second connection portion 342 of the second color sub-pixel 220, and the data line Vd connected to the second electrode of the data writing transistor T2 of the second color sub-pixel 220 all overlap, and the second center line There is overlap with the second power signal line 500, the second connection portion 342 and the data line Vd are located on both sides of the second center line; along the direction perpendicular to the base substrate 100, the second effective light-emitting area 2202 and the data line Vd, The second power signal line 500 and the first connection portion 341 overlap, and the second center line overlaps the second power signal line 500.
  • the first connection portion 341 and the data line Vd are located on both sides of the second center line. .
  • the third effective light-emitting area 2300 is connected to the second electrode of the data writing transistor T2 of the adjacent second color sub-pixel 220.
  • the data line Vd, the first connection portion 341 and the second connection portion 342 of the third color sub-pixel 230 all overlap, and the data line Vd is located on one side of the third center line, the first connection portion 341 and the second connection portion 342 is located on the other side of the third centerline.
  • the portion where the second connection portion 342 is electrically connected to the first electrode of the second reset transistor T7 through the via 387 overlaps the fracture.
  • the portion of the light shielding portion S extending in the Z direction overlaps the fracture, and the via 3833 overlaps the fracture.
  • the portion of the first pole CC1 of the capacitor C connected to the second power signal line through the via 3832 overlaps the break.
  • the second electrode 212 of the first color sub-pixel 210 includes a first body electrode 2121 and a first connection electrode 2122.
  • the first body electrode 2121 and the first connection electrode 2122 may be an integral structure, and the first connection electrode 2122 is connected to the fourth connection portion 450 through the via 1210, so as to be connected to the second light emission control transistor T5 of the first color sub-pixel 210.
  • the second pole is connected.
  • the second electrode 222 of each second-color sub-pixel in the second-color sub-pixel pair 220 includes a second body electrode 2221 and a second connection electrode 2222.
  • the second electrode of the first sub-pixel in the second-color sub-pixel pair 220 includes a second body portion 2221-1 and a second connection portion 2222-1, and the second electrode of the second sub-pixel in the second-color sub-pixel pair 220
  • the electrode includes a second body portion 2221-2 and a second connection portion 2222-2.
  • the second body electrode 2221 and the second connection electrode 2222 of each second color sub-pixel may be an integral structure, and the second connection electrode 2222 of the second color sub-pixel is connected to the fourth connection portion 450 through the via hole 1210 to It is connected to the second pole of the second light-emitting control transistor T5 of the second color sub-pixel.
  • the second electrode 232 of the third color sub-pixel 230 includes a third body electrode 2321 and a third connection electrode 2322.
  • the third body electrode 2321 and the third connection electrode 2322 may be an integral structure, and the third connection electrode 2322 is connected to the fourth connection portion 450 through the via 1210 to achieve the second light emission control of the third color sub-pixel 130
  • the second pole of the transistor T5 is connected.
  • the first connecting electrode 2122 of the first color sub-pixel 210 is located on the side of the first body electrode 2121 close to the second color sub-pixel pair 220, and the second connecting electrode 2222 of the second color sub-pixel pair 220 is located on the second body electrode.
  • a side of 2221 away from the first color sub-pixel 210, and the third center line of the third effective light-emitting area 2300 of the third color sub-pixel 230 passes through the third body electrode 2321 and the third connection electrode 2322.
  • the shape of the body electrode of each sub-pixel is approximately the same as the shape of the light-emitting region, and the area of the body electrode of each sub-pixel is larger than the area of the effective light-emitting region.
  • the geometric center of the body electrode of each sub-pixel roughly coincides with the geometric center of the effective light-emitting area.
  • the shape of the first body electrode 2121 of the first color sub-pixel 210 and the third body electrode 2321 of the third color sub-pixel 230 is approximately a hexagon or an ellipse, and each of the second color sub-pixel pairs 220
  • the shape of the second body electrode 2221 of the two-color sub-pixel is approximately pentagonal, circular or drop-shaped.
  • FIG. 14 is a schematic diagram of a planar structure of a second electrode of each sub-pixel in a display substrate.
  • the display substrate shown in FIG. 14 is different from the display substrate shown in FIGS. 1 to 13 of the embodiment of the present disclosure in that the shape of the connecting electrode of the second electrode of the organic light-emitting element shown in FIG. 14 is different from that of the present disclosure.
  • the shape of the connecting electrode of the second electrode of the organic light-emitting element in the embodiment is shown in FIG. 13. As shown in FIG.
  • the shape of the body electrode 11 included in the second electrode of the organic light-emitting element of the first color sub-pixel and the shape of the light-emitting area 1 are both hexagonal; the second color of the organic light-emitting element of the third color sub-pixel
  • the shape of the body electrode 31 included in the electrode and the shape of the light-emitting area 3 are both hexagonal; the shape of the body electrode 21 included in the second electrode of the organic light-emitting element of the second color sub-pixel and the shape of the light-emitting area 2 are both pentagonal shape.
  • the second electrode of one second color sub-pixel includes a main body electrode 21-1 and a connection electrode 22-1, and the second electrode of the other second color sub pixel includes a main body electrode 21-2 and a connection electrode 22-2.
  • the main body electrode and the connection electrode in the second electrode of each sub-pixel may be an integral structure.
  • the boundary between the main body electrode and the connection electrode is the boundary shown by the dashed line in FIG. 14. It can be seen from FIG. 14 that the shape of the body electrode of each sub-pixel may be a regular polygon, and the shape of the connecting electrode may be an irregular shape.
  • the fingerprint detection technology under the optical screen can be used.
  • the fingerprint detection technology under the optical screen relies on light reflection to detect the fingerprint loop, and compares the obtained fingerprint image with the image in the database to achieve the purpose of fingerprint detection.
  • the fingerprint detection technology under the optical screen is particularly widely used in organic light emitting diode display devices.
  • the fingerprint detection technology under the optical screen usually uses the light emitted by the display substrate as the light source.
  • the fingerprint sensor is usually arranged on the non-display side of the display substrate, for example, it can be located on the side of the organic light-emitting element close to the base substrate to realize the function of fingerprint detection under the screen.
  • each sub-pixel can be used for display and as the light for fingerprint detection under the screen.
  • a top film layer can be provided on the side of the sub-pixel away from the base substrate to place the finger; the fingerprint sensor that collects the fingerprint image can be used with each sub-pixel.
  • the pixels are arranged on the same side of the display substrate, and the fingerprint sensor is arranged on the side of each sub-pixel organic light-emitting element close to the base substrate for detecting the reflected light reflected from the fingerprint on the surface of the top film layer.
  • the fingerprint sensor may include a plurality of detection units arranged in an array.
  • the film layers such as the top film and the base substrate are transparent, and a transparent area is provided between adjacent sub-pixels (the transparent area is the transparent area of the display substrate).
  • the reflected light of the fingerprint on the surface of the top film can be incident on the fingerprint sensor to obtain a fingerprint image.
  • the anode (second electrode) of the organic light-emitting element of each sub-pixel is formed of an opaque material, the light-shielding area of the anode of each sub-pixel will affect the light transmittance, which in turn affects the sensitivity of fingerprint detection.
  • the area ratio of the effective light-emitting area 1 to the second electrode is approximately 52.85%; in the second color sub-pixel, the area ratio of the effective light-emitting area 2 to the second electrode is approximately 42.31 %; In the third color sub-pixel, the area ratio of the effective light-emitting area 3 to the second electrode is approximately 66.99%.
  • the area ratio of the second electrode of the first color subpixel, the two second electrodes in the second color subpixel pair, and the second electrode in the third color subpixel is 1:1.58:1.16.
  • the light-shielding area can be reduced by changing the shape of the second electrode outside the effective light-emitting area, such as the shape of the connecting electrode, and the area of the transparent area of the display substrate can be increased, thereby increasing The sensitivity of fingerprint detection.
  • the area of the effective light-emitting area of each sub-pixel is unchanged, compared to the shape of the second electrode of each sub-pixel in the display substrate shown in FIG.
  • the area of the pixel located outside the effective light-emitting area can reduce the light-shielding area of the second electrode and increase the light transmittance of the display substrate.
  • the area ratio of the first effective light-emitting region 2100 to the second electrode 212 is 53% to 55%
  • the second color sub-pixel pair 220 The area ratio of the two second effective light-emitting regions 2200 to the two second electrodes 222 is 43.5% to 48%.
  • the area ratio of the third effective light-emitting region 2300 to the second electrode 232 is 67.5% to 69%.
  • the first-color sub-pixels, the second-color sub-pixels, and the third-color sub-pixels in the embodiments of the present disclosure may correspond to the first-color sub-pixels, the second-color sub-pixels, and the third-color sub-pixels in FIG. 14 in a one-to-one correspondence.
  • the area ratio of the first effective light-emitting area 2100 to the second electrode 212 is 54.9%
  • two second effective light-emitting areas 2200 and two second The area ratio of the electrode 222 is 47%.
  • the area ratio of the third effective light-emitting region 2300 to the second electrode 232 is 68.3%, so that the overall transmittance of the display substrate is increased by approximately 0.23%.
  • the embodiment of the present disclosure can increase the overall transmittance of the display substrate by increasing the area ratio of the effective light-emitting area of each sub-pixel to the second electrode, thereby increasing the sensitivity of fingerprint detection.
  • the area ratio of the first effective light-emitting area 2100, the two second effective light-emitting areas 2200 and the third effective light-emitting area 2300 in the second color sub-pixel pair 220 is approximately 1:1.27:1.47; the first color sub-pixel 210
  • the area ratio of the second electrode 212, the two second electrodes 222 in the second color sub-pixel pair 220, and the second electrode 232 in the third color sub-pixel 230 is approximately 1:1.48:1.18.
  • the display substrate is positioned at least A part of the area is a transparent area.
  • the transparent area 10 here includes no pixel circuit 0221, the first power signal line 400, the second power signal line 500, the data line Vd, the scanning signal line Ga, the reset power signal line Init, the reset control signal line Rst, and the light emission control signal.
  • the area of the line EM that is, the transparent area 10 refers to the area where light can enter the fingerprint sensor from the transparent area on the base substrate 100 that is not covered by the light-shielding film layer.
  • the light-shielding film layer includes the active semiconductor layer 310, the first conductive layer 320, and the second conductive layer.
  • no projections of the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source/drain metal layer 340, and the third conductive layer 350 fall within the area .
  • the projection of no via, connecting portion, or spacer falls within the area.
  • one or more insulating layers are provided, such as the gate insulating layer 160, the first insulating layer 150, the second insulating layer 140, the passivation layer 123, and the first flat layer. 121 and the second flat layer 122, etc., and the transmittance of the one or more insulating layers is greater than that of the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, and the source Any one of the drain metal layer 340 and the third conductive layer 350.
  • one or more insulating layers are provided, such as the gate insulating layer 160, the first insulating layer 150, the second insulating layer 140, the passivation layer 123, and the first flat layer. 121 and the second flat layer 122, etc., and multiple insulating layers are sequentially formed on the display substrate, and in the transparent area, the multiple insulating layers are adjacent to each other, that is, from far away from the display substrate.
  • the second insulating layer is in direct contact with the first insulating layer
  • the third insulating layer is in direct contact with the second insulating layer.
  • the one or more insulating layers may be organic layers or inorganic layers.
  • the area corresponding to at least a part of the recess is set as a transparent area, in this area, the gate insulating layer is formed on the surface of the base substrate, and the first insulating layer is located on the surface of the gate insulating layer away from the base substrate, The second insulating layer is located on the surface of the first insulating layer away from the base substrate, the passivation layer is located on the surface of the second insulating layer away from the base substrate, the second flat layer is located on the surface of the passivation layer away from the base substrate, the first flat layer The second flat layer is located on the surface away from the base substrate, and the second electrode, such as the anode, is a notch at this position, that is, the surface of the first flat layer away from the base substrate directly contacts the pixel defining layer formed after the second electrode.
  • the area corresponding to at least a part of the recess is set as a transparent area, in this area, the gate insulating layer is formed on the surface of the base substrate, and the first insulating layer is located on the surface of the gate insulating layer away from the base substrate, The second insulating layer is located on the surface of the first insulating layer away from the base substrate, the second flat layer is located on the surface of the second insulating layer away from the base substrate, and the first flat layer is located on the surface of the second flat layer away from the base substrate.
  • the two electrodes, such as the anode are notches in this position, that is, the first flat layer is in direct contact with the pixel defining layer formed after the second electrode on the surface away from the base substrate.
  • the connecting portion between the first connecting electrode 2122 and the first main body electrode 2121 is provided with a first notch 2123, and the display substrate corresponds to the first notch 2123.
  • At least a part of the area 2123 is the transparent area 10. That is, the portion of the first recess 2123 does not overlap with the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source and drain metal layer 340, and the third conductive layer 350.
  • the first recess 2123 The area that does not overlap with the above-mentioned film layer forms a transparent area of the display substrate. As shown in FIGS.
  • the first notch 2123 is a part of the first connecting electrode 2122 in the embodiment of the disclosure that is recessed inward with respect to the connecting electrode 12 shown in FIG.
  • the light-shielding film layers such as the semiconductor layer 310, the first conductive layer 320, and the source/drain metal layer 340 overlap, and the other part of the recessed portion only overlaps the base substrate 100 and the multilayer transparent insulating layer. That is, the position of the first recess should be selected in consideration of the positional relationship between it and the light-transmitting area exposed by the light-shielding film layer other than the film layer where the second electrode is located. At least part of the first recess is related to the light-transmitting area. Together, the transparent area of the display substrate is formed.
  • the side of the connecting electrode 12 shown in FIG. 14 that is connected to the main body electrode 11 is substantially straight, and the first notch 2123 shown in FIG. 13 is formed by bending the straight side to the side close to the first main electrode 2121 The notch.
  • a notch is provided where the first connection electrode and the transparent area are directly opposite, so that the light transmittance of the display substrate can be increased, and the sensitivity of fingerprint detection can be improved.
  • the region 101 surrounded by the active semiconductor layer 310 of the channel region and the source and drain doped regions of each transistor and the first electrode CC1 of the storage capacitor C and the first notch 2123 of the second electrode 212 of the first color sub-pixel 210 There is overlap.
  • the connection electrode 12 described in FIG. 14 in the embodiment of the present disclosure, by providing the first notch 2123 at the position of the first connection electrode 2122 corresponding to the area 101, the light transmittance of the display substrate can be increased.
  • the first connection electrode 2122 is connected to the fourth connection portion 450 through the first connection via 1211, and the first notch 2123 is located in the first connection via. 1211 is far away from the side of the second color sub-pixel 220 that is in the same repeating unit as the first color sub-pixel 210.
  • the degree of depression of the first recess 2123 depends on the edge of the first connection electrode 2122 and the first connection via 1211 The first notch 2123 needs to avoid the first connection via 1211 to prevent the electrical connection between the first connection electrode 2122 and the fourth connection portion 450 from being affected.
  • the first notch 2123 is a notch formed by a side edge of the first connection electrode 2122 facing the first connection via 1211 that is away from the second color sub-pixel 220 inwardly, and the edge of the notch extends To the edge of the first body electrode 2121.
  • the width of the portion of the connection electrode 12 near the main electrode 11 in the X direction is wider, that is, the portion between the connection via hole connected to the connection electrode 12 and the portion between the main electrode 11
  • the width in the X direction is relatively wide. Therefore, after the first notch 2123 shown in FIG. 13 is formed on the connecting electrode 12 shown in FIG. 14, it can be ensured that the first connecting electrode 2122 can still be held through the first connecting via 1211. It is reliably connected to the fourth connecting portion 450.
  • the connection portion between the first connection electrode 2222-1 and the first body electrode 2221-1 A second notch 2223-1 is provided, and the area of the display substrate corresponding to at least a part of the second notch 2223-1 is a transparent area. That is, the part of the second recess 2223-1 does not overlap with the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source and drain metal layer 340, and the third conductive layer 350.
  • the second recess The area of the opening 2223-1 that does not overlap the above-mentioned film layer forms a transparent area of the display substrate.
  • the second notch 2223-1 is the recessed portion of the second connecting electrode 2222-1 in the embodiment of the disclosure relative to the connecting electrode 22-1 shown in FIG.
  • One part overlaps with the active semiconductor layer 310, the first conductive layer 320, and the source/drain metal layer 340 and other light-shielding film layers, and the other part of the recessed part only overlaps with the base substrate 100 and the multilayer transparent insulating layer. That is, the selection of the position of the second notch needs to consider the positional relationship between it and the light-transmitting area exposed by the light-shielding film layer other than the film layer where the second electrode is located. At least part of the second notch is related to the light-transmitting area. Together, the transparent area of the display substrate is formed.
  • the side of the connecting electrode 22-1 shown in FIG. 14 that is connected to the main body electrode 21-1 is substantially straight, and the second notch 2223-1 shown in FIG. 13 is closer to the second main electrode from the straight side.
  • the notch formed by bending one side of 2221-1.
  • a notch is provided where the second connecting electrode and the transparent area are directly opposite, so that the light transmittance of the display substrate can be increased, and the sensitivity of fingerprint detection can be improved.
  • the emission control signal line EM and the second power signal line of the pixel circuit of the first sub-pixel of the second color sub-pixel pair 220 are connected In the area surrounded by 500 and the first electrode CC1 of the storage capacitor C, a part of the area 102 close to the emission control signal line EM overlaps with the second notch 2223-1 of the second electrode 222-1 of the first sub-pixel.
  • the connection electrode 22-1 described in FIG. 14 in the embodiment of the present disclosure, by providing the second notch 2223-1 at the position of the second connection electrode 2222-1 corresponding to the area 102, the light transmission of the display substrate can be increased. Rate.
  • the connection portion between the second connection electrode 2222-2 and the second body electrode 2221-2 A third notch 2223-2 is provided, and the area of the display substrate corresponding to at least a part of the third notch 2223-2 is a transparent area. That is, the part of the third recess 2223-2 does not overlap with the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source and drain metal layer 340, and the third conductive layer 350, and the third recess
  • the area of the opening 2223-2 that does not overlap with the above-mentioned film layer forms a transparent area of the display substrate.
  • the third notch 2223-2 is the recessed portion of the second connecting electrode 2222-2 in the embodiment of the disclosure relative to the connecting electrode 22-2 shown in FIG.
  • One part overlaps with the active semiconductor layer 310, the first conductive layer 320, and the source/drain metal layer 340 and other light-shielding film layers, and the other part of the recessed part only overlaps with the base substrate 100 and the multilayer transparent insulating layer. That is, the selection of the position of the third notch needs to consider its positional relationship with the light-transmitting area exposed by the light-shielding film layer other than the film layer where the second electrode is located, and at least part of the third notch is shared with the light-transmitting area.
  • the transparent area of the display substrate is formed.
  • the side of the connecting electrode 22-2 shown in FIG. 14 that is connected to the main body electrode 21-2 is substantially straight, and the second notch 2223-2 shown in FIG. 13 is away from the first color element from the straight side.
  • a notch is provided where the second connecting electrode and the transparent area are directly opposite to each other, which can increase the light transmittance of the display substrate, thereby increasing the sensitivity of fingerprint detection.
  • the second connection electrode 2222-2 includes a first portion 2-1 extending in the second direction and a curved second portion 2-2, the first part 2-1 is located on the side of the second part 2-2 away from the second body electrode 2221-2, the second part 2-2 is connected to the body electrode 2221-2, and the first part 2-1 is along the The maximum dimension in one direction is greater than the maximum dimension of the second portion 2-2 in the first direction.
  • the emission control signal line EM, the second power signal line 500, and the third connection portion 343 connected to the pixel circuit of the second sub-pixel surround A part of the area 103 near the second power supply signal line 500 and the light emission control signal line EM in the area overlaps the third notch 2223-2 of the second electrode 222-2 of the second sub-pixel.
  • the third notch 2223-2 is provided at the position of the second connection electrode 2222-2 corresponding to the area 103, so that the light transmission of the display substrate can be increased. Overrate.
  • the first part 22-21 included in the connecting electrode 22-2 shown in FIG. 14 is substantially the same in shape and size as the first part 2-1 included in the second connecting electrode 2222-2 according to the embodiment of the present disclosure.
  • the connecting electrode 22-2 shown includes a second portion 22-22 that has a larger size along the first direction than the size of the first portion 22-21 along the first direction, and the second portion 22-22 covers the film layer except the second electrode.
  • Part of the light-transmitting area exposed by the light-shielding film layer so by reducing the area of the part where the second portion 22-22 overlaps the light-transmitting area, for example, it is close to the first effective light-emitting area of the first color sub-pixel
  • the part covering the light-transmitting area is removed to form the third notch 2223-2, which can improve the light transmittance of the display substrate.
  • the second portion 22-22 of the connecting electrode 22-2 shown in FIG. 14 is connected to the first side of the main electrode 21-2 close to the first color sub-pixel and the second side far away from the first color sub-pixel.
  • the second part 2-2 of the second connecting electrode 2222-2 in the embodiment of the present disclosure is only connected to the second side of the second body electrode 2221-2 away from the first color sub-pixel, so that the second body electrode The light-transmitting area near the first side is not covered by the second connecting electrode.
  • the second connection electrode 2222-2 does not overlap the source and drain doped regions of the first light-emitting control transistor T4.
  • the portion of the second portion 22-22 of the connection electrode 22-2 shown in FIG. 14 close to the first effective light-emitting region 1 of the first color sub-pixel covers the source and drain doped regions of the first light-emitting control transistor T4.
  • the second part 2-2 of the second connecting electrode 2222-2 can be The source and drain doped regions of the first light-emitting control transistor T4 do not overlap, so that the second portion 2-2 and the light-transmitting regions near the source and drain doped regions of the first light-emitting control transistor T4 do not overlap, thereby improving the display substrate ⁇ Transmittance.
  • the first connection electrode 2222-1 is connected to the fourth connection portion 450 through the second connection via 1212-1, and the second notch 2223-1 Located on the side of the second connection via 1212-1 close to the first color sub-pixel 210 in the same repeating unit as the second color sub-pixel 220, the degree of depression of the second recess 2223-1 depends on the first connection electrode
  • the distance between the edge of 2222-1 and the second connection via 1212-1, the second notch 2223-1 needs to avoid the second connection via 1212-1 to prevent the first connection electrode 2222-1 and the fourth connection from being affected
  • the electrical connection of the section 450 The electrical connection of the section 450.
  • the second notch 2223-1 is a notch formed by a side edge of the first connection electrode 2222-1 facing the second connection via 1212-1 that is close to the first color sub-pixel 210 inwardly. And the edge of the notch extends to the edge of the first body electrode 2221-1.
  • the width of the portion of the connection electrode 22-1 near the main body electrode 21-1 in the X direction is wider, that is, the portion of the connection via that is connected to the connection electrode 22-1 to the main body electrode
  • the portion between 21-1 has a wider width in the X direction. Therefore, after the second notch 2223-1 shown in FIG. 13 is formed on the connecting electrode 22-1 shown in FIG. 14, the first connection can be ensured.
  • the electrode 2222-1 can still be reliably connected to the fourth connection portion 450 through the second connection via 1212-1.
  • the first connection electrode 2222-2 is connected to the fourth connection portion 450 through the third connection via 1212-2, and the third notch 2223-2 Located on the side of the third connection via 1212-2 close to the first color sub-pixel 210 in the same repeating unit as the second color sub-pixel 220, the degree of depression of the third recess 2223-2 depends on the first connection electrode The distance between the edge of 2222-2 and the third connection via 1212-2, the third notch 2223-2 needs to avoid the third connection via 1212-2 to prevent the first connection electrode 2222-2 and the fourth connection from being affected The electrical connection of the section 450.
  • the third notch 2223-2 is a notch formed by the first connection electrode 2222-2 facing the third connection via 1212-2, and the edge of the first connection electrode 2222-2 that is close to the first color sub-pixel 210 is recessed inwardly. And the edge of the notch extends to the edge of the first body electrode 2221-2.
  • the width of the portion of the connection electrode 22-2 near the main body electrode 21-2 in the X direction is wider, that is, the portion of the connection via connected to the connection electrode 22-2 to the main body electrode
  • the part between 21-2 has a wider width in the X direction. Therefore, after the third notch 2223-2 shown in FIG. 13 is formed on the connecting electrode 22-2 shown in FIG. 14, the first connection can be ensured.
  • the electrode 2222-2 can still be reliably connected to the fourth connection part 450 through the third connection via 1212-2.
  • the connection part between the third connecting electrode 2322 and the third main body electrode 2321 is provided with a fourth notch 2323, and the display substrate is The area corresponding to at least a part of the fourth recess 2323 is the transparent area 10. That is, the part of the fourth recess 2323 does not overlap with the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source and drain metal layer 340, and the third conductive layer 350.
  • the fourth recess 2323 The area that does not overlap with the above-mentioned film layer forms a transparent area of the display substrate. As shown in FIGS.
  • the fourth notch 2323 is the recessed portion of the second connecting electrode 232 in the embodiment of the disclosure relative to the connecting electrode 2322 shown in FIG. 310, the first conductive layer 320, the source and drain metal layer 340 and other light-shielding film layers overlap, and the other part of the above-mentioned recessed portion is only overlapped with the base substrate 100 and the multilayer transparent insulating layer, that is, the fourth recess
  • the selection of the position of the opening needs to consider the positional relationship between it and the light-transmitting area exposed by the light-shielding film layer except for the film layer where the second electrode is located. At least part of the fourth notch and the above-mentioned light-transmitting area together form the transparency of the display substrate. area.
  • the side of the connecting electrode 32 shown in FIG. 14 that is connected to the main body electrode 31 is substantially straight, and the fourth notch 2323 shown in FIG. 13 is formed by bending the straight side to the side close to the third main electrode 2321 The notch.
  • the embodiment of the present disclosure provides a notch directly opposite to the light-transmitting area exposed by the light-shielding film layer except for the film layer where the second electrode is located, thereby improving the display substrate. The light transmittance, thereby improving the sensitivity of fingerprint detection.
  • the fourth notch 2323 is provided in the portion of the third connection electrode 2322 corresponding to the area 104, so that the light transmittance of the display substrate can be increased.
  • connection electrode 32 shown in FIG. 14 close to the first color sub-pixel overlaps with the light-transmitting area exposed by the light-shielding film layer except for the film layer where the second electrode is located.
  • Part of the light-transmitting area that is close to the first color sub-pixel and covers the above-mentioned light-transmitting area is partially removed to form the fourth notch 2323, which can increase the light transmittance of the display substrate.
  • the first connection electrode 2322 is connected to the fourth connection portion 450 through the fourth connection via 1213, and the fourth notch 2323 is located in the fourth connection via.
  • 1213 is close to the side of the first color sub-pixel 210 adjacent to the third color sub-pixel 230, and the degree of depression of the fourth recess 2323 depends on the distance between the edge of the first connection electrode 2322 and the fourth connection via 1213
  • the fourth notch 2323 needs to avoid the fourth connection via 1213 to prevent the electrical connection between the first connection electrode 2223 and the fourth connection portion 450 from being affected.
  • the fourth notch 2323 is a notch formed by a side edge of the first connection electrode 2223 directly opposite to the fourth connection via 1213, which is close to the first color sub-pixel 210, inwardly formed, and the edge of the notch extends To the edge of the first body electrode 2321.
  • the width of the portion of the connection electrode 32 near the main body electrode 31 in the X direction is wider, that is, the portion between the connection via hole connected to the connection electrode 32 and the portion between the main body electrode 31
  • the width in the X direction is relatively wide. Therefore, after the fourth notch 2323 shown in FIG. 13 is formed on the connection electrode 32 shown in FIG. 14, it can be ensured that the first connection electrode 2223 can still be held through the fourth connection via 1213. It is reliably connected to the fourth connecting portion 450.
  • Another embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • the display device including the above-mentioned display substrate can avoid the occurrence of color shift as much as possible.
  • the display device provided by the embodiment of the present disclosure can apply fingerprint detection technology, and the display substrate included in the display device has high fingerprint detection sensitivity.

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Abstract

一种显示基板以及显示装置。显示基板包括第一电源信号线以及像素限定层。第一电源信号线包括沿第一方向延伸的第一子电源信号线以及沿第二方向延伸的第二子电源信号线；像素限定层包括多个开口以限定多个子像素的有效发光区，多个子像素包括沿第二方向排列的两个子像素组成的子像素对，子像素对包括彼此间具有间隔的两个子有效发光区。在平面图中，第一子电源信号线穿过两个子有效发光区之间的间隔，至少一条第二子电源信号线包括断口，两个子有效发光区位于断口处，以使连接第二子电源信号线的断口的两端点的虚拟直线贯穿两个子有效发光区。第二子电源信号线设置的断口可以减少两个子有效发光区与第一电源信号线的交叠，减少子像素对的色偏。

Description

显示基板以及显示装置 技术领域
本公开至少一个实施例涉及一种显示基板以及显示装置。
背景技术
有机发光二极管具有自发光、高效率、色彩鲜艳、轻薄省电等优点，已经逐步应用于大面积显示、照明以及车载显示等领域。为了提高有机发光二极管显示装置的均一性，可以采用两层电源信号线的结构，且靠近有机发光二极管的发光层一侧的电源信号线形成网格状图案，以减小电源信号线的压降。
发明内容
本公开的至少一实施例提供一种显示基板以及显示装置。
本公开的至少一实施例提供一种显示基板，包括：衬底基板；第一电源信号线，位于所述衬底基板上，所述第一电源信号线包括沿第一方向延伸的多条第一子电源信号线以及沿第二方向延伸的多条第二子电源信号线，所述第一子电源信号线与所述第二子电源信号线相连；像素限定层，位于所述第一电源信号线远离所述衬底基板的一侧，所述像素限定层包括多个开口以限定多个子像素的有效发光区，所述多个子像素包括沿所述第二方向排列的两个子像素组成的子像素对，所述子像素对包括彼此间具有间隔的两个子有效发光区。在平面图中，所述第一子电源信号线穿过所述两个子有效发光区之间的间隔，至少一条所述第二子电源信号线包括至少一个断口，所述两个子有效发光区以及位于所述两个子有效发光区之间的所述间隔均位于所述断口处，以使连接所述第二子电源信号线的同一断口的两个端点的沿所述第二方向延伸的虚拟直线贯穿所述两个子有效发光区以及所述间隔。
例如，在本公开的实施例中，沿垂直于所述衬底基板的方向，具有所述断口的所述第二子电源信号线与所述两个子有效发光区以及所述间隔均没有交叠。
例如，在本公开的实施例中，显示基板还包括：多条第二电源信号线，沿所述第二方向延伸，位于所述第一电源信号线与所述衬底基板之间，且所述第二电源信号线与所述第二子电源信号线通过位于所述第二子电源信号线与所述第二电源线之间的绝缘层中的过孔电连接。所述第二子电源信号线在所述衬底基板上的正投影与所述第二电源信号线在所述衬底基板上的正投影至少部分交叠，且所述两个子有效发光区在所述衬底基板上的正投影与所述第二电源信号线在所述衬底基板上的正投影有交叠。
例如，在本公开的实施例中，所述第一子电源信号线在所述衬底基板上的正投影与所述两个子有效发光区的在所述衬底基板上的两个正投影的两个中心之间的距离之比为0.9～1.1。
例如，在本公开的实施例中，所述两个子有效发光区在所述衬底基板上的两个正投 影的两个中心位于所述第二电源信号线在所述衬底基板上的正投影内。
例如，在本公开的实施例中，所述显示基板包括位于所述衬底基板上的多个重复单元，所述多个重复单元的每个包括沿所述第一方向依次排列的一个第一颜色子像素、一个第二颜色子像素对以及一个第三颜色子像素，所述第二颜色子像素对包括两个相同颜色的第二颜色子像素，且沿所述第二方向排列的所述两个子像素组成的所述子像素对为所述第二颜色子像素对；所述第一颜色子像素包括第一有效发光区，所述两个子有效发光区为两个第二有效发光区，且所述第三颜色子像素包括第三有效发光区。
例如，在本公开的实施例中，沿所述第二方向，所述间隔的尺寸小于所述第一有效发光区的尺寸，且所述间隔的尺寸小于所述第三有效发光区的尺寸。
例如，在本公开的实施例中，在垂直于所述衬底基板的方向上，所述第一有效发光区与所述第二子电源信号线以及所述第二电源信号线均没有交叠。
例如，在本公开的实施例中，所述第一有效发光区位于相邻的所述第二子电源信号线之间，且所述第一有效发光区位于相邻的所述第二电源信号线之间。
例如，在本公开的实施例中，所述第一有效发光区在所述衬底基板上的正投影的中心位于所述第一子电源信号线在所述衬底基板上的正投影内。
例如，在本公开的实施例中，显示基板还包括：多个垫块，沿所述第二方向延伸，且与所述第一电源信号线同层设置。位于第一有效发光区两侧且与所述第一有效发光区紧邻的两条第二子电源信号线距所述第一有效发光区的沿所述第二方向延伸的中心线的距离不相等，且所述第一有效发光区位于所述垫块与距所述第一有效发光区的所述中心线距离较近的所述第二子电源信号线之间。
例如，在本公开的实施例中，在所述第一方向上，所述第一有效发光区的中心线与位于所述第一有效发光区两侧的所述垫块和所述第二子电源信号线的距离之比为0.9～1.1。
例如，在本公开的实施例中，沿垂直于所述衬底基板的方向，所述垫块与所述第一子电源信号线交叠，且彼此电连接。
例如，在本公开的实施例中，所述垫块的形状大致为长条形，且所述垫块在所述衬底基板上的正投影的中心位于所述第一子电源信号线在所述衬底基板上的正投影内。
例如，在本公开的实施例中，沿所述第一方向排列且彼此相邻的所述第一颜色子像素和所述第三颜色子像素之间设置有所述垫块，且所述垫块与位于所述第一颜色子像素与所述第三颜色子像素之间的所述第二子电源信号线电连接。
例如，在本公开的实施例中，显示基板还包括：连接部，与所述垫块同层设置，且位于所述第二子电源信号线与所述垫块之间。所述垫块通过所述连接部连接至所述第二子电源信号线。
例如，在本公开的实施例中，所述垫块和与其连接的所述第二子电源信号线之间具有间隔，所述连接部位于所述垫块和所述第二子电源信号线之间，且所述连接部、所述垫块以及所述第二子电源信号线形成环状结构。
例如，在本公开的实施例中，多条所述第二子电源信号线包括沿所述第一方向交替排列的第一子信号线和第二子信号线，所述第一子信号线为连续的信号线，所述第二子信号线为具有所述断口的信号线。
例如，在本公开的实施例中，所述垫块通过所述连接部连接至所述第二子信号线，且所述垫块在与连接至该垫块的所述第二子信号线相邻的另一条所述第二子信号线上的正投影位于该另一条所述第二子信号线的断口内。
例如，在本公开的实施例中，沿所述第二方向，所述垫块的尺寸小于所述第一有效发光区的尺寸。
例如，在本公开的实施例中，在垂直于所述衬底基板的方向，所述第三有效发光区与所述第二子电源信号线以及所述第二电源信号线没有交叠。
例如，在本公开的实施例中，所述第三有效发光区位于相邻的所述第二子电源信号线之间，且所述第三有效发光区位于相邻的所述第二电源信号线之间。
例如，在本公开的实施例中，所述第三有效发光区在所述衬底基板上的正投影的中心位于所述第一子电源信号线在所述衬底基板上的正投影内。
例如，在本公开的实施例中，位于所述第三颜色子像素两侧且与所述第三颜色子像素紧邻的两条所述第二子电源信号线在所述衬底基板上的正投影与所述第三有效发光区在所述衬底基板上的正投影的中心的距离之比为0.9～1.1。
例如，在本公开的实施例中，各所述子像素包括有机发光元件，所述有机发光元件包括依次层叠设置的第一电极、发光层以及第二电极，所述发光层的至少部分位于所述开口内，且所述第二电极位于所述像素限定层面向所述衬底基板的一侧，所述第一颜色子像素中，所述第一有效发光区与所述第二电极的面积比为53％～55％；所述第二颜色子像素对中，所述两个第二有效发光区与两个第二电极的面积比为43.5％～48％；所述第三颜色子像素中，所述第三有效发光区与第二电极的面积比为67.5％～69％。
例如，在本公开的实施例中，所述第一有效发光区和所述第三有效发光区的形状包括六边形或者椭圆形，所述第二颜色子像素对包括的每个上述第二有效发光区的形状包括五边形、圆形或者水滴形。
例如，在本公开的实施例中，各颜色子像素的所述第二电极包括彼此连接的主体电极和连接电极，所述主体电极的形状与相应子像素的有效发光区的形状大致相同；各所述子像素中，所述连接电极与所述主体电极连接的部分设置有凹口，沿垂直于所述衬底基板的方向，所述显示基板在对应于所述凹口的至少一部分的区域为透明区域。
例如，在本公开的实施例中，显示基板还包括：多条数据线，沿所述第二方向延伸，且与所述第二电源信号线同层设置；多条扫描信号线，沿所述第一方向延伸，且位于所述数据线所在膜层面向所述衬底基板的一侧；多条复位电源信号线，沿所述第一方向延伸，且位于所述扫描信号线所在膜层与所述数据线所在膜层之间；多条复位控制信号线，沿所述第一方向延伸，且与所述扫描信号线同层设置；以及多条发光控制信号线，沿所述第一方向延伸，且与所述扫描信号线同层设置。各所述子像素还包括驱动所述有机发 光元件的像素电路，所述像素电路包括驱动晶体管、数据写入晶体管、存储电容、阈值补偿晶体管、第一发光控制晶体管、第二光控制晶体管、第一复位晶体管和第二复位晶体管；所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极与所述数据线电连接以接收数据信号，所述数据写入晶体管的栅极与所述扫描信号线电连接以接收扫描信号；所述存储电容的第一极与所述第二电源信号线电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接；所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接，所述阈值补偿晶体管的栅极与所述扫描信号线电连接以接收补偿控制信号；所述第一复位晶体管的第一极与所述复位电源信号线电连接以接收第一复位信号，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的栅极与所述复位控制信号线电连接以接收第一子复位控制信号；所述第二复位晶体管的第一极与所述复位电源信号线电连接以接收第二复位信号，所述第二复位晶体管的第二极与所述有机发光元件的第一电极电连接，所述第二复位晶体管的栅极与所述复位控制信号线电连接以接收第二子复位控制信号；所述第一发光控制晶体管的第一极与所述第二电源信号线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极与所述发光控制信号线电连接以接收第一发光控制信号；所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述有机发光元件的第二电极电连接，所述第二发光控制晶体管的栅极与所述发光控制信号线电连接以接收第二发光控制信号。所述显示基板还包括与所述数据线同层设置的第一连接部、第二连接部以及第三连接部，以及与所述第一电源信号线同层设置的第四连接部，所述第一连接部被配置为连接所述阈值补偿晶体管的第二极和所述驱动晶体管的栅极，所述第二连接部被配置为连接所述复位电源信号线和所述第二复位晶体管的第一极，所述第三连接部被配置为连接所述第二发光控制晶体管的第二极与所述第四连接部，所述第四连接部被配置为连接所述第三连接部和所述有机发光元件的第二电极的所述连接电极。
例如，在本公开的实施例中，所述透明区域包括没有设置所述像素电路、所述第一电源信号线、所述第二电源信号线、所述数据线、所述扫描信号线、所述复位电源信号线、所述复位控制信号线以及所述发光控制信号线的区域。
例如，在本公开的实施例中，沿垂直于所述衬底基板的方向，连接至所述第一颜色子像素的所述像素电路的所述发光控制信号线、所述第二电源信号线、包括各所述子像素的各晶体管的沟道区和源漏掺杂区的有源半导体层以及所述存储电容的第一极包围的区域与所述第一颜色子像素的第二电极的凹口有交叠。
例如，在本公开的实施例中，沿垂直于所述衬底基板的方向，连接至所述第二颜色子像素对的第一子像素的所述像素电路的所述发光控制信号线、所述第二电源信号线以及所述存储电容的第一极包围的区域中靠近所述发光控制信号线的部分区域与所述第一子像素的第二电极的凹口有交叠。
例如，在本公开的实施例中，所述第二颜色子像素对的第二子像素中，所述连接电极包括沿所述第二方向延伸的第一部分以及弯曲的第二部分，所述第一部分位于所述第二部分远离所述主体电极的一侧，所述第二部分与所述主体电极连接，且所述第一部分沿所述第一方向的最大尺寸大于所述第二部分沿所述第一方向的最大尺寸。
例如，在本公开的实施例中，所述第二子像素中，所述连接电极与所述第一发光控制晶体管的源漏掺杂区没有交叠。
例如，在本公开的实施例中，沿垂直于所述衬底基板的方向，连接至所述第二子像素的所述像素电路的所述发光控制信号线、所述第二电源信号线以及所述第三连接部包围的区域中靠近所述第二电源信号线和所述发光控制信号线的部分区域与所述第二子像素的第二电极的凹口有交叠。
例如，在本公开的实施例中，沿垂直于所述衬底基板的方向，连接至所述第二子像素的所述像素电路的所述数据线、所述有源半导体层以及所述存储电容的第一极所在膜层围成的区域中远离所述发光控制信号线的部分区域与所述第三颜色子像素的第二电极的凹口有交叠。
例如，在本公开的实施例中，所述第一颜色子像素为红色子像素，所述第二颜色子像素为绿色子像素，所述第三颜色子像素为蓝色子像素。
本公开的至少一实施例提供一种显示装置，包括上述显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为根据本公开一实施例提供的显示基板中的第一电源信号线与有效发光区的位置关系的平面图；
图1B为图1A所示的显示基板中的第一电源信号线、第二电源信号线以及有效发光区的位置关系的平面图；
图2为沿图1A和图1B所示的AA’线所截的局部截面结构示意图；
图3A为沿图1A和图1B所示的BB’所截的局部截面结构示意图；
图3B为沿图1B所示的CC’所截的局部截面结构示意图；
图3C为本公开实施例中另一示例中沿图1B所示的BB’线所截的截面图；
图4为各子像素包括的与有机发光元件连接的像素电路的示意图；
图5-图11为本公开一些实施例提供的一种像素电路以及各信号线的各层层叠的示意图；
图12为与图11所示的各像素电路结构一一对应的有机发光元件的平面示意图；
图13为各子像素的第二电极的平面形状示意图；以及
图14为一种显示基板中的各子像素的第二电极的平面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
有机发光二极管显示器件中包括像素限定层，像素限定层包括用于限定子像素的发光区的开口，该开口暴露有机发光元件的阳极，当后续的有机发光元件的发光层形成在上述像素限定层的开口中时，发光层与阳极接触，从而这部分能够驱动发光层进行发光以形成发光区。
在研究中，本申请的发明人发现：有机发光二极管显示器中，靠近有机发光二极管的发光层一侧的电源信号线存在与开***叠的情况时，位于发光区的电源信号线容易造成色偏现象。
本公开的实施例提供一种显示基板以及显示装置。显示基板包括：衬底基板、位于衬底基板上的第一电源信号线以及位于第一电源信号线远离衬底基板的一侧的像素限定层。第一电源信号线包括沿第一方向延伸的多条第一子电源信号线以及沿第二方向延伸的多条第二子电源信号线，第一子电源信号线与第二子电源信号线相连；像素限定层包括多个开口以限定多个子像素的有效发光区，多个子像素包括沿第二方向排列的两个子像素组成的子像素对，子像素对包括彼此间具有间隔的两个子有效发光区。在平面图中，第一子电源信号线穿过两个子有效发光区之间的间隔，至少一条第二子电源信号线包括断口，两个子有效发光区以及位于两个子有效发光区之间的间隔均位于断口处，以使连接第二子电源信号线的同一断口的两个端点的沿第二方向延伸的虚拟直线贯穿两个子有效发光区以及间隔。本公开实施例通过在第二子电源信号线中设置断口以减少两个子有效发光区与第一电源信号线的交叠面积，可以尽量避免子像素对在显示时发生色偏。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图1A为根据本公开一实施例提供的显示基板中的第一电源信号线与有效发光区的位置关系的平面图，图1B为图1A所示的显示基板中的第一电源信号线、第二电源信号线以及有效发光区的位置关系的平面图，图2为沿图1A和图1B所示的AA’线所截的局部截面结构示意图。如图1A-图2所示，显示基板包括衬底基板100以及位于衬底基板100上的多个重复单元200。每个重复单元200包括沿第一方向(图中所示的X方向)排列的一个第一颜色子像素210、一个第二颜色子像素对220以及一个第三颜色子像素230， 第二颜色子像素对220包括的两个第二颜色子像素沿第二方向(图中所示的Z方向，不同于第一方向的方向)排列。多个重复单元200沿第一方向排列以形成多个重复单元组，多个重复单元组沿第二方向排列，且多个重复单元组中的相邻重复单元组沿第一方向彼此错开，即，相邻的重复单元组沿第一方向有一定的偏移量。因此，相邻重复单元组中相同颜色的子像素在第二方向上并不是对齐的。奇数行重复单元组中像素排列方式相同，偶数行重复单元组中像素排列方式相同。
例如，相邻重复单元组在第一方向上的偏移量大致为重复单元200在第一方向上的尺寸的一半。例如，重复单元200在第一方向上的尺寸为重复单元200在第一方向上的节距。这里的节距指沿第一方向相邻两个重复单元200中的两个第一颜色子像素210的发光区的中心之间的距离，这里发光区的中心指发光区的平面形状的几何中心。
上述第一方向和第二方向分别为在同一平面内相互垂直的两个方向。例如，该平面为像素进行排列的平面。这里的重复单元仅指子像素的重复，其他结构可以不相同也可以相同。此外，上述的重复是指大概的位置和形状、大小差不多即可。在有些情况下，为了布线或者开孔的需要，形状可能略有不同，如在不同的位置有开孔。
例如，本公开实施例的一示例中，第一颜色子像素210可以为红色子像素，第二颜色子像素对220可以为绿色子像素对，第三颜色子像素230可以为蓝色子像素。但不限于此，各颜色子像素可以互换。
如图1A-图2所示，显示基板还包括位于衬底基板100上的第一电源信号线400，第一电源信号线400包括沿第一方向延伸的多条第一子电源信号线410以及沿第二方向延伸的多条第二子电源信号线420，第一子电源信号线410与第二子电源信号线420相连。
如图1A-图2所示，显示基板还包括位于第一电源信号线400远离衬底基板100的一侧的像素限定层130，像素限定层130包括多个开口以限定各子像素的有效发光区。这里的“有效发光区”可以指二维的平面区域，该平面区域平行于衬底基板。需要说明的是，像素限定层的开口由于工艺原因，远离衬底基板的部分尺寸略大于靠近衬底基板部分的尺寸，或者从靠近衬底基板一侧到远离衬底基板一侧的方向上呈现尺寸逐渐增加的形态，因此有效发光区的尺寸与像素限定层开口的不同位置的尺寸可能略有不同，但整体区域形状和尺寸基本相当。例如，有效发光区在衬底基板上的投影与对应的像素限定层的开口在衬底基板上的投影大致重合。例如，有效发光区在衬底基板上的投影完全落在对应的像素限定层的开口在衬底基板上的投影内，且二者形状相似，有效发光区在衬底基板上的投影面积相比对应的像素限定层的开口在衬底基板上的投影略小。
例如，各子像素包括有机发光元件，有机发光元件包括依次层叠设置的第一电极、发光层以及第二电极，发光层的至少部分位于开口内，且第二电极位于像素限定层面向衬底基板的一侧。例如，如图2所示，以第二颜色子像素对包括的一个第二颜色子像素为例，第二颜色子像素包括有机发光元件，该有机发光元件包括第一电极221、第二电极222以及位于第一电极221和第二电极222之间的发光层223。像素限定层130的开口暴露部分第二电极222，当发光层223形成在上述像素限定层130的开口中时，发光层223 与第二电极222接触，从而这部分能够驱动发光层进行发光以形成第二有效发光区2200。第二颜色子像素对220包括两个第二有效发光区2201以及2202。
本公开实施例以第二颜色子像素对包括的两个第二颜色子像素的发光层是一体的为例进行描述，例如第二颜色子像素对的两个第二颜色子像素的发光层是连起来的整体膜层，即两个第二颜色子像素的发光层是一个连续的完整的图形，或者两个第二颜色子像素的发光层在衬底基板上的投影是连续完整的，两个第二颜色子像素的发光层可以通过一个开口制作。但不限于此，例如，第二颜色子像素对包括的两个第二颜色子像素的发光层也可以是分离的。
如图1A-图2所示，第一颜色子像素210包括第一有效发光区2100，第二颜色子像素对包括彼此之间具有间隔的两个第二有效发光区2200(包括第一子有效发光区2201和第二子有效发光区2202)，第三颜色子像素230包括第三有效发光区2300。图中以像素限定层开口中发光层与第二电极接触的部分作为有效发光区进行示意。上述“第二颜色子像素对包括彼此之间具有间隔的两个第二有效发光区2200”中的“间隔”指像素限定层限定的两个开口之间的像素限定层的实体部分。如图1A所示的间隔S在X方向延伸的直线上的正投影可以与第二颜色子像素对在X方向延伸的直线上的正投影基本重合，间隔S在Z方向延伸的直线上的正投影位于第二颜色子像素对在Z方向延伸的直线上的两个正投影之间。
如图1A-图2所示，在平面图中，例如平行于衬底基板100的平面(或者后续结构在该平面上的正投影)，第一子电源信号线410穿过两个第二有效发光区2200之间的间隔，至少一条第二子电源信号线420包括断口421，两个第二有效发光区2200以及上述间隔位于断口421处，以使第二子电源信号线420没有贯穿两个第二有效发光区2200以及上述间隔。也就是，连接断口421两侧端点的且沿Z方向延伸的虚拟直线4210穿过两个第二有效发光区2200以及位于两个第二有效发光区2200之间的间隔S。上述“断口”指第二子电源信号线420不是连续的信号线，且该信号线包括彼此断开的多个信号线段，相邻两个信号线段之间的间隔即为上述断口421。
例如，沿垂直于衬底基板100的方向，具有断口421的第二子电源信号420线与两个第二有效发光区2200以及间隔S均没有交叠。
例如，沿垂直于衬底基板100的方向，两个第二有效发光区2200与第一电源信号线400没有交叠。即，在垂直于衬底基板100的方向，两个第二有效发光区2200与断口421有交叠，而与第二子电源信号线420没有交叠，并且两个第二有效发光区2200与第一子电源信号线410也没有交叠。从而，沿垂直于衬底基板的方向，第二颜色子像素对包括的两个第二有效发光区与第一电源信号线均没有交叠，以提高位于两个第二有效发光区内的第二电极远离发光层一侧的膜层的平坦性，可以尽量避免第二颜色子像素对在显示时发生色偏。
例如，如图1A和图1B所示，两个第二有效发光区2200之间的间隔沿第二方向的尺寸小于第一有效发光区2100沿第二方向的尺寸，且两个第二有效发光区2200之间的 间隔沿第二方向的尺寸小于第三有效发光区2300沿第二方向的尺寸。
例如，沿第二方向，第一有效发光区2100的尺寸大于第三有效发光区2300的尺寸，例如，第一有效发光区2100的尺寸可以为45～49微米，例如，可以为47微米；第三有效发光区2300的尺寸可以为38～42微米，例如，可以为40微米。
例如，如图1A和图1B所示，第一子电源信号线410在衬底基板100上的正投影与两个第二有效发光区2200在衬底基板100上的两个正投影的两个中心之间的距离之比为0.9～1.1。例如，第一子电源信号线410在衬底基板100上的正投影与两个第二有效发光区2200在衬底基板100上的两个正投影的两个中心之间的距离大致相等。由此，第二颜色子像素对包括的两个第二有效发光区相对于第一子电源信号线对称分布，有利于确保第二颜色子像素对包括的两个第二颜色子像素的环境一致性。例如，第一子电源信号线410在衬底基板100上的正投影也可以更靠近第二颜色子像素对中之一。例如，第一子电源信号线410在衬底基板100上的正投影与第二颜色子像素对中的两个第二颜色子像素的第二电极投影不重叠。
上述正投影的中心指正投影的形状的几何中心，有效发光区在衬底基板上的正投影的形状由有效发光区的形状决定，有效发光区的形状与其对应的像素限定层的开口的形状大致相同。
例如，如图1A和图1B所示，第二颜色子像素对220包括的每个第二有效发光区2200的形状包括五边形、圆形或者水滴形。例如，图1A和图1B示意性的示出每个第二有效发光区2200的形状为五边形，五边形包括一组平行的对边(平行于第二方向)以及一条垂直边(平行于第一方向)，垂直边与一组平行的对边垂直，每个第二颜色子像素对220中的两个第二有效发光区2200的两条垂直边相邻设置。例如，第一子电源信号线410位于上述两条垂直边之间，且穿过上述两条垂直边之间的最短连线的中点。
此外，虽然在图1A和图1B中的第二颜色子像素的第二有效发光区的形状包括严格的由两条线段形成的角，但在一些实施例中，第二颜色子像素的第二有效发光区的形状可以均为圆角图形，例如圆形或者水滴形。也就是，在上述五边形形状的基础上，第二颜色子像素的第二有效发光区的角被倒圆。例如，形成像素限定层的开口时，开口的角落处的部分则可能会形成圆角形状，从而形成的发光区的形状可能为圆角形状。
例如，如图1A-图2所示，显示基板还包括：位于第一电源信号线400与衬底基板100之间第二电源信号线500，第二电源信号线500沿第二方向延伸。第二子电源信号线420在衬底基板100上的正投影与第二电源信号线500在衬底基板100上的正投影至少部分交叠，且两个第二有效发光区2200在衬底基板100上的正投影与第二电源信号线500在衬底基板100上的正投影有交叠。即，沿垂直于衬底基板100的方向，断口421与第二电源信号线500有交叠。例如，第二子电源信号线420在衬底基板100上的正投影位于第二电源信号线500在衬底基板100上的正投影内。例如，第二电源信号线可以与第二子电源信号线的除了断口以外的部分大致重合，但第二子电源信号线的线宽有部分调整而未与第二电源信号线完全重合，例如，第二电源信号线与第二子电源信号线交叠部 分的面积占第二电源信号线的面积的70％以上。
例如，第二子电源信号线420在其延伸方向上的不同位置处，第二子电源信号线420在第一方向上的宽度略有不同，例如，第二子电源信号线420在对应某些颜色子像素的位置处的宽度减小。同理，第二电源信号线500在其延伸方向上的不同位置处的沿第一方向上的宽度略有不同。
例如，如图1A-图1B所示，位于同一重复单元组且彼此相邻的两个重复单元200包括第一重复单元201和第二重复单元202，第一重复单元201的第三颜色子像素230与第二重复单元202的第一颜色子像素210相邻，与第一重复单元201和第二重复单元202均相邻且位于相邻重复单元组中的重复单元200为第三重复单元203。第三重复单元203中的第一颜色子像素210与第一重复单元201中的第三颜色子像素230之间设置有一条连续的第二子电源信号线420，即第一子信号线4201，位于该连续的第二子电源信号线420两侧且与该第二子电源信号线420紧邻的一列第一颜色子像素210和一列第三颜色子像素230在该第二子电源信号线420上的正投影沿第二方向交替排列。第一颜色子像素210在该连续的第二子电源信号线420上的正投影位置处的第二子电源信号线420的宽度为第一宽度，第一颜色子像素210和第三颜色子像素230在该第二子电源信号线420上的相邻两个正投影之间的间隔位置处的第二子电源信号线420的宽度为第二宽度，第三颜色子像素230在该连续的第二子电源信号线420上的正投影位置处的第二子电源信号线420的宽度为第三宽度，第一宽度小于第二宽度，且第三宽度小于第二宽度。上述第一宽度和第三宽度可以相同，也可以不同，例如，第三宽度小于第一宽度。该连续的第二子电源信号线420包括分别对应于第一颜色子像素210和第三颜色子像素230的第一段和第二段，以及连接第一段和第二段的连接段。沿第二方向，该连续的第二子电源信号线420的第一段和第二段交替排列。第一段的远离相应的第一颜色子像素210的第一中心线的边缘与连接段远离该第一中心线的边缘位于沿第二方向延伸的同一条直线上，第一段的靠近相应的第一颜色子像素201的第一中心线的边缘距第一中心线的距离大于连接段靠近该第一中心线的边缘与第一中心线之间的距离。同理，第二段的远离相应的第三颜色子像素的第三中心线的边缘与连接段远离该第三中心线的边缘位于沿第二方向延伸的同一条直线上，第二段的靠近相应的第三颜色子像素的第三中心线的边缘距第三中心线的距离大于连接段靠近该第三中心线的边缘与第三中心线之间的距离。也就是，第一段和位于第一段两侧的连接段形成了朝向第一颜色子像素凹陷的第一凹陷部，第二段和位于第二段两侧的连接段形成了朝向第三颜色子像素凹陷的第二凹陷部，第一凹陷部和第二凹陷部的设置可以防止第一有效发光与第三有效发光区与第二子电源信号线交叠，减少色偏。
例如，第一重复单元201中的第三颜色子像素230和第三重复单元203中的第一颜色子像素210之间设置有一条包括断口的第二子电源信号线420，即，第二子信号线4202。例如，第一子信号线4201与第二子信号线4202沿第一方向交替排列，且数量大致相等。例如，第二子信号线4202包括彼此断开的多个信号线段，各信号线段可以通过位于第二 电源信号线与第二子信号线之间的绝缘层中的过孔实现与第二电源信号线的电连接。
例如，沿第二方向排列的相邻两个断口之间的第二子电源信号线420(信号线段)包括沿第二方向依次连接的第三段、第四段以及第五段，沿第一方向，第三段的宽度可以与第五段的宽度大致相等，且第三段的宽度和第五段的宽度均大于第四段的宽度。由此，第三段、第四段和第五段形成了朝向第二重复单元202中的第一颜色子像素210凹陷的第三凹陷部。第四段在衬底基板上的正投影落入第二电源信号线在衬底基板上的正投影内，以防止影响显示基板的透光率。第二子电源信号线的第四段与第一子电源信号线电连接。
同理，第二电源信号线500也具有与第二子电源信号线相同的特征，在此不再赘述。
例如，第一颜色子像素210的第一有效发光区2100在第二子信号线4202上的正投影与断口421没有交叠，即第一颜色子像素210的第一有效发光区2100在第二子信号线4202上的正投影位于信号线段内。例如，第三颜色子像素230的第三有效发光区2300在第二子信号线4202上的正投影与断口421没有交叠，即第三颜色子像素230的第三有效发光区2300在第二子信号线4202上的正投影位于信号线段内。
例如，第二子电源信号线420的第一段沿第一方向的宽度可以为2.5～3.7微米，第二子电源信号线420的连接段沿第一方向的宽度可以为5.8～7微米。例如，位于第三颜色子像素230两侧且与其紧邻的两条第二子电源线420之一的连接段与另一条的第三段的彼此靠近的边缘之间的距离大致为23.4～26微米。
例如，第二子电源信号线420以及第二电源信号线500的，各自有部分区域在第一方向的宽度大致相等且基本完全交叠。例如，断口的两个边缘的位置均位于第二子电源信号线420以及第二电源信号线500的基本完全交叠的区域。例如，沿第二方向排列的相邻的两个断口的彼此靠近的边缘之间的距离(即一个信号线段的长度)大于一个像素电路在第二方向的尺寸。例如，各断口沿第二方向的尺寸小于一个像素电路在第二方向的尺寸。例如，沿第二方向排列的相邻的两个断口的彼此靠近的边缘之间的距离(即一个信号线段的长度)大致为69～75微米。例如，像素电路沿第二方向的尺寸大致为63～65微米。例如，断口沿第二方向的尺寸大致为52～57微米。例如，断口沿第二方向的尺寸与一个像素电路在第二方向的尺寸的比例为0.8～0.9。例如，沿第二方向排列的相邻的两个断口的彼此靠近的边缘之间的距离(即一个信号线段的长度)与一个像素电路在第二方向的尺寸的比例为1.1～1.2。
例如，如图1A-图1B所示，断口421的沿第二方向的尺寸D3与位于断口421内的两个第二有效发光区2200和间隔S的沿第二方向的尺寸之和D2的差值的一半D1可以为1.8～6.5微米。例如，断口421的沿第二方向的尺寸D3与位于断口421内的两个第二有效发光区2200和间隔S的沿第二方向的尺寸之和D2的比值可以为1.07～1.25。
例如，如图1A-图2所示，第一电源信号线400与各子像素的第二电极之间设置有第一平坦层121以起到平坦化的作用。第一电源信号线400与第二电源信号线500之间设置有第二平坦层122和钝化层123以起到平坦化的作用。本公开实施例不限于第一电 源信号线400与第二电源信号线500之间设置有第二平坦层122和钝化层123，也可以仅设置第二平坦层122，不设置钝化层123。
例如，如图1A-图2所示，两个第二有效发光区2200在衬底基板100上的两个正投影的两个中心位于第二电源信号线500在衬底基板100上的正投影内。沿垂直于衬底基板100的方向，第二有效发光区2200虽然与第二电源信号线500有交叠，但是第二电源信号线500穿过两个第二有效发光区的中心，可以保证第二有效发光区2200沿第一方向具有的较好的对称性，以改善色偏。
例如，如图1A和图1B所示，相邻第二子电源信号线420之间的沿第一方向的距离大于第一有效发光区2100的沿第一方向的尺寸，且第一有效发光区2100位于相邻的第二子电源信号线420之间。同理，第一有效发光区2100位于相邻的第二电源信号线500之间。本公开实施例中，第一颜色子像素的第一有效发光区的尺寸小于相邻两条第二子电源信号线之间的距离，通过将第一有效发光区设置在相邻第二子电源信号线之间，可以防止第一有效发光区与第二子电源信号线以及第二电源线交叠，可以改善第一有效发光区内膜层的平坦性，提高第一有效发光区在第一方向上的对称性，有利于改善色偏。
例如，如图1A和图1B所示，相邻第二子电源信号线420之间的沿第一方向的距离大于第三有效发光区2300的沿第一方向的尺寸，且第三有效发光区2300位于相邻第二子电源信号线420之间。例如，第二子电源信号线420在对应第三颜色子像素230的位置处的宽度减小，以使相邻第二子电源信号线420的彼此靠近的边缘(对应于第三有效发光区位置处的两个边缘)之间的沿第一方向的距离大于第三有效发光区2300的沿第一方向的尺寸。同理，第三有效发光区2300位于相邻的第二电源信号线500之间。本公开实施例中，第三颜色子像素的第三有效发光区的尺寸小于相邻两条第二子电源信号线之间的距离，通过将第三有效发光区设置在相邻第二子电源信号线之间，可以防止第三有效发光区与第二子电源信号线以及第二电源线交叠，可以改善第三有效发光区内膜层的平坦性，提高第三有效发光区在第一方向上的对称性，有利于改善色偏。
例如，第三颜色子像素230的第二电极在衬底基板100上的正投影与第二子电源信号线420基本没有交叠。例如，第二子电源信号线420在对应第三颜色子像素230的位置处的宽度减小，以使相邻第二子电源信号线420的彼此靠近的边缘(对应于第三颜色子像素的第二电极位置处的两个边缘)之间的沿第一方向的距离大于第三颜色子像素230的第二电极的沿第一方向的尺寸。
例如，如图1A和图1B所示，沿第一方向排列的相邻两个子像素的有效发光区之间设置有一条第二子电源信号线420，即，第一有效发光区2100与第二有效发光区2200之间设置有一条第二子电源信号线420，第二有效发光区2200与第三有效发光区2300之间设置有一条第二子电源信号线420，第三有效发光区2300与第一有效发光区2100之间设置一条第二子电源信号线420。
例如，如图1A和图1B所示，多条第二子电源信号线420在第一方向上均匀分布，也就是，多条第二子电源信号线420之间的间隔大致相等。
例如，如图1A和图1B所示，在第一方向上，位于第一有效发光区2100两侧且与第一有效发光区2100紧邻的两条第二子电源信号线420的彼此靠近的边之间的距离为第一距离d1。这里以位于第一有效发光区2100一侧的第二子电源信号线420的第一段和位于第一有效发光区2100的另一侧的第二子电源信号线420的第三段的彼此靠近的边缘之间的距离为第一距离为例。位于第二有效发光区2200两侧且与第二有效发光区2200紧邻的两条第二子电源信号线420之间的距离为第二距离d2。这里以位于第二有效发光区2200一侧的第二子电源信号线420的第一段和位于第二有效发光区220的另一侧的第二子电源信号线420的第二段的彼此靠近的边缘之间的距离为第二距离为例。位于第三有效发光区2300两侧且与第三有效发光区2300紧邻的两条第二子电源信号线420之间的距离为第三距离d3。这里以位于第三有效发光区2300一侧的第二子电源信号线420的第二段和位于第三有效发光区2300的另一侧的第二子电源信号线420的第三段的彼此靠近的边缘之间的距离为第三距离为例。第一距离与第三距离之比为0.9～1.1，例如，第一距离与第三距离大致相等，第二距离大致为第一距离的两倍。上述位于有效发光区两侧且与有效发光区紧邻的第二子电源信号线指沿第一方向，该第二子电源信号线与有效发光区之间没有其他的第二子电源信号线。
例如，如图1A和图1B所示，位于第二颜色子像素对220两侧且与第二颜色子像素对220紧邻的两条第二子电源信号线420距第二颜色子像素对220的第二有效发光区2200的沿第二方向延伸的第二中心线的距离之比为0.9～1.1，例如位于第二颜色子像素对220两侧且与第二颜色子像素对220紧邻的两条第二子电源信号线420距第二颜色子像素对220的第二有效发光区2200的沿第二方向延伸的第二中心线的距离大致相等。由此，位于第二有效发光区2200两侧且与第二有效发光区2200紧邻的两条第二子电源信号线420相对于第二中心线大致对称分布，从而保证第二颜色子像素对的第二电极在第一方向上的对称性，以改善色偏。
例如，如图1A和图1B所示，位于第三颜色子像素230两侧且与第三颜色子像素230紧邻的两条第二子电源信号线420距第三颜色子像素230的第三有效发光区2300的沿第二方向延伸的第三中心线的距离之比为0.9～1.1，例如，位于第三颜色子像素230两侧且与第三颜色子像素230紧邻的两条第二子电源信号线420距第三颜色子像素230的第三有效发光区2300的沿第二方向延伸的第三中心线的距离大致相等。这里的位于第三颜色子像素230两侧的第二子电源信号线420距第三中心线的距离可以指第二子电源信号线420的靠近第三中心线的边缘与第三中心线之间的距离，位于第三颜色子像素230一侧的第二子电源信号线420对应于第三颜色子像素230的位置处宽度较窄，该位置为第二子电源信号线420的第二段，该第二段通过与连接段形成第二凹陷部以使位于第三颜色子像素230两侧且与第三颜色子像素230紧邻的两条第二子电源信号线420的彼此靠近的边缘分别与第三颜色子像素230的第三有效发光区2300的沿第二方向延伸的第三中心线的之间的距离大致相等。位于第三有效发光区2300两侧且与第三有效发光区2300紧邻的两条第二子电源信号线420相对于第三中心线大致对称分布，从而保证第三颜色子像 素的第二电极在第一方向上的对称性，以改善色偏。
例如，如图1A和图1B所示，位于第一颜色子像素210两侧且与第一颜色子像素210紧邻的两条第二子电源信号线420距第一颜色子像素210的第一有效发光区2100的沿第二方向延伸的第一中心线的距离不相等。也就是，即位于第一有效发光区2100两侧且与第一有效发光区2100紧邻的两条第二子电源信号线420相对于第一中心线并不对称分布。例如，位于第一有效发光区2100与第二有效发光区2200之间的第二子电源信号线420的靠近第一中心线的边缘与第一中心线之间的距离为第四距离。这里以位于第一重复单元201中的第一有效发光区2100与第二有效发光区2200之间的第二子电源信号线420的第一段的靠近第一中心线的边缘与第一中心线之间的距离为第四距离为例。位于第一有效发光区2100与第三有效发光区2300之间的第二子电源信号线420与第一中心线之间的距离为第五距离，第五距离大于第四距离。这里以位于第一重复单元201中的第三有效发光区2300与第二重复单元202中的第一有效发光区2100之间的第二子电源信号线420的第三段的靠近第一中心线的边缘与第一中心线之间的距离为第五距离为例。
例如，如图1A和图1B所示，第二有效发光区2200与紧邻的第二子电源信号线420的彼此相对的边缘之间的距离大于第一有效发光区2100与紧邻的第二子电源信号线420的彼此相对的边缘之间的距离。
例如，如图1A和图1B所示，不同颜色子像素的发光区边界之间的距离(PDL gap)基本上是一致的，即，沿第一方向排列的子像素中，第一有效发光区2100与第二有效发光区2200的彼此靠近的边缘之间的距离与第二有效发光区2200与第三有效发光区2300的彼此靠近的边缘之间的距离之比例如为0.9～1.1。例如，第一有效发光区2100与第二有效发光区2200的彼此靠近的边缘之间的距离大致等于第二有效发光区2200与第三有效发光区2300的彼此靠近的边缘之间的距离。由此，位于第一有效发光区与第二有效发光区之间的第二子电源信号线距第一中心线之间的距离小于位于第一有效发光区与第三有效发光区之间的第二子电源信号线距第一中心线之间的距离。
例如，如图1A和图1B所示，显示基板还包括与第一电源信号线400同层设置的多个垫块430，垫块430沿第二方向延伸，且第一有效发光区2100位于垫块430与距第一中心线距离较近(与第一有效发光区2100紧邻的第二子电源信号线420中)的第二子电源信号线420之间。例如，垫块430的靠近第一中心线的边缘与第一有效发光区2100的第一中心线之间的距离为第六距离，第六距离小于第五距离。本公开实施例通过在第一有效发光区的一侧设置垫块，有利于提高第一颜色子像素的第二电极在第一方向上的对称性，以改善色偏。
例如，第六距离与第四距离之比可为0.9～1.1，以进一步提高第一颜色子像素的第二电极在第一方向上的对称性。
例如，沿垂直于衬底基板的方向，垫块430与第一有效发光区2100没有交叠，以防止影响第一颜色子像素的显示。
例如，沿垂直于衬底基板的方向，垫块430与第一有效发光区2100远离垫块430一 侧第二子电源信号线420没有交叠。
例如，沿垂直于衬底基板的方向，垫块430与第一颜色子像素的第二电极没有交叠，或者两者交叠的面积很小，有利于减少色偏。
例如，如图1A和图1B所示，垫块430位于设置在第一颜色子像素210和第三颜色子像素230之间的第二子电源信号线420的靠近第一颜色子像素410的一侧。本公开实施例中的垫块可以减小设置在第一有效发光区远离第二有效发光区一侧的第一电源信号线所在膜层图案距第一中心线的距离，有利于提高第一颜色子像素的第二电极在第一方向上的对称性，以改善色偏。例如，垫块430可以为与设置在第一有效发光区远离第二有效发光区一侧的第一电源信号线为一体，相当于在该第一电源信号线靠近第一颜色子像素210的区域将该第一电源信号线在第一方向上加宽，使得第一颜色子像素210的第一有效发光区的两侧边缘与第一电源信号线所在膜层图案之间的距离相当，以减少色偏。例如，第一垫块430与第一电源信号线中间连接的部分可以为实体结构。例如，第一垫块430与第一电源信号线中间连接的部分可以设置为镂空结构，即在第一垫块430与第一电源信号线之间去除一部分图形，以减少与该区域交叠部分图形的寄生电容或者晶体管负载，或提高透过率。例如，第一垫块430与第一颜色子像素靠近的部分线宽不大于第一电源信号线与第一颜色子像素靠近的部分线宽。
例如，第一颜色子像素的第一有效发光区的沿第二方向的长度大于其沿第一方向的宽度，第一有效发光区的长度方向与第二子电源信号线的延伸方向一致，由此，在第一有效发光区的沿第一方向的一侧设置了沿第二方向延伸的垫块。例如，第三颜色子像素的第三有效发光区的沿第二方向的长度大于其沿第一方向的宽度，且第一有效发光区的长宽比大于第三有效发光区的长宽比。由此，第一有效发光区可能会出现其第一中心线与位于该第一有效发光区两侧且紧邻的两条第二子电源信号线的距离之差较大的情况，通过在第一有效发光区的一侧设置上述垫块，可以减小色偏。
例如，如图1A和图1B所示，在第一方向上，第一有效发光区2100的中心线与位于第一有效发光区2100两侧的垫块430和第二子电源信号线420的距离大致相等。也就是，位于第一中心线两侧的垫块430以及第二子电源信号线距该第一中心线的距离大致相等，从而可以进一步提高第一颜色子像素的第二电极在第一方向上的对称性，有利于改善色偏。
例如，如图1A和图1B所示，垫块430与第一电源信号线400电连接以防止垫块处于浮置(floating)状态，影响有机发光元件正常工作。
例如，如图1A和图1B所示，沿垂直于衬底基板100的方向，垫块430与第一子电源信号线410有交叠，且彼此电连接，第一子电源信号线410为垫块430提供电信号。例如，第一子电源信号线410可以与垫块430一体成型以节省工艺。
例如，垫块430的形状大致为长条形，且垫块430在衬底基板100上的正投影的中心位于第一子电源信号线410在衬底基板100上的正投影内。
例如，如图1A和图1B所示，垫块430沿第二方向的尺寸大于其沿第一方向的尺寸。 沿第二方向，垫块430的尺寸小于第一有效发光区2100的尺寸。本公开实施例中的显示基板应用于屏下指纹检测时，垫块沿第二方向的尺寸设计小于第一有效发光区的尺寸，例如，垫块尽量与透光区域(后面描述)没有交叠，有利于提高显示基板的透光率。
例如，如图1A和图1B所示，显示基板还包括与垫块430同层设置的连接部440。垫块430与第二子信号线4202之间具有间隔，且连接部440位于第二子电源信号线420(即第二子信号线4202)与垫块430之间，且垫块430通过连接部440连接至第二子电源信号线420。
例如，连接部440沿第二方向的尺寸可以为36～40微米，例如可以为38微米。例如，沿第二方向，连接部440的尺寸小于第一有效发光区2100以及第三有效发光区2300的尺寸。
例如，连接部440在沿第二方向延伸的直线上的正投影可以位于第三有效发光区2300在该直线上的正投影内。
例如，垫块430和连接部440在沿第二方向延伸的直线上的正投影均位于第三有效发光区2300在该直线上的正投影内。
例如，垫块430在第二方向的尺寸小于第三有效发光区2300在第二方向的尺寸。
例如，位于连接部440与第三颜色子像素230之间的第二子电源信号线420与垫块430的彼此靠近的边缘之间的距离可以为11～13微米，例如可以为12微米。
例如，连接部440、垫块430以及第二子电源信号线420形成环状结构。
例如，如图1A和图1B所示，连接部440包括两个子连接部，垫块430的两个端部分别通过两个子连接部与第二子电源信号线420电连接。本公开实施例提供的连接部、垫块以及与连接部连接的第二子电源信号线形成了环形回路，有利于第一颜色子像素的均一性。
例如，各子连接部沿第二方向的尺寸可以为2.5～3.5微米，例如可以为3微米。两个子连接部彼此靠近的边缘之间的距离可以为32微米。
例如，连接部440、垫块430以及第二子电源信号线420为一体设置的结构，以节省工艺步骤。
例如，垫块430通过连接部440连接至第二子信号线4202，且垫块430在与连接至该垫块430的第二子信号线4202相邻的另一条第二子信号线4202上的正投影位于该另一条第二子信号线4202的断口421内。
例如，本公开实施例中的显示基板应用于屏下指纹检测时，连接部与透明区域(后面描述)没有交叠，可以保证不影响显示基板的透光率。
例如，图3A为沿图1A和图1B所示的BB’所截的局部截面结构示意图，图3B为沿图1B所示的CC’所截的局部截面结构示意图。如图1A-图3B所示，在垂直于衬底基板100的方向上，第一有效发光区2100与第二子电源信号线420以及第二电源信号线500没有交叠，从而可以保证第一有效发光区沿第一方向具有较好的对称性，以改善色偏。同理，在垂直于衬底基板100的方向上，第三有效发光区2300与第二子电源信号线420 以及第二电源信号线500没有交叠，从而可以保证第三有效发光区沿第一方向具有较好的对称性。
例如，如图1A-图3B所示，第一有效发光区2100的第一中心线与数据线Vd(后面描述)有交叠，从而可以保证第一有效发光区沿第一方向具有较好的对称性。例如，数据线Vd沿第二方向贯穿第一有效发光区2100，使得第一有效发光区2100沿第二方向具有一定均匀性。本公开实施例中的“贯穿”指数据线、第一电源信号线等结构与有效发光区在平面上的位置关系。
例如，如图1A和图1B所示，第一颜色子像素210的第一有效发光区2100和第三颜色子像素230的第三有效发光区2300的形状均包括六边形或者椭圆形。例如，第一有效发光区2100和第三有效发光区2300的形状均为六边形，六边形中的三组对边均平行，且还六边形包括平行于第二方向的边。该六边形包括沿第一方向延伸的对称轴以及沿第二方向延伸的对称轴。
虽然图1A所示的第一有效发光区和第三有效发光区的形状包括严格的由两条线段形成的角，但在一些实施例中，第一有效发光区和第三有效发光区的形状可以均为圆角图形，例如椭圆形。也就是，在上述六边形的基础上，第一有效发光区和第三有效发光区的角被倒圆。例如，形成像素限定层的开口时，开口的角落处的部分则可能会形成圆角形状，从而形成的第一有效发光区和第三有效发光区的形状可能为圆角形状。
例如，如图1A-图3B所示，第一有效发光区2100在衬底基板100上的正投影的中心位于第一子电源信号线410在衬底基板100上的正投影内。例如，第一子电源信号线410在衬底基板100上的正投影穿过第一有效发光区2100在衬底基板100上的正投影的中心。也就是，在平面图中，第一有效发光区2100相对于第一子电源信号线410呈对称分布，即，第一子电源信号线410与第一有效发光区2100的沿第一方向延伸的对称轴重合，可以保证第一有效发光区2100沿第二方向具有的较好的对称性，以改善色偏。
例如，如图1A-图3B所示，第三有效发光区2300在衬底基板100上的正投影的中心位于第一子电源信号线410在衬底基板100上的正投影内。例如，第一子电源信号线410在衬底基板100上的正投影穿过第三有效发光区2300在衬底基板100上的正投影的中心。也就是，在平面图中，第三有效发光区2300相对于第一子电源信号线410大致呈对称分布，即，第三有效发光区2300的沿第一方向延伸的对称轴落在第一子电源信号线410内，可以保证第三有效发光区2300沿第二方向具有的较好的对称性，以改善色偏。
例如，图4为各子像素包括的与有机发光元件连接的像素电路的示意图。如图4所示，各子像素还包括驱动有机发光元件发光的像素电路0221，像素电路0221可以包括驱动电路0222、第一发光控制电路0223、第二发光控制电路0224、数据写入电路0226、存储电路0227、阈值补偿电路0228和复位电路0229。驱动电路0222包括控制端、第一端和第二端，且被配置为对有机发光元件0220提供驱动有机发光元件0220发光的驱动电流。
例如，第一发光控制电路0223与第一电压端VDD以及驱动电路0222的第一端电连 接，且被配置为实现驱动电路0222和第一电压端VDD之间的连接导通或断开；第二发光控制电路0224与驱动电路0222的第二端和有机发光元件0220的第一电极电连接，且被配置为实现驱动电路0222和有机发光元件0220之间的连接导通或断开。数据写入电路0226与驱动电路0222的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路0227。存储电路0227与驱动电路0222的控制端和第一电压端VDD电连接，且被配置为存储数据信号。阈值补偿电路0228与驱动电路0222的控制端和第二端电连接，且被配置为对驱动电路0222进行阈值补偿。复位电路0229与驱动电路0222的控制端和有机发光元件0220的第一电极电连接，且配置为在复位控制信号的控制下对驱动电路0222的控制端和有机发光元件0220的第一电极进行复位。
例如，如图4所示，驱动电路0222包括驱动晶体管T1，驱动电路0222的控制端包括驱动晶体管T1的栅极，驱动电路0222的第一端包括驱动晶体管T1的第一极，驱动电路0222的第二端包括驱动晶体管T1的第二极。数据写入电路0226包括数据写入晶体管T2，存储电路0227包括电容C，阈值补偿电路0228包括阈值补偿晶体管T3，第一发光控制电路0223包括第一发光控制晶体管T4，第二发光控制电路0224包括第二发光控制晶体管T5，复位电路0229包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
例如，如图4所示，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；电容C的第一极与第一电源端VDD电连接，电容C的第二极与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与有机发光元件0220的第一电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与有机发光元件0220的第二电极电连接，第二发光控制晶体管T5的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；有机发光元件0220的第一电极与第二电源端VSS电连接。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如， 如图4所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
例如，如图4所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置第二扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T2的栅极电连接到第一扫描信号线Ga1，阈值补偿晶体管T3的栅极电连接到第二扫描信号线Ga2，而第一扫描信号线Ga1和第二扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T2的栅极和阈值补偿晶体管T3可以被分开单独控制，增加控制像素电路的灵活性。
例如，如图4所示，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T4的栅极电连接到第一发光控制信号线EM1，第二发光控制晶体管T5的栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T4和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T4为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，第一子复位控制信号和第二子复位控制信号可以相同，即，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T6的栅极电连接到第一复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一子复位控制信号和第二子复位控制信号也可以不相同。
例如，在一些示例中，第二子复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到扫描信号线Ga以接收扫描信号作为第二子复位控制信号。
例如，第一复位晶体管T6的源极和第二复位晶体管T7的源极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2 可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T6的源极和第二复位晶体管T7的源极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的栅极和发光元件0220的第一电极进行复位即可，本公开对此不作限制。例如，第一复位晶体管T6的栅极和第二复位晶体管T7的源极可以均连接至复位电源信号线Init。
需要说明的是，图4所示的像素电路中的驱动电路0222、数据写入电路0226、存储电路0227、阈值补偿电路0228和复位电路0229仅为示意性的，驱动电路0222、数据写入电路0226、存储电路0227、阈值补偿电路0228和复位电路0229等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图4所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图5-图11为本公开一些实施例提供的一种像素电路以及各信号线的各层层叠的示意图。下面结合附图5-图11描述像素电路中的各个电路以及各信号线在背板上的位置关系，图5-图11所示的示例以四个子像素包括的四个相邻的像素电路0221为例，且以一个子像素包括的像素电路的各晶体管的位置进行示意，其他子像素中像素电路包括的部件与该子像素包括的各晶体管的位置大致相同。如图5所示，该子像素的像素电路0221包括图4所示的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7、电容C。
例如，图5示出了该显示基板中像素电路的有源半导体层310。有源半导体层310可采用半导体材料图案化形成。有源半导体层310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管 T5、第一复位晶体管T6和第二复位晶体管T7的有源层。有源半导体层310包括各子像素的各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，有源半导体层310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，沿第一方向排列的不同颜色子像素的像素电路中的有源半导体层没有连接关系，彼此断开。沿第二方向排列的子像素的像素电路中的有源半导体层可以为一体设置，也可以彼此断开。
图5-图11还示出了电连接到各个颜色子像素的像素电路0121的扫描信号线Ga(包括第一扫描信号线Ga1和第二扫描信号线Ga2)、复位控制信号线Rst(包括第一复位控制信号线Rst1和第二复位控制信号线Rst2)、复位电源端Vinit的复位电源信号线Init(包括第一复位电源端Vinit1的第一复位电源信号线Init1以及第二复位电源端Vinit2的第二复位电源信号线Init2)、发光控制信号线EM(包括第一发光控制信号线EM1和第二发光控制信号线EM2)、数据线Vd以及第一电源信号线400以及第二电源信号线500。第一电源信号线400和第二电源信号线500彼此电连接。
需要说明的是，在图5至图11所示的示例中，第一扫描信号线Ga1和第二扫描信号线Ga2为同一条信号线Ga，第一复位电源信号线Init1和第二复位电源信号线Init2为同一条信号线Init，第一复位控制信号线Rst1和第二复位控制信号线Rst2为同一条信号线Rst，第一发光控制信号线EM1和第二发光控制信号线EM2为同一条信号线EM，但不限于此。
例如，像素电路的栅极金属层可以包括第一导电层和第二导电层。在上述的有源半导体层310上形成有栅极绝缘层(图2所示的栅极绝缘层160)，用于将上述的有源半导体层310与后续形成的栅极金属层绝缘。图6示出了该显示基板包括的第一导电层320，第一导电层320设置在栅极绝缘层上，从而与有源半导体层310绝缘。第一导电层320可以包括电容C的第二极CC2、扫描信号线Ga、复位控制信号线Rst、发光控制信号线EM以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。
例如，如图6所示，数据写入晶体管T2的栅极可以为扫描信号线Ga与有源半导体层310交叠的部分；第一发光控制晶体管T4的栅极可以为发光控制信号线EM与有源半导体层310交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线EM与有源半导体层310交叠的第二部分；第一复位晶体管T6的栅极为复位控制信号线Rst与有源半导体层310交叠的第一部分，第二复位晶体管T7的栅极为复位控制信号线Rst 与有源半导体层310交叠的第二部分；阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为扫描信号线Ga与有源半导体层310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从扫描信号线Ga突出的突出结构P与有源半导体层310交叠的部分。如图4和6所示，驱动晶体管T1的栅极可为电容C的第二极CC2。
需要说明的是，图5和图6中的各虚线矩形框示出了第一导电层320与有源半导体层310交叠的各个部分。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。
例如，如图6所示，扫描信号线Ga、复位控制信号线Rst和发光控制信号线EM沿第二方向(Z方向)排布。扫描信号线Ga位于复位控制信号线Rst和发光控制信号线EM之间。
例如，在第二方向上，电容C的第二极CC2(即驱动晶体管T1的栅极)位于扫描信号线Ga和发光控制信号线EM之间。从扫描信号线Ga突出的突出结构P位于扫描信号线Ga的远离发光控制信号线EM的一侧。
例如，如图6所示，在第二方向上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极和第一复位晶体管T6的栅极均位于驱动晶体管T1的栅极的第一侧，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极以及第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第二侧。例如，图6所示的示例中，子像素的像素电路的驱动晶体管T1的栅极的第一侧和第二侧为在第二方向上驱动晶体管T1的栅极的彼此相对的两侧。例如，如图6所示，在XZ面内，子像素的像素电路的驱动晶体管T1的栅极的第一侧可以为驱动晶体管T1的栅极的上侧，子像素的像素电路的驱动晶体管T1的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管T1的栅极的下侧，为驱动晶体管T1的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管T1的栅极的更远离IC的一侧。
例如，在一些实施例中，如图6所示，在第一方向(X方向)上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。例如，图6所示的示例中，子像素的像素电路的驱动晶体管T1的栅极的第三侧和第四侧为在第一方向X上驱动晶体管T1的栅极的彼此相对的两侧。例如，像素电路的驱动晶体管T1的栅极的第三侧可以为像素电路的驱动晶体管T1的栅极的左侧，像素电路的驱动晶体管T1的栅极的第四侧可以为像素电路的驱动晶体管T1的栅极的右侧。所述左侧和右侧，例如与同一像素电路连接的数据线Vd和第二电源信号线500中，数据线Vd在第二电源信号线500左侧，第二电源信号线500在数据线Vd右侧。
需要说明的是，各个像素电路的结构可以为图6所示的镜像结构，即各个像素电路的各层结构均以驱动晶体管T1的沟道区为基准，左右两侧的结构进行翻转，因此上述所 述的左侧和右侧的关系可以是相反的。
例如，在上述的第一导电层320上形成有第一绝缘层(如图2所示的第一绝缘层150)，用于将上述的第一导电层320与后续形成的第二导电层330绝缘。图7示出了该像素电路的第二导电层330，第二导电层330包括电容C的第一极CC1、复位电源信号线Init以及遮光部S。电容C的第一极CC1与电容C的第二极CC2至少部分重叠以形成电容C。
例如，如图7所示，双栅型阈值补偿晶体管T3两段沟道之间的有源半导体层在阈值补偿晶体管T3关闭时处于浮置(floating)状态，易受周围线路电压的影响而跳变，从而会影响阈值补偿晶体管T3的漏电流，进而影响发光亮度。为了保持阈值补偿晶体管T3两段沟道之间的有源半导体层电压稳定，设计遮光部S与阈值补偿晶体管T3两段沟道之间的有源半导体层形成电容，遮光部S可以连接至第二电源信号线以获得恒定电压电压恒定，因此处于浮置状态的有源半导体层的电压可以保持稳定。遮光部S与双栅型阈值补偿晶体管T3两段沟道之间的有源半导体层交叠，还可以防止两个栅极之间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
例如，在上述的第二导电层330上形成有第二绝缘层(如图2所示的第二绝缘层140)，用于将上述的第二导电层330与后续形成的源漏极金属层340绝缘。图8示出了在上述的第二导电层330上形成有第二绝缘层中的过孔，图9示出了该像素电路的源漏极金属层340。如图8和图9所示，源漏极金属层340包括数据线Vd以及第二电源信号线500。上述数据线Vd以及第二电源信号线500均沿Z方向延伸。
例如，源漏极金属层340还包括第一连接部341、第二连接部342和第三连接部343。图8和图9示出了多个过孔的示例性位置，源漏金属层340通过所示的多个过孔与有源半导体层310、第一导电层膜层320以及第二导电层330连接。
例如，如图8和图9所示，数据线Vd通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔381与数据写入晶体管T2的第二极电连接。第二电源信号线500通过贯穿栅极绝缘层160、第一绝缘层150和第二绝缘层140的过孔382与第一发光控制晶体管T4的第一极电连接。第二电源信号线500和数据线Vd沿第一方向交替设置。第二电源信号线500通过贯穿第二绝缘层140的过孔3832与电容C的第一极CC1电连接。第二电源信号线500通过贯穿第二绝缘层的过孔3833与遮光部S电连接以为遮光部S提供恒定电压。第一连接部341的一端通过贯穿栅极绝缘层160、第一绝缘层150和第二绝缘层140中的过孔384与阈值补偿晶体管T3的第二极电连接，第一连接部341的另一端通过贯穿第一绝缘层150和第二绝缘层140中的过孔385与驱动晶体管T1的栅极(即电容C的第二极CC2)电连接。第二连接部342的一端通过贯穿第二绝缘层140中的过孔386与复位电源信号线Init电连接，第二连接部342的另一端通过贯穿栅极绝缘层160、第一绝缘层150和第二绝缘层140中的过孔387与第二复位晶体管T7的第一极电连接。第三连接部343通过贯穿栅极绝缘层160、第一绝缘层150和第二绝缘层140中的过孔352与第二发光控制晶体管T5的第二极电连接。
例如，在上述的源漏极金属层340上形成有钝化层123以及第二平坦层122(如图2-图3B所示)用于保护上述的源漏极金属层340。如图10所示，钝化层123以及第二平坦层122包括过孔351以及过孔354。
本公开实施例不限于在上述的源漏极金属层340上形成有钝化层123以及第二平坦层122。图3C为本公开实施例中另一示例中沿图1B所示的BB’线所截的截面图。例如，如图3C所示，在上述的源漏金属层340上还可以仅形成第二平坦层122，而没有形成钝化层123。
例如，图11示出了该像素电路的第三导电层350，第三导电层350包括第四连接部450以及沿X方向和Y方向交叉分布的第一电源信号线400。图11还示出了多个过孔351和354的示例性位置，第三导电层350通过所示的多个过孔351和354与源漏金属层340连接。第三导电层350远离衬底基板100的一侧设置有第一平坦层121，各个子像素的有机发光元件的第二电极可设置在第一平坦层121远离衬底基板100的一侧，且有机发光二极管的第二电极通过第一平坦层121中设置的过孔1210与第四连接部450电连接，以实现与第二发光控制晶体管T5的第二极电连接。
例如，如图1A-图1B以及图11所示，第三导电层350包括多个第四连接部450，相邻两条第二子电源信号线420之间设置有一列第四连接部450。例如，各子像素的像素电路中包括一个第四连接部450，且多个子像素包括的多个第四连接部450沿第一方向和第二方向阵列排布。例如，多个第四连接部450沿第一方向等间距排布，且多个第四连接部450沿第二方向也等间距排布。
例如，沿垂直于衬底基板100的方向，各有效发光区与第四连接部450没有交叠。例如，第三有效发光区2300在衬底基板100上的正投影的中心线穿过一列第四连接部450在衬底基板100上的正投影。例如，垫块430所在的沿第二方向延伸的直线穿过一列第四连接部450。例如，沿第一方向排列的相邻两个第四连接部450的彼此靠近的边缘之间的距离大于第二有效发光区2200的沿第一方向的尺寸。例如，沿第二方向排列的相邻两个第四连接部450的彼此靠近的边缘之间的距离大于各有效发光区的沿第二方向的尺寸。例如，沿第二方向排列的相邻两个第四连接部450的彼此靠近的边缘之间的距离小于断口421的沿第二方向的尺寸。
例如，各颜色子像素包括的第二电极与第三导电层350之间设置有第一平坦层121(图2所示)，第二电极通过第一平坦层中设置的过孔与第四连接部450连接，以实现与第二发光控制晶体管T5的第二极相连。
图12为与图11所示的各像素电路结构一一对应的有机发光元件的平面示意图，图13为各子像素的第二电极的平面形状示意图。
例如，如图1B和图12所示，沿垂直于衬底基板100的方向，第一有效发光区2100与连接至第一颜色子像素210的数据写入晶体管T2的第二极的数据线Vd交叠。
例如，如图1B和图12所示，沿垂直于衬底基板100的方向，第二有效发光区2201与连接至第二颜色子像素220的第一发光控制晶体管T4的第一极的第二电源信号线500、 第二颜色子像素220的第二连接部342以及连接至第二颜色子像素220的数据写入晶体管T2的第二极的数据线Vd均有交叠，且第二中心线与第二电源信号线500有交叠，第二连接部342和数据线Vd位于第二中心线的两侧；沿垂直于衬底基板100的方向，第二有效发光区2202与数据线Vd、第二电源信号线500以及第一连接部341均有交叠，且第二中心线与第二电源信号线500有交叠，第一连接部341和数据线Vd位于第二中心线的两侧。
例如，如图1B和图12所示，沿垂直于衬底基板100的方向，第三有效发光区2300与连接至相邻的第二颜色子像素220的数据写入晶体管T2的第二极的数据线Vd、第三颜色子像素230的第一连接部341以及第二连接部342均有交叠，且数据线Vd位于第三中心线的一侧，第一连接部341以及第二连接部342位于第三中心线的另一侧。
例如，如图12所示，沿垂直于衬底基板100的方向，第二连接部342通过过孔387与第二复位晶体管T7的第一极电连接的部分与断***叠。例如，沿垂直于衬底基板100的方向，遮光部S中沿Z方向延伸的部分与断***叠，且过孔3833与断***叠。例如，沿垂直于衬底基板100的方向，电容C的第一极CC1的通过过孔3832与第二电源信号线连接的部分与断***叠。
例如，如图5-图13所示，第一颜色子像素210的第二电极212包括第一主体电极2121和第一连接电极2122。第一主体电极2121和第一连接电极2122可以为一体结构，且第一连接电极2122通过过孔1210连接至第四连接部450，以实现与第一颜色子像素210的第二发光控制晶体管T5的第二极相连。
例如，第二颜色子像素对220中各第二颜色子像素的第二电极222包括第二主体电极2221和第二连接电极2222。第二颜色子像素对220中的第一子像素的第二电极包括第二主体部2221-1和第二连接部2222-1，第二颜色子像素对220中的第二子像素的第二电极包括第二主体部2221-2和第二连接部2222-2。例如，各第二颜色子像素的第二主体电极2221和第二连接电极2222可以为一体结构，且第二颜色子像素的第二连接电极2222通过过孔1210连接至第四连接部450，以实现与第二颜色子像素的第二发光控制晶体管T5的第二极相连。
例如，第三颜色子像素230的第二电极232包括第三主体电极2321和第三连接电极2322。例如，第三主体电极2321和第三连接电极2322可以为一体结构，且第三连接电极2322通过过孔1210连接至第四连接部450，以实现与第三颜色子像素130的第二发光控制晶体管T5的第二极相连。
例如，第一颜色子像素210的第一连接电极2122位于第一主体电极2121靠近第二颜色子像素对220的一侧，第二颜色子像素对220的第二连接电极2222位于第二主体电极2221远离第一颜色子像素210的一侧，第三颜色子像素230的第三有效发光区2300的第三中心线穿过第三主体电极2321和第三连接电极2322。
例如，如图1A、图1B、图12以及图13所示，各子像素的主体电极的形状与发光区的形状大致相同，且各子像素的主体电极的面积大于有效发光区的面积。例如，各子 像素的主体电极的几何中心与有效发光区的几何中心大致重合。例如，第一颜色子像素210的第一主体电极2121和第三颜色子像素230的第三主体电极2321的形状大致为六边形或者椭圆形，第二颜色子像素对220中的每个第二颜色子像素的第二主体电极2221的形状大致为五边形、圆形或者水滴形。
例如，图14为一种显示基板中的各子像素的第二电极的平面结构示意图。图14所示的显示基板与本公开实施例的如图1-图13所示的显示基板的不同之处在于图14所示的有机发光元件的第二电极的连接电极的形状不同于本公开实施例中如图13所示的有机发光元件的第二电极的连接电极的形状。如图14所示，第一颜色子像素的有机发光元件的第二电极包括的主体电极11的形状与其发光区1的形状均为六边形；第三颜色子像素的有机发光元件的第二电极包括的主体电极31的形状与其发光区3的形状均为六边形；第二颜色子像素的有机发光元件的第二电极包括的主体电极21的形状与其发光区2的形状均为五边形。一个第二颜色子像素的第二电极包括主体电极21-1和连接电极22-1，另一个第二颜色子像素的第二电极包括主体电极21-2以及连接电极22-2。各子像素的第二电极中的主体电极和连接电极可以为一体结构，此时主体电极与连接电极之间的边界为图14中的点划线所示的边界。由图14可以看出，各子像素的主体电极的形状可以是规则的多边形，连接电极的形状可以是不规则的形状。
在图14所示的显示基板应用于指纹检测时，可以采用光学屏下指纹检测技术。光学屏下指纹检测技术依靠光线反射来探测指纹回路，并将获得的指纹图像与数据库中的图像进行对比，以达到检测指纹的目的。光学屏下指纹检测技术在有机发光二极管显示装置中的应用尤其广泛。
光学屏下指纹检测技术通常采用显示基板发出的光作为光源，指纹传感器通常设置在显示基板的非显示侧，例如可以位于有机发光元件靠近衬底基板的一侧，以实现屏下指纹检测功能。
例如，各子像素发出的光可以用于显示以及作为屏下指纹检测的光，子像素远离衬底基板的一侧还可以设置顶膜层以放置手指；采集指纹图像的指纹传感器可以与各子像素设置于显示基板同一侧，且指纹传感器设置于各子像素有机发光元件靠近衬底基板的一侧，用于检测从顶膜层的表面的指纹反射的反射光。指纹传感器可以包括多个阵列排布的检测单元。为了实现屏下指纹检测功能，上述顶层膜和衬底基板等膜层的至少部分是透明的，并且相邻的子像素之间设置有透明区域(该透明区域为显示基板的透明区域)，以使顶层膜表面的指纹的反射光可以入射到指纹传感器上，以获取指纹图像。由于各子像素的有机发光元件的阳极(第二电极)由不透光材料形成，因此，各子像素的阳极的遮光面积会影响光透过率，进而影响到指纹检测的灵敏度。
如图14所示，第一颜色子像素中，有效发光区1和第二电极的面积比大致为52.85％；第二颜色子像素中，有效发光区2和第二电极的面积比大致为42.31％；第三颜色子像素中，有效发光区3与第二电极的面积比大致为66.99％。第一颜色子像素的第二电极、第二颜色子像素对中的两个第二电极以及第三颜色子像素中的第二电极的面积比为1： 1.58：1.16。
在保证各子像素的发光区的面积不变的情况下，可以通过改变第二电极位于有效发光区以外的区域例如连接电极的形状而减少遮光面积，增加显示基板的透明区域的面积，进而提高指纹检测的灵敏度。
在各子像素的有效发光区的面积不变的情况下，相比于图14所示的显示基板中各子像素的第二电极的形状，本公开实施例提供的显示基板通过减小各子像素的位于有效发光区以外的区域例如连接电极的面积，可以减小第二电极对光的遮挡面积，提高显示基板的光透过率。
例如，如图1A、图12-图13所示，第一颜色子像素210中，第一有效发光区2100与第二电极212的面积比为53％～55％，第二颜色子像素对220中，两个第二有效发光区2200与两个第二电极222的面积比为43.5％～48％，第三颜色子像素230中，第三有效发光区2300与第二电极232的面积比为67.5％～69％。本公开实施例中的第一颜色子像素、第二颜色子像素以及第三颜色子像素可与图14中的第一颜色子像素、第二颜色子像素以及第三颜色子像素一一对应。例如，第一颜色子像素210中，第一有效发光区2100与第二电极212的面积比为54.9％，第二颜色子像素对220中，两个第二有效发光区2200与两个第二电极222的面积比为47％，第三颜色子像素230中，第三有效发光区2300与第二电极232的面积比为68.3％，从而，显示基板整体透过率提升大致0.23％。相比于图14所示的显示基板，本公开实施例通过提高各子像素的有效发光区与第二电极的面积比，可以提高显示基板整体透过率，进而提高指纹检测的灵敏度。
例如，第一有效发光区2100、第二颜色子像素对220中的两个第二有效发光区2200以及第三有效发光区2300的面积比大致为1：1.27：1.47；第一颜色子像素210的第二电极212、第二颜色子像素对220中的两个第二电极222以及第三颜色子像素230中的第二电极232的面积比大致为1：1.48：1.18。
例如，如图1A-图13所示，各子像素中，连接电极与主体电极连接的部分设置有至少一个凹口，沿垂直于衬底基板100的方向，显示基板在对应于凹口的至少一部分的区域为透明区域。这里的透明区域10包括没有设置像素电路0221、第一电源信号线400、第二电源信号线500、数据线Vd、扫描信号线Ga、复位电源信号线Init、复位控制信号线Rst以及发光控制信号线EM的区域。也就是，透明区域10指光可以从衬底基板100上没有被遮光膜层覆盖的透光区入射到指纹传感器的区域，遮光膜层包括有源半导体层310、第一导电层320、第二导电层330、源漏金属层340、第三导电层350、各子像素的第二电极所在膜层。例如，在对应于凹口的至少一部分的区域，没有有源半导体层310、第一导电层320、第二导电层330、源漏金属层340以及第三导电层350的投影落在该区域内。例如，在对应于凹口的至少一部分的区域，没有过孔、连接部、垫块的投影落在该区域内。例如，在对应于凹口的至少一部分的区域，设置有一层或多层绝缘层，例如栅极绝缘层160、第一绝缘层150、第二绝缘层140、钝化层123、第一平坦层121以及第二平坦层122等中的一层或多层，且所述一层或多层绝缘层的透过率大于有源半导体 层310、第一导电层320、第二导电层330、源漏金属层340、第三导电层350中的任意一层。例如，在对应于凹口的至少一部分的区域，设置有一层或多层绝缘层，例如栅极绝缘层160、第一绝缘层150、第二绝缘层140、钝化层123、第一平坦层121以及第二平坦层122等中的一层或多层，且多层绝缘层依次形成在显示基板上，并且在透明区域，所述多层绝缘层之间彼此紧邻，即从远离显示基板的方向上，第二层绝缘层与第一层绝缘层直接接触，第三层绝缘层与第二层绝缘层直接接触。例如，所述一层或多层绝缘层可以为有机层，也可以为无机层。例如，在对应于凹口的至少一部分的区域，设置为透明区域，在该区域，栅极绝缘层形成于衬底基板的表面，第一绝缘层位于栅极绝缘层远离衬底基板的表面，第二绝缘层位于第一绝缘层远离衬底基板的表面，钝化层位于第二绝缘层远离衬底基板的表面，第二平坦层位于钝化层远离衬底基板的表面，第一平坦层位于第二平坦层远离衬底基板的表面，且第二电极例如阳极在该位置为凹口，即第一平坦层远离衬底基板的表面上与第二电极之后形成的像素限定层直接接触。例如，在对应于凹口的至少一部分的区域，设置为透明区域，在该区域，栅极绝缘层形成于衬底基板的表面，第一绝缘层位于栅极绝缘层远离衬底基板的表面，第二绝缘层位于第一绝缘层远离衬底基板的表面，第二平坦层位于第二绝缘层远离衬底基板的表面，第一平坦层位于第二平坦层远离衬底基板的表面，且第二电极例如阳极在该位置为凹口，即第一平坦层远离衬底基板的表面上与第二电极之后形成的像素限定层直接接触。例如，如图12-图13所示，第一颜色子像素210中，第一连接电极2122与第一主体电极2121的连接部分设置有第一凹口2123，显示基板在对应于第一凹口2123的至少一部分的区域为透明区域10。也就是，第一凹口2123的部分与有源半导体层310、第一导电层320、第二导电层330、源漏金属层340、第三导电层350均没有交叠，第一凹口2123的与上述膜层没有交叠的区域形成了显示基板的透明区域。如图13-图14所示，第一凹口2123为本公开实施例中的第一连接电极2122相对于图14所示的连接电极12向内凹陷的部分，上述凹陷部分的一部分与有源半导体层310、第一导电层320以及源漏金属层340等遮光膜层有交叠，上述凹陷部分的另一部分仅与衬底基板100以及多层透明的绝缘层有交叠。也就是，该第一凹口的位置的选取需考虑其与除第二电极所在膜层以外的遮光膜层暴露的透光区域的位置关系，该第一凹口的至少部分与上述透光区域共同形成了显示基板的透明区域。
例如，图14所示的连接电极12的与主体电极11连接的边大致为直边，图13所示的第一凹口2123是由上述直边向靠近第一主体电极2121一侧弯曲后形成的凹口。相对于图14所示的显示基板，本公开实施例通过将第一连接电极与透明区域正对的地方设置凹口，可以提高显示基板的光透过率，进而提高指纹检测的灵敏度。
例如，如图12-图13所示，沿垂直于衬底基板100的方向，连接至第一颜色子像素210的像素电路的发光控制信号线EM、第二电源信号线500、包括各子像素的各晶体管的沟道区和源漏掺杂区的有源半导体层310以及存储电容C的第一极CC1包围的区域101与第一颜色子像素210的第二电极212的第一凹口2123有交叠。相对于图14所述的 连接电极12，本公开实施例中通过在第一连接电极2122对应于区域101的位置设置第一凹口2123，可以增加显示基板的光透过率。
例如，如图12-图13所示，第一颜色子像素210中，第一连接电极2122通过第一连接过孔1211连接至第四连接部450，第一凹口2123位于第一连接过孔1211远离与该第一颜色子像素210位于同一重复单元的第二颜色子像素220的一侧，第一凹口2123的凹陷的程度取决于第一连接电极2122的边缘与第一连接过孔1211的距离，第一凹口2123需要避开第一连接过孔1211，以防止影响第一连接电极2122与第四连接部450的电连接。例如，第一凹口2123为由第一连接过孔1211正对的第一连接电极2122的远离上述第二颜色子像素220的一侧边缘向内凹形成的凹口，且凹口的边缘延伸到第一主体电极2121的边缘。
例如，如图14所示，连接电极12靠近主体电极11一侧的部分的沿X方向的宽度较宽，也就是与连接电极12连接的连接过孔的部分到主体电极11之间的部分沿X方向的宽度较宽，由此，将图14所示的连接电极12上形成图13所示的第一凹口2123后，可以保证第一连接电极2122仍可以通过第一连接过孔1211保持与第四连接部450可靠的连接。
例如，如图12-图13所示，第二颜色子像素对220的第一子像素的第二电极222-1中，第一连接电极2222-1与第一主体电极2221-1的连接部分设置有第二凹口2223-1，显示基板在对应于第二凹口2223-1的至少一部分的区域为透明区域。也就是，第二凹口2223-1的部分与有源半导体层310、第一导电层320、第二导电层330、源漏金属层340、第三导电层350均没有交叠，第二凹口2223-1的与上述膜层没有交叠的区域形成了显示基板的透明区域。如图13-图14所示，第二凹口2223-1为本公开实施例中的第二连接电极2222-1相对于图14所示的连接电极22-1凹陷的部分，上述凹陷部分的一部分与有源半导体层310、第一导电层320以及源漏金属层340等遮光膜层有交叠，上述凹陷部分的另一部分仅与衬底基板100以及多层透明的绝缘层有交叠，也就是，该第二凹口的位置的选取需考虑其与除第二电极所在膜层以外的遮光膜层暴露的透光区域的位置关系，该第二凹口的至少部分与上述透光区域共同形成了显示基板的透明区域。
例如，图14所示的连接电极22-1的与主体电极21-1连接的边大致为直边，图13所示的第二凹口2223-1是由上述直边向靠近第二主体电极2221-1一侧弯曲后形成的凹口。相对于图14所示的显示基板，本公开实施例通过将第二连接电极与透明区域正对的地方设置凹口，可以提高显示基板的光透过率，进而提高指纹检测的灵敏度。
例如，如图12-图13所示，沿垂直于衬底基板100的方向，连接至第二颜色子像素对220的第一子像素的像素电路的发光控制信号线EM、第二电源信号线500以及存储电容C的第一极CC1包围的区域中靠近发光控制信号线EM的部分区域102与第一子像素的第二电极222-1的第二凹口2223-1有交叠。相对于图14所述的连接电极22-1，本公开实施例中通过在第二连接电极2222-1对应于区域102的位置设置第二凹口2223-1，可以增加显示基板的光透过率。
例如，如图12-图13所示，第二颜色子像素对220的第二子像素的第二电极222-2中，第二连接电极2222-2与第二主体电极2221-2的连接部分设置有第三凹口2223-2，显示基板在对应于第三凹口2223-2的至少一部分的区域为透明区域。也就是，第三凹口2223-2的部分与有源半导体层310、第一导电层320、第二导电层330、源漏金属层340、第三导电层350均没有交叠，第三凹口2223-2的与上述膜层没有交叠的区域形成了显示基板的透明区域。如图13-图14所示，第三凹口2223-2为本公开实施例中的第二连接电极2222-2相对于图14所示的连接电极22-2凹陷的部分，上述凹陷部分的一部分与有源半导体层310、第一导电层320以及源漏金属层340等遮光膜层有交叠，上述凹陷部分的另一部分仅与衬底基板100以及多层透明的绝缘层有交叠，也就是，第三凹口的位置的选取需考虑其与除第二电极所在膜层以外的遮光膜层暴露的透光区域的位置关系，该第三凹口的至少部分与上述透光区域共同形成了显示基板的透明区域。
例如，图14所示的连接电极22-2的与主体电极21-2连接的边大致为直边，图13所示的第二凹口2223-2是由上述直边向远离第一颜色子像素的一侧弯曲后形成的凹口。相对于图14所示的显示基板，本公开实施例通过将第二连接电极与透明区域正对的地方设置凹口，可以提高显示基板的光透过率，进而提高指纹检测的灵敏度。
例如，如图12-图13所示，第二颜色子像素对220的第二子像素中，第二连接电极2222-2包括沿第二方向延伸的第一部分2-1以及弯曲的第二部分2-2，第一部分2-1位于第二部分2-2远离第二主体电极2221-2的一侧，第二部分2-2与主体电极2221-2连接，且第一部分2-1沿第一方向的最大尺寸大于第二部分2-2沿第一方向的最大尺寸。
例如，如图12-图13所示，沿垂直于衬底基板100的方向，连接至第二子像素的像素电路的发光控制信号线EM、第二电源信号线500以及第三连接部343包围的区域中靠近第二电源信号线500和发光控制信号线EM的部分区域103与第二子像素的第二电极222-2的第三凹口2223-2有交叠。
相对于图14所示的连接电极22-2，本公开实施例中通过在第二连接电极2222-2对应于区域103的位置设置第三凹口2223-2，从而可以增加显示基板的光透过率。
图14所示的连接电极22-2包括的第一部分22-21与本公开实施例所述的第二连接电极2222-2包括的第一部分2-1的形状以及尺寸基本相同，而图14所示的连接电极22-2包括的第二部分22-22沿第一方向的尺寸大于第一部分22-21沿第一方向的尺寸，且第二部分22-22覆盖了除第二电极所在膜层以外的遮光膜层暴露的透光区域的一部分，所以通过减小第二部分22-22与上述透光区域交叠的部分的面积，例如将其靠近第一颜色子像素的第一有效发光区的且覆盖上述透光区域的部分去掉而形成第三凹口2223-2，可以提高显示基板的光透过率。
例如，图14所示的连接电极22-2的第二部分22-22与主体电极21-2的靠近第一颜色子像素的第一边和远离第一颜色子像素的第二边均连接，而本公开实施例中的第二连接电极2222-2的第二部分2-2仅与第二主体电极2221-2的远离第一颜色子像素的第二边连接，从而可以使得第二主体电极的第一边附近的透光区域不被第二连接电极覆盖。
例如，如图12-图13所示，第二子像素中，第二连接电极2222-2与第一发光控制晶体管T4的源漏掺杂区没有交叠。图14所示的连接电极22-2的第二部分22-22靠近第一颜色子像素的第一有效发光区1的部分覆盖了第一发光控制晶体管T4的源漏掺杂区。本公开实施例通过将图14所示的连接电极22-2的第二部分22-22靠近第一颜色子像素的部分去掉，可以使得第二连接电极2222-2的第二部分2-2与第一发光控制晶体管T4的源漏掺杂区没有交叠，从而可以使得第二部分2-2与第一发光控制晶体管T4的源漏掺杂区附近的透光区域没有交叠，提高显示基板的光透过率。
例如，如图12-图13所示，第二颜色子像素220中，第一连接电极2222-1通过第二连接过孔1212-1连接至第四连接部450，第二凹口2223-1位于第二连接过孔1212-1靠近与该第二颜色子像素220位于同一重复单元的第一颜色子像素210的一侧，第二凹口2223-1的凹陷的程度取决于第一连接电极2222-1的边缘与第二连接过孔1212-1的距离，第二凹口2223-1需要避开第二连接过孔1212-1，以防止影响第一连接电极2222-1与第四连接部450的电连接。例如，第二凹口2223-1为由第二连接过孔1212-1正对的第一连接电极2222-1的靠近上述第一颜色子像素210的一侧边缘向内凹形成的凹口，且凹口的边缘延伸到第一主体电极2221-1的边缘。
例如，如图14所示，连接电极22-1靠近主体电极21-1一侧的部分的沿X方向的宽度较宽，也就是与连接电极22-1连接的连接过孔的部分到主体电极21-1之间的部分沿X方向的宽度较宽，由此，将图14所示的连接电极22-1上形成图13所示的第二凹口2223-1后，可以保证第一连接电极2222-1仍可以通过第二连接过孔1212-1保持与第四连接部450可靠的连接。
例如，如图12-图13所示，第二颜色子像素220中，第一连接电极2222-2通过第三连接过孔1212-2连接至第四连接部450，第三凹口2223-2位于第三连接过孔1212-2靠近与该第二颜色子像素220位于同一重复单元的第一颜色子像素210的一侧，第三凹口2223-2的凹陷的程度取决于第一连接电极2222-2的边缘与第三连接过孔1212-2的距离，第三凹口2223-2需要避开第三连接过孔1212-2，以防止影响第一连接电极2222-2与第四连接部450的电连接。例如，第三凹口2223-2为由第三连接过孔1212-2正对的第一连接电极2222-2的靠近上述第一颜色子像素210的一侧边缘向内凹形成的凹口，且凹口的边缘延伸到第一主体电极2221-2的边缘。
例如，如图14所示，连接电极22-2靠近主体电极21-2一侧的部分的沿X方向的宽度较宽，也就是与连接电极22-2连接的连接过孔的部分到主体电极21-2之间的部分沿X方向的宽度较宽，由此，将图14所示的连接电极22-2上形成图13所示的第三凹口2223-2后，可以保证第一连接电极2222-2仍可以通过第三连接过孔1212-2保持与第四连接部450可靠的连接。
例如，如图12-图13所示，第三颜色子像素对230的第二电极232中，第三连接电极2322与第三主体电极2321的连接部分设置有第四凹口2323，显示基板在对应于第四凹口2323的至少一部分的区域为透明区域10。也就是，第四凹口2323的部分与有源半 导体层310、第一导电层320、第二导电层330、源漏金属层340、第三导电层350均没有交叠，第四凹口2323的与上述膜层没有交叠的区域形成了显示基板的透明区域。如图13-图14所示，第四凹口2323为本公开实施例中的第二连接电极232相对于图14所示的连接电极2322凹陷的部分，上述凹陷部分的一部分与有源半导体层310、第一导电层320以及源漏金属层340等遮光膜层有交叠，上述凹陷部分的另一部分仅与衬底基板100以及多层透明的绝缘层有交叠，也就是，第四凹口的位置的选取需考虑其与除第二电极所在膜层以外的遮光膜层暴露的透光区域的位置关系，该第四凹口的至少部分与上述透光区域共同形成了显示基板的透明区域。
例如，图14所示的连接电极32的与主体电极31连接的边大致为直边，图13所示的第四凹口2323是由上述直边向靠近第三主体电极2321一侧弯曲后形成的凹口。相对于图14所示的显示基板，本公开实施例通过将第二连接电极与除第二电极所在膜层以外的遮光膜层暴露的透光区域正对的地方设置凹口，可以提高显示基板的光透过率，进而提高指纹检测的灵敏度。
例如，如图12-图13所示，沿垂直于衬底基板100的方向，连接至第二颜色像素对的第二子像素的像素电路的数据线Vd、有源半导体层310以及存储电容C的第一极CC1所在膜层围成的区域中远离发光控制信号线EM的部分区域104与第三颜色子像素230的第二电极2322的第四凹口2323有交叠。相对于图14所示的连接电极32，本公开实施例中通过在第三连接电极2322对应于区域104的部分设置第四凹口2323，从而可以增加显示基板的光透过率。
图14所示的连接电极32靠近第一颜色子像素的部分与除第二电极所在膜层以外的遮光膜层暴露的透光区域有交叠，本公开实施例通过将第三连接电极2322的靠近第一颜色子像素的且覆盖上述透光区域得到部分去掉而形成第四凹口2323，可以提高显示基板的光透过率。
例如，如图12-图13所示，第三颜色子像素230中，第一连接电极2322通过第四连接过孔1213连接至第四连接部450，第四凹口2323位于第四连接过孔1213靠近与该第三颜色子像素230相邻的第一颜色子像素210的一侧，第四凹口2323的凹陷的程度取决于第一连接电极2322的边缘与第四连接过孔1213的距离，第四凹口2323需要避开第四连接过孔1213，以防止影响第一连接电极2223与第四连接部450的电连接。例如，第四凹口2323为由第四连接过孔1213正对的第一连接电极2223的靠近上述第一颜色子像素210的一侧边缘向内凹形成的凹口，且凹口的边缘延伸到第一主体电极2321的边缘。
例如，如图14所示，连接电极32靠近主体电极31一侧的部分的沿X方向的宽度较宽，也就是与连接电极32连接的连接过孔的部分到主体电极31之间的部分沿X方向的宽度较宽，由此，将图14所示的连接电极32上形成图13所示的第四凹口2323后，可以保证第一连接电极2223仍可以通过第四连接过孔1213保持与第四连接部450可靠的连接。
本公开另一实施例提供一种显示装置，包括上述任一显示基板。包括上述显示基板 的显示装置可以尽量避免色偏现象的发生。
本公开实施例提供的显示装置可以应用指纹检测技术，且该显示装置包括的显示基板具有较高的指纹检测灵敏度。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (37)

  1. 一种显示基板，包括：
    衬底基板；
    第一电源信号线，位于所述衬底基板上，所述第一电源信号线包括沿第一方向延伸的多条第一子电源信号线以及沿第二方向延伸的多条第二子电源信号线，所述第一子电源信号线与所述第二子电源信号线相连；
    像素限定层，位于所述第一电源信号线远离所述衬底基板的一侧，所述像素限定层包括多个开口以限定多个子像素的有效发光区，所述多个子像素包括沿所述第二方向排列的两个子像素组成的子像素对，所述子像素对包括彼此间具有间隔的两个子有效发光区；
    其中，在平面图中，所述第一子电源信号线穿过所述两个子有效发光区之间的间隔，至少一条所述第二子电源信号线包括至少一个断口，所述两个子有效发光区以及位于所述两个子有效发光区之间的所述间隔均位于所述断口处，以使连接所述第二子电源信号线的同一断口的两个端点的沿所述第二方向延伸的虚拟直线贯穿所述两个子有效发光区以及所述间隔。
  2. 根据权利要求1所述的显示基板，其中，沿垂直于所述衬底基板的方向，具有所述断口的所述第二子电源信号线与所述两个子有效发光区以及所述间隔均没有交叠。
  3. 根据权利要求1或2所述的显示基板，还包括：
    多条第二电源信号线，沿所述第二方向延伸，位于所述第一电源信号线与所述衬底基板之间，且所述第二电源信号线与所述第二子电源信号线通过位于所述第二子电源信号线与所述第二电源线之间的绝缘层中的过孔电连接，
    其中，所述第二子电源信号线在所述衬底基板上的正投影与所述第二电源信号线在所述衬底基板上的正投影至少部分交叠，且所述两个子有效发光区在所述衬底基板上的正投影与所述第二电源信号线在所述衬底基板上的正投影有交叠。
  4. 根据权利要求3所述的显示基板，其中，所述第一子电源信号线在所述衬底基板上的正投影与所述两个子有效发光区的在所述衬底基板上的两个正投影的两个中心之间的距离之比为0.9～1.1。
  5. 根据权利要求3或4所述的显示基板，其中，所述两个子有效发光区在所述衬底基板上的两个正投影的两个中心位于所述第二电源信号线在所述衬底基板上的正投影内。
  6. 根据权利要求3-5任一项所述的显示基板，其中，所述显示基板包括位于所述衬底基板上的多个重复单元，所述多个重复单元的每个包括沿所述第一方向依次排列的一个第一颜色子像素、一个第二颜色子像素对以及一个第三颜色子像素，所述第二颜色子像素对包括两个相同颜色的第二颜色子像素，且沿所述第二方向排列的所述两个子像素组成的所述子像素对为所述第二颜色子像素对；
    所述第一颜色子像素包括第一有效发光区，所述两个子有效发光区为两个第二有效发光区，且所述第三颜色子像素包括第三有效发光区。
  7. 根据权利要求6所述的显示基板，其中，沿所述第二方向，所述间隔的尺寸小于所述第一有效发光区的尺寸，且所述间隔的尺寸小于所述第三有效发光区的尺寸。
  8. 根据权利要求6或7所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第一有效发光区与所述第二子电源信号线以及所述第二电源信号线均没有交叠。
  9. 根据权利要求8所述的显示基板，其中，所述第一有效发光区位于相邻的所述第二子电源信号线之间，且所述第一有效发光区位于相邻的所述第二电源信号线之间。
  10. 根据权利要求8或9所述的显示基板，其中，所述第一有效发光区在所述衬底基板上的正投影的中心位于所述第一子电源信号线在所述衬底基板上的正投影内。
  11. 根据权利要求8-10任一项所述的显示基板，还包括：
    多个垫块，沿所述第二方向延伸，且与所述第一电源信号线同层设置，
    其中，位于所述第一有效发光区两侧且与所述第一有效发光区紧邻的两条第二子电源信号线距所述第一有效发光区的沿所述第二方向延伸的中心线的距离不相等，且所述第一有效发光区位于所述垫块与距所述第一有效发光区的所述中心线距离较近的所述第二子电源信号线之间。
  12. 根据权利要求11所述的显示基板，其中，在所述第一方向上，所述第一有效发光区的中心线与位于所述第一有效发光区两侧的所述垫块和所述第二子电源信号线的距离之比为0.9～1.1。
  13. 根据权利要求11或12所述的显示基板，其中，沿垂直于所述衬底基板的方向，所述垫块与所述第一子电源信号线交叠，且彼此电连接。
  14. 根据权利要求13所述的显示基板，其中，所述垫块的形状大致为长条形，且所述垫块在所述衬底基板上的正投影的中心位于所述第一子电源信号线在所述衬底基板上的正投影内。
  15. 根据权利要求11-14任一项所述的显示基板，其中，沿所述第一方向排列且彼此相邻的所述第一颜色子像素和所述第三颜色子像素之间设置有所述垫块，且所述垫块与位于所述第一颜色子像素与所述第三颜色子像素之间的所述第二子电源信号线电连接。
  16. 根据权利要求15所述的显示基板，还包括：
    连接部，与所述垫块同层设置，且位于所述第二子电源信号线与所述垫块之间，
    其中，所述垫块通过所述连接部连接至所述第二子电源信号线。
  17. 根据权利要求16所述的显示基板，其中，所述垫块和与其连接的所述第二子电源信号线之间具有间隔，所述连接部位于所述垫块和所述第二子电源信号线之间，且所述连接部、所述垫块以及所述第二子电源信号线形成环状结构。
  18. 根据权利要求16或17所述的显示基板，其中，多条所述第二子电源信号线包括沿所述第一方向交替排列的第一子信号线和第二子信号线，所述第一子信号线为连续 的信号线，所述第二子信号线为具有所述断口的信号线。
  19. 根据权利要求18所述的显示基板，其中，所述垫块通过所述连接部连接至所述第二子信号线，且所述垫块在与连接至该垫块的所述第二子信号线相邻的另一条所述第二子信号线上的正投影位于该另一条所述第二子信号线的断口内。
  20. 根据权利要求11-19任一项所述的显示基板，其中，沿所述第二方向，所述垫块的尺寸小于所述第一有效发光区的尺寸。
  21. 根据权利要求6-20任一项所述的显示基板，其中，在垂直于所述衬底基板的方向，所述第三有效发光区与所述第二子电源信号线以及所述第二电源信号线没有交叠。
  22. 根据权利要求21所述的显示基板，其中，所述第三有效发光区位于相邻的所述第二子电源信号线之间，且所述第三有效发光区位于相邻的所述第二电源信号线之间。
  23. 根据权利要求21或22所述的显示基板，其中，所述第三有效发光区在所述衬底基板上的正投影的中心位于所述第一子电源信号线在所述衬底基板上的正投影内。
  24. 根据权利要求21-23任一项所述的显示基板，其中，位于所述第三颜色子像素两侧且与所述第三颜色子像素紧邻的两条所述第二子电源信号线在所述衬底基板上的正投影与所述第三有效发光区在所述衬底基板上的正投影的中心的距离之比为0.9～1.1。
  25. 根据权利要求6-24任一项所述的显示基板，其中，各所述子像素包括有机发光元件，所述有机发光元件包括依次层叠设置的第一电极、发光层以及第二电极，所述发光层的至少部分位于所述开口内，且所述第二电极位于所述像素限定层面向所述衬底基板的一侧，
    所述第一颜色子像素中，所述第一有效发光区与所述第二电极的面积比为53％～55％；所述第二颜色子像素对中，所述两个第二有效发光区与两个第二电极的面积比为43.5％～48％；所述第三颜色子像素中，所述第三有效发光区与所述第二电极的面积比为67.5％～69％。
  26. 根据权利要求25所述的显示基板，其中，所述第一有效发光区和所述第三有效发光区的形状包括六边形或者椭圆形，所述第二颜色子像素对包括的每个所述第二有效发光区的形状包括五边形、圆形或者水滴形。
  27. 根据权利要求26所述的显示基板，其中，各颜色子像素的所述第二电极包括彼此连接的主体电极和连接电极，所述主体电极的形状与相应子像素的有效发光区的形状大致相同；
    各所述子像素中，所述连接电极与所述主体电极连接的部分设置有凹口，沿垂直于所述衬底基板的方向，所述显示基板在对应于所述凹口的至少一部分的区域为透明区域。
  28. 根据权利要求27所述的显示基板，还包括：
    多条数据线，沿所述第二方向延伸，且与所述第二电源信号线同层设置；
    多条扫描信号线，沿所述第一方向延伸，且位于所述数据线所在膜层面向所述衬底基板的一侧；
    多条复位电源信号线，沿所述第一方向延伸，且位于所述扫描信号线所在膜层与所 述数据线所在膜层之间；
    多条复位控制信号线，沿所述第一方向延伸，且与所述扫描信号线同层设置；以及
    多条发光控制信号线，沿所述第一方向延伸，且与所述扫描信号线同层设置，
    其中，各所述子像素还包括驱动所述有机发光元件的像素电路，所述像素电路包括驱动晶体管、数据写入晶体管、存储电容、阈值补偿晶体管、第一发光控制晶体管、第二光控制晶体管、第一复位晶体管和第二复位晶体管；
    所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极与所述数据线电连接以接收数据信号，所述数据写入晶体管的栅极与所述扫描信号线电连接以接收扫描信号；
    所述存储电容的第一极与所述第二电源信号线电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接；
    所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接，所述阈值补偿晶体管的栅极与所述扫描信号线电连接以接收补偿控制信号；
    所述第一复位晶体管的第一极与所述复位电源信号线电连接以接收第一复位信号，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的栅极与所述复位控制信号线电连接以接收第一子复位控制信号；
    所述第二复位晶体管的第一极与所述复位电源信号线电连接以接收第二复位信号，所述第二复位晶体管的第二极与所述有机发光元件的第一电极电连接，所述第二复位晶体管的栅极与所述复位控制信号线电连接以接收第二子复位控制信号；
    所述第一发光控制晶体管的第一极与所述第二电源信号线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极与所述发光控制信号线电连接以接收第一发光控制信号；
    所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述有机发光元件的第二电极电连接，所述第二发光控制晶体管的栅极与所述发光控制信号线电连接以接收第二发光控制信号；
    其中，所述显示基板还包括与所述数据线同层设置的第一连接部、第二连接部以及第三连接部，以及与所述第一电源信号线同层设置的第四连接部，所述第一连接部被配置为连接所述阈值补偿晶体管的第二极和所述驱动晶体管的栅极，所述第二连接部被配置为连接所述复位电源信号线和所述第二复位晶体管的第一极，所述第三连接部被配置为连接所述第二发光控制晶体管的第二极与所述第四连接部，所述第四连接部被配置为连接所述第三连接部和所述有机发光元件的第二电极的所述连接电极。
  29. 根据权利要求28所述的显示基板，其中，所述透明区域包括没有设置所述像素电路、所述第一电源信号线、所述第二电源信号线、所述数据线、所述扫描信号线、所述复位电源信号线、所述复位控制信号线以及所述发光控制信号线的区域。
  30. 根据权利要求29所述的显示基板，其中，沿垂直于所述衬底基板的方向，连接 至所述第一颜色子像素的所述像素电路的所述发光控制信号线、所述第二电源信号线、包括各所述子像素的各晶体管的沟道区和源漏掺杂区的有源半导体层以及所述存储电容的第一极包围的区域与所述第一颜色子像素的第二电极的凹口有交叠。
  31. 根据权利要求30所述的显示基板，其中，沿垂直于所述衬底基板的方向，连接至所述第二颜色子像素对的第一子像素的所述像素电路的所述发光控制信号线、所述第二电源信号线以及所述存储电容的第一极包围的区域中靠近所述发光控制信号线的部分区域与所述第一子像素的第二电极的凹口有交叠。
  32. 根据权利要求30或31所述的显示基板，其中，所述第二颜色子像素对的第二子像素中，所述连接电极包括沿所述第二方向延伸的第一部分以及弯曲的第二部分，所述第一部分位于所述第二部分远离所述主体电极的一侧，所述第二部分与所述主体电极连接，且所述第一部分沿所述第一方向的最大尺寸大于所述第二部分沿所述第一方向的最大尺寸。
  33. 根据权利要求32所述的显示基板，其中，所述第二子像素中，所述连接电极与所述第一发光控制晶体管的源漏掺杂区没有交叠。
  34. 根据权利要求32或33所述的显示基板，其中，沿垂直于所述衬底基板的方向，连接至所述第二子像素的所述像素电路的所述发光控制信号线、所述第二电源信号线以及所述第三连接部包围的区域中靠近所述第二电源信号线和所述发光控制信号线的部分区域与所述第二子像素的第二电极的凹口有交叠。
  35. 根据权利要求34所述的显示基板，其中，沿垂直于所述衬底基板的方向，连接至所述第二子像素的所述像素电路的所述数据线、所述有源半导体层以及所述存储电容的第一极所在膜层围成的区域中远离所述发光控制信号线的部分区域与所述第三颜色子像素的第二电极的凹口有交叠。
  36. 根据权利要求6-35任一项所述的显示基板，其中，所述第一颜色子像素为红色子像素，所述第二颜色子像素为绿色子像素，所述第三颜色子像素为蓝色子像素。
  37. 一种显示装置，包括权利要求1-36任一项所述的显示基板。
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