WO2021208637A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2021208637A1
WO2021208637A1 PCT/CN2021/079674 CN2021079674W WO2021208637A1 WO 2021208637 A1 WO2021208637 A1 WO 2021208637A1 CN 2021079674 W CN2021079674 W CN 2021079674W WO 2021208637 A1 WO2021208637 A1 WO 2021208637A1
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layer
shielding layer
shielding
electrode
magnetic
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PCT/CN2021/079674
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English (en)
French (fr)
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吴玉雷
吴保磊
王晓光
平尔萱
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长鑫存储技术有限公司
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Priority to EP21788560.7A priority Critical patent/EP3992969A4/en
Priority to US17/593,874 priority patent/US20230217837A1/en
Publication of WO2021208637A1 publication Critical patent/WO2021208637A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1695—Protection circuits or methods

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a semiconductor structure and a manufacturing method thereof.
  • STT Spin Transfer Torque
  • MRAM Magnetic Memory
  • the core of its storage unit is a MTJ (Magnetic Tunnel Junction), which consists of a stacked structure of magnetic layers, The first electrode and the second electrode are formed, wherein the magnetic layer stack structure includes a free layer, a spacer layer and a fixed layer stacked from top to bottom, the second electrode is located on the top of the free layer, and the first electrode is located on the bottom of the fixed layer.
  • MTJ Magnetic Tunnel Junction
  • STT-MRAM is susceptible to interference from external electromagnetic fields, and the current chip-level shielding is not enough to completely shield the interference from external electromagnetic fields.
  • a semiconductor structure and a manufacturing method thereof are provided to shield interference from external electromagnetic fields.
  • a method for manufacturing a semiconductor structure includes:
  • a second electrode that penetrates the shielding layer and is electrically connected to the storage structure is formed.
  • the storage structure includes a magnetic layer stack structure.
  • the step of forming the first electrode penetrating the first shielding layer includes:
  • the first electrode is formed in the first opening.
  • the method before the second shielding layer is formed on the top and sidewalls of the storage structure, the method further includes:
  • a second dielectric layer covering the top and sidewalls of the magnetic layer stack structure is formed, and the first dielectric layer and the second dielectric layer together constitute an isolation layer.
  • the materials of the first shielding layer and the second shielding layer include conductive materials and/or magnetically permeable materials.
  • it includes:
  • the materials of the first shielding layer and the second shielding layer are different;
  • the first shielding layer and the second shielding layer remaining under the second shielding layer on the sidewall of the magnetic layer stack structure form the shielding layer.
  • the bottom of the shielding layer is lower than the bottom of the magnetic layer stack structure.
  • the top of the magnetic layer stack structure is arc-shaped.
  • the lateral dimension of the magnetic layer stack structure is larger than the lateral dimension of the first electrode.
  • the step of forming a second electrode that penetrates the shielding layer and is electrically connected to the storage structure includes:
  • the second electrode is formed in the second opening.
  • the embodiment of the present invention also provides a semiconductor structure, including:
  • the first electrode is located in the substrate
  • a shielding layer covering the top and side walls of the storage structure, and the bottom of the shielding layer is lower than the bottom of the storage structure
  • the second electrode penetrates the shielding layer on the top of the storage structure and is electrically connected to the storage structure.
  • the storage structure includes a magnetic layer stack structure.
  • the magnetic layer stack structure includes a fixed layer, a spacer layer and a free layer.
  • the material of the fixed layer and the free layer includes Co, Fe, B, Ta or Ru; the material of the spacer layer includes Mg or O.
  • the top of the magnetic layer stack structure is arc-shaped.
  • it further includes:
  • the isolation layer includes a first dielectric layer and a second dielectric layer
  • the first dielectric layer is located between the shielding layer and the first electrode
  • the second dielectric layer is located between the shielding layer and the magnetic laminated structure.
  • the lateral dimension of the magnetic layer stack structure is larger than the lateral dimension of the first electrode.
  • the shielding layer includes a first shielding layer and a second shielding layer
  • the first shielding layer is located between the first dielectric layer and the substrate, wherein one end of the first shielding layer is located in the projection area of the magnetic layer stack structure on the substrate;
  • the second shielding layer is located on the outer surface of the sidewall of the first dielectric layer and the outer surface of the second dielectric layer.
  • the materials of the first shielding layer and the second shielding layer include conductive materials and/or magnetically permeable materials; the materials of the first shielding layer and the second shielding layer are different.
  • the bottom of the second electrode is on the same horizontal plane as the top surface of the magnetic layer stack structure, the top surface of the shielding layer, and the top surface of the isolation layer.
  • a semiconductor structure and a manufacturing method thereof are provided.
  • the first shielding layer By forming the first shielding layer first, and then sequentially forming the first electrode, the storage structure, and the second shielding layer, the first shielding layer and the second shielding layer form a shielding layer covering the storage structure. Good shielding of external electromagnetic field interference to the storage structure, ensuring that information can be stored and read and written correctly.
  • FIG. 1 is a flowchart of a manufacturing method of a semiconductor structure according to an embodiment
  • FIGS. 2 to 11 are structural schematic diagrams during the formation of a semiconductor structure provided by an embodiment
  • FIG. 12 is a schematic structural diagram of a semiconductor structure provided by an embodiment
  • FIG. 13 is a schematic structural diagram of a semiconductor structure provided by another embodiment
  • FIG. 14 is a schematic structural diagram of a semiconductor structure provided by another embodiment.
  • an embodiment provides a method for fabricating a semiconductor structure, including:
  • Step S110 providing a substrate 100
  • Step S120 forming a first shielding layer 200a on the substrate 100;
  • Step S130 forming a first electrode 400 penetrating the first shielding layer 200a;
  • Step S140 forming a storage structure 500 on the first electrode 400;
  • Step S150 forming a second shielding layer 200b on the top and sidewalls of the storage structure 500, and the first shielding layer 200a and the second shielding layer 200b together form the shielding layer 200;
  • step S160 a second electrode 600 that penetrates the shielding layer 200 and is electrically connected to the storage structure 500 is formed.
  • the first shielding layer 200a and the second shielding layer 200b form the storage structure covering the storage structure.
  • the shielding layer 200 of 500 can better shield the interference of the external electromagnetic field on the storage structure, and ensure that the information can be stored and read and written correctly.
  • step S110 is performed to provide the substrate 100.
  • the substrate 100 provided may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-coated insulating substrate, but is not limited to this.
  • the substrate of the element can be any.
  • the substrate 100 may include device structures, such as semiconductor transistors and plugs connected to the semiconductor transistors.
  • step S120 is performed to form a first shielding layer 200 a on the substrate 100.
  • a shielding material is deposited on the substrate 100 through a deposition process to form a first shielding layer 200a covering the surface of the substrate 100.
  • the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
  • the shielding material can be a material with good conductivity, such as silver, copper, gold, etc., which can play a good shielding effect on the electric field; the shielding material can also be a material with good magnetic permeability, such as iron (Fe) , Cobalt (Co) and nickel (Ni) alloys, such as cobalt-iron, nickel-iron and nickel-cobalt-iron, various combinations of NiFe and Co and other alloys with higher magnetic permeability, doped amorphous ferromagnetic alloys Wait. It should be noted that the material with good conductivity can also play a certain shielding effect on the magnetic field, and the material with good magnetic permeability can also play a certain shielding effect on the electric field.
  • a first dielectric layer 300a is further formed on the first shielding layer 200a.
  • a dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride is deposited on the first shielding layer 200a through a deposition process to form the first dielectric layer 300a covering the first shielding layer 200a.
  • the first dielectric layer 300a can be used as a hard mask for patterning the first shielding layer 200a, and can also be used as a part of an isolation layer between the first shielding layer 200a and a subsequently formed storage structure.
  • step S130 is performed to form a first electrode 400 penetrating the first shielding layer 200a.
  • a first opening (not shown in the figure) is formed in the first shielding layer 200a and the first dielectric layer 300a by using photolithography and etching processes; a first electrode is formed in the first opening
  • the first electrode layer fills the trenches and covers the first dielectric layer 300a.
  • the first electrode layer is formed by physical weather deposition, chemical vapor deposition or electroplating processes, and the second An electrode layer is a conductive material layer, such as a metal material layer with good conductivity such as Al, W, Cu, etc.; the first electrode layer covering the upper surface of the first dielectric layer 300a is removed to form a layer in the first opening The first electrode 400.
  • the first electrode layer covering the upper surface of the first dielectric layer 300a may be removed by using an etch-back or chemical mechanical polishing process to form the first electrode 400.
  • the top of the first electrode 400 is flush with the top of the first dielectric layer 300a. It can be understood that when the top of the first electrode 400 is flush with the top of the first dielectric layer 300a, the bottom of the first shielding layer 200a is lower than the bottom of the subsequently formed storage structure, which increases the shielding range.
  • step S140 is performed to form a storage structure 500 on the first electrode 400.
  • the storage structure 500 is a magnetic layer stack structure.
  • Forming the magnetic layer stack structure specifically includes: as shown in FIG. 5a, a first magnetic layer 530a, a spacer material layer 520a, and a second magnetic layer 510a are sequentially deposited on the substrate 100 on which the first electrode 400 is formed; then, as shown in FIG. As shown in 5b, the first magnetic layer 530a, the spacer material layer 520a, and the second magnetic layer 510a are patterned by photolithography and etching processes to form a magnetic layer stack structure including a fixed layer 530, a spacer layer 520, and a free layer 510 .
  • the material of the first magnetic layer 530a and the second magnetic layer 510a includes Co, Fe, B, Ta or Ru; the material of the spacer material layer 520a includes Mg or O.
  • the fixed layer 530 may be CoFeB
  • the spacer layer 520 may be a MgO layer
  • the free layer 510 may be CoFeB.
  • the number of the storage structure 500 and the number of the first electrode 400 are both multiple, and the first electrode 400 and the storage structure 500 are arranged in a one-to-one correspondence; the first electrode 400 are distributed on the substrate 100 at intervals.
  • the storage structures 500 have spaces between them.
  • the top of the magnetic layer stack structure is arc-shaped.
  • the first magnetic layer 530a, the spacer material layer 520a, and the second magnetic layer 510a are etched by an ion beam etching (IBE) process to form the magnetic layer stack structure, and the magnetic layer
  • IBE ion beam etching
  • the top of the free layer 510 of the stacked structure is arc-shaped, which can increase the distance between the tops of the adjacent magnetic layer stacked structures, reduce the risk of contact with the tops of the adjacent magnetic layer stacked structures, and increase the product yield; at the same time; It is also conducive to the filling of the subsequent third dielectric layer in the space between the adjacent magnetic layer stack structures.
  • step S150 is performed to form a second shielding layer 200 b on the top and sidewalls of the storage structure.
  • the first shielding layer 200 a and the second shielding layer 200 b together form the shielding layer 200.
  • it includes: depositing a shielding material on the storage structure through a deposition process to form a second shielding layer 200b covering the top and sidewalls of the storage structure.
  • the second shielding layer 200b is connected to the first shielding layer 200a to form a shielding layer 200 covering the storage structure 500 together.
  • the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
  • the shielding material can be a material with good conductivity, such as silver, copper, gold, etc., which can play a good shielding effect on the electric field; the shielding material can also be a material with good magnetic permeability, such as iron (Fe) , Cobalt (Co) and Nickel (Ni) alloys, such as cobalt-iron, nickel-iron and nickel-cobalt-iron, various combinations of NiFe and Co and other alloys with higher magnetic permeability, doped amorphous ferromagnetic alloys Wait. It should be noted that the material with good conductivity can also play a certain shielding effect on the magnetic field, and the material with good magnetic permeability can also play a certain shielding effect on the electric field.
  • the materials of the first shielding layer 200a and the second shielding layer 200b are different.
  • the first shielding layer 200a and the second shielding layer 200b are both materials with good magnetic permeability, but the materials of the first shielding layer 200a and the second shielding layer 200b are different, for example, The first shielding layer 200a is cobalt-iron, and the second shielding layer 200b is nickel-iron; or both the first shielding layer 200a and the second shielding layer 200b are materials with good conductivity, but the first The materials of the shielding layer 200a and the second shielding layer 200b are different.
  • the first shielding layer 200a is silver, and the second shielding layer 200b is copper; or the first shielding layer 200a is made of good conductivity.
  • the material, such as copper, and the second shielding layer 200b is a material with good magnetic permeability, such as nickel-iron.
  • the first shielding layer 200a and the second shielding layer 200b have an etching selection ratio, and the self-aligned etching is used to remove the sidewalls of the magnetic layer stack structure.
  • the first shielding layer 200a except under the second shielding layer 200b; the first shielding layer 200a and the first shielding layer 200a and the The second shielding layer 200b forms the shielding layer 200.
  • This method can reduce process steps and save costs; at the same time, self-aligned etching can be used to prevent over-etching errors caused by the photolithography process and improve product yield.
  • the second shielding layer before the second shielding layer is formed on the top and sidewalls of the storage structure, it further includes: forming a second shielding layer covering the top and sidewalls of the magnetic layer stack structure.
  • Two dielectric layers 300b, the first dielectric layer 300a and the second dielectric layer 300b together constitute an isolation layer 300.
  • it includes: using a deposition process to deposit an isolation material, such as silicon oxide, silicon nitride, or silicon oxynitride, to form a second dielectric layer 300b covering the first dielectric layer 300a and the top and sidewalls of the magnetic layer stack structure Then, an etching process is used to remove the second dielectric layer 300b on the upper surface of the first dielectric layer 300a to form a second dielectric layer 300b covering only the top and sidewalls of the magnetic layer stack structure.
  • the same material is used to make the first dielectric layer 300a and the second dielectric layer 300b. Therefore, the first dielectric layer between adjacent magnetic layer stack structures can also be removed by one etching process.
  • the first dielectric layer 300 a and the second dielectric layer 300b retain the first dielectric layer 300a and the second dielectric layer 300b on the top and sidewalls of the magnetic layer stack structure.
  • the first dielectric layer 300 a and the second dielectric layer 300 b jointly constitute an isolation layer 300.
  • the isolation layer can relieve the stress of the shielding layer 200 and isolate the shielding layer 200 and the magnetic layer stack structure.
  • the lateral dimension of the magnetic layer stack structure is larger than the lateral dimension of the first electrode.
  • the size of the magnetic layer stack structure in the direction along the surface of the substrate 100 is larger than the size of the first electrode 400 in the direction along the surface of the substrate 100, so that A part of the shielding layer 200 is also formed between the substrate 100 and the magnetic layer stack structure, and the formed shielding layer 200 also has a certain shielding effect at the bottom of the magnetic layer stack structure to enhance the shielding effect.
  • step S160 is performed to form a second electrode 600 that penetrates the shielding layer 200 and is electrically connected to the storage structure. Specifically, it includes: forming a third dielectric layer 700 on the substrate 100 and the storage structure; forming a third opening 900 in the third dielectric layer 700 through photolithography and etching processes to expose the storage structure. The top of the structure 500; finally, the third opening 900 is filled with a conductive material, and the conductive material on the surface of the third dielectric layer 700 is removed by an etch-back or mechanochemical polishing process to form the second electrode 600.
  • the second electrode layer may be a metal material layer with good conductivity such as Al, W, and Cu.
  • forming a second electrode that penetrates the shielding layer and is electrically connected to the storage structure includes: the storage structure is a magnetic layer stack structure; The top of the layer stack structure is arc-shaped; a third dielectric layer 700 is formed on the substrate and the magnetic layer stack structure; a part of the shielding layer above the magnetic layer stack structure is removed by a grinding process to expose the magnetic layer A fourth dielectric layer 800 is formed on the top of the magnetic layer stack structure; a second opening (not shown in the figure) is formed in the fourth dielectric layer 800 to expose the magnetic layer stack The top of the structure; the second electrode 600 is formed in the second opening.
  • Using a grinding process to remove part of the shielding layer above the magnetic layer stack structure to expose the top of the magnetic layer stack structure can simplify the manufacturing process, and at the same time, when the second opening is subsequently formed, the shielding layer and the Etching the isolation layer can reduce damage to the magnetic layer stack structure; while the arc-shaped top structure can make the non-exposed area of the magnetic layer stack structure exposed by the grinding process.
  • the external isolation layer and shielding layer will not be removed, thereby enhancing the shielding effect.
  • the bottom of the second electrode 600 and the top surface of the magnetic layer stack structure, the top surface of the shielding layer 200 and the top surface of the isolation layer 300 are on the same level.
  • the semiconductor structure includes: a substrate 100, a first electrode 400, a storage structure 500, a shielding layer 200, and a second electrode 600.
  • the first electrode 400 is located in the substrate 100; the storage structure 500 is located on the first electrode 400; the shielding layer 200 covers the top and sidewalls of the storage structure 500, and the bottom of the shielding layer 200 is lower than The bottom of the storage structure 500; the second electrode 600 penetrates the shielding layer 200 on the top of the storage structure 500 and is electrically connected to the storage structure 500.
  • the shielding layer 200 covers the storage structure 500, which can better shield the interference of the external electromagnetic field on the storage structure 500, and ensure that information can be stored and read and written correctly.
  • the substrate 100 can be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-coated insulating substrate, but is not limited to this.
  • the substrate 100 may include device structures, such as semiconductor transistors and plugs connected to the semiconductor transistors.
  • the number of the storage structure 500, the number of the first electrode 400, and the number of the second electrode 600 are multiple, and the first electrode 400 and the second electrode 600 It is arranged in a one-to-one correspondence with the storage structure 500, and there are spaces between the storage structures 500; the semiconductor structure further includes a third dielectric layer 700, which is located on the substrate 100, and The space between the storage structures 500 is filled and used to isolate two adjacent second electrodes 600 and two adjacent shielding layers 200.
  • the third dielectric layer 700 may be formed of dielectric materials such as silicon nitride, silicon oxide, or silicon oxynitride.
  • the storage structure 500 is a magnetic layer stack structure.
  • the magnetic layer stack structure at least includes a free layer 510, a spacer layer 520, and a pinned layer 530 stacked from top to bottom.
  • the material of the free layer 510 and the pinned layer 530 includes Co, Fe, B, Ta or Ru; the material of the spacer layer includes Mg or O.
  • the fixed layer 530 may be CoFeB, the spacer layer may be a MgO layer, and the free layer 510 may be CoFeB.
  • an isolation layer 300 is further included, and the isolation layer 300 covers the magnetic laminate structure.
  • the isolation layer 300 includes a first dielectric layer 300a and a second dielectric layer 300b; the first dielectric layer 300a is located between the shielding layer 200 and the first electrode 400; the second dielectric layer 300b is located between the shielding layer 200 and the magnetic laminated structure.
  • the top of the magnetic layer stack structure is arc-shaped.
  • the top of the magnetic layer stack structure is arc-shaped, and the tops of the isolation layer 300 and the shielding layer 200 covered thereon are also arc-shaped.
  • the arc shape is an arc shape that protrudes outward
  • the top of the free layer 510 of the magnetic layer stack structure is an arc shape, which can increase the distance between the tops of the adjacent magnetic layer stack structures and reduce The risk of contacting the top of the adjacent magnetic layer stack structure increases the product yield; at the same time, it also facilitates the filling of the third dielectric layer 700 in the space between the adjacent magnetic layer stack structures.
  • the arc-shaped top structure can prevent the isolation layer 200 and the shielding layer 300 outside the non-exposed region of the magnetic layer stack structure when the top of the magnetic layer stack structure is exposed by a grinding process. Is removed, thereby enhancing the shielding effect.
  • the lateral dimension of the magnetic layer stack structure is larger than the lateral dimension of the first electrode.
  • the size of the magnetic layer stack structure along the surface of the substrate 100 is larger than the size of the first electrode 400 along the surface of the substrate 100, so that the substrate 100 and A part of the shielding layer 200 is also formed between the magnetic layer stack structure. That is, a part of the shielding layer 200 is also formed at the bottom of the magnetic layer stack structure. Shielding effect, enhance the shielding effect.
  • the shielding layer 200 includes a first shielding layer 200a and a second shielding layer 200b; the first shielding layer 200a is located between the first dielectric layer 300a and the liner. Between the bottoms 100, one end of the first shielding layer 200a is located in the projection area of the magnetic layer stack structure on the substrate 100; the second shielding layer 200b is located on the first dielectric layer 300a The outer surface of the sidewall and the outer surface of the second dielectric layer 300b. The ends of the first shielding layer 200a and the second shielding layer 200b are connected to form a shielding layer 200 covering the top, sidewalls and part of the bottom of the magnetic layer stack structure.
  • the material of the first shielding layer 200a and the second shielding layer 200b can be materials with good conductivity, such as silver, copper, gold, etc., which can effectively shield the electric field;
  • the materials of the first shielding layer 200a and the second shielding layer 200b may also be materials with good magnetic permeability, such as alloys including iron (Fe), cobalt (Co), and nickel (Ni), such as cobalt-iron, nickel-iron, and nickel. Cobalt iron, various combinations of NiFe and Co and other alloys with higher magnetic permeability, doped amorphous ferromagnetic alloys, etc.
  • the material with good conductivity can also play a certain shielding effect on the magnetic field
  • the material with good magnetic permeability can also play a certain shielding effect on the electric field.
  • the materials of the first shielding layer 200a and the second shielding layer 200b are different.
  • the first shielding layer 200a and the second shielding layer 200b are both materials with good magnetic permeability, but the materials of the first shielding layer 200a and the second shielding layer 200b are different, for example, the first shielding layer 200a and the second shielding layer 200b have different materials.
  • the layer 200a is cobalt-iron, and the second shielding layer 200b is nickel-iron; or the first shielding layer 200a and the second shielding layer 200b are both materials with good conductivity, but the first shielding layer 200a and The material of the second shielding layer 200b is different.
  • the first shielding layer 200a is silver and the second shielding layer 200b is copper; or the first shielding layer 200a is a material with good conductivity, such as copper.
  • the second shielding layer 200b is made of a material with good magnetic permeability, such as nickel iron.
  • the first shielding layer 200a and the second shielding layer 200b have an etching selection ratio, and self-aligned etching is used to remove one of the sidewalls of the first electrode 400.
  • the outer first shielding layer 200a; the first shielding layer 200a and the second shielding layer 200b remaining on the sidewalls of the first electrode 400 form the shielding layer 200.
  • This method can reduce process steps and save costs; at the same time, self-aligned etching can be used to prevent over-etching errors caused by the photolithography process and improve product yield.
  • the bottom of the second electrode 600 is in contact with the top surface of the magnetic layer stack structure, the top surface of the shielding layer 200, and the top surface of the isolation layer 300. On the same level. Specifically, as shown in FIGS.
  • the storage structure 500 is a magnetic layer stack structure; the top of the magnetic layer stack structure is arc-shaped; formed on the substrate 100 and the magnetic layer stack structure A third dielectric layer 700; a grinding process is used to remove part of the shielding layer 200 above the magnetic layer stack structure to expose the top of the magnetic layer stack structure; a fourth dielectric layer 800 is formed on the top of the magnetic layer stack structure; A second opening (not shown) is formed in the fourth dielectric layer 800 to expose the top of the magnetic layer stack structure; the second electrode 600 is formed in the second opening.
  • Using a grinding process to remove part of the shielding layer 200 above the magnetic layer stack structure to expose the top of the magnetic layer stack structure can simplify the manufacturing process, and at the same time, when the second opening is subsequently formed, the shielding layer and the The isolation layer is etched to reduce damage to the magnetic layer stack structure; while the arc-shaped top structure can make the magnetic layer stack structure unexposed when the top of the magnetic layer stack structure is exposed by a grinding process
  • the isolation layer 300 and the shielding layer 200 outside the area will not be removed, thereby enhancing the shielding effect.
  • the bottom of the second electrode 600 and the top surface of the magnetic layer stack structure, the top surface of the shielding layer 200 and the top surface of the isolation layer 300 are on the same level.

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Abstract

一种半导体结构的制作方法包括：提供衬底；在所述衬底上形成第一屏蔽层；形成贯穿所述第一屏蔽层的第一电极；在所述第一电极上形成存储结构；在所述存储结构的顶部和侧壁形成第二屏蔽层，所述第一屏蔽层与所述第二屏蔽层共同构成屏蔽层；形成贯穿所述屏蔽层且与所述存储结构电连接的第二电极。

Description

半导体结构及其制作方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
自旋转移矩(STT)磁性存储器(MRAM)是通过自旋电流实现信息写入的一种存储器，其存储单元的核心是一个MTJ(Magnetic Tunnel Junction，磁性隧道结)，由磁性层堆叠结构、第一电极和第二电极构成，其中磁性层堆叠结构包括从上到下叠层设置的自由层、间隔层和固定层，第二电极位于自由层的顶部，第一电极位于固定层的底部。
但是，STT-MRAM容易受到外部电磁场的干扰，目前芯片级的屏蔽不足以完全屏蔽外部电磁场的干扰。
发明内容
根据各个实施例，提供了一种半导体结构及其制作方法，以屏蔽外部电磁场的干扰。
一种半导体结构的制作方法，包括：
提供衬底；
在所述衬底上形成第一屏蔽层；
形成贯穿所述第一屏蔽层的第一电极；
在所述第一电极上形成存储结构；
在所述存储结构的顶部和侧壁形成第二屏蔽层，所述第一屏蔽层与所述第二屏蔽层共同构成屏蔽层；
形成贯穿所述屏蔽层且与所述存储结构电连接的第二电极。
在其中一个实施例中，所述存储结构包括磁性层堆叠结构。
在其中一个实施例中，所述形成贯穿所述第一屏蔽层的第一电极的步骤，包括：
在所述第一屏蔽层上形成第一介质层；
在所述第一屏蔽层和所述第一介质层中形成第一开口；
在所述第一开口中形成所述第一电极。
在其中一个实施例中，所述在所述存储结构的顶部和侧壁形成第二屏蔽层之前，还包括：
形成覆盖所述磁性层堆叠结构的顶部和侧壁的第二介质层，所述第一介质层和所述第二介质层共同构成隔离层。
在其中一个实施例中，所述第一屏蔽层和所述第二屏蔽层的材料包括导电性材料和/或导磁性材料。
在其中一个实施例中，包括：
所述第一屏蔽层和所述第二屏蔽层的材质不同；
利用自对准刻蚀工艺去除所述磁性层堆叠结构侧壁上的所述第二屏蔽层下方之外的所述第一屏蔽层；
所述磁性层堆叠结构侧壁上的所述第二屏蔽层下方保留的所述第一屏蔽层和所述第二屏蔽层形成所述屏蔽层。
在其中一个实施例中，所述屏蔽层的底部低于所述磁性层堆叠结构的底部。
在其中一个实施例中，所述磁性层堆叠结构的顶部呈弧形。
在其中一个实施例中，所述磁性层堆叠结构的横向尺寸大于所述第一电极的横向尺寸。
在其中一个实施例中，所述形成贯穿所述屏蔽层且与所述存储结构电连接的第二电极的步骤，包括：
在所述衬底和所述屏蔽层上形成第三介质层；
利用研磨工艺去除所述磁性层堆叠结构上方的部分屏蔽层以暴露所述磁性层堆叠结构的顶部；
在所述磁性层堆叠结构的顶部形成第四介质层；
在所述第四介质层中形成第二开口，以暴露出所述磁性层堆叠结构的顶部；
于所述第二开口中形成所述第二电极。
本发明实施例还提供了一种半导体结构，包括：
衬底；
第一电极，位于所述衬底内；
存储结构，位于所述第一电极上；
屏蔽层，覆盖所述存储结构的顶部和侧壁，且所述屏蔽层的底部低于所述存储结构的底部；以及
第二电极，贯穿所述存储结构顶部的所述屏蔽层且与所述存储结构电连接。
在其中一个实施例中，所述存储结构包括磁性层堆叠结构。
在其中一个实施例中，所述磁性层堆叠结构包括固定层、间隔层和自由层。
在其中一个实施例中，所述固定层和所述自由层的材质包含Co、Fe、B、Ta或Ru；所述间隔层的材质包含Mg或O。
在其中一个实施例中，所述磁性层堆叠结构的顶部呈弧形。
在其中一个实施例中，还包括：
隔离层，包覆在所述磁性层叠结构上；
所述隔离层包括第一介质层和第二介质层；
所述第一介质层位于所述屏蔽层和所述第一电极之间；
所述第二介质层位于所述屏蔽层和所述磁性层叠结构之间。
在其中一个实施例中，所述磁性层堆叠结构的横向尺寸大于所述第一电极的横向 尺寸。
在其中一个实施例中，所述屏蔽层包括第一屏蔽层和第二屏蔽层；
所述第一屏蔽层位于所述第一介质层和所述衬底之间，其中所述第一屏蔽层的一个端部位于所述磁性层堆叠结构在所述衬底的投影区域之中；
所述第二屏蔽层位于所述第一介质层的侧壁外表面和所述第二介质层的外表面。
在其中一个实施例中，所述第一屏蔽层和所述第二屏蔽层的材料包括导电性材料和/或导磁性材料；所述第一屏蔽层和所述第二屏蔽层的材质不同。
在其中一个实施例中，所述第二电极的底部与所述磁性层堆叠结构的顶表面、所述屏蔽层的顶表面以及所述隔离层的顶表面在同一水平面上。
综上，提供了一种半导体结构及其制作方法。通过先形成第一屏蔽层，然后再依次形成第一电极、存储结构和第二屏蔽层，所述第一屏蔽层和所述第二屏蔽层形成包覆所述存储结构的屏蔽层，可更好的屏蔽外部电磁场对所述存储结构的干扰，确保信息能够被正确存储以及读写。
附图说明
图1为一实施例提供的一种半导体结构的制作方法流程图；
图2-图11为一实施例提供的半导体结构形成过程中的结构示意图；
图12为一实施例提供的一种半导体结构的结构示意图；
图13为另一实施例提供的一种半导体结构的结构示意图；
图14为又一实施例提供的一种半导体结构的结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解 本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施的限制。
请参见图1，一实施例提供了一种半导体结构的制作方法，包括：
步骤S110，提供衬底100；
步骤S120，在所述衬底100上形成第一屏蔽层200a；
步骤S130，形成贯穿所述第一屏蔽层200a的第一电极400；
步骤S140，在所述第一电极400上形成存储结构500；
步骤S150，在所述存储结构500的顶部和侧壁形成第二屏蔽层200b，所述第一屏蔽层200a和所述第二屏蔽层200b共同构成屏蔽层200；
步骤S160，形成贯穿所述屏蔽层200且与所述存储结构500电连接的第二电极600。
通过先形成第一屏蔽层200a，然后再依次形成第一电极400、存储结构500和第二屏蔽层200b，所述第一屏蔽层200a和所述第二屏蔽层200b形成包覆所述存储结构500的屏蔽层200，可更好的屏蔽外部电磁场对所述存储结构的干扰，确保信息能够被正确存储以及读写。
为了更清楚的描述本技术方案，下面按照制作流程，对每一制作过程进行详细的描述。
本实施例中，执行步骤S110，提供衬底100。提供的所述衬底100可为硅基底、外延硅基底、硅锗基底、碳化硅基底或硅覆绝缘基底，但不以此为限，本领域技术人员熟知的任何用于承载半导体集成电路组成元件的基材均可。所述衬底100可以包含器件结构，如半导体晶体管以及连接所述半导体晶体管的插塞等。
请参见图2，执行步骤S120，在所述衬底100上形成第一屏蔽层200a。
通过沉积工艺在衬底100上沉积屏蔽材料，以形成覆盖所述衬底100表面的第一屏蔽层200a。本实施中，所述沉积工艺包括化学气相沉积(CVD)、物理气相沉积(PVD) 或原子层沉积(ALD)等。所述屏蔽材料可以为导电性良好的材料，如银，铜，金等，可以对电场起到很好的屏蔽作用；所述屏蔽材料也可以为导磁性良好的材料，如包括铁(Fe)、钴(Co)和镍(Ni)的合金，例如钴铁、镍铁和镍钴铁，各种组合的NiFe和Co等其它具有较高磁导率的合金、掺杂的无定形铁磁合金等。需要说明的是，所述导电性良好的材料也可以对磁场起到一定的屏蔽作用，所述导磁性良好的材料也可以对电场起到一定的屏蔽作用。
在其中一个实施例中，请参见图3，在所述第一屏蔽层200a上还形成第一介质层300a。具体的，通过沉积工艺在所述第一屏蔽层200a上沉积介质材料，例如氮化硅、氧化硅、氮氧化硅材料，以形成覆盖所述第一屏蔽层200a的第一介质层300a。所述第一介质层300a可作为图案化所述第一屏蔽层200a的硬掩模，同时也能作为所述第一屏蔽层200a和后续形成的存储结构之间的隔离层的一部分。
请参见图4，执行步骤S130，形成贯穿所述第一屏蔽层200a的第一电极400。具体的，利用光刻以及刻蚀工艺在所述第一屏蔽层200a和所述第一介质层300a中形成第一开口(图中未示出)；在所述第一开口中形成第一电极层，所述第一电极层填满所述沟槽并覆盖所述第一介质层300a，具体的，利用物理气象沉积，化学气相沉积或者电镀等工艺形成所述第一电极层，所述第一电极层为导电材料层，如Al、W、Cu等导电性良好的金属材料层；去除覆盖所述第一介质层300a上表面的所述第一电极层以形成所述第一开口中的所述第一电极400。具体的，可以利用回刻蚀或者化学机械研磨工艺去除覆盖所述第一介质层300a上表面的所述第一电极层以形成所述第一电极400。
在其中一个实施例中，所述第一电极400的顶部与所述第一介质层300a的顶部齐平。可以理解，所述第一电极400的顶部与所述第一介质层300a的顶部齐平时，使得第一屏蔽层200a的底部低于后续形成的存储结构的底部，增大屏蔽范围。
请参见图5a和图5b，执行步骤S140，在所述第一电极400上形成存储结构500。
在其中一个实施例中，所述存储结构500为磁性层堆叠结构。形成所述磁性层堆 叠结构具体包括：如图5a所示，在形成第一电极400的衬底100上依次沉积第一磁层530a、间隔材料层520a和第二磁层510a；然后，如图5b所示，利用光刻以及刻蚀工艺对第一磁层530a、间隔材料层520a和第二磁层510a进行图案化，形成包含固定层530、间隔层520和自由层510的磁性层堆叠结构。具体的，所述第一磁层530a和第二磁层510a的材质包含Co、Fe、B、Ta或Ru；所述间隔材料层520a的材质包含Mg或O。例如，所述固定层530可以为CoFeB，所述间隔层520为MgO层，所述自由层510为CoFeB。
在其中一个实施例中，所述存储结构500的数量、所述第一电极400的数量均为多个，所述第一电极400与所述存储结构500一一对应设置；所述第一电极400在所述衬底100上间隔分布。所述存储结构500之间具有间隔。
在其中一个实施例中，所述磁性层堆叠结构的顶部呈弧形。具体的，采用离子束刻蚀(IBE)工艺对所述第一磁层530a、所述间隔材料层520a和所述第二磁层510a进行刻蚀形成所述磁性层堆叠结构，所述磁性层堆叠结构的自由层510的顶部呈弧形，可以增大相邻所述磁性层堆叠结构顶部之间的距离，减少相邻所述磁性层堆叠结构顶部的接触风险，增大产品良率；同时也有利于后续第三介质层在相邻所述磁性层堆叠结构之间间隔中的填充。
请参见图8，执行步骤S150，在所述存储结构的顶部和侧壁形成第二屏蔽层200b，所述第一屏蔽层200a和所述第二屏蔽层200b共同构成屏蔽层200。具体包括：通过沉积工艺在所述存储结构上沉积屏蔽材料，以形成覆盖所述存储结构的顶部和侧壁的第二屏蔽层200b。所述第二屏蔽层200b与所述第一屏蔽层200a相连，共同构成包覆所述存储结构500的屏蔽层200。所述沉积工艺包括化学气相沉积(CVD)、物理气相沉积(PVD)或原子层沉积(ALD)等。所述屏蔽材料可以为导电性良好的材料，如银，铜，金等，可以对电场起到很好的屏蔽作用；所述屏蔽材料也可以为导磁性良好的材料，如包括铁(Fe)、钴(Co)和镍(Ni)的合金，例如钴铁、镍铁和镍钴铁，各种组合的NiFe 和Co等其它具有较高磁导率的合金、掺杂的无定形铁磁合金等。需要说明的是，所述导电性良好的材料也可以对磁场起到一定的屏蔽作用，所述导磁性良好的材料也可以对电场起到一定的屏蔽作用。
在其中一个实施例中，所述第一屏蔽层200a和所述第二屏蔽层200b的材质不同。例如，所述第一屏蔽层200a和所述第二屏蔽层200b均为导磁性良好的材料，但所述所述第一屏蔽层200a和所述第二屏蔽层200b的材质不同，例如，所述第一屏蔽层200a为钴铁，所述第二屏蔽层200b为镍铁；或者所述第一屏蔽层200a和所述第二屏蔽层200b均为导电性良好的材料，但所述第一屏蔽层200a和所述第二屏蔽层200b的材质不同，例如，所述第一屏蔽层200a为银，所述第二屏蔽层200b为铜；或者所述第一屏蔽层200a为导电性良好的材料，如铜，所述第二屏蔽层200b为导磁性良好的材料，如镍铁。如图9所示，所述第一屏蔽层200a和所述第二屏蔽层200b具有刻蚀选择比，利用所述刻蚀选择比自对准的刻蚀去除所述磁性层堆叠结构侧壁上的所述第二屏蔽层200b下方之外的所述第一屏蔽层200a；所述磁性层堆叠结构侧壁上的所述第二屏蔽层200b下方保留的所述第一屏蔽层200a和所述第二屏蔽层200b形成所述屏蔽层200。此种方法可以减少工艺步骤，节约成本；同时利用自对准的刻蚀，可以防止光刻工艺产生的套刻误差，提高产品良率。
在其中一个实施例中，请参见图6和图7，在所述存储结构的顶部和侧壁形成第二屏蔽层之前，还包括：形成覆盖所述磁性层堆叠结构的顶部和侧壁的第二介质层300b，所述第一介质层300a和所述第二介质层300b共同构成隔离层300。具体包括：利用沉积工艺沉积隔离材料，例如氧化硅、氮化硅或氮氧化硅等，形成覆盖所述第一介质层300a以及所述磁性层堆叠结构的顶部和侧壁的第二介质层300b，然后利用刻蚀工艺去除第一介质层300a上表面的第二介质层300b，形成仅覆盖所述磁性层堆叠结构的顶部和侧壁的第二介质层300b。本实施例中，参见图7，使用相同的材料制作第一介质层300a和第二介质层300b，因此还可以通过一次刻蚀工艺去除相邻磁性层堆叠结构之间 的所述第一介质层300a和所述第二介质层300b，保留所述磁性层堆叠结构顶部和侧壁的所述第一介质层300a和所述第二介质层300b。所述第一介质层300a和所述第二介质层300b共同构成隔离层300。所述隔离层可以缓释所述屏蔽层200的应力以及隔离所述屏蔽层200和所述磁性层堆叠结构。
在其中一个实施例中，所述磁性层堆叠结构的横向尺寸大于所述第一电极的横向尺寸。具体的，如图13所示，所述磁性层堆叠结构在沿所述衬底100表面的方向上的尺寸大于所述第一电极400在沿所述衬底100表面的方向上的尺寸，使得所述衬底100和磁性层堆叠结构之间也形成一部分屏蔽层200，所述形成的屏蔽层200在所述磁性层堆叠结构的底部也起到一定的屏蔽作用，增强屏蔽效果。
请参见图10和图12，执行步骤S160，形成贯穿所述屏蔽层200且与所述存储结构电连接的第二电极600。具体包括：在所述衬底100和所述存储结构上形成第三介质层700；通过光刻以及刻蚀工艺在所述第三介质层700中形成第三开口900，以暴露出所述存储结构500的顶部；最后，利用导电材料填充所述第三开口900，并通过回刻蚀或机械化学研磨工艺去除第三介质层700表面的导电材料，形成所述第二电极600。所述第二电极层可以为Al、W、Cu等导电性良好的金属材料层。
在其中一个实施例中，如图11和图14所示，形成贯穿所述屏蔽层且与所述存储结构电连接的第二电极，包括：所述存储结构为磁性层堆叠结构；所述磁性层堆叠结构的顶部呈弧形；在所述衬底和所述磁性层堆叠结构上形成第三介质层700；利用研磨工艺去除所述磁性层堆叠结构上方的部分屏蔽层以暴露所述磁性层堆叠结构的顶部；在所述磁性层堆叠结构的顶部形成第四介质层800；在所述第四介质层800中形成第二开口(图中未示出)，以暴露出所述磁性层堆叠结构的顶部；于所述第二开口中形成所述第二电极600。利用研磨工艺去除所述磁性层堆叠结构上方的部分屏蔽层以暴露所述磁性层堆叠结构的顶部可以简化制作工艺，同时使得后续形成所述第二开口时，无须对所述屏蔽层以及所述隔离层进行刻蚀，可以减少对所述磁性层堆叠结构的损伤；而 弧形的顶部结构，可以使得利用研磨工艺暴露所述磁性层堆叠结构的顶部时，所述磁性层堆叠结构非暴露区域外部的隔离层和屏蔽层不会被去除，进而增强屏蔽效果。在本实施例中，所述第二电极600的底部与所述磁性层堆叠结构的顶表面、所述屏蔽层200的顶表面以及所述隔离层300的顶表面在同一水平面上。
基于同一发明构思，还提供了一种半导体结构，请参见图12，所述半导体结构包括：衬底100、第一电极400、存储结构500、屏蔽层200和第二电极600。其中第一电极400位于所述衬底100内；存储结构500位于所述第一电极400上；屏蔽层200覆盖所述存储结构500的顶部和侧壁，且所述屏蔽层200的底部低于所述存储结构500的底部；第二电极600，贯穿所述存储结构500顶部的所述屏蔽层200，且与所述存储结构500电连接。
所述屏蔽层200包覆所述存储结构500，可更好的屏蔽外部电磁场对存储结构500的干扰，确保信息能够被正确存储以及读写。所述衬底100可为硅基底、外延硅基底、硅锗基底、碳化硅基底或硅覆绝缘基底，但不以此为限。所述衬底100可以包含器件结构，如半导体晶体管以及连接所述半导体晶体管的插塞等。
在其中一个实施例中，所述存储结构500的数量、所述第一电极400的数量及所述第二电极600的数量均为多个，所述第一电极400及所述第二电极600与所述存储结构500一一对应设置，所述存储结构500之间存在间隔；所述的半导体结构还包括第三介质层700，所述第三介质层700位于所述衬底100上，并填充所述存储结构500之间的间隔，以及用于对相邻的两个所述第二电极600以及相邻的两个屏蔽层200进行隔离。本实施例中，所述第三介质层700可以为氮化硅、氧化硅或氮氧化硅等介质材料形成。
在其中一个实施例中，所述存储结构500为磁性层堆叠结构。所述磁性层堆叠结构至少包括自上到下叠层设置的自由层510、间隔层520和固定层530。具体的，所述自由层510和所述固定层530的材质包含Co、Fe、B、Ta或Ru；所述间隔层的材质包 含Mg或O。例如，所述固定层530可以为CoFeB，所述间隔层为MgO层，所述自由层510为CoFeB。
在其中一个实施例中，还包括隔离层300，所述隔离层300包覆在所述磁性叠层结构上。具体的，所述隔离层300包括第一介质层300a和第二介质层300b；所述第一介质层300a位于所述屏蔽层200和所述第一电极400之间；所述第二介质层300b位于所述屏蔽层200和所述磁性层叠结构之间。
在其中一个实施例中，所述磁性层堆叠结构的顶部呈弧形。如图12所示，所述磁性层堆叠结构的顶部呈弧形，以及包覆在其上的隔离层300以及屏蔽层200的顶部也呈弧形。具体的，所述弧形为向外部凸出的弧形，所述磁性层堆叠结构的自由层510的顶部呈弧形，可以增大相邻所述磁性层堆叠结构顶部之间的距离，减少相邻所述磁性层堆叠结构顶部的接触风险，增大产品良率；同时也有利于第三介质层700在相邻所述磁性层堆叠结构之间间隔中的填充。此外，如图14所示，弧形的顶部结构，可以使得利用研磨工艺暴露所述磁性层堆叠结构的顶部时，所述磁性层堆叠结构非暴露区域外部的隔离层200和屏蔽层300不会被去除，进而增强屏蔽效果。
在其中一个实施例中，所述磁性层堆叠结构的横向尺寸大于所述第一电极的横向尺寸。如图13所示，所述磁性层堆叠结构在沿所述衬底100表面方向上的尺寸大于所述第一电极400在沿所述衬底100表面上的尺寸，使得所述衬底100和磁性层堆叠结构之间也形成一部分屏蔽层200，即在所述磁性层堆叠结构底部也形成部分所述屏蔽层200，所述屏蔽层200在所述磁性层堆叠结构的底部也起到一定的屏蔽作用，增强屏蔽效果。
在其中一个实施例中，如图13所示，所述屏蔽层200包括第一屏蔽层200a和第二屏蔽层200b；所述第一屏蔽层200a位于所述第一介质层300a和所述衬底100之间，其所述第一屏蔽层200a的一个端部位于所述磁性层堆叠结构在所述衬底100的投影区域之中；所第二屏蔽层200b位于所述第一介质层300a的侧壁外表面和所述第二介质 层300b的外表面。所述第一屏蔽层200a和所述第二屏蔽层200b的端部相连，共同形成包覆所述磁性层堆叠结构顶部，侧壁以及部分底部的屏蔽层200。
在其中一个实施例中，所述第一屏蔽层200a和第二屏蔽层200b的材料可以为导电性良好的材料，如银，铜，金等，可以对电场起到很好的屏蔽作用；所述第一屏蔽层200a和第二屏蔽层200b的材料也可以为导磁性良好的材料，如包括铁(Fe)、钴(Co)和镍(Ni)的合金，例如钴铁、镍铁和镍钴铁，各种组合的NiFe和Co等其它具有较高磁导率的合金、掺杂的无定形铁磁合金等。需要说明的是，所述导电性良好的材料也可以对磁场起到一定的屏蔽作用，所述导磁性良好的材料也可以对电场起到一定的屏蔽作用。
在其中一个实施例中，所述第一屏蔽层200a和所述第二屏蔽层200b的材质不同。例如，所述第一屏蔽层200a和所述第二屏蔽层200b均为导磁性良好的材料，但第一屏蔽层200a和所述第二屏蔽层200b的材质不同，例如，所述第一屏蔽层200a为钴铁，所述第二屏蔽层200b为镍铁；或者所述第一屏蔽层200a和所述第二屏蔽层200b均为导电性良好的材料，但所述第一屏蔽层200a和所述第二屏蔽层200b的材质不同，例如，所述第一屏蔽层200a为银，所述第二屏蔽层200b为铜；或者所述第一屏蔽层200a为导电性良好的材料，如铜，所述第二屏蔽层200b为导磁性良好的材料，如镍铁。如图9所示，所述第一屏蔽层200a和所述第二屏蔽层200b具有刻蚀选择比，利用所述刻蚀选择比自对准的刻蚀去除所述第一电极400侧壁之外的所述第一屏蔽层200a；所述第一电极400侧壁上保留的所述第一屏蔽层200a和所述第二屏蔽层200b形成所述屏蔽层200。此种方法可以减少工艺步骤，节约成本；同时利用自对准的刻蚀，可以防止光刻工艺产生的套刻误差，提高产品良率。
在其中一个实施例中，如图14所示，所述第二电极600的底部与所述磁性层堆叠结构的顶表面、所述屏蔽层200的顶表面以及所述隔离层300的顶表面在同一水平面上。具体的，如图11和图14所示，所述存储结构500为磁性层堆叠结构；所述磁性 层堆叠结构的顶部呈弧形；在所述衬底100和所述磁性层堆叠结构上形成第三介质层700；利用研磨工艺去除所述磁性层堆叠结构上方的部分屏蔽层200以暴露所述磁性层堆叠结构的顶部；在所述磁性层堆叠结构的顶部形成第四介质层800；在所述第四介质层800中形成第二开口(图未示)，以暴露出所述磁性层堆叠结构的顶部；于所述第二开口中形成所述第二电极600。利用研磨工艺去除所述磁性层堆叠结构上方的部分屏蔽层200以暴露所述磁性层堆叠结构的顶部可以简化制作工艺，同时使得后续形成所述第二开口时，无须对所述屏蔽层以及所述隔离层进行刻蚀，可以减少对所述磁性层堆叠结构的损伤；而弧形的顶部结构，可以使得利用研磨工艺暴露所述磁性层堆叠结构的顶部时，所述磁性层堆叠结构非暴露区域外部的隔离层300和屏蔽层200不会被去除，进而增强屏蔽效果。在本实施例中，所述第二电极600的底部与所述磁性层堆叠结构的顶表面、所述屏蔽层200的顶表面以及所述隔离层300的顶表面在同一水平面上。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体结构的制作方法，包括：
    提供衬底；
    在所述衬底上形成第一屏蔽层；
    形成贯穿所述第一屏蔽层的第一电极；
    在所述第一电极上形成存储结构；
    在所述存储结构的顶部和侧壁形成第二屏蔽层，所述第一屏蔽层与所述第二屏蔽层共同构成屏蔽层；及
    形成贯穿所述屏蔽层且与所述存储结构电连接的第二电极。
  2. 如权利要求1所述的方法，其特征在于，所述存储结构包括磁性层堆叠结构。
  3. 如权利要求2所述的方法，其特征在于，所述形成贯穿所述第一屏蔽层的第一电极，包括：
    在所述第一屏蔽层上形成第一介质层；
    在所述第一屏蔽层和所述第一介质层中形成第一开口；及
    在所述第一开口中形成所述第一电极。
  4. 如权利要求3所述的方法，其特征在于，所述在所述存储结构的顶部和侧壁形成第二屏蔽层之前，所述方法还包括：
    形成覆盖所述磁性层堆叠结构的顶部和侧壁的第二介质层，所述第一介质层和所述第二介质层共同构成隔离层。
  5. 如权利要求4所述的方法，其特征在于，所述第一屏蔽层和所述第二屏蔽层的材料包括导电性材料和/或导磁性材料。
  6. 如权利要求5所述的方法，其特征在于，所述第一屏蔽层和所述第二 屏蔽层的材质不同；
    利用自对准刻蚀工艺去除所述磁性层堆叠结构侧壁上的所述第二屏蔽层下方之外的所述第一屏蔽层；
    所述磁性层堆叠结构侧壁上的所述第二屏蔽层下方保留的所述第一屏蔽层和所述第二屏蔽层形成所述屏蔽层。
  7. 如权利要求6所述的方法，其特征在于，所述屏蔽层的底部低于所述磁性层堆叠结构的底部。
  8. 如权利要求4所述的方法，其特征在于，所述磁性层堆叠结构的顶部呈弧形。
  9. 如权利要求4所述的方法，其特征在于，所述磁性层堆叠结构的横向尺寸大于所述第一电极的横向尺寸。
  10. 如权利要求8所述的作方法，其特征在于，所述形成贯穿所述屏蔽层且与所述存储结构电连接的第二电极，包括：
    在所述衬底和所述屏蔽层上形成第三介质层；
    利用研磨工艺去除所述磁性层堆叠结构上方的部分屏蔽层以暴露所述磁性层堆叠结构的顶部；
    在所述磁性层堆叠结构的顶部形成第四介质层；
    在所述第四介质层中形成第二开口，以暴露出所述磁性层堆叠结构的顶部；及
    于所述第二开口中形成所述第二电极。
  11. 一种半导体结构，包括：
    衬底；
    第一电极，位于所述衬底内；
    存储结构，位于所述第一电极上；
    屏蔽层，覆盖所述存储结构的顶部和侧壁，且所述屏蔽层的底部低于所述存储结构的底部；以及
    第二电极，贯穿所述存储结构顶部的所述屏蔽层且与所述存储结构电连接。
  12. 如权利要求11所述的半导体结构，其特征在于，所述存储结构包括磁性层堆叠结构。
  13. 如权利要求12所述的半导体结构，其特征在于，所述磁性层堆叠结构包括固定层、间隔层和自由层。
  14. 如权利要求13所述的半导体结构，其特征在于，所述固定层和所述自由层的材质包含Co、Fe、B、Ta或Ru；所述间隔层的材质包含Mg或O。
  15. 如权利要求12所述的半导体结构，其特征在于，所述磁性层堆叠结构的顶部呈弧形。
  16. 如权利要求12所述的半导体结构，其特征在于，还包括：
    隔离层，包覆在所述磁性层叠结构上；
    所述隔离层包括第一介质层和第二介质层，所述第一介质层位于所述屏蔽层和所述第一电极之间，所述第二介质层位于所述屏蔽层和所述磁性层叠结构之间。
  17. 如权利要求16所述的半导体结构，其特征在于，所述磁性层堆叠结构的横向尺寸大于所述第一电极的横向尺寸。
  18. 如权利要求17所述的半导体结构，其特征在于，所述屏蔽层包括第一屏蔽层和第二屏蔽层；
    所述第一屏蔽层位于所述第一介质层和所述衬底之间，其中所述第一屏 蔽层的一个端部位于所述磁性层堆叠结构在所述衬底的投影区域之中；
    所述第二屏蔽层位于所述第一介质层的侧壁外表面和所述第二介质层的外表面。
  19. 如权利要求18所述的半导体结构，其特征在于，所述第一屏蔽层和所述第二屏蔽层的材料包括导电性材料和/或导磁性材料；所述第一屏蔽层和所述第二屏蔽层的材质不同。
  20. 如权利要求16所述的半导体结构，其特征在于，所述第二电极的底部与所述磁性层堆叠结构的顶表面、所述屏蔽层的顶表面以及所述隔离层的顶表面在同一水平面上。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103443860A (zh) * 2011-02-14 2013-12-11 高通股份有限公司 将屏蔽集成到用于磁阻随机存取存储器的磁隧道结装置中的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW569442B (en) * 2001-12-18 2004-01-01 Toshiba Corp Magnetic memory device having magnetic shield layer, and manufacturing method thereof
US20040061987A1 (en) * 2002-09-27 2004-04-01 International Business Machines Corporation Self-stabilized giant magnetoresistive spin valve read sensor
JP2005223102A (ja) * 2004-02-04 2005-08-18 Nec Corp 不揮発性記憶装置及びその製造方法
JP5702177B2 (ja) * 2011-02-04 2015-04-15 ルネサスエレクトロニクス株式会社 半導体装置
US8541767B2 (en) * 2011-04-25 2013-09-24 National University Of Singapore Memory component having an electrical contact free of a metal layer
US9564403B2 (en) * 2013-09-27 2017-02-07 Infineon Technologies Ag Magnetic shielding of perpendicular STT-MRAM
US9230576B1 (en) * 2014-09-08 2016-01-05 HGST Netherlands B.V. Scissor reader with side shield decoupled from bias material
US9875971B2 (en) * 2015-03-26 2018-01-23 Globalfoundries Singapore Pte. Ltd. Magnetic shielding of MRAM package
US10096768B2 (en) * 2015-05-26 2018-10-09 Globalfoundries Singapore Pte. Ltd. Magnetic shielding for MTJ device or bit
KR102355296B1 (ko) * 2017-08-08 2022-01-25 삼성전자주식회사 반도체 메모리 장치 및 이의 제조를 위한 반도체 메모리 제조 장치
US10439129B2 (en) * 2018-01-18 2019-10-08 Globalfoundries Inc. Shielded MRAM cell

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103443860A (zh) * 2011-02-14 2013-12-11 高通股份有限公司 将屏蔽集成到用于磁阻随机存取存储器的磁隧道结装置中的方法

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