WO2021203699A1 - 变频器 igbt 驱动控制方法和控制装置 - Google Patents

变频器 igbt 驱动控制方法和控制装置 Download PDF

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Publication number
WO2021203699A1
WO2021203699A1 PCT/CN2020/128972 CN2020128972W WO2021203699A1 WO 2021203699 A1 WO2021203699 A1 WO 2021203699A1 CN 2020128972 W CN2020128972 W CN 2020128972W WO 2021203699 A1 WO2021203699 A1 WO 2021203699A1
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Prior art keywords
level signal
flag bit
signal
processor
trigger
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PCT/CN2020/128972
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English (en)
French (fr)
Inventor
宋承林
张鸿波
刘锡安
刘坤
韩宁
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青岛中加特电气股份有限公司
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Priority to AU2020441878A priority Critical patent/AU2020441878B2/en
Publication of WO2021203699A1 publication Critical patent/WO2021203699A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques

Definitions

  • the invention belongs to the technical field of power electronics, and in particular relates to an inverter IGBT drive control method and an inverter IGBT drive control device.
  • the single-channel plug-and-play driver 1SP0335 produced and sold by Power Integrations can safely and reliably drive parallel high-voltage, high-power IGBT modules.
  • the driving logic of this kind of driver during normal operation is to return a 700ns high-level pulse signal after receiving the trigger signal, and return a 700ns high-level pulse signal after receiving the turn-off signal to represent the normal operation of the driver. In the process of triggering, if a fault occurs, a 9 ⁇ s high-level signal will be fed back.
  • the IGBT module If the IGBT module is used to drive an inductive load, such as a motor, it needs to collect the clock signals of six IGBTs, which puts forward very high requirements for the selection of an external crystal oscillator.
  • the driver since the driver may also be integrated with the DC voltage detection module, output voltage detection module, and current detection module on the same PCB circuit board, the external crystal oscillator will introduce high-frequency signals, which can easily cause EMC to exceed the standard and affect the detection accuracy.
  • An inverter IGBT drive control method comprising the following steps: a first processor determines whether to generate a trigger level signal according to the working state of the inverter; if the trigger level signal is generated, the first processor receives the output of the drive circuit Feedback signal and determine whether there is an output pulse in the feedback signal; if there is an output pulse in the feedback signal, and the current feedback signal has the same level state as the trigger level signal, the first processor sends The second processor outputs a driving abnormal level signal; if there is an output pulse in the feedback signal, and the current feedback signal is opposite to the level state of the trigger level signal, the first processor sends the signal to the second processor The output drives the normal level signal.
  • the first processor determines that the trigger level signal is not generated according to the working state of the inverter, the first processor outputs a system holding level signal to the second processor; wherein , The system keeps the level signal at the same level as the drive abnormal level signal.
  • the abnormal drive level signal is a high level signal
  • the drive normal level signal is a low level signal
  • the system maintain level signal is a high level signal
  • the drive abnormal level signal is a low level signal
  • the drive normal level signal is a high level signal
  • the system maintain level signal is Low-level signal
  • the method further includes the following steps: configuring a first flag bit, a second flag bit, a third flag bit, and a fourth flag bit in the first processor; A flag bit, a second flag bit, a third flag bit, and a fourth flag bit are configured as 0; if the first processor determines that the trigger level signal is not generated according to the working state of the inverter, then the first The flag bit and the second flag bit are configured as 0; if the first processor determines that the trigger level signal is generated according to the working state of the inverter and the first processor receives the feedback signal output by the drive circuit, it will The first flag bit and the second flag bit are configured as 1; if the first processor determines that there is an output pulse in the feedback signal, the third flag bit is configured to follow the trigger level signal; if When the trigger level signal is generated, the third flag bit is configured as 1; it is determined whether the first flag bit, the second flag bit, and the third flag bit are all configured as 1; if
  • the first processor is a CPLD controller.
  • an inverter IGBT drive control device including: a trigger level signal generation module, the trigger level signal generation module is used to determine whether to generate a trigger level signal according to the working state of the inverter; A judgment module, the first judgment module is used to receive the feedback signal output by the driving circuit and judge whether there is an output pulse in the feedback signal when the trigger level signal is generated; the second judgment module, the The second judgment module is used for judging whether the current feedback signal and the level state of the trigger level signal are the same when the output pulse is present in the feedback signal; and a signal output module, the signal output module is used for When the second judgment module judges that the current feedback signal and the trigger level signal have the same level state, it is configured to output a drive abnormal level signal to the external processor; and is used to judge the current feedback in the second judgment module When the level state of the signal is opposite to the trigger level signal, the configuration is configured to output a driving normal level signal to the external processor.
  • the signal output module is further configured to output a system holding level signal to an external processor without generating the trigger level signal; wherein, the system holding level signal is related to the drive abnormality The level state of the level signal is the same.
  • the abnormal drive level signal is a high level signal
  • the drive normal level signal is a low level signal
  • the system maintain level signal is a high level signal
  • the abnormal drive level signal is a low level signal
  • the drive normal level signal is a high level signal
  • the system maintain level signal is a low level signal
  • the inverter system is adapted to a variety of driving circuits.
  • Fig. 1 is a flowchart of the first specific embodiment of the inverter IGBT drive control method disclosed in the present invention
  • FIG. 2 is a flowchart of a second specific embodiment of the inverter IGBT drive control method disclosed in the present invention
  • FIG. 3 is a flowchart of a third specific embodiment of the inverter IGBT drive control method disclosed in the present invention.
  • Figure 4 is a system architecture diagram of the inverter IGBT drive system
  • Fig. 5 is a schematic block diagram of the structure of the inverter IGBT drive control device disclosed in the present invention.
  • FIG. 1 In order to play the role of early warning and protection, while avoiding the introduction of external crystal oscillators, so that the system can be matched with multiple types of drive circuits, a newly designed inverter IGBT drive control method is shown in Figure 1.
  • Figure 4 To introduce the basic hardware architecture of the inverter control system.
  • the PWM signal generated by the DSP is output to the IGBT inverter unit to control Its on-off state and further control the operating state of the load.
  • the PWM signal generated by the DSP can be transmitted in serial mode or in parallel mode. It is preferable to use optical fiber as the transmission medium to meet the long-distance signal transmission requirements of the high-power frequency converter.
  • the normal operation and protection of the IGBT inverter unit are realized by the drive circuit.
  • the drive circuit of the IGBT inverter unit may use drive circuit integrated chips produced and sold by multiple companies.
  • the model of the drive circuit integrated chip includes but is not limited to Power The single-channel plug-and-play driver 1SP0335 ⁇ 1SP 0635 produced and sold by Integrations.
  • the driving circuit and the first processor communicate in two directions to upload the working status of the IGBT inverter unit.
  • the first processor is preferably implemented by a CPLD controller.
  • the CPLD controller Facing the load of the IGBT inverter unit circuit, the CPLD controller has more stable performance and faster signal transmission speed, and can flexibly realize a variety of functions.
  • the transmission medium of the CPLD controller is also preferably optical fiber to meet the long-distance signal transmission requirements of the high-power frequency converter.
  • control methods are used to automatically monitor the working status of the IGBT inverter unit. Specifically, it includes the following steps:
  • the first processor judges whether to generate a trigger level signal according to the working state of the frequency converter. When the inverter is in the working state, the first processor generates a trigger level signal to ensure the normal operation of the entire inverter system. When the inverter is in the standby state, the first processor interrupts the generation of the trigger level signal.
  • the trigger level signal is preferably set to a high level signal.
  • the first processor determines whether there is an output pulse in the feedback signal.
  • the output pulse includes at least one falling edge of the signal, that is, when the feedback signal includes a complete combination of a high-level signal, a falling edge, and a low-level signal, the first processor determines that there is an output pulse in the feedback signal , The communication between the first processor and the drive circuit is normal.
  • the first processor further judges whether the current feedback signal and the level state of the trigger level signal are the same. If the current feedback signal and the trigger level signal have the same level state, it indicates that the switching behavior of the IGBT inverter unit controlled by the driving circuit is abnormal, and the first processor outputs a driving abnormal level signal to the second processor.
  • the second processor can be the host computer of the CPLD controller, or other integrated chips with data processing capabilities and independent multi-channel I/O interfaces.
  • the model of the second processor will not be further described here. limited.
  • the inverter system is adapted to a variety of driving circuits.
  • the first processor judges not to generate a trigger level signal according to the working state of the inverter, and the first processor further outputs a system holding level signal to the second processor.
  • the system maintains the same level state of the level signal and the level state of the drive abnormal level signal.
  • the driving abnormal level signal as a high level signal
  • the driving normal level signal as a low level signal
  • the system maintaining level signal as a high level signal
  • the driving abnormal level signal as a low level signal
  • driving the normal level signal as a high level signal
  • the system maintaining level signal as a low level signal
  • the system can determine which output signal is generated through the first flag bit, the second flag bit, and the third flag bit, and whether the current IGBT inverter unit is in a normal working state.
  • the external processor can also obtain the working status of the system through the fourth flag bit. When the fourth flag bit is set to 1, it can quickly intervene in the system, and the response speed of the system can be quickly improved.
  • FIG. 5 Another aspect of the present invention provides an inverter IGBT drive control device, as shown at 10 in FIG. 5, which includes the following modules:
  • Trigger level signal generation module 10 Trigger level signal generation module 10; trigger level signal generation module 10 is used to determine whether to generate a trigger level signal according to the working state of the inverter: when the inverter is in working state, the trigger level signal generation module 10 is configured to control to The external output trigger level signal; when the inverter is in the standby state, the trigger level signal generation module 10 is configured to interrupt the generation of the trigger level signal.
  • the trigger level signal is a high level signal.
  • the first judging module 12 is used for receiving the feedback signal output by the driving circuit and judging whether there is an output pulse in the feedback signal when the trigger level signal is generated.
  • the output pulse includes the falling edge of at least one signal, that is, when the feedback signal includes a complete combination of a high-level signal, a falling edge, and a low-level signal, the first determining module 12 is configured to determine that there is an output pulse in the feedback signal.
  • the second judging module 13 is used to judge whether the current feedback signal and the trigger level signal are the same in the state of the output pulse in the feedback signal; if the current feedback signal is equal to the trigger level signal If the level state is the same, it means that the switching behavior of the IGBT inverter unit controlled by the drive circuit is abnormal; if the current feedback signal is opposite to the level state of the trigger level signal, it means that the switching behavior of the IGBT inverter unit controlled by the drive circuit is normal.
  • the signal output module 14 is used to configure the external processor to output a driving abnormal level signal when the second judgment module 13 judges that the current feedback signal is the same as the trigger level signal;
  • the second judgment module 13 judges that the level state of the current feedback signal and the trigger level signal are opposite, it is configured to output a driving normal level signal to the external processor.
  • the drive circuit with feedback pulse or square wave signal can be matched with the above-mentioned protection control device, no external crystal oscillator is required, the matching degree of the control device is higher, and the use is more flexible.
  • the signal output module is also used to configure to output a system holding level signal to the external processor without generating a trigger level signal; wherein the level state of the system holding level signal is the same as that of the driving abnormal level signal. In order to realize the normal operation of the system in the standby state.
  • the driving abnormal level signal it is preferable to set the driving abnormal level signal as a high level signal, the driving normal level signal as a low level signal, and the system maintaining level signal as a high level signal.
  • the driving abnormal level signal it is also possible to set the driving abnormal level signal as a low level signal, the driving normal level signal as a high level signal, and the system maintaining level signal as a low level signal.
  • the embodiment of the present application also provides a computer storage medium, wherein the computer storage medium is stored in a computer program for electronic data exchange, and the computer program causes the frequency converter to execute part or all of the steps of any method recorded in the above method embodiment.
  • the disclosed device may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the above-mentioned units or modules is only a logical function division.
  • there may be other division methods for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one physical space, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Control Of High-Frequency Heating Circuits (AREA)
  • Control Of Electric Motors In General (AREA)
  • Control Of Direct Current Motors (AREA)

Abstract

一种变频器IGBT驱动控制方法和控制装置，方法包括以下步骤：第一处理器根据变频器工作状态判断是否生成触发电平信号(S1)；如果生成触发电平信号，第一处理器接收驱动电路输出的反馈信号，并判断反馈信号中是否存在输出脉冲(S2)；如果反馈信号中存在输出脉冲，且当前反馈信号与触发电平信号的电平状态相同，则第一处理器向第二处理器输出驱动异常电平信号(S31)；如果反馈信号中存在输出脉冲，且当前反馈信号与触发电平信号的电平状态相反，第一处理器向第二处理器输出驱动正常电平信号(S32)。采用本方法可以在不设置外部晶体振荡器的前提下起到对IGBT逆变单元的保护作用，只要驱动电路可以反馈脉冲信号即可以完成整个逻辑控制，变频器***适配多种驱动电路。

Description

变频器IGBT驱动控制方法和控制装置 技术领域
本发明属于电力电子技术领域，尤其涉及一种变频器IGBT驱动控制方法以及一种变频器IGBT驱动控制装置。
 背景技术
近年来，以逆变电路为核心的变频技术不断提高，发展迅速。大功率变频技术应用日益增长。大功率变频器通常选用大功率IGBT作为逆变电路的主开关器件，其通断状态变化由以单片机为核心的主控电路通过驱动电路实现。
针对其中所选用的驱动电路，目前市面上有多种驱动器可供选择。如Power Integrations公司生产并销售的单通道即插即用型驱动器1SP0335，这种驱动器能够安全可靠地驱动并联的高压、大功率IGBT模块。这种驱动器正常工作时的驱动逻辑为在接收到触发信号后返回一个700ns的高电平脉冲信号，在接收到关断信号后返回一个700ns的高电平脉冲信号，以代表驱动器正常工作。在触发工作过程中，如果发生故障，则会反馈一个9μs的高电平信号。为采集到驱动器反馈的时序信号，正常情况下需要为CPLD配置高精度高处理性能的外部晶振进行捕捉。
 技术问题
如果IGBT模块用于驱动感性负载，如电机等，则需要采集六路IGBT的时钟信号，对外部晶振的选配提出了非常高的要求。此外，由于驱动器还可能与直流电压检测模块、输出电压检测模块、电流检测模块集成在同一个PCB电路板上，外部晶振会引入高频信号，很容易导致EMC超标，影响检测精度。
 技术解决方案
本发明针对现有技术中变频器IGBT驱动控制时需要外部晶体振荡器辅助，芯片匹配度低且容易引入高频信号，导致EMC超标的问题，设计并提出一种无需晶体振荡器的变频器IGBT驱动控制方法。
一种变频器IGBT驱动控制方法，包括以下步骤：第一处理器根据变频器工作状态判断是否生成触发电平信号；如果生成所述触发电平信号，所述第一处理器接收驱动电路输出的反馈信号，并判断所述反馈信号中是否存在输出脉冲；如果所述反馈信号中存在输出脉冲，且当前反馈信号与所述触发电平信号的电平状态相同，则所述第一处理器向第二处理器输出驱动异常电平信号；如果所述反馈信号中存在输出脉冲，且当前反馈信号与所述触发电平信号的电平状态相反，则所述第一处理器向第二处理器输出驱动正常电平信号。
为保证待机状态下的正常工作逻辑，如果所述第一处理器根据变频器工作状态判断不生成触发电平信号，则所述第一处理器向第二处理器输出***保持电平信号；其中，所述***保持电平信号与所述驱动异常电平信号的电平状态相同。
优选的，所述驱动异常电平信号为高电平信号，所述驱动正常电平信号为低电平信号，所述***保持电平信号为高电平信号。
作为另一种可选方案，以适配不同的处理器，所述驱动异常电平信号为低电平信号，所述驱动正常电平信号为高电平信号，所述***保持电平信号为低电平信号。
为提高***的处理速度和能力，还包括以下步骤：在所述第一处理器中配置第一标志位、第二标志位、第三标志位和第四标志位；初始状态下，所述第一标志位、第二标志位、第三标志位和第四标志位配置为0；如果所述第一处理器根据变频器工作状态判断不生成所述触发电平信号，则保持所述第一标志位和第二标志位配置为0；如果所述第一处理器根据变频器工作状态判断生成所述触发电平信号且所述第一处理器接收到驱动电路输出的反馈信号，则将所述第一标志位和第二标志位配置为1；如果所述第一处理器判断所述反馈信号中存在输出脉冲，则将所述第三标志位配置为跟随所述触发电平信号；如果生成所述触发电平信号，则将所述第三标志位配置为1；判断所述第一标志位、第二标志位和第三标志位是否均配置为1；如果所述第一标志位、第二标志位和第三标志位均配置为1，则将所述第四标志位配置为1，所述第一处理器向第二处理器输出驱动异常电平信号；如果所述第一标志位、第二标志位和第三标志位不均配置为1，则保持将第四标志位配置为0，如果第一标志位和第二标志位均配置为0，所述第一处理器向第二处理器输出***保持电平信号；如果第一标志位和第二标志位均配置为1，所述第一处理器向第二处理器输出驱动正常电平信号。
优选的，所述第一处理器为CPLD控制器。
本发明的另一个方面提供了一种变频器IGBT驱动控制装置，包括：触发电平信号生成模块，所述触发电平信号生成模块用于根据变频器工作状态判断是否生成触发电平信号；第一判断模块，所述第一判断模块用于在生成所述触发电平信号的状态下，接收驱动电路输出的反馈信号并判断所述反馈信号中是否存在输出脉冲；第二判断模块，所述第二判断模块用于在所述反馈信号中存在所述输出脉冲的状态下判断当前反馈信号与所述触发电平信号的电平状态是否相同；和信号输出模块，所述信号输出模块用于在所述第二判断模块判断当前反馈信号与所述触发电平信号的电平状态相同时，配置向外部处理器输出驱动异常电平信号；且用于在所述第二判断模块判断当前反馈信号与所述触发电平信号的电平状态相反时，配置向外部处理器输出驱动正常电平信号。
进一步的，所述信号输出模块还用于在不生成所述触发电平信号的状态下，配置向外部处理器输出***保持电平信号；其中，所述***保持电平信号与所述驱动异常电平信号的电平状态相同。
优选的，所述驱动异常电平信号为高电平信号，所述驱动正常电平信号为低电平信号，所述***保持电平信号为高电平信号。
作为另一种备选方案，所述驱动异常电平信号为低电平信号，所述驱动正常电平信号为高电平信号，所述***保持电平信号为低电平信号。
 有益效果
通过根据变频器的工作状态生成并输出触发电平信号、并对驱动电路反馈信号中的输出脉冲，以及当前反馈信号与触发电平信号电平状态的采样和监控，可以在不设置外部晶体振荡器的前提下起到对IGBT逆变单元的保护作用，采用此种方法，只要驱动电路可以反馈脉冲信号即可以完成整个逻辑控制，因此，变频器***适配多种驱动电路。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1 为本发明所公开的变频器IGBT驱动控制方法第一种具体实施例的流程图；
图2为本发明所公开的变频器IGBT驱动控制方法第二种具体实施例的流程图；
图3为本发明所公开的变频器IGBT驱动控制方法第三种具体实施例的流程图；
图4为变频器IGBT驱动***的***架构图；
图5为本发明所公开的变频器IGBT驱动控制装置的结构示意框图。
 本发明的最佳实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下将结合附图和实施例，对本发明作进一步详细说明。
本发明的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们的任何变形，代表覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本发明中“实施例”代表结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中，各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员可以理解，本文所描述的实施例可以与其它实施例相结合。
为起到预警和保护作用，同时避免引入外部晶体振荡器，使得***可以与多种型号的驱动电路匹配，一种全新设计的变频器IGBT驱动控制方法如图1所示。首先参照图4所示对变频器控制***的基硬件本架构进行介绍，从整体上说，在变频器（变频调速***）中，DSP产生的PWM信号输出至IGBT逆变单元中，以控制其通断状态并进一步控制负载的运行状态。DSP产生的PWM信号既可以采用串行方式进行传输，也可以采用并行方式进行传输。优选采用光纤作为传输介质，以满足大功率变频器长距离信号传递的要求。IGBT逆变单元的正常工作和保护由驱动电路实现。在本实施例中，IGBT逆变单元的驱动电路可以采用多个公司生产并销售的驱动电路集成芯片，驱动电路集成芯片的型号包括但不限于Power Integrations公司生产并销售的单通道即插即用型驱动器1SP0335\1SP 0635。驱动电路和第一处理器双向通信以上传IGBT逆变单元的工作状态。考虑到***潜在的信号通路扩展需求和DSP有限输出端口之间不匹配的问题，在本发明中，第一处理器优选通过CPLD控制器实现。面对负载的IGBT逆变单元电路，CPLD控制器具有更稳定的性能的更快的信号传输速度，可以灵活的实现多种功能。CPLD控制器的传输介质同样优选采用光纤，以满足大功率变频器长距离信号传递的要求。
在不配置外部晶振的情况下，通过以下控制方法起到对IGBT逆变单元工作状态的自动监控。具体来说，包括以下步骤：
S1，第一处理器根据变频器工作状态判断是否生成触发电平信号。当变频器处于工作状态时，第一处理器即生成触发电平信号，以保证整个变频器***的正常工作。当变频器处于待机状态时，第一处理器即中断生成触发电平信号。通常来说，触发电平信号优选设定为高电平信号。
S2, 如果变频器处于正常工作状态，则生成触发电平信号，第一处理器即开始接收IGBT逆变单元驱动电路输出的反馈信号。特别设计的，第一处理器判断反馈信号中是否存在输出脉冲。需要进一步说明的时，输出脉冲包括至少一个信号的下降沿，即在反馈信号中包括高电平信号、下降沿和低电平信号的完整组合时，第一处理器判断反馈信号中存在输出脉冲，第一处理器和驱动电路之间的通信正常。
S31,如果反馈信号中存在输出脉冲，则第一处理器进一步判断当前反馈信号与触发电平信号的电平状态是否相同。如果当前反馈信号与触发电平信号的电平状态相同，说明通过驱动电路控制的IGBT逆变单元的开关行为出现异常，第一处理器向第二处理器输出驱动异常电平信号。
S32，如果反馈信号中存在输出脉冲，但第一处理器进一步判断当前反馈信号与触发电平信号的电平状态相反，说明通过驱动电路控制IGBT逆变单元的开关行为正常，第一处理器向第二处理器输出驱动正常电平信号。
其中，第二处理器可以是CPLD控制器的上位机，也可以是其它的具有数据处理能力，且具有独立的多路I/O接口的集成芯片，在此不对第二处理器的型号进行进一步限定。
通过根据变频器的工作状态生成并输出触发电平信号、并对驱动电路反馈信号中的输出脉冲，以及当前反馈信号与触发电平信号电平状态的采样和监控，可以在不设置外部晶体振荡器的前提下起到对IGBT逆变单元的保护作用，同时，只要驱动电路可以反馈脉冲信号即可以完成整个逻辑控制，因此，变频器***适配多种驱动电路。
如图2所示，在变频器待机时，如步骤S22, 第一处理器根据变频器工作状态判断不生成触发电平信号，第一处理器进一步向第二处理器输出***保持电平信号。***保持电平信号与驱动异常电平信号的电平状态相同。
在本发明中，优选设计驱动异常电平信号为高电平信号，驱动正常电平信号为低电平信号，***保持电平信号为高电平信号。
作为另一种备选方案，还可以设计驱动异常电平信号为低电平信号，驱动正常电平信号为高电平信号，***保持电平信号为低电平信号。
以驱动异常电平信号为高电平信号，驱动正常电平信号为低电平信号，***保持电平信号为高电平信号为例，结合图3对以CPLD控制器作为第一处理器的***的具体控制方法进行介绍。
S10,在第一处理器中配置第一标志位、第二标志位、第三标志位和第四标志位。初始状态下，第一标志位、第二标志位、第三标志位和第四标志位都默认配置为0。
S11,如果第一处理器根据变频器工作状态判断不生成触发电平信号，则保持第一标志位和第二标志位配置为0，以为下一步判定提供标识。
S12,如果第一处理器根据变频器工作状态判断生成触发电平信号，同时第一处理器接收到驱动电路输出的反馈信号，则将第一标志位和第二标志位配置为1，以为下一步判定提供标识。
S13,如果第一处理器判断反馈信号中存在输出脉冲，则将第三标志位配置为跟随触发电平信号。也就是说。如果当前状态下根据变频器的工作状态生成触发电平信号，则将第三标志位配置为1，如果当前状态下根据变频器的工作状态不生成触发电平信号，则第三标志位保持配置为0。
S14,进一步根据第一标志位、第二标志位和第三标志位判断生成何种输出信号。具体来说，判断第一标志位、第二标志位和第三标志位是否均配置为1.
S15,如果第一标志位、第二标志位和第三标志位均配置为1，则将第四标志位配置为1，第一处理器向第二处理器输出驱动异常电平信号。同时，外部处理器还可以通过直接调用第四标志位获取当前***的工作状态，即使预警或者干预。
S16，如果所述第一标志位、第二标志位和第三标志位不均配置为1，则保持将第四标志位配置为0。
S17，如果第一标志位和第二标志位均配置为0，第一处理器向第二处理器输出***保持电平信号；S18,如果第一标志位和第二标志位均配置为1，第一处理器向第二处理器输出驱动正常电平信号。
通过此种优选的数据处理方式，***可以通过第一标志位、第二标志位和第三标志位判断生成何种输出信号，以及当前IGBT逆变单元是否处于正常的工作状态。外部处理器还可以通过第四标志位获取***的工作状态，当第四标志位置1时，迅速对***进行干预，***响应速度得以快速提升。
本发明的另一个方面提供一种变频器IGBT驱动控制装置，如图5中10所示，其包括以下几个模块：
触发电平信号生成模块10；触发电平信号生成模块10用于根据变频器工作状态判断是否生成触发电平信号：当变频器处于工作状态时，触发电平信号生成模块10配置为控制以向外输出触发电平信号；当变频器处于待机状态时，触发电平信号生成模块10配置为中断生成触发电平信号。优选的，触发电平信号为高电平信号。
第一判断模块12；第一判断模块12用于在生成触发电平信号的状态下，接收驱动电路输出的反馈信号并判断反馈信号中是否存在输出脉冲。输出脉冲包括至少一个信号的下降沿、即反馈信号中包括高电平信号、下降沿和低电平信号的完整组合时，第一判断模块12配置为判定反馈信号中存在输出脉冲。
第二判断模块13；第二判断模块13用于在反馈信号中存在输出脉冲的状态下判断当前反馈信号与触发电平信号的电平状态是否相同；如果当前反馈信号与触发电平信号的电平状态相同，说明通过驱动电路控制的IGBT逆变单元的开关行为出现异常；如果当前反馈信号与触发电平信号的电平状态相反，说明通过驱动电路控制IGBT逆变单元的开关行为正常。
信号输出模块14；信号输出模块14用于在第二判断模块13判断当前反馈信号与触发电平信号的电平状态相同时，配置向外部处理器输出驱动异常电平信号；且用于在第二判断模块13判断当前反馈信号与触发电平信号的电平状态相反时，配置向外部处理器输出驱动正常电平信号。
通过上述多个模块的协同控制，即可以实现根据变频器的工作状态生成并输出触发电平信号，对驱动电路反馈信号中输出脉冲，以及当前反馈信号与触发电平状态的采样和监控，任何具备反馈脉冲或方波信号的驱动电路均可以与上述保护控制装置匹配，无需设置外部晶体振荡器，控制装置的匹配度更高，使用更为灵活。
信号输出模块还用于在不生成触发电平信号的状态下，配置向外部处理器输出***保持电平信号；其中，***保持电平信号与驱动异常电平信号的电平状态相同。以实现待机状态下***的正常运行。
在本实施例中，优选设定驱动异常电平信号为高电平信号，驱动正常电平信号为低电平信号，***保持电平信号为高电平信号。作为另一组备选方案，也可以设定驱动异常电平信号为低电平信号，驱动正常电平信号为高电平信号，***保持电平信号为低电平信号。
本申请实施例还提供一种计算机存储介质，其中，该计算机存储介质存储于电子数据交换的计算机程序，该计算机程序使得变频器执行如上方法实施例中记载的任一方法的部分或全部步骤。
在上述实施例中，对各个实施例的描述均各有侧重，某个实施例中没有详述的部分，可以参见其它实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元或模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个物理空间，或者也可以分布到多个网络单元上，可以根据实际需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上实施例仅用以说明本发明的技术方案，而非对其进行限制；尽管参照前述实施例对本发明进行了详细的说明，对于本领域的普通技术人员来说，依然可以对前述实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或替换，并不使相应技术方案的本质脱离本发明所要求保护的技术方案的精神和范围。
 

Claims (10)

  1. 一种变频器IGBT驱动控制方法，其特征在于，包括以下步骤：
    第一处理器根据变频器工作状态判断是否生成触发电平信号；
    如果生成所述触发电平信号，所述第一处理器接收驱动电路输出的反馈信号，并判断所述反馈信号中是否存在输出脉冲；
    如果所述反馈信号中存在输出脉冲，且当前反馈信号与所述触发电平信号的电平状态相同，则所述第一处理器向第二处理器输出驱动异常电平信号；如果所述反馈信号中存在输出脉冲，且当前反馈信号与所述触发电平信号的电平状态相反，则所述第一处理器向第二处理器输出驱动正常电平信号。
  2. 根据权利要求1所述的变频器IGBT驱动控制方法，其特征在于：
    如果所述第一处理器根据变频器工作状态判断不生成触发电平信号，则所述第一处理器向第二处理器输出***保持电平信号；其中，所述***保持电平信号与所述驱动异常电平信号的电平状态相同。
  3. 根据权利要求2所述的变频器IGBT驱动控制方法，其特征在于：
    所述驱动异常电平信号为高电平信号，所述驱动正常电平信号为低电平信号，所述***保持电平信号为高电平信号。
  4. 根据权利要求2所述的变频器IGBT驱动控制方法，其特征在于：
    所述驱动异常电平信号为低电平信号，所述驱动正常电平信号为高电平信号，所述***保持电平信号为低电平信号。
  5. 根据权利要求3所述的变频器IGBT驱动控制方法，其特征在于：
    还包括以下步骤：
    在所述第一处理器中配置第一标志位、第二标志位、第三标志位和第四标志位；初始状态下，所述第一标志位、第二标志位、第三标志位和第四标志位配置为0；
    如果所述第一处理器根据变频器工作状态判断不生成所述触发电平信号，则保持所述第一标志位和第二标志位配置为0；
    如果所述第一处理器根据变频器工作状态判断生成所述触发电平信号且所述第一处理器接收到驱动电路输出的反馈信号，则将所述第一标志位和第二标志位配置为1；
    如果所述第一处理器判断所述反馈信号中存在输出脉冲，则将所述第三标志位配置为跟随所述触发电平信号；如果生成所述触发电平信号，则将所述第三标志位配置为1；
    判断所述第一标志位、第二标志位和第三标志位是否均配置为1；
    如果所述第一标志位、第二标志位和第三标志位均配置为1，则将所述第四标志位配置为1，所述第一处理器向第二处理器输出驱动异常电平信号；
    如果所述第一标志位、第二标志位和第三标志位不均配置为1，则保持将第四标志位配置为0，如果第一标志位和第二标志位均配置为0，所述第一处理器向第二处理器输出***保持电平信号；如果第一标志位和第二标志位均配置为1，所述第一处理器向第二处理器输出驱动正常电平信号。
  6. 根据权利要求1至5任一项所述的变频器LGBT驱动控制方法，其特征在于，
    所述第一处理器为CPLD控制器。
  7. 一种变频器IGBT驱动控制装置，其特征在于，包括：
    触发电平信号生成模块，所述触发电平信号生成模块用于根据变频器工作状态判断是否生成触发电平信号；
    第一判断模块，所述第一判断模块用于在生成所述触发电平信号的状态下，接收驱动电路输出的反馈信号并判断所述反馈信号中是否存在输出脉冲；
    第二判断模块，所述第二判断模块用于在所述反馈信号中存在所述输出脉冲的状态下判断当前反馈信号与所述触发电平信号的电平状态是否相同；和
    信号输出模块，所述信号输出模块用于在所述第二判断模块判断当前反馈信号与所述触发电平信号的电平状态相同时，配置向外部处理器输出驱动异常电平信号；且用于在所述第二判断模块判断当前反馈信号与所述触发电平信号的电平状态相反时，配置向外部处理器输出驱动正常电平信号。
  8. 根据权利要求7所述的变频器IGBT驱动控制装置，其特征在于，
    所述信号输出模块还用于在不生成所述触发电平信号的状态下，配置向外部处理器输出***保持电平信号；其中，所述***保持电平信号与所述驱动异常电平信号的电平状态相同。
  9. 根据权利要求8所述的变频器IGBT驱动控制装置，其特征在于，
    所述驱动异常电平信号为高电平信号，所述驱动正常电平信号为低电平信号，所述***保持电平信号为高电平信号。
  10. 根据权利要求8所述的变频器IGBT驱动控制装置，其特征在于，
    所述驱动异常电平信号为低电平信号，所述驱动正常电平信号为高电平信号，所述***保持电平信号为低电平信号。
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