WO2021203485A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

Info

Publication number
WO2021203485A1
WO2021203485A1 PCT/CN2020/086024 CN2020086024W WO2021203485A1 WO 2021203485 A1 WO2021203485 A1 WO 2021203485A1 CN 2020086024 W CN2020086024 W CN 2020086024W WO 2021203485 A1 WO2021203485 A1 WO 2021203485A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
node
potential
signal
output terminal
Prior art date
Application number
PCT/CN2020/086024
Other languages
English (en)
French (fr)
Inventor
陶健
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/966,032 priority Critical patent/US11749166B2/en
Publication of WO2021203485A1 publication Critical patent/WO2021203485A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular, to a GOA circuit and a display panel.
  • GOA Gate Driver On Array
  • GOA technology can reduce the bonding process of external IC, can reduce product cost, and is more suitable for manufacturing narrow-frame or borderless display products.
  • the existing GOA circuit includes a plurality of cascaded GOA units, and each level of GOA unit correspondingly drives a level of horizontal scan line.
  • Each level of GOA unit mainly includes a pull-up circuit, a pull-up control circuit, a pull-down circuit, and a pull-down sustain circuit.
  • the pull-up circuit is mainly responsible for outputting the clock signal as the gate signal, that is, the Gate signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and is generally connected to the Gate signal transmitted by the previous GOA unit; the pull-down circuit is responsible for the first time The Gate signal is pulled down to a low level, that is, the Gate signal is turned off; the pull-down sustain circuit is responsible for maintaining the Gate signal and the Gate signal of the pull-up circuit (usually called the Q point) in the off state.
  • FIG. 1 is a circuit diagram of an existing GOA circuit
  • FIG. 2 is an ideal timing diagram of an existing GOA circuit
  • FIG. 3 is a simulation timing diagram of an existing GOA circuit.
  • the potentials of node Qb and node Qa are maintained by capacitor C1, but in the case of long-term maintenance, such as in the t1 and t2 stages of Figure 2 and Figure 3, the capacitor C1 will pass through NT2 and NT10 If the two leakage paths leak, the potentials of node Qb and node Qa will decrease over time, especially when the holding time is long, the voltage of node Qb and node Qa will drop faster, so that the bootstrap voltage of node Qa ( Phase t2) will become lower, which will affect the gate output waveform, causing an abnormal screen, that is, the bootstrap voltage (the gate voltage of the driving transistor T3), that is, the potential of the node Qb and the node Qa will decrease due to leakage, thereby affecting the bootstrap voltage. Amplitude, leading to serious distortion of the gate output waveform, causing abnormal display of the screen.
  • the present application provides a GOA circuit and a display panel to solve the problem that when the screen holding time is longer during the touch scan phase during the normal display phase, the potential of the node Qb and the node Qa is reduced, which causes serious distortion of the gate output waveform and causes the screen The problem of abnormal display.
  • the present application provides a GOA circuit.
  • the GOA circuit includes a plurality of cascaded GOA units.
  • the GOA units of each stage include: a positive and negative scanning module 100, a reset module 200, a pull-up module 300, a pull-down module 400, and a voltage regulator Module 500, anti-leakage module 500, voltage stabilization module 600, signal control module 700, and pull-up maintenance module 800.
  • the positive and negative scanning module 100 includes a first transistor T1 and a second transistor T2, wherein the gate of the first transistor T1 is connected to the output terminal G(N-1) of the upper-level GOA unit, and the source is connected to the forward The scan signal U2D, the drain is electrically connected to the first node Qb; the gate of the second transistor T2 is connected to the output terminal G(N+1) of the lower-level GOA unit, the source is connected to the reverse scan signal D2U, and the drain is Electrically connected to the first node Qb.
  • the reset module 200 includes a seventh transistor T7, wherein the gate and source of the seventh transistor T7 are both connected to the reset signal Reset, and the drain is electrically connected to the second node P.
  • the pull-up module 300 includes a third transistor T3, wherein the gate of the third transistor T3 is electrically connected to the pull-up node Qa, the source is connected to the Nth clock signal CK(N), and the drain is electrically connected The output terminal G (N).
  • the pull-down module 400 includes a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is
  • the leakage prevention module 500 includes a ninth transistor T9, wherein the gate of the ninth transistor T9 is connected to the second potential, the source is electrically connected to the first node Qb, and the drain is electrically connected to the Pull up node Qa.
  • the voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to the first potential; One end of the two capacitors C2 is electrically connected to the second node P, and the other end is connected to the first potential.
  • the signal control module 700 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is electrically connected to the first node Qb, the source is connected to the first potential, and the drain is connected to the first node Qb. Is electrically connected to the second node P; the gate of the sixth transistor T6 is connected to the N+1th clock signal CK(N+1), the source is connected to the second potential, and the drain is electrically connected The second node P.
  • the pull-up maintenance module 800 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13, wherein the gate and source of the eleventh transistor T11 are both connected to the second potential, The drain is electrically connected to the third node K; the gate of the twelfth transistor T12 is electrically connected to the third node K, the source is connected to the second potential, and the drain is electrically connected to the first node Qb; the gate of the thirteenth transistor T13 is electrically connected to the second node P, the source is connected to the first potential, and the drain is electrically connected to the third node K.
  • the GOA circuit has a reset phase and a normal display phase.
  • the reset signal Reset provides a single pulse signal of the second potential to control the seventh transistor T7 to turn on so that the second node P is at the second potential, and the second node P controls
  • the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned on so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K Is the first potential.
  • the normal display phase includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t3.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second level so that the first transistor T1 or The second transistor T2 is turned on, so that the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged.
  • the third transistor T3 and the The fifth transistor T5 is turned on; the fifth transistor T5 is turned on to convert the second node P to the first potential so that the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned off .
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit provide a first level so that the first transistor T1 and The second transistor T2 is turned off, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on to keep the first node Qb at the second potential, and the pull-up node
  • the potential of Qa is converted from the second potential to a bootstrap potential; at the same time, the Nth clock signal CK(N) provides the second potential and is output as the output terminal G( N) Signal.
  • the thirteenth transistor T13 is turned off so that the third node K is converted to the second potential under the control of the eleventh transistor, so that all The twelfth transistor T12 is turned on to charge the first node Qb so that the first node Qb maintains the second potential.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second potential to enable the first transistor T1 or the second transistor T2 to turn on.
  • the scan signal U2D or the reverse scan signal D2U provides a first potential to the first node Qb and the pull-up node Qa, and the N+1th clock signal CK(N+1) turns on the sixth transistor T6 to
  • the second node P is converted to the second potential and the second capacitor C2 is charged.
  • the second node P causes the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor to be charged.
  • the transistor T13 is turned on to convert the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K into a first potential; the third node K enables the The twelfth transistor is turned off so that the twelfth transistor T12 stops charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at the first potential to keep the third transistor T3 off, and the second capacitor C2 keeps the second node P The second potential is maintained to keep the fourth transistor T4 turned on, and the output terminal G(N) is maintained at the first potential.
  • one of the forward scan signal U2D and the reverse scan signal D2U is at a high level and the other signal is at a low level.
  • the output terminal G(N-1) of the upper-level GOA unit controls the first transistor T1 to turn on, and the gate of the first transistor T1 of the first-level GOA unit is connected to the start signal STV.
  • the output terminal G(N+1) of the lower-level GOA unit controls the second transistor T2 to turn on, and the gate of the second transistor T2 of the final-level GOA unit is connected to the start signal STV.
  • each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high potential VGH.
  • the reset signal Reset provides a single high-potential pulse signal to make the second node P high, the first node Qb, the pull-up node Qa, the third node K,
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit are both low potential.
  • the forward scan signal U2D is a constant voltage high potential VGH during forward scanning and the reverse scan signal D2U is a constant voltage low potential VGL during reverse scanning.
  • the forward scan signal U2D is a constant voltage low potential VGL and the reverse scan signal D2U is a constant voltage high potential VGH
  • the second node P, the Nth clock signal CK(N), the first N+1 clock signals CK(N+1), the output terminal G(N), and the output terminal (G+1) of the lower-level GOA unit are all low potentials
  • the first node Qb, the pull-up node Qa, and the third node K are all high potentials.
  • the second node P, the N+1th clock signal CK(N+1), and the upper-level GOA unit output terminal G(N-1) And the output terminal G(N+1) of the lower-level GOA unit are both low potentials, the first node Qb, the pull-up node Qa, the third node K, and the Nth clock signal CK(N ) And the output terminal G(N) are both high potential;
  • the first node Qb, the pull-up node Qa, the third node K, the Nth clock signal CK(N), the output The terminal G(N) and the output terminal G(N-1) of the upper-level GOA unit are both low, the second node P, the N+1th clock signal CK(N+1) and the The output terminal G(N+1) of the lower-level GOA unit is all high potential.
  • the GOA circuit further includes an output control module 900
  • the output control module 900 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the global control signal GAS, and the source is connected to the The first potential, the drain is electrically connected to the output terminal G(N).
  • the GOA circuit further includes a touch scan phase after the normal display phase
  • the global control signal GAS controls the output terminals G(N) of all GOA units to be converted to a first potential.
  • each transistor in the GOA circuit is an N-type thin film transistor, and the global control signal GAS is at a low level during the reset phase and the normal display phase, and during the touch scan phase For high potential.
  • each clock signal is a periodic pulse signal; during the touch scan phase, each clock signal is synchronized with the frequency of the touch scan signal Pulse signal.
  • the GOA circuit includes a first clock signal CK1 and a second clock signal CK2; when the Nth clock signal CK(N) is the first clock signal CK1, the Nth clock signal CK1 +1 clock signal CK(N+1) is CK2; in the reset phase and the normal display phase, the period of the first clock signal CK1 and the second clock signal CK2 are the same, and the previous clock signal When the pulse signal of the signal ends, the next clock pulse signal is generated.
  • An embodiment of the present application also provides a display panel including the GOA circuit described above.
  • the GOA circuit includes a plurality of cascaded GOA units, and the GOA units at each stage include: a positive and negative scanning module 100, a reset module 200, a pull-up module 300, a pull-down module 400, a voltage stabilizing module 500, an anti-leakage module 500, The voltage stabilization module 600, the signal control module 700, and the pull-up maintenance module 800.
  • the positive and negative scanning module 100 includes a first transistor T1 and a second transistor T2, wherein the gate of the first transistor T1 is connected to the output terminal G(N-1) of the upper-level GOA unit, and the source is connected to the forward The scan signal U2D, the drain is electrically connected to the first node Qb; the gate of the second transistor T2 is connected to the output terminal G(N+1) of the lower-level GOA unit, the source is connected to the reverse scan signal D2U, and the drain is Electrically connected to the first node Qb.
  • the reset module 200 includes a seventh transistor T7, wherein the gate and source of the seventh transistor T7 are both connected to the reset signal Reset, and the drain is electrically connected to the second node P.
  • the pull-up module 300 includes a third transistor T3, wherein the gate of the third transistor T3 is electrically connected to the pull-up node Qa, the source is connected to the Nth clock signal CK(N), and the drain is electrically connected The output terminal G (N).
  • the pull-down module 400 includes a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is
  • the leakage prevention module 500 includes a ninth transistor T9, wherein the gate of the ninth transistor T9 is connected to the second potential, the source is electrically connected to the first node Qb, and the drain is electrically connected to the Pull up node Qa.
  • the voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to the first potential; One end of the two capacitors C2 is electrically connected to the second node P, and the other end is connected to the first potential.
  • the signal control module 700 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is electrically connected to the first node Qb, the source is connected to the first potential, and the drain is connected to the first node Qb. Is electrically connected to the second node P; the gate of the sixth transistor T6 is connected to the N+1th clock signal CK(N+1), the source is connected to the second potential, and the drain is electrically connected The second node P.
  • the pull-up maintenance module 800 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13, wherein the gate and source of the eleventh transistor T11 are both connected to the second potential, The drain is electrically connected to the third node K; the gate of the twelfth transistor T12 is electrically connected to the third node K, the source is connected to the second potential, and the drain is electrically connected to the first node Qb; the gate of the thirteenth transistor T13 is electrically connected to the second node P, the source is connected to the first potential, and the drain is electrically connected to the third node K.
  • the GOA circuit has a reset phase and a normal display phase.
  • the reset signal Reset provides a single pulse signal of the second potential to control the seventh transistor T7 to turn on so that the second node P is at the second potential, and the second node P controls
  • the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned on so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K Is the first potential.
  • the normal display phase includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t3.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second level so that the first transistor T1 or The second transistor T2 is turned on, so that the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged.
  • the third transistor T3 and the The fifth transistor T5 is turned on; the fifth transistor T5 is turned on to convert the second node P to the first potential so that the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned off .
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit provide a first level so that the first transistor T1 and The second transistor T2 is turned off, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on to keep the first node Qb at the second potential, and the pull-up node
  • the potential of Qa is converted from the second potential to a bootstrap potential; at the same time, the Nth clock signal CK(N) provides the second potential and is output as the output terminal G( N) Signal.
  • the thirteenth transistor T13 is turned off so that the third node K is converted to the second potential under the control of the eleventh transistor, so that all The twelfth transistor T12 is turned on to charge the first node Qb so that the first node Qb maintains the second potential.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second potential to enable the first transistor T1 or the second transistor T2 to turn on.
  • the scan signal U2D or the reverse scan signal D2U provides a first potential to the first node Qb and the pull-up node Qa, and the N+1th clock signal CK(N+1) turns on the sixth transistor T6 to
  • the second node P is converted to the second potential and the second capacitor C2 is charged.
  • the second node P causes the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor to be charged.
  • the transistor T13 is turned on to convert the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K into a first potential; the third node K enables the The twelfth transistor is turned off so that the twelfth transistor T12 stops charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at the first potential to keep the third transistor T3 off, and the second capacitor C2 keeps the second node P The second potential is maintained to keep the fourth transistor T4 turned on, and the output terminal G(N) is maintained at the first potential.
  • one of the forward scan signal U2D and the reverse scan signal D2U is at a high level and the other signal is at a low level.
  • the output terminal G(N-1) of the upper-level GOA unit controls the first transistor T1 to turn on, and the gate of the first transistor T1 of the first-level GOA unit is connected to the start signal STV.
  • the output terminal G(N+1) of the lower-level GOA unit controls the second transistor T2 to turn on, and the gate of the second transistor T2 of the final-level GOA unit is connected to the start signal STV.
  • each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high potential VGH.
  • the reset signal Reset provides a single high-potential pulse signal to make the second node P high, the first node Qb, the pull-up node Qa, the third node K,
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit are both low potential.
  • the forward scan signal U2D is a constant voltage high potential VGH during forward scanning and the reverse scan signal D2U is a constant voltage low potential VGL during reverse scanning.
  • the forward scan signal U2D is a constant voltage low potential VGL and the reverse scan signal D2U is a constant voltage high potential VGH
  • the second node P, the Nth clock signal CK(N), the first N+1 clock signals CK(N+1), the output terminal G(N), and the output terminal (G+1) of the lower-level GOA unit are all low potentials
  • the first node Qb, the pull-up node Qa, and the third node K are all high potentials.
  • the second node P, the N+1th clock signal CK(N+1), and the upper-level GOA unit output terminal G(N-1) And the output terminal G(N+1) of the lower-level GOA unit are both low potentials, the first node Qb, the pull-up node Qa, the third node K, and the Nth clock signal CK(N ) And the output terminal G(N) are both high potential;
  • the first node Qb, the pull-up node Qa, the third node K, the Nth clock signal CK(N), the output The terminal G(N) and the output terminal G(N-1) of the upper-level GOA unit are both low, the second node P, the N+1th clock signal CK(N+1) and the The output terminal G(N+1) of the lower-level GOA unit is all high potential.
  • the GOA circuit further includes an output control module 900
  • the output control module 900 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the global control signal GAS, and the source is connected to the The first potential, the drain is electrically connected to the output terminal G(N).
  • the GOA circuit further includes a touch scan phase after the normal display phase
  • the global control signal GAS controls the output terminals G(N) of all GOA units to be converted to a first potential.
  • each transistor in the GOA circuit is an N-type thin film transistor, and the global control signal GAS is at a low level during the reset phase and the normal display phase, and during the touch scan phase For high potential.
  • each clock signal is a periodic pulse signal; during the touch scan phase, each clock signal is synchronized with the frequency of the touch scan signal Pulse signal.
  • the GOA circuit includes a first clock signal CK1 and a second clock signal CK2; when the Nth clock signal CK(N) is the first clock signal CK1, the Nth clock signal CK1 +1 clock signal CK(N+1) is CK2; in the reset phase and the normal display phase, the first clock signal CK1 and the second clock signal CK2 have the same period, and the previous clock signal When the pulse signal of the signal ends, the next clock pulse signal is generated.
  • the pull-up sustaining module 800 composed of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 is provided between the forward and reverse scanning module 100 and the first node Qb, so In the pre-charge sub-phase t1 and the output sub-phase t2 of the normal display phase, since the first node Qb is at a high potential, the second node P is pulled down to turn off the thirteenth transistor T13, so that the third node K is turned off by the eleventh transistor T11 is controlled to switch to a high potential, so that the twelfth transistor T12 is turned on and the first node Qb maintains the second potential, and the pull-up node Qa maintains the second potential during the precharge sub-phase t1 and the bootstrap potential during the output sub-phase t2.
  • the second node P is set high to turn on the thirteenth transistor T13, so that the third node K is pulled low. In this way, the third node K turns off the twelfth transistor T12 and stops charging the first node Qb, without affecting the pull-down process.
  • Fig. 1 is a circuit diagram of an existing GOA.
  • Figure 2 is an ideal timing diagram of an existing GOA circuit.
  • Fig. 3 is a simulation timing diagram of an existing GOA circuit.
  • Figure 4 is a GOA circuit diagram of an embodiment of the application.
  • FIG. 5 is a simulation timing diagram of the GOA circuit according to an embodiment of the application.
  • FIG. 6 is a simulation comparison diagram of the pull-up node Qa in the existing GOA circuit and the GOA circuit of the embodiment of the present application when the holding time is 0 seconds.
  • FIG. 7 is a simulation comparison diagram of the pull-up node Qa in the existing GOA circuit and the GOA circuit of the embodiment of the present application when the holding time is 200 microseconds.
  • FIG. 4 is a GOA circuit provided by an embodiment of the application.
  • the GOA circuit includes cascaded multi-level GOA units.
  • Each level of GOA unit includes: a positive and negative scan module 100, a reset module 200, a pull-up module 300, The pull-down module 400, the voltage stabilization module 500, the anti-leakage module 500, the voltage stabilization module 600, the signal control module 700, and the pull-up maintenance module 800.
  • the positive and negative scanning module 100 includes a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is connected to the output terminal G(N-1) of the upper-level GOA unit, and the source is connected to the forward scanning signal U2D.
  • the drain is electrically connected to the first node Qb;
  • the gate of the second transistor T2 is connected to the output terminal G(N+1) of the lower-level GOA unit, the source is connected to the reverse scan signal D2U, and the drain is electrically connected to the first node Qb.
  • the reset module 200 includes a seventh transistor T7.
  • the gate and source of the seventh transistor T7 are both connected to the reset signal Reset, and the drain is electrically connected to the second node P.
  • the pull-up module 300 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the pull-up node Qa, the source is connected to the Nth clock signal CK(N), and the drain is electrically connected to the output terminal G(N). .
  • the pull-down module 400 includes a fourth transistor T4 and a tenth transistor T10.
  • the gates of the fourth transistor T4 and the tenth transistor T10 are electrically connected to the second node P, the sources are connected to the first potential, and the drain of the fourth transistor T4
  • the pole is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the first node Qb.
  • the leakage prevention module 500 includes a ninth transistor T9.
  • the gate of the ninth transistor T9 is connected to the second potential, the source is electrically connected to the first node Qb, and the drain is electrically connected to the pull-up node Qa.
  • the voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2. One end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to the first potential; one end of the second capacitor C2 is electrically connected to the second node P , The other end is connected to the first potential.
  • the signal control module 700 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is electrically connected to the first node Qb, the source is connected to the first potential, and the drain is electrically connected to the second node P;
  • the gate of the transistor T6 is connected to the N+1th clock signal CK(N+1), the source is connected to the second potential, and the drain is electrically connected to the second node P.
  • the pull-up maintenance module 800 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.
  • the gate and source of the eleventh transistor T11 are both connected to the second potential, and the drain is electrically connected to the third node K;
  • the gate of the twelfth transistor T12 is electrically connected to the third node K, the source is connected to the second potential, and the drain is electrically connected to the first node Qb;
  • the gate of the thirteenth transistor T13 is electrically connected to the second node P, the source is connected to the first potential, and the drain is electrically connected to the third node K.
  • the working process of the GOA circuit has a reset stage and a normal display stage.
  • the reset signal Reset provides a single second potential pulse signal to control the seventh transistor T7 to turn on to make the second node P the second potential, and the second node P controls the fourth transistor T4, the tenth transistor T10 and the thirteenth transistor T13 is turned on so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K are at the first potential.
  • the normal display stage includes a pre-charge sub-stage t1, an output sub-stage t2, and a pull-down sub-stage t3.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second level to enable the first transistor T1 or the second transistor T2 to turn on
  • the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged, while the third transistor T3 and the fifth transistor T5 are turned on; the fifth transistor T5 is turned on to convert the second node P to the first potential So that the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned off.
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit provide the first level to turn off the first transistor T1 and the second transistor T2.
  • the transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on to keep the first node Qb at the second potential, and the potential of the pull-up node Qa is converted from the second potential to the bootstrap potential; at the same time, the Nth clock signal CK( N) Provide a second potential and output it as an output terminal G(N) signal through the third transistor T3.
  • the thirteenth transistor T13 is turned off to convert the third node K from the eleventh transistor to the second potential, so that the twelfth transistor T12 is turned on and the first node Qb is charged to make The first node Qb maintains the second potential.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second potential to turn on the first transistor T1 or the second transistor T2, and scan forward
  • the signal U2D or the reverse scan signal D2U provides a first potential to the first node Qb and the pull-up node Qa, and the N+1th clock signal CK(N+1) turns on the sixth transistor T6 to switch the second node P
  • the second node P turns on the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 to make the output terminal G(N), the first node Qb, and the pull-up node Qa and the third node K are converted to the first potential;
  • the third node K turns off the twelfth transistor and causes the twelfth transistor T12 to stop charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at the first potential to keep the third transistor T3 off
  • the second capacitor C2 keeps the second node P at the second potential to keep the fourth transistor T4 on
  • the output terminal G(N) maintains the first potential.
  • one of the forward scanning signal U2D and the reverse scanning signal D2U is at a high level and the other signal is at a low level; during forward scanning, the output terminal G(N-1) of the upper-level GOA unit controls the first The transistor T1 is turned on, and the gate of the first transistor T1 of the first-level GOA unit is connected to the start signal STV (not shown in Fig. 5); during reverse scanning, the output terminal G(N+1) of the lower-level GOA unit controls the second The transistor T2 is turned on, and the gate of the second transistor T2 of the final GOA unit is connected to the start signal STV.
  • FIG. 5 is a simulation timing diagram of the GOA circuit of the embodiment of the application.
  • FIG. 5 corresponds to that each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high The situation of potential VGH.
  • the forward scanning signal U2D When scanning in the forward direction, the forward scanning signal U2D is a constant voltage high potential VGH and the reverse scanning signal D2U is a constant voltage low potential VGL.
  • the forward scanning signal U2D When scanning in a reverse direction, the forward scanning signal U2D is a constant voltage low potential VGL and the reverse scanning signal D2U is Constant voltage and high potential VGH (not shown in FIG. 5), the embodiment of the present application takes forward scanning as an example.
  • the GOA circuit workflow includes a reset phase and a normal display phase, as described in detail below.
  • the reset signal Reset provides a single high-potential pulse signal earlier than other control signals to control the seventh transistor to turn on, so that the second node P is high.
  • the second node P controls the fourth transistor T4, the tenth transistor T10 and The thirteenth transistor T13 is turned on, thereby pre-pulling the output terminal G(N), the first node Qb, the pull-up node Qa and the third node K low, so that the initial potential of the output terminal G(N) is the constant voltage low potential VGL .
  • the reset signal Reset is set low, and the seventh transistor T7 is turned off, waiting for the arrival of the normal display stage.
  • the normal display phase also includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t3.
  • the output terminal G(N-1) of the upper-level GOA unit provides a high level to turn on the first transistor T1, so that the first node Qb and the pull-up node Qa are pulled up to a constant voltage.
  • the first capacitor C1 is charged, and the third transistor T3 and the fifth transistor T5 are turned on; the fifth transistor T5 causes the second node P to be pulled down to the constant voltage low potential VHL, so that the fourth transistor T4,
  • the tenth transistor T10 and the thirteenth transistor T13 are turned off.
  • the Nth clock signal CKN is at a high potential
  • the third transistor T3 outputs the Nth clock signal CK(N) as the output terminal G(N) signal.
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit are both low potential
  • the first transistor T1 and the second transistor T2 are both turned off
  • the third transistor T3 Turned on, the first node Qb and the pull-up node Qa have no leakage paths, so they still maintain a high potential.
  • the pull-up node Qa is due to The lifting effect is pulled higher, from the constant voltage high potential VGH to a higher bootstrap potential.
  • the thirteenth transistor T13 is turned off so that the third node K is controlled by the eleventh transistor T11 to switch to the second potential, so that the twelfth transistor T12 is turned on and the first node Qb is turned on. Maintain the second potential.
  • the leakage prevention module 500 includes a twelfth transistor T12.
  • the gate of the twelfth transistor T12 is connected to a constant voltage high potential VGH to keep the twelfth transistor T12 open, and the first node Qb is at a constant voltage high potential At VGH, the twelfth transistor T12 is equivalent to a diode that is turned on in the direction of pulling up the node Qa from the first node Qb to prevent the high potential of the pull-up node Qa from being higher than the high potential of the first node Qb. Backflow to the first node Qb, so as to maintain the high potential of the bootstrap of the pull-up node Qa.
  • the output terminal G(N+1) of the lower-level GOA unit provides a high potential to turn on the first transistor T1 or the second transistor T2, and the reverse scan signal D2U provides a low level to the first node Qb and the pull-up node Qa.
  • the N+1th clock signal CK(N+1) provides a high potential to turn on the sixth transistor T6 so that the second node P is pulled up to the constant voltage high potential VGH.
  • the second capacitor C2 is charged, and the second The node P turns on the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13, so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K are pulled down to a constant voltage low Potential VGL.
  • the third node K is pulled low to turn off the twelfth transistor T12 and stop charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at a constant voltage low potential VGL to keep the third transistor T3 off
  • the second capacitor C2 keeps the second node P at a constant voltage high potential VGH to make the fourth
  • the transistor T4 remains open, and the output terminal G (N) maintains a constant voltage low potential VGL.
  • the pull-up maintenance module 800 composed of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 is provided between the forward and backward scanning module 100 and the first node Qb. Therefore, in the pre-charge sub-phase t1 and the output sub-phase t2 of the normal display phase, since the first node Qb is at a high potential, the second node P is pulled down to turn off the thirteenth transistor T13, so that the third node K is changed from the tenth node.
  • a transistor T11 is controlled to switch to a high potential, so that the twelfth transistor T12 is turned on and the first node Qb maintains the second potential, and the pull-up node Qa maintains the second potential during the precharge sub-phase t1 and maintains the bootstrap during the output sub-phase t2 Potential.
  • the pull-down sub-phase t3 when the output terminal G(N+1) of the lower-level GOA unit receives the pull-down signal, the second node P is set high to turn on the thirteenth transistor T13, so that the third node K is pulled low. In this way, the third node K turns off the twelfth transistor T12 and stops charging the first node Qb, without affecting the pull-down process.
  • the holding time is 0 seconds and 200 microseconds
  • the original output waveform of the pull-up node Qa in the precharge sub-phase t1 and output sub-phase t2 (the pull-up node Qa in Figure 3 Figure 6 and Figure 7 are obtained by comparing the waveform) with the current output waveform (the waveform of the pull-up node Qa in Figure 5).
  • Figure 6 shows the current GOA circuit with a holding time of 0 microseconds and the GOA circuit in the embodiment of the application.
  • FIG. 7 is a simulation comparison diagram of the pull-up node Qa in the existing GOA circuit and the GOA circuit of the embodiment of the present application when the holding time is 200 microseconds, where the dashed curve is the pull-up node Qa The original output waveform of, the solid curve is the current output waveform of the pull-up node Qa. .
  • the amplitude of the current output waveform of the pull-up node Qa in the pre-charge sub-phase t1 and output sub-phase t2 is higher than the original output waveform.
  • the original output waveform is in the charging process of the pre-charge sub-phase t1
  • the bootstrap voltage of the output sub-phase t2 also shows a voltage drop behavior, and when the holding time is long, the pull-up node Qa has been dropping, the drop amplitude is about 0.5V, and the bootstrap voltage is about 0.5V. The potential is also affected.
  • the GOA circuit further includes an output control module 900.
  • the output control module 900 includes an eighth transistor T8.
  • the gate of the eighth transistor T8 is connected to the global control signal GAS, the source is connected to the first potential, and the drain is electrically connected. Connect the output terminal G(N).
  • the GOA circuit also includes a touch scanning stage after the normal display stage; in the touch scanning stage, the global control signal GAS controls the output terminals G(N) of all stages of GOA units to be converted to the first potential, which is called All gate
  • the off function is to turn off the G(N) signal at the output terminals of all GOA units to suspend the cascade when the touch scan phase comes, so as to prevent interference between the scan drive signal and the touch signal.
  • each transistor in the GOA circuit is an N-type thin film transistor, that is, the eighth transistor T8 is an N-type thin film transistor, and the global control signal GAS is at a low level during the reset phase and the normal display phase.
  • the stage is high potential.
  • each clock signal is a periodic pulse signal
  • each clock signal is a pulse signal synchronized with the frequency of the touch scan signal.
  • the GOA circuit includes a first clock signal CK1 and a second clock signal CK2; when the Nth clock signal CK(N) is the first clock signal CK1, the N+1th clock signal CK (N+1) is CK2; in the reset phase and the normal display phase, the cycles of the first clock signal CK1 and the second clock signal CK2 are the same, and the pulse signal of the previous clock signal ends while the next clock pulse signal is generated.
  • An embodiment of the present application also provides a display panel including the GOA circuit as described above, and the display panel has the same structure and beneficial effects as the GOA circuit provided in the foregoing embodiments. Since the foregoing embodiment has described the structure and beneficial effects of the GOA circuit in detail, it will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路及显示面板，设置了由T11、T12和T13构成的上拉维持模块，可在预充子阶段t1和输出子阶段t2中，由于Qb点为高电位而拉低P点使T13关闭，从而使K点由T11控制、转换为高电位，使T12打开而Qb点保持高电位，以及Qa点在预充子阶段保持高电位、在输出子阶段保持自举电位。

Description

GOA电路及显示面板 技术领域
本申请实施例涉及显示技术领域，尤其涉及一种GOA电路及显示面板。
 背景技术
GOA（Gate Driver On Array）技术是将显示面板的栅极驱动电路集成在玻璃基板上，形成对显示面板的扫描驱动。GOA技术能较少外接IC的绑定（bonding）工序，能降低产品成本，且更适合制作窄边框或无边框的显示产品。
现有的GOA电路包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。每一级GOA单元主要包括上拉电路、上拉控制电路、下拉电路和下拉维持电路。上拉电路主要负责将时钟信号输出为栅极信号即Gate信号；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA单元传递过来的Gate信号；下拉电路负责在第一时间将Gate信号拉低为低电位，即关闭Gate信号；下拉维持电路负责将Gate信号和上拉电路的Gate信号(通常称为Q点）维持在关闭状态。
图1为现有的一种GOA电路图，图2为现有的一种GOA电路的理想时序图，图3为现有的一种GOA电路的仿真时序图。参考图1，TDDI产品在触控扫描信号（touch 信号）来的时候，显示功能暂停，此时GOA的级传暂停，CLK均置低，而节点Qb和节点Qa却要保持高电平，等待touch结束后CK高电平到来。由于Touch 时间在200us到300us左右，节点Qb和节点Qa电位由电容C1维持，但是在长时间保持的情况下，例如在图2和图3的t1阶段和t2阶段，电容C1会通过NT2和NT10两个泄电路径漏电，节点Qb和节点Qa的电位就会随着时间降低，尤其在holding时间较长的情况，节点Qb和节点Qa电压会掉的比较快，这样节点Qa的自举电压（t2阶段）就会变低，从而影响gate输出波形，引起画面异常，即自举电压（驱动晶体管T3的栅极电压）即节点Qb和节点Qa电位会因为漏电而降低，从而影响自举电压的幅值，导致gate输出波形严重失真，引起画面异常显示。
 技术问题
本申请提供一种GOA电路及显示面板，以解决上述在正常显示阶段之中触控扫描阶段到来画面holding时间较长时，节点Qb和节点Qa的电位降低，导致gate输出波形严重失真，引起画面异常显示的问题。
 技术解决方案
本申请提供一种GOA电路，该GOA电路包括级联的多个GOA单元，每一级所述GOA单元包括：正反扫描模块100、复位模块200、上拉模块300、下拉模块400、稳压模块500、防漏电模块500、稳压模块600、信号控制模块700和上拉维持模块800。
所述正反扫描模块100包括第一晶体管T1和第二晶体管T2，其中，所述第一晶体管T1的栅极接入上级GOA单元的输出端G(N-1），源极接入正向扫描信号U2D，漏极电性连接第一节点Qb；所述第二晶体管T2的栅极接入下级GOA单元的输出端G(N+1），源极接入反向扫描信号D2U，漏极电性连接第一节点Qb。
所述复位模块200包括第七晶体管T7，其中，所述第七晶体管T7的栅极和源极均接入复位信号Reset，漏极电性连接第二节点P。
所述上拉模块300包括第三晶体管T3，其中，所述第三晶体管T3的栅极电性连接上拉节点Qa，源极接入第N条时钟信号CK（N），漏极电性连接输出端G（N）。
所述下拉模块400包括第四晶体管T4和第十晶体管T10，其中，所述第四晶体管T4和所述第十晶体管T10的栅极均电性连接第二节点P，所述第四晶体管T4和所述第十晶体管T10的源极均接入第一电位，所述第四晶体管T4的漏极电性连接所述输出端G（N），所述第十晶体管T10的漏极电性连接所述第一节点Qb。
所述防漏电模块500包括第九晶体管T9，其中，所述第九晶体管T9的栅极接入所述第二电位，源极电性连接所述第一节点Qb，漏极电性连接所述上拉节点Qa。
所述稳压模块600包括第一电容C1和第二电容C2，其中，所述第一电容C1的一端电性连接所述第一节点Qb，另一端接入所述第一电位；所述第二电容C2的一端电性连接所述第二节点P，另一端接入所述第一电位。
所述信号控制模块700包括第五晶体管T5和第六晶体管T6，其中，所述第五晶体管T5的栅极电性连接所述第一节点Qb，源极接入所述第一电位，漏极电性连接所述第二节点P；所述第六晶体管T6的栅极接入第N+1条时钟信号CK（N+1），源极接入所述第二电位，漏极电性连接所述第二节点P。
所述上拉维持模块800包括第十一晶体管T11、第十二晶体管T12和第十三晶体管T13，其中，所述第十一晶体管T11的栅极和源极均接入所述第二电位，漏极电性连接第三节点K；所述第十二晶体管T12的栅极电性连接所述第三节点K，源极接入所述第二电位，漏极电性连接所述第一节点Qb；所述第十三晶体管T13的栅极电性连接所述第二节点P，源极接入所述第一电位，漏极电性连接所述第三节点K。
在一些实施例中，所述GOA电路具有复位阶段和正常显示阶段。
在所述复位阶段，所述复位信号Reset提供单个所述第二电位的脉冲信号控制所述第七晶体管T7打开使所述第二节点P为所述第二电位，所述第二节点P控制所述第四晶体管T4、第十晶体管T10和所述第十三晶体管T13打开使所述输出端G（N）、所述第一节点Qb、所述上拉节点Qa和所述第三节点K为所述第一电位。
所述正常显示阶段包括预充子阶段t1、输出子阶段t2和下拉子阶段t3。
在所述预充子阶段t1，所述上级GOA单元的输出端G(N-1)或所述下级GOA单元的输出端G(N+1)提供第二电平使所述第一晶体管T1或所述第二晶体管T2打开，以使所述第一节点Qb和所述上拉节点Qa转换为所述第二电位且所述第一电容C1被充电，同时使所述第三晶体管T3和所述第五晶体管T5打开；所述第五晶体管T5打开使所述第二节点P转换为第一电位以使所述第四晶体管T4、所述第十晶体管T10和所述第十三晶体管T13关闭。
在所述输出子阶段t2，所述上级GOA单元的输出端G(N-1)和所述下级GOA单元的输出端G(N+1)提供第一电平使所述第一晶体管T1和所述第二晶体管T2关闭，所述第一晶体管T1和所述第二晶体管T2关闭、所述第三晶体管T3打开使所述第一节点Qb保持为所述第二电位，所述上拉节点Qa的电位由所述第二电位转换为自举电位；同时，所述第N条时钟信号CK（N）提供所述第二电位并通过所述第三晶体管T3输出为所述输出端G（N）信号。
在所述预充子阶段t1和所述输出子阶段t2中，所述第十三晶体管T13关闭使所述第三节点K由所述第十一晶体管控制转换为所述第二电位，以使所述第十二晶体管T12打开而对所述第一节点Qb充电使所述第一节点Qb保持所述第二电位。
在所述下拉子阶段t3，上级GOA单元的输出端G(N-1)或下级GOA单元的输出端G(N+1)提供第二电位使第一晶体管T1或第二晶体管T2打开，正向扫描信号U2D或反向扫描信号D2U向第一节点Qb和上拉节点Qa提供第一电位，且所述第N+1条时钟信号CK（N+1）使所述第六晶体管T6打开以使所述第二节点P转换为所述第二电位且所述第二电容C2被充电，所述第二节点P使所述第四晶体管T4、所述第十晶体管T10和所述第十三晶体管T13打开以使所述输出端G（N）、所述第一节点Qb、所述上拉节点Qa和所述第三节点K转换为第一电位；所述第三节点K使所述第十二晶体管关闭而使所述第十二晶体管T12停止对所述第一节点Qb充电。
之后，所述第一电容C1使所述第一节点Qb和所述上拉节点Qa维持第一电位以使所述第三晶体管T3保持关闭，所述第二电容C2使所述第二节点P维持第二电位以使所述第四晶体管T4保持打开，所述输出端G（N）保持所述第一电位。
在一些实施例中，所述正向扫描信号U2D和所述反向扫描信号D2U中的一个信号为高电位且另一个信号为低电位。
正向扫描时所述上级GOA单元的输出端G(N-1）控制所述第一晶体管T1打开，首级GOA单元的第一晶体管T1的栅极接入起始信号STV。
反向扫描时所述下级GOA单元的输出端G(N+1）控制所述第二晶体管T2打开，末级GOA单元的第二晶体管T2的栅极接入所述起始信号STV。
在一些实施例中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述第一电位为恒压低电位VGL，所述第二电位为恒压高电位VGH。
在所述复位阶段，所述复位信号Reset提供单个高电位的脉冲信号使所述第二节点P为高电位，所述第一节点Qb、所述上拉节点Qa、所述第三节点K、所述正向扫描信号U2D、反向扫描信号D2U、所述第N条时钟信号CK（N）、所述第N+1条时钟信号CK（N+1）、所述输出端G(N)、所述上级GOA单元输出端G(N-1）和所述下级GOA单元输出端G(N+1）均为低电位。
在所述正常显示阶段的所述预充子阶段t1，正向扫描时所述正向扫描信号U2D为恒压高电位VGH且所述反向扫描信号D2U为恒压低电位VGL，反向扫描时所述正向扫描信号U2D为恒压低电位VGL且所述反向扫描信号D2U为恒压高电位VGH，所述第二节点P、所述第N条时钟信号CK（N）、所述第N+1条时钟信号CK（N+1）、所述输出端G(N)和所述下级GOA单元输出端（G+1）均为低电位，所述上级GOA单元输出端G(N-1）、所述第一节点Qb、所述上拉节点Qa和所述第三节点K均为高电位。
在所述正常显示阶段的所述输出子阶段t2，所述第二节点P、所述第N+1条时钟信号CK（N+1）、所述上级GOA单元输出端G(N-1）和所述下级GOA单元输出端G(N+1）均为低电位，所述第一节点Qb、所述上拉节点Qa、所述第三节点K、所述第N条时钟信号CK（N）和所述输出端G(N)均为高电位；
在所述正常显示阶段的所述下拉子阶段t3，所述第一节点Qb、所述上拉节点Qa、所述第三节点K、所述第N条时钟信号CK（N）、所述输出端G(N)和所述上级GOA单元的输出端G(N-1）均为低电位，所述第二节点P、所述第N+1条时钟信号CK（N+1）和所述下级GOA单元输出端G(N+1）均为高电位。
在一些实施例中，该GOA电路还包括输出控制模块900，所述输出控制模块900包括第八晶体管T8，所述第八晶体管T8的栅极接入全局控制信号GAS，源极接入所述第一电位，漏极电性连接所述输出端G(N）。
在一些实施例中，所述GOA电路在所述正常显示阶段之后还包括触控扫描阶段；
在所述触控扫描阶段，所述全局控制信号GAS控制所有级GOA单元的输出端G(N）转换为第一电位。
在一些实施例中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述全局控制信号GAS在所述复位阶段和所述正常显示阶段均为低电位，在所述触控扫描阶段为高电位。
在一些实施例中，在所述复位阶段和所述正常显示阶段，各条时钟信号均为周期性脉冲信号；在所述触控扫描阶段，各条时钟信号均为与触控扫描信号频率同步的脉冲信号。
在一些实施例中，所述GOA电路包括第一条时钟信号CK1和第二条时钟信号CK2；当所述第N条时钟信号CK（N）为第一条时钟信号CK1时，所述第N+1条时钟信号CK（N+1）为CK2；在所述复位阶段和所述正常显示阶段，所述第一条时钟信号CK1和所述第二条时钟信号CK2的周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟脉冲信号产生。
本申请实施例还提供一种显示面板，包括如上所述的GOA电路。该GOA电路包括级联的多个GOA单元，每一级所述GOA单元包括：正反扫描模块100、复位模块200、上拉模块300、下拉模块400、稳压模块500、防漏电模块500、稳压模块600、信号控制模块700和上拉维持模块800。
所述正反扫描模块100包括第一晶体管T1和第二晶体管T2，其中，所述第一晶体管T1的栅极接入上级GOA单元的输出端G(N-1），源极接入正向扫描信号U2D，漏极电性连接第一节点Qb；所述第二晶体管T2的栅极接入下级GOA单元的输出端G(N+1），源极接入反向扫描信号D2U，漏极电性连接第一节点Qb。
所述复位模块200包括第七晶体管T7，其中，所述第七晶体管T7的栅极和源极均接入复位信号Reset，漏极电性连接第二节点P。
所述上拉模块300包括第三晶体管T3，其中，所述第三晶体管T3的栅极电性连接上拉节点Qa，源极接入第N条时钟信号CK（N），漏极电性连接输出端G（N）。
所述下拉模块400包括第四晶体管T4和第十晶体管T10，其中，所述第四晶体管T4和所述第十晶体管T10的栅极均电性连接第二节点P，所述第四晶体管T4和所述第十晶体管T10的源极均接入第一电位，所述第四晶体管T4的漏极电性连接所述输出端G（N），所述第十晶体管T10的漏极电性连接所述第一节点Qb。
所述防漏电模块500包括第九晶体管T9，其中，所述第九晶体管T9的栅极接入所述第二电位，源极电性连接所述第一节点Qb，漏极电性连接所述上拉节点Qa。
所述稳压模块600包括第一电容C1和第二电容C2，其中，所述第一电容C1的一端电性连接所述第一节点Qb，另一端接入所述第一电位；所述第二电容C2的一端电性连接所述第二节点P，另一端接入所述第一电位。
所述信号控制模块700包括第五晶体管T5和第六晶体管T6，其中，所述第五晶体管T5的栅极电性连接所述第一节点Qb，源极接入所述第一电位，漏极电性连接所述第二节点P；所述第六晶体管T6的栅极接入第N+1条时钟信号CK（N+1），源极接入所述第二电位，漏极电性连接所述第二节点P。
所述上拉维持模块800包括第十一晶体管T11、第十二晶体管T12和第十三晶体管T13，其中，所述第十一晶体管T11的栅极和源极均接入所述第二电位，漏极电性连接第三节点K；所述第十二晶体管T12的栅极电性连接所述第三节点K，源极接入所述第二电位，漏极电性连接所述第一节点Qb；所述第十三晶体管T13的栅极电性连接所述第二节点P，源极接入所述第一电位，漏极电性连接所述第三节点K。
在一些实施例中，所述GOA电路具有复位阶段和正常显示阶段。
在所述复位阶段，所述复位信号Reset提供单个所述第二电位的脉冲信号控制所述第七晶体管T7打开使所述第二节点P为所述第二电位，所述第二节点P控制所述第四晶体管T4、第十晶体管T10和所述第十三晶体管T13打开使所述输出端G（N）、所述第一节点Qb、所述上拉节点Qa和所述第三节点K为所述第一电位。
所述正常显示阶段包括预充子阶段t1、输出子阶段t2和下拉子阶段t3。
在所述预充子阶段t1，所述上级GOA单元的输出端G(N-1)或所述下级GOA单元的输出端G(N+1)提供第二电平使所述第一晶体管T1或所述第二晶体管T2打开，以使所述第一节点Qb和所述上拉节点Qa转换为所述第二电位且所述第一电容C1被充电，同时使所述第三晶体管T3和所述第五晶体管T5打开；所述第五晶体管T5打开使所述第二节点P转换为第一电位以使所述第四晶体管T4、所述第十晶体管T10和所述第十三晶体管T13关闭。
在所述输出子阶段t2，所述上级GOA单元的输出端G(N-1)和所述下级GOA单元的输出端G(N+1)提供第一电平使所述第一晶体管T1和所述第二晶体管T2关闭，所述第一晶体管T1和所述第二晶体管T2关闭、所述第三晶体管T3打开使所述第一节点Qb保持为所述第二电位，所述上拉节点Qa的电位由所述第二电位转换为自举电位；同时，所述第N条时钟信号CK（N）提供所述第二电位并通过所述第三晶体管T3输出为所述输出端G（N）信号。
在所述预充子阶段t1和所述输出子阶段t2中，所述第十三晶体管T13关闭使所述第三节点K由所述第十一晶体管控制转换为所述第二电位，以使所述第十二晶体管T12打开而对所述第一节点Qb充电使所述第一节点Qb保持所述第二电位。
在所述下拉子阶段t3，上级GOA单元的输出端G(N-1)或下级GOA单元的输出端G(N+1)提供第二电位使第一晶体管T1或第二晶体管T2打开，正向扫描信号U2D或反向扫描信号D2U向第一节点Qb和上拉节点Qa提供第一电位，且所述第N+1条时钟信号CK（N+1）使所述第六晶体管T6打开以使所述第二节点P转换为所述第二电位且所述第二电容C2被充电，所述第二节点P使所述第四晶体管T4、所述第十晶体管T10和所述第十三晶体管T13打开以使所述输出端G（N）、所述第一节点Qb、所述上拉节点Qa和所述第三节点K转换为第一电位；所述第三节点K使所述第十二晶体管关闭而使所述第十二晶体管T12停止对所述第一节点Qb充电。
之后，所述第一电容C1使所述第一节点Qb和所述上拉节点Qa维持第一电位以使所述第三晶体管T3保持关闭，所述第二电容C2使所述第二节点P维持第二电位以使所述第四晶体管T4保持打开，所述输出端G（N）保持所述第一电位。
在一些实施例中，所述正向扫描信号U2D和所述反向扫描信号D2U中的一个信号为高电位且另一个信号为低电位。
正向扫描时所述上级GOA单元的输出端G(N-1）控制所述第一晶体管T1打开，首级GOA单元的第一晶体管T1的栅极接入起始信号STV。
反向扫描时所述下级GOA单元的输出端G(N+1）控制所述第二晶体管T2打开，末级GOA单元的第二晶体管T2的栅极接入所述起始信号STV。
在一些实施例中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述第一电位为恒压低电位VGL，所述第二电位为恒压高电位VGH。
在所述复位阶段，所述复位信号Reset提供单个高电位的脉冲信号使所述第二节点P为高电位，所述第一节点Qb、所述上拉节点Qa、所述第三节点K、所述正向扫描信号U2D、反向扫描信号D2U、所述第N条时钟信号CK（N）、所述第N+1条时钟信号CK（N+1）、所述输出端G(N)、所述上级GOA单元输出端G(N-1）和所述下级GOA单元输出端G(N+1）均为低电位。
在所述正常显示阶段的所述预充子阶段t1，正向扫描时所述正向扫描信号U2D为恒压高电位VGH且所述反向扫描信号D2U为恒压低电位VGL，反向扫描时所述正向扫描信号U2D为恒压低电位VGL且所述反向扫描信号D2U为恒压高电位VGH，所述第二节点P、所述第N条时钟信号CK（N）、所述第N+1条时钟信号CK（N+1）、所述输出端G(N)和所述下级GOA单元输出端（G+1）均为低电位，所述上级GOA单元输出端G(N-1）、所述第一节点Qb、所述上拉节点Qa和所述第三节点K均为高电位。
在所述正常显示阶段的所述输出子阶段t2，所述第二节点P、所述第N+1条时钟信号CK（N+1）、所述上级GOA单元输出端G(N-1）和所述下级GOA单元输出端G(N+1）均为低电位，所述第一节点Qb、所述上拉节点Qa、所述第三节点K、所述第N条时钟信号CK（N）和所述输出端G(N)均为高电位；
在所述正常显示阶段的所述下拉子阶段t3，所述第一节点Qb、所述上拉节点Qa、所述第三节点K、所述第N条时钟信号CK（N）、所述输出端G(N)和所述上级GOA单元的输出端G(N-1）均为低电位，所述第二节点P、所述第N+1条时钟信号CK（N+1）和所述下级GOA单元输出端G(N+1）均为高电位。
在一些实施例中，该GOA电路还包括输出控制模块900，所述输出控制模块900包括第八晶体管T8，所述第八晶体管T8的栅极接入全局控制信号GAS，源极接入所述第一电位，漏极电性连接所述输出端G(N）。
在一些实施例中，所述GOA电路在所述正常显示阶段之后还包括触控扫描阶段；
在所述触控扫描阶段，所述全局控制信号GAS控制所有级GOA单元的输出端G(N）转换为第一电位。
在一些实施例中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述全局控制信号GAS在所述复位阶段和所述正常显示阶段均为低电位，在所述触控扫描阶段为高电位。
在一些实施例中，在所述复位阶段和所述正常显示阶段，各条时钟信号均为周期性脉冲信号；在所述触控扫描阶段，各条时钟信号均为与触控扫描信号频率同步的脉冲信号。
在一些实施例中，所述GOA电路包括第一条时钟信号CK1和第二条时钟信号CK2；当所述第N条时钟信号CK（N）为第一条时钟信号CK1时，所述第N+1条时钟信号CK（N+1）为CK2；在所述复位阶段和所述正常显示阶段，所述第一条时钟信号CK1和所述第二条时钟信号CK2的周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟脉冲信号产生。
 有益效果
本申请提供的GOA电路，由于在正反扫描模块100和第一节点Qb之间设置了由第十一晶体管T11、第十二晶体管T12和第十三晶体管T13构成的上拉维持模块800，因此可以在正常显示阶段的预充子阶段t1和输出子阶段t2中，由于第一节点Qb为高电位拉低第二节点P使第十三晶体管T13关闭，从而使第三节点K由第十一晶体管T11控制转换为高电位，以使第十二晶体管T12打开而第一节点Qb保持第二电位，以及上拉节点Qa在预充子阶段t1保持第二电位、在输出子阶段t2保持自举电位。而在下拉子阶段t3，收到下拉信号下级GOA单元输出端G（N+1）时，第二节点P被置高使第十三晶体管T13打开，从而使第三节点K被拉低。这样第三节点K使第十二晶体管T12关闭而停止对第一节点Qb充电，不影响下拉过程。
 附图说明
图1为现有的一种GOA电路图。
图2为现有的一种GOA电路的理想时序图。
图3为现有的一种GOA电路的仿真时序图。
图4为本申请实施例的GOA电路图。
图5为本申请实施例的GOA电路的仿真时序图。
图6为holding时间为0秒时现有的GOA电路和本申请实施例的GOA电路中上拉节点Qa的仿真对比图。
图7为holding时间为200微秒时现有的GOA电路和本申请实施例的GOA电路中上拉节点Qa的仿真对比图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
参考图4，图4为本申请实施例提供的GOA电路，该GOA电路包括级联的多级GOA单元，每一级GOA单元包括：正反扫描模块100、复位模块200、上拉模块300、下拉模块400、稳压模块500、防漏电模块500、稳压模块600、信号控制模块700和上拉维持模块800。
其中，正反扫描模块100包括第一晶体管T1和第二晶体管T2，第一晶体管T1的栅极接入上级GOA单元的输出端G(N-1），源极接入正向扫描信号U2D，漏极电性连接第一节点Qb；第二晶体管T2的栅极接入下级GOA单元的输出端G(N+1），源极接入反向扫描信号D2U，漏极电性连接第一节点Qb。
复位模块200包括第七晶体管T7，第七晶体管T7的栅极和源极均接入复位信号Reset，漏极电性连接第二节点P。
上拉模块300包括第三晶体管T3，第三晶体管T3的栅极电性连接上拉节点Qa，源极接入第N条时钟信号CK（N），漏极电性连接输出端G（N）。
下拉模块400包括第四晶体管T4和第十晶体管T10，第四晶体管T4和第十晶体管T10的栅极均电性连接第二节点P，源极均接入第一电位，第四晶体管T4的漏极电性连接输出端G（N），第十晶体管T10的漏极电性连接第一节点Qb。
防漏电模块500包括第九晶体管T9，第九晶体管T9的栅极接入第二电位，源极电性连接第一节点Qb，漏极电性连接上拉节点Qa。
稳压模块600包括第一电容C1和第二电容C2，第一电容C1的一端电性连接第一节点Qb，另一端接入第一电位；第二电容C2的一端电性连接第二节点P，另一端接入第一电位。
信号控制模块700包括第五晶体管T5和第六晶体管T6，第五晶体管T5的栅极电性连接第一节点Qb，源极接入第一电位，漏极电性连接第二节点P；第六晶体管T6的栅极接入第N+1条时钟信号CK（N+1），源极接入第二电位，漏极电性连接第二节点P。
上拉维持模块800包括第十一晶体管T11、第十二晶体管T12和第十三晶体管T13，第十一晶体管T11的栅极和源极均接入第二电位，漏极电性连接第三节点K；第十二晶体管T12的栅极电性连接第三节点K，源极接入第二电位，漏极电性连接第一节点Qb；第十三晶体管T13的栅极电性连接第二节点P，源极接入第一电位，漏极电性连接第三节点K。
该GOA电路的工作过程先后具有复位阶段和正常显示阶段。
在复位阶段，复位信号Reset提供单个第二电位的脉冲信号控制第七晶体管T7打开使第二节点P为第二电位，第二节点P控制第四晶体管T4、第十晶体管T10和第十三晶体管T13打开使输出端G（N）、第一节点Qb、上拉节点Qa和第三节点K为第一电位。
正常显示阶段包括预充子阶段t1、输出子阶段t2和下拉子阶段t3。
在预充子阶段t1，上级GOA单元的输出端G(N-1)或下级GOA单元的输出端G(N+1)提供第二电平使第一晶体管T1或第二晶体管T2打开，以使第一节点Qb和上拉节点Qa转换为第二电位且第一电容C1被充电，同时使第三晶体管T3和第五晶体管T5打开；第五晶体管T5打开使第二节点P转换为第一电位以使第四晶体管T4、第十晶体管T10和第十三晶体管T13关闭。
在输出子阶段t2，上级GOA单元的输出端G(N-1)和下级GOA单元的输出端G(N+1)提供第一电平使第一晶体管T1和第二晶体管T2关闭，第一晶体管T1和第二晶体管T2关闭、第三晶体管T3打开使第一节点Qb保持为第二电位，上拉节点Qa的电位由第二电位转换为自举电位；同时，第N条时钟信号CK（N）提供第二电位并通过第三晶体管T3输出为输出端G（N）信号。
在预充子阶段t1和输出子阶段t2中，第十三晶体管T13关闭使第三节点K由第十一晶体管转换为第二电位，以使第十二晶体管T12打开而对第一节点Qb充电使第一节点Qb保持第二电位。
在下拉子阶段t3，上级GOA单元的输出端G(N-1)或下级GOA单元的输出端G(N+1)提供第二电位使第一晶体管T1或第二晶体管T2打开，正向扫描信号U2D或反向扫描信号D2U向第一节点Qb和上拉节点Qa提供第一电位，且第N+1条时钟信号CK（N+1）使第六晶体管T6打开以使第二节点P转换为第二电位且第二电容C2被充电，第二节点P使第四晶体管T4、第十晶体管T10和第十三晶体管T13打开以使输出端G（N）、第一节点Qb、上拉节点Qa和第三节点K转换为第一电位；第三节点K使第十二晶体管关闭而使第十二晶体管T12停止对第一节点Qb充电。
之后，第一电容C1使第一节点Qb和上拉节点Qa维持第一电位以使第三晶体管T3保持关闭，第二电容C2使第二节点P维持第二电位以使第四晶体管T4保持打开，输出端G（N）保持第一电位。
需要说明的是，正向扫描信号U2D和反向扫描信号D2U中的一个信号为高电位且另一个信号为低电位；正向扫描时上级GOA单元的输出端G(N-1）控制第一晶体管T1打开，首级GOA单元的第一晶体管T1的栅极接入起始信号STV（图5中未示出）；反向扫描时下级GOA单元的输出端G(N+1）控制第二晶体管T2打开，末级GOA单元的第二晶体管T2的栅极接入起始信号STV。
图5为本申请实施例的GOA电路的仿真时序图，图5对应的是GOA电路中的各个晶体管均为N型薄膜晶体管，第一电位为恒压低电位VGL，第二电位为恒压高电位VGH的情况。
正向扫描时正向扫描信号U2D为恒压高电位VGH且反向扫描信号D2U为恒压低电位VGL，反向扫描时正向扫描信号U2D为恒压低电位VGL且反向扫描信号D2U为恒压高电位VGH（图5中未示出），本申请实施例以正向扫描为例。
结合图4和图5，该GOA电路工作流程包括复位阶段和正常显示阶段，具体如下所述。
在复位阶段，复位信号Reset早于其他控制信号提供单个高电位的脉冲信号控制第七晶体管打开，从而使第二节点P为高电位，第二节点P控制第四晶体管T4、第十晶体管T10和第十三晶体管T13打开，从而将输出端G（N）、第一节点Qb、上拉节点Qa和第三节点K预拉低，使输出端G（N）的初始电位为恒压低电位VGL。之后复位信号Reset置低，第七晶体管T7关闭，等待正常显示阶段的到来。
正常显示阶段先后还包括预充子阶段t1、输出子阶段t2和下拉子阶段t3。
在预充子阶段t1：正向扫描时上级GOA单元的输出端G(N-1)提供高电平将第一晶体管T1打开，使第一节点Qb和上拉节点Qa被拉高到恒压高电位VGH，此时第一电容C1被充电，同时第三晶体管T3和第五晶体管T5打开；第五晶体管T5使第二节点P被拉低到恒压低电位VHL，从而使第四晶体管T4、第十晶体管T10和第十三晶体管T13关闭。
在输出子阶段t2，第N条时钟信号CKN为高电位，第三晶体管T3将第N条时钟信号CK（N）输出为输出端G（N）信号。此时，上级GOA单元的输出端G(N-1）和下级GOA单元的输出端G(N+1）均为低电位，第一晶体管T1和第二晶体管T2均关闭，而第三晶体管T3打开，第一节点Qb和上拉节点Qa没有泄电路径因此仍然保持高电位，并且，由于第三晶体管T3存在寄生电容，且输出端G（N）信号为高电位，上拉节点Qa因自举作用被拉得更高，由恒压高电位VGH升高到更高的自举电位。
在预充子阶段t1和输出子阶段t2中，第十三晶体管T13关闭使第三节点K由第十一晶体管T11控制转换为第二电位，以使第十二晶体管T12打开而使第一节点Qb保持第二电位。
需要说明的是，为了防止上拉节点Qa在被自举为高电位时上拉节点Qa的高电位被反灌到第一节点Q，因此在第一节点Q和上拉节点Qa之间设置防漏电模块500，防漏电模块500包括第十二晶体管T12，第十二晶体管T12的栅极接入恒压高电位VGH，使第十二晶体管T12保持打开状态，第一节点Qb为恒压高电位VGH时，第十二晶体管T12相当于由第一节点Qb向上拉节点Qa方向导通的二极管，防止当上拉节点Qa的高电位高于第一节点Qb的高电位时，上拉节点的电位反灌到第一节点Qb，从而维持上拉节点Qa自举的高电位。
在下拉子阶段t3，下级GOA单元的输出端G(N+1)提供高电位使第一晶体管T1或第二晶体管T2打开，反向扫描信号D2U向第一节点Qb和上拉节点Qa提供低电位，且第N+1条时钟信号CK（N+1）提供高电位使第六晶体管T6打开以使第二节点P拉高为恒压高电位VGH，此时，第二电容C2被充电，第二节点P使第四晶体管T4、第十晶体管T10和第十三晶体管T13打开，从而使输出端G（N）、第一节点Qb、上拉节点Qa和第三节点K被拉低为恒压低电位VGL。第三节点K被拉低使第十二晶体管T12关闭而停止对第一节点Qb充电。
之后，第一电容C1使第一节点Qb和上拉节点Qa维持恒压低电位VGL以使第三晶体管T3保持关闭，第二电容C2使第二节点P维持恒压高电位VGH以使第四晶体管T4保持打开，输出端G（N）保持恒压低电位VGL。
本申请实施例提供的GOA电路，由于在正反扫描模块100和第一节点Qb之间设置了由第十一晶体管T11、第十二晶体管T12和第十三晶体管T13构成的上拉维持模块800，因此可以在正常显示阶段的预充子阶段t1和输出子阶段t2中，由于第一节点Qb为高电位拉低第二节点P使第十三晶体管T13关闭，从而使第三节点K由第十一晶体管T11控制转换为高电位，以使第十二晶体管T12打开而第一节点Qb保持第二电位，以及上拉节点Qa在预充子阶段t1保持第二电位、在输出子阶段t2保持自举电位。而在下拉子阶段t3，收到下拉信号下级GOA单元输出端G（N+1）时，第二节点P被置高使第十三晶体管T13打开，从而使第三节点K被拉低。这样第三节点K使第十二晶体管T12关闭而停止对第一节点Qb充电，不影响下拉过程。
例如，将正常显示阶段中触控信号到来，holding时间分别为0秒和200微秒，上拉节点Qa在预充子阶段t1和输出子阶段t2的原输出波形（图3中上拉节点Qa的波形）和现输出波形（图5中上拉节点Qa的波形）进行对比得到图6和图7，图6为holding时间为0微秒现有的GOA电路和本申请实施例的GOA电路中上拉节点Qa的仿真对比图，图7为holding时间为200微秒时现有的GOA电路和本申请实施例的GOA电路中上拉节点Qa的仿真对比图，其中，虚曲线为上拉节点Qa的原输出波形，实曲线为上拉节点Qa的现输出波形。。
从图6和图7中可以看出，上拉节点Qa在预充子阶段t1和输出子阶段t2的现输出波形的幅值都比原输出波形高，原输出波形在预充子阶段t1的充电过程中明显乏力，在输出子阶段t2的自举电压也出现了电压下降的行为，且在holding时间较长的时候，上拉节点Qa一直在下降，下降幅值约为0.5V，对其自举电位也受到了影响。
参考图4，该GOA电路还包括输出控制模块900，输出控制模块900包括第八晶体管T8，第八晶体管T8的栅极接入全局控制信号GAS，源极接入第一电位，漏极电性连接输出端G(N）。
进一步地，GOA电路在正常显示阶段之后还包括触控扫描阶段；在触控扫描阶段，全局控制信号GAS控制所有级GOA单元的输出端G(N）转换为第一电位，此即为All gate off功能，该功能是为了在触控扫描阶段到来时关闭所有级GOA单元的输出端G(N)信号暂停级联，以防止扫描驱动信号和触控信号之间产生干扰。
可以理解的是，GOA电路中的各个晶体管均为N型薄膜晶体管，即第八晶体管T8为N型薄膜晶体管，则全局控制信号GAS在复位阶段和正常显示阶段均为低电位，在触控扫描阶段为高电位。
需要说明的是，在复位阶段和正常显示阶段，各条时钟信号均为周期性脉冲信号；在触控扫描阶段，各条时钟信号均为与触控扫描信号频率同步的脉冲信号。
还需要说明的是，GOA电路包括第一条时钟信号CK1和第二条时钟信号CK2；当第N条时钟信号CK（N）为第一条时钟信号CK1时，第N+1条时钟信号CK（N+1）为CK2；在复位阶段和正常显示阶段，第一条时钟信号CK1和第二条时钟信号CK2的周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟脉冲信号产生。
本申请实施例还提供一种显示面板，该显示面板包括如上所述的GOA电路，该显示面板具有与前述实施例提供的GOA电路相同的结构和有益效果。由于前述实施例已经对该GOA电路的结构和有益效果进行了详细的描述，此处不再赘述。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (18)

  1. 一种GOA电路，其包括级联的多个GOA单元，每一级所述GOA单元包括：正反扫描模块（100）、复位模块（200）、上拉模块（300）、下拉模块（400）、稳压模块（500）、防漏电模块（500）、稳压模块（600）、信号控制模块（700）和上拉维持模块（800）；
    所述正反扫描模块（100）包括第一晶体管（T1）和第二晶体管（T2），其中，所述第一晶体管（T1）的栅极接入上级GOA单元的输出端G(N-1），源极接入正向扫描信号（U2D），漏极电性连接第一节点（Qb）；所述第二晶体管（T2）的栅极接入下级GOA单元的输出端G（N+1），源极接入反向扫描信号（D2U），漏极电性连接第一节点（Qb）；
    所述复位模块（200）包括第七晶体管（T7），其中，所述第七晶体管（T7）的栅极和源极均接入复位信号（Reset），漏极电性连接第二节点（P）；
    所述上拉模块（300）包括第三晶体管（T3），其中，所述第三晶体管（T3）的栅极电性连接上拉节点（Qa），源极接入第N条时钟信号（CK（N）），漏极电性连接输出端（G（N））；
    所述下拉模块（400）包括第四晶体管（T4）和第十晶体管（T10），其中，所述第四晶体管（T4）和所述第十晶体管（T10）的栅极均电性连接第二节点（P），所述第四晶体管（T4）和所述第十晶体管（T10）的源极均接入第一电位，所述第四晶体管（T4）的漏极电性连接所述输出端（G（N）），所述第十晶体管（T10）的漏极电性连接所述第一节点（Qb）；
    所述防漏电模块（500）包括第九晶体管（T9），其中，所述第九晶体管（T9）的栅极接入第二电位，源极电性连接所述第一节点（Qb），漏极电性连接所述上拉节点（Qa）；
    所述稳压模块（600）包括第一电容C1和第二电容C2，其中，所述第一电容C1的一端电性连接所述第一节点（Qb），另一端接入所述第一电位；所述第二电容C2的一端电性连接所述第二节点（P），另一端接入所述第一电位；
    所述信号控制模块（700）包括第五晶体管（T5）和第六晶体管（T6），其中，所述第五晶体管（T5）的栅极电性连接所述第一节点（Qb），源极接入所述第一电位，漏极电性连接所述第二节点（P）；所述第六晶体管（T6）的栅极接入第N+1条时钟信号（CK（N+1）），源极接入所述第二电位，漏极电性连接所述第二节点（P）；
    所述上拉维持模块（800）包括第十一晶体管（T11）、第十二晶体管（T12）和第十三晶体管（T13），其中，所述第十一晶体管（T11）的栅极和源极均接入所述第二电位，漏极电性连接第三节点（K）；所述第十二晶体管（T12）的栅极电性连接所述第三节点（K），源极接入所述第二电位，漏极电性连接所述第一节点（Qb）；所述第十三晶体管（T13）的栅极电性连接所述第二节点（P），源极接入所述第一电位，漏极电性连接所述第三节点（K）。
  2. 如权利要求1所述的GOA电路，其中，所述GOA电路具有复位阶段和正常显示阶段；
    在所述复位阶段，所述复位信号（Reset）提供单个所述第二电位的脉冲信号控制所述第七晶体管（T7）打开使所述第二节点（P）为所述第二电位，所述第二节点（P）控制所述第四晶体管（T4）、第十晶体管（T10）和所述第十三晶体管（T13）打开使所述输出端（G（N））、所述第一节点（Qb）、所述上拉节点（Qa）和所述第三节点（K）为所述第一电位；
    所述正常显示阶段包括预充子阶段（t1）、输出子阶段（t2）和下拉子阶段（t3）；
    在所述预充子阶段（t1），所述上级GOA单元的输出端G(N-1)或所述下级GOA单元的输出端（G(N+1)）提供第二电平使所述第一晶体管（T1）或所述第二晶体管（T2）打开，以使所述第一节点（Qb）和所述上拉节点（Qa）转换为所述第二电位且所述第一电容C1被充电，同时使所述第三晶体管（T3）和所述第五晶体管（T5）打开；所述第五晶体管（T5）打开使所述第二节点（P）转换为第一电位以使所述第四晶体管（T4）、所述第十晶体管（T10）和所述第十三晶体管（T13）关闭；
    在所述输出子阶段（t2），所述上级GOA单元的输出端G(N-1)和所述下级GOA单元的输出端（G(N+1)）提供第一电平使所述第一晶体管（T1）和所述第二晶体管（T2）关闭，所述第一晶体管（T1）和所述第二晶体管（T2）关闭、所述第三晶体管（T3）打开使所述第一节点（Qb）保持为所述第二电位，所述上拉节点（Qa）的电位由所述第二电位转换为自举电位；同时，所述第N条时钟信号（CK（N））提供所述第二电位并通过所述第三晶体管（T3）输出为所述输出端（G（N））信号；
    在所述预充子阶段（t1）和所述输出子阶段（t2）中，所述第十三晶体管（T13）关闭使所述第三节点（K）由所述第十一晶体管控制转换为所述第二电位，以使所述第十二晶体管（T12）打开而对所述第一节点（Qb）充电使所述第一节点（Qb）保持所述第二电位；
    在所述下拉子阶段（t3），上级GOA单元的输出端G(N-1)或下级GOA单元的输出端（G(N+1)）提供第二电位使第一晶体管（T1）或第二晶体管（T2）打开，正向扫描信号（U2D）或反向扫描信号（D2U）向第一节点（Qb）和上拉节点（Qa）提供第一电位，且所述第N+1条时钟信号CK（N+1）使所述第六晶体管（T6）打开以使所述第二节点（P）转换为所述第二电位且所述第二电容C2被充电，所述第二节点（P）使所述第四晶体管（T4）、所述第十晶体管（T10）和所述第十三晶体管（T13）打开以使所述输出端（G（N））、所述第一节点（Qb）、所述上拉节点（Qa）和所述第三节点（K）转换为第一电位；所述第三节点（K）使所述第十二晶体管关闭而使所述第十二晶体管（T12）停止对所述第一节点（Qb）充电；
    之后，所述第一电容C1使所述第一节点（Qb）和所述上拉节点（Qa）维持第一电位以使所述第三晶体管（T3）保持关闭，所述第二电容C2使所述第二节点（P）维持第二电位以使所述第四晶体管（T4）保持打开，所述输出端（G（N））保持所述第一电位。
  3. 如权利要求2所述的GOA电路，其中，所述正向扫描信号（U2D）和所述反向扫描信号（D2U）中的一个信号为高电位且另一个信号为低电位；
    正向扫描时所述上级GOA单元的输出端G(N-1）控制所述第一晶体管（T1）打开，首级GOA单元的第一晶体管（T1）的栅极接入起始信号（STV）；
    反向扫描时所述下级GOA单元的输出端（G（N+1））控制所述第二晶体管（T2）打开，末级GOA单元的第二晶体管（T2）的栅极接入所述起始信号（STV）。
  4. 如权利要求2所述的GOA电路，其中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述第一电位为恒压低电位（VGL），所述第二电位为恒压高电位（VGH）；
    在所述复位阶段，所述复位信号（Reset）提供单个高电位的脉冲信号使所述第二节点（P）为高电位，所述第一节点（Qb）、所述上拉节点（Qa）、所述第三节点（K）、所述正向扫描信号（U2D）、反向扫描信号（D2U）、所述第N条时钟信号（CK（N））、所述第N+1条时钟信号（CK（N+1））、所述输出端（G（N））、所述上级GOA单元输出端（G(N-1））和所述下级GOA单元输出端G（N+1）均为低电位；
    在所述正常显示阶段的所述预充子阶段（t1），正向扫描时所述正向扫描信号（U2D）为恒压高电位（VGH）且所述反向扫描信号（D2U）为恒压低电位（VGL），反向扫描时所述正向扫描信号（U2D）为恒压低电位（VGL）且所述反向扫描信号（D2U）为恒压高电位（VGH），所述第二节点（P）、所述第N条时钟信号（CK（N））、所述第N+1条时钟信号CK（N+1）、所述输出端（G（N））和所述下级GOA单元输出端（G（N））均为低电位，所述上级GOA单元输出端G(N-1）、所述第一节点（Qb）、所述上拉节点（Qa）和所述第三节点（K）均为高电位；
    在所述正常显示阶段的所述输出子阶段（t2），所述第二节点（P）、所述第N+1条时钟信号（CK（N+1））所述上级GOA单元输出端（G(N-1））和所述下级GOA单元输出端（G（N+1））均为低电位，所述第一节点（Qb）、所述上拉节点（Qa）、所述第三节点（K）、所述第N条时钟信号（CK（N））和所述输出端（G（N））均为高电位；
    在所述正常显示阶段的所述下拉子阶段（t3），所述第一节点（Qb）、所述上拉节点（Qa）、所述第三节点（K）、所述第N条时钟信号（CK（N））、所述输出端（G(N)）和所述上级GOA单元的输出端（G(N-1））均为低电位，所述第二节点（P）、所述第N+1条时钟信号（CK（N+1））和所述下级GOA单元输出端（G（N+1））均为高电位。
  5. 如权利要求2所述的GOA电路，其中，所述GOA电路还包括输出控制模块（900），所述输出控制模块（900）包括第八晶体管（T8），所述第八晶体管（T8）的栅极接入全局控制信号（GAS），源极接入所述第一电位，漏极电性连接所述输出端（G（N））。
  6. 如权利要求5所述的GOA电路，其中，所述GOA电路在所述正常显示阶段之后还包括触控扫描阶段；
    在所述触控扫描阶段，所述全局控制信号（GAS）控制所有级GOA单元的输出端（G（N））转换为第一电位。
  7. 如权利要求6所述的GOA电路，其中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述全局控制信号（GAS）在所述复位阶段和所述正常显示阶段均为低电位，在所述触控扫描阶段为高电位。
  8. 如权利要求6所述的GOA电路，其中，在所述复位阶段和所述正常显示阶段，各条时钟信号均为周期性脉冲信号；在所述触控扫描阶段，各条时钟信号均为与触控扫描信号频率同步的脉冲信号。
  9. 如权利要求8所述的GOA电路，其中，所述GOA电路包括第一条时钟信号（CK1）和第二条时钟信号（CK2）；当所述第N条时钟信号（CK（N））为第一条时钟信号（CK1）时，所述第N+1条时钟信号（CK（N+1））为（CK2）；在所述复位阶段和所述正常显示阶段，所述第一条时钟信号（CK1）和所述第二条时钟信号（CK2）的周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟脉冲信号产生。
  10. 一种显示面板，其中，包括GOA电路，所述GOA电路包括级联的多个GOA单元；
    每一级所述GOA单元包括：正反扫描模块（100）、复位模块（200）、上拉模块（300）、下拉模块（400）、稳压模块（500）、防漏电模块（500）、稳压模块（600）、信号控制模块（700）和上拉维持模块（800）；
    所述正反扫描模块（100）包括第一晶体管（T1）和第二晶体管（T2），其中，所述第一晶体管（T1）的栅极接入上级GOA单元的输出端G(N-1），源极接入正向扫描信号（U2D），漏极电性连接第一节点（Qb）；所述第二晶体管（T2）的栅极接入下级GOA单元的输出端G（N+1），源极接入反向扫描信号（D2U），漏极电性连接第一节点（Qb）；
    所述复位模块（200）包括第七晶体管（T7），其中，所述第七晶体管（T7）的栅极和源极均接入复位信号（Reset），漏极电性连接第二节点（P）；
    所述上拉模块（300）包括第三晶体管（T3），其中，所述第三晶体管（T3）的栅极电性连接上拉节点（Qa），源极接入第N条时钟信号（CK（N）），漏极电性连接输出端（G（N））；
    所述下拉模块（400）包括第四晶体管（T4）和第十晶体管（T10），其中，所述第四晶体管（T4）和所述第十晶体管（T10）的栅极均电性连接第二节点（P），所述第四晶体管（T4）和所述第十晶体管（T10）的源极均接入第一电位，所述第四晶体管（T4）的漏极电性连接所述输出端（G（N）），所述第十晶体管（T10）的漏极电性连接所述第一节点（Qb）；
    所述防漏电模块（500）包括第九晶体管（T9），其中，所述第九晶体管（T9）的栅极接入第二电位，源极电性连接所述第一节点（Qb），漏极电性连接所述上拉节点（Qa）；
    所述稳压模块（600）包括第一电容C1和第二电容C2，其中，所述第一电容C1的一端电性连接所述第一节点（Qb），另一端接入所述第一电位；所述第二电容C2的一端电性连接所述第二节点（P），另一端接入所述第一电位；
    所述信号控制模块（700）包括第五晶体管（T5）和第六晶体管（T6），其中，所述第五晶体管（T5）的栅极电性连接所述第一节点（Qb），源极接入所述第一电位，漏极电性连接所述第二节点（P）；所述第六晶体管（T6）的栅极接入第N+1条时钟信号（CK（N+1）），源极接入所述第二电位，漏极电性连接所述第二节点（P）；
    所述上拉维持模块（800）包括第十一晶体管（T11）、第十二晶体管（T12）和第十三晶体管（T13），其中，所述第十一晶体管（T11）的栅极和源极均接入所述第二电位，漏极电性连接第三节点（K）；所述第十二晶体管（T12）的栅极电性连接所述第三节点（K），源极接入所述第二电位，漏极电性连接所述第一节点（Qb）；所述第十三晶体管（T13）的栅极电性连接所述第二节点（P），源极接入所述第一电位，漏极电性连接所述第三节点（K）。
  11. 如权利要求10所述的显示面板，其中，所述GOA电路具有复位阶段和正常显示阶段；
    在所述复位阶段，所述复位信号（Reset）提供单个所述第二电位的脉冲信号控制所述第七晶体管（T7）打开使所述第二节点（P）为所述第二电位，所述第二节点（P）控制所述第四晶体管（T4）、第十晶体管（T10）和所述第十三晶体管（T13）打开使所述输出端（G（N））、所述第一节点（Qb）、所述上拉节点（Qa）和所述第三节点（K）为所述第一电位；
    所述正常显示阶段包括预充子阶段（t1）、输出子阶段（t2）和下拉子阶段（t3）；
    在所述预充子阶段（t1），所述上级GOA单元的输出端G(N-1)或所述下级GOA单元的输出端（G(N+1)）提供第二电平使所述第一晶体管（T1）或所述第二晶体管（T2）打开，以使所述第一节点（Qb）和所述上拉节点（Qa）转换为所述第二电位且所述第一电容C1被充电，同时使所述第三晶体管（T3）和所述第五晶体管（T5）打开；所述第五晶体管（T5）打开使所述第二节点（P）转换为第一电位以使所述第四晶体管（T4）、所述第十晶体管（T10）和所述第十三晶体管（T13）关闭；
    在所述输出子阶段（t2），所述上级GOA单元的输出端G(N-1)和所述下级GOA单元的输出端（G(N+1)）提供第一电平使所述第一晶体管（T1）和所述第二晶体管（T2）关闭，所述第一晶体管（T1）和所述第二晶体管（T2）关闭、所述第三晶体管（T3）打开使所述第一节点（Qb）保持为所述第二电位，所述上拉节点（Qa）的电位由所述第二电位转换为自举电位；同时，所述第N条时钟信号（CK（N））提供所述第二电位并通过所述第三晶体管（T3）输出为所述输出端（G（N））信号；
    在所述预充子阶段（t1）和所述输出子阶段（t2）中，所述第十三晶体管（T13）关闭使所述第三节点（K）由所述第十一晶体管控制转换为所述第二电位，以使所述第十二晶体管（T12）打开而对所述第一节点（Qb）充电使所述第一节点（Qb）保持所述第二电位；
    在所述下拉子阶段（t3），上级GOA单元的输出端G(N-1)或下级GOA单元的输出端（G(N+1)）提供第二电位使第一晶体管（T1）或第二晶体管（T2）打开，正向扫描信号（U2D）或反向扫描信号（D2U）向第一节点（Qb）和上拉节点（Qa）提供第一电位，且所述第N+1条时钟信号CK（N+1）使所述第六晶体管（T6）打开以使所述第二节点（P）转换为所述第二电位且所述第二电容C2被充电，所述第二节点（P）使所述第四晶体管（T4）、所述第十晶体管（T10）和所述第十三晶体管（T13）打开以使所述输出端（G（N））、所述第一节点（Qb）、所述上拉节点（Qa）和所述第三节点（K）转换为第一电位；所述第三节点（K）使所述第十二晶体管关闭而使所述第十二晶体管（T12）停止对所述第一节点（Qb）充电；
    之后，所述第一电容C1使所述第一节点（Qb）和所述上拉节点（Qa）维持第一电位以使所述第三晶体管（T3）保持关闭，所述第二电容C2使所述第二节点（P）维持第二电位以使所述第四晶体管（T4）保持打开，所述输出端（G（N））保持所述第一电位。
  12. 如权利要求11所述的显示面板，其中，所述正向扫描信号（U2D）和所述反向扫描信号（D2U）中的一个信号为高电位且另一个信号为低电位；
    正向扫描时所述上级GOA单元的输出端G(N-1）控制所述第一晶体管（T1）打开，首级GOA单元的第一晶体管（T1）的栅极接入起始信号（STV）；
    反向扫描时所述下级GOA单元的输出端（G（N+1））控制所述第二晶体管（T2）打开，末级GOA单元的第二晶体管（T2）的栅极接入所述起始信号（STV）。
  13. 如权利要求11所述的显示面板，其中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述第一电位为恒压低电位（VGL），所述第二电位为恒压高电位（VGH）；
    在所述复位阶段，所述复位信号（Reset）提供单个高电位的脉冲信号使所述第二节点（P）为高电位，所述第一节点（Qb）、所述上拉节点（Qa）、所述第三节点（K）、所述正向扫描信号（U2D）、反向扫描信号（D2U）、所述第N条时钟信号（CK（N））、所述第N+1条时钟信号（CK（N+1））、所述输出端（G（N））、所述上级GOA单元输出端（G(N-1））和所述下级GOA单元输出端G（N+1）均为低电位；
    在所述正常显示阶段的所述预充子阶段（t1），正向扫描时所述正向扫描信号（U2D）为恒压高电位（VGH）且所述反向扫描信号（D2U）为恒压低电位（VGL），反向扫描时所述正向扫描信号（U2D）为恒压低电位（VGL）且所述反向扫描信号（D2U）为恒压高电位（VGH），所述第二节点（P）、所述第N条时钟信号（CK（N））、所述第N+1条时钟信号CK（N+1）、所述输出端（G（N））和所述下级GOA单元输出端（G（N））均为低电位，所述上级GOA单元输出端G(N-1）、所述第一节点（Qb）、所述上拉节点（Qa）和所述第三节点（K）均为高电位；
    在所述正常显示阶段的所述输出子阶段（t2），所述第二节点（P）、所述第N+1条时钟信号（CK（N+1））所述上级GOA单元输出端（G(N-1））和所述下级GOA单元输出端（G（N+1））均为低电位，所述第一节点（Qb）、所述上拉节点（Qa）、所述第三节点（K）、所述第N条时钟信号（CK（N））和所述输出端（G（N））均为高电位；
    在所述正常显示阶段的所述下拉子阶段（t3），所述第一节点（Qb）、所述上拉节点（Qa）、所述第三节点（K）、所述第N条时钟信号（CK（N））、所述输出端（G(N)）和所述上级GOA单元的输出端（G(N-1））均为低电位，所述第二节点（P）、所述第N+1条时钟信号（CK（N+1））和所述下级GOA单元输出端（G（N+1））均为高电位。
  14. 如权利要求11所述的显示面板，其中，所述GOA电路还包括输出控制模块（900），所述输出控制模块（900）包括第八晶体管（T8），所述第八晶体管（T8）的栅极接入全局控制信号（GAS），源极接入所述第一电位，漏极电性连接所述输出端（G（N））。
  15. 如权利要求14所述的显示面板，其中，所述GOA电路在所述正常显示阶段之后还包括触控扫描阶段；
    在所述触控扫描阶段，所述全局控制信号（GAS）控制所有级GOA单元的输出端（G（N））转换为第一电位。
  16. 如权利要求15所述的显示面板，其中，所述GOA电路中的各个晶体管均为N型薄膜晶体管，所述全局控制信号（GAS）在所述复位阶段和所述正常显示阶段均为低电位，在所述触控扫描阶段为高电位。
  17. 如权利要求15所述的显示面板，其中，在所述复位阶段和所述正常显示阶段，各条时钟信号均为周期性脉冲信号；在所述触控扫描阶段，各条时钟信号均为与触控扫描信号频率同步的脉冲信号。
  18. 如权利要求17所述的显示面板，其中，所述GOA电路包括第一条时钟信号（CK1）和第二条时钟信号（CK2）；当所述第N条时钟信号（CK（N））为第一条时钟信号（CK1）时，所述第N+1条时钟信号（CK（N+1））为（CK2）；在所述复位阶段和所述正常显示阶段，所述第一条时钟信号（CK1）和所述第二条时钟信号（CK2）的周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟脉冲信号产生。
PCT/CN2020/086024 2020-04-07 2020-04-22 Goa 电路及显示面板 WO2021203485A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/966,032 US11749166B2 (en) 2020-04-07 2020-04-22 GOA circuit and display panel thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010264553.3A CN111326096A (zh) 2020-04-07 2020-04-07 Goa电路及显示面板
CN202010264553.3 2020-04-07

Publications (1)

Publication Number Publication Date
WO2021203485A1 true WO2021203485A1 (zh) 2021-10-14

Family

ID=71167857

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/086024 WO2021203485A1 (zh) 2020-04-07 2020-04-22 Goa 电路及显示面板

Country Status (3)

Country Link
US (1) US11749166B2 (zh)
CN (1) CN111326096A (zh)
WO (1) WO2021203485A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115691393A (zh) * 2022-11-14 2023-02-03 惠科股份有限公司 栅极驱动电路及显示装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111754950A (zh) * 2020-07-10 2020-10-09 武汉华星光电技术有限公司 Goa电路、显示面板和显示装置
US11238823B1 (en) 2020-07-30 2022-02-01 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit, display panel and display device
KR20220034470A (ko) * 2020-09-11 2022-03-18 엘지디스플레이 주식회사 스캔 드라이버 및 이를 포함하는 유기 발광 표시 장치
CN112527149A (zh) * 2020-12-14 2021-03-19 福建华佳彩有限公司 一种提升显示稳定性的gip电路及驱动方法
CN112735321B (zh) * 2021-01-12 2024-04-05 福建华佳彩有限公司 一种提高显示屏驱动电流的电路及驱动方法
CN113077741B (zh) * 2021-03-16 2022-05-17 武汉华星光电技术有限公司 Goa电路及显示面板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040111016A (ko) * 2003-06-16 2004-12-31 미쓰비시덴키 가부시키가이샤 표시 장치 및 표시 제어 회로
CN106128392A (zh) * 2016-08-29 2016-11-16 武汉华星光电技术有限公司 Goa驱动电路和嵌入式触控显示面板
CN106128354A (zh) * 2016-09-12 2016-11-16 武汉华星光电技术有限公司 平面显示装置及其扫描驱动电路
CN106297636A (zh) * 2016-09-12 2017-01-04 武汉华星光电技术有限公司 平面显示装置及其扫描驱动电路
CN106898319A (zh) * 2017-02-20 2017-06-27 武汉华星光电技术有限公司 一种goa电路及液晶显示面板
US9711098B2 (en) * 2014-12-02 2017-07-18 Samsung Display Co., Ltd. Display apparatus with dummy pixel row and method of driving the display apparatus
CN109300428A (zh) * 2018-11-28 2019-02-01 武汉华星光电技术有限公司 Goa电路及显示面板
CN109461402A (zh) * 2019-01-07 2019-03-12 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102708778B (zh) * 2011-11-28 2014-04-23 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN103050106B (zh) * 2012-12-26 2015-02-11 京东方科技集团股份有限公司 栅极驱动电路、显示模组和显示器
JP2015041235A (ja) * 2013-08-21 2015-03-02 株式会社ジャパンディスプレイ タッチパネル付液晶表示装置
CN105047119B (zh) * 2014-05-02 2018-01-30 乐金显示有限公司 移位寄存器及使用该移位寄存器的显示装置
CN104464662B (zh) 2014-11-03 2017-01-25 深圳市华星光电技术有限公司 基于低温多晶硅半导体薄膜晶体管的goa电路
KR101679923B1 (ko) * 2014-12-02 2016-11-28 엘지디스플레이 주식회사 스캔 구동부를 포함하는 표시패널 및 그의 구동방법
CN105161134B (zh) * 2015-10-09 2018-10-23 京东方科技集团股份有限公司 移位寄存器单元及其操作方法、移位寄存器
CN105206244B (zh) * 2015-10-29 2017-10-17 武汉华星光电技术有限公司 一种goa电路及液晶显示器
CN105469760B (zh) * 2015-12-17 2017-12-29 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN105489180B (zh) * 2016-01-04 2018-06-01 武汉华星光电技术有限公司 Goa电路
CN105469766B (zh) * 2016-01-04 2019-04-30 武汉华星光电技术有限公司 Goa电路
CN105513550B (zh) * 2016-01-04 2019-02-01 武汉华星光电技术有限公司 Goa驱动电路
CN105427830A (zh) * 2016-01-12 2016-03-23 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105679262B (zh) * 2016-01-12 2017-08-29 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105976781B (zh) * 2016-07-14 2018-08-14 武汉华星光电技术有限公司 Goa电路
CN108319385B (zh) * 2016-12-23 2021-06-25 鸿富锦精密工业（深圳）有限公司 移位寄存器及具有移位寄存器的触控显示装置
CN106782389A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 一种阵列基板行驱动电路
CN109410811B (zh) * 2017-08-17 2020-11-06 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
JP2019090927A (ja) * 2017-11-15 2019-06-13 シャープ株式会社 走査信号線駆動回路およびそれを備えた表示装置
CN108399906B (zh) * 2018-05-25 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN108766380B (zh) * 2018-05-30 2020-05-29 武汉华星光电技术有限公司 Goa电路
KR102666646B1 (ko) * 2018-06-08 2024-05-20 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치
CN108665846B (zh) * 2018-07-13 2022-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN108962168A (zh) * 2018-07-24 2018-12-07 武汉华星光电技术有限公司 单型goa电路
CN109036304B (zh) * 2018-07-26 2020-09-08 武汉华星光电技术有限公司 一种goa电路、显示面板及显示装置
CN110415664B (zh) * 2019-08-01 2021-10-08 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
KR102628945B1 (ko) * 2020-12-10 2024-01-24 엘지디스플레이 주식회사 게이트 구동 회로, 디스플레이 장치 및 디스플레이 장치의 구동 방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040111016A (ko) * 2003-06-16 2004-12-31 미쓰비시덴키 가부시키가이샤 표시 장치 및 표시 제어 회로
US9711098B2 (en) * 2014-12-02 2017-07-18 Samsung Display Co., Ltd. Display apparatus with dummy pixel row and method of driving the display apparatus
CN106128392A (zh) * 2016-08-29 2016-11-16 武汉华星光电技术有限公司 Goa驱动电路和嵌入式触控显示面板
CN106128354A (zh) * 2016-09-12 2016-11-16 武汉华星光电技术有限公司 平面显示装置及其扫描驱动电路
CN106297636A (zh) * 2016-09-12 2017-01-04 武汉华星光电技术有限公司 平面显示装置及其扫描驱动电路
CN106898319A (zh) * 2017-02-20 2017-06-27 武汉华星光电技术有限公司 一种goa电路及液晶显示面板
CN109300428A (zh) * 2018-11-28 2019-02-01 武汉华星光电技术有限公司 Goa电路及显示面板
CN109461402A (zh) * 2019-01-07 2019-03-12 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115691393A (zh) * 2022-11-14 2023-02-03 惠科股份有限公司 栅极驱动电路及显示装置
CN115691393B (zh) * 2022-11-14 2024-01-23 惠科股份有限公司 栅极驱动电路及显示装置

Also Published As

Publication number Publication date
US20230154376A1 (en) 2023-05-18
US11749166B2 (en) 2023-09-05
CN111326096A (zh) 2020-06-23

Similar Documents

Publication Publication Date Title
WO2021203485A1 (zh) Goa 电路及显示面板
WO2020019381A1 (zh) 一种goa电路、显示面板及显示装置
KR102178652B1 (ko) Goa 회로
WO2020019379A1 (zh) 一种goa电路、显示面板及显示装置
WO2018171133A1 (zh) 移位寄存器单元、栅极驱动电路以及驱动方法
WO2019210830A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
JP5535374B2 (ja) 走査信号線駆動回路およびそれを備えた表示装置
WO2016188287A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2018028009A1 (zh) Goa电路
US10121442B2 (en) Driving methods and driving devices of gate driver on array (GOA) circuit
JP2018088301A (ja) 単位シフトレジスタ回路、シフトレジスタ回路、単位シフトレジスタ回路の制御方法及び表示装置
JP2020517994A (ja) 走査駆動回路
KR20090004201A (ko) 액정 표시 장치 및 그의 구동 방법
CN106504721B (zh) 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
WO2017107294A1 (zh) Goa电路及液晶显示装置
WO2021120449A1 (zh) Goa器件及显示面板
WO2020107949A1 (zh) Goa电路及显示面板
CN110007628B (zh) Goa电路及显示面板
WO2020133823A1 (zh) Goa电路
CN112102768B (zh) Goa电路及显示面板
CN110264940B (zh) 驱动电路
WO2021012313A1 (zh) 栅极驱动电路
WO2020107658A1 (zh) Goa电路和显示面板
WO2021159586A1 (zh) 一种goa电路及其显示面板
WO2020048081A1 (zh) Goa 电路及液晶面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20930163

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20930163

Country of ref document: EP

Kind code of ref document: A1