WO2021190183A1 - 像素电路及其驱动方法、显示基板和显示装置 - Google Patents

像素电路及其驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2021190183A1
WO2021190183A1 PCT/CN2021/075716 CN2021075716W WO2021190183A1 WO 2021190183 A1 WO2021190183 A1 WO 2021190183A1 CN 2021075716 W CN2021075716 W CN 2021075716W WO 2021190183 A1 WO2021190183 A1 WO 2021190183A1
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terminal
voltage
control
light
sub
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PCT/CN2021/075716
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English (en)
French (fr)
Inventor
丛宁
玄明花
张粲
杨明
王灿
张盎然
陈昊
陈小川
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US17/433,244 priority Critical patent/US11663955B2/en
Publication of WO2021190183A1 publication Critical patent/WO2021190183A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B44/00—Circuit arrangements for operating electroluminescent light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate and a display device.
  • Miniature inorganic light-emitting diodes that is, light-emitting diode miniaturization and matrix technology, refers to a high-density, small-size light-emitting diode array integrated on a chip. Miniature inorganic light-emitting diodes have received extensive attention due to their high brightness, high efficiency, fast response time, small size, long life and many other advantages.
  • the embodiment of the present disclosure provides a pixel circuit, including: a light-emitting device, a current supply sub-circuit, and a time control sub-circuit, wherein:
  • the current supply sub-circuit is connected to the scan signal terminal, the data signal terminal, the light-emitting control terminal, the first power supply voltage terminal, the time control sub-circuit and the light-emitting device, and is configured to receive the data voltage of the data signal terminal and provide the light-emitting device.
  • the device provides drive current
  • the time control sub-circuit is connected to the scan signal terminal, the duration signal terminal, the second power supply voltage terminal, the DC signal control terminal and the DC voltage terminal, and is configured to receive the duration voltage of the duration signal terminal and the DC input from the DC voltage terminal Voltage, and according to the duration voltage and the direct current voltage, control the duration of the current supply sub-circuit to communicate with the light-emitting device, so as to control the light-emitting duration of the light-emitting device.
  • the time control sub-circuit includes a first signal writing module and a duration control module, wherein:
  • the first signal writing module is connected to the scan signal terminal, the duration signal terminal, the second power supply voltage terminal, and the duration control module, and is configured to, under the control of the scan signal terminal, set the The duration voltage of the duration signal terminal is input to the duration control module;
  • the duration control module is connected to the DC signal control terminal, the DC voltage terminal, and the current supply sub-circuit, and is configured to receive the DC voltage of the DC voltage terminal under the control of the DC signal control terminal, according to The duration voltage and the direct current voltage control the duration of the current supply sub-circuit to communicate with the light-emitting device to control the light-emitting duration of the light-emitting device.
  • the duration control module includes a voltage input module and a switch module, wherein:
  • the voltage input module is connected to the DC signal control terminal, the DC voltage terminal, the first signal writing module, and the switch module, and is configured to transfer the DC signal under the control of the DC signal control terminal.
  • the DC voltage at the voltage terminal is input to the switch module;
  • the switch module is connected to the first signal writing module, the current supply sub-circuit, and the voltage input module, and is configured to receive the duration voltage, and control the duration voltage according to the duration voltage and the direct current voltage.
  • the duration of communication between the current supply sub-circuit and the light-emitting device is used to control the light-emitting duration of the light-emitting device.
  • the voltage input module includes at least two voltage input sub-units
  • the DC signal control terminal includes at least two sub-DC signal control terminals
  • the DC voltage terminal includes at least two sub-DC voltage terminals
  • Each of the voltage input sub-units corresponds to a sub-DC signal control terminal and a sub-DC voltage terminal;
  • each voltage input subunit is connected to the sub DC signal control end corresponding to the voltage input subunit, the second end is connected to the sub DC voltage end corresponding to the voltage input subunit, and the third The terminal is connected with the switch module.
  • each of the voltage input subunits includes a transistor
  • the control terminal of the transistor is connected to the sub DC signal control terminal, the first pole is connected to the sub DC voltage terminal, and the second pole is connected to the switch module.
  • the switch module includes a first transistor and a first capacitor, wherein:
  • the control terminal of the first transistor is connected to one end of the first capacitor and the first signal writing module, and the first pole and the second pole are connected to the current supply sub-circuit;
  • the other end of the first capacitor is connected to the voltage input module.
  • the first signal writing module includes a second transistor and a third transistor, wherein:
  • the control terminal of the second transistor is connected to the scan signal terminal, the first electrode is connected to the duration signal terminal, and the second electrode is connected to the duration control module;
  • the control terminal of the third transistor is connected to the scan signal terminal, the first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the duration control module.
  • the current supply sub-circuit includes a second signal writing module, a light emitting control module, and a driving module, wherein:
  • the second signal writing module is connected to the scan signal terminal, the data signal terminal, the time control sub-circuit and the driving module, and is configured to transfer the data signal under the control of the scan signal terminal.
  • the data voltage of the terminal is input to the driving module;
  • the light-emitting control module is connected to the light-emitting control terminal, the first power supply voltage terminal, the second signal writing module, the drive module, the time control sub-circuit and the light-emitting device, and is set to Under the control of the light-emitting control terminal, connecting the first power supply voltage terminal to the driving module, and connecting the time control sub-circuit to the light-emitting device;
  • the driving module is connected to the first power supply voltage terminal, the light-emitting control module and the second signal writing module, and is configured to provide a driving current to the light-emitting device.
  • the second signal writing module includes a fourth transistor and a fifth transistor, wherein:
  • the control terminal of the fourth transistor is connected to the scan signal terminal, the first electrode is connected to the data signal terminal, and the second electrode is connected to the light emitting control module and the driving module;
  • the control terminal of the fifth transistor is connected to the scan signal terminal, the first pole is connected to the driving module, and the second pole is connected to the time control sub-circuit and the driving module.
  • the driving module includes a sixth transistor and a second capacitor, wherein:
  • the control terminal of the sixth transistor is connected to the second signal writing module, the first pole is connected to the second signal writing module and the light-emitting control module, and the second pole is connected to the time control sub-circuit and the The second signal writing module;
  • One end of the second capacitor is connected to the first power supply voltage terminal, and the other end is connected to the second signal writing module and the control terminal of the sixth transistor.
  • the light emission control module includes a seventh transistor and an eighth transistor, wherein:
  • the control terminal of the seventh transistor is connected to the light-emitting control terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the driving module and the second signal writing module;
  • the control terminal of the eighth transistor is connected to the light emitting control terminal, the first electrode is connected to the light emitting device, and the second electrode is connected to the time control sub-circuit.
  • the pixel circuit further includes a reset module connected to a reset signal terminal, an initial voltage terminal, and the current supply sub-circuit, and is configured to, under the control of the reset signal terminal, set the initial The initial voltage of the voltage terminal is input to the current supply sub-circuit to initialize the current supply sub-circuit.
  • a reset module connected to a reset signal terminal, an initial voltage terminal, and the current supply sub-circuit, and is configured to, under the control of the reset signal terminal, set the initial The initial voltage of the voltage terminal is input to the current supply sub-circuit to initialize the current supply sub-circuit.
  • the reset module includes a ninth transistor
  • the control terminal of the ninth transistor is connected to the reset signal terminal, the first electrode is connected to the initial voltage terminal, and the second electrode is connected to the current supply sub-circuit.
  • An embodiment of the present disclosure provides a display substrate including a plurality of pixel units arranged in an array, and each of the pixel units includes the pixel circuit illustrated in the foregoing embodiments.
  • An embodiment of the present disclosure provides a display device, including the display substrate illustrated in the foregoing embodiment.
  • the embodiment of the present disclosure provides a method for driving a pixel circuit, which is used for the pixel circuit illustrated in the foregoing embodiment, and includes:
  • the direct-current voltage input from the direct-current voltage terminal is received, and the current supply sub-circuit and the light-emitting circuit are controlled according to the duration voltage and the direct-current voltage.
  • the duration of the device connection is used to control the light-emitting duration of the light-emitting device.
  • the data voltage of the data signal terminal is input to the current supply sub-circuit, and the duration voltage of the duration signal terminal is input to the time control sub-circuit.
  • the circuit Before the circuit, it also includes:
  • the initial voltage of the initial voltage terminal is input to the current supply sub-circuit to initialize the current supply sub-circuit.
  • Figure 1 is a circuit diagram of a full-screen sequential pixel circuit
  • FIG. 2 is a timing diagram of the pixel circuit of FIG. 1;
  • FIG. 3 is a block diagram of a pixel circuit provided by an embodiment of the disclosure.
  • 4-6 are specific block diagrams of a pixel circuit provided by embodiments of the disclosure.
  • FIG. 7 is a circuit diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 8 is a timing diagram of the pixel circuit of FIG. 7;
  • FIG. 9 is a circuit diagram of another pixel circuit provided by an example of the present disclosure.
  • FIG. 10 is a timing diagram of the pixel circuit of FIG. 9;
  • Figure 11 is a GOA circuit diagram that provides the timing signals of Figure 10;
  • FIG. 12 is a circuit diagram of a pixel circuit provided by an embodiment of the disclosure in a reset phase
  • FIG. 13 is a circuit diagram of a pixel circuit provided by an embodiment of the disclosure in a data writing stage
  • FIG. 14 is a circuit diagram of a pixel circuit provided by an embodiment of the disclosure in the first light-emitting stage
  • 15 is a circuit diagram of a pixel circuit provided by an embodiment of the disclosure in a second light-emitting stage
  • 16 is a circuit diagram of a pixel circuit provided by an embodiment of the disclosure in a third light-emitting stage
  • FIG. 17 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the disclosure.
  • Figure 1 shows a pixel circuit for driving current-type light-emitting elements
  • Figure 2 is a timing diagram of the pixel circuit shown in Figure 1, where the current-type Light-emitting elements include organic electroluminescent diodes or miniature inorganic light-emitting diodes.
  • the data voltage VdataI of the data signal terminal DataI controls the working state of the driving transistor T2, thereby controlling the working current of the miniature inorganic light-emitting diode D; when the transistor T4 is turned on (GateB is low), the capacitance of the capacitor C2 One end is written with the duration voltage VdataT of the duration signal terminal DataT, and the other end is written with the voltage Vramp of the voltage terminal Ramp.
  • Vramp is a voltage signal that changes with time. For example, as shown in Figure 2, when Vramp decreases, the gate voltage of transistor T5 will decrease. When the turn-on condition of transistor T5 is reached, transistor T5 is turned on and the miniature inorganic light-emitting diode emits light. Therefore, different VdataTs correspond to different on-times, so that the current-type light-emitting elements produce different brightness.
  • the voltage terminals Ramp in the pixel circuit for driving each pixel are connected together, that is, all pixels receive a uniform Vramp signal, and the same column
  • the data signal terminals DataI of the pixel circuits are connected together, and the duration signal terminals DataT of the pixel circuits of the same column are connected together.
  • the data voltage VdataI and the duration voltage VdataT are input to each row of pixel circuits in turn, and then the light-emitting control terminals (
  • the light emission control signal (EM) output by the EM) becomes an effective level signal, and at the same time the voltage Vramp provided by the voltage terminal Ramp also starts to change with time, that is, all pixels emit light at the same time.
  • the inventor found that one of the problems of the above-mentioned driving method is that it cannot correspond to a high-resolution display panel, because the writing time of the data voltage VdataI and the duration voltage VdataT is 2H, where 1H means that a row of pixels is used for writing the data voltage or duration voltage.
  • the value ranges from a few microseconds to tens of microseconds.
  • the total writing time needs to be multiplied by the number of rows of the pixel unit, so that only the data voltage VdataI and the duration voltage VdataT are written in a few milliseconds to ten milliseconds.
  • Inorganic light-emitting diodes have little time left to emit light. Therefore, the pixel circuits and their driving timings shown in Figures 1 and 2 can only correspond to low-resolution products.
  • the embodiments of the present disclosure provide a new pixel circuit and a driving method thereof, and provide a mature micro-inorganic light-emitting diode display driving solution, which can correspond to high-resolution products.
  • the embodiment of the present disclosure provides a pixel circuit, including: a light-emitting device, a current supply sub-circuit, and a time control sub-circuit, wherein:
  • the current supply sub-circuit is connected to the scan signal terminal, the data signal terminal, the light-emitting control terminal, the first power supply voltage terminal, the time control sub-circuit and the light-emitting device, and is set to receive the data voltage of the data signal terminal and provide a driving current for the light-emitting device;
  • the time control sub-circuit is connected to the scanning signal terminal, the duration signal terminal, the second power supply voltage terminal, the DC signal control terminal and the DC voltage terminal, and is set to receive the duration voltage of the duration signal terminal and the DC voltage input from the DC voltage terminal, and according to the duration voltage and The direct current voltage controls the length of time that the current supply sub-circuit is connected with the light-emitting device to control the light-emitting time of the light-emitting device.
  • the embodiment of the present disclosure can control the light-emitting device to always work in a high current density area through the current supply sub-circuit, that is, work in a stable device efficiency area;
  • the time control sub-circuit can control the duration of the connection between the current supply sub-circuit and the light-emitting device to control the light-emitting duration of the light-emitting device. Therefore, the embodiments of the present disclosure can jointly realize the gray-scale display of the light-emitting device by combining the two control methods of current and duration.
  • the different light-emitting durations of the embodiments of the present disclosure correspond to different gray levels of the light-emitting devices.
  • the light-emitting device in the embodiment of the present disclosure is a miniature inorganic light-emitting diode, because the pixel circuit in the embodiment of the present disclosure can control the light-emitting device to always work in a high current density region through a current supply sub-circuit, and can pass current and duration.
  • the two control methods are combined to realize the grayscale display of the light-emitting device. Therefore, the pixel circuit in the embodiment of the present disclosure effectively avoids the luminous efficiency of the miniature inorganic light-emitting diode from changing with the current density at low current density. And the color coordinate also changes with the change of current density.
  • the pixel circuit provided by the embodiment of the present disclosure includes a light-emitting device 10, a current supply sub-circuit 11, and a time control sub-circuit 12;
  • the current supply sub-circuit 11 is connected to the scanning signal terminal (Gate), the data signal terminal (DataI), the light-emitting control terminal (EM), the first power supply voltage terminal (DD), the time control sub-circuit 12 and the light-emitting device 10, and is set to receive
  • the data voltage VdataI of the data signal terminal (DataI) provides a driving current for the light emitting device 10;
  • the time control sub-circuit 12 is connected to the scanning signal terminal (Gate), the duration signal terminal (DataT), the second power supply voltage terminal (COM), the DC signal control terminal (S) and the DC voltage terminal (D), and is set to receive the duration signal The duration voltage VdataT of the terminal (DataT) and the DC voltage input from the DC voltage terminal (D), according to the duration voltage VdataT and the DC voltage, control the duration of the connection between the current supply sub-circuit 11 and the light-emitting device 10 (that is, the control current supply sub-circuit 11 and The duration of connection and conduction of the light-emitting device 10) to control the light-emitting duration of the light-emitting device 10.
  • the pixel circuit provided by the embodiment of the present disclosure includes a current supply sub-circuit 11 and a time control sub-circuit 12.
  • the embodiment of the present disclosure can control the light-emitting device 10 to always work in a high current density region through the current supply sub-circuit 11, that is, when the device efficiency is stable. Area; since the time control sub-circuit 12 can control the duration of the current supply sub-circuit 11 and the light-emitting device 10 to control the light-emitting duration of the light-emitting device 10, the embodiments of the present disclosure can be implemented by combining the current and duration control methods
  • the gray scale of the light emitting device 10 shows that different light emitting durations in the embodiment of the present disclosure correspond to different gray scales of the light emitting device.
  • the time control sub-circuit 12 includes a first signal writing module 121 and a duration control module 122, wherein:
  • the first signal writing module 121 is connected to the scan signal terminal (Gate), the duration signal terminal (DataT), the second power supply voltage terminal (COM) and the duration control module 122, and is set to be under the control of the scan signal terminal (Gate), Input the duration voltage VdataT of the duration signal terminal (DataT) into the duration control module 122;
  • the duration control module 122 is connected to the DC signal control terminal (S), the DC voltage terminal (D) and the current supply sub-circuit 11, and is set to receive the DC signal from the DC voltage terminal (D) under the control of the DC signal control terminal (S).
  • the voltage according to the duration voltage VdataT and the DC voltage, controls the duration of the connection between the current supply sub-circuit 11 and the light-emitting device 10 to control the light-emitting duration of the light-emitting device 10.
  • the duration control module 122 includes a voltage input module 1221 and a switch module 1222, wherein:
  • the voltage input module 1221 is connected to the DC signal control terminal (S), the DC voltage terminal (D), the first signal writing module 121 and the switch module 1222, and is set to transfer the DC voltage under the control of the DC signal control terminal (S) The DC voltage at the end (D) is input to the switch module 1222;
  • the switch module 1222 is connected to the first signal writing module 121, the current supply sub-circuit 11 and the voltage input module 1221, and is set to receive the duration voltage VdataT, and controls the current supply sub-circuit 11 to communicate with the light emitting device 10 according to the duration voltage VdataT and the DC voltage To control the light-emitting time of the light-emitting device 10.
  • the voltage input module 1221 includes at least two voltage input subunits 12211, and the DC signal control terminal (S) includes at least two sub DC signal control terminals, as shown in FIG. n sub-DC signal control terminals (S1, S2...Sn), the direct-current voltage terminal (D) includes at least two sub-direct-current voltage terminals, Figure 6 shows n sub-direct-current voltage terminals (D1, D2...Dn);
  • Each voltage input sub-unit 12211 corresponds to a sub-DC signal control terminal and a sub-DC voltage terminal; and the first terminal of each voltage input sub-unit 12211 is connected to the corresponding sub-DC signal control terminal of the voltage input sub-unit 12211, The second terminal is connected to the sub-DC voltage terminal corresponding to the voltage input sub-unit 12211, and the third terminal is connected to the switch module 1222.
  • the current supply sub-circuit 11 includes a second signal writing module 111, a light emitting control module 112, and a driving module 113;
  • the second signal writing module 111 is connected to the scanning signal terminal (Gate), the data signal terminal (DataI), the time control sub-circuit 12 and the driving module 113, and is set to transfer the data signal terminal under the control of the scanning signal terminal (Gate).
  • the data voltage VdataI of (DataI) is input to the driving module 113;
  • the light emitting control module 112 is connected to the light emitting control terminal (EM), the first power supply voltage terminal (DD), the second signal writing module 111, the driving module 113, the time control sub-circuit 12 and the light emitting device 10, and is arranged at the light emitting control terminal Under the control of (EM), connect the first power supply voltage terminal (DD) to the driving module 113, and connect the time control sub-circuit 12 to the light emitting device 10;
  • the driving module 113 is connected to the first power supply voltage terminal (DD), the light emitting control module 112 and the second signal writing module 111, and is configured to provide a driving current to the light emitting device 10.
  • the pixel circuit of the embodiment of the present disclosure may further include a reset module 13, which is connected to a reset signal terminal (RST), an initial voltage terminal (Int), and a current supply sub-circuit 11. It is set to input the initial voltage Vint of the initial voltage terminal (Int) into the current supply sub-circuit 11 under the control of the reset signal terminal (RST), so that the current supply sub-circuit 11 is initialized.
  • a reset module 13 which is connected to a reset signal terminal (RST), an initial voltage terminal (Int), and a current supply sub-circuit 11. It is set to input the initial voltage Vint of the initial voltage terminal (Int) into the current supply sub-circuit 11 under the control of the reset signal terminal (RST), so that the current supply sub-circuit 11 is initialized.
  • the initialization phase is the time period between adjacent image frames, and this time period is used to eliminate the residual image of the previous frame. For any image frame, it will go through a progressive scan from the first row of raster lines to the last row of raster lines. Therefore, the initialization phase occurs after the last row of raster lines of the previous image frame is scanned and the last row of pixels is displayed to the next Before the raster line of the first row of an image frame starts to scan.
  • the pixel circuit provided by the embodiment of the present disclosure includes a second signal writing module 111, a light emission control module 112, a driving module 113, a reset module 13, and a first signal writing module.
  • FIG. 8 is a timing diagram of the pixel circuit shown in FIG.
  • the voltage input module 1221 includes at least two voltage input subunits, and each voltage input subunit includes a transistor.
  • FIG. 7 shows that the voltage input module 1221 includes n Voltage input subunit, the first voltage input subunit includes transistor T10, the second voltage input subunit includes transistor T11, the third voltage input subunit includes transistor T12, and the nth voltage input subunit includes transistor T(n +9).
  • Each voltage input sub-unit corresponds to a sub-DC signal control terminal and a sub-DC voltage terminal, as shown in Figure 7, the first voltage input sub-unit corresponds to the sub-DC signal control terminal (S1) and the sub-DC voltage terminal (D1) , The second voltage input subunit corresponds to the sub DC signal control terminal (S2) and the sub DC voltage terminal (D2), and the third voltage input subunit corresponds to the sub DC signal control terminal (S3) and the sub DC voltage terminal (D3).
  • the n voltage input subunits correspond to the sub DC signal control terminal (Sn) and the sub DC voltage terminal (Dn).
  • the control terminal of the transistor T10 is connected to the DC signal control terminal (S1), the first pole is connected to the DC voltage terminal (D1), and the second pole is connected to the switch module 1222;
  • the control terminal of the transistor T11 is connected to the DC signal Control terminal (S2), the first pole is connected to the DC voltage terminal (D2), the second pole is connected to the switch module 1222;
  • the control terminal of the transistor T12 is connected to the DC signal control terminal (S3), and the first pole is connected to the DC voltage terminal ( D3), the second pole is connected to the switch module 1222;
  • the control terminal of the transistor T(n+9) is connected to the sub-DC signal control terminal (Sn), the first pole is connected to the sub-DC voltage terminal (Dn), and the second pole is connected to the switch module 1222 .
  • the switch module 1222 includes a first transistor T8 and a first capacitor C2; the control terminal of the first transistor T8 is connected to one end of the first capacitor C2 and the first signal writing module 121 ,
  • the first pole and the second pole are connected to the current supply sub-circuit, wherein the second pole is connected to the second signal writing module 111 and the driving module 113 included in the current supply sub-circuit, and the first pole is connected to the light emission control included in the current supply sub-circuit Module 112; the other end of the first capacitor C2 is connected to the voltage input module 1221.
  • the first signal writing module 121 includes a second transistor T7 and a third transistor T9; the control terminal of the second transistor T7 is connected to the scan signal terminal (Gate), and the first electrode Connected to the duration signal terminal (DataT), the second pole is connected to the switch module 1222 included in the duration control module 122; the control terminal of the third transistor T9 is connected to the scan signal terminal (Gate), and the first pole is connected to the second power supply voltage terminal (COM),
  • the second pole connection duration control module 122 includes a switch module 1222 and a voltage input module 1221.
  • the second signal writing module 111 includes a fourth transistor T2 and a fifth transistor T3; the control terminal of the fourth transistor T2 is connected to the scan signal terminal (Gate), and the first terminal Connect the data signal terminal (DataI), the second pole is connected to the light-emitting control module 112 and the driving module 113; the control terminal of the fifth transistor T3 is connected to the scanning signal terminal (Gate), and the first pole is connected to the driving module 113 and the reset module 13 (optional ), the second pole is connected to the switch module 1222 and the drive module 113 included in the time control sub-circuit 12.
  • the driving module 113 includes a sixth transistor T4 and a second capacitor C1; the control end of the sixth transistor T4 is connected to the second signal writing module 111 and the reset module 13 (optional ), the first pole is connected to the second signal writing module 111 and the light-emitting control module 112, the second pole is connected to the switch module 1222 and the second signal writing module 111 included in the time control sub-circuit 12; one end of the second capacitor C1 is connected to the One end of the power supply voltage (DD), the other end is connected to the second signal writing module 111, the reset module 13 (optional) and the control end of the sixth transistor T4.
  • DD power supply voltage
  • the emission control module 112 includes a seventh transistor T5 and an eighth transistor T6; the control terminal of the seventh transistor T5 is connected to the emission control terminal (EM), and the first pole is connected to the first transistor.
  • the time control sub-circuit 12 includes a switch module 1222.
  • the reset module 13 includes a ninth transistor T1, the control terminal of the ninth transistor T1 is connected to the reset signal terminal (RST), and the first electrode is connected to the initial voltage terminal (Int), The second pole is connected to the driving module 113 and the second signal writing module 111 included in the current supply sub-circuit 11.
  • the light emitting device 10 in the embodiment of the present disclosure may be a miniature inorganic light emitting diode.
  • the eighth transistor T6, the ninth transistor T1, the transistor T10, the transistor T11, the transistor T12, and the transistor T(n+9) are all P-type transistors; of course, in actual circuit design, these transistors can also be N-type transistors.
  • the disclosed embodiments do not limit the types of transistors.
  • the first electrode of these transistors can be the source and the second electrode can be the drain. Of course, the first electrode can also be the drain, and the second electrode can also be the source. In actual design, the first electrode of these transistors It can be interchanged with the second pole.
  • the pixel circuit provided by the embodiment of the present disclosure includes a scan signal terminal (Gate), an emission control terminal (EM), a data signal terminal (DataI), a duration signal terminal (DataT), and a first power supply voltage terminal (DD).
  • control terminal of the first transistor T8 is connected to the first terminal of the first capacitor C2 and the second terminal of the second transistor T7, the first terminal is connected to the second terminal of the eighth transistor T6, and the first terminal is connected to the second terminal of the eighth transistor T6.
  • the two poles are connected to the second pole of the fifth transistor T3 and the second pole of the sixth transistor T4.
  • the control terminal of the second transistor T7 is connected to the scan signal terminal (Gate), the first electrode is connected to the duration signal terminal (DataT), and the second electrode is connected to the control terminal of the first transistor T8 and the first terminal of the first capacitor C2.
  • the control terminal of the third transistor T9 is connected to the scan signal terminal (Gate), the first electrode is connected to the second power supply voltage terminal (COM), and the second electrode is connected to the second terminal of the first capacitor C2.
  • the control end of the fourth transistor T2 is connected to the scan signal end (Gate), the first electrode is connected to the data signal end (DataI), and the second electrode is connected to the second electrode of the seventh transistor T5 and the first electrode of the sixth transistor T4.
  • the control end of the fifth transistor T3 is connected to the scan signal end (Gate), the first electrode is connected to the control end of the sixth transistor T4, the second end of the second capacitor C1 and the second electrode of the ninth transistor T1, and the second electrode is connected to the The second pole of a transistor T8 and the second pole of a sixth transistor T4.
  • the control terminal of the sixth transistor T4 is connected to the second terminal of the second capacitor C1, the second terminal of the ninth transistor T1 and the first terminal of the fifth transistor T3, and the first terminal is connected to the second terminal of the fourth transistor T2 and the seventh terminal.
  • the second electrode and the second electrode of the transistor T5 are connected to the second electrode of the fifth transistor T3 and the second electrode of the first transistor T8.
  • the control terminal of the seventh transistor T5 is connected to the light emission control terminal (EM), the first terminal is connected to the first power supply voltage terminal (DD), and the second terminal is connected to the second terminal of the fourth transistor T2 and the first terminal of the sixth transistor T4.
  • the control terminal of the eighth transistor T6 is connected to the light emitting control terminal (EM), the first electrode is connected to the light emitting device 10, and the second electrode is connected to the first electrode of the first transistor T8.
  • the control terminal of the ninth transistor T1 is connected to the reset signal terminal (RST), the first electrode is connected to the initial voltage terminal (Int), and the second electrode is connected to the second terminal of the second capacitor C1, the control terminal of the sixth transistor T4, and the fifth terminal.
  • the control terminal of the transistor T10 is connected to the DC signal control terminal (S1), the first pole is connected to the DC voltage terminal (D1), the second pole is connected to the second terminal of the first capacitor C2; the control terminal of the transistor T11 is connected to the DC signal control Terminal (S2), the first pole is connected to the DC voltage terminal (D2), the second pole is connected to the second terminal of the first capacitor C2; the control terminal of the transistor T12 is connected to the DC signal control terminal (S3), the first pole is connected The second terminal of the DC voltage terminal (D3) is connected to the second terminal of the first capacitor C2.
  • FIG. 10 is a timing diagram of the pixel circuit shown in FIG. 9.
  • the timing signal of FIG. 10 can be provided by the GOA circuit shown in FIG. 11.
  • the GOA circuit includes a multi-stage cascaded shift register. , ESTV, SSTV1, SSTV2, and SSTV3 are the input signals of the GOA circuit.
  • the output signal corresponding to the GSTV signal is the signal of the scanning signal terminal (Gate)
  • the output signal corresponding to the ESTV signal is the signal of the light-emitting control terminal (EM)
  • the SSTV1 signal corresponds to
  • the output signal is the signal of the sub-DC signal control terminal S3
  • the output signal corresponding to the SSTV2 signal is the signal of the sub-DC signal control terminal S2
  • the output signal corresponding to the SSTV3 signal is the signal of the sub-DC signal control terminal S1. The working process will not be repeated here.
  • the working process of the pixel circuit provided by the embodiment of the present disclosure includes a reset phase, a data writing phase, and a light emitting phase.
  • the light emitting device 10 in this embodiment is a miniature inorganic light emitting diode.
  • the reset signal terminal (RST) outputs a low-level signal
  • the scanning signal terminal (Gate) the light-emitting control terminal (EM), the sub-DC signal control terminal (S1), and the sub-DC signal control
  • the terminal (S2) and the sub-DC signal control terminal (S3) both output high-level signals, as shown in Figure 12.
  • the ninth transistor T1 is turned on, and the rest of the transistors are turned off.
  • the potential of the two plates of the second capacitor C1 is The first pole is connected to the initial voltage Vint of the initial voltage terminal (Int) and the power supply voltage VDD of the first power supply voltage terminal (DD) for initialization, and the initialization can make the pixel circuit in a certain initial state.
  • the scan signal terminal (Gate) outputs a low-level signal
  • the reset signal terminal (RST) the light-emitting control terminal (EM), the sub-DC signal control terminal (S1), and the sub-DC
  • the signal control terminal (S2) and the sub-DC signal control terminal (S3) both output high-level signals, as shown in FIG.
  • the fourth transistor T2, the fifth transistor T3, the sixth transistor T4, the second transistor T7, and the third transistor T9 is turned on, the other transistors are all off, the data voltage VdataI of the data signal terminal (DataI) is written, and the voltage at point N1 is VdataI+the threshold voltage Vth of the sixth transistor T4; and the duration voltage VdataT of the duration signal terminal (DataT) Write, the voltage at point N2 is VdataT, and the duration voltage VdataT is stored in the first capacitor C2.
  • the light-emitting stage of the pixel circuit provided in this embodiment includes three stages.
  • the light-emitting control terminal (EM) and the sub-DC signal control terminal (S1) output low-level signals.
  • the scan signal terminal (Gate), reset signal terminal (RST), sub-DC signal control terminal (S2) and sub-DC signal control terminal (S3) all output high-level signals; in the second light-emitting stage, the light-emitting control terminal (EM ) And the sub-DC signal control terminal (S2) output low-level signals, and the scan signal terminal (Gate), reset signal terminal (RST), sub-DC signal control terminal (S1) and sub-DC signal control terminal (S3) all output high-voltage Level signal; in the third light-emitting stage, the light-emitting control terminal (EM) and the sub-DC signal control terminal (S3) output low-level signals, the scan signal terminal (Gate), the reset signal terminal (RST), and the sub-DC signal control terminal ( S1) and the sub-DC signal control terminal (S2) both output high-level signals.
  • the sixth transistor T4 In the first light-emitting stage, as shown in FIG. 14, the sixth transistor T4, the seventh transistor T5, the eighth transistor T6, and the transistor T10 are turned on, the state of the first transistor T8 is pending, and the remaining transistors are all turned off. In the current control part, the sixth transistor T4 generates the working current I DS of the miniature inorganic light emitting diode:
  • ⁇ represents the mobility of the material of the sixth transistor T4
  • Cox represents the capacitance value of the sixth transistor T4
  • W represents the width of the sixth transistor T4
  • L represents the length of the sixth transistor T4. Therefore, this embodiment emits light in the first
  • the working current IDS of the micro-inorganic light-emitting diode is independent of the threshold voltage Vth of the sixth transistor T4, and will not affect the light emission of the micro-inorganic light-emitting diode.
  • the second terminal of the first capacitor C2 is connected to the sub-DC voltage terminal (D1).
  • the voltage at point N2 is bootstrapped to VdataT+V1- VCOM, if the voltage at point N2 VdataT+V1-VCOM makes the first transistor T8 meet the turn-on condition V GS ⁇ Vth8, and Vth8 is the threshold voltage of the first transistor T8, the first transistor T8 is turned on and the miniature inorganic light-emitting diode starts to emit light. If the voltage VdataT+V1-VCOM at point N2 cannot satisfy the turn-on condition of the first transistor T8, the miniature inorganic light-emitting diode does not emit light during the period when the sub-DC signal control terminal (S1) outputs a low-level signal.
  • the sixth transistor T4 In the second light-emitting stage, as shown in FIG. 15, the sixth transistor T4, the seventh transistor T5, the eighth transistor T6, and the transistor T11 are turned on, the state of the first transistor T8 is pending, and the remaining transistors are all turned off.
  • the current control part is the same as the first light-emitting stage, and will not be repeated here.
  • the time control part since the transistor T11 is turned on, the second terminal of the first capacitor C2 is connected to the sub-DC voltage terminal (D2).
  • the voltage at point N2 is bootstrapped to VdataT+V2- VCOM, if the voltage at point N2 VdataT+V2-VCOM makes the first transistor T8 meet the turn-on condition V GS ⁇ Vth8, the first transistor T8 is turned on and the miniature inorganic light-emitting diode continues to emit light. If the voltage at point N2 VdataT+V2-VCOM cannot be satisfied When the first transistor T8 is turned on, the miniature inorganic light-emitting diode does not emit light during the period when the sub-DC signal control terminal (S2) outputs a low-level signal.
  • S2 sub-DC signal control terminal
  • the sixth transistor T4, the seventh transistor T5, the eighth transistor T6, and the transistor T12 are turned on, the state of the first transistor T8 is to be determined, and the remaining transistors are all turned off.
  • the current control part is the same as the first light-emitting stage, and will not be repeated here.
  • the time control part since the transistor T12 is turned on, the second terminal of the first capacitor C2 is connected to the sub-DC voltage terminal (D3).
  • the voltage at point N2 is bootstrapped to VdataT+V3- VCOM, if the N2 point voltage VdataT+V3-VCOM makes the first transistor T8 meet the turn-on condition V GS ⁇ Vth8, then the first transistor T8 is turned on and the miniature inorganic light-emitting diode continues to emit light. If the N2 point voltage VdataT+V3-VCOM cannot be satisfied When the first transistor T8 is turned on, the miniature inorganic light-emitting diode does not emit light during the period when the sub-DC signal control terminal (S3) outputs a low-level signal.
  • S3 sub-DC signal control terminal
  • the data voltage VdataI is used to control the miniature inorganic light-emitting diode to always work in the high current density region, that is, to work in the device efficiency stable region, and then the transistor T10, the transistor T11, and the transistor T12 are turned on in sequence, and the first capacitor C2 is turned on.
  • the two terminals are respectively connected with DC voltage V1, DC voltage V2 and DC voltage V3, the first terminal of the second capacitor C2 will be bootstrapped to the corresponding voltage, thereby controlling the conduction state of the first transistor T8, and then controlling the miniature inorganic light-emitting diode
  • the two control methods of current and duration are combined to realize the grayscale display of the micro-inorganic light-emitting diode.
  • the pixel circuit of the embodiment of the present disclosure compensates for the defects of the micro-inorganic light-emitting diode light-emitting device itself through time length control.
  • sub-DC voltage terminals D1, D2, D3, and the transmitted DC voltages V1, V2, V3 are voltages of fixed amplitude, and the light-emitting device 10 realizes different gray levels mainly provided by the fixed-duration signal terminal (DataT) The duration is determined by the voltage VdataT.
  • the voltage condition that V1 needs to meet is: V1 is greater than or equal to Vs-VdataT+VCOM+Vth8, and the voltage conditions that V2 and V3 need to meet are the same as the conditions that V1 needs to meet.
  • the middle gray scale state of the brightest gray scale state and the darkest gray scale state can also be achieved when both the micro-inorganic light-emitting diodes in the first and second light-emitting stages emit light, and the micro-inorganic light-emitting diodes in the third light-emitting stage do not emit light.
  • the embodiments of the present disclosure only need to ensure There is at least one light-emitting stage that emits light, and the three light-emitting stages do not emit light at the same time to realize the intermediate grayscale state of the miniature inorganic light-emitting diode.
  • the voltage condition that V1 needs to meet is: V1 is greater than or equal to zero and less than or equal to Vs-VdataT+VCOM+Vth8.
  • the voltage condition that V2 needs to meet is: V2 is greater than or equal to Vs-VdataT+VCOM+Vth8, and the voltage condition that V3 needs to meet is the same as that of V2.
  • V1, V2, and V3 can be set to be unequal in amplitude under the condition that V1, V2, and V3 meet the above-mentioned voltage range, such as V1, V2, and V3.
  • the value of V3 can be set in a manner of increasing or decreasing sequentially.
  • the duration of the effective level (ie, low level) of the sub DC signal control terminal S1, the sub DC signal control terminal S2, and the sub DC signal control terminal S3 can be set to be equal, or can be set Because the three are not equal, there is no specific relationship between the three, as long as the total effective level duration of S1, S2 and S3 is less than or equal to [display panel one frame display duration-(the reset duration of each row of pixel units (that is, the reset signal effective level time )+the data writing duration of each row of pixel units (that is, the gate signal effective level time)].
  • the data signal terminals DataI of the pixel circuit of the same column are connected together, and the duration signal terminals DataT of the pixel circuit of the same column are connected together.
  • Embodiment DC voltage V1, DC voltage V2, and DC voltage V3 are DC signals shared by the entire screen, and the timing of the sub-DC signal control terminal S1, the sub-DC signal control terminal S2, and the sub-DC signal control terminal S3 is used to select and connect to the pixel circuit Since the sub-DC signal control terminal (S1), the sub-DC signal control terminal (S2) and the sub-DC signal control terminal (S3) are provided by a set of GOA circuits, the pixel circuit provided in the embodiments of the present disclosure can realize the pixel Row by row light emission, that is, after the data voltage VdataI and the duration voltage VdataT of a row of pixels are written, the row of pixels directly
  • the pixel circuit provided by the embodiment of the present disclosure can also emit light at the same time for all pixels. After the data voltage VdataI and the duration voltage VdataT of all pixels are written, all pixels start to emit light.
  • the writing time of each row of pixel data voltage VdataI and duration voltage VdataT is 1H, which only takes more than ten microseconds, and there is no need to wait for the full-screen data voltage VdataI and duration voltage.
  • VdataT emits light after being written, so the pixel circuit provided in the embodiments of the present disclosure can be applied to high-resolution products.
  • embodiments of the present disclosure also provide a display substrate, which includes a plurality of pixel units arranged in an array, and each pixel unit includes the pixel circuit illustrated in the foregoing embodiments. Since the display substrate includes the pixel circuit provided by the foregoing embodiment of the present disclosure, the display substrate provided by the embodiment of the present disclosure has the same beneficial effects as the pixel circuit, and will not be repeated here.
  • embodiments of the present disclosure also provide a display device, including the display substrate shown in the foregoing embodiments. Since the display device includes the display substrate provided in the foregoing embodiment of the present disclosure, the display device provided by the embodiment of the present disclosure has the same beneficial effects as the display substrate, and will not be repeated here.
  • an embodiment of the present disclosure also provides a driving method of a pixel circuit.
  • a flowchart of the driving method is shown in FIG. 17, and the method includes:
  • the method further includes: S101.
  • the initial voltage of the initial voltage terminal is input to the current supply sub-circuit to initialize the current supply sub-circuit.
  • the pixel circuit provided by the embodiment of the present disclosure is under the control of the scan signal terminal, the data voltage input current of the data signal terminal is supplied to the sub-circuit, and the duration voltage of the duration signal terminal is input into the time control sub-circuit; Under control, the DC voltage input from the DC voltage terminal is received, and according to the duration voltage and the DC voltage, the duration of the connection between the current supply sub-circuit and the light-emitting device is controlled to control the light-emitting duration of the light-emitting device.
  • the embodiment of the present disclosure can control the light emitting device to always work in a high current density area, that is, work in a stable device efficiency area through the data voltage; the embodiment of the present disclosure can realize the grayscale display of the light emitting device by combining the current and duration control methods.
  • the embodiment of the present disclosure can control the light-emitting device to always work in a high current density region through the current supply sub-circuit, that is, work in a stable device efficiency. Area; because the time control sub-circuit can control the duration of the current supply sub-circuit and the light-emitting device to control the light-emitting duration of the light-emitting device, therefore, the embodiment of the present disclosure can realize the gray of the light-emitting device through the combination of current and duration control methods.
  • the level display shows that different light-emitting durations in the embodiments of the present disclosure correspond to different gray levels of the light-emitting device.
  • the light-emitting device in the embodiment of the present disclosure is a miniature inorganic light-emitting diode. Because the pixel circuit in the embodiment of the present disclosure can control the light-emitting device to always work in a high current density area through a current supply sub-circuit, and can pass both current and duration. The combination of these control methods together realizes the grayscale display of the light-emitting device. Therefore, the pixel circuit in the embodiment of the present disclosure effectively prevents the luminous efficiency of the miniature inorganic light-emitting diode from changing with the current density under low current density, and the color The coordinate also changes with the current density.
  • the data voltage VdataI controls the miniature inorganic light-emitting diode to always work in the high current density area, that is, the device efficiency stable area, and then the transistor T10, the transistor T11, and the transistor T12 are turned on in sequence, the first capacitor
  • the second terminal of C2 is connected to DC voltage V1, DC voltage V2, and DC voltage V3 respectively.
  • the first terminal of the second capacitor C2 will be bootstrapped to the corresponding voltage to control the conduction state of the first transistor T8 to achieve Controlling the light-emitting duration of the micro-inorganic light-emitting diode finally realizes the combination of current and time control methods to realize the gray-scale display of the micro-inorganic light-emitting diode.
  • the pixel circuit of the embodiment of the present disclosure compensates for the micro-inorganic light-emitting diode light-emitting device through time control. Its own flaws.
  • the DC voltage V1, DC voltage V2, and DC voltage V3 of the embodiments of the present disclosure are DC signals shared by the entire screen. ) To select the DC voltage connected to the pixel circuit. Since the sub-DC signal control terminal (S1), the sub-DC signal control terminal (S2) and the sub-DC signal control terminal (S3) are provided by a set of GOA circuits, this The pixel circuit of the disclosed embodiment is applicable to both a driving method that sequentially lights up row by row and a driving method that lights up all rows at the same time.
  • the writing time of each row of pixel data voltage VdataI and duration voltage VdataT is 1H, which only takes more than ten microseconds, and there is no need to wait for the full-screen data voltage VdataI and The duration voltage VdataT emits light after being written, so the pixel circuit provided by the embodiment of the present disclosure can be applied to high-resolution products.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present disclosure, unless otherwise specified, “plurality” means two or more.

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Abstract

一种像素电路、像素电路的驱动方法、显示基板和显示装置。像素电路包括：发光器件（10）、电流供给子电路（11）和时间控制子电路（12）；电流供给子电路（11）连接扫描信号端（Gate）、数据信号端（DataI）、发光控制端（EM）、第一电源电压端（DD）、时间控制子电路（12）和发光器件（10），设置为接收数据信号端（DataI）的数据电压（VdataI），并为发光器件（10）提供驱动电流；时间控制子电路（12）连接扫描信号端（Gate）、时长信号端（DataT）、第二电源电压端（COM）、直流信号控制端（S）和直流电压端（D），设置为接收时长信号端（DataT）的时长电压（VdataT）以及直流电压端（D）输入的直流电压，并根据时长电压（VdataT）和直流电压，控制电流供给子电路（11）与发光器件（10）连通的时长，以控制发光器件（10）的发光时长。

Description

像素电路及其驱动方法、显示基板和显示装置
本申请要求于2020年3月23日提交中国专利局、申请号为202010209937.5、发明名称为“一种像素电路及其驱动方法、显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种像素电路及其驱动方法、显示基板和显示装置。
背景技术
微型无机发光二极管，即发光二极管微缩化和矩阵化技术，指的是在一个芯片上集成的高密度微小尺寸的发光二极管阵列。微型无机发光二极管因其高亮度、高效率、反应时间快、体积小、寿命长等诸多优点而受到广泛的关注。
但是，由于微型无机发光二极管的发光效率在低电流密度下随着电流密度的变化而变化，且色坐标也随着电流密度的变化而变化，目前仍然没有成熟的微型无机发光二极管显示驱动方案。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种像素电路，包括：发光器件、电流供给子电路和时间控制子电路，其中：
所述电流供给子电路，连接扫描信号端、数据信号端、发光控制端、第一电源电压端、时间控制子电路和发光器件，设置为接收所述数据信号端的数据电压，并为所述发光器件提供驱动电流；
所述时间控制子电路，连接扫描信号端、时长信号端、第二电源电压端、直流信号控制端和直流电压端，设置为接收所述时长信号端的时长电压以及所述直流电压端输入的直流电压，并根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发光器件的发光时长。
在一示例性实施例中，所述时间控制子电路包括第一信号写入模块和时长控制模块，其中：
所述第一信号写入模块，连接所述扫描信号端、所述时长信号端、所述第二电源电压端和所述时长控制模块，设置为在所述扫描信号端的控制下，将所述时长信号端的时长电压输入所述时长控制模块；
所述时长控制模块，连接所述直流信号控制端、所述直流电压端和所述电流供给子电路，设置为在所述直流信号控制端的控制下，接收所述直流电压端的直流电压，根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发光器件的发光时长。
在一示例性实施例中，所述时长控制模块包括电压输入模块和开关模块，其中：
所述电压输入模块，连接所述直流信号控制端、所述直流电压端、所述第一信号写入模块和所述开关模块，设置为在所述直流信号控制端的控制下，将所述直流电压端的直流电压输入所述开关模块；
所述开关模块，连接所述第一信号写入模块、所述电流供给子电路和所述电压输入模块，设置为接收所述时长电压，根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发光器件的发光时长。
在一示例性实施例中，所述电压输入模块包括至少两个电压输入子单元，所述直流信号控制端包括至少两个子直流信号控制端，所述直流电压端包括至少两个子直流电压端；
每一所述电压输入子单元均对应一所述子直流信号控制端和一所述子直流电压端；以及
每一所述电压输入子单元的第一端与该电压输入子单元对应的所述子直流信号控制端连接，第二端与该电压输入子单元对应的所述子直流电压端连接，第三端与所述开关模块连接。
在一示例性实施例中，每一所述电压输入子单元包括一晶体管；
所述晶体管的控制端连接所述子直流信号控制端，第一极连接所述子直流电压端，第二极连接所述开关模块。
在一示例性实施例中，所述开关模块包括第一晶体管和第一电容，其中：
所述第一晶体管的控制端连接所述第一电容的一端和所述第一信号写入模块，第一极和第二极连接所述电流供给子电路；
所述第一电容的另一端连接所述电压输入模块。
在一示例性实施例中，所述第一信号写入模块包括第二晶体管和第三晶体管，其中：
所述第二晶体管的控制端连接所述扫描信号端，第一极连接所述时长信号端，第二极连接所述时长控制模块；
所述第三晶体管的控制端连接所述扫描信号端，第一极连接所述第二电源电压端，第二极连接所述时长控制模块。
在一示例性实施例中，所述电流供给子电路包括第二信号写入模块、发光控制模块和驱动模块，其中：
所述第二信号写入模块，连接所述扫描信号端、所述数据信号端、所述时间控制子电路和所述驱动模块，设置为在所述扫描信号端的控制下，将所述数据信号端的数据电压输入所述驱动模块；
所述发光控制模块，连接所述发光控制端、所述第一电源电压端、所述第二信号写入模块、所述驱动模块、所述时间控制子电路和所述发光器件，设置为在所述发光控制端的控制下，将所述第一电源电压端与所述驱动模块连接，以及将所述时间控制子电路与所述发光器件连接；
所述驱动模块，连接所述第一电源电压端、所述发光控制模块和所述第二信号写入模块，设置为向所述发光器件提供驱动电流。
在一示例性实施例中，所述第二信号写入模块包括第四晶体管和第五晶体管，其中：
所述第四晶体管的控制端连接所述扫描信号端，第一极连接所述数据信号端，第二极连接所述发光控制模块和所述驱动模块；
所述第五晶体管的控制端连接所述扫描信号端，第一极连接所述驱动模块，第二极连接所述时间控制子电路和所述驱动模块。
在一示例性实施例中，所述驱动模块包括第六晶体管和第二电容，其中：
所述第六晶体管的控制端连接所述第二信号写入模块，第一极连接所述第二信号写入模块和所述发光控制模块，第二极连接所述时间控制子电路和所述第二信号写入模块；
所述第二电容的一端连接所述第一电源电压端，另一端连接所述第二信号写入模块和所述第六晶体管的控制端。
在一示例性实施例中，所述发光控制模块包括第七晶体管和第八晶体管，其中：
所述第七晶体管的控制端连接所述发光控制端，第一极连接所述第一电源电压端，第二极连接所述驱动模块和所述第二信号写入模块；
所述第八晶体管的控制端连接所述发光控制端，第一极连接所述发光器件，第二极连接所述时间控制子电路。
在一示例性实施例中，所述像素电路还包括复位模块，连接重置信号端、初始电压端和所述电流供给子电路，设置为在所述重置信号端的控制下，将所述初始电压端的初始电压输入所述电流供给子电路，使所述电流供给子电路初始化。
在一示例性实施例中，所述复位模块包括第九晶体管；
所述第九晶体管的控制端连接所述重置信号端，第一极连接所述初始电压端，第二极连接所述电流供给子电路。
本公开实施例提供了一种显示基板，包括阵列设置的若干像素单元，每一所述像素单元均包括前述实施例示意的像素电路。
本公开实施例提供了一种显示装置，包括前述实施例示意的显示基板。
本公开实施例提供一种像素电路的驱动方法，用于前述实施例示意的像素电路，包括：
在所述扫描信号端的控制下，将所述数据信号端的数据电压输入所述电流供给子电路，以及将所述时长信号端的时长电压输入所述时间控制子电路；
在所述直流信号控制端和所述发光控制端的控制下，接收所述直流电压端输入的直流电压，并根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发光器件的发光时长。
在一示例性实施例中，所述在所述扫描信号端的控制下，将所述数据信号端的数据电压输入所述电流供给子电路，以及将所述时长信号端的时长电压输入所述时间控制子电路之前，还包括：
在重置信号端的控制下，将初始电压端的初始电压输入所述电流供给子电路，以对所述电流供给子电路初始化。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
本公开实施例上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为一种全屏时序像素电路的电路图；
图2为图1像素电路的时序图；
图3为本公开实施例提供的一种像素电路的框图；
图4-图6为本公开实施例提供的一种像素电路的具体框图；
图7为本公开实施例提供的一种像素电路的电路图；
图8为图7像素电路的时序图；
图9为本公开的示例提供的另一像素电路的电路图；
图10为图9像素电路的时序图；
图11为提供图10时序信号的GOA电路图；
图12为本公开实施例提供的像素电路在复位阶段的电路图；
图13为本公开实施例提供的像素电路在数据写入阶段的电路图；
图14为本公开实施例提供的像素电路在第一发光阶段的电路图；
图15为本公开实施例提供的像素电路在第二发光阶段的电路图；
图16为本公开实施例提供的像素电路在第三发光阶段的电路图；
图17为本公开实施例提供的一种像素电路的驱动方法流程图。
具体实施方式
下面详细描述本公开，本公开的实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外，如果已知技术的详细描述对于示出的本公开的特征是不必要的，则将其省略。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能解释为对本公开的限制。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本公开所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本公开的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。应该理解，当我们称元件被“连接”到另一元件时，它可以直接连接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”可以包括无线连接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
微型无机发光二极管技术中，如图1和图2所示，其中图1所示为一种驱动电流型发光元件的像素电路，图2为图1所示像素电路的时序图，其中， 电流型发光元件包括有机电致发光二极管，或者微型无机发光二极管。
如图1所示，数据信号端DataI的数据电压VdataI控制驱动晶体管T2的工作状态，从而控制微型无机发光二极管D的工作电流；在晶体管T4导通时(GateB为低电平时)，电容C2的一端被写入时长信号端DataT的时长电压VdataT，另一端被写入电压端Ramp的电压Vramp。Vramp是随时间变化的电压信号，例如图2所示，当Vramp降低时，晶体管T5的栅极电压会随着降低，当达到晶体管T5的开启条件时，晶体管T5导通，微型无机发光二极管发光，因此不同的VdataT对应不同的导通时长，从而使电流型发光元件产生不同的亮度。
如图2所示，在具有阵列排布的多个像素的显示面板中，用于驱动每个像素的像素电路中的电压端Ramp连接在一起，即所有像素接收统一的Vramp信号，而同一列像素电路的数据信号端DataI连接在一起，同一列像素电路的时长信号端DataT连接在一起，先依次向每一行像素电路输入数据电压VdataI和时长电压VdataT，再将所有像素电路中发光控制端(EM)输出的发光控制信号(EM)变为有效电平信号，同时电压端Ramp提供的电压Vramp也开始随时间变化，即所有的像素同时发光。
发明人发现，上述驱动方法的问题之一是无法对应高分辨率显示面板，因为数据电压VdataI和时长电压VdataT的写入时间是2H，其中1H的含义是一行像素写入数据电压或时长电压所用的时间，数值范围在几微秒到几十微秒，总写入时间需要再乘以像素单元的行数，这样仅数据电压VdataI和时长电压VdataT写入就用了几毫秒到十毫秒，微型无机发光二极管发光时间所剩无几，因此，图1和图2所示的像素电路及其驱动时序仅可对应低分辨率产品。
有鉴于此，本公开实施例提供一种新的像素电路及其驱动方法，提供一种成熟的微型无机发光二极管显示驱动方案，可对应高分辨率产品。
下面通过示例性实施例对本公开的技术方案进行详细说明。
本公开实施例提供一种像素电路，包括：发光器件、电流供给子电路和时间控制子电路，其中：
电流供给子电路连接扫描信号端、数据信号端、发光控制端、第一电源电压端、时间控制子电路和发光器件，设置为接收数据信号端的数据电压，并为发光器件提供驱动电流；
时间控制子电路连接扫描信号端、时长信号端、第二电源电压端、直流信号控制端和直流电压端，设置为接收时长信号端的时长电压以及直流电压端输入的直流电压，并根据时长电压和直流电压，控制电流供给子电路与发光器件连通的时长，以控制发光器件的发光时长。
由于本公开实施例提供的像素电路包括电流供给子电路和时间控制子电路，本公开实施例可以通过电流供给子电路控制发光器件始终工作在高电流密度区域，即工作在器件效率稳定区域；由于时间控制子电路可以控制电流供给子电路与发光器件连通的时长，以控制发光器件的发光时长，因此，本公开实施例能够通过电流和时长两种控制方法结合来共同实现发光器件的灰阶显示，本公开实施例不同的发光时长对应发光器件的不同灰阶。
可选地，本公开实施例中的发光器件为微型无机发光二极管，由于本公开实施例中的像素电路可以通过电流供给子电路控制发光器件始终工作在高电流密度区域，且能够通过电流和时长两种控制方法结合来共同实现发光器件的灰阶显示，因此，本公开实施例中的像素电路有效的避免了微型无机发光二极管的发光效率在低电流密度下随着电流密度的变化而变化，且色坐标也随着电流密度的变化而变化的问题。
如图3所示，本公开实施例提供的像素电路包括发光器件10、电流供给子电路11和时间控制子电路12；
电流供给子电路11，连接扫描信号端(Gate)、数据信号端(DataI)、发光控制端(EM)、第一电源电压端(DD)、时间控制子电路12和发光器件10，设置为接收数据信号端(DataI)的数据电压VdataI，并为发光器件10提供驱动电流；
时间控制子电路12，连接扫描信号端(Gate)、时长信号端(DataT)、第二电源电压端(COM)、直流信号控制端(S)和直流电压端(D)，设置为接收时长信号端(DataT)的时长电压VdataT以及直流电压端(D)输入的直流电压，根据时长电压VdataT和直流电压，控制电流供给子电路11 与发光器件10连通的时长(即控制电流供给子电路11与发光器件10连接且导通的时长)，以控制发光器件10的发光时长。
本公开实施例提供的像素电路包括电流供给子电路11和时间控制子电路12，本公开实施例可以通过电流供给子电路11控制发光器件10始终工作在高电流密度区域，即工作在器件效率稳定区域；由于时间控制子电路12可以控制电流供给子电路11与发光器件10连通的时长，以控制发光器件10的发光时长，因此，本公开实施例能够通过电流和时长两种控制方法结合共同实现发光器件10的灰阶显示，本公开实施例不同的发光时长对应发光器件的不同灰阶。
在一示例性实施例中，如图4所示，时间控制子电路12包括第一信号写入模块121和时长控制模块122，其中：
第一信号写入模块121，连接扫描信号端(Gate)、时长信号端(DataT)、第二电源电压端(COM)和时长控制模块122，设置为在扫描信号端(Gate)的控制下，将时长信号端(DataT)的时长电压VdataT输入时长控制模块122；
时长控制模块122，连接直流信号控制端(S)、直流电压端(D)和电流供给子电路11，设置为在直流信号控制端(S)的控制下，接收直流电压端(D)的直流电压，根据时长电压VdataT和直流电压，控制电流供给子电路11与发光器件10连通的时长，以控制发光器件10的发光时长。
在一示例性实施例中，如图5所示，时长控制模块122包括电压输入模块1221和开关模块1222，其中：
电压输入模块1221，连接直流信号控制端(S)、直流电压端(D)、第一信号写入模块121和开关模块1222，设置为在直流信号控制端(S)的控制下，将直流电压端(D)的直流电压输入开关模块1222；
开关模块1222，连接第一信号写入模块121、电流供给子电路11和电压输入模块1221，设置为接收时长电压VdataT，根据时长电压VdataT和直流电压，控制电流供给子电路11与发光器件10连通的时长，以控制发光器件10的发光时长。
在一示例性实施例中，如图6所示，电压输入模块1221包括至少两个电 压输入子单元12211，直流信号控制端(S)包括至少两个子直流信号控制端，图6中示出了n个子直流信号控制端(S1、S2……Sn)，直流电压端(D)包括至少两个子直流电压端，图6中示出了n个子直流电压端(D1、D2……Dn)；
每一电压输入子单元12211均对应一子直流信号控制端和一子直流电压端；以及每一电压输入子单元12211的第一端与该电压输入子单元12211对应的子直流信号控制端连接，第二端与该电压输入子单元12211对应的子直流电压端连接，第三端与开关模块1222连接。
在一示例性实施例中，如图6所示，电流供给子电路11包括第二信号写入模块111、发光控制模块112和驱动模块113；
第二信号写入模块111，连接扫描信号端(Gate)、数据信号端(DataI)、时间控制子电路12和驱动模块113，设置为在扫描信号端(Gate)的控制下，将数据信号端(DataI)的数据电压VdataI输入驱动模块113；
发光控制模块112，连接发光控制端(EM)、第一电源电压端(DD)、第二信号写入模块111、驱动模块113、时间控制子电路12和发光器件10，设置为在发光控制端(EM)的控制下，将第一电源电压端(DD)与驱动模块113连接，以及将时间控制子电路12与发光器件10连接；
驱动模块113，连接第一电源电压端(DD)、发光控制模块112和第二信号写入模块111，设置为向发光器件10提供驱动电流。
在一示例性实施例中，如图6所示，本公开实施例的像素电路还可包括复位模块13，连接重置信号端(RST)、初始电压端(Int)和电流供给子电路11，设置为在重置信号端(RST)的控制下，将初始电压端(Int)的初始电压Vint输入电流供给子电路11，使电流供给子电路11初始化。
初始化阶段为相邻图像帧之间的时间段，该时间段用于消除上一帧的残留图像。对于任一图像帧，都会经过从第一行栅线到最后一行栅线的逐行扫描，因而，初始化阶段发生在前一图像帧的最后一行栅线扫描完且最后一行像素完成显示之后到下一图像帧的第一行栅线开始扫描之前。
在一种示例性的实施例中，如图7所示，本公开实施例提供的像素电路 包括第二信号写入模块111、发光控制模块112、驱动模块113、复位模块13、第一信号写入模块121、电压输入模块1221和开关模块1222，图8为图7所示像素电路的时序图。
在一示例性实施例中，如图7所示，电压输入模块1221包括至少两个电压输入子单元，每一电压输入子单元包括一晶体管，图7中示出了电压输入模块1221包括n个电压输入子单元，第一个电压输入子单元包括晶体管T10、第二个电压输入子单元包括晶体管T11，第三个电压输入子单元包括晶体管T12，第n个电压输入子单元包括晶体管T(n+9)。每一电压输入子单元均对应一子直流信号控制端和一子直流电压端，如图7所示，第一个电压输入子单元对应子直流信号控制端(S1)和子直流电压端(D1)，第二个电压输入子单元对应子直流信号控制端(S2)和子直流电压端(D2)，第三个电压输入子单元对应子直流信号控制端(S3)和子直流电压端(D3)，第n个电压输入子单元对应子直流信号控制端(Sn)和子直流电压端(Dn)。如图7所示，晶体管T10的控制端连接子直流信号控制端(S1)，第一极连接子直流电压端(D1)，第二极连接开关模块1222；晶体管T11的控制端连接子直流信号控制端(S2)，第一极连接子直流电压端(D2)，第二极连接开关模块1222；晶体管T12的控制端连接子直流信号控制端(S3)，第一极连接子直流电压端(D3)，第二极连接开关模块1222；晶体管T(n+9)的控制端连接子直流信号控制端(Sn)，第一极连接子直流电压端(Dn)，第二极连接开关模块1222。
在一示例性实施例中，如图7所示，开关模块1222包括第一晶体管T8和第一电容C2；第一晶体管T8的控制端连接第一电容C2的一端和第一信号写入模块121，第一极和第二极连接电流供给子电路，其中，第二极连接电流供给子电路包括的第二信号写入模块111以及驱动模块113，第一极连接电流供给子电路包括的发光控制模块112；第一电容C2的另一端连接电压输入模块1221。
在一示例性实施例中，如图7所示，第一信号写入模块121包括第二晶体管T7和第三晶体管T9；第二晶体管T7的控制端连接扫描信号端(Gate)，第一极连接时长信号端(DataT)，第二极连接时长控制模块122包括的开关 模块1222；第三晶体管T9的控制端连接扫描信号端(Gate)，第一极连接第二电源电压端(COM)，第二极连接时长控制模块122包括的开关模块1222和电压输入模块1221。
在一示例性实施例中，如图7所示，第二信号写入模块111包括第四晶体管T2和第五晶体管T3；第四晶体管T2的控制端连接扫描信号端(Gate)，第一极连接数据信号端(DataI)，第二极连接发光控制模块112和驱动模块113；第五晶体管T3的控制端连接扫描信号端(Gate)，第一极连接驱动模块113和复位模块13(可选)，第二极连接时间控制子电路12包括的开关模块1222和驱动模块113。
在一示例性实施例中，如图7所示，驱动模块113包括第六晶体管T4和第二电容C1；第六晶体管T4的控制端连接第二信号写入模块111和复位模块13(可选)，第一极连接第二信号写入模块111和发光控制模块112，第二极连接时间控制子电路12包括的开关模块1222和第二信号写入模块111；第二电容C1的一端连接第一电源电压端(DD)，另一端连接第二信号写入模块111、复位模块13(可选)和第六晶体管T4的控制端。
在一示例性实施例中，如图7所示，发光控制模块112包括第七晶体管T5和第八晶体管T6；第七晶体管T5的控制端连接发光控制端(EM)，第一极连接第一电源电压端(DD)，第二极连接驱动模块113和第二信号写入模块111；第八晶体管T6的控制端连接发光控制端(EM)，第一极连接发光器件10，第二极连接时间控制子电路12包括的开关模块1222。
在一示例性实施例中，如图7所示，复位模块13包括第九晶体管T1，第九晶体管T1的控制端连接重置信号端(RST)，第一极连接初始电压端(Int)，第二极连接电流供给子电路11包括的驱动模块113和第二信号写入模块111。
可选地，本公开实施例中的发光器件10可以为微型无机发光二极管。
可选地，如图7所示，本公开实施例中第一晶体管T8、第二晶体管T7、第三晶体管T9、第四晶体管T2、第五晶体管T3、第六晶体管T4、第七晶体管T5、第八晶体管T6、第九晶体管T1、晶体管T10、晶体管T11、晶体管T12和晶体管T(n+9)均为P型晶体管；当然，在实际电路设计中，这些晶体管也可以为N型晶体管，本公开实施例并不对晶体管的类型做限定。这些 晶体管的第一极可以为源极，第二极可以为漏极，当然，第一极也可以为漏极，第二极也可以为源极，在实际设计中，这些晶体管的第一极和第二极可以互换。
下面结合一个示例详细说明本公开实施例的像素电路。
如图9所示，本公开实施例提供的像素电路包括扫描信号端(Gate)、发光控制端(EM)、数据信号端(DataI)、时长信号端(DataT)、第一电源电压端(DD)、第二电源电压端(COM)、直流信号控制端(S1、S2和S3)、直流电压端(D1、D2和D3)、重置信号端(RST)、初始电压端(Int)、第一电容C2、第二电容C1、第一晶体管T8、第二晶体管T7、第三晶体管T9、第四晶体管T2、第五晶体管T3、第六晶体管T4、第七晶体管T5、第八晶体管T6、第九晶体管T1、晶体管T10、晶体管T11和晶体管T12。
可选地，如图9所示，第一晶体管T8的控制端连接第一电容C2的第一端和第二晶体管T7的第二极，第一极连接第八晶体管T6的第二极，第二极连接第五晶体管T3的第二极和第六晶体管T4的第二极。
第二晶体管T7的控制端连接扫描信号端(Gate)，第一极连接时长信号端(DataT)，第二极连接第一晶体管T8的控制端和第一电容C2的第一端。
第三晶体管T9的控制端连接扫描信号端(Gate)，第一极连接第二电源电压端(COM)，第二极连接第一电容C2的第二端。
第四晶体管T2的控制端连接扫描信号端(Gate)，第一极连接数据信号端(DataI)，第二极连接第七晶体管T5的第二极和第六晶体管T4的第一极。
第五晶体管T3的控制端连接扫描信号端(Gate)，第一极连接第六晶体管T4的控制端、第二电容C1的第二端和第九晶体管T1的第二极，第二极连接第一晶体管T8的第二极和第六晶体管T4的第二极。
第六晶体管T4的控制端连接第二电容C1的第二端、第九晶体管T1的第二极和第五晶体管T3的第一极，第一极连接第四晶体管T2的第二极和第七晶体管T5的第二极，第二极连接第五晶体管T3的第二极和第一晶体管T8的第二极。
第七晶体管T5的控制端连接发光控制端(EM)，第一极连接第一电源 电压端(DD)，第二极连接第四晶体管T2的第二极和第六晶体管T4的第一极。
第八晶体管T6的控制端连接发光控制端(EM)，第一极连接发光器件10，第二极连接第一晶体管T8的第一极。
第九晶体管T1的控制端连接重置信号端(RST)，第一极连接初始电压端(Int)，第二极连接第二电容C1的第二端、第六晶体管T4的控制端和第五晶体管T3的第一极。
晶体管T10的控制端连接子直流信号控制端(S1)，第一极连接子直流电压端(D1)，第二极连接第一电容C2的第二端；晶体管T11的控制端连接子直流信号控制端(S2)，第一极连接子直流电压端(D2)，第二极连接第一电容C2的第二端；晶体管T12的控制端连接子直流信号控制端(S3)，第一极连接子直流电压端(D3)，第二极连接第一电容C2的第二端。
图10为图9所示像素电路的时序图，图10的时序信号可以由图11所示的GOA电路提供，如图11所示，该GOA电路包括多级级联的移位寄存器，其中GSTV、ESTV、SSTV1、SSTV2和SSTV3为GOA电路的输入信号，GSTV信号对应的输出信号为扫描信号端(Gate)的信号，ESTV信号对应的输出信号为发光控制端(EM)的信号，SSTV1信号对应的输出信号为子直流信号控制端S3的信号，SSTV2信号对应的输出信号为子直流信号控制端S2的信号，SSTV3信号对应的输出信号为子直流信号控制端S1的信号，对该GOA电路的工作过程，这里不再赘述。
下面结合附图介绍本公开实施例提供的像素电路的工作过程。
本公开实施例提供的像素电路的工作过程包括复位阶段、数据写入阶段和发光阶段。本实施例中的发光器件10为微型无机发光二极管。
如图10所示，在复位阶段，重置信号端(RST)输出低电平信号，扫描信号端(Gate)、发光控制端(EM)、子直流信号控制端(S1)、子直流信号控制端(S2)和子直流信号控制端(S3)均输出高电平信号，如图12所示，此时仅第九晶体管T1导通，其余晶体管均处于关闭状态，第二电容C1两极板电位被第一极连接初始电压端(Int)的初始电压Vint和第一电源电压 端(DD)的电源电压VDD初始化，初始化可以使得像素电路处于确定的初始状态。
如图10所示，在数据写入阶段，扫描信号端(Gate)输出低电平信号，重置信号端(RST)、发光控制端(EM)、子直流信号控制端(S1)、子直流信号控制端(S2)和子直流信号控制端(S3)均输出高电平信号，如图13所示，第四晶体管T2、第五晶体管T3、第六晶体管T4、第二晶体管T7和第三晶体管T9导通，其余晶体管均处于关闭状态，数据信号端(DataI)的数据电压VdataI写入，N1点电压为VdataI+第六晶体管T4的阈值电压Vth；并且，时长信号端(DataT)的时长电压VdataT写入，N2点电压为VdataT，该时长电压VdataT存入第一电容C2中。
如图10所示，在发光阶段，本实施例提供的像素电路的发光阶段包括三个阶段，在第一发光阶段，发光控制端(EM)和子直流信号控制端(S1)输出低电平信号，扫描信号端(Gate)、重置信号端(RST)、子直流信号控制端(S2)和子直流信号控制端(S3)均输出高电平信号；在第二发光阶段，发光控制端(EM)和子直流信号控制端(S2)输出低电平信号，扫描信号端(Gate)、重置信号端(RST)、子直流信号控制端(S1)和子直流信号控制端(S3)均输出高电平信号；在第三发光阶段，发光控制端(EM)和子直流信号控制端(S3)输出低电平信号，扫描信号端(Gate)、重置信号端(RST)、子直流信号控制端(S1)和子直流信号控制端(S2)均输出高电平信号。
在第一发光阶段，如图14所示，第六晶体管T4、第七晶体管T5、第八晶体管T6和晶体管T10导通，第一晶体管T8状态待定，其余晶体管均处于关闭状态。电流控制部分，第六晶体管T4产生微型无机发光二极管的工作电流I DS：
Figure PCTCN2021075716-appb-000001
其中：μ表示第六晶体管T4材料的迁移率，Cox表示第六晶体管T4的电容值，W表示第六晶体管T4的宽度，L表示第六晶体管T4的长度，因此，本实施例在第一发光阶段微型无机发光二极管的工作电流I DS与第六晶体管T4的阈值电压Vth无关，并不会影响微型无机发光二极管的发光。时间控制 部分，由于晶体管T10导通，第一电容C2的第二端接到了子直流电压端(D1)，由于第一电容C2的自举作用，则N2点电压被自举为VdataT+V1-VCOM，若N2点电压VdataT+V1-VCOM使得第一晶体管T8满足开启条件V GS≥Vth8，Vth8为第一晶体管T8的阈值电压，则第一晶体管T8导通，微型无机发光二极管开始发光，若N2点电压VdataT+V1-VCOM不能满足第一晶体管T8的开启条件，则微型无机发光二极管在子直流信号控制端(S1)输出低电平信号的时间段内不发光。
在第二发光阶段，如图15所示，第六晶体管T4、第七晶体管T5、第八晶体管T6和晶体管T11导通，第一晶体管T8状态待定，其余晶体管均处于关闭状态。电流控制部分同第一发光阶段，在此不再赘述。时间控制部分，由于晶体管T11导通，第一电容C2的第二端接到了子直流电压端(D2)，由于第一电容C2的自举作用，则N2点电压被自举为VdataT+V2-VCOM，若N2点电压VdataT+V2-VCOM使得第一晶体管T8满足开启条件V GS≥Vth8，则第一晶体管T8导通，微型无机发光二极管继续发光，若N2点电压VdataT+V2-VCOM不能满足第一晶体管T8的开启条件，则微型无机发光二极管在子直流信号控制端(S2)输出低电平信号的时间段内不发光。
在第三发光阶段，如图16所示，第六晶体管T4、第七晶体管T5、第八晶体管T6和晶体管T12导通，第一晶体管T8状态待定，其余晶体管均处于关闭状态。电流控制部分同第一发光阶段，在此不再赘述。时间控制部分，由于晶体管T12导通，第一电容C2的第二端接到了子直流电压端(D3)，由于第一电容C2的自举作用，则N2点电压被自举为VdataT+V3-VCOM，若N2点电压VdataT+V3-VCOM使得第一晶体管T8满足开启条件V GS≥Vth8，则第一晶体管T8导通，微型无机发光二极管继续发光，若N2点电压VdataT+V3-VCOM不能满足第一晶体管T8的开启条件，则微型无机发光二极管在子直流信号控制端(S3)输出低电平信号的时间段内不发光。
本公开实施例通过数据电压VdataI控制微型无机发光二极管始终工作在高电流密度区域，即工作在器件效率稳定区域，然后晶体管T10、晶体管T11和晶体管T12按时序依次导通，第一电容C2的第二端分别接入直流电压V1、直流电压V2和直流电压V3，第二电容C2的第一端会自举到相应的电压， 从而控制第一晶体管T8的导通状态，继而控制微型无机发光二极管的发光时长，最终通过电流和时长两种控制方法结合共同实现微型无机发光二极管的灰阶显示，本公开实施例的像素电路通过时长控制弥补了微型无机发光二极管发光器件本身的缺陷。
可以理解的是，子直流电压端D1、D2、D3、传输的直流电压V1、V2、V3是固定幅值的电压，发光器件10实现不同灰阶主要是由固定时长信号端(DataT)提供的时长电压VdataT决定的。
下面结合图10、图14、图15和图16说明本公开实施例中发光器件(如微型无机发光二极管)不同灰阶的实现方式。
如图10和图14所示，在第一发光阶段，当N2点电压VdataT+V1-VCOM使得第一晶体管T8满足开启条件V GS≥Vth8，则第一晶体管T8导通，微型无机发光二极管开始发光；如图10和图15所示，在第二发光阶段，当N2点电压VdataT+V2-VCOM使得第一晶体管T8满足开启条件V GS≥Vth8，则第一晶体管T8导通，微型无机发光二极管开始发光；如图10和图16所示，在第三发光阶段，当N2点电压VdataT+V3-VCOM使得第一晶体管T8满足开启条件V GS≥Vth8，则第一晶体管T8导通，微型无机发光二极管开始发光；即本公开实施例中第一发光阶段、第二发光阶段和第三发光阶段微型无机发光二极管均发光，此时能够实现微型无机发光二极管的最亮灰阶状态。
因此，在当子直流电压端D1传输的直流电压V1的幅值满足条件：0≤V1≤(Vs-VdataT+VCOM+Vth8)时，其中Vs为第一晶体管T8的源极电压，该值在电路设计确定的情况下，是一个固定值；子直流电压端D2和D3传输的直流电压V2和V3需要满足的电压条件与V1需要满足的条件相同，即可实现最亮灰阶。
如图10和图14所示，在第一发光阶段，当N2点电压VdataT+V1-VCOM不能满足第一晶体管T8的开启条件V GS≥Vth8，则第一晶体管T8截止，微型无机发光二极管不发光；如图10和图15所示，在第二发光阶段，当N2点电压VdataT+V2-VCOM不能满足第一晶体管T8的开启条件V GS≥Vth8，则第一晶体管T8截止，微型无机发光二极管不发光；如图10和图16所示，在第三发光阶段，当N2点电压VdataT+V3-VCOM不能满足第一晶体管T8 的开启条件V GS≥Vth8，则第一晶体管T8截止，微型无机发光二极管不发光；即本公开实施例中第一发光阶段、第二发光阶段和第三发光阶段微型无机发光二极管均不发光，此时能够实现微型无机发光二极管的最暗灰阶状态。
可选地，实现最暗灰阶状态时，V1需要满足的电压条件为：V1大于等于Vs-VdataT+VCOM+Vth8，V2和V3需要满足的电压条件与V1需要满足的条件相同。
如图10和图14所示，在第一发光阶段，当N2点电压VdataT+V1-VCOM使得第一晶体管T8满足开启条件V GS≥Vth8，则第一晶体管T8导通，微型无机发光二极管开始发光；如图10和图15所示，在第二发光阶段，当N2点电压VdataT+V2-VCOM不能满足第一晶体管T8的开启条件V GS≥Vth8，则第一晶体管T8截止，微型无机发光二极管不发光；如图10和图16所示，在第三发光阶段，当N2点电压VdataT+V3-VCOM不能满足第一晶体管T8的开启条件V GS≥Vth8，则第一晶体管T8截止，微型无机发光二极管不发光；即本公开实施例中第一发光阶段微型无机发光二极管发光，第二发光阶段和第三发光阶段微型无机发光二极管均不发光，此时能够实现微型无机发光二极管的介于最亮灰阶状态和最暗灰阶状态的中间灰阶状态。当然，实现微型无机发光二极管的中间灰阶状态还可以是第一发光阶段和第二发光阶段微型无机发光二极管均发光，第三发光阶段微型无机发光二极管不发光等情形，本公开实施例只要保证有至少一个发光阶段发光，且三个发光阶段不同时发光即可实现微型无机发光二极管的中间灰阶状态。
可选地，实现中间灰阶状态时(以第一发光阶段微型无机发光二极管发光，第二发光阶段和第三发光阶段微型无机发光二极管均不发光为例)，V1需要满足的电压条件为：V1大于等于零，且小于等于Vs-VdataT+VCOM+Vth8，V2需要满足的电压条件为：V2大于等于Vs-VdataT+VCOM+Vth8，V3需要满足的电压条件与V2满足的电压条件相同。另外，为了更好的实现中间灰阶状态，本公开实施例中V1、V2和V3在满足上述电压范围的条件下，V1、V2和V3的幅值可以设置为不相等，例如V1、V2和V3的值可以按照依次递增或递减的方式设置。
如图10所示，本公开实施例中子直流信号控制端S1、子直流信号控制 端S2和子直流信号控制端S3的有效电平(即低电平)的时长可以设置为相等，也可以设置为不相等，三者没有特定的关系，只要保证S1、S2和S3的有效电平总时长小于等于[显示面板一帧显示时长-(每行像素单元的复位时长(即Reset信号有效电平时间)+每行像素单元的数据写入时长(即Gate信号有效电平时间)]即可。
本公开实施例在具有阵列排布的多个像素的显示面板中，同一列像素电路的数据信号端DataI连接在一起，同一列像素电路的时长信号端DataT连接在一起，同一行像素电路的扫描信号端Gate连接在一起，同一行像素电路的发光控制端EM连接在一起，同一行像素电路的直流信号控制端S连接在一起，同一行像素电路的重置信号端RST连接在一起；本公开实施例直流电压V1、直流电压V2和直流电压V3是全屏共用的直流信号，利用子直流信号控制端S1、子直流信号控制端S2和子直流信号控制端S3的时序来选择接入到像素电路中的直流电压，由于子直流信号控制端(S1)、子直流信号控制端(S2)和子直流信号控制端(S3)由一套GOA电路提供，因此，本公开实施例提供的像素电路可以实现像素逐行发光，即当一行像素的数据电压VdataI和时长电压VdataT写入后，该行像素直接就发光。当然，本公开实施例提供的像素电路也可以所有像素同时发光，当所有像素的数据电压VdataI和时长电压VdataT写入后，所有像素才开始发光。当本公开实施例提供的像素电路采用逐行发光的方式时，每行像素数据电压VdataI和时长电压VdataT写入时间是1H，仅需十几微秒，不需要等全屏数据电压VdataI和时长电压VdataT写入后发光，因此本公开实施例提供的像素电路可以应用于高分辨率产品中。
基于同一构思，本公开实施例还提供一种显示基板，该显示基板包括阵列设置的若干像素单元，每一像素单元均包括前述实施例示意的像素电路。由于显示基板包括本公开前述实施例提供的像素电路，因此本公开实施例提供的显示基板具有与像素电路相同的有益效果，这里不再赘述。
基于同一构思，本公开实施例还提供一种显示装置，包括前述实施例所 示的显示基板。由于显示装置包括本公开前述实施例所示提供的显示基板，因此本公开实施例提供的显示装置具有与显示基板相同的有益效果，这里不再赘述。
基于同一构思，本公开实施例还提供一种像素电路的驱动方法，该驱动方法的流程图如图17所示，该方法包括：
S102、在扫描信号端的控制下，将数据信号端的数据电压输入电流供给子电路，以及将时长信号端的时长电压输入时间控制子电路；
S103、在直流信号控制端和发光控制端的控制下，接收直流电压端输入的直流电压，并根据时长电压和直流电压，控制电流供给子电路与发光器件连通的时长，以控制发光器件的发光时长。
可选地，如图17所示，在扫描信号端的控制下，将数据信号端的数据电压输入电流供给子电路，以及将时长信号端的时长电压输入时间控制子电路之前，还包括：S101、在重置信号端的控制下，将初始电压端的初始电压输入电流供给子电路，以对电流供给子电路初始化。
本公开实施例中像素电路的驱动过程以及工作原理在上面已经进行了介绍，这里不再赘述。
由于本公开实施例提供的像素电路在扫描信号端的控制下，将数据信号端的数据电压输入电流供给子电路，以及将时长信号端的时长电压输入时间控制子电路；在直流信号控制端和发光控制端的控制下，接收直流电压端输入的直流电压，并根据时长电压和直流电压，控制电流供给子电路与发光器件连通的时长，以控制发光器件的发光时长。本公开实施例可以通过数据电压控制发光器件始终工作在高电流密度区域，即工作在器件效率稳定区域；本公开实施例能够通过电流和时长两种控制方法结合共同实现发光器件的灰阶显示。
应用本公开实施例，至少能够实现如下有益效果之一：
第一、由于本公开实施例提供的像素电路包括电流供给子电路和时间控 制子电路，本公开实施例可以通过电流供给子电路控制发光器件始终工作在高电流密度区域，即工作在器件效率稳定区域；由于时间控制子电路可以控制电流供给子电路与发光器件连通的时长，以控制发光器件的发光时长，因此，本公开实施例能够通过电流和时长两种控制方法结合共同实现发光器件的灰阶显示，本公开实施例不同的发光时长对应发光器件的不同灰阶。
第二、本公开实施例中的发光器件为微型无机发光二极管，由于本公开实施例中的像素电路可以通过电流供给子电路控制发光器件始终工作在高电流密度区域，且能够通过电流和时长两种控制方法结合共同实现发光器件的灰阶显示，因此，本公开实施例中的像素电路有效的避免了微型无机发光二极管的发光效率在低电流密度下随着电流密度的变化而变化，且色坐标也随着电流密度的变化而变化的问题。
第三、本公开实施例通过数据电压VdataI控制微型无机发光二极管始终工作在高电流密度区域，即工作在器件效率稳定区域，然后晶体管T10、晶体管T11和晶体管T12按时序依次导通，第一电容C2的第二端分别接入直流电压V1、直流电压V2和直流电压V3，第二电容C2的第一端会自举到相应的电压，以此来控制第一晶体管T8的导通状态，实现控制微型无机发光二极管的发光时长，最终实现了通过电流和时长两种控制方法结合共同实现微型无机发光二极管的灰阶显示，本公开实施例的像素电路通过时长控制弥补了微型无机发光二极管发光器件本身的缺陷。
第四、本公开实施例直流电压V1、直流电压V2和直流电压V3是全屏共用的直流信号，利用子直流信号控制端(S1)、子直流信号控制端(S2)和子直流信号控制端(S3)的时序来选择接入到像素电路中的直流电压，由于子直流信号控制端(S1)、子直流信号控制端(S2)和子直流信号控制端(S3)由一套GOA电路提供，因此本公开实施例的像素电路既适用于逐行顺序点亮的驱动方式也适用于所有行同时点亮的驱动方式。
第五、本公开实施例的像素电路采用逐行顺序点亮方式时，每行像素数据电压VdataI和时长电压VdataT写入时间是1H，仅需十几微秒，不需要等全屏数据电压VdataI和时长电压VdataT写入后发光，因此本公开实施例提供的像素电路可以应用于高分辨率产品中。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上。
以上所述仅是本公开的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种像素电路，包括：发光器件、电流供给子电路和时间控制子电路，其中：
    所述电流供给子电路，连接扫描信号端、数据信号端、发光控制端、第一电源电压端、时间控制子电路和发光器件，设置为接收所述数据信号端的数据电压，并为所述发光器件提供驱动电流；
    所述时间控制子电路，连接扫描信号端、时长信号端、第二电源电压端、直流信号控制端和直流电压端，设置为接收所述时长信号端的时长电压以及所述直流电压端输入的直流电压，并根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发光器件的发光时长。
  2. 根据权利要求1所述的像素电路，其中，所述时间控制子电路包括第一信号写入模块和时长控制模块，其中：
    所述第一信号写入模块，连接所述扫描信号端、所述时长信号端、所述第二电源电压端和所述时长控制模块，设置为在所述扫描信号端的控制下，将所述时长信号端的时长电压输入所述时长控制模块；
    所述时长控制模块，连接所述直流信号控制端、所述直流电压端和所述电流供给子电路，设置为在所述直流信号控制端的控制下，接收所述直流电压端的直流电压，根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发光器件的发光时长。
  3. 根据权利要求2所述的像素电路，其中，所述时长控制模块包括电压输入模块和开关模块，其中：
    所述电压输入模块，连接所述直流信号控制端、所述直流电压端、所述第一信号写入模块和所述开关模块，设置为在所述直流信号控制端的控制下，将所述直流电压端的直流电压输入所述开关模块；
    所述开关模块，连接所述第一信号写入模块、所述电流供给子电路和所述电压输入模块，设置为接收所述时长电压，根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发 光器件的发光时长。
  4. 根据权利要求3所述的像素电路，其中，所述电压输入模块包括至少两个电压输入子单元，所述直流信号控制端包括至少两个子直流信号控制端，所述直流电压端包括至少两个子直流电压端；
    每一所述电压输入子单元均对应一所述子直流信号控制端和一所述子直流电压端；以及
    每一所述电压输入子单元的第一端与该电压输入子单元对应的所述子直流信号控制端连接，第二端与该电压输入子单元对应的所述子直流电压端连接，第三端与所述开关模块连接。
  5. 根据权利要求4所述的像素电路，其中，每一所述电压输入子单元包括一晶体管；
    所述晶体管的控制端连接所述子直流信号控制端，第一极连接所述子直流电压端，第二极连接所述开关模块。
  6. 根据权利要求3所述的像素电路，其中，所述开关模块包括第一晶体管和第一电容，其中：
    所述第一晶体管的控制端连接所述第一电容的一端和所述第一信号写入模块，第一极和第二极连接所述电流供给子电路；
    所述第一电容的另一端连接所述电压输入模块。
  7. 根据权利要求2所述的像素电路，其中，所述第一信号写入模块包括第二晶体管和第三晶体管，其中：
    所述第二晶体管的控制端连接所述扫描信号端，第一极连接所述时长信号端，第二极连接所述时长控制模块；
    所述第三晶体管的控制端连接所述扫描信号端，第一极连接所述第二电源电压端，第二极连接所述时长控制模块。
  8. 根据权利要求1所述的像素电路，其中，所述电流供给子电路包括第二信号写入模块、发光控制模块和驱动模块，其中：
    所述第二信号写入模块，连接所述扫描信号端、所述数据信号端、所述 时间控制子电路和所述驱动模块，设置为在所述扫描信号端的控制下，将所述数据信号端的数据电压输入所述驱动模块；
    所述发光控制模块，连接所述发光控制端、所述第一电源电压端、所述第二信号写入模块、所述驱动模块、所述时间控制子电路和所述发光器件，设置为在所述发光控制端的控制下，将所述第一电源电压端与所述驱动模块连接，以及将所述时间控制子电路与所述发光器件连接；
    所述驱动模块，连接所述第一电源电压端、所述发光控制模块和所述第二信号写入模块，设置为向所述发光器件提供驱动电流。
  9. 根据权利要求8所述的像素电路，其中，所述第二信号写入模块包括第四晶体管和第五晶体管，其中：
    所述第四晶体管的控制端连接所述扫描信号端，第一极连接所述数据信号端，第二极连接所述发光控制模块和所述驱动模块；
    所述第五晶体管的控制端连接所述扫描信号端，第一极连接所述驱动模块，第二极连接所述时间控制子电路和所述驱动模块。
  10. 根据权利要求8所述的像素电路，其中，所述驱动模块包括第六晶体管和第二电容，其中：
    所述第六晶体管的控制端连接所述第二信号写入模块，第一极连接所述第二信号写入模块和所述发光控制模块，第二极连接所述时间控制子电路和所述第二信号写入模块；
    所述第二电容的一端连接所述第一电源电压端，另一端连接所述第二信号写入模块和所述第六晶体管的控制端。
  11. 根据权利要求8所述的像素电路，其中，所述发光控制模块包括第七晶体管和第八晶体管，其中：
    所述第七晶体管的控制端连接所述发光控制端，第一极连接所述第一电源电压端，第二极连接所述驱动模块和所述第二信号写入模块；
    所述第八晶体管的控制端连接所述发光控制端，第一极连接所述发光器件，第二极连接所述时间控制子电路。
  12. 根据权利要求1所述的像素电路，还包括复位模块，连接重置信号端、初始电压端和所述电流供给子电路，设置为在所述重置信号端的控制下，将所述初始电压端的初始电压输入所述电流供给子电路，使所述电流供给子电路初始化。
  13. 根据权利要求12所述的像素电路，其中，所述复位模块包括第九晶体管；
    所述第九晶体管的控制端连接所述重置信号端，第一极连接所述初始电压端，第二极连接所述电流供给子电路。
  14. 一种显示基板，包括阵列设置的若干像素单元，每一所述像素单元均包括如权利要求1至13中任一项所述的像素电路。
  15. 一种显示装置，包括如权利要求14所述的显示基板。
  16. 一种像素电路的驱动方法，用于如权利要求1至13中任一项所述的像素电路，包括：
    在所述扫描信号端的控制下，将所述数据信号端的数据电压输入所述电流供给子电路，以及将所述时长信号端的时长电压输入所述时间控制子电路；
    在所述直流信号控制端和所述发光控制端的控制下，接收所述直流电压端输入的直流电压，并根据所述时长电压和所述直流电压，控制所述电流供给子电路与所述发光器件连通的时长，以控制所述发光器件的发光时长。
  17. 根据权利要求16所述的驱动方法，其中，所述在所述扫描信号端的控制下，将所述数据信号端的数据电压输入所述电流供给子电路，以及将所述时长信号端的时长电压输入所述时间控制子电路之前，还包括：
    在重置信号端的控制下，将初始电压端的初始电压输入所述电流供给子电路，以对所述电流供给子电路初始化。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022222055A1 (zh) * 2021-04-21 2022-10-27 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板及其驱动方法
KR20230017973A (ko) * 2021-07-28 2023-02-07 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
CN117859167A (zh) * 2022-06-21 2024-04-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN117999600A (zh) * 2022-09-01 2024-05-07 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
TWI828412B (zh) * 2022-11-10 2024-01-01 友達光電股份有限公司 顯示裝置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160353539A1 (en) * 2012-11-22 2016-12-01 Sct Technology, Ltd. Apparatus and method for driving led display panel
CN108538241A (zh) * 2018-06-29 2018-09-14 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109920371A (zh) * 2019-04-26 2019-06-21 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN110010057A (zh) * 2019-04-25 2019-07-12 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法和显示装置
CN110310594A (zh) * 2019-07-22 2019-10-08 京东方科技集团股份有限公司 一种显示面板和显示装置
CN110491335A (zh) * 2019-09-03 2019-11-22 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4467909B2 (ja) * 2002-10-04 2010-05-26 シャープ株式会社 表示装置
JP5007490B2 (ja) * 2005-04-08 2012-08-22 セイコーエプソン株式会社 画素回路、及びその駆動方法、発光装置、並びに電子機器
WO2013136998A1 (ja) * 2012-03-14 2013-09-19 シャープ株式会社 表示装置
CN112904941A (zh) * 2014-02-28 2021-06-04 株式会社半导体能源研究所 电子设备
JP2016066065A (ja) * 2014-09-05 2016-04-28 株式会社半導体エネルギー研究所 表示装置、および電子機器
US9477345B2 (en) * 2015-01-30 2016-10-25 Lg Display Co., Ltd. Display device, and device and method for driving the same
JP2018013567A (ja) * 2016-07-20 2018-01-25 株式会社ジャパンディスプレイ 表示装置
US20180075798A1 (en) * 2016-09-14 2018-03-15 Apple Inc. External Compensation for Display on Mobile Device
CN107068107A (zh) * 2017-06-23 2017-08-18 京东方科技集团股份有限公司 像素电路、显示装置以及驱动方法
CN108447446A (zh) * 2018-04-10 2018-08-24 京东方科技集团股份有限公司 像素电路、显示面板及其驱动方法
KR102490631B1 (ko) * 2018-06-12 2023-01-20 엘지디스플레이 주식회사 유기발광 표시장치와 그 구동방법
CN109872680B (zh) * 2019-03-20 2020-11-24 京东方科技集团股份有限公司 像素电路及驱动方法、显示面板及驱动方法、显示装置
CN109979378B (zh) * 2019-05-15 2020-12-04 京东方科技集团股份有限公司 像素驱动电路和显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160353539A1 (en) * 2012-11-22 2016-12-01 Sct Technology, Ltd. Apparatus and method for driving led display panel
CN108538241A (zh) * 2018-06-29 2018-09-14 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN110010057A (zh) * 2019-04-25 2019-07-12 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法和显示装置
CN109920371A (zh) * 2019-04-26 2019-06-21 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN110310594A (zh) * 2019-07-22 2019-10-08 京东方科技集团股份有限公司 一种显示面板和显示装置
CN110491335A (zh) * 2019-09-03 2019-11-22 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置

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