WO2021184912A1 - 数据驱动器及其控制方法、显示装置 - Google Patents

数据驱动器及其控制方法、显示装置 Download PDF

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Publication number
WO2021184912A1
WO2021184912A1 PCT/CN2020/140911 CN2020140911W WO2021184912A1 WO 2021184912 A1 WO2021184912 A1 WO 2021184912A1 CN 2020140911 W CN2020140911 W CN 2020140911W WO 2021184912 A1 WO2021184912 A1 WO 2021184912A1
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Prior art keywords
input terminal
driving unit
data
signal
unit
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PCT/CN2020/140911
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English (en)
French (fr)
Inventor
王会明
汪敏
刘荣铖
杨秀琴
马京
赵鹏
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/417,389 priority Critical patent/US20220328016A1/en
Publication of WO2021184912A1 publication Critical patent/WO2021184912A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, in particular to a data driver and its control method, and a display device.
  • the present disclosure provides a data driver, a control method thereof, and a display device.
  • the present disclosure provides a data driver including: a control unit, a data distribution unit, a first driving unit, and a second driving unit; the data distribution unit is connected to the input terminal of the first driving unit and the second driving unit, respectively.
  • the input terminal is coupled to the input terminal and is configured to provide a first data distribution signal to the input terminal of the first driving unit, and to provide a second data distribution signal to the input terminal of the second driving unit;
  • the data distribution signal generates a first data signal
  • the second driving unit is configured to generate a second data signal according to the second data distribution signal, and the voltage polarities of the first data signal and the second data signal are different;
  • the control The unit is respectively coupled to the input terminal of the first driving unit and the input terminal of the second driving unit, and is configured to control the input terminal of the first driving unit and the input terminal of the second driving unit according to a power-on reset signal Short circuit or disconnection.
  • the present disclosure provides a display device including the data driver as described above.
  • the present disclosure provides a data driver control method, which is applied to the data driver as described above, and the control method includes: the control unit controls the input terminal and the first drive unit according to a power-on reset signal.
  • the input terminal of the second drive unit is short-circuited or disconnected.
  • FIG. 1 is a diagram showing the relationship between the gate-source voltage (Vgs) and the charging current (Ids) of a thin film transistor in a liquid crystal display device;
  • FIG. 2 is a schematic diagram showing that the actual pixel charging voltage of data signals with different voltage polarities is asymmetric with respect to the common voltage;
  • FIG. 3 is a schematic diagram of separate control of the first data signal and the second data signal of different voltage polarities in an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of power supply of a data driver provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of pumping large currents
  • FIG. 6 is a schematic structural diagram of a data driver provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a first data distribution signal and a second data distribution signal in an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a data driver provided by another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the effect of a data driver according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a work flow of a data driver according to an embodiment of the disclosure.
  • the present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art.
  • the embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form a unique solution defined by the claims.
  • Any feature or element of any embodiment can also be combined with features or elements from other solutions to form another unique solution defined by the claims. Therefore, it should be understood that any feature shown or discussed in this disclosure can be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other restrictions except for the restrictions made according to the appended claims and their equivalents.
  • one or more modifications and changes may be made within the protection scope of the appended claims.
  • the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As those of ordinary skill in the art will understand, other sequence of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims for the method or process should not be limited to performing their steps in the written order, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure.
  • Electrode connection includes the case where the constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • Examples of “elements having a certain electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.
  • the liquid crystal display device includes a gate driving circuit, a source driving circuit, a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel regions formed by crossing the scan lines and the data lines.
  • the plurality of scan lines are connected to the gate driving circuit.
  • the electrode driving circuit provides gate driving signals to the plurality of sub-pixels through a plurality of scan lines; the plurality of data lines are connected to the source driving circuit, and the source driving circuit provides display signals to the plurality of sub-pixels through the plurality of data lines.
  • Each sub-pixel area is provided with a thin film transistor (TFT, Thin Film Transistor), the gate of the thin film transistor is coupled to the scan line, the source of the thin film transistor is connected to the data line, and the drain of the thin film transistor is coupled to the pixel electrode.
  • TFT Thin Film Transistor
  • the on-off of the thin film transistor can be controlled by the signal of the scan line, thereby controlling whether to write the signal of the data line (that is, the data signal) to the pixel electrode.
  • the light-emitting brightness of each sub-pixel of the liquid crystal display device is determined by the voltage difference applied between the pixel electrode and the common electrode.
  • the liquid crystal display device In order to prevent the polarization of the liquid crystal, the liquid crystal display device mostly adopts a driving method of polarity inversion, that is, it is necessary to switch the positive and negative polarity of the voltage of the data signal input to the sub-pixel.
  • the driving mode of polarity inversion includes frame inversion, row inversion, column inversion and dot inversion.
  • the voltage polarity of the data signal input to the pixel electrode in one frame is positive (that is, the positive frame drive is performed), and the voltage polarity of the data signal input to the pixel electrode in the other frame is Is negative (that is, negative frame driving is performed); or, for two adjacent rows of sub-pixels, the voltage polarity of the data signal input to the pixel electrode of one row of sub-pixels is positive, and the voltage polarity of the data signal input to the pixel electrode of the other row of sub-pixels The voltage polarity is negative.
  • FIG. 1 is a diagram showing the relationship between the gate-source voltage (Vgs) and the charging current (Ids) of the TFT in the liquid crystal display device.
  • Vgs gate-source voltage
  • Ids charging current
  • the abscissa is the gate-source voltage of the TFT, in volts (V);
  • the ordinate is the charging current of the TFT, in amperes (A).
  • FIG. 2 is a schematic diagram showing that the actual pixel charging voltage of data signals with different voltage polarities is asymmetric with respect to the common voltage (Vcom).
  • 211 is the pixel voltage actually charged by the pixel electrode of the sub-pixel of the positive frame during the positive frame driving, which can be called the original pixel voltage of the positive frame
  • 212 is the data line input of the positive frame sub-pixel coupling during the positive frame driving.
  • the data voltage can be called the positive frame original data voltage
  • 213 is the pixel voltage actually charged on the pixel electrode of the negative frame sub-pixel when the negative frame is driven, which can be called the negative frame original pixel voltage
  • 214 is the negative frame when the negative frame is driven.
  • the data voltage input from the data line coupled to the frame sub-pixels may be referred to as a negative frame original data voltage. It can be seen from FIG. 2 that the time required to charge the pixel voltage of the pixel electrode to the original data voltage 212 of the positive frame during positive frame driving is longer than the time required to charge the pixel voltage of the pixel electrode to the negative frame original data voltage 214 during negative frame driving. The length of time required.
  • the pixel voltage of the positive frame sub-pixel has not yet reached the positive frame original data voltage 212, while the pixel voltage of the negative frame sub-pixel has reached the negative frame original data voltage.
  • 214 making the positive frame original pixel voltage 211 on the pixel electrode of the positive frame sub-pixel in the Mth row and the negative frame original pixel voltage 213 on the pixel electrode of the negative frame sub-pixel in the Mth row asymmetric with respect to the common voltage (Vcom), That is, under positive frame driving and negative frame driving, the absolute value A1 of the voltage difference between the positive frame original pixel voltage 211 of the positive frame sub-pixels in the Mth row and the common voltage is the same as the negative frame original pixel of the negative frame sub-pixels in the Mth row The absolute value A2 of the voltage difference between the voltage 213 and the common voltage is not equal. Among them, there is a large deviation between A1 and A2, which is a direct current component.
  • the pixel voltage of the sub-pixels in the positive frame of the M+1 row can reach the original data voltage of the positive frame, and the original pixel voltage of the positive frame on the pixel electrodes of the sub-pixels of the positive frame in the M+1 row is equal to the M+th pixel voltage.
  • the negative frame original pixel voltage on the pixel electrode of the negative frame sub-pixels of 1 row is symmetrical with respect to the common voltage, that is, under positive frame driving and negative frame driving, the positive frame original pixel voltage and the common voltage of the positive frame sub-pixels in the M+1 row
  • the absolute value B1 of the voltage difference therebetween is equal to the absolute value B2 of the voltage difference between the negative frame original pixel voltage of the negative frame sub-pixels in the M+1th row and the common voltage.
  • the Vgs of the driving transistor of the negative frame sub-pixel is about 32V
  • the charging speed of the negative frame sub-pixel is fast
  • the Vgs of the driving transistor of the positive frame sub-pixel is about 16V.
  • the charging speed of the positive frame sub-pixels is slow, causing the actual pixel charging voltages of the positive frame sub-pixels and the negative frame sub-pixels to be asymmetrical with respect to the common voltage Vcom, which will generate a significant DC bias voltage in the first black to white line, resulting in short-term DC line afterimages .
  • the embodiments of the present disclosure provide a data driver, a control method thereof, and a display device, which can improve short-term line afterimages, and can suppress the existing problem of large current drawn, thereby improving circuit stability and safety.
  • the embodiment of the present disclosure provides a data driver including: a control unit, a data distribution unit, a first driving unit, and a second driving unit; the data distribution unit is respectively coupled to the input terminal of the first driving unit and the input terminal of the second driving unit Connected, configured to provide a first data distribution signal to the input terminal of the first driving unit, and provide a second data distribution signal to the input terminal of the second driving unit; the first driving unit is configured to generate first data according to the first data distribution signal Signal, the second driving unit is configured to generate a second data signal according to the second data distribution signal, and the voltage polarities of the first data signal and the second data signal are different; the control unit is connected to the input terminal and the first driving unit respectively The input terminals of the two driving units are coupled, and are configured to control the input terminal of the first driving unit and the input terminal of the second driving unit to be short-circuited or disconnected according to the power-on reset signal.
  • the number of the first drive unit may be multiple, the number of the second drive unit may be multiple, and the data distribution unit may provide each first drive unit with the first data distribution signal, respectively.
  • a second data distribution signal is provided to each second driving unit.
  • the control unit may be respectively coupled to the input terminals of the plurality of first driving units and the input terminals of the plurality of second driving units, and control the input terminals of the plurality of first driving units and the plurality of second driving units according to the power-on reset signal The input terminal of the unit is short-circuited or disconnected.
  • the first driving unit and the second driving unit may be a positive frame driving unit and a negative frame driving unit, respectively, and the first data signal provided by the first driving unit and the second data signal provided by the second driving unit may be Provided to different data lines to charge the pixel electrodes of different sub-pixels.
  • the short-term line afterimage can be improved by separately controlling the first data signal and the second data signal with different voltage polarities. Take the voltage polarity of the first data signal as positive and the voltage polarity of the second data signal as negative as an example for description.
  • FIG. 3 is a schematic diagram of separate control of the first data signal and the second data signal of different voltage polarities. As shown in FIG. 3, 215 is the pixel voltage actually charged by the pixel electrode of the positive frame sub-pixel during the positive frame driving, and 216 is the data voltage provided by the first data signal during the positive frame driving; 217 is the negative frame sub-pixel during negative frame driving. The pixel voltage actually charged by the pixel electrode of the pixel 218 is the data voltage provided by the second data signal during negative frame driving.
  • the falling edge delay time D of the second data signal is greater than the rising edge delay time Tr of the first data signal (Tr is 0 as shown in FIG. 3).
  • Tr rising edge delay time
  • the actual charging voltage of the sub-pixels in the positive frame and the actual charging voltage of the sub-pixels in the negative frame are symmetrical with respect to the common voltage.
  • the black to white first line position is biased to improve the line afterimage.
  • FIG. 4 is a schematic diagram of power supply of a data driver provided by an embodiment of the present disclosure.
  • the data driver provided in this embodiment is powered by a timing controller (Timer Control, TCON).
  • TCON is configured to provide a variety of voltage signals that support the operation of the data driver.
  • the TCON includes an integrated power management circuit (Power Management Integrated Circuit, PMIC), and the PMIC is configured to output a digital power signal, an analog power signal, a semi-analog power signal, etc. according to an input signal.
  • PMIC Power Management Integrated Circuit
  • the PMIC is configured to output a digital power signal, an analog power signal, a semi-analog power signal, etc. according to an input signal.
  • PMIC Power Management Integrated Circuit
  • a voltage signal is provided to the data driver through a boost circuit.
  • TCON includes a PMIC and a boost circuit.
  • the PMIC is configured to output an analog power signal AVDD and a semi-analog power signal HAVDD according to the input signal Vin
  • the boost circuit is configured to output an analog power signal AVDDS according to the input signal Vin;
  • the voltages of the analog power signals AVDD and AVDDS are the same.
  • the TCON can be powered by the analog power signal AVDD generated by the PMIC.
  • the data driver provided in this embodiment can be powered by the analog power signal AVDDS generated by the boost circuit to provide driving capability.
  • the first data distribution signal and the second data signal with different voltage polarities are controlled separately, during a power-on reset (Power On Reset), the first data distribution signal and the second data signal provided by the data distribution unit in the data driver are controlled separately.
  • the climbing speed of the two data distribution signals will be inconsistent, resulting in the output voltage of the first driving unit and the output voltage of the second driving unit being inconsistent, and before the power-on reset is released, the data driver will have a charge sharing process, namely The output terminals of the first driving unit and the second driving unit will be short-circuited together.
  • FIG. 6 is a schematic structural diagram of a data driver provided by an embodiment of the disclosure.
  • the data driver provided by the embodiment of the present disclosure includes: a data distribution unit 31, a control unit 32, a first driving unit 33, a second driving unit 34, and a charge sharing unit 35.
  • the data distribution unit 31 provides a first data distribution signal Vbias-P to the input terminal of the first driving unit 33, and the data distribution unit 31 provides a second data distribution signal Vbias-P to the input terminal of the second driving unit 34.
  • the first driving unit 33 is configured to generate the first data signal Sout1 according to the first data distribution signal Vbias-P
  • the second driving unit 34 is configured to generate the second data signal Sout2 according to the second data distribution signal Vbias-N.
  • the voltage polarities of the first data signal and the second data signal are different. In this example, the voltage polarity of the first data signal is positive, and the voltage polarity of the second data signal is negative.
  • control unit 32 is respectively coupled to the input terminal of the first driving unit 33 and the input terminal of the second driving unit 34.
  • the control unit 32 does not detect the power-on reset signal (that is, before the power-on reset), it controls the input terminal of the first driving unit 33 and the input terminal of the second driving unit 34 to be short-circuited, so that the first driving unit 33 and the second driving unit 34 are short-circuited.
  • the units 34 maintain a short-circuit state, that is, the first data distribution signal Vbis-P and the second data distribution signal Vbis-N maintain the same potential, so that the large current drawn disappears and the boost circuit is prevented from being burned.
  • the control unit 32 When the control unit 32 detects the power-on reset signal, the control unit 32 controls the input end of the first drive unit 33 and the input end of the second drive unit 34 to be disconnected, so that the first drive unit 33 and the second drive unit 34 are disconnected from each other. Maintain an open circuit state to achieve separate control of the first data distribution signal Vbis-P and the second data distribution signal Vbis-N, thereby separately controlling the output of the first data signal Sout1 output by the first driving unit 33 and the output of the second driving unit 34
  • the second data signal Sout2 of the second data signal for example, controls the falling edge delay time of the second data signal to be greater than the rising edge delay time of the first data signal, so as to improve the short-term line afterimage.
  • the power-on reset signal may be generated when the data driver starts to output after power-on.
  • the power-on reset signal may indicate a period in which the data driver starts to output the data signal.
  • the power-on reset signal may be generated by a power-on reset circuit, and the control unit 32 may be coupled to the power-on reset circuit to detect the power-on reset signal.
  • the control unit 32 can control the input terminal of the first drive unit 33 and the input terminal of the second drive unit 34 to disconnect when detecting the power-on reset signal, and can control the input terminal and the second drive unit 33 of the first drive unit 33 during the rest of the time.
  • the input terminal of unit 34 is short-circuited.
  • control unit 32 may control the input terminal of the first driving unit 33 and the input terminal of the second driving unit 34 to be disconnected when the power-on reset signal of the first potential is detected, wherein the first potential may be a high potential or Low level.
  • the present disclosure does not limit the generation method and form of the power-on reset signal.
  • control unit 32 may include one or more switching transistors.
  • the implementation of the control unit 32 is not limited to this, as long as its function can be realized.
  • the output terminals of the first driving unit 33 and the second driving unit 34 are respectively coupled to the charge sharing unit 35.
  • the charge sharing unit 35 can make the output terminals of the first driving unit 33 and the second driving unit 34 perform charge sharing under the control of the charge sharing control signal, that is, short-circuit the output terminals of the first driving unit 33 and the second driving unit 34 , To reduce power consumption.
  • the charge sharing unit 35 may include one or more switching transistors.
  • the present disclosure does not limit the implementation of the charge sharing unit 35, as long as its function can be realized.
  • FIG. 7 is a schematic diagram of a first data distribution signal and a second data distribution signal in an embodiment of the disclosure.
  • the first data distribution signal Vbias-P and the second data distribution signal Vbias-N are the same, there is no voltage difference between the two, and no pumping is caused during the charge sharing process. Load high current is generated, which can prevent the boost circuit from being burnt.
  • FIG. 8 is a schematic structural diagram of a data driver according to an embodiment of the disclosure.
  • the data distribution unit 31 includes: a first digital-to-analog converter (DAC, Digital to Analog Converter) 311 and a second digital-to-analog converter Converter 312; the first driving unit includes a first operational amplifier 331, and the second driving unit includes a second operational amplifier 341.
  • the output terminal of the first digital-to-analog converter 311 is coupled to the input terminal of the first operational amplifier 331, and the output terminal of the second digital-to-analog converter 312 is coupled to the input terminal of the second operational amplifier 341.
  • the output terminals of the first operational amplifier 331 and the second operational amplifier 341 are respectively coupled to the charge sharing unit 35.
  • the first operational amplifier 331 can be a positive signal amplifier
  • the second operational amplifier 341 can be a negative signal amplifier.
  • the first digital-to-analog converter 311 is configured to receive the analog power signal AVDDS and the semi-analog power signal HAVDD; the second digital-to-analog converter 312 is configured to receive the semi-analog power signal HAVDD and the ground signal GND.
  • the first digital-to-analog converter 311 can generate a first data distribution signal Vbias-P and provide it to the input terminal of the first operational amplifier 331; the second digital-to-analog converter 312 can generate a second data distribution signal Vbias-N and provide
  • the second operational amplifier 312 is provided to support the first operational amplifier 331 and the second operational amplifier 341 to generate independent currents (as shown by the dotted line in FIG. 8).
  • the entire data driver when the control unit 32 does not receive the power-on reset signal, the entire data driver can work in a charge sharing state, that is, the output terminals of all channels are short-circuited together through the charge sharing unit 35 to neutralize
  • the control unit 32 can control the output terminal of the first data converter 311 and the output terminal of the second data converter 312 to short-circuit, that is, control the first data distribution signal Vias-P and the second data distribution signal Vbias-N maintains the same potential; after the control unit 32 detects or receives the power-on reset signal, the control unit 32 controls the output terminal of the first data converter 311 and the output terminal of the second data converter 312 to disconnect, so that the first The operational amplifier 331 and the second operational amplifier 341 can work separately to generate a negative frame data signal with a larger falling edge delay time, so as to improve short-term line afterimages.
  • FIG. 9 is a schematic diagram of the effect of the data driver according to the embodiment of the disclosure.
  • the current I-AVDD of the data driver is not abnormally large, and the output terminal Sout1 is not abnormally raised. It can be seen that the data driver provided in this embodiment can solve the problem of large current drawn as shown in FIG. 5, thereby improving circuit stability and safety.
  • the abscissa in Fig. 5 and Fig. 9 represents time (t).
  • FIG. 10 is a schematic diagram of a work flow of a data driver provided by an embodiment of the disclosure.
  • the data driver in this embodiment may be as shown in FIG. 6.
  • the working process of the data driver provided in this embodiment may include the following steps.
  • Step 401 The data driver is powered on.
  • the data driver receives the voltage signal provided by TCON, for example, including the analog power signal AVDDS and the semi-analog power signal HAVDD.
  • Step 402 The control unit of the data driver determines whether the power-on reset signal is detected; if the power-on reset signal is detected, step 404 is executed, and if the power-on reset signal is not detected, step 403 is executed.
  • the power-on reset signal is generated when the data driver starts to output after power-on.
  • the power-on reset signal may indicate a period in which the data driver starts to output the data signal.
  • Step 403 The control unit does not detect the power-on reset signal, and short-circuits the input terminal of the first drive unit and the input terminal of the second drive unit; then, returns to step 402 to continue to determine whether the power-on reset signal is detected.
  • Step 404 The control unit detects the power-on reset signal, and disconnects the input terminal of the first drive unit and the input terminal of the second drive unit, so that the data distribution unit can provide the first data distribution signal and the second data distribution independent of each other
  • the signals are respectively provided to the first driving unit and the second driving unit.
  • the data driver can normally provide the first data signal and the second data signal to the data line through the first driving unit and the second driving unit.
  • Step 405 After the data driver normally provides the data signal to the data line, it can perform charge sharing through the charge sharing unit.
  • Step 406 The data driver is powered off, that is, TCON stops supplying power to the data driver.
  • the data driver provided by the embodiments of the present disclosure can improve the short-term line afterimage of the large-size and high-resolution liquid crystal display device during the startup process, and can solve the problem of large current drawn, thereby improving circuit stability and safety.
  • the embodiment of the present disclosure also provides a data driver control method, which is applied to the above-mentioned data driver.
  • the control method provided in this embodiment includes: the control unit controls the input terminal and the first drive unit according to a power-on reset signal.
  • the input terminal of the second drive unit is short-circuited or disconnected.
  • control unit controls the input terminal of the first driving unit and the input terminal of the second driving unit to be short-circuited or disconnected according to the power-on reset signal, including:
  • control unit When the control unit does not detect the power-on reset signal, it controls the input terminal of the first drive unit and the input terminal of the second drive unit to short-circuit;
  • control unit When the control unit detects the power-on reset signal, it controls the input terminal of the first driving unit and the input terminal of the second driving unit to be disconnected.
  • An embodiment of the present disclosure also provides a display device, which includes the data driver described in the foregoing embodiment.
  • the display device may include a plurality of data drivers described in the foregoing embodiments.
  • the display device of this embodiment may be any product or component with display function, such as a liquid crystal display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the orientation or positional relationship indicated by “outside” is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, It is constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present disclosure.

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Abstract

一种数据驱动器，包括：控制单元（32）、数据分配单元（31）、第一驱动单元（33）和第二驱动单元（34）；数据分配单元（31）分别与第一驱动单元（33）的输入端和第二驱动单元（34）的输入端耦接，配置为向第一驱动单元（33）的输入端提供第一数据分配信号（Vbias-P），向第二驱动单元（34）的输入端提供第二数据分配信号（Vbias-N）；第一驱动单元（33）配置为根据第一数据分配信号（Vbias-P）生成第一数据信号（Sout1），第二驱动单元（34）配置为根据第二数据分配信号（Vbias-N）生成第二数据信号（Sout2），且第一数据信号（Sout1）和第二数据信号（Sout2）的电压极性不同；控制单元（32），分别与第一驱动单元（33）的输入端和第二驱动单元（34）的输入端耦接，配置为根据上电复位信号，控制第一驱动单元（33）的输入端和第二驱动单元（34）的输入端短路或断开。

Description

数据驱动器及其控制方法、显示装置
本申请要求于2020年3月19日提交中国专利局、申请号为202010206097.7、发明名称为“数据驱动器及其控制方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，尤指一种数据驱动器及其控制方法、显示装置。
背景技术
随着液晶显示技术的不断发展，大尺寸、高分辨率的液晶显示装置得到人们的广泛关注。然而，由于液晶显示装置的面板尺寸大且分辨率高，单个像素的充电时间较短，会导致充电率不足，进而造成短期线残像，而且还存在抽载(Inrush)大电流问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种数据驱动器及其控制方法、显示装置。
一方面，本公开提供一种数据驱动器，包括：控制单元、数据分配单元、第一驱动单元和第二驱动单元；所述数据分配单元分别与第一驱动单元的输入端和第二驱动单元的输入端耦接，配置为向第一驱动单元的输入端提供第一数据分配信号，向第二驱动单元的输入端提供第二数据分配信号；所述第一驱动单元配置为根据所述第一数据分配信号生成第一数据信号，所述第二驱动单元配置为根据所述第二数据分配信号生成第二数据信号，且第一数据信号和第二数据信号的电压极性不同；所述控制单元，分别与所述第一驱动单元的输入端和第二驱动单元的输入端耦接，配置为根据上电复位信号，控 制所述第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
另一方面，本公开提供一种显示装置，包括如上所述的数据驱动器。
另一方面，本公开提供一种数据驱动器的控制方法，应用于如上所述的数据驱动器，所述控制方法包括：所述控制单元根据上电复位信号，控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为液晶显示装置中的薄膜晶体管的栅源电压(Vgs)与充电电流(Ids)的关系图；
图2为不同电压极性的数据信号的实际像素充电电压相对于公共电压不对称的示意图；
图3为本公开一实施例中的不同电压极性的第一数据信号和第二数据信号分开控制的示意图；
图4为本公开一实施例提供的数据驱动器的供电示意图；
图5为抽载大电流的示意图；
图6为本公开一实施例提供的数据驱动器的结构示意图；
图7为本公开一实施例中第一数据分配信号和第二数据分配信号的示意图；
图8为本公开另一实施例提供的数据驱动器的结构示意图；
图9为本公开一实施例的数据驱动器的效果示意图；
图10为本公开一实施例的数据驱动器的工作流程示意图。
具体实施方式
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的方案。任何实施例的任何特征或元件也可以与来自其它方案的特征或元件组合，以形成另一个由权利要求限定的独特的方案。因此，应当理解，在本公开中示出或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行一种或多种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
在附图中，有时为了明确起见，夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
除非另外定义，本公开使用的技术术语或科学术语为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以 及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。本公开中，“多个”可以表示两个或两个以上的数目。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“耦接”、“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“电性的连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且可以包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
液晶显示装置包括栅极驱动电路、源极驱动电路、多条扫描线、多条数据线以及由扫描线和数据线交叉形成的多个子像素区域，多条扫描线连接至栅极驱动电路，栅极驱动电路通过多条扫描线给多个子像素提供栅极驱动信号；多条数据线连接至源极驱动电路，源极驱动电路通过多条数据线给多个子像素提供显示信号。每个子像素区域中设置有薄膜晶体管(TFT，Thin Film Transistor)，薄膜晶体管的栅极与扫描线耦接，薄膜晶体管的源极与数据线连接，薄膜晶体管的漏极与像素电极耦接。通过扫描线的信号可以控制薄膜晶体管的通断，从而控制是否将数据线的信号(即数据信号)写入像素电极。液晶显示装置的每一个子像素的发光亮度是由其像素电极与公共电极之间施加的电压差决定的。
为了防止液晶极化，液晶显示装置多采用极性反转的驱动方式，即需要将输入到子像素的数据信号的电压的正负极性进行切换。极性反转的驱动方式包括帧反转、行反转、列反转和点反转。比如，针对相邻两帧画面，一帧画面中输入至像素电极的数据信号的电压极性为正(即进行正帧驱动)，另一帧画面中输入到像素电极的数据信号的电压极性为负(即进行负帧驱动)； 或者，针对相邻两行子像素，输入至一行子像素的像素电极的数据信号的电压极性为正，输入另一行子像素的像素电极的数据信号的电压极性为负。
图1为液晶显示装置中的TFT的栅源电压(Vgs)与充电电流(Ids)的关系图。在图1中，横坐标为TFT的栅源电压，单位为伏特(V)；纵坐标为TFT的充电电流，单位为安培(A)。由图1可见，在Vgs大于-10V时，Vgs越大，充电电流越大，像素电极完全充电所需的时间越短(即充电快)，而Vgs越小，充电电流越小，像素电极完全充电所需的时间较长(即充电慢)。
图2为不同电压极性的数据信号的实际像素充电电压相对于公共电压(Vcom)不对称的示意图。在图2中，211为正帧驱动时正帧子像素的像素电极实际充入的像素电压，可以称为正帧原始像素电压，212为正帧驱动时正帧子像素耦接的数据线输入的数据电压，可以称为正帧原始数据电压；213为负帧驱动时负帧子像素的像素电极上实际充入的像素电压，可以称为负帧原始像素电压，214为负帧驱动时负帧子像素耦接的数据线输入的数据电压，可以称为负帧原始数据电压。由图2可以看到，正帧驱动时将像素电极的像素电压充至正帧原始数据电压212所需的时长，大于负帧驱动时将像素电极的像素电压充至负帧原始数据电压214所需的时长。
如图2所示，针对第M行的子像素，正帧子像素此时的像素电压还未达到正帧原始数据电压212，而负帧子像素此时的像素电压已达到负帧原始数据电压214，使得第M行正帧子像素的像素电极上的正帧原始像素电压211和第M行负帧子像素的像素电极上的负帧原始像素电压213相对于公共电压(Vcom)不对称，即正帧驱动与负帧驱动下，第M行正帧子像素的正帧原始像素电压211与公共电压之间的压差的绝对值A1，与第M行负帧子像素的负帧原始像素电压213与公共电压之间的压差的绝对值A2不相等。其中，A1和A2之间存在较大的偏差，该偏差为一直流分量。
如图2所示，第M+1行正帧子像素的像素电压可以达到正帧原始数据电压，则第M+1行正帧子像素的像素电极上的正帧原始像素电压与第M+1行负帧子像素的像素电极上的负帧原始像素电压相对于公共电压对称，即正帧驱动和负帧驱动下，第M+1行正帧子像素的正帧原始像素电压与公共电压之间的压差的绝对值B1，与第M+1行负帧子像素的负帧原始像素电压与公共 电压之间的压差的绝对值B2相等。
在实际充电时，当液晶显示装置由黑到白变化时，负帧子像素的驱动晶体管的Vgs约为32V，负帧子像素充电速度快，正帧子像素的驱动晶体管的Vgs约为16V，正帧子像素充电速度慢，导致正帧子像素和负帧子像素的实际像素充电电压关于公共电压Vcom不对称，会在黑到白首行产生明显直流偏置电压，导致短期直流线残影。
由于大尺寸、高分辨率的液晶显示装置的充电率不足且驱动晶体管的Vgs对充电率存在影响，导致正帧子像素和负帧子像素的充电率有明显差异，会导致液晶显示装置的黑白分界线有明显偏压，存在严重的短期线残像。
本公开实施例提供一种数据驱动器及其控制方法、显示装置，可以改善短期线残像，而且可以抑制存在的抽载大电流问题，从而提高电路稳定性和安全性。
本公开实施例提供一种数据驱动器，包括：控制单元、数据分配单元、第一驱动单元和第二驱动单元；数据分配单元分别与第一驱动单元的输入端和第二驱动单元的输入端耦接，配置为向第一驱动单元的输入端提供第一数据分配信号，向第二驱动单元的输入端提供第二数据分配信号；第一驱动单元配置为根据第一数据分配信号生成第一数据信号，第二驱动单元配置为根据第二数据分配信号生成第二数据信号，且第一数据信号和第二数据信号的电压极性不同；控制单元，分别与第一驱动单元的输入端和第二驱动单元的输入端耦接，配置为根据上电复位信号，控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
在本实施例中，第一驱动单元的数目可以为多个，第二驱动单元的数目可以为多个，且数据分配单元可以分别给每个第一驱动单元提供第一数据分配信号，可以分别给每个第二驱动单元提供第二数据分配信号。控制单元可以分别与多个第一驱动单元的输入端和多个第二驱动单元的输入端耦接，并根据上电复位信号，控制多个第一驱动单元的输入端和多个第二驱动单元的输入端短路或断开。在本实施例中，第一驱动单元和第二驱动单元可以分别为正帧驱动单元和负帧驱动单元，第一驱动单元提供的第一数据信号和第二驱动单元提供的第二数据信号可以提供给不同的数据线，从而给不同子像素 的像素电极充电。
在本实施例中，可以通过对不同电压极性的第一数据信号和第二数据信号进行分开控制，来改善短期线残像。以第一数据信号的电压极性为正，第二数据信号的电压极性为负为例进行说明。图3为不同电压极性的第一数据信号和第二数据信号分开控制的示意图。如图3所示，215为正帧驱动时正帧子像素的像素电极实际充入的像素电压，216为正帧驱动时第一数据信号提供的数据电压；217为负帧驱动时负帧子像素的像素电极实际充入的像素电压，218为负帧驱动时第二数据信号提供的数据电压。第二数据信号的下降沿延时时长D大于第一数据信号的上升沿延时时长Tr(如图3所示Tr为0)。在图3中，正帧子像素的实际充电电压与负帧子像素的实际充电电压相对于公共电压对称。相较于图2所示的正帧原始像素电压与负帧原始像素电压相对于公共电压不对称的情况，在本实施例中，通过增加负帧像素电压的下降沿延时时长，可以抵消从黑到白的首行位置偏压，从而改善线残像。
图4为本公开一实施例提供的数据驱动器的供电示意图。本实施例提供的数据驱动器由时序控制器(Timer Control，TCON)供电。TCON配置为提供支持数据驱动器工作的多种电压信号。通常，TCON包括集成电源管理电路(Power Management Integrated Circuit，PMIC)，PMIC配置为根据输入信号输出数字电源信号、模拟电源信号、半模拟电源信号等。针对大尺寸、高分辨率的液晶显示装置，由于所需的模拟电源功率过大，单个PMIC无法负担，因此，本示例性实施例中，通过升压(Boost)电路向数据驱动器提供电压信号。如图4所示，TCON包括PMIC和升压电路，PMIC配置为根据输入信号Vin输出模拟电源信号AVDD和半模拟电源信号HAVDD，升压电路配置为根据输入信号Vin输出模拟电源信号AVDDS；其中，模拟电源信号AVDD和AVDDS的电压大小一致。TCON可以使用由PMIC产生的模拟电源信号AVDD进行供电，本实施例提供的数据驱动器可以使用由升压电路产生的模拟电源信号AVDDS进行供电，以提供驱动能力。
在本实施例中，由于不同电压极性的第一数据信号和第二数据信号分开控制，在上电复位(Power On Reset)时，数据驱动器内数据分配单元提供的第一数据分配信号和第二数据分配信号的爬升速度会不一致，导致第一驱动 单元的输出电压和第二驱动单元的输出电压会不一致，而且，上电复位解除前，数据驱动器会有电荷共享(Charge Sharing)过程，即第一驱动单元和第二驱动单元的输出端会短接在一起，因此，第一驱动单元和第二驱动单元之间会有短暂很大的抽载(Inrush)电流(如图5中的虚线框所示，当使用多个数据驱动器时，短暂抽载电流I-AVDDS可以达到10A)，较大的抽载电流会造成TCON的升压电路被烧毁。
本公开实施例提供的数据驱动器通过设置控制单元来解决上述抽载大电流问题。图6为本公开一实施例提供的数据驱动器的结构示意图。如图6所示，本公开实施例提供的数据驱动器包括：数据分配单元31、控制单元32、第一驱动单元33、第二驱动单元34以及电荷共享单元35。
如图6所示，数据分配单元31向第一驱动单元33的输入端提供第一数据分配信号Vbias-P，数据分配单元31向第二驱动单元34的输入端提供第二数据分配信号Vbias-N；第一驱动单元33配置为根据第一数据分配信号Vbias-P生成第一数据信号Sout1，第二驱动单元34配置为根据第二数据分配信号Vbias-N生成第二数据信号Sout2。其中，第一数据信号和第二数据信号的电压极性不同。在本示例中，第一数据信号的电压极性为正，第二数据信号的电压极性为负。
在本实施例中，控制单元32分别与第一驱动单元33的输入端和第二驱动单元34的输入端耦接。控制单元32在未检测到上电复位信号时(即上电复位之前)，控制第一驱动单元33的输入端和第二驱动单元34的输入端短路，使得第一驱动单元33和第二驱动单元34之间保持短路状态，即第一数据分配信号Vbis-P和第二数据分配信号Vbis-N保持相同电位，从而使得抽载大电流消失，避免升压电路被烧毁。控制单元32在检测到上电复位信号时，控制单元32控制第一驱动单元33的输入端和第二驱动单元34的输入端断开，使得第一驱动单元33和第二驱动单元34之间保持开路状态，以实现对第一数据分配信号Vbis-P和第二数据分配信号Vbis-N进行单独控制，从而单独控制第一驱动单元33输出的第一数据信号Sout1和第二驱动单元34输出的第二数据信号Sout2，比如，控制第二数据信号的下降沿延时时长大于第一数据信号的上升沿延时时长，以改善短期线残像。
在本实施例中，上电复位信号可以在数据驱动器上电后开始输出时产生。上电复位信号可以指示数据驱动器开始输出数据信号的时段。例如，上电复位信号可以由上电复位电路产生，控制单元32可以耦接上电复位电路，来检测上电复位信号。控制单元32可以在检测到上电复位信号时，控制第一驱动单元33的输入端和第二驱动单元34的输入端断开，其余时间可以控制第一驱动单元33的输入端和第二驱动单元34的输入端短路。比如，控制单元32可以在检测到第一电位的上电复位信号时，控制第一驱动单元33的输入端和第二驱动单元34的输入端断开，其中，第一电位可以为高电位或低电平。本公开对于上电复位信号的产生方式以及形式并不限定。
在一示例性实施方式中，控制单元32可以包括一个或多个开关晶体管。然而，控制单元32的实现方式不限于此，只要能够实现其功能即可。
如图6所示，第一驱动单元33和第二驱动单元34的输出端分别与电荷共享单元35耦接。电荷共享单元35可以在电荷共享控制信号的控制下，使得第一驱动单元33和第二驱动单元34的输出端进行电荷分享，即短接第一驱动单元33和第二驱动单元34的输出端，以降低功耗。其中，电荷共享单元35可以包括一个或多个开关晶体管。然而，本公开对于电荷共享单元35的实现方式并不限定，只要能够实现其功能即可。
图7为本公开实施例中第一数据分配信号和第二数据分配信号的示意图。如图7所示，在控制单元32的控制下，第一数据分配信号Vbias-P和第二数据分配信号Vbias-N相同，两者之间没有压差，在电荷共享过程中不会导致抽载大电流产生，可以避免升压电路被烧毁。
图8为本公开一实施例的数据驱动器的结构示意图。如图8所示，在图6所示的数据驱动器的基础上，在本实施例中，数据分配单元31包括：第一数模转换器(DAC，Digital to Analog Converter)311和第二数模转换器312；第一驱动单元包括第一运算放大器331，第二驱动单元包括第二运算放大器341。第一数模转换器311的输出端与第一运算放大器331的输入端耦接，第二数模转换器312的输出端与第二运算放大器341的输入端耦接。第一运算放大器331和第二运算放大器341的输出端分别与电荷共享单元35耦接。比如，第一运算放大器331可以为正性信号放大器，第二运算放大器341可以 为负性信号放大器。
如图8所示，第一数模转换器311配置为接收模拟电源信号AVDDS和半模拟电源信号HAVDD；第二数模转换器312配置为接收半模拟电源信号HAVDD和接地信号GND。第一数模转换器311可以产生第一数据分配信号Vbias-P，并提供给第一运算放大器331的输入端；第二数模转换器312可以产生第二数据分配信号Vbias-N，并提供给第二运算放大器312，以支持第一运算放大器331和第二运算放大器341产生独立的电流(如图8中所示的虚线)。
在本实施例中，控制单元32没有接收到上电复位信号时，整个数据驱动器可以工作在电荷共享状态，即通过电荷共享单元35将所有通道的输出端都短接在一起，起到中和正负电荷的作用，而且，控制单元32可以控制第一数据转换器311的输出端和第二数据转换器312的输出端短路，即控制第一数据分配信号Vias-P和第二数据分配信号Vbias-N保持相同电位；在控制单元32检测或接收到上电复位信号后，控制单元32控制第一数据转换器311的输出端和第二数据转换器312的输出端断开，使得第一运算放大器331和第二运算放大器341可以分开工作，产生下降沿延时时长较大的负帧数据信号，以改善短期线残像。
图9为本公开实施例的数据驱动器的效果示意图。如图9所示，相较于图5所示，在相同上电条件下，数据驱动器的抽载电流I-AVDD没有异常大电流，而且输出端Sout1没有异常抬起。由此可见，本实施例提供的数据驱动器可以解决图5所示的抽载大电流问题，从而可以提高电路稳定性和安全性。图5和图9中横坐标表示时间(t)。
图10为本公开实施例提供的数据驱动器的工作流程示意图。本实施例中的数据驱动器可以如图6所示。如图10所示，本实施例提供的数据驱动器的工作流程可以包括以下步骤。
步骤401、数据驱动器上电。例如，数据驱动器接收到TCON提供的电压信号，比如，包括模拟电源信号AVDDS、半模拟电源信号HAVDD。
步骤402、数据驱动器的控制单元判断是否检测到上电复位信号；若检测到上电复位信号，则执行步骤404，若没有检测到上电复位信号，则执行 步骤403。其中，上电复位信号在数据驱动器上电后开始输出时产生。上电复位信号可以指示数据驱动器开始输出数据信号的时段。
步骤403、控制单元没有检测到上电复位信号，将第一驱动单元的输入端和第二驱动单元的输入端短路；然后，返回步骤402，继续判断是否检测到上电复位信号。
步骤404、控制单元检测到上电复位信号，将第一驱动单元的输入端和第二驱动单元的输入端断开，使得数据分配单元可以提供相互独立的第一数据分配信号和第二数据分配信号，分别提供给第一驱动单元和第二驱动单元。在本阶段中，数据驱动器可以通过第一驱动单元和第二驱动单元正常向数据线提供第一数据信号和第二数据信号。
步骤405、数据驱动器在正常向数据线提供数据信号后，可以通过电荷共享单元进行电荷共享。
步骤406、数据驱动器关电，即TCON停止给数据驱动器供电。
本公开实施例提供的数据驱动器可以改善大尺寸、高分辨率的液晶显示装置在启动过程的短期线残像，而且可以解决存在的抽载大电流问题，从而可以提高电路稳定性和安全性。
本公开实施例还提供一种数据驱动器的控制方法，应用于如上所述的数据驱动器，本实施例提供的控制方法包括：控制单元根据上电复位信号，控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
在一示例性实施方式中，控制单元根据上电复位信号，控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开，包括：
控制单元在未检测到上电复位信号时，控制第一驱动单元的输入端和第二驱动单元的输入端短接；
控制单元在检测到所述上电复位信号时，控制第一驱动单元的输入端和第二驱动单元的输入端断开。
关于本实施例中的数据驱动器的结构和工作过程可以参照上述实施例的描述，故于此不再赘述。
本公开实施例还提供了一种显示装置，该显示装置包括采用前述实施例 所述的数据驱动器。其中，显示装置可以包括多个前述实施例所述的数据驱动器。本实施例的显示装置可以为：液晶显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例的描述中，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (9)

  1. 一种数据驱动器，包括：
    控制单元、数据分配单元、第一驱动单元和第二驱动单元；
    所述数据分配单元分别与第一驱动单元的输入端和第二驱动单元的输入端耦接，配置为向第一驱动单元的输入端提供第一数据分配信号，向第二驱动单元的输入端提供第二数据分配信号；
    所述第一驱动单元配置为根据所述第一数据分配信号生成第一数据信号，所述第二驱动单元配置为根据所述第二数据分配信号生成第二数据信号，且所述第一数据信号和第二数据信号的电压极性不同；
    所述控制单元，分别与所述第一驱动单元的输入端和第二驱动单元的输入端耦接，配置为根据上电复位信号，控制所述第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
  2. 根据权利要求1所述的数据驱动器，其中，所述控制单元配置为未检测到所述上电复位信号时，控制所述第一驱动单元的输入端和第二驱动单元的输入端短路；检测到所述上电复位信号时，控制所述第一驱动单元的输入端和第二驱动单元的输入端断开。
  3. 根据权利要求1所述的数据驱动器，其中，所述数据分配单元，包括：第一数模转换器和第二数模转换器；所述第一驱动单元包括第一运算放大器，所述第二驱动单元包括第二运算放大器；
    所述第一数模转换器的输出端与所述第一运算放大器的输入端耦接，所述第二数模转换器的输出端与所述第二运算放大器的输入端耦接。
  4. 根据权利要求1所述的数据驱动器，其中，所述第一数据信号的电压极性为正，所述第二数据信号的电压极性为负，且所述第二数据信号的下降沿延时时长大于所述第一数据信号的上升沿延时时长。
  5. 根据权利要求1所述的数据驱动器，其中，所述数据分配单元配置为接收由时序控制器内的升压电路产生的模拟电源信号和由时序控制器内的集成电源管理电路产生的半模拟电源信号。
  6. 根据权利要求1所述的数据驱动器，还包括：电荷共享单元，所述电 荷共享单元分别与所述第一驱动单元的输出端和第二驱动单元的输出端耦接。
  7. 一种显示装置，包括：如权利要求1至6中任一项所述的数据驱动器。
  8. 一种数据驱动器的控制方法，应用于如权利要求1至6中任一项所述的数据驱动器，所述控制方法包括：
    所述控制单元根据上电复位信号，控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
  9. 根据权利要求8所述的控制方法，其中，所述控制单元根据上电复位信号，控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开，包括：
    所述控制单元在未检测到所述上电复位信号时，控制第一驱动单元的输入端和第二驱动单元的输入端短路；
    所述控制单元在检测到所述上电复位信号时，控制第一驱动单元的输入端和第二驱动单元的输入端断开。
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