WO2021184912A1 - 数据驱动器及其控制方法、显示装置 - Google Patents
数据驱动器及其控制方法、显示装置 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 29
- 230000000630 rising effect Effects 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 19
- 239000004973 liquid crystal related substance Substances 0.000 description 15
- 206010047571 Visual impairment Diseases 0.000 description 9
- 239000010409 thin film Substances 0.000 description 7
- 238000005086 pumping Methods 0.000 description 5
- 239000000470 constituent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/025—Reduction of instantaneous peaks of current
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/026—Arrangements or methods related to booting a display
Definitions
- the present disclosure relates to, but is not limited to, the field of display technology, in particular to a data driver and its control method, and a display device.
- the present disclosure provides a data driver, a control method thereof, and a display device.
- the present disclosure provides a data driver including: a control unit, a data distribution unit, a first driving unit, and a second driving unit; the data distribution unit is connected to the input terminal of the first driving unit and the second driving unit, respectively.
- the input terminal is coupled to the input terminal and is configured to provide a first data distribution signal to the input terminal of the first driving unit, and to provide a second data distribution signal to the input terminal of the second driving unit;
- the data distribution signal generates a first data signal
- the second driving unit is configured to generate a second data signal according to the second data distribution signal, and the voltage polarities of the first data signal and the second data signal are different;
- the control The unit is respectively coupled to the input terminal of the first driving unit and the input terminal of the second driving unit, and is configured to control the input terminal of the first driving unit and the input terminal of the second driving unit according to a power-on reset signal Short circuit or disconnection.
- the present disclosure provides a display device including the data driver as described above.
- the present disclosure provides a data driver control method, which is applied to the data driver as described above, and the control method includes: the control unit controls the input terminal and the first drive unit according to a power-on reset signal.
- the input terminal of the second drive unit is short-circuited or disconnected.
- FIG. 1 is a diagram showing the relationship between the gate-source voltage (Vgs) and the charging current (Ids) of a thin film transistor in a liquid crystal display device;
- FIG. 2 is a schematic diagram showing that the actual pixel charging voltage of data signals with different voltage polarities is asymmetric with respect to the common voltage;
- FIG. 3 is a schematic diagram of separate control of the first data signal and the second data signal of different voltage polarities in an embodiment of the present disclosure
- FIG. 4 is a schematic diagram of power supply of a data driver provided by an embodiment of the present disclosure.
- Figure 5 is a schematic diagram of pumping large currents
- FIG. 6 is a schematic structural diagram of a data driver provided by an embodiment of the present disclosure.
- FIG. 7 is a schematic diagram of a first data distribution signal and a second data distribution signal in an embodiment of the present disclosure
- FIG. 8 is a schematic structural diagram of a data driver provided by another embodiment of the present disclosure.
- FIG. 9 is a schematic diagram of the effect of a data driver according to an embodiment of the present disclosure.
- FIG. 10 is a schematic diagram of a work flow of a data driver according to an embodiment of the disclosure.
- the present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art.
- the embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form a unique solution defined by the claims.
- Any feature or element of any embodiment can also be combined with features or elements from other solutions to form another unique solution defined by the claims. Therefore, it should be understood that any feature shown or discussed in this disclosure can be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other restrictions except for the restrictions made according to the appended claims and their equivalents.
- one or more modifications and changes may be made within the protection scope of the appended claims.
- the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As those of ordinary skill in the art will understand, other sequence of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims for the method or process should not be limited to performing their steps in the written order, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure.
- Electrode connection includes the case where the constituent elements are connected together by elements having a certain electrical function.
- An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
- Examples of “elements having a certain electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.
- the liquid crystal display device includes a gate driving circuit, a source driving circuit, a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel regions formed by crossing the scan lines and the data lines.
- the plurality of scan lines are connected to the gate driving circuit.
- the electrode driving circuit provides gate driving signals to the plurality of sub-pixels through a plurality of scan lines; the plurality of data lines are connected to the source driving circuit, and the source driving circuit provides display signals to the plurality of sub-pixels through the plurality of data lines.
- Each sub-pixel area is provided with a thin film transistor (TFT, Thin Film Transistor), the gate of the thin film transistor is coupled to the scan line, the source of the thin film transistor is connected to the data line, and the drain of the thin film transistor is coupled to the pixel electrode.
- TFT Thin Film Transistor
- the on-off of the thin film transistor can be controlled by the signal of the scan line, thereby controlling whether to write the signal of the data line (that is, the data signal) to the pixel electrode.
- the light-emitting brightness of each sub-pixel of the liquid crystal display device is determined by the voltage difference applied between the pixel electrode and the common electrode.
- the liquid crystal display device In order to prevent the polarization of the liquid crystal, the liquid crystal display device mostly adopts a driving method of polarity inversion, that is, it is necessary to switch the positive and negative polarity of the voltage of the data signal input to the sub-pixel.
- the driving mode of polarity inversion includes frame inversion, row inversion, column inversion and dot inversion.
- the voltage polarity of the data signal input to the pixel electrode in one frame is positive (that is, the positive frame drive is performed), and the voltage polarity of the data signal input to the pixel electrode in the other frame is Is negative (that is, negative frame driving is performed); or, for two adjacent rows of sub-pixels, the voltage polarity of the data signal input to the pixel electrode of one row of sub-pixels is positive, and the voltage polarity of the data signal input to the pixel electrode of the other row of sub-pixels The voltage polarity is negative.
- FIG. 1 is a diagram showing the relationship between the gate-source voltage (Vgs) and the charging current (Ids) of the TFT in the liquid crystal display device.
- Vgs gate-source voltage
- Ids charging current
- the abscissa is the gate-source voltage of the TFT, in volts (V);
- the ordinate is the charging current of the TFT, in amperes (A).
- FIG. 2 is a schematic diagram showing that the actual pixel charging voltage of data signals with different voltage polarities is asymmetric with respect to the common voltage (Vcom).
- 211 is the pixel voltage actually charged by the pixel electrode of the sub-pixel of the positive frame during the positive frame driving, which can be called the original pixel voltage of the positive frame
- 212 is the data line input of the positive frame sub-pixel coupling during the positive frame driving.
- the data voltage can be called the positive frame original data voltage
- 213 is the pixel voltage actually charged on the pixel electrode of the negative frame sub-pixel when the negative frame is driven, which can be called the negative frame original pixel voltage
- 214 is the negative frame when the negative frame is driven.
- the data voltage input from the data line coupled to the frame sub-pixels may be referred to as a negative frame original data voltage. It can be seen from FIG. 2 that the time required to charge the pixel voltage of the pixel electrode to the original data voltage 212 of the positive frame during positive frame driving is longer than the time required to charge the pixel voltage of the pixel electrode to the negative frame original data voltage 214 during negative frame driving. The length of time required.
- the pixel voltage of the positive frame sub-pixel has not yet reached the positive frame original data voltage 212, while the pixel voltage of the negative frame sub-pixel has reached the negative frame original data voltage.
- 214 making the positive frame original pixel voltage 211 on the pixel electrode of the positive frame sub-pixel in the Mth row and the negative frame original pixel voltage 213 on the pixel electrode of the negative frame sub-pixel in the Mth row asymmetric with respect to the common voltage (Vcom), That is, under positive frame driving and negative frame driving, the absolute value A1 of the voltage difference between the positive frame original pixel voltage 211 of the positive frame sub-pixels in the Mth row and the common voltage is the same as the negative frame original pixel of the negative frame sub-pixels in the Mth row The absolute value A2 of the voltage difference between the voltage 213 and the common voltage is not equal. Among them, there is a large deviation between A1 and A2, which is a direct current component.
- the pixel voltage of the sub-pixels in the positive frame of the M+1 row can reach the original data voltage of the positive frame, and the original pixel voltage of the positive frame on the pixel electrodes of the sub-pixels of the positive frame in the M+1 row is equal to the M+th pixel voltage.
- the negative frame original pixel voltage on the pixel electrode of the negative frame sub-pixels of 1 row is symmetrical with respect to the common voltage, that is, under positive frame driving and negative frame driving, the positive frame original pixel voltage and the common voltage of the positive frame sub-pixels in the M+1 row
- the absolute value B1 of the voltage difference therebetween is equal to the absolute value B2 of the voltage difference between the negative frame original pixel voltage of the negative frame sub-pixels in the M+1th row and the common voltage.
- the Vgs of the driving transistor of the negative frame sub-pixel is about 32V
- the charging speed of the negative frame sub-pixel is fast
- the Vgs of the driving transistor of the positive frame sub-pixel is about 16V.
- the charging speed of the positive frame sub-pixels is slow, causing the actual pixel charging voltages of the positive frame sub-pixels and the negative frame sub-pixels to be asymmetrical with respect to the common voltage Vcom, which will generate a significant DC bias voltage in the first black to white line, resulting in short-term DC line afterimages .
- the embodiments of the present disclosure provide a data driver, a control method thereof, and a display device, which can improve short-term line afterimages, and can suppress the existing problem of large current drawn, thereby improving circuit stability and safety.
- the embodiment of the present disclosure provides a data driver including: a control unit, a data distribution unit, a first driving unit, and a second driving unit; the data distribution unit is respectively coupled to the input terminal of the first driving unit and the input terminal of the second driving unit Connected, configured to provide a first data distribution signal to the input terminal of the first driving unit, and provide a second data distribution signal to the input terminal of the second driving unit; the first driving unit is configured to generate first data according to the first data distribution signal Signal, the second driving unit is configured to generate a second data signal according to the second data distribution signal, and the voltage polarities of the first data signal and the second data signal are different; the control unit is connected to the input terminal and the first driving unit respectively The input terminals of the two driving units are coupled, and are configured to control the input terminal of the first driving unit and the input terminal of the second driving unit to be short-circuited or disconnected according to the power-on reset signal.
- the number of the first drive unit may be multiple, the number of the second drive unit may be multiple, and the data distribution unit may provide each first drive unit with the first data distribution signal, respectively.
- a second data distribution signal is provided to each second driving unit.
- the control unit may be respectively coupled to the input terminals of the plurality of first driving units and the input terminals of the plurality of second driving units, and control the input terminals of the plurality of first driving units and the plurality of second driving units according to the power-on reset signal The input terminal of the unit is short-circuited or disconnected.
- the first driving unit and the second driving unit may be a positive frame driving unit and a negative frame driving unit, respectively, and the first data signal provided by the first driving unit and the second data signal provided by the second driving unit may be Provided to different data lines to charge the pixel electrodes of different sub-pixels.
- the short-term line afterimage can be improved by separately controlling the first data signal and the second data signal with different voltage polarities. Take the voltage polarity of the first data signal as positive and the voltage polarity of the second data signal as negative as an example for description.
- FIG. 3 is a schematic diagram of separate control of the first data signal and the second data signal of different voltage polarities. As shown in FIG. 3, 215 is the pixel voltage actually charged by the pixel electrode of the positive frame sub-pixel during the positive frame driving, and 216 is the data voltage provided by the first data signal during the positive frame driving; 217 is the negative frame sub-pixel during negative frame driving. The pixel voltage actually charged by the pixel electrode of the pixel 218 is the data voltage provided by the second data signal during negative frame driving.
- the falling edge delay time D of the second data signal is greater than the rising edge delay time Tr of the first data signal (Tr is 0 as shown in FIG. 3).
- Tr rising edge delay time
- the actual charging voltage of the sub-pixels in the positive frame and the actual charging voltage of the sub-pixels in the negative frame are symmetrical with respect to the common voltage.
- the black to white first line position is biased to improve the line afterimage.
- FIG. 4 is a schematic diagram of power supply of a data driver provided by an embodiment of the present disclosure.
- the data driver provided in this embodiment is powered by a timing controller (Timer Control, TCON).
- TCON is configured to provide a variety of voltage signals that support the operation of the data driver.
- the TCON includes an integrated power management circuit (Power Management Integrated Circuit, PMIC), and the PMIC is configured to output a digital power signal, an analog power signal, a semi-analog power signal, etc. according to an input signal.
- PMIC Power Management Integrated Circuit
- the PMIC is configured to output a digital power signal, an analog power signal, a semi-analog power signal, etc. according to an input signal.
- PMIC Power Management Integrated Circuit
- a voltage signal is provided to the data driver through a boost circuit.
- TCON includes a PMIC and a boost circuit.
- the PMIC is configured to output an analog power signal AVDD and a semi-analog power signal HAVDD according to the input signal Vin
- the boost circuit is configured to output an analog power signal AVDDS according to the input signal Vin;
- the voltages of the analog power signals AVDD and AVDDS are the same.
- the TCON can be powered by the analog power signal AVDD generated by the PMIC.
- the data driver provided in this embodiment can be powered by the analog power signal AVDDS generated by the boost circuit to provide driving capability.
- the first data distribution signal and the second data signal with different voltage polarities are controlled separately, during a power-on reset (Power On Reset), the first data distribution signal and the second data signal provided by the data distribution unit in the data driver are controlled separately.
- the climbing speed of the two data distribution signals will be inconsistent, resulting in the output voltage of the first driving unit and the output voltage of the second driving unit being inconsistent, and before the power-on reset is released, the data driver will have a charge sharing process, namely The output terminals of the first driving unit and the second driving unit will be short-circuited together.
- FIG. 6 is a schematic structural diagram of a data driver provided by an embodiment of the disclosure.
- the data driver provided by the embodiment of the present disclosure includes: a data distribution unit 31, a control unit 32, a first driving unit 33, a second driving unit 34, and a charge sharing unit 35.
- the data distribution unit 31 provides a first data distribution signal Vbias-P to the input terminal of the first driving unit 33, and the data distribution unit 31 provides a second data distribution signal Vbias-P to the input terminal of the second driving unit 34.
- the first driving unit 33 is configured to generate the first data signal Sout1 according to the first data distribution signal Vbias-P
- the second driving unit 34 is configured to generate the second data signal Sout2 according to the second data distribution signal Vbias-N.
- the voltage polarities of the first data signal and the second data signal are different. In this example, the voltage polarity of the first data signal is positive, and the voltage polarity of the second data signal is negative.
- control unit 32 is respectively coupled to the input terminal of the first driving unit 33 and the input terminal of the second driving unit 34.
- the control unit 32 does not detect the power-on reset signal (that is, before the power-on reset), it controls the input terminal of the first driving unit 33 and the input terminal of the second driving unit 34 to be short-circuited, so that the first driving unit 33 and the second driving unit 34 are short-circuited.
- the units 34 maintain a short-circuit state, that is, the first data distribution signal Vbis-P and the second data distribution signal Vbis-N maintain the same potential, so that the large current drawn disappears and the boost circuit is prevented from being burned.
- the control unit 32 When the control unit 32 detects the power-on reset signal, the control unit 32 controls the input end of the first drive unit 33 and the input end of the second drive unit 34 to be disconnected, so that the first drive unit 33 and the second drive unit 34 are disconnected from each other. Maintain an open circuit state to achieve separate control of the first data distribution signal Vbis-P and the second data distribution signal Vbis-N, thereby separately controlling the output of the first data signal Sout1 output by the first driving unit 33 and the output of the second driving unit 34
- the second data signal Sout2 of the second data signal for example, controls the falling edge delay time of the second data signal to be greater than the rising edge delay time of the first data signal, so as to improve the short-term line afterimage.
- the power-on reset signal may be generated when the data driver starts to output after power-on.
- the power-on reset signal may indicate a period in which the data driver starts to output the data signal.
- the power-on reset signal may be generated by a power-on reset circuit, and the control unit 32 may be coupled to the power-on reset circuit to detect the power-on reset signal.
- the control unit 32 can control the input terminal of the first drive unit 33 and the input terminal of the second drive unit 34 to disconnect when detecting the power-on reset signal, and can control the input terminal and the second drive unit 33 of the first drive unit 33 during the rest of the time.
- the input terminal of unit 34 is short-circuited.
- control unit 32 may control the input terminal of the first driving unit 33 and the input terminal of the second driving unit 34 to be disconnected when the power-on reset signal of the first potential is detected, wherein the first potential may be a high potential or Low level.
- the present disclosure does not limit the generation method and form of the power-on reset signal.
- control unit 32 may include one or more switching transistors.
- the implementation of the control unit 32 is not limited to this, as long as its function can be realized.
- the output terminals of the first driving unit 33 and the second driving unit 34 are respectively coupled to the charge sharing unit 35.
- the charge sharing unit 35 can make the output terminals of the first driving unit 33 and the second driving unit 34 perform charge sharing under the control of the charge sharing control signal, that is, short-circuit the output terminals of the first driving unit 33 and the second driving unit 34 , To reduce power consumption.
- the charge sharing unit 35 may include one or more switching transistors.
- the present disclosure does not limit the implementation of the charge sharing unit 35, as long as its function can be realized.
- FIG. 7 is a schematic diagram of a first data distribution signal and a second data distribution signal in an embodiment of the disclosure.
- the first data distribution signal Vbias-P and the second data distribution signal Vbias-N are the same, there is no voltage difference between the two, and no pumping is caused during the charge sharing process. Load high current is generated, which can prevent the boost circuit from being burnt.
- FIG. 8 is a schematic structural diagram of a data driver according to an embodiment of the disclosure.
- the data distribution unit 31 includes: a first digital-to-analog converter (DAC, Digital to Analog Converter) 311 and a second digital-to-analog converter Converter 312; the first driving unit includes a first operational amplifier 331, and the second driving unit includes a second operational amplifier 341.
- the output terminal of the first digital-to-analog converter 311 is coupled to the input terminal of the first operational amplifier 331, and the output terminal of the second digital-to-analog converter 312 is coupled to the input terminal of the second operational amplifier 341.
- the output terminals of the first operational amplifier 331 and the second operational amplifier 341 are respectively coupled to the charge sharing unit 35.
- the first operational amplifier 331 can be a positive signal amplifier
- the second operational amplifier 341 can be a negative signal amplifier.
- the first digital-to-analog converter 311 is configured to receive the analog power signal AVDDS and the semi-analog power signal HAVDD; the second digital-to-analog converter 312 is configured to receive the semi-analog power signal HAVDD and the ground signal GND.
- the first digital-to-analog converter 311 can generate a first data distribution signal Vbias-P and provide it to the input terminal of the first operational amplifier 331; the second digital-to-analog converter 312 can generate a second data distribution signal Vbias-N and provide
- the second operational amplifier 312 is provided to support the first operational amplifier 331 and the second operational amplifier 341 to generate independent currents (as shown by the dotted line in FIG. 8).
- the entire data driver when the control unit 32 does not receive the power-on reset signal, the entire data driver can work in a charge sharing state, that is, the output terminals of all channels are short-circuited together through the charge sharing unit 35 to neutralize
- the control unit 32 can control the output terminal of the first data converter 311 and the output terminal of the second data converter 312 to short-circuit, that is, control the first data distribution signal Vias-P and the second data distribution signal Vbias-N maintains the same potential; after the control unit 32 detects or receives the power-on reset signal, the control unit 32 controls the output terminal of the first data converter 311 and the output terminal of the second data converter 312 to disconnect, so that the first The operational amplifier 331 and the second operational amplifier 341 can work separately to generate a negative frame data signal with a larger falling edge delay time, so as to improve short-term line afterimages.
- FIG. 9 is a schematic diagram of the effect of the data driver according to the embodiment of the disclosure.
- the current I-AVDD of the data driver is not abnormally large, and the output terminal Sout1 is not abnormally raised. It can be seen that the data driver provided in this embodiment can solve the problem of large current drawn as shown in FIG. 5, thereby improving circuit stability and safety.
- the abscissa in Fig. 5 and Fig. 9 represents time (t).
- FIG. 10 is a schematic diagram of a work flow of a data driver provided by an embodiment of the disclosure.
- the data driver in this embodiment may be as shown in FIG. 6.
- the working process of the data driver provided in this embodiment may include the following steps.
- Step 401 The data driver is powered on.
- the data driver receives the voltage signal provided by TCON, for example, including the analog power signal AVDDS and the semi-analog power signal HAVDD.
- Step 402 The control unit of the data driver determines whether the power-on reset signal is detected; if the power-on reset signal is detected, step 404 is executed, and if the power-on reset signal is not detected, step 403 is executed.
- the power-on reset signal is generated when the data driver starts to output after power-on.
- the power-on reset signal may indicate a period in which the data driver starts to output the data signal.
- Step 403 The control unit does not detect the power-on reset signal, and short-circuits the input terminal of the first drive unit and the input terminal of the second drive unit; then, returns to step 402 to continue to determine whether the power-on reset signal is detected.
- Step 404 The control unit detects the power-on reset signal, and disconnects the input terminal of the first drive unit and the input terminal of the second drive unit, so that the data distribution unit can provide the first data distribution signal and the second data distribution independent of each other
- the signals are respectively provided to the first driving unit and the second driving unit.
- the data driver can normally provide the first data signal and the second data signal to the data line through the first driving unit and the second driving unit.
- Step 405 After the data driver normally provides the data signal to the data line, it can perform charge sharing through the charge sharing unit.
- Step 406 The data driver is powered off, that is, TCON stops supplying power to the data driver.
- the data driver provided by the embodiments of the present disclosure can improve the short-term line afterimage of the large-size and high-resolution liquid crystal display device during the startup process, and can solve the problem of large current drawn, thereby improving circuit stability and safety.
- the embodiment of the present disclosure also provides a data driver control method, which is applied to the above-mentioned data driver.
- the control method provided in this embodiment includes: the control unit controls the input terminal and the first drive unit according to a power-on reset signal.
- the input terminal of the second drive unit is short-circuited or disconnected.
- control unit controls the input terminal of the first driving unit and the input terminal of the second driving unit to be short-circuited or disconnected according to the power-on reset signal, including:
- control unit When the control unit does not detect the power-on reset signal, it controls the input terminal of the first drive unit and the input terminal of the second drive unit to short-circuit;
- control unit When the control unit detects the power-on reset signal, it controls the input terminal of the first driving unit and the input terminal of the second driving unit to be disconnected.
- An embodiment of the present disclosure also provides a display device, which includes the data driver described in the foregoing embodiment.
- the display device may include a plurality of data drivers described in the foregoing embodiments.
- the display device of this embodiment may be any product or component with display function, such as a liquid crystal display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
- the orientation or positional relationship indicated by “outside” is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, It is constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present disclosure.
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Abstract
Description
Claims (9)
- 一种数据驱动器,包括:控制单元、数据分配单元、第一驱动单元和第二驱动单元;所述数据分配单元分别与第一驱动单元的输入端和第二驱动单元的输入端耦接,配置为向第一驱动单元的输入端提供第一数据分配信号,向第二驱动单元的输入端提供第二数据分配信号;所述第一驱动单元配置为根据所述第一数据分配信号生成第一数据信号,所述第二驱动单元配置为根据所述第二数据分配信号生成第二数据信号,且所述第一数据信号和第二数据信号的电压极性不同;所述控制单元,分别与所述第一驱动单元的输入端和第二驱动单元的输入端耦接,配置为根据上电复位信号,控制所述第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
- 根据权利要求1所述的数据驱动器,其中,所述控制单元配置为未检测到所述上电复位信号时,控制所述第一驱动单元的输入端和第二驱动单元的输入端短路;检测到所述上电复位信号时,控制所述第一驱动单元的输入端和第二驱动单元的输入端断开。
- 根据权利要求1所述的数据驱动器,其中,所述数据分配单元,包括:第一数模转换器和第二数模转换器;所述第一驱动单元包括第一运算放大器,所述第二驱动单元包括第二运算放大器;所述第一数模转换器的输出端与所述第一运算放大器的输入端耦接,所述第二数模转换器的输出端与所述第二运算放大器的输入端耦接。
- 根据权利要求1所述的数据驱动器,其中,所述第一数据信号的电压极性为正,所述第二数据信号的电压极性为负,且所述第二数据信号的下降沿延时时长大于所述第一数据信号的上升沿延时时长。
- 根据权利要求1所述的数据驱动器,其中,所述数据分配单元配置为接收由时序控制器内的升压电路产生的模拟电源信号和由时序控制器内的集成电源管理电路产生的半模拟电源信号。
- 根据权利要求1所述的数据驱动器,还包括:电荷共享单元,所述电 荷共享单元分别与所述第一驱动单元的输出端和第二驱动单元的输出端耦接。
- 一种显示装置,包括:如权利要求1至6中任一项所述的数据驱动器。
- 一种数据驱动器的控制方法,应用于如权利要求1至6中任一项所述的数据驱动器,所述控制方法包括:所述控制单元根据上电复位信号,控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开。
- 根据权利要求8所述的控制方法,其中,所述控制单元根据上电复位信号,控制第一驱动单元的输入端和第二驱动单元的输入端短路或断开,包括:所述控制单元在未检测到所述上电复位信号时,控制第一驱动单元的输入端和第二驱动单元的输入端短路;所述控制单元在检测到所述上电复位信号时,控制第一驱动单元的输入端和第二驱动单元的输入端断开。
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US17/417,389 US20220328016A1 (en) | 2020-03-19 | 2020-12-29 | Data Driver, Control Method thereof, and Display Device |
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CN202010206097.7A CN111261125B (zh) | 2020-03-19 | 2020-03-19 | 数据驱动器及其控制方法、显示装置 |
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CN111261125B (zh) * | 2020-03-19 | 2021-10-22 | 合肥京东方显示技术有限公司 | 数据驱动器及其控制方法、显示装置 |
CN112992096B (zh) * | 2021-03-19 | 2022-09-09 | 合肥京东方显示技术有限公司 | 改善残像的方法、装置及显示装置 |
KR20230019352A (ko) * | 2021-07-30 | 2023-02-08 | 삼성디스플레이 주식회사 | 표시 장치 |
CN116343695A (zh) * | 2021-12-16 | 2023-06-27 | 合肥京东方显示技术有限公司 | 显示面板的驱动方法及显示装置 |
CN115101019B (zh) * | 2022-06-09 | 2024-07-05 | 重庆惠科金渝光电科技有限公司 | 源极驱动电路、方法及显示面板 |
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