WO2021165483A1

WO2021165483A1 - Power semiconductor module

Info

Publication number: WO2021165483A1
Application number: PCT/EP2021/054188
Authority: WO
Inventors: Chunlei Liu; Jürgen Schuderer; Fabian MOHN; Marco Bellini; Peter Karl STEIMER
Original assignee: Abb Power Grids Switzerland Ag
Priority date: 2020-02-20
Filing date: 2021-02-19
Publication date: 2021-08-26
Also published as: JP3240772U; DE212021000316U1; CN219040456U

Abstract

Disclosed is a power semiconductor module comprising a baseplate, a wide bandgap material die comprising an array of multiple semiconductor circuits in the wide bandgap material die attached to the base plate, wherein the semiconductor circuits are separated by an edge termination area from each other, a metal preform pressed against each of the multiple semiconductor circuits to electrically contact each of the multiple semiconductor circuits and being adapted to form an at least temporary conducting path through the wide bandgap material die, when heated by an overcurrent, wherein the semiconductor circuits are connected in parallel via the base plate and the metal preform.

Description

POWER SEMICONDUCTOR MODULE

TECHNICAL FIELD

The invention relates to the field of power semiconductor devices. In particular, the invention relates to a power semiconductor module for such devices.

TECHNICAL BACKGROUND This section provides background information related to the present disclosure which is not necessarily prior art.

Power semiconductor devices such as converters, electrical drives etc. are usually assembled of a plurality of power semiconductor modules, each of which mechanically and electrically connects one or more power semiconductor elements. In high voltage DC (HVDC) applications, a series connection of multiple power semiconductor modules is usually required to fulfil high voltage and high current requirements. A power semiconductor module that in case of a failure becomes permanently conducting may have great advantages in such series connections, because the remaining modules can share the blocking voltage. Such operation is referred to as short circuit failure mode (SCFM). One existing packaging technology which has the ability to achieve SCFM is the press-pack technology, which was developed e.g. for Thyristors and GTOs (gate turn-off thyristor) and IGCTs (integrated gate-commutated thyristor) and IGBTs (insulated-gate bipolar transistor) because of the ease with which they can be connected electrically and mechanically in series. In semiconductor modules with a Si (silicon) based semiconductor element, a metal preform may be formed on an electrode of a Si chip which is adapted to form a low melting eutectic alloy with the Si material of the chip and which creates a conducting path to carry the full current load through the failure point. For example, the eutectic reaction between Si and Al (aluminium) at a relative low temperature (577° C) enables such an intrinsic failure compensation. Due to their high blocking capabilities, semiconductor modules with semiconductor elements based on SiC (silicon carbide) and other wide bandgap substrates are more and more employed in high voltage applications.

WO 2018/ 141811 A1 discloses a power semiconductor device comprising a Si (silicon) chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel.

WO 2018/ 065317 A1 discloses a semiconductor module comprising a semiconductor chip comprising a Si base layer and a SiC (silicon carbide) epitaxy layer on the Si base layer, the SiC epitaxy layer comprising a semiconductor element; an electrical conducting top layer for providing an electrical contact of the semiconductor module on a side of the SiC epitaxy layer; an electrical conducting bottom layer for providing an electrical contact of the semiconductor module on a side of the Si base layer; and a failure mode layer in contact with the SiC epitaxy layer and arranged between the top layer and the bottom layer, the failure mode layer comprising a metal material adapted for forming a eutectic alloy with the Si base layer, to short-circuit the semiconductor module.

SUMMARY

This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

According to one embodiment, a power semiconductor module comprises a baseplate, a wide bandgap material die comprising an array of multiple semiconductor circuits in the wide bandgap material die attached to the base plate, wherein the semiconductor circuits are separated by an edge termination area from each other, a metal preform pressed against each of the multiple semiconductor circuits to electrically contact each of the multiple semiconductor circuits and being adapted to form an at least temporary conducting path through the wide bandgap material die, when heated by an overcurrent. The semiconductor circuits are connected in parallel via the base plate and the metal preform. According to another embodiment, the wide bandgap material comprises silicon carbide (SiC).

According to another embodiment, the metal preform comprises at least one of Mo (Molybdenum), W (Wolfram), Cu (Copper) or an alloy thereof. According to another embodiment, the base plate comprises at least one of Mo, W, Cu or an alloy thereof.

According to another embodiment, at least one of the multiple semiconductor circuits comprises at least one of an IGBT (Insulated Gate BipolarTransistor), a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or a diode. According to another embodiment, the array of multiple semiconductor circuits comprises four semiconductor circuits connected in parallel with each other.

According to another embodiment, the power semiconductor module further comprises at least one press pin pressing the metal preform against each of the multiple semiconductor circuits. According to another embodiment, the power semiconductor module further comprises an electrically conducting top plate connected to the at least one press pin.

According to another embodiment, the at least one press pin comprises a spring element.

According to a further aspect, a power semiconductor module comprises a baseplate, at least two module portions, at least two wide bandgap material dies each arranged in one of the at least two module portions and each comprising an array of multiple semiconductor circuits in the wide bandgap material die attached to the base plate, wherein the semiconductor circuits are separated by an edge termination area from each other. The power semiconductor module further comprises at least two metal preforms each pressed against each of the multiple semiconductor circuits to electrically contact each of the multiple semiconductor circuits and being adapted to form an at least temporary conducting path through the wide bandgap material die, when heated by an overcurrent, wherein the semiconductor circuits of each of the at least two wide bandgap material dies are connected in parallel via the base plate and one of the at least two metal preforms. The power semiconductor module further comprises at least two press pins pressing each of the metal preforms against each of the multiple semiconductor circuits of each of the at least two wide bandgap material dies, an electrically conducting top plate connected to the at least two press pins.

According to another embodiment, the at least two module portions are arranged in one package.

Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

DRAWINGS

The drawings described herein are only for illustrative purposes of selected embodiments and not for all possible implementations, and is not intended to limit the scope of the present disclosure.

Figure 1 schematically shows an example of an embodiment of a power semiconductor module.

Figure 2 schematically shows another example of an embodiment of a power semiconductor module.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Examples of embodiments will now be described more fully with reference to the accompanying drawings.

Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having," are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

When an element or layer is referred to as being "on," "engaged to," "connected to," or "coupled to" another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Developing a high current module with SCFM (Short Circuit Failure Mode) capability is challenging because e.g. when using SiC (silicon carbide) as wide bandgap material for the die, a High voltage SiC chip (e.g. MOSFET) is small (ca. 5*5mm²) and will remain with small size in near future due to its yield and cost reasons (intrinsic defects and process yield). Recently SiC SCFM is validated i) for a small metal preform on single small SiC chips or ii) as multiple-pin preform on one large SiC chip. With both solutions above, a high current SiC module with SCFM capability can be realized. However, recently it is difficult to manufacture high current SiC modules with SCFM capability for high power application (e.g. HVDC, VSC) with the high yield of the single small SiC chips. This is because when using multiple single small SiC chips connected by one multiple-pin preform, a stable short cannot be ensured when one of the single small SiC chips fails because arcing may occur. Otherwise, large SiC chips (e.g. 12*12mm²) are not yet available on a commercial scale, because the yield of large SiC chips is too low.

It is therefore one objective of the invention to provide a compact, secure power semiconductor module design with SCFM (Short Circuit Failure Mode) formation capability and with a high yield.

This objective is achieved by the subject-matter of the independent claim. Further exemplary embodiments are evident from the dependent claims and the following description. The invention relates to a power semiconductor module. In particular the invention relates to a High current power module design with SCFM (Short Circuit Failure Mode) formation capability. A new chip structure enables a high current module with SCFM. Here and in the following, the term "power" may relate to the ability to process currents of more than 10 A and/or more than 1.000 V. A power semiconductor module in general may be a device mechanically supporting and providing terminals for one or more power semiconductor elements such as transistors, thyristors, diodes, etc. In general, a power semiconductor module may comprise a housing providing the terminals, in which the one or more power semiconductor elements are accommodated.

According to one embodiment of the invention as disclosed in Fig.l, a power semiconductor module comprises a baseplate 10, a wide bandgap material die 12 comprising an array of multiple semiconductor circuits 11 in the wide bandgap material die 12 attached to the base plate 10, wherein the semiconductor circuits 11 are separated by an edge termination area 16 from each other. By forming the multiple semiconductor circuits 11 in the wide bandgap material die 12 separated by an edge termination area 16, the high yield of a small SiC chip can be maintained and concurrently a stable short of a large chip with multiple- pin preform can be ensured.

The wide bandgap material may comprise silicon carbide (SiC). The wide bandgap material may also be GaN, etc. It may be characterized with a semiconductor bandgap wider than that of Silicon (Si), e.g. wider than 1,1 eV. A metal preform 14 is pressed against each of the multiple semiconductor circuits 11 to electrically contact each of the multiple semiconductor circuits 11 and being adapted to form an at least temporary conducting path through the wide bandgap material die 12, when heated by an overcurrent. Such an overcurrent might appear in a failure situation when one of the semiconductor circuits 11 fails. Generally, the failure mode of a power electronic component can be classified as open-circuit failure or short-circuit failure. Semiconductor components which fail to an open circuit are unsuitable for applications requiring series connection. Especially, in some high-power applications, the modules must be designed such that when a failure occurs, the failed module keeps carrying the load current by the formation of a stable short circuit, while the remaining modules share the blocking voltage. The semiconductor circuits 11 are connected in parallel via the base plate 10 and the metal preform 14.

With e.g. laser dicing technique, a wide bandgap material die 12 with a new chip structure with multiple small semiconductor circuits 11, being separated by an edge termination area 16 from each other, can be realized as one single large chip unit which maintains the high yield of small individual chips. At least one of the multiple semiconductor circuits 11 may comprise at least one of an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or a diode. By using a multi-pin preform concept which presses the metal preform 14 against each of the multiple semiconductor circuits 11 to electrically contact each of the multiple semiconductor circuits 11, the multiple semiconductor circuits 11 are electrically connected in parallel via the base plate and the metal preform 14 for high current classification and to guarantee Short Circuit Failure Mode (SCFM). Furthermore the multi-pin preform concept supports a uniform pressure over the complete area of the wide bandgap material die 12. The metal preform 14 and / or the base plate 10 may comprise at least one of Mo (Molybdenum), W (Wolfram), Cu (Copper) or an alloy thereof. Mo may be beneficial, because it has a similar coefficient of thermal expansion as SiC or other wide bandgap materials. Furthermore, also Mo may form with the wide bandgap substrate of the wide bandgap material die 12 under higher temperature at least temporarily a conducting path.

Exemplarily, the multiple semiconductor circuits 11 are connected in parallel within the power semiconductor module. It is noted that the semiconductor circuit 11 may be a completely passive element and/or layer only providing a rather high resistance for the current path along the metal preform 14. I.e. it may be that during normal operation no current flows through the semiconductor circuit 11 at all. The metal preform 14 is adapted for forming at least a temporary conducting path through the semiconductor circuit 11, when heated by an overcurrent caused e.g. by a chip failure. Here, an overcurrent may be a current so high that the wide bandgap material, e.g. SiC, decomposes. The temporary conducting path through the wide bandgap material may degrade due to the materials formed for the conducting path. For example, a SiC substrate and a metal preform may form electrically conducting substances. The term "temporary" may relate to a time span much smaller than a "permanent" time span. For example a temporary time span may be shorter than 1 second. Compared with a Silicon substrate, the wide bandgap material die and the melted metal preform 14 form no alloy, because e.g SiC only melts at highertemperatures. In case of a wide bandgap material die, the low-ohmic path is formed by decomposition (e.g. by arcing) of the wide bandgap material. Due to the fact that the multiple small semiconductor circuits 11 are separated by an edge termination area 16 from each other, but are still on one single die, the necessary space for dicing the chips can be saved as well as a low resistance current path can be ensured in case of a circuit failure.

The array of multiple semiconductor circuits 11 may comprise e.g. three or four semiconductor circuits 11 connected in parallel with each other. With these number of semiconductor circuits 11, the yield can be maintained high while ensuring a high power application. Furthermore, a higher number of semiconductor circuits 11 on the wide bandgap material die 12 results in an increase of the active area because of saving the termination area between the semiconductor circuits 11. The power semiconductor module 1 may further comprise at least one press pin 18 pressing the metal preform 14 against each of the multiple semiconductor circuits 11. A pressing force may be applied by the electrically conducting press pin 18 which is pressed against the respective metal preform 14. The power semiconductor module may further comprise an electrically conducting top plate 20 connected to the at least one press pin 18.

The at least one press pin 18 may comprise a spring element 22, which, for example, may comprise a disc spring, a leaf spring or a coil spring. The metal preform 14, the press pins 18 and/orthe spring elements 22 may be accommodated between the wide bandgap material die 12 and the top plate 20. In addition to the multi-pin preform concept the spring element 22 further supports a uniform pressure distribution over the complete area of the wide bandgap material die 12. In one embodiment, the top plate 20 is part of the press pin 18.

Fig. 2 shows another embodiment of the present invention, illustrating a multichip power semiconductor module comprising two wide bandgap material dies, one in each of the module portions 31 and 32. The two wide bandgap material dies are arranged on one single baseplate 10. The number of dies is not limited to one or two. In one embodiment, e.g. three or six dies may be combined in one module 1. Multiple modules 1 may be combined in one package to form one single product. Similarly, two or more metal preforms 14 may be used to contact respective arrays of multiple semiconductor circuits 11 in a single, wide bandgap material die attached to a base plate 10 (not shown).

The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and may be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure. LIST OF REFERENCE SIGNS 1 power semiconductor module 10 base plate 11 semiconductor circuit

12 wide bandgap material die 14 metal preform 16 edge termination area 18 press pin 20 top plate

22 spring element

31, 32 module portions

Claims

1. A power semiconductor module (1), comprising: a baseplate (10); a wide bandgap material die (12) comprising an array of multiple semiconductor circuits (11) in the wide bandgap material die (12) attached to the base plate (10), wherein the semiconductor circuits (11) are separated by an edge termination area (16) from each other; a metal preform (14) pressed against each of the multiple semiconductor circuits (11) to electrically contact each of the multiple semiconductor circuits (11) and being adapted to form an at least temporary conducting path through the wide bandgap material die (12), when heated by an overcurrent; wherein the semiconductor circuits (11) are connected in parallel via the base plate (10) and the metal preform (14).

2. The power semiconductor module (1) according to claim 1, wherein the wide bandgap material comprises silicon carbide (SiC).

3. The power semiconductor module (1) according to claim 1 or 2, wherein the metal preform (14) comprises at least one of Mo, W, Cu or an alloy thereof.

4. The power semiconductor module (1) according to any of claims 1 to 3, wherein the base plate (10) comprises at least one of Mo, W, Cu or an alloy thereof.

5. The power semiconductor module (1) according to any of claims 1 to 4, wherein at least one of the multiple semiconductor circuits (11) comprises at least one of an IGBT, a MOSFET or a diode.

6. The power semiconductor module (1) according to any of claims 1 to 5, wherein the array of multiple semiconductor circuits (11) comprises four semiconductor circuits (11).

7. The power semiconductor module (1) according to any of claims 1 to 6, further comprising at least one press pin (18) pressing the metal preform (14) against each of the multiple semiconductor circuits (11).

8. The power semiconductor module (1) according to claim 7, further comprising an electrically conducting top plate (20) connected to the at least one press pin (18).

9. The power semiconductor module (1) according to any of claims 7 or 8, wherein the at least one press pin (18) comprises a spring element (22).

10. The power semiconductor module (1) according to claim 1, further comprising: at least two module portions (31) and (32); at least one further wide bandgap material die (12), each one of the at least two wide bandgap material dies (12) arranged in one of the at least two module portions (31) and (32) and each comprising an array of multiple semiconductor circuits (11) in the wide bandgap material die (12) attached to the base plate (10), wherein the semiconductor circuits (11) are separated by an edge termination area (16) from each other; at least one further metal preform (14), each one of the at least two metal preforms (14) pressed against each of the multiple semiconductor circuits (11) in one of the at least two wide bandgap material dies (12) arranged in one of the at least two module portions (31) and (32) to electrically contact each of the respective multiple semiconductor circuits (11) and being adapted to form an at least temporary conducting path through the respective wide bandgap material die (12), when heated by an overcurrent; wherein the semiconductor circuits (11) of each of the at least two wide bandgap material dies (12) are connected in parallel via the base plate (10) and one of the at least two metal preforms (14); at least two press pins (18) pressing each of the metal preforms (14) against each of the multiple semiconductor circuits (11) of each of the at least two wide bandgap material dies (12); an electrically conducting top plate (20) connected to the at least two press pins (18).

11. The power semiconductor module (1) according to claim 10, wherein the at least two module portions (31) and (32) are arranged in one package.