WO2021161509A1 - Procédé de fabrication d'un dispositif semi-conducteur au nitrure - Google Patents

Procédé de fabrication d'un dispositif semi-conducteur au nitrure Download PDF

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WO2021161509A1
WO2021161509A1 PCT/JP2020/005788 JP2020005788W WO2021161509A1 WO 2021161509 A1 WO2021161509 A1 WO 2021161509A1 JP 2020005788 W JP2020005788 W JP 2020005788W WO 2021161509 A1 WO2021161509 A1 WO 2021161509A1
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nitride semiconductor
semiconductor layer
annealing
manufacturing
protective film
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PCT/JP2020/005788
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English (en)
Japanese (ja)
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健太 渡邉
峰司 大川
紘子 井口
大悟 菊田
朋彦 森
大至 木村
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トヨタ自動車株式会社
株式会社豊田中央研究所
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Priority to PCT/JP2020/005788 priority Critical patent/WO2021161509A1/fr
Publication of WO2021161509A1 publication Critical patent/WO2021161509A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Definitions

  • the technique disclosed in the present specification relates to a method for manufacturing a nitride semiconductor device.
  • Patent Document 1 discloses an example of a technique for forming a p-type region in a nitride semiconductor layer.
  • a method for manufacturing a nitride semiconductor device having a p-type region is required.
  • the method for manufacturing a nitride semiconductor device disclosed in the present specification includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film on the surface of the nitride semiconductor layer after the ion implantation step.
  • a protective film forming step for forming a film and an annealing treatment step for annealing the nitride semiconductor layer after the protective film forming step can be provided.
  • the annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher in an ammonia atmosphere and at a pressure lower than 10 kPa.
  • the nitride semiconductor layer In order to activate the p-type dopant in the nitride semiconductor layer, it is necessary to heat the nitride semiconductor layer to 1200 ° C. or higher. However, when the nitride semiconductor layer is heated to 1200 ° C. or higher, the surface of the nitride semiconductor layer is thermally decomposed. Even when the protective film is formed on the surface of the nitride semiconductor layer, nitrogen may escape from the surface of the nitride semiconductor layer through the grain boundaries of the protective film. According to this manufacturing method, nitrogen generated by thermal decomposition of ammonia is transferred to the surface of the nitride semiconductor layer through the grain boundaries of the protective film so as to compensate for the escape of nitrogen through the grain boundaries of the protective film. Is supplied to.
  • the cross-sectional view of the main part of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the second manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the third manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the third manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. It is the 4th manufacturing method of the nitride semiconductor apparatus of 1st Embodiment, and shows the time change of the temperature of the nitride semiconductor layer in the annealing process. It is the 5th manufacturing method of the nitride semiconductor apparatus of 1st Embodiment, and shows the flow of an ion implantation process.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • the cross-sectional view of the main part of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • the surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 6 kPa in an ammonia atmosphere is shown.
  • the surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 12 kPa in an ammonia atmosphere is shown.
  • the surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 20 kPa in an ammonia atmosphere is shown.
  • FIG. 1 shows a cross-sectional view of a main part of the nitride semiconductor device 1.
  • the nitride semiconductor device 1 includes a nitride semiconductor layer 20, a drain electrode 32 provided so as to cover the lower surface of the nitride semiconductor layer 20, and a source provided so as to cover the upper surface of the nitride semiconductor layer 20. It includes an electrode 34 and a planar type insulating gate 36 provided on a part of the upper surface of the nitride semiconductor layer 20.
  • the nitride semiconductor layer 20 includes an n-type drain region 21, an n-type drift region 22, an n-type JFET region 23, a p-type body region 24, an n-type source region 25, and a p-type body contact region. Has 26.
  • the drain region 21 is provided at a position exposed on the lower surface of the nitride semiconductor layer 20 and is in ohmic contact with the drain electrode 32.
  • the drain region 21 is made of gallium nitride (GaN) containing n-type impurities.
  • the drift region 22 is provided on the drain region 21, and is arranged between the drain region 21 and the JFET region 23 and between the drain region 21 and the body region 24.
  • the drift region 22 is made of gallium nitride (GaN) containing n-type impurities.
  • the JFET region 23 is provided on the drift region 22 and is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and extends in the thickness direction from the upper surface of the drift region 22 to the upper surface of the nitride semiconductor layer 20. It has a shape protruding from the upper surface of the drift region 22. In other words, the JFET region 23 extends from the upper surface of the nitride semiconductor layer 20 through the body region 24 to the drift region 22.
  • the JFET region 23 is made of gallium nitride (GaN) containing n-type impurities. In this example, the impurity concentration in the JFET region 23 is equal to the impurity concentration in the drift region 22, and can be said to be a part of the drift region 22.
  • the body region 24 is provided on the drift region 22 and is adjacent to the side surface of the JFET region 23.
  • the body region 24 has a high-concentration body region 24a and a low-concentration body region 24b.
  • the body region 24 is made of gallium nitride (GaN) containing p-type impurities.
  • the high-concentration body region 24a is arranged between the drift region 22 and the low-concentration body region 24b, and is in contact with the lower side surface of the JFET region 23.
  • the high-concentration body region 24a contains p-type impurities at a higher concentration than the low-concentration body region 24b, and is provided to prevent the low-concentration body region 24b from punching through when it is off.
  • the low-concentration body region 24b is provided on the high-concentration body region 24a, is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and is in contact with the upper side surface of the JFET region 23.
  • the impurity concentration in the low concentration body region 24b is adjusted to a desired gate threshold voltage.
  • a part of the low-concentration body region 24b located on the upper surface of the nitride semiconductor layer 20 and between the JFET region 23 and the source region 25 is particularly referred to as a channel region CH.
  • the source region 25 is provided on the low-concentration body region 24b, is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and is separated from the JFET region 23 by the low-concentration body region 24b.
  • the source region 25 is made of gallium nitride (GaN) containing n-type impurities.
  • the source region 25 is in ohmic contact with the source electrode 34.
  • the body contact region 26 is arranged on the low-concentration body region 24b, and is provided at a position exposed on the upper surface of the nitride semiconductor layer 20.
  • the body contact region 26 is made of gallium nitride (GaN) containing p-type impurities.
  • the body contact region 26 is in ohmic contact with the source electrode 34.
  • the insulating gate portion 36 is provided on a part of the upper surface of the nitride semiconductor layer 20, and has a silicon oxide gate insulating film 36a and a polysilicon gate electrode 36b.
  • the gate electrode 36b faces the channel region CH of the low-concentration body region 24b of the portion separating the JFET region 23 and the source region 25 and the JFET region 23 via the gate insulating film 36a.
  • the operation of the nitride semiconductor device 1 will be described.
  • a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded.
  • a positive voltage higher than the gate threshold voltage is applied to the gate electrode 36b, an inversion layer is formed in the channel region CH between the JFET region 23 and the source region 25, and the source region 25 to the JFET region via the inversion layer are formed. Electrons flow into 23. The electrons that have flowed into the JFET region 23 flow vertically through the JFET region 23 and head toward the drain electrode 32. As a result, the drain electrode 32 and the source electrode 34 become conductive, and the nitride semiconductor device 1 turns on.
  • the nitride semiconductor device 1 can execute a switching operation of switching on and off between the drain electrode 32 and the source electrode 34 based on the voltage applied to the gate electrode 36b.
  • an n-type GaN drift region 22 is epitaxially grown from the surface of a drain region 21 which is a GaN substrate to form a nitride semiconductor layer 20 by using an epitaxial growth technique.
  • silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 25.
  • magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using an ion implantation technique to form a body region 24 and a body contact region 26.
  • Magnesium is implanted into the nitride semiconductor layer 20 by a plurality of ion implantations at different implantation depths.
  • hydrogen may be ion-implanted into the magnesium injection range.
  • a highly active p-type region can be formed by co-injecting magnesium and hydrogen.
  • an amorphous protective film 42 for annealing is formed so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using the vapor deposition technique.
  • a vapor deposition technique a CVD method or a PVD method is used.
  • the CVD method for example, an atomic layer deposition method may be used.
  • the protective film 42 for annealing is a material that crystallizes in the subsequent annealing treatment for activation, and is, for example, aluminum nitride (AlN).
  • the protective film 42 for annealing may be aluminum gallium nitride (AlGaN), aluminum oxide (Al 2 O 3 ), zinc oxide (Zn O), or silicon oxide (SiO 2 ).
  • an annealing treatment step is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20.
  • This annealing treatment step includes a heating step of heating the nitride semiconductor layer 20 at a temperature of 1200 ° C. or higher, in an ammonia atmosphere, and at a low pressure of less than 10 kPa. More specifically, the temperature of this heating step is 1200 to 1500 ° C.
  • the amorphous protective film 42 for annealing crystallizes. At this time, grain boundaries may be formed that penetrate from the upper surface to the lower surface of the protective film 42 for annealing. Therefore, nitrogen may escape from the upper surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 42, and pits may be formed on the upper surface of the nitride semiconductor layer 20.
  • FIG. 2E shows that when this annealing treatment step is carried out, the amorphous protective film 42 for annealing crystallizes. At this time, grain boundaries may be formed that penetrate from the upper surface to the lower surface of the protective film 42 for annealing. Therefore, nitrogen may escape from the upper surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 42, and pits may be formed on the upper surface of the nitride semiconductor layer 20.
  • FIG. 2E shows that shows that this annealing treatment step is carried out.
  • the heating step during this annealing treatment step is carried out under a reduced pressure of less than 10 kPa, hydrogen generated by the thermal decomposition of ammonia is efficiently discharged from the annealing furnace. Therefore, the amount of hydrogen generated by thermal decomposition is suppressed from being supplied to the upper surface of the nitride semiconductor layer 20 via the grain boundaries of the annealing protective film 42. As described above, in the heating step carried out under reduced pressure, it is possible to prevent the upper surface of the nitride semiconductor layer 20 from being damaged by hydrogen generated by thermal decomposition.
  • FIGS. 10 to 12 show surface optical microscope images of the nitride semiconductor layer 20 after performing the heating step at 1400 ° C. in an ammonia atmosphere.
  • FIG. 10 shows the result of carrying out the heating step at a pressure of 6 kPa
  • FIG. 11 shows the result of carrying out the heating step at a pressure of 12 kPa
  • FIG. 12 shows the result of carrying out the heating step at a pressure of 20 kPa.
  • the density and size of the pits depends on the pressure during the heating process. From this result, in the heating step of the ammonia atmosphere, the formation of pits on the upper surface of the nitride semiconductor layer 20 can be suppressed by lowering the pressure during the heating step below the standard atmospheric pressure.
  • the pressure during the heating step may be less than 20 kPa, less than 15 kPa, less than 12 kPa, less than 11 kPa, less than 10 kPa, less than 9 kPa, less than 8 kPa, less than 7 kPa or less than 6 kPa.
  • the pressure during the heating process is reduced, the density of the pits can be further reduced and the size of the pits can be further reduced.
  • the pressure during the heating step is less than 10 kPa, the formation of pits can be remarkably suppressed. It should be noted that such a result is not limited to the case where the temperature of the heating step is 1400 ° C., and is the same when the temperature of the heating step is 1200 to 1500 ° C.
  • the amount of hydrogen generated by the thermal decomposition of ammonia is suppressed from being supplied to the upper surface of the nitride semiconductor layer 20, at least a part of the hydrogen generated by the thermal decomposition of ammonia is passed through the protective film 42 for annealing. It is introduced into the nitride semiconductor layer 20.
  • the hydrogen introduced into the nitride semiconductor layer 20 can be bonded to magnesium, which is a p-type dopant. Magnesium to which hydrogen is bound has the property of being easily taken up by Ga sites. Therefore, when the heating step is carried out in an ammonia atmosphere, magnesium can be efficiently incorporated into the Ga site.
  • magnesium and hydrogen are co-implanted in the ion implantation step, hydrogen generated by thermal decomposition of ammonia is present in the atmosphere, so that the ion-implanted hydrogen is difficult to be desorbed. Since hydrogen is less likely to be desorbed, it is possible to prevent hydrogen from being desorbed before the magnesium to which hydrogen is bound is incorporated into the Ga site. As a result, magnesium can be taken into the Ga site more efficiently.
  • the protective film 44 for dehydrogenation is applied so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using a vapor deposition technique.
  • a vapor deposition technique a CVD method or a PVD method is used.
  • the CVD method for example, an atomic layer deposition method may be used.
  • the dehydrogenation protective film 44 is a material having higher hydrogen permeability than the annealing protective film 42, and is, for example, silicon oxide (SiO 2 ).
  • an annealing treatment is performed in order to remove hydrogen in the nitride semiconductor layer 20.
  • the temperature is 500 to 1500 ° C.
  • hydrogen bonded to magnesium is removed from the nitride semiconductor layer 20, and magnesium, which is a p-type dopant, is activated.
  • uptake of magnesium into the Ga site, activation of magnesium, and removal of hydrogen can be performed by one annealing treatment. In this case, the dehydrogenation step shown in FIG. 2F can be omitted.
  • a gate insulating film 36a is formed so as to cover the upper surface of the nitride semiconductor layer 20 by using a vapor deposition technique.
  • a vapor deposition technique an atomic layer deposition method or a plasma CVD method is used.
  • a post-annealing (PDA) treatment is performed to improve the film quality of the gate insulating film 36a.
  • PDA post-annealing
  • a large amount of hydrogen remains in the gate insulating film 36a formed by using the vapor deposition technique.
  • gallium (Ga) may diffuse into the gate insulating film 36a.
  • the annealing step is carried out by a method other than the annealing step for activation described above, the surface of the nitride semiconductor layer 20 becomes excessive in Ga, so that a large amount of Ga is applied to the gate insulating film 36a in the post-annealing treatment. It will spread.
  • gallium (Ga) is diffused in the gate insulating film 36a, deterioration of electrical characteristics such as fluctuation of the gate threshold voltage becomes a problem.
  • the temperature and pressure of this post-annealing process are set under conditions in which the solid phase of the phase diagram is maintained based on the phase diagram of gallium nitride (GaN) constituting the nitride semiconductor layer 20.
  • the solid phase is maintained at a pressure of 1 MPa or more at a temperature of 1000 ° C. Therefore, the pressure of this post-annealing process is set to 1 MPa or more. More specifically, the temperature of the post-annealing treatment is 500 to 1500 ° C., and the pressure of the post-annealing treatment is 1 MPa to 1 GPa. Thereby, the film quality of the gate insulating film 36a can be improved while suppressing the thermal decomposition of the nitride semiconductor layer 20.
  • the gate electrode 36b is formed on the surface of the gate insulating film 36a by using the vapor deposition technique. Further, the gate insulating film 36a and the gate electrode 36b are processed by using the etching technique to form the insulated gate portion 36. After that, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured by forming the drain electrode 32 and the source electrode 34 by using a known manufacturing technique.
  • the steps up to the ion implantation step of the p-type dopant that is, the steps from FIGS. 2A to 2C can be the same as the first manufacturing method.
  • an amorphous protective film for annealing is used to cover the upper surface and the lower surface of the nitride semiconductor layer 20 and the extending side surface between the upper surface and the lower surface by using a vapor deposition technique. 46 is formed into a film. That is, the annealing protective film 46 is formed so as to cover the entire surface of the nitride semiconductor layer 20.
  • the protective film 46 for annealing is formed on the side surface of the unit cell of the device, it should be noted that the protective film 46 for annealing is actually formed on the side surface of the wafer. sea bream.
  • a CVD method or a PVD method is used.
  • CVD method a method having a high step coating property is desirable, and for example, an atomic layer deposition method may be used.
  • the PVD method in order to improve the step coating property, the nitride semiconductor layer 20 being formed is tilted at a predetermined speed while tilting the target cathode at an angle larger than 0 ° with respect to the nitride semiconductor layer 20. You may rotate it.
  • the protective film 46 for annealing is a material that crystallizes in the subsequent annealing treatment for activation, and is, for example, aluminum nitride (AlN).
  • AlN aluminum nitride
  • the protective film 46 for annealing may be aluminum gallium nitride (AlGaN), aluminum oxide (Al 2 O 3 ), zinc oxide (Zn O), or silicon oxide (SiO 2 ).
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step may be the same as the annealing treatment step of the first manufacturing method.
  • the annealing step under reduced pressure of less than 10 kPa is carried out.
  • the nitride semiconductor layer 20 is more easily thermally decomposed than under a pressure of 10 kPa or more. Therefore, when the annealing step of the first manufacturing method is adopted, by forming the protective film 46 for annealing on the side surface of the nitride semiconductor layer 20, not only the upper surface and the lower surface of the nitride semiconductor layer 20 but also the lower surface thereof are formed. Thermal decomposition of the side surface can also be suppressed. As described above, the technique of forming the protective film 46 for annealing on the side surface of the nitride semiconductor layer 20 is particularly useful when the annealing step of the first manufacturing method is adopted.
  • a protective film 46 for annealing is also formed on the side surface of the nitride semiconductor layer 20. Therefore, the decomposition of the GaN crystal on the side surface of the nitride semiconductor layer 20 can be suppressed, so that a large effective area of the device can be secured.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • the steps up to the ion implantation step of the p-type dopant that is, the steps from FIGS. 2A to 2C can be the same as the first manufacturing method.
  • an amorphous aluminum nitride film 48a is formed so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using the vapor deposition technique.
  • a CVD method or a PVD method is used as the vapor deposition technique.
  • the CVD method for example, an atomic layer deposition method may be used.
  • an oxide film 48b of aluminum oxide (Al 2 O 3 ) is formed on the surface of the aluminum nitride film 48a.
  • the laminated film of the aluminum nitride film 48a and the oxide film 48b serves as the protective film 48 for annealing.
  • the oxide film 48b may be formed by forming an aluminum nitride film 48a on each of the upper surface and the lower surface of the nitride semiconductor layer 20 and then performing heat treatment in an oxygen atmosphere, or by performing oxygen plasma irradiation. A film may be formed.
  • an oxide gas is added to the film forming raw material of aluminum nitride to form an oxide film 48b of aluminum nitride (AlON). May be formed.
  • the aluminum nitride film 48a and the aluminum nitride (AlON) oxide film 48b may be formed on the lower surface of the nitride semiconductor layer 20 by the CVD method.
  • the thickness of each of the aluminum nitride film 48a and the oxide film 48b is 1000 nm or less.
  • the annealing protective film 48 may also be formed on the side surface of the nitride semiconductor layer 20.
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step may be the same as the annealing treatment step of the first manufacturing method.
  • the oxide film 48b By forming the oxide film 48b, the amount of hydrogen generated by the thermal decomposition of ammonia can be further suppressed in the nitride semiconductor layer 20. As a result, it is possible to further prevent the surface of the nitride semiconductor layer 20 from being damaged by hydrogen.
  • the technique for forming the oxide film 48b is particularly useful when the annealing treatment step of the first production method is adopted.
  • Crystallization of the oxide film 48b is suppressed even in the annealing treatment at 1300 ° C. or higher. Therefore, it is suppressed that both the aluminum nitride film 48a and the oxide film 48b, that is, the grain boundaries penetrating from the upper surface to the lower surface of the protective film 48 for annealing are formed. Therefore, it is possible to prevent nitrogen from escaping from the surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 48 and forming pits on the surface of the nitride semiconductor layer 20.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • the steps up to the ion implantation step of the p-type dopant can be the same as the first manufacturing method.
  • the annealing protective film 42 of the first manufacturing method, the annealing protective film 46 of the second manufacturing method, or the annealing protective film 48 of the third manufacturing method is applied, and the nitride semiconductor layer 20 is applied.
  • a protective film for annealing is formed on the surface of the above.
  • FIG. 5 shows the time change of the temperature of the nitride semiconductor layer 20 in the annealing process.
  • the annealing process includes a temperature raising step of raising the temperature of the nitride semiconductor layer 20 from time t 0 to time t 2 and a heating step of heating the nitride semiconductor layer 20 at temperature T 2 from time t 2 to time t 3. And have.
  • the temperature T 2 in the heating step is 1200 ° C. or higher. More specifically, the temperature T 2 in the heating step is 1200 to 1500 ° C.
  • the atmospheric gas and pressure in the heating step are not particularly limited. For example, this heating step can be the same as the heating step of the annealing step of the first manufacturing method.
  • the temperature of the nitride semiconductor layer 20 starts to rise from time t 0, and the temperature of the nitride semiconductor layer 20 reaches 1200 ° C. at time t 1 (when the heating temperature T 2 is 1200 ° C., Time t 1 and time t 2 are the same).
  • the temperature rising rate from time t 0 to time t 2 is 1 to 100 ° C./min.
  • the initial pressure in the annealing furnace at time t 0 is 50 Mpa or more.
  • the protective film for annealing (protective films 42, 46, 48 for annealing in the first to third manufacturing methods) formed on the surface of the nitride semiconductor layer 20 prior to the annealing treatment step is formed in an amorphous state. Will be done.
  • This protective film for annealing crystallizes when the temperature rises, and is crystallized by the time t 1 when the temperature of the nitride semiconductor layer 20 reaches at least 1200 ° C. Therefore, the protective film for annealing from time t 0 to time t 1 may be in an amorphous state, and nitrogen is easily released from the upper surface of the nitride semiconductor layer 20.
  • the solid phase is at a pressure of 50 MPa or more at a temperature of 1200 ° C.
  • the initial pressure in the annealing furnace at time t 0 is set to 50 Mpa or more
  • the pressure in the annealing furnace from time t 0 to time t 1 is maintained to be 50 Mpa or more.
  • NS the thermal decomposition of the nitride semiconductor layer 20 can be suppressed between the time t 0 and the time t 1, so that the escape of nitrogen from the upper surface of the nitride semiconductor layer 20 can be suppressed.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using the ion implantation technique.
  • the amount of magnesium ion-implanted is less than the amount ultimately required to form the body region 24 and the body contact region 26.
  • hydrogen may also be ion-implanted into the magnesium injection range.
  • step S2 an annealing treatment is performed in order to recover the crystal defects formed by the previous ion implantation.
  • the temperature of this annealing treatment is less than 1200 ° C. More specifically, in this annealing treatment, the temperature is 500 to 1000 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • step S3 it is determined whether or not the number of treatments in the process combining the ion implantation and the annealing treatment has reached a predetermined number of times. If the number of processes has not reached the predetermined number, the process returns to step S1. When the number of treatments reaches a predetermined number, that is, when the amount of magnesium ion-implanted exceeds the amount finally required to form the body region 24 and the body contact region 26, the process proceeds to step S4.
  • a protective film for annealing is formed on the surface of the nitride semiconductor layer 20.
  • the protective film for annealing any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
  • step S5 an annealing treatment step is carried out in order to activate the n-type dopant and the p-type dopant of the nitride semiconductor layer 20.
  • this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods.
  • pores are formed in the nitride semiconductor layer 20.
  • the nitride semiconductor layer 20 in which such pore-type defects are present is subjected to a high-temperature (1200 ° C. or higher) annealing treatment for activating the dopant, the pore-type defects are aggregated and the donor-type defects are aggregated. Is formed. As a result, the activation rate of the p-type dopant decreases, and it becomes difficult to form a highly active p-type region.
  • a plurality of steps of combining ion implantation and low temperature (less than 1200 ° C.) annealing treatment are performed.
  • the amount of pores formed for each ion implantation can be suppressed.
  • the density of pore-shaped defects in the nitride semiconductor layer 20 can be reduced. Therefore, when the annealing treatment at a high temperature (1200 ° C.
  • the density of the pore-type defects in the nitride semiconductor layer 20 is sufficiently low, so that the aggregation of the pore-type defects is suppressed.
  • NS the activation rate of the p-type dopant can be increased, and a highly active p-type region can be formed.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • a protective film for annealing in step S4 may be formed between steps S1 and S2. In this case, if the determination result in step S3 is NO, the process returns to step S1 after removing the protective film for annealing.
  • an n-type GaN drift region 22 is epitaxially grown from the surface of a drain region 21 which is a GaN substrate to form a nitride semiconductor layer 20 by using an epitaxial growth technique.
  • magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using an ion implantation technique to form a high-concentration body region 24a.
  • the surface concentration of magnesium contained in the high-concentration body region 24a is 1 ⁇ 10 18 cm -3 or more.
  • hydrogen may also be ion-implanted into the magnesium injection range.
  • n-type GaN is epitaxially grown from the surface of the drift region 22 by using the epitaxial growth technique.
  • the magnesium contained in the high-concentration body region 24a diffuses into the epitaxial growth layer, so that the low-concentration body region 24b is formed.
  • hydrogen derived from the material used in the epitaxial regrowth step is incorporated into the high-concentration body region 24a and the low-concentration body region 24b.
  • silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 25. Further, using the ion implantation technique, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant to form the body contact region 26.
  • a protective film for annealing is formed on the surface of the nitride semiconductor layer 20.
  • the protective film for annealing any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods.
  • the first production method when the first production method is adopted in the annealing process for activating the p-type dopant, if the amount of ion-implanted p-type dopant is large, some hydrogen generated by the decomposition of ammonia may be used. The amount of hydrogen introduced into the nitride semiconductor layer 20 may be insufficient.
  • hydrogen is incorporated into the nitride semiconductor layer 20 before the annealing treatment step, so that a highly active p-type region can be formed.
  • the technique utilizing the epitaxial growth technique can effectively form a highly active p-type region by combining with the annealing step of the first production method.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • FIG. 8 shows a cross-sectional view of a main part of the nitride semiconductor device 2.
  • the nitride semiconductor device 2 includes a nitride semiconductor layer 120, a drain electrode 132 provided so as to cover the lower surface of the nitride semiconductor layer 120, and a source provided so as to cover the upper surface of the nitride semiconductor layer 120. It includes an electrode 134 and a trench-type insulating gate portion 136 provided in a trench formed in a part of the upper surface of the nitride semiconductor layer 120.
  • the nitride semiconductor layer 120 has an n-type drain region 121, an n-type drift region 122, a p-type body region 124, an n-type source region 125, and a p-type body contact region 126.
  • the drain region 121 is provided at a position exposed on the lower surface of the nitride semiconductor layer 120, and is in ohmic contact with the drain electrode 132.
  • the drain region 121 is made of gallium nitride (GaN) containing n-type impurities.
  • the drift area 122 is provided on the drain area 121, and is arranged between the drain area 121 and the body area 124.
  • the drift region 122 is made of gallium nitride (GaN) containing n-type impurities.
  • the body region 124 is provided on the drift region 122, and has a high-concentration body region 124a and a low-concentration body region 124b.
  • the body region 124 is made of gallium nitride (GaN) containing p-type impurities.
  • the high-concentration body region 124a is arranged between the drift region 122 and the low-concentration body region 124b, and is provided away from the side surface of the insulated gate portion 136.
  • the high-concentration body region 124a contains p-type impurities at a higher concentration than the low-concentration body region 124b, and is provided to relax the electric field at the bottom corner of the insulating gate portion 136 when it is off.
  • the low-concentration body region 124b is provided on the high-concentration body region 124a, is provided at a position exposed on the upper surface of the nitride semiconductor layer 120, and is in contact with the side surface of the insulating gate portion 136.
  • the impurity concentration in the low concentration body region 124b is adjusted to a desired gate threshold voltage.
  • a part of the low-concentration body region 124b located in contact with the side surface of the insulated gate portion 136 and between the drift region 122 and the source region 125 is particularly referred to as a channel region CH.
  • the source region 125 is provided on the low-concentration body region 124b, is provided at a position exposed on the upper surface of the nitride semiconductor layer 120, and is separated from the drift region 122 by the low-concentration body region 124b.
  • the source region 125 is made of gallium nitride (GaN) containing n-type impurities.
  • the source region 125 is in ohmic contact with the source electrode 134.
  • the body contact region 126 is arranged on the low-concentration body region 124b, and is provided at a position exposed on the upper surface of the nitride semiconductor layer 120.
  • the body contact region 126 is made of gallium nitride (GaN) containing p-type impurities.
  • the body contact region 126 is in ohmic contact with the source electrode 134.
  • the insulated gate portion 136 is provided in a trench formed in a part of the upper surface of the nitride semiconductor layer 120, and has a silicon oxide gate insulating film 136a and a polysilicon gate electrode 136b.
  • the gate electrode 136b faces the channel region CH of the low-concentration body region 124b of the portion separating the drift region 122 and the source region 125 via the gate insulating film 136a.
  • a positive voltage is applied to the drain electrode 132, and the source electrode 134 is grounded.
  • a positive voltage higher than the gate threshold voltage is applied to the gate electrode 136b, an inversion layer is formed in the channel region CH between the drift region 122 and the source region 125, and an inversion layer is formed from the source region 125 to the drift region via the inversion layer. Electrons flow into 122. The electrons that have flowed into the drift region 122 flow vertically through the drift region 122 and head toward the drain electrode 132. As a result, the drain electrode 132 and the source electrode 134 become conductive, and the nitride semiconductor device 2 turns on.
  • the nitride semiconductor device 2 can execute a switching operation of switching on and off between the drain electrode 132 and the source electrode 134 based on the voltage applied to the gate electrode 136b.
  • an n-type GaN drift region 122 is epitaxially grown from the surface of a drain region 121, which is a GaN substrate, to form a nitride semiconductor layer 120 by using an epitaxial growth technique.
  • magnesium is ion-implanted into the nitride semiconductor layer 120 as a p-type dopant by using an ion implantation technique to form a high-concentration body region 124a.
  • hydrogen may also be ion-implanted into the magnesium injection range.
  • the low-concentration body region 124b of p-type GaN is epitaxially grown from the surface of the drift region 122 by using the epitaxial growth technique.
  • hydrogen derived from the material used in the epitaxial regrowth step is taken into the high-concentration body region 124a and the low-concentration body region 124b.
  • silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 125. Further, using the ion implantation technique, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant to form the body contact region 126.
  • a protective film for annealing is formed on the surface of the nitride semiconductor layer 120.
  • the protective film for annealing any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods of the nitride semiconductor device 1 of the first embodiment.
  • a dry etching technique is used to form a trench TR1 that penetrates the source region 125 and the low-concentration body region 124b from the upper surface of the nitride semiconductor layer 120 and reaches the drift region 122. ..
  • a gate insulating film 136a is formed so as to cover the upper surface of the nitride semiconductor layer 120 including the inner wall surface of the trench TR1 by using a thin film deposition technique.
  • a vapor deposition technique an atomic layer deposition method or a plasma CVD method is used.
  • a post-deposition annealing (PDA) treatment is performed to improve the film quality of the gate insulating film 136a.
  • the post-annealing process can be the same as the post-annealing process of the first manufacturing method of the nitride semiconductor device 1 of the first embodiment.
  • a gate electrode 136b is formed on the surface of the gate insulating film 136a so as to be filled in the trench TR1 by using a thin film deposition technique. Further, the gate insulating film 136a and the gate electrode 136b are processed by using the etching technique to form the insulated gate portion 136. After that, the nitride semiconductor device 2 shown in FIG. 8 can be manufactured by forming the drain electrode 132 and the source electrode 134 by using a known manufacturing technique.
  • the technique of incorporating hydrogen derived from a material by epitaxial regrowth can be applied to a p-type region other than the body region, and can also be applied to a peripheral pressure resistant structure such as a guard ring or a resurf layer.
  • the epitaxial growth layer formed by epitaxial regrowth can be n-type, p-type or i-type depending on the structure to be formed. Further, the epitaxial growth layer formed by epitaxial regrowth may be removed if necessary.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step.
  • the annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher under an ammonia atmosphere and at a pressure lower than the standard atmospheric pressure (100 kPa).
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step. In the protective film forming step, the protective film is formed on the surface of the nitride semiconductor layer so as to cover the side surfaces extending between the pair of main surfaces of the nitride semiconductor layer.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step.
  • an annealing treatment step of annealing the nitride semiconductor layer can be provided.
  • the protective film film forming step includes a first film forming step of forming an aluminum nitride film on the surface of the nitride semiconductor layer and a second film forming step of forming an oxide film on the surface of the aluminum nitride film. And can have.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer, an annealing step of annealing the nitride semiconductor layer after the ion implantation step, and an annealing step.
  • the annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher.
  • a combination of ion implantation and annealing treatment of the p-type dopant is carried out a plurality of times.
  • the temperature of the annealing treatment in the ion implantation step is lower than the temperature of the heating step.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion injection step of ion-injecting a p-type dopant into one main surface of the nitride semiconductor layer, and the one of the nitride semiconductor layers after the ion injection step. It is possible to include a pivotal growth step of epitaxially growing a nitride semiconductor on the main surface, and an annealing treatment step of annealing the nitride semiconductor layer after the epitaxial growth step.
  • the p-type dopant is magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step.
  • the annealing treatment step can include a step of raising the temperature of the nitride semiconductor layer to a temperature of 1200 ° C. after setting the initial pressure to 50 MPa or more.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting magnesium as a p-type dopant into the nitride semiconductor layer, and an annealing treatment step of annealing the nitride semiconductor layer after the ion implantation step. And can be provided.
  • hydrogen is also ion-implanted into the magnesium introduction range.
  • the method for manufacturing a nitride semiconductor device is as follows: a gate insulating film film forming step of forming a gate insulating film on the surface of the nitride semiconductor layer, and a post annealing (Post Deposition) after the gate insulating film film forming step.
  • Annealing: PDA can be provided with a post-annealing process for processing.
  • the temperature and pressure in the post-annealing treatment step are set under conditions in which the solid phase of the state diagram is maintained based on the state diagram of the nitride semiconductor constituting the nitride semiconductor layer.

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Abstract

Ce procédé de fabrication d'un dispositif semi-conducteur au nitrure comprend : une étape d'implantation ionique pour implanter des ions d'un dopant de type p dans une couche semi-conductrice au nitrure ; une étape de formation de film protecteur pour former un film protecteur sur la surface de la couche semi-conductrice au nitrure après l'étape d'implantation ionique ; une étape de traitement de recuit pour recuire la couche de semi-conducteur au nitrure après l'étape de formation de film protecteur. L'étape de traitement de recuit comprend une étape de chauffage dans laquelle la couche semi-conductrice de nitrure est chauffée : à une température supérieure ou égale à 1200 °C ; dans une atmosphère d'ammoniac ; et à une pression inférieure à 10 kPa.
PCT/JP2020/005788 2020-02-14 2020-02-14 Procédé de fabrication d'un dispositif semi-conducteur au nitrure WO2021161509A1 (fr)

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WO2015015973A1 (fr) * 2013-07-31 2015-02-05 富士電機株式会社 Procédé de fabrication de dispositif à semi-conducteur et dispositif à semi-conducteur
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CN113913771A (zh) * 2021-10-09 2022-01-11 中紫半导体科技(东莞)有限公司 一种高激活率掺杂氮化铝单晶薄膜的制作方法

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