WO2021161509A1 - Method for manufacturing nitride semiconductor device - Google Patents

Method for manufacturing nitride semiconductor device Download PDF

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Publication number
WO2021161509A1
WO2021161509A1 PCT/JP2020/005788 JP2020005788W WO2021161509A1 WO 2021161509 A1 WO2021161509 A1 WO 2021161509A1 JP 2020005788 W JP2020005788 W JP 2020005788W WO 2021161509 A1 WO2021161509 A1 WO 2021161509A1
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Prior art keywords
nitride semiconductor
semiconductor layer
annealing
manufacturing
protective film
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PCT/JP2020/005788
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French (fr)
Japanese (ja)
Inventor
健太 渡邉
峰司 大川
紘子 井口
大悟 菊田
朋彦 森
大至 木村
Original Assignee
トヨタ自動車株式会社
株式会社豊田中央研究所
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Priority to PCT/JP2020/005788 priority Critical patent/WO2021161509A1/en
Publication of WO2021161509A1 publication Critical patent/WO2021161509A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Definitions

  • the technique disclosed in the present specification relates to a method for manufacturing a nitride semiconductor device.
  • Patent Document 1 discloses an example of a technique for forming a p-type region in a nitride semiconductor layer.
  • a method for manufacturing a nitride semiconductor device having a p-type region is required.
  • the method for manufacturing a nitride semiconductor device disclosed in the present specification includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film on the surface of the nitride semiconductor layer after the ion implantation step.
  • a protective film forming step for forming a film and an annealing treatment step for annealing the nitride semiconductor layer after the protective film forming step can be provided.
  • the annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher in an ammonia atmosphere and at a pressure lower than 10 kPa.
  • the nitride semiconductor layer In order to activate the p-type dopant in the nitride semiconductor layer, it is necessary to heat the nitride semiconductor layer to 1200 ° C. or higher. However, when the nitride semiconductor layer is heated to 1200 ° C. or higher, the surface of the nitride semiconductor layer is thermally decomposed. Even when the protective film is formed on the surface of the nitride semiconductor layer, nitrogen may escape from the surface of the nitride semiconductor layer through the grain boundaries of the protective film. According to this manufacturing method, nitrogen generated by thermal decomposition of ammonia is transferred to the surface of the nitride semiconductor layer through the grain boundaries of the protective film so as to compensate for the escape of nitrogen through the grain boundaries of the protective film. Is supplied to.
  • the cross-sectional view of the main part of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the second manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the third manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the third manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. It is the 4th manufacturing method of the nitride semiconductor apparatus of 1st Embodiment, and shows the time change of the temperature of the nitride semiconductor layer in the annealing process. It is the 5th manufacturing method of the nitride semiconductor apparatus of 1st Embodiment, and shows the flow of an ion implantation process.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown.
  • the cross-sectional view of the main part of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • a cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown.
  • the surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 6 kPa in an ammonia atmosphere is shown.
  • the surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 12 kPa in an ammonia atmosphere is shown.
  • the surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 20 kPa in an ammonia atmosphere is shown.
  • FIG. 1 shows a cross-sectional view of a main part of the nitride semiconductor device 1.
  • the nitride semiconductor device 1 includes a nitride semiconductor layer 20, a drain electrode 32 provided so as to cover the lower surface of the nitride semiconductor layer 20, and a source provided so as to cover the upper surface of the nitride semiconductor layer 20. It includes an electrode 34 and a planar type insulating gate 36 provided on a part of the upper surface of the nitride semiconductor layer 20.
  • the nitride semiconductor layer 20 includes an n-type drain region 21, an n-type drift region 22, an n-type JFET region 23, a p-type body region 24, an n-type source region 25, and a p-type body contact region. Has 26.
  • the drain region 21 is provided at a position exposed on the lower surface of the nitride semiconductor layer 20 and is in ohmic contact with the drain electrode 32.
  • the drain region 21 is made of gallium nitride (GaN) containing n-type impurities.
  • the drift region 22 is provided on the drain region 21, and is arranged between the drain region 21 and the JFET region 23 and between the drain region 21 and the body region 24.
  • the drift region 22 is made of gallium nitride (GaN) containing n-type impurities.
  • the JFET region 23 is provided on the drift region 22 and is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and extends in the thickness direction from the upper surface of the drift region 22 to the upper surface of the nitride semiconductor layer 20. It has a shape protruding from the upper surface of the drift region 22. In other words, the JFET region 23 extends from the upper surface of the nitride semiconductor layer 20 through the body region 24 to the drift region 22.
  • the JFET region 23 is made of gallium nitride (GaN) containing n-type impurities. In this example, the impurity concentration in the JFET region 23 is equal to the impurity concentration in the drift region 22, and can be said to be a part of the drift region 22.
  • the body region 24 is provided on the drift region 22 and is adjacent to the side surface of the JFET region 23.
  • the body region 24 has a high-concentration body region 24a and a low-concentration body region 24b.
  • the body region 24 is made of gallium nitride (GaN) containing p-type impurities.
  • the high-concentration body region 24a is arranged between the drift region 22 and the low-concentration body region 24b, and is in contact with the lower side surface of the JFET region 23.
  • the high-concentration body region 24a contains p-type impurities at a higher concentration than the low-concentration body region 24b, and is provided to prevent the low-concentration body region 24b from punching through when it is off.
  • the low-concentration body region 24b is provided on the high-concentration body region 24a, is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and is in contact with the upper side surface of the JFET region 23.
  • the impurity concentration in the low concentration body region 24b is adjusted to a desired gate threshold voltage.
  • a part of the low-concentration body region 24b located on the upper surface of the nitride semiconductor layer 20 and between the JFET region 23 and the source region 25 is particularly referred to as a channel region CH.
  • the source region 25 is provided on the low-concentration body region 24b, is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and is separated from the JFET region 23 by the low-concentration body region 24b.
  • the source region 25 is made of gallium nitride (GaN) containing n-type impurities.
  • the source region 25 is in ohmic contact with the source electrode 34.
  • the body contact region 26 is arranged on the low-concentration body region 24b, and is provided at a position exposed on the upper surface of the nitride semiconductor layer 20.
  • the body contact region 26 is made of gallium nitride (GaN) containing p-type impurities.
  • the body contact region 26 is in ohmic contact with the source electrode 34.
  • the insulating gate portion 36 is provided on a part of the upper surface of the nitride semiconductor layer 20, and has a silicon oxide gate insulating film 36a and a polysilicon gate electrode 36b.
  • the gate electrode 36b faces the channel region CH of the low-concentration body region 24b of the portion separating the JFET region 23 and the source region 25 and the JFET region 23 via the gate insulating film 36a.
  • the operation of the nitride semiconductor device 1 will be described.
  • a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded.
  • a positive voltage higher than the gate threshold voltage is applied to the gate electrode 36b, an inversion layer is formed in the channel region CH between the JFET region 23 and the source region 25, and the source region 25 to the JFET region via the inversion layer are formed. Electrons flow into 23. The electrons that have flowed into the JFET region 23 flow vertically through the JFET region 23 and head toward the drain electrode 32. As a result, the drain electrode 32 and the source electrode 34 become conductive, and the nitride semiconductor device 1 turns on.
  • the nitride semiconductor device 1 can execute a switching operation of switching on and off between the drain electrode 32 and the source electrode 34 based on the voltage applied to the gate electrode 36b.
  • an n-type GaN drift region 22 is epitaxially grown from the surface of a drain region 21 which is a GaN substrate to form a nitride semiconductor layer 20 by using an epitaxial growth technique.
  • silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 25.
  • magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using an ion implantation technique to form a body region 24 and a body contact region 26.
  • Magnesium is implanted into the nitride semiconductor layer 20 by a plurality of ion implantations at different implantation depths.
  • hydrogen may be ion-implanted into the magnesium injection range.
  • a highly active p-type region can be formed by co-injecting magnesium and hydrogen.
  • an amorphous protective film 42 for annealing is formed so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using the vapor deposition technique.
  • a vapor deposition technique a CVD method or a PVD method is used.
  • the CVD method for example, an atomic layer deposition method may be used.
  • the protective film 42 for annealing is a material that crystallizes in the subsequent annealing treatment for activation, and is, for example, aluminum nitride (AlN).
  • the protective film 42 for annealing may be aluminum gallium nitride (AlGaN), aluminum oxide (Al 2 O 3 ), zinc oxide (Zn O), or silicon oxide (SiO 2 ).
  • an annealing treatment step is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20.
  • This annealing treatment step includes a heating step of heating the nitride semiconductor layer 20 at a temperature of 1200 ° C. or higher, in an ammonia atmosphere, and at a low pressure of less than 10 kPa. More specifically, the temperature of this heating step is 1200 to 1500 ° C.
  • the amorphous protective film 42 for annealing crystallizes. At this time, grain boundaries may be formed that penetrate from the upper surface to the lower surface of the protective film 42 for annealing. Therefore, nitrogen may escape from the upper surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 42, and pits may be formed on the upper surface of the nitride semiconductor layer 20.
  • FIG. 2E shows that when this annealing treatment step is carried out, the amorphous protective film 42 for annealing crystallizes. At this time, grain boundaries may be formed that penetrate from the upper surface to the lower surface of the protective film 42 for annealing. Therefore, nitrogen may escape from the upper surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 42, and pits may be formed on the upper surface of the nitride semiconductor layer 20.
  • FIG. 2E shows that shows that this annealing treatment step is carried out.
  • the heating step during this annealing treatment step is carried out under a reduced pressure of less than 10 kPa, hydrogen generated by the thermal decomposition of ammonia is efficiently discharged from the annealing furnace. Therefore, the amount of hydrogen generated by thermal decomposition is suppressed from being supplied to the upper surface of the nitride semiconductor layer 20 via the grain boundaries of the annealing protective film 42. As described above, in the heating step carried out under reduced pressure, it is possible to prevent the upper surface of the nitride semiconductor layer 20 from being damaged by hydrogen generated by thermal decomposition.
  • FIGS. 10 to 12 show surface optical microscope images of the nitride semiconductor layer 20 after performing the heating step at 1400 ° C. in an ammonia atmosphere.
  • FIG. 10 shows the result of carrying out the heating step at a pressure of 6 kPa
  • FIG. 11 shows the result of carrying out the heating step at a pressure of 12 kPa
  • FIG. 12 shows the result of carrying out the heating step at a pressure of 20 kPa.
  • the density and size of the pits depends on the pressure during the heating process. From this result, in the heating step of the ammonia atmosphere, the formation of pits on the upper surface of the nitride semiconductor layer 20 can be suppressed by lowering the pressure during the heating step below the standard atmospheric pressure.
  • the pressure during the heating step may be less than 20 kPa, less than 15 kPa, less than 12 kPa, less than 11 kPa, less than 10 kPa, less than 9 kPa, less than 8 kPa, less than 7 kPa or less than 6 kPa.
  • the pressure during the heating process is reduced, the density of the pits can be further reduced and the size of the pits can be further reduced.
  • the pressure during the heating step is less than 10 kPa, the formation of pits can be remarkably suppressed. It should be noted that such a result is not limited to the case where the temperature of the heating step is 1400 ° C., and is the same when the temperature of the heating step is 1200 to 1500 ° C.
  • the amount of hydrogen generated by the thermal decomposition of ammonia is suppressed from being supplied to the upper surface of the nitride semiconductor layer 20, at least a part of the hydrogen generated by the thermal decomposition of ammonia is passed through the protective film 42 for annealing. It is introduced into the nitride semiconductor layer 20.
  • the hydrogen introduced into the nitride semiconductor layer 20 can be bonded to magnesium, which is a p-type dopant. Magnesium to which hydrogen is bound has the property of being easily taken up by Ga sites. Therefore, when the heating step is carried out in an ammonia atmosphere, magnesium can be efficiently incorporated into the Ga site.
  • magnesium and hydrogen are co-implanted in the ion implantation step, hydrogen generated by thermal decomposition of ammonia is present in the atmosphere, so that the ion-implanted hydrogen is difficult to be desorbed. Since hydrogen is less likely to be desorbed, it is possible to prevent hydrogen from being desorbed before the magnesium to which hydrogen is bound is incorporated into the Ga site. As a result, magnesium can be taken into the Ga site more efficiently.
  • the protective film 44 for dehydrogenation is applied so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using a vapor deposition technique.
  • a vapor deposition technique a CVD method or a PVD method is used.
  • the CVD method for example, an atomic layer deposition method may be used.
  • the dehydrogenation protective film 44 is a material having higher hydrogen permeability than the annealing protective film 42, and is, for example, silicon oxide (SiO 2 ).
  • an annealing treatment is performed in order to remove hydrogen in the nitride semiconductor layer 20.
  • the temperature is 500 to 1500 ° C.
  • hydrogen bonded to magnesium is removed from the nitride semiconductor layer 20, and magnesium, which is a p-type dopant, is activated.
  • uptake of magnesium into the Ga site, activation of magnesium, and removal of hydrogen can be performed by one annealing treatment. In this case, the dehydrogenation step shown in FIG. 2F can be omitted.
  • a gate insulating film 36a is formed so as to cover the upper surface of the nitride semiconductor layer 20 by using a vapor deposition technique.
  • a vapor deposition technique an atomic layer deposition method or a plasma CVD method is used.
  • a post-annealing (PDA) treatment is performed to improve the film quality of the gate insulating film 36a.
  • PDA post-annealing
  • a large amount of hydrogen remains in the gate insulating film 36a formed by using the vapor deposition technique.
  • gallium (Ga) may diffuse into the gate insulating film 36a.
  • the annealing step is carried out by a method other than the annealing step for activation described above, the surface of the nitride semiconductor layer 20 becomes excessive in Ga, so that a large amount of Ga is applied to the gate insulating film 36a in the post-annealing treatment. It will spread.
  • gallium (Ga) is diffused in the gate insulating film 36a, deterioration of electrical characteristics such as fluctuation of the gate threshold voltage becomes a problem.
  • the temperature and pressure of this post-annealing process are set under conditions in which the solid phase of the phase diagram is maintained based on the phase diagram of gallium nitride (GaN) constituting the nitride semiconductor layer 20.
  • the solid phase is maintained at a pressure of 1 MPa or more at a temperature of 1000 ° C. Therefore, the pressure of this post-annealing process is set to 1 MPa or more. More specifically, the temperature of the post-annealing treatment is 500 to 1500 ° C., and the pressure of the post-annealing treatment is 1 MPa to 1 GPa. Thereby, the film quality of the gate insulating film 36a can be improved while suppressing the thermal decomposition of the nitride semiconductor layer 20.
  • the gate electrode 36b is formed on the surface of the gate insulating film 36a by using the vapor deposition technique. Further, the gate insulating film 36a and the gate electrode 36b are processed by using the etching technique to form the insulated gate portion 36. After that, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured by forming the drain electrode 32 and the source electrode 34 by using a known manufacturing technique.
  • the steps up to the ion implantation step of the p-type dopant that is, the steps from FIGS. 2A to 2C can be the same as the first manufacturing method.
  • an amorphous protective film for annealing is used to cover the upper surface and the lower surface of the nitride semiconductor layer 20 and the extending side surface between the upper surface and the lower surface by using a vapor deposition technique. 46 is formed into a film. That is, the annealing protective film 46 is formed so as to cover the entire surface of the nitride semiconductor layer 20.
  • the protective film 46 for annealing is formed on the side surface of the unit cell of the device, it should be noted that the protective film 46 for annealing is actually formed on the side surface of the wafer. sea bream.
  • a CVD method or a PVD method is used.
  • CVD method a method having a high step coating property is desirable, and for example, an atomic layer deposition method may be used.
  • the PVD method in order to improve the step coating property, the nitride semiconductor layer 20 being formed is tilted at a predetermined speed while tilting the target cathode at an angle larger than 0 ° with respect to the nitride semiconductor layer 20. You may rotate it.
  • the protective film 46 for annealing is a material that crystallizes in the subsequent annealing treatment for activation, and is, for example, aluminum nitride (AlN).
  • AlN aluminum nitride
  • the protective film 46 for annealing may be aluminum gallium nitride (AlGaN), aluminum oxide (Al 2 O 3 ), zinc oxide (Zn O), or silicon oxide (SiO 2 ).
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step may be the same as the annealing treatment step of the first manufacturing method.
  • the annealing step under reduced pressure of less than 10 kPa is carried out.
  • the nitride semiconductor layer 20 is more easily thermally decomposed than under a pressure of 10 kPa or more. Therefore, when the annealing step of the first manufacturing method is adopted, by forming the protective film 46 for annealing on the side surface of the nitride semiconductor layer 20, not only the upper surface and the lower surface of the nitride semiconductor layer 20 but also the lower surface thereof are formed. Thermal decomposition of the side surface can also be suppressed. As described above, the technique of forming the protective film 46 for annealing on the side surface of the nitride semiconductor layer 20 is particularly useful when the annealing step of the first manufacturing method is adopted.
  • a protective film 46 for annealing is also formed on the side surface of the nitride semiconductor layer 20. Therefore, the decomposition of the GaN crystal on the side surface of the nitride semiconductor layer 20 can be suppressed, so that a large effective area of the device can be secured.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • the steps up to the ion implantation step of the p-type dopant that is, the steps from FIGS. 2A to 2C can be the same as the first manufacturing method.
  • an amorphous aluminum nitride film 48a is formed so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using the vapor deposition technique.
  • a CVD method or a PVD method is used as the vapor deposition technique.
  • the CVD method for example, an atomic layer deposition method may be used.
  • an oxide film 48b of aluminum oxide (Al 2 O 3 ) is formed on the surface of the aluminum nitride film 48a.
  • the laminated film of the aluminum nitride film 48a and the oxide film 48b serves as the protective film 48 for annealing.
  • the oxide film 48b may be formed by forming an aluminum nitride film 48a on each of the upper surface and the lower surface of the nitride semiconductor layer 20 and then performing heat treatment in an oxygen atmosphere, or by performing oxygen plasma irradiation. A film may be formed.
  • an oxide gas is added to the film forming raw material of aluminum nitride to form an oxide film 48b of aluminum nitride (AlON). May be formed.
  • the aluminum nitride film 48a and the aluminum nitride (AlON) oxide film 48b may be formed on the lower surface of the nitride semiconductor layer 20 by the CVD method.
  • the thickness of each of the aluminum nitride film 48a and the oxide film 48b is 1000 nm or less.
  • the annealing protective film 48 may also be formed on the side surface of the nitride semiconductor layer 20.
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step may be the same as the annealing treatment step of the first manufacturing method.
  • the oxide film 48b By forming the oxide film 48b, the amount of hydrogen generated by the thermal decomposition of ammonia can be further suppressed in the nitride semiconductor layer 20. As a result, it is possible to further prevent the surface of the nitride semiconductor layer 20 from being damaged by hydrogen.
  • the technique for forming the oxide film 48b is particularly useful when the annealing treatment step of the first production method is adopted.
  • Crystallization of the oxide film 48b is suppressed even in the annealing treatment at 1300 ° C. or higher. Therefore, it is suppressed that both the aluminum nitride film 48a and the oxide film 48b, that is, the grain boundaries penetrating from the upper surface to the lower surface of the protective film 48 for annealing are formed. Therefore, it is possible to prevent nitrogen from escaping from the surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 48 and forming pits on the surface of the nitride semiconductor layer 20.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • the steps up to the ion implantation step of the p-type dopant can be the same as the first manufacturing method.
  • the annealing protective film 42 of the first manufacturing method, the annealing protective film 46 of the second manufacturing method, or the annealing protective film 48 of the third manufacturing method is applied, and the nitride semiconductor layer 20 is applied.
  • a protective film for annealing is formed on the surface of the above.
  • FIG. 5 shows the time change of the temperature of the nitride semiconductor layer 20 in the annealing process.
  • the annealing process includes a temperature raising step of raising the temperature of the nitride semiconductor layer 20 from time t 0 to time t 2 and a heating step of heating the nitride semiconductor layer 20 at temperature T 2 from time t 2 to time t 3. And have.
  • the temperature T 2 in the heating step is 1200 ° C. or higher. More specifically, the temperature T 2 in the heating step is 1200 to 1500 ° C.
  • the atmospheric gas and pressure in the heating step are not particularly limited. For example, this heating step can be the same as the heating step of the annealing step of the first manufacturing method.
  • the temperature of the nitride semiconductor layer 20 starts to rise from time t 0, and the temperature of the nitride semiconductor layer 20 reaches 1200 ° C. at time t 1 (when the heating temperature T 2 is 1200 ° C., Time t 1 and time t 2 are the same).
  • the temperature rising rate from time t 0 to time t 2 is 1 to 100 ° C./min.
  • the initial pressure in the annealing furnace at time t 0 is 50 Mpa or more.
  • the protective film for annealing (protective films 42, 46, 48 for annealing in the first to third manufacturing methods) formed on the surface of the nitride semiconductor layer 20 prior to the annealing treatment step is formed in an amorphous state. Will be done.
  • This protective film for annealing crystallizes when the temperature rises, and is crystallized by the time t 1 when the temperature of the nitride semiconductor layer 20 reaches at least 1200 ° C. Therefore, the protective film for annealing from time t 0 to time t 1 may be in an amorphous state, and nitrogen is easily released from the upper surface of the nitride semiconductor layer 20.
  • the solid phase is at a pressure of 50 MPa or more at a temperature of 1200 ° C.
  • the initial pressure in the annealing furnace at time t 0 is set to 50 Mpa or more
  • the pressure in the annealing furnace from time t 0 to time t 1 is maintained to be 50 Mpa or more.
  • NS the thermal decomposition of the nitride semiconductor layer 20 can be suppressed between the time t 0 and the time t 1, so that the escape of nitrogen from the upper surface of the nitride semiconductor layer 20 can be suppressed.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using the ion implantation technique.
  • the amount of magnesium ion-implanted is less than the amount ultimately required to form the body region 24 and the body contact region 26.
  • hydrogen may also be ion-implanted into the magnesium injection range.
  • step S2 an annealing treatment is performed in order to recover the crystal defects formed by the previous ion implantation.
  • the temperature of this annealing treatment is less than 1200 ° C. More specifically, in this annealing treatment, the temperature is 500 to 1000 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • step S3 it is determined whether or not the number of treatments in the process combining the ion implantation and the annealing treatment has reached a predetermined number of times. If the number of processes has not reached the predetermined number, the process returns to step S1. When the number of treatments reaches a predetermined number, that is, when the amount of magnesium ion-implanted exceeds the amount finally required to form the body region 24 and the body contact region 26, the process proceeds to step S4.
  • a protective film for annealing is formed on the surface of the nitride semiconductor layer 20.
  • the protective film for annealing any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
  • step S5 an annealing treatment step is carried out in order to activate the n-type dopant and the p-type dopant of the nitride semiconductor layer 20.
  • this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods.
  • pores are formed in the nitride semiconductor layer 20.
  • the nitride semiconductor layer 20 in which such pore-type defects are present is subjected to a high-temperature (1200 ° C. or higher) annealing treatment for activating the dopant, the pore-type defects are aggregated and the donor-type defects are aggregated. Is formed. As a result, the activation rate of the p-type dopant decreases, and it becomes difficult to form a highly active p-type region.
  • a plurality of steps of combining ion implantation and low temperature (less than 1200 ° C.) annealing treatment are performed.
  • the amount of pores formed for each ion implantation can be suppressed.
  • the density of pore-shaped defects in the nitride semiconductor layer 20 can be reduced. Therefore, when the annealing treatment at a high temperature (1200 ° C.
  • the density of the pore-type defects in the nitride semiconductor layer 20 is sufficiently low, so that the aggregation of the pore-type defects is suppressed.
  • NS the activation rate of the p-type dopant can be increased, and a highly active p-type region can be formed.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • a protective film for annealing in step S4 may be formed between steps S1 and S2. In this case, if the determination result in step S3 is NO, the process returns to step S1 after removing the protective film for annealing.
  • an n-type GaN drift region 22 is epitaxially grown from the surface of a drain region 21 which is a GaN substrate to form a nitride semiconductor layer 20 by using an epitaxial growth technique.
  • magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using an ion implantation technique to form a high-concentration body region 24a.
  • the surface concentration of magnesium contained in the high-concentration body region 24a is 1 ⁇ 10 18 cm -3 or more.
  • hydrogen may also be ion-implanted into the magnesium injection range.
  • n-type GaN is epitaxially grown from the surface of the drift region 22 by using the epitaxial growth technique.
  • the magnesium contained in the high-concentration body region 24a diffuses into the epitaxial growth layer, so that the low-concentration body region 24b is formed.
  • hydrogen derived from the material used in the epitaxial regrowth step is incorporated into the high-concentration body region 24a and the low-concentration body region 24b.
  • silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 25. Further, using the ion implantation technique, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant to form the body contact region 26.
  • a protective film for annealing is formed on the surface of the nitride semiconductor layer 20.
  • the protective film for annealing any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods.
  • the first production method when the first production method is adopted in the annealing process for activating the p-type dopant, if the amount of ion-implanted p-type dopant is large, some hydrogen generated by the decomposition of ammonia may be used. The amount of hydrogen introduced into the nitride semiconductor layer 20 may be insufficient.
  • hydrogen is incorporated into the nitride semiconductor layer 20 before the annealing treatment step, so that a highly active p-type region can be formed.
  • the technique utilizing the epitaxial growth technique can effectively form a highly active p-type region by combining with the annealing step of the first production method.
  • the subsequent steps can be the same as the first manufacturing method.
  • the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
  • FIG. 8 shows a cross-sectional view of a main part of the nitride semiconductor device 2.
  • the nitride semiconductor device 2 includes a nitride semiconductor layer 120, a drain electrode 132 provided so as to cover the lower surface of the nitride semiconductor layer 120, and a source provided so as to cover the upper surface of the nitride semiconductor layer 120. It includes an electrode 134 and a trench-type insulating gate portion 136 provided in a trench formed in a part of the upper surface of the nitride semiconductor layer 120.
  • the nitride semiconductor layer 120 has an n-type drain region 121, an n-type drift region 122, a p-type body region 124, an n-type source region 125, and a p-type body contact region 126.
  • the drain region 121 is provided at a position exposed on the lower surface of the nitride semiconductor layer 120, and is in ohmic contact with the drain electrode 132.
  • the drain region 121 is made of gallium nitride (GaN) containing n-type impurities.
  • the drift area 122 is provided on the drain area 121, and is arranged between the drain area 121 and the body area 124.
  • the drift region 122 is made of gallium nitride (GaN) containing n-type impurities.
  • the body region 124 is provided on the drift region 122, and has a high-concentration body region 124a and a low-concentration body region 124b.
  • the body region 124 is made of gallium nitride (GaN) containing p-type impurities.
  • the high-concentration body region 124a is arranged between the drift region 122 and the low-concentration body region 124b, and is provided away from the side surface of the insulated gate portion 136.
  • the high-concentration body region 124a contains p-type impurities at a higher concentration than the low-concentration body region 124b, and is provided to relax the electric field at the bottom corner of the insulating gate portion 136 when it is off.
  • the low-concentration body region 124b is provided on the high-concentration body region 124a, is provided at a position exposed on the upper surface of the nitride semiconductor layer 120, and is in contact with the side surface of the insulating gate portion 136.
  • the impurity concentration in the low concentration body region 124b is adjusted to a desired gate threshold voltage.
  • a part of the low-concentration body region 124b located in contact with the side surface of the insulated gate portion 136 and between the drift region 122 and the source region 125 is particularly referred to as a channel region CH.
  • the source region 125 is provided on the low-concentration body region 124b, is provided at a position exposed on the upper surface of the nitride semiconductor layer 120, and is separated from the drift region 122 by the low-concentration body region 124b.
  • the source region 125 is made of gallium nitride (GaN) containing n-type impurities.
  • the source region 125 is in ohmic contact with the source electrode 134.
  • the body contact region 126 is arranged on the low-concentration body region 124b, and is provided at a position exposed on the upper surface of the nitride semiconductor layer 120.
  • the body contact region 126 is made of gallium nitride (GaN) containing p-type impurities.
  • the body contact region 126 is in ohmic contact with the source electrode 134.
  • the insulated gate portion 136 is provided in a trench formed in a part of the upper surface of the nitride semiconductor layer 120, and has a silicon oxide gate insulating film 136a and a polysilicon gate electrode 136b.
  • the gate electrode 136b faces the channel region CH of the low-concentration body region 124b of the portion separating the drift region 122 and the source region 125 via the gate insulating film 136a.
  • a positive voltage is applied to the drain electrode 132, and the source electrode 134 is grounded.
  • a positive voltage higher than the gate threshold voltage is applied to the gate electrode 136b, an inversion layer is formed in the channel region CH between the drift region 122 and the source region 125, and an inversion layer is formed from the source region 125 to the drift region via the inversion layer. Electrons flow into 122. The electrons that have flowed into the drift region 122 flow vertically through the drift region 122 and head toward the drain electrode 132. As a result, the drain electrode 132 and the source electrode 134 become conductive, and the nitride semiconductor device 2 turns on.
  • the nitride semiconductor device 2 can execute a switching operation of switching on and off between the drain electrode 132 and the source electrode 134 based on the voltage applied to the gate electrode 136b.
  • an n-type GaN drift region 122 is epitaxially grown from the surface of a drain region 121, which is a GaN substrate, to form a nitride semiconductor layer 120 by using an epitaxial growth technique.
  • magnesium is ion-implanted into the nitride semiconductor layer 120 as a p-type dopant by using an ion implantation technique to form a high-concentration body region 124a.
  • hydrogen may also be ion-implanted into the magnesium injection range.
  • the low-concentration body region 124b of p-type GaN is epitaxially grown from the surface of the drift region 122 by using the epitaxial growth technique.
  • hydrogen derived from the material used in the epitaxial regrowth step is taken into the high-concentration body region 124a and the low-concentration body region 124b.
  • silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 125. Further, using the ion implantation technique, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant to form the body contact region 126.
  • a protective film for annealing is formed on the surface of the nitride semiconductor layer 120.
  • the protective film for annealing any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
  • an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant.
  • the temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C.
  • the atmospheric gas and pressure of the annealing treatment are not particularly limited.
  • this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods of the nitride semiconductor device 1 of the first embodiment.
  • a dry etching technique is used to form a trench TR1 that penetrates the source region 125 and the low-concentration body region 124b from the upper surface of the nitride semiconductor layer 120 and reaches the drift region 122. ..
  • a gate insulating film 136a is formed so as to cover the upper surface of the nitride semiconductor layer 120 including the inner wall surface of the trench TR1 by using a thin film deposition technique.
  • a vapor deposition technique an atomic layer deposition method or a plasma CVD method is used.
  • a post-deposition annealing (PDA) treatment is performed to improve the film quality of the gate insulating film 136a.
  • the post-annealing process can be the same as the post-annealing process of the first manufacturing method of the nitride semiconductor device 1 of the first embodiment.
  • a gate electrode 136b is formed on the surface of the gate insulating film 136a so as to be filled in the trench TR1 by using a thin film deposition technique. Further, the gate insulating film 136a and the gate electrode 136b are processed by using the etching technique to form the insulated gate portion 136. After that, the nitride semiconductor device 2 shown in FIG. 8 can be manufactured by forming the drain electrode 132 and the source electrode 134 by using a known manufacturing technique.
  • the technique of incorporating hydrogen derived from a material by epitaxial regrowth can be applied to a p-type region other than the body region, and can also be applied to a peripheral pressure resistant structure such as a guard ring or a resurf layer.
  • the epitaxial growth layer formed by epitaxial regrowth can be n-type, p-type or i-type depending on the structure to be formed. Further, the epitaxial growth layer formed by epitaxial regrowth may be removed if necessary.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step.
  • the annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher under an ammonia atmosphere and at a pressure lower than the standard atmospheric pressure (100 kPa).
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step. In the protective film forming step, the protective film is formed on the surface of the nitride semiconductor layer so as to cover the side surfaces extending between the pair of main surfaces of the nitride semiconductor layer.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step.
  • an annealing treatment step of annealing the nitride semiconductor layer can be provided.
  • the protective film film forming step includes a first film forming step of forming an aluminum nitride film on the surface of the nitride semiconductor layer and a second film forming step of forming an oxide film on the surface of the aluminum nitride film. And can have.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer, an annealing step of annealing the nitride semiconductor layer after the ion implantation step, and an annealing step.
  • the annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher.
  • a combination of ion implantation and annealing treatment of the p-type dopant is carried out a plurality of times.
  • the temperature of the annealing treatment in the ion implantation step is lower than the temperature of the heating step.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion injection step of ion-injecting a p-type dopant into one main surface of the nitride semiconductor layer, and the one of the nitride semiconductor layers after the ion injection step. It is possible to include a pivotal growth step of epitaxially growing a nitride semiconductor on the main surface, and an annealing treatment step of annealing the nitride semiconductor layer after the epitaxial growth step.
  • the p-type dopant is magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step.
  • the annealing treatment step can include a step of raising the temperature of the nitride semiconductor layer to a temperature of 1200 ° C. after setting the initial pressure to 50 MPa or more.
  • the type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
  • the method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting magnesium as a p-type dopant into the nitride semiconductor layer, and an annealing treatment step of annealing the nitride semiconductor layer after the ion implantation step. And can be provided.
  • hydrogen is also ion-implanted into the magnesium introduction range.
  • the method for manufacturing a nitride semiconductor device is as follows: a gate insulating film film forming step of forming a gate insulating film on the surface of the nitride semiconductor layer, and a post annealing (Post Deposition) after the gate insulating film film forming step.
  • Annealing: PDA can be provided with a post-annealing process for processing.
  • the temperature and pressure in the post-annealing treatment step are set under conditions in which the solid phase of the state diagram is maintained based on the state diagram of the nitride semiconductor constituting the nitride semiconductor layer.

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Abstract

This method for manufacturing a nitride semiconductor device comprises: an ion implantation step for implanting ions of a p-type dopant into a nitride semiconductor layer; a protective film formation step for forming a protective film on the surface of the nitride semiconductor layer after the ion implantation step; an annealing treatment step for annealing the nitride semiconductor layer after the protective film formation step. The annealing treatment step has a heating step in which the nitride semiconductor layer is heated: at a temperature of 1200°C or higher; in an ammonia atmosphere; and at a pressure lower than 10 kPa.

Description

窒化物半導体装置の製造方法Nitride semiconductor device manufacturing method
　本明細書が開示する技術は、窒化物半導体装置の製造方法に関する。 The technique disclosed in the present specification relates to a method for manufacturing a nitride semiconductor device.
　窒化物半導体装置を製造するためには、窒化物半導体層内にｐ型領域を形成する工程が必要である。特許文献１には、窒化物半導体層内にｐ型領域を形成する技術の一例が開示されている。 In order to manufacture a nitride semiconductor device, a step of forming a p-type region in the nitride semiconductor layer is required. Patent Document 1 discloses an example of a technique for forming a p-type region in a nitride semiconductor layer.
特開２０１７－０５４９４４号公報Japanese Unexamined Patent Publication No. 2017-054944
　ｐ型領域を有する窒化物半導体装置の製造方法が必要とされている。 A method for manufacturing a nitride semiconductor device having a p-type region is required.
　本明細書が開示する窒化物半導体装置の製造方法は、窒化物半導体層にｐ型ドーパントをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層の表面上に保護膜を成膜する保護膜成膜工程と、前記保護膜成膜工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記アニール処理工程は、１２００℃以上の温度であって、アンモニア雰囲気下、且つ、１０ｋＰａよりも低い圧力で前記窒化物半導体層を加熱する加熱工程、を有することができる。前記窒化物半導体層内の前記ｐ型ドーパントを活性化させるためには、前記窒化物半導体層を１２００℃以上に加熱する必要がある。ところが、前記窒化物半導体層を１２００℃以上に加熱すると、前記窒化物半導体層の表面が熱分解してしまう。前記窒化物半導体層の表面上に前記保護膜を成膜した場合でも、前記窒化物半導体層の表面から前記保護膜の粒界を介して窒素が抜ける虞がある。この製造方法によると、前記保護膜の粒界を介して窒素が抜けるのを補償するように、アンモニアの熱分解で生じた窒素が前記保護膜の粒界を介して前記窒化物半導体層の表面に供給される。これにより、前記窒化物半導体層の表面にピットが形成されるのを抑えることができる。このように、上記製造方法によると、前記窒化物半導体層の表面にピットが形成されるのを抑えながら、ｐ型領域を有する窒化物半導体装置を製造することができる。さらに、この加熱工程では、１０ｋＰａ未満の減圧下で実施されるので、アンモニアの熱分解で生じた水素が効率的にアニール炉から排出される。このため、熱分解で生じた水素が前記保護膜の粒界を介して前記窒化物半導体層の表面に供給される量が抑えられる。このように、減圧下で実施される加熱工程では、熱分解で生じた水素によって前記窒化物半導体層の表面にダメージが加えられることが抑えられる。 The method for manufacturing a nitride semiconductor device disclosed in the present specification includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film on the surface of the nitride semiconductor layer after the ion implantation step. A protective film forming step for forming a film and an annealing treatment step for annealing the nitride semiconductor layer after the protective film forming step can be provided. The annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher in an ammonia atmosphere and at a pressure lower than 10 kPa. In order to activate the p-type dopant in the nitride semiconductor layer, it is necessary to heat the nitride semiconductor layer to 1200 ° C. or higher. However, when the nitride semiconductor layer is heated to 1200 ° C. or higher, the surface of the nitride semiconductor layer is thermally decomposed. Even when the protective film is formed on the surface of the nitride semiconductor layer, nitrogen may escape from the surface of the nitride semiconductor layer through the grain boundaries of the protective film. According to this manufacturing method, nitrogen generated by thermal decomposition of ammonia is transferred to the surface of the nitride semiconductor layer through the grain boundaries of the protective film so as to compensate for the escape of nitrogen through the grain boundaries of the protective film. Is supplied to. As a result, it is possible to suppress the formation of pits on the surface of the nitride semiconductor layer. As described above, according to the above-mentioned manufacturing method, it is possible to manufacture a nitride semiconductor device having a p-type region while suppressing the formation of pits on the surface of the nitride semiconductor layer. Further, since this heating step is carried out under a reduced pressure of less than 10 kPa, hydrogen generated by the thermal decomposition of ammonia is efficiently discharged from the annealing furnace. Therefore, the amount of hydrogen generated by thermal decomposition is suppressed from being supplied to the surface of the nitride semiconductor layer through the grain boundaries of the protective film. As described above, in the heating step carried out under reduced pressure, it is possible to prevent the surface of the nitride semiconductor layer from being damaged by hydrogen generated by thermal decomposition.
第１実施形態の窒化物半導体装置の要部断面図を模式的に示す。The cross-sectional view of the main part of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第１の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the first manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第２の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the second manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第３の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the third manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第３の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the third manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第４の製造方法であって、アニール処理工程における窒化物半導体層の温度の時間変化を示す。It is the 4th manufacturing method of the nitride semiconductor apparatus of 1st Embodiment, and shows the time change of the temperature of the nitride semiconductor layer in the annealing process. 第１実施形態の窒化物半導体装置の第５の製造方法であって、イオン注入工程のフローを示す。It is the 5th manufacturing method of the nitride semiconductor apparatus of 1st Embodiment, and shows the flow of an ion implantation process. 第１実施形態の窒化物半導体装置の第６の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第６の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第６の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第１実施形態の窒化物半導体装置の第６の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the sixth manufacturing method of the nitride semiconductor device of the first embodiment is schematically shown. 第２実施形態の窒化物半導体装置の要部断面図を模式的に示す。The cross-sectional view of the main part of the nitride semiconductor device of the second embodiment is schematically shown. 第２実施形態の窒化物半導体装置の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown. 第２実施形態の窒化物半導体装置の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown. 第２実施形態の窒化物半導体装置の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown. 第２実施形態の窒化物半導体装置の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown. 第２実施形態の窒化物半導体装置の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown. 第２実施形態の窒化物半導体装置の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown. 第２実施形態の窒化物半導体装置の製造方法の一製造過程における要部断面図を模式的に示す。A cross-sectional view of a main part in one manufacturing process of the manufacturing method of the nitride semiconductor device of the second embodiment is schematically shown. アンモニア雰囲気下、１４００℃の温度、６ｋＰａの圧力の加熱工程を実施した後の窒化物半導体層の表面光学顕微鏡像を示す。The surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 6 kPa in an ammonia atmosphere is shown. アンモニア雰囲気下、１４００℃の温度、１２ｋＰａの圧力の加熱工程を実施した後の窒化物半導体層の表面光学顕微鏡像を示す。The surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 12 kPa in an ammonia atmosphere is shown. アンモニア雰囲気下、１４００℃の温度、２０ｋＰａの圧力の加熱工程を実施した後の窒化物半導体層の表面光学顕微鏡像を示す。The surface optical microscope image of the nitride semiconductor layer after carrying out the heating process at a temperature of 1400 ° C. and a pressure of 20 kPa in an ammonia atmosphere is shown.
　以下、図面を参照して各実施形態の半導体装置を説明する。各図面において、図示明瞭化を目的とし、共通する構成要素についてはそれらの１つの構成要素にのみ符号を付すことがある。 Hereinafter, the semiconductor device of each embodiment will be described with reference to the drawings. In each drawing, for the purpose of clarifying the illustration, only one of the common components may be indicated by a reference.
（第１実施形態の窒化物半導体装置１）
　図１に、窒化物半導体装置１の要部断面図を示す。窒化物半導体装置１は、窒化物半導体層２０、窒化物半導体層２０の下面を被覆するように設けられているドレイン電極３２、窒化物半導体層２０の上面を被覆するように設けられているソース電極３４、及び、窒化物半導体層２０の上面の一部に設けられているプレーナー型の絶縁ゲート部３６を備えている。窒化物半導体層２０は、ｎ型のドレイン領域２１、ｎ型のドリフト領域２２、ｎ型のＪＦＥＴ領域２３、ｐ型のボディ領域２４、ｎ型のソース領域２５、及び、ｐ型のボディコンタクト領域２６を有している。 (Nitride semiconductor device 1 of the first embodiment)
FIG. 1 shows a cross-sectional view of a main part of the nitride semiconductor device 1. The nitride semiconductor device 1 includes a nitride semiconductor layer 20, a drain electrode 32 provided so as to cover the lower surface of the nitride semiconductor layer 20, and a source provided so as to cover the upper surface of the nitride semiconductor layer 20. It includes an electrode 34 and a planar type insulating gate 36 provided on a part of the upper surface of the nitride semiconductor layer 20. The nitride semiconductor layer 20 includes an n-type drain region 21, an n-type drift region 22, an n-type JFET region 23, a p-type body region 24, an n-type source region 25, and a p-type body contact region. Has 26.
　ドレイン領域２１は、窒化物半導体層２０の下面に露出する位置に設けられており、ドレイン電極３２にオーミック接触している。ドレイン領域２１は、ｎ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。 The drain region 21 is provided at a position exposed on the lower surface of the nitride semiconductor layer 20 and is in ohmic contact with the drain electrode 32. The drain region 21 is made of gallium nitride (GaN) containing n-type impurities.
　ドリフト領域２２は、ドレイン領域２１上に設けられており、ドレイン領域２１とＪＦＥＴ領域２３の間、且つ、ドレイン領域２１とボディ領域２４の間に配置されている。ドリフト領域２２は、ｎ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。 The drift region 22 is provided on the drain region 21, and is arranged between the drain region 21 and the JFET region 23 and between the drain region 21 and the body region 24. The drift region 22 is made of gallium nitride (GaN) containing n-type impurities.
　ＪＦＥＴ領域２３は、ドリフト領域２２上に設けられており、窒化物半導体層２０の上面に露出する位置に設けられており、ドリフト領域２２の上面から窒化物半導体層２０の上面まで厚み方向に延びており、ドリフト領域２２の上面から突出した形態を有している。換言すると、ＪＦＥＴ領域２３は、窒化物半導体層２０の上面からボディ領域２４を貫通してドリフト領域２２まで延びている。ＪＦＥＴ領域２３は、ｎ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。この例では、ＪＦＥＴ領域２３の不純物濃度は、ドリフト領域２２の不純物濃度と等しく、ドリフト領域２２の一部と言うことができる。 The JFET region 23 is provided on the drift region 22 and is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and extends in the thickness direction from the upper surface of the drift region 22 to the upper surface of the nitride semiconductor layer 20. It has a shape protruding from the upper surface of the drift region 22. In other words, the JFET region 23 extends from the upper surface of the nitride semiconductor layer 20 through the body region 24 to the drift region 22. The JFET region 23 is made of gallium nitride (GaN) containing n-type impurities. In this example, the impurity concentration in the JFET region 23 is equal to the impurity concentration in the drift region 22, and can be said to be a part of the drift region 22.
　ボディ領域２４は、ドリフト領域２２上に設けられており、ＪＦＥＴ領域２３の側面に隣接している。ボディ領域２４は、高濃度ボディ領域２４ａ及び低濃度ボディ領域２４ｂを有している。ボディ領域２４は、ｐ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。 The body region 24 is provided on the drift region 22 and is adjacent to the side surface of the JFET region 23. The body region 24 has a high-concentration body region 24a and a low-concentration body region 24b. The body region 24 is made of gallium nitride (GaN) containing p-type impurities.
　高濃度ボディ領域２４ａは、ドリフト領域２２と低濃度ボディ領域２４ｂの間に配置されているとともに、ＪＦＥＴ領域２３の下側の側面に接している。高濃度ボディ領域２４ａは、低濃度ボディ領域２４ｂよりもｐ型不純物を高濃度に含んでおり、オフのときに低濃度ボディ領域２４ｂがパンチスルーするのを抑えるために設けられている。 The high-concentration body region 24a is arranged between the drift region 22 and the low-concentration body region 24b, and is in contact with the lower side surface of the JFET region 23. The high-concentration body region 24a contains p-type impurities at a higher concentration than the low-concentration body region 24b, and is provided to prevent the low-concentration body region 24b from punching through when it is off.
　低濃度ボディ領域２４ｂは、高濃度ボディ領域２４ａ上に設けられており、窒化物半導体層２０の上面に露出する位置に設けられており、ＪＦＥＴ領域２３の上側の側面に接している。低濃度ボディ領域２４ｂの不純物濃度は、所望のゲート閾値電圧となるように調整されている。窒化物半導体層２０の上面に露出する位置にあるとともにＪＦＥＴ領域２３とソース領域２５の間に位置する低濃度ボディ領域２４ｂの一部を特にチャネル領域ＣＨという。 The low-concentration body region 24b is provided on the high-concentration body region 24a, is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and is in contact with the upper side surface of the JFET region 23. The impurity concentration in the low concentration body region 24b is adjusted to a desired gate threshold voltage. A part of the low-concentration body region 24b located on the upper surface of the nitride semiconductor layer 20 and between the JFET region 23 and the source region 25 is particularly referred to as a channel region CH.
　ソース領域２５は、低濃度ボディ領域２４ｂ上に設けられており、窒化物半導体層２０の上面に露出する位置に設けられており、低濃度ボディ領域２４ｂによってＪＦＥＴ領域２３から隔てられている。ソース領域２５は、ｎ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。ソース領域２５は、ソース電極３４にオーミック接触している。 The source region 25 is provided on the low-concentration body region 24b, is provided at a position exposed on the upper surface of the nitride semiconductor layer 20, and is separated from the JFET region 23 by the low-concentration body region 24b. The source region 25 is made of gallium nitride (GaN) containing n-type impurities. The source region 25 is in ohmic contact with the source electrode 34.
　ボディコンタクト領域２６は、低濃度ボディ領域２４ｂ上に配置されており、窒化物半導体層２０の上面に露出する位置に設けられている。ボディコンタクト領域２６は、ｐ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。ボディコンタクト領域２６は、ソース電極３４にオーミック接触している。 The body contact region 26 is arranged on the low-concentration body region 24b, and is provided at a position exposed on the upper surface of the nitride semiconductor layer 20. The body contact region 26 is made of gallium nitride (GaN) containing p-type impurities. The body contact region 26 is in ohmic contact with the source electrode 34.
　絶縁ゲート部３６は、窒化物半導体層２０の上面の一部に設けられており、酸化シリコンのゲート絶縁膜３６ａ及びポリシリコンのゲート電極３６ｂを有している。ゲート電極３６ｂは、ＪＦＥＴ領域２３とソース領域２５を隔てる部分の低濃度ボディ領域２４ｂのチャネル領域ＣＨ、及び、ＪＦＥＴ領域２３にゲート絶縁膜３６ａを介して対向している。 The insulating gate portion 36 is provided on a part of the upper surface of the nitride semiconductor layer 20, and has a silicon oxide gate insulating film 36a and a polysilicon gate electrode 36b. The gate electrode 36b faces the channel region CH of the low-concentration body region 24b of the portion separating the JFET region 23 and the source region 25 and the JFET region 23 via the gate insulating film 36a.
　次に、窒化物半導体装置１の動作を説明する。使用時には、ドレイン電極３２に正電圧が印加され、ソース電極３４が接地される。ゲート電極３６ｂにゲート閾値電圧よりも高い正電圧が印加されると、ＪＦＥＴ領域２３とソース領域２５の間のチャネル領域ＣＨに反転層が形成され、その反転層を介してソース領域２５からＪＦＥＴ領域２３に電子が流入する。ＪＦＥＴ領域２３に流入した電子は、そのＪＦＥＴ領域２３を縦方向に流れてドレイン電極３２に向かう。これにより、ドレイン電極３２とソース電極３４が導通し、窒化物半導体装置１がターンオンする。ゲート電極３６ｂが接地されると、反転層が消失し、窒化物半導体装置１がターンオフする。このように、窒化物半導体装置１は、ゲート電極３６ｂに印加する電圧に基づいてドレイン電極３２とソース電極３４の間のオンとオフを切り換えるスイッチング動作を実行することができる。 Next, the operation of the nitride semiconductor device 1 will be described. At the time of use, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 36b, an inversion layer is formed in the channel region CH between the JFET region 23 and the source region 25, and the source region 25 to the JFET region via the inversion layer are formed. Electrons flow into 23. The electrons that have flowed into the JFET region 23 flow vertically through the JFET region 23 and head toward the drain electrode 32. As a result, the drain electrode 32 and the source electrode 34 become conductive, and the nitride semiconductor device 1 turns on. When the gate electrode 36b is grounded, the inversion layer disappears and the nitride semiconductor device 1 turns off. In this way, the nitride semiconductor device 1 can execute a switching operation of switching on and off between the drain electrode 32 and the source electrode 34 based on the voltage applied to the gate electrode 36b.
（窒化物半導体装置１の第１の製造方法）
　まず、図２Ａに示されるように、エピタキシャル成長技術を利用して、ＧａＮ基板であるドレイン領域２１の表面からｎ型ＧａＮのドリフト領域２２をエピタキシャル成長させ、窒化物半導体層２０を形成する。 (First Manufacturing Method of Nitride Semiconductor Device 1)
First, as shown in FIG. 2A, an n-type GaN drift region 22 is epitaxially grown from the surface of a drain region 21 which is a GaN substrate to form a nitride semiconductor layer 20 by using an epitaxial growth technique.
　次に、図２Ｂに示されるように、イオン注入技術を利用して、窒化物半導体層２０にｎ型ドーパントとしてシリコン又はゲルマニウムをイオン注入し、ソース領域２５を形成する。 Next, as shown in FIG. 2B, silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 25.
　次に、図２Ｃに示されるように、イオン注入技術を利用して、窒化物半導体層２０にｐ型ドーパントとしてマグネシウムをイオン注入し、ボディ領域２４及びボディコンタクト領域２６を形成する。マグネシウムは、注入深さを変えた複数回のイオン注入によって窒化物半導体層２０に注入される。このとき、マグネシウムの注入範囲に水素をイオン注入してもよい。後述するように、マグネシウムと水素を共注入することにより、高活性なｐ型領域を形成することができる。 Next, as shown in FIG. 2C, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using an ion implantation technique to form a body region 24 and a body contact region 26. Magnesium is implanted into the nitride semiconductor layer 20 by a plurality of ion implantations at different implantation depths. At this time, hydrogen may be ion-implanted into the magnesium injection range. As will be described later, a highly active p-type region can be formed by co-injecting magnesium and hydrogen.
　次に、図２Ｄに示されるように、蒸着技術を利用して、窒化物半導体層２０の上面及び下面を被覆するように、アモルファスのアニール用保護膜４２を成膜する。蒸着技術としては、ＣＶＤ法又はＰＶＤ法が用いられる。ＣＶＤ法としては、例えば原子層堆積法が用いられてもよい。アニール用保護膜４２は、この後の活性化のためのアニール処理において結晶化する材料であり、例えば窒化アルミニウム（ＡｌＮ）である。この例に代えて、アニール用保護膜４２は、窒化アルミニウムガリウム（ＡｌＧａＮ）、酸化アルミニウム（Ａｌ2Ｏ3）、酸化亜鉛（ＺｎＯ）又は酸化シリコン（ＳｉＯ2）であってもよい。 Next, as shown in FIG. 2D, an amorphous protective film 42 for annealing is formed so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using the vapor deposition technique. As the vapor deposition technique, a CVD method or a PVD method is used. As the CVD method, for example, an atomic layer deposition method may be used. The protective film 42 for annealing is a material that crystallizes in the subsequent annealing treatment for activation, and is, for example, aluminum nitride (AlN). Instead of this example, the protective film 42 for annealing may be aluminum gallium nitride (AlGaN), aluminum oxide (Al 2 O 3 ), zinc oxide (Zn O), or silicon oxide (SiO 2 ).
　次に、図２Ｅに示されるように、窒化物半導体層２０内のｎ型ドーパント及びｐ型ドーパントを活性化させるために、アニール処理工程を実施する。このアニール処理工程は、１２００℃以上の温度であって、アンモニア雰囲気下、且つ、１０ｋＰａ未満の低い圧力で窒化物半導体層２０を加熱する加熱工程を有している。より具体的には、この加熱工程の温度が１２００～１５００℃である。 Next, as shown in FIG. 2E, an annealing treatment step is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20. This annealing treatment step includes a heating step of heating the nitride semiconductor layer 20 at a temperature of 1200 ° C. or higher, in an ammonia atmosphere, and at a low pressure of less than 10 kPa. More specifically, the temperature of this heating step is 1200 to 1500 ° C.
　図２Ｅに示されるように、このアニール処理工程が実施されると、アモルファスであったアニール用保護膜４２が結晶化する。このとき、アニール用保護膜４２の上面から下面まで貫く粒界が形成されることがある。このため、窒化物半導体層２０の上面からアニール用保護膜４２の粒界を介して窒素が抜けて、窒化物半導体層２０の上面にピットが形成される虞がある。しかしながら、図２Ｅに示されるように、このアニール処理工程中の加熱工程は、アンモニア雰囲気下で実施されるので、アニール炉内のアンモニアが熱分解され、アニール用保護膜４２の表面近傍に窒素と水素が生じる。熱分解で生じた窒素は、窒化物半導体層２０の上面からの窒素の抜けを補償するように、アニール用保護膜４２の粒界を介して窒化物半導体層２０の上面に供給される。これにより、窒化物半導体層２０の上面にピットが形成されるのを抑えることができる。アンモニアの熱分解で生じた水素は、軽い原子であることから、アニール炉から排出される。特に、このアニール処理工程中の加熱工程は、１０ｋＰａ未満の減圧下で実施されるので、アンモニアの熱分解で生じた水素が効率的にアニール炉から排出される。このため、熱分解で生じた水素がアニール用保護膜４２の粒界を介して窒化物半導体層２０の上面に供給される量が抑えられる。このように、減圧下で実施される加熱工程では、熱分解で生じた水素によって窒化物半導体層２０の上面にダメージが加えられることが抑えられる。 As shown in FIG. 2E, when this annealing treatment step is carried out, the amorphous protective film 42 for annealing crystallizes. At this time, grain boundaries may be formed that penetrate from the upper surface to the lower surface of the protective film 42 for annealing. Therefore, nitrogen may escape from the upper surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 42, and pits may be formed on the upper surface of the nitride semiconductor layer 20. However, as shown in FIG. 2E, since the heating step during this annealing treatment step is carried out in an ammonia atmosphere, the ammonia in the annealing furnace is thermally decomposed, and nitrogen is generated in the vicinity of the surface of the protective film 42 for annealing. Hydrogen is produced. Nitrogen generated by thermal decomposition is supplied to the upper surface of the nitride semiconductor layer 20 via the grain boundaries of the annealing protective film 42 so as to compensate for the escape of nitrogen from the upper surface of the nitride semiconductor layer 20. As a result, it is possible to prevent the formation of pits on the upper surface of the nitride semiconductor layer 20. Hydrogen generated by the thermal decomposition of ammonia is discharged from the annealing furnace because it is a light atom. In particular, since the heating step during this annealing treatment step is carried out under a reduced pressure of less than 10 kPa, hydrogen generated by the thermal decomposition of ammonia is efficiently discharged from the annealing furnace. Therefore, the amount of hydrogen generated by thermal decomposition is suppressed from being supplied to the upper surface of the nitride semiconductor layer 20 via the grain boundaries of the annealing protective film 42. As described above, in the heating step carried out under reduced pressure, it is possible to prevent the upper surface of the nitride semiconductor layer 20 from being damaged by hydrogen generated by thermal decomposition.
　ここで、図１０～図１２に、アンモニア雰囲気下、１４００℃の加熱工程を実施した後の窒化物半導体層２０の表面光学顕微鏡像を示す。図１０は６ｋＰａの圧力で加熱工程を実施した結果であり、図１１は１２ｋＰａの圧力で加熱工程を実施した結果であり、図１２は２０ｋＰａの圧力で加熱工程を実施した結果である。図１０～図１２に示すように、ピットの密度及び大きさは、加熱工程中の圧力に依存している。この結果から、アンモニア雰囲気の加熱工程では、加熱工程中の圧力を標準気圧未満において低下させることにより、窒化物半導体層２０の上面にピットが形成されるのを抑えることができる。加熱工程中の圧力は、２０ｋＰａ未満、１５ｋＰａ未満、１２ｋＰａ未満、１１ｋＰａ未満、１０ｋＰａ未満、９ｋＰａ未満、８ｋＰａ未満、７ｋＰａ未満又は６ｋＰａ未満としてもよい。加熱工程中の圧力を低下させるほど、ピットの密度をさらに低下させるとともに、ピットの大きさもさらに小さくすることができる。特に、加熱工程中の圧力が１０ｋＰａ未満であると、ピットの形成を顕著に抑えることができる。なお、このような結果は、加熱工程の温度が１４００℃の場合に限られず、加熱工程の温度が１２００～１５００℃においても同様である。 Here, FIGS. 10 to 12 show surface optical microscope images of the nitride semiconductor layer 20 after performing the heating step at 1400 ° C. in an ammonia atmosphere. FIG. 10 shows the result of carrying out the heating step at a pressure of 6 kPa, FIG. 11 shows the result of carrying out the heating step at a pressure of 12 kPa, and FIG. 12 shows the result of carrying out the heating step at a pressure of 20 kPa. As shown in FIGS. 10-12, the density and size of the pits depends on the pressure during the heating process. From this result, in the heating step of the ammonia atmosphere, the formation of pits on the upper surface of the nitride semiconductor layer 20 can be suppressed by lowering the pressure during the heating step below the standard atmospheric pressure. The pressure during the heating step may be less than 20 kPa, less than 15 kPa, less than 12 kPa, less than 11 kPa, less than 10 kPa, less than 9 kPa, less than 8 kPa, less than 7 kPa or less than 6 kPa. As the pressure during the heating process is reduced, the density of the pits can be further reduced and the size of the pits can be further reduced. In particular, when the pressure during the heating step is less than 10 kPa, the formation of pits can be remarkably suppressed. It should be noted that such a result is not limited to the case where the temperature of the heating step is 1400 ° C., and is the same when the temperature of the heating step is 1200 to 1500 ° C.
　なお、アンモニアの熱分解で生じた水素が窒化物半導体層２０の上面に供給される量が抑えられるものの、アンモニアの熱分解で生じた少なくとも一部の水素は、アニール用保護膜４２を介して窒化物半導体層２０内に導入される。窒化物半導体層２０内に導入された水素は、ｐ型ドーパントであるマグネシウムと結合することができる。水素が結合したマグネシウムは、Ｇａサイトに取り込められ易くなるという性質がある。このため、アンモニア雰囲気下で加熱工程を実施すると、マグネシウムを効率的にＧａサイトに取り込むことができる。なお、イオン注入工程において、マグネシウムと水素を共注入した場合には、アンモニアの熱分解で生じた水素が雰囲気中に存在するため、イオン注入した水素が脱離しにくくなる。水素が脱離しにくくなるため、水素が結合したマグネシウムがＧａサイトに取り込まれる前に水素が脱離してしまうことを抑制できる。これにより、マグネシウムをより効率的にＧａサイトに取り込むことができる。 Although the amount of hydrogen generated by the thermal decomposition of ammonia is suppressed from being supplied to the upper surface of the nitride semiconductor layer 20, at least a part of the hydrogen generated by the thermal decomposition of ammonia is passed through the protective film 42 for annealing. It is introduced into the nitride semiconductor layer 20. The hydrogen introduced into the nitride semiconductor layer 20 can be bonded to magnesium, which is a p-type dopant. Magnesium to which hydrogen is bound has the property of being easily taken up by Ga sites. Therefore, when the heating step is carried out in an ammonia atmosphere, magnesium can be efficiently incorporated into the Ga site. When magnesium and hydrogen are co-implanted in the ion implantation step, hydrogen generated by thermal decomposition of ammonia is present in the atmosphere, so that the ion-implanted hydrogen is difficult to be desorbed. Since hydrogen is less likely to be desorbed, it is possible to prevent hydrogen from being desorbed before the magnesium to which hydrogen is bound is incorporated into the Ga site. As a result, magnesium can be taken into the Ga site more efficiently.
　次に、図２Ｆに示されるように、アニール用保護膜４２を除去した後に、蒸着技術を利用して、窒化物半導体層２０の上面及び下面を被覆するように、脱水素用保護膜４４を成膜する。蒸着技術としては、ＣＶＤ法又はＰＶＤ法が用いられる。ＣＶＤ法としては、例えば原子層堆積法が用いられてもよい。脱水素用保護膜４４は、アニール用保護膜４２よりも水素透過性の高い材料であり、例えば酸化シリコン（ＳｉＯ2）である。次に、窒化物半導体層２０内の水素を除去するために、アニール処理を実施する。この脱水素のためのアニール処理では、温度が５００～１５００℃である。このアニール処理により、マグネシウムと結合していた水素が窒化物半導体層２０から除去され、ｐ型ドーパントであるマグネシウムが活性化する。なお、図２Ｅを参照して説明したアニール処理工程の条件を調整することにより、マグネシウムのＧａサイトへの取り込みとマグネシウムの活性化と水素の除去を１つのアニール処理で行うことができる。この場合、図２Ｆに示される脱水素工程を省略することができる。 Next, as shown in FIG. 2F, after removing the protective film 42 for annealing, the protective film 44 for dehydrogenation is applied so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using a vapor deposition technique. Form a film. As the vapor deposition technique, a CVD method or a PVD method is used. As the CVD method, for example, an atomic layer deposition method may be used. The dehydrogenation protective film 44 is a material having higher hydrogen permeability than the annealing protective film 42, and is, for example, silicon oxide (SiO 2 ). Next, an annealing treatment is performed in order to remove hydrogen in the nitride semiconductor layer 20. In this annealing treatment for dehydrogenation, the temperature is 500 to 1500 ° C. By this annealing treatment, hydrogen bonded to magnesium is removed from the nitride semiconductor layer 20, and magnesium, which is a p-type dopant, is activated. By adjusting the conditions of the annealing treatment step described with reference to FIG. 2E, uptake of magnesium into the Ga site, activation of magnesium, and removal of hydrogen can be performed by one annealing treatment. In this case, the dehydrogenation step shown in FIG. 2F can be omitted.
　次に、図２Ｇに示されるように、脱水素用保護膜４４を除去した後に、蒸着技術を利用して、窒化物半導体層２０の上面を被覆するようにゲート絶縁膜３６ａを成膜する。蒸着技術としては、原子層堆積法又はプラズマＣＶＤ法が利用される。次に、ポストアニール（Post Deposition Annealing: PDA）処理を実施してゲート絶縁膜３６ａの膜質を改善する。蒸着技術を利用して成膜されたゲート絶縁膜３６ａ内には、多くの水素が残存している。ゲート絶縁膜３６ａに残存する水素を取り除くには、１０００℃以上のアニール処理が望ましいとされているが、そのような高温のアニール処理では、窒化物半導体層２０のＧａＮ結晶の熱分解が生じ、ゲート絶縁膜３６ａ内にガリウム（Ｇａ）が拡散することが懸念される。さらに、上記した活性化のためのアニール処理工程以外の手法によりアニール処理工程を実施すると、窒化物半導体層２０の表面がＧａ過多となるため、ポストアニール処理において多量のＧａがゲート絶縁膜３６ａに拡散してしまう。ゲート絶縁膜３６ａ内にガリウム（Ｇａ）が拡散すると、ゲート閾値電圧の変動といった電気的特性の悪化が問題となる。このポストアニール処理の温度及び圧力は、窒化物半導体層２０を構成する窒化ガリウム（ＧａＮ）の状態図に基づいて、状態図の固相が維持される条件に設定されている。窒化ガリウム（ＧａＮ）の状態図の昇華圧曲線によれば、１０００℃の温度に関しては、１ＭＰａ以上の圧力で固相が維持される。したがって、このポストアニール処理の圧力は、１ＭＰａ以上に設定されている。より具体的には、ポストアニール処理の温度が５００～１５００℃であり、ポストアニール処理の圧力が１ＭＰａ～１ＧＰａである。これにより、窒化物半導体層２０の熱分解を抑えながら、ゲート絶縁膜３６ａの膜質を改善することができる。 Next, as shown in FIG. 2G, after removing the dehydrogenation protective film 44, a gate insulating film 36a is formed so as to cover the upper surface of the nitride semiconductor layer 20 by using a vapor deposition technique. As the vapor deposition technique, an atomic layer deposition method or a plasma CVD method is used. Next, a post-annealing (PDA) treatment is performed to improve the film quality of the gate insulating film 36a. A large amount of hydrogen remains in the gate insulating film 36a formed by using the vapor deposition technique. In order to remove the hydrogen remaining in the gate insulating film 36a, it is desirable to perform an annealing treatment at 1000 ° C. or higher. However, such a high-temperature annealing treatment causes thermal decomposition of the GaN crystal of the nitride semiconductor layer 20. There is concern that gallium (Ga) may diffuse into the gate insulating film 36a. Further, when the annealing step is carried out by a method other than the annealing step for activation described above, the surface of the nitride semiconductor layer 20 becomes excessive in Ga, so that a large amount of Ga is applied to the gate insulating film 36a in the post-annealing treatment. It will spread. When gallium (Ga) is diffused in the gate insulating film 36a, deterioration of electrical characteristics such as fluctuation of the gate threshold voltage becomes a problem. The temperature and pressure of this post-annealing process are set under conditions in which the solid phase of the phase diagram is maintained based on the phase diagram of gallium nitride (GaN) constituting the nitride semiconductor layer 20. According to the sublimation pressure curve of the gallium nitride (GaN) phase diagram, the solid phase is maintained at a pressure of 1 MPa or more at a temperature of 1000 ° C. Therefore, the pressure of this post-annealing process is set to 1 MPa or more. More specifically, the temperature of the post-annealing treatment is 500 to 1500 ° C., and the pressure of the post-annealing treatment is 1 MPa to 1 GPa. Thereby, the film quality of the gate insulating film 36a can be improved while suppressing the thermal decomposition of the nitride semiconductor layer 20.
　次に、図２Ｈに示されるように、蒸着技術を利用して、ゲート絶縁膜３６ａの表面上にゲート電極３６ｂを成膜する。さらに、エッチング技術を利用して、ゲート絶縁膜３６ａ及びゲート電極３６ｂを加工し、絶縁ゲート部３６を形成する。この後、既知の製造技術を利用して、ドレイン電極３２及びソース電極３４を形成することで、図１に示す窒化物半導体装置１を製造することができる。 Next, as shown in FIG. 2H, the gate electrode 36b is formed on the surface of the gate insulating film 36a by using the vapor deposition technique. Further, the gate insulating film 36a and the gate electrode 36b are processed by using the etching technique to form the insulated gate portion 36. After that, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured by forming the drain electrode 32 and the source electrode 34 by using a known manufacturing technique.
（窒化物半導体装置１の第２の製造方法）
　まず、ｐ型ドーパントのイオン注入工程まで、即ち、図２Ａ～図２Ｃまでの工程は、第１の製造方法と同一とすることができる。次に、図３に示されるように、蒸着技術を利用して、窒化物半導体層２０の上面、下面、及び、上面と下面の間の延びる側面を被覆するように、アモルファスのアニール用保護膜４６を成膜する。即ち、アニール用保護膜４６は、窒化物半導体層２０の表面全体を被覆するように成膜される。なお、図３では、デバイスの単位セルの側面にアニール用保護膜４６が成膜されるように図示されているが、実際はウェハの側面にアニール用保護膜４６が成膜されることに留意されたい。蒸着技術としては、ＣＶＤ法又はＰＶＤ法が用いられる。ＣＶＤ法としては、段差被膜性の高い方法が望ましく、例えば原子層堆積法が用いられてもよい。ＰＶＤ法が用いられる場合、段差被膜性を向上させるために、ターゲットカソードを窒化物半導体層２０に対して０°よりも大きい角度で傾けながら、成膜中の窒化物半導体層２０を所定速度で回転させてもよい。アニール用保護膜４６は、この後の活性化のためのアニール処理において結晶化する材料であり、例えば窒化アルミニウム（ＡｌＮ）である。この例に代えてアニール用保護膜４６は、、窒化アルミニウムガリウム（ＡｌＧａＮ）、酸化アルミニウム（Ａｌ2Ｏ3）、酸化亜鉛（ＺｎＯ）又は酸化シリコン（ＳｉＯ2）であってもよい。 (Second Manufacturing Method of Nitride Semiconductor Device 1)
First, the steps up to the ion implantation step of the p-type dopant, that is, the steps from FIGS. 2A to 2C can be the same as the first manufacturing method. Next, as shown in FIG. 3, an amorphous protective film for annealing is used to cover the upper surface and the lower surface of the nitride semiconductor layer 20 and the extending side surface between the upper surface and the lower surface by using a vapor deposition technique. 46 is formed into a film. That is, the annealing protective film 46 is formed so as to cover the entire surface of the nitride semiconductor layer 20. Although it is shown in FIG. 3 that the protective film 46 for annealing is formed on the side surface of the unit cell of the device, it should be noted that the protective film 46 for annealing is actually formed on the side surface of the wafer. sea bream. As the vapor deposition technique, a CVD method or a PVD method is used. As the CVD method, a method having a high step coating property is desirable, and for example, an atomic layer deposition method may be used. When the PVD method is used, in order to improve the step coating property, the nitride semiconductor layer 20 being formed is tilted at a predetermined speed while tilting the target cathode at an angle larger than 0 ° with respect to the nitride semiconductor layer 20. You may rotate it. The protective film 46 for annealing is a material that crystallizes in the subsequent annealing treatment for activation, and is, for example, aluminum nitride (AlN). Instead of this example, the protective film 46 for annealing may be aluminum gallium nitride (AlGaN), aluminum oxide (Al 2 O 3 ), zinc oxide (Zn O), or silicon oxide (SiO 2 ).
　次に、窒化物半導体層２０内のｎ型ドーパント及びｐ型ドーパントを活性化させるために、アニール処理を実施する。このアニール処理の温度は、１２００℃以上である。より具体的には、アニール処理の温度が１２００～１５００℃である。なお、アニール処理の雰囲気ガス及び圧力は、特に限定されるものではない。例えば、このアニール処理工程は、第１の製造方法のアニール処理工程と同一としてもよい。第１の製造方法のアニール処理工程を採用した場合、１０ｋＰａ未満の減圧下のアニール処理工程が実施される。このような１０ｋＰａ未満の減圧下のアニール処理工程では、１０ｋＰａ以上の圧力下よりも窒化物半導体層２０は熱分解しやすくなる。したがって、第１の製造方法のアニール処理工程を採用した場合、窒化物半導体層２０の側面にもアニール用保護膜４６を成膜することにより、窒化物半導体層２０の上面及び下面だけでなく、側面の熱分解も抑制できる。このように、窒化物半導体層２０の側面にもアニール用保護膜４６を成膜する技術は、第１の製造方法のアニール処理工程を採用した場合に特に有用である。 Next, an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20. The temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C. The atmospheric gas and pressure of the annealing treatment are not particularly limited. For example, this annealing treatment step may be the same as the annealing treatment step of the first manufacturing method. When the annealing step of the first production method is adopted, the annealing step under reduced pressure of less than 10 kPa is carried out. In such an annealing process under a reduced pressure of less than 10 kPa, the nitride semiconductor layer 20 is more easily thermally decomposed than under a pressure of 10 kPa or more. Therefore, when the annealing step of the first manufacturing method is adopted, by forming the protective film 46 for annealing on the side surface of the nitride semiconductor layer 20, not only the upper surface and the lower surface of the nitride semiconductor layer 20 but also the lower surface thereof are formed. Thermal decomposition of the side surface can also be suppressed. As described above, the technique of forming the protective film 46 for annealing on the side surface of the nitride semiconductor layer 20 is particularly useful when the annealing step of the first manufacturing method is adopted.
　また、このアニール処理では、窒化物半導体層２０の側面にもアニール用保護膜４６が成膜されている。このため、窒化物半導体層２０の側面におけるＧａＮ結晶の分解を抑えることができるので、素子の有効面積を大きく確保することができる。 Further, in this annealing treatment, a protective film 46 for annealing is also formed on the side surface of the nitride semiconductor layer 20. Therefore, the decomposition of the GaN crystal on the side surface of the nitride semiconductor layer 20 can be suppressed, so that a large effective area of the device can be secured.
　これ以降の工程は、第１の製造方法と同一とすることができる。これにより、図１に示す窒化物半導体装置１を製造することができる。 The subsequent steps can be the same as the first manufacturing method. As a result, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
（窒化物半導体装置１の第３の製造方法）
　まず、ｐ型ドーパントのイオン注入工程まで、即ち、図２Ａ～図２Ｃまでの工程は、第１の製造方法と同一とすることができる。次に、図４Ａに示されるように、蒸着技術を利用して、窒化物半導体層２０の上面及び下面を被覆するように、アモルファスの窒化アルミニウム膜４８ａを成膜する。蒸着技術としては、ＣＶＤ法又はＰＶＤ法が用いられる。ＣＶＤ法としては、例えば原子層堆積法が用いられてもよい。 (Third manufacturing method of nitride semiconductor device 1)
First, the steps up to the ion implantation step of the p-type dopant, that is, the steps from FIGS. 2A to 2C can be the same as the first manufacturing method. Next, as shown in FIG. 4A, an amorphous aluminum nitride film 48a is formed so as to cover the upper surface and the lower surface of the nitride semiconductor layer 20 by using the vapor deposition technique. As the vapor deposition technique, a CVD method or a PVD method is used. As the CVD method, for example, an atomic layer deposition method may be used.
　次に、図４Ｂに示されるように、窒化アルミニウム膜４８ａの表面上に酸化アルミニウム（Ａｌ2Ｏ3）の酸化膜４８ｂを成膜する。この例では、窒化アルミニウム膜４８ａと酸化膜４８ｂの積層膜がアニール用保護膜４８となる。酸化膜４８ｂは、窒化物半導体層２０の上面と下面の各々に窒化アルミニウム膜４８ａを成膜した後に、酸素雰囲気下で熱処理を行うことで成膜してもよく、酸素プラズマ照射を行うことで成膜してもよい。この例に代えて、ＣＶＤ法によって窒化物半導体層２０の上面に窒化アルミニウム膜４８ａを成膜した後に、窒化アルミニウムの成膜原料に酸化ガスを付加して酸窒化アルミニウム（ＡｌＯＮ）の酸化膜４８ｂを成膜してもよい。同様に、窒化物半導体層２０の下面にもＣＶＤ法によって窒化アルミニウム膜４８ａと酸窒化アルミニウム（ＡｌＯＮ）の酸化膜４８ｂを成膜してもよい。窒化アルミニウム膜４８ａと酸化膜４８ｂの各々の厚みは、１０００ｎｍ以下である。なお、アニール用保護膜４８は、窒化物半導体層２０の側面にも成膜されてもよい。 Next, as shown in FIG. 4B, an oxide film 48b of aluminum oxide (Al 2 O 3 ) is formed on the surface of the aluminum nitride film 48a. In this example, the laminated film of the aluminum nitride film 48a and the oxide film 48b serves as the protective film 48 for annealing. The oxide film 48b may be formed by forming an aluminum nitride film 48a on each of the upper surface and the lower surface of the nitride semiconductor layer 20 and then performing heat treatment in an oxygen atmosphere, or by performing oxygen plasma irradiation. A film may be formed. Instead of this example, after forming an aluminum nitride film 48a on the upper surface of the nitride semiconductor layer 20 by a CVD method, an oxide gas is added to the film forming raw material of aluminum nitride to form an oxide film 48b of aluminum nitride (AlON). May be formed. Similarly, the aluminum nitride film 48a and the aluminum nitride (AlON) oxide film 48b may be formed on the lower surface of the nitride semiconductor layer 20 by the CVD method. The thickness of each of the aluminum nitride film 48a and the oxide film 48b is 1000 nm or less. The annealing protective film 48 may also be formed on the side surface of the nitride semiconductor layer 20.
　次に、窒化物半導体層２０内のｎ型ドーパント及びｐ型ドーパントを活性化させるために、アニール処理を実施する。このアニール処理の温度は、１２００℃以上である。より具体的には、アニール処理の温度が１２００～１５００℃である。なお、アニール処理の雰囲気ガス及び圧力は、特に限定されるものではない。例えば、このアニール処理工程は、第１の製造方法のアニール処理工程と同一としてもよい。酸化膜４８ｂの形成により、アンモニアが熱分解して生じた水素が窒化物半導体層２０内に供給される量をさらに抑えることができる。これにより、水素によって窒化物半導体層２０の表面にダメージが加えられることをより抑えることができる。このように、酸化膜４８ｂを形成する技術は、第１の製造方法のアニール処理工程を採用した場合に特に有用である。 Next, an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20. The temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C. The atmospheric gas and pressure of the annealing treatment are not particularly limited. For example, this annealing treatment step may be the same as the annealing treatment step of the first manufacturing method. By forming the oxide film 48b, the amount of hydrogen generated by the thermal decomposition of ammonia can be further suppressed in the nitride semiconductor layer 20. As a result, it is possible to further prevent the surface of the nitride semiconductor layer 20 from being damaged by hydrogen. As described above, the technique for forming the oxide film 48b is particularly useful when the annealing treatment step of the first production method is adopted.
　酸化膜４８ｂは、１３００℃以上のアニール処理においても結晶化が抑制される。このため、窒化アルミニウム膜４８ａと酸化膜４８ｂの双方、即ち、アニール用保護膜４８の上面から下面まで貫く粒界が形成されることが抑制される。このため、窒化物半導体層２０の表面からアニール用保護膜４８の粒界を介して窒素が抜けて、窒化物半導体層２０の表面にピットが形成されるのを抑えることができる。 Crystallization of the oxide film 48b is suppressed even in the annealing treatment at 1300 ° C. or higher. Therefore, it is suppressed that both the aluminum nitride film 48a and the oxide film 48b, that is, the grain boundaries penetrating from the upper surface to the lower surface of the protective film 48 for annealing are formed. Therefore, it is possible to prevent nitrogen from escaping from the surface of the nitride semiconductor layer 20 through the grain boundaries of the annealing protective film 48 and forming pits on the surface of the nitride semiconductor layer 20.
　これ以降の工程は、第１の製造方法と同一とすることができる。これにより、図１に示す窒化物半導体装置１を製造することができる。 The subsequent steps can be the same as the first manufacturing method. As a result, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
（窒化物半導体装置１の第４の製造方法）
　まず、ｐ型ドーパントのイオン注入工程まで、即ち、図２Ａ～図２Ｃまでの工程は、第１の製造方法と同一とすることができる。次に、第１の製造方法のアニール用保護膜４２、第２の製造方法のアニール用保護膜４６又は第３の製造方法のアニール用保護膜４８のいずれかを適用し、窒化物半導体層２０の表面上にアニール用保護膜を成膜する。 (Fourth Manufacturing Method of Nitride Semiconductor Device 1)
First, the steps up to the ion implantation step of the p-type dopant, that is, the steps from FIGS. 2A to 2C can be the same as the first manufacturing method. Next, either the annealing protective film 42 of the first manufacturing method, the annealing protective film 46 of the second manufacturing method, or the annealing protective film 48 of the third manufacturing method is applied, and the nitride semiconductor layer 20 is applied. A protective film for annealing is formed on the surface of the above.
　次に、窒化物半導体層２０内のｎ型ドーパント及びｐ型ドーパントを活性化させるために、アニール処理工程を実施する。図５に、アニール処理工程における窒化物半導体層２０の温度の時間変化を示す。アニール処理工程は、時間ｔ０から時間ｔ２まで窒化物半導体層２０の温度を上昇させる昇温工程と、時間ｔ２から時間ｔ３まで窒化物半導体層２０を温度Ｔ２で加熱する加熱工程と、を有している。加熱工程の温度Ｔ２は１２００℃以上である。より具体的には、加熱工程の温度Ｔ２は１２００～１５００℃である。なお、加熱工程の雰囲気ガス及び圧力は、特に限定されるものではない。例えば、この加熱工程は、第１の製造方法のアニール処理工程の加熱工程と同一とすることができる。 Next, an annealing treatment step is carried out in order to activate the n-type dopant and the p-type dopant in the nitride semiconductor layer 20. FIG. 5 shows the time change of the temperature of the nitride semiconductor layer 20 in the annealing process. The annealing process includes a temperature raising step of raising the temperature of the nitride semiconductor layer 20 from time t 0 to time t 2 and a heating step of heating the nitride semiconductor layer 20 at temperature T 2 from time t 2 to time t 3. And have. The temperature T 2 in the heating step is 1200 ° C. or higher. More specifically, the temperature T 2 in the heating step is 1200 to 1500 ° C. The atmospheric gas and pressure in the heating step are not particularly limited. For example, this heating step can be the same as the heating step of the annealing step of the first manufacturing method.
　昇温工程では、時間ｔ０から窒化物半導体層２０の温度上昇が開始し、時間ｔ１において窒化物半導体層２０の温度が１２００℃に達する（なお、加熱温度Ｔ２が１２００℃の場合、時間ｔ１と時間ｔ２は同一である）。昇温工程では、時間ｔ０から時間ｔ２までの昇温レートが１～１００℃／ｍｉｎである。また、時間ｔ０のアニール炉内の初期圧力が５０Ｍｐａ以上である。 In the temperature raising step, the temperature of the nitride semiconductor layer 20 starts to rise from time t 0, and the temperature of the nitride semiconductor layer 20 reaches 1200 ° C. at time t 1 (when the heating temperature T 2 is 1200 ° C., Time t 1 and time t 2 are the same). In the temperature raising step, the temperature rising rate from time t 0 to time t 2 is 1 to 100 ° C./min. Further, the initial pressure in the annealing furnace at time t 0 is 50 Mpa or more.
　アニール処理工程に先立って窒化物半導体層２０の表面に成膜されるアニール用保護膜（第１～第３の製造方法のアニール用保護膜４２、４６、４８）は、アモルファスの状態で成膜される。このアニール用保護膜は、温度が上昇すると結晶化するものであり、窒化物半導体層２０の温度が少なくとも１２００℃に達する時間ｔ１までに結晶化している。したがって、時間ｔ０から時間ｔ１までのアニール用保護膜は、アモルファスの状態である可能性があり、窒化物半導体層２０の上面からの窒素が抜けやすい状態である。 The protective film for annealing ( protective films 42, 46, 48 for annealing in the first to third manufacturing methods) formed on the surface of the nitride semiconductor layer 20 prior to the annealing treatment step is formed in an amorphous state. Will be done. This protective film for annealing crystallizes when the temperature rises, and is crystallized by the time t 1 when the temperature of the nitride semiconductor layer 20 reaches at least 1200 ° C. Therefore, the protective film for annealing from time t 0 to time t 1 may be in an amorphous state, and nitrogen is easily released from the upper surface of the nitride semiconductor layer 20.
　窒化物半導体層２０を構成する窒化ガリウム（ＧａＮ）の状態図の昇華圧曲線によれば、１２００℃の温度に関しては、５０ＭＰａ以上の圧力で固相である。上記の昇温工程では、時間ｔ０のアニール炉内の初期圧力が５０Ｍｐａ以上に設定されているので、時間ｔ０から時間ｔ１までのアニール炉内の圧力が５０Ｍｐａ以上となるように維持される。これにより、時間ｔ０から時間ｔ１までの間において、窒化物半導体層２０の熱分解を抑えることができるので、窒化物半導体層２０の上面からの窒素の抜けを抑えることができる。 According to the sublimation pressure curve of the phase diagram of gallium nitride (GaN) constituting the nitride semiconductor layer 20, the solid phase is at a pressure of 50 MPa or more at a temperature of 1200 ° C. In the above heating step, since the initial pressure in the annealing furnace at time t 0 is set to 50 Mpa or more, the pressure in the annealing furnace from time t 0 to time t 1 is maintained to be 50 Mpa or more. NS. As a result, the thermal decomposition of the nitride semiconductor layer 20 can be suppressed between the time t 0 and the time t 1, so that the escape of nitrogen from the upper surface of the nitride semiconductor layer 20 can be suppressed.
　これ以降の工程は、第１の製造方法と同一とすることができる。これにより、図１に示す窒化物半導体装置１を製造することができる。 The subsequent steps can be the same as the first manufacturing method. As a result, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
（窒化物半導体装置１の第５の製造方法）
　まず、ｎ型ドーパントのイオン注入工程まで、即ち、図２Ａ～図２Ｂまでの工程は、第１の製造方法と同一とすることができる。次に、図６に示されるフローに沿って、ｐ型ドーパントであるマグネシウムが窒化物半導体層２０にイオン注入される。 (Fifth Manufacturing Method of Nitride Semiconductor Device 1)
First, the steps up to the ion implantation step of the n-type dopant, that is, the steps from FIGS. 2A to 2B can be the same as the first manufacturing method. Next, magnesium, which is a p-type dopant, is ion-implanted into the nitride semiconductor layer 20 along the flow shown in FIG.
　まず、ステップＳ１では、イオン注入技術を利用して、窒化物半導体層２０にｐ型ドーパントとしてマグネシウムをイオン注入する。イオン注入されるマグネシウム量は、ボディ領域２４及びボディコンタクト領域２６を形成するために最終的に必要とされる量よりも少ない。このとき、マグネシウムの注入範囲に水素もイオン注入してもよい。 First, in step S1, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using the ion implantation technique. The amount of magnesium ion-implanted is less than the amount ultimately required to form the body region 24 and the body contact region 26. At this time, hydrogen may also be ion-implanted into the magnesium injection range.
　次に、ステップＳ２では、先のイオン注入で形成された結晶欠陥を回復させるために、アニール処理を実施する。このアニール処理の温度は、１２００℃未満である。より具体的には、このアニール処理では、温度は５００～１０００℃である。なお、アニール処理の雰囲気ガス及び圧力は、特に限定されるものではない。 Next, in step S2, an annealing treatment is performed in order to recover the crystal defects formed by the previous ion implantation. The temperature of this annealing treatment is less than 1200 ° C. More specifically, in this annealing treatment, the temperature is 500 to 1000 ° C. The atmospheric gas and pressure of the annealing treatment are not particularly limited.
　次に、ステップＳ３では、イオン注入とアニール処理を組み合わせた工程の処理回数が所定回数に達したか否かが判定される。処理回数が所定回数に達していないときは、ステップＳ１に戻る。処理回数が所定回数に達したとき、即ち、イオン注入されるマグネシウム量がボディ領域２４及びボディコンタクト領域２６を形成するために最終的に必要とされる量を超えたときには、ステップＳ４に進む。 Next, in step S3, it is determined whether or not the number of treatments in the process combining the ion implantation and the annealing treatment has reached a predetermined number of times. If the number of processes has not reached the predetermined number, the process returns to step S1. When the number of treatments reaches a predetermined number, that is, when the amount of magnesium ion-implanted exceeds the amount finally required to form the body region 24 and the body contact region 26, the process proceeds to step S4.
　次に、ステップＳ４では、窒化物半導体層２０の表面上にアニール用保護膜を成膜する。アニール用保護膜は、第１の製造方法のアニール用保護膜４２、第２の製造方法のアニール用保護膜４６又は第３の製造方法のアニール用保護膜４８のいずれを適用してもよい。 Next, in step S4, a protective film for annealing is formed on the surface of the nitride semiconductor layer 20. As the protective film for annealing, any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
　次に、ステップＳ５では、窒化物半導体層２０のｎ型ドーパント及びｐ型ドーパントを活性化させるために、アニール処理工程を実施する。例えば、このアニール処理工程は、第１～第４の製造方法のいずれかのアニール処理工程と同一とすることができる。 Next, in step S5, an annealing treatment step is carried out in order to activate the n-type dopant and the p-type dopant of the nitride semiconductor layer 20. For example, this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods.
　窒化物半導体層２０にドーパントをイオン注入すると、窒化物半導体層２０に空孔が形成される。このような空孔型欠陥が存在する窒化物半導体層２０に対して、ドーパントを活性化させるための高温（１２００℃以上）のアニール処理を行うと、空孔型欠陥が凝集し、ドナー型欠陥が形成される。この結果、ｐ型ドーパントの活性化率が低下し、高活性なｐ型領域を形成することが困難となる。 When a dopant is ion-implanted into the nitride semiconductor layer 20, pores are formed in the nitride semiconductor layer 20. When the nitride semiconductor layer 20 in which such pore-type defects are present is subjected to a high-temperature (1200 ° C. or higher) annealing treatment for activating the dopant, the pore-type defects are aggregated and the donor-type defects are aggregated. Is formed. As a result, the activation rate of the p-type dopant decreases, and it becomes difficult to form a highly active p-type region.
　上記の製造方法では、イオン注入と低温（１２００℃未満）のアニール処理を組み合わせた工程の複数回が実施される。イオン注入を複数回に分けることで、イオン注入毎に形成される空孔量を抑えることができる。さらに、イオン注入毎に低温（１２００℃未満）のアニール処理を実施することにより、窒化物半導体層２０内の空孔型欠陥の密度を低下させることができる。したがって、活性化のための高温（１２００℃以上）のアニール処理を実施するときには、窒化物半導体層２０内の空孔型欠陥の密度が十分に低いことから、空孔型欠陥の凝集が抑制される。この結果、ドナー型欠陥の少ない状態でｐ型ドーパントが活性化させることができるので、ｐ型ドーパントの活性化率を高くすることができ、高活性なｐ型領域を形成することができる。 In the above manufacturing method, a plurality of steps of combining ion implantation and low temperature (less than 1200 ° C.) annealing treatment are performed. By dividing the ion implantation into a plurality of times, the amount of pores formed for each ion implantation can be suppressed. Further, by performing an annealing treatment at a low temperature (less than 1200 ° C.) for each ion implantation, the density of pore-shaped defects in the nitride semiconductor layer 20 can be reduced. Therefore, when the annealing treatment at a high temperature (1200 ° C. or higher) for activation is performed, the density of the pore-type defects in the nitride semiconductor layer 20 is sufficiently low, so that the aggregation of the pore-type defects is suppressed. NS. As a result, since the p-type dopant can be activated with few donor-type defects, the activation rate of the p-type dopant can be increased, and a highly active p-type region can be formed.
　これ以降の工程は、第１の製造方法と同一とすることができる。これにより、図１に示す窒化物半導体装置１を製造することができる。 The subsequent steps can be the same as the first manufacturing method. As a result, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
　なお、上記のイオン注入工程において、ステップＳ１とステップＳ２の間に、ステップＳ４のアニール用保護膜の成膜を行ってもよい。この場合、ステップＳ３の判定結果がＮＯのときは、アニール用保護膜を除去した後にステップＳ１に戻る。 In the above ion implantation step, a protective film for annealing in step S4 may be formed between steps S1 and S2. In this case, if the determination result in step S3 is NO, the process returns to step S1 after removing the protective film for annealing.
（窒化物半導体装置１の第６の製造方法）
　まず、図７Ａに示されるように、エピタキシャル成長技術を利用して、ＧａＮ基板であるドレイン領域２１の表面からｎ型ＧａＮのドリフト領域２２をエピタキシャル成長させ、窒化物半導体層２０を形成する。 (Sixth Manufacturing Method of Nitride Semiconductor Device 1)
First, as shown in FIG. 7A, an n-type GaN drift region 22 is epitaxially grown from the surface of a drain region 21 which is a GaN substrate to form a nitride semiconductor layer 20 by using an epitaxial growth technique.
　次に、図７Ｂに示されるように、イオン注入技術を利用して、窒化物半導体層２０にｐ型ドーパントとしてマグネシウムをイオン注入し、高濃度ボディ領域２４ａを形成する。高濃度ボディ領域２４ａに含まれるマグネシウムの表面濃度は、１×１０18ｃｍ-3以上である。このとき、マグネシウムの注入範囲に水素もイオン注入してもよい。 Next, as shown in FIG. 7B, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant by using an ion implantation technique to form a high-concentration body region 24a. The surface concentration of magnesium contained in the high-concentration body region 24a is 1 × 10 18 cm -3 or more. At this time, hydrogen may also be ion-implanted into the magnesium injection range.
　次に、図７Ｃに示されるように、エピタキシャル成長技術を利用して、ドリフト領域２２の表面からｎ型ＧａＮをエピタキシャル成長させる。このエピタキシャル再成長では、高濃度ボディ領域２４ａに含まれていたマグネシウムがエピタキシャル成長層へと拡散することにより、低濃度ボディ領域２４ｂが形成される。また、エピタキシャル再成長工程で用いられる材料由来の水素が、高濃度ボディ領域２４ａ及び低濃度ボディ領域２４ｂに取り込まれる。 Next, as shown in FIG. 7C, n-type GaN is epitaxially grown from the surface of the drift region 22 by using the epitaxial growth technique. In this epitaxial regrowth, the magnesium contained in the high-concentration body region 24a diffuses into the epitaxial growth layer, so that the low-concentration body region 24b is formed. Further, hydrogen derived from the material used in the epitaxial regrowth step is incorporated into the high-concentration body region 24a and the low-concentration body region 24b.
　次に、図７Ｄに示されるように、イオン注入技術を利用して、窒化物半導体層２０にｎ型ドーパントとしてシリコン又はゲルマニウムをイオン注入し、ソース領域２５を形成する。さらに、イオン注入技術を利用して、窒化物半導体層２０にｐ型ドーパントとしてマグネシウムをイオン注入し、ボディコンタクト領域２６を形成する。 Next, as shown in FIG. 7D, silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 25. Further, using the ion implantation technique, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant to form the body contact region 26.
　次に、窒化物半導体層２０の表面上にアニール用保護膜を成膜する。アニール用保護膜は、第１の製造方法のアニール用保護膜４２、第２の製造方法のアニール用保護膜４６又は第３の製造方法のアニール用保護膜４８のいずれを適用してもよい。 Next, a protective film for annealing is formed on the surface of the nitride semiconductor layer 20. As the protective film for annealing, any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
　次に、ｎ型ドーパント及びｐ型ドーパントを活性化させるために、アニール処理を実施する。このアニール処理の温度は、１２００℃以上である。より具体的には、アニール処理の温度が１２００～１５００℃である。なお、アニール処理の雰囲気ガス及び圧力は、特に限定されるものではない。例えば、このアニール処理工程は、第１～第４の製造方法のいずれかのアニール処理工程と同一とすることができる。 Next, an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant. The temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C. The atmospheric gas and pressure of the annealing treatment are not particularly limited. For example, this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods.
　上記したように、この製造方法では、エピタキシャル再成長のときに、材料由来の水素が高濃度ボディ領域２４ａ及び低濃度ボディ領域２４ｂに取り込まれる。このため、アニール処理工程を実施すると、高濃度ボディ領域２４ａ及び低濃度ボディ領域２４ｂに取り込まれた水素は、ｐ型ドーパントであるマグネシウムと結合することができる。水素が結合したマグネシウムは、Ｇａサイトに取り込められ易くなるという性質がある。このため、アニール処理工程を実施すると、マグネシウムを効率的にＧａサイトに取り込むことができる。この結果、ｐ型ドーパントの活性化率を高くすることができるので、高活性なｐ型領域を形成することができる。例えば、ｐ型ドーパントを活性化させるためのアニール処理工程に第１の製造方法を採用した場合、イオン注入したｐ型ドーパントのドーズ量が多いと、アンモニアの分解により生じた一部の水素では、窒化物半導体層２０に導入される水素量が不十分な場合がある。上記のエピタキシャル成長技術を利用した製造方法を実施することにより、アニール処理工程の前に窒化物半導体層２０内に水素が取り込まれるため、高活性なｐ型領域を形成することができる。このように、エピタキシャル成長技術を利用する技術は、第１の製造方法のアニール処理工程と組み合わせることにより、高活性なｐ型領域を効果的に形成することができる。 As described above, in this production method, hydrogen derived from the material is incorporated into the high-concentration body region 24a and the low-concentration body region 24b at the time of epitaxial regrowth. Therefore, when the annealing treatment step is carried out, the hydrogen incorporated in the high-concentration body region 24a and the low-concentration body region 24b can be bonded to magnesium which is a p-type dopant. Magnesium to which hydrogen is bound has the property of being easily taken up by Ga sites. Therefore, when the annealing treatment step is carried out, magnesium can be efficiently incorporated into the Ga site. As a result, the activation rate of the p-type dopant can be increased, so that a highly active p-type region can be formed. For example, when the first production method is adopted in the annealing process for activating the p-type dopant, if the amount of ion-implanted p-type dopant is large, some hydrogen generated by the decomposition of ammonia may be used. The amount of hydrogen introduced into the nitride semiconductor layer 20 may be insufficient. By carrying out the manufacturing method using the above epitaxial growth technique, hydrogen is incorporated into the nitride semiconductor layer 20 before the annealing treatment step, so that a highly active p-type region can be formed. As described above, the technique utilizing the epitaxial growth technique can effectively form a highly active p-type region by combining with the annealing step of the first production method.
　これ以降の工程は、第１の製造方法と同一とすることができる。これにより、図１に示す窒化物半導体装置１を製造することができる。 The subsequent steps can be the same as the first manufacturing method. As a result, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.
（第２実施形態の窒化物半導体装置２）
　図８に、窒化物半導体装置２の要部断面図を示す。窒化物半導体装置２は、窒化物半導体層１２０、窒化物半導体層１２０の下面を被覆するように設けられているドレイン電極１３２、窒化物半導体層１２０の上面を被覆するように設けられているソース電極１３４、及び、窒化物半導体層１２０の上面の一部に形成されたトレンチ内に設けられているトレンチ型の絶縁ゲート部１３６を備えている。窒化物半導体層１２０は、ｎ型のドレイン領域１２１、ｎ型のドリフト領域１２２、ｐ型のボディ領域１２４、ｎ型のソース領域１２５、及び、ｐ型のボディコンタクト領域１２６を有している。 (Nitride semiconductor device 2 of the second embodiment)
FIG. 8 shows a cross-sectional view of a main part of the nitride semiconductor device 2. The nitride semiconductor device 2 includes a nitride semiconductor layer 120, a drain electrode 132 provided so as to cover the lower surface of the nitride semiconductor layer 120, and a source provided so as to cover the upper surface of the nitride semiconductor layer 120. It includes an electrode 134 and a trench-type insulating gate portion 136 provided in a trench formed in a part of the upper surface of the nitride semiconductor layer 120. The nitride semiconductor layer 120 has an n-type drain region 121, an n-type drift region 122, a p-type body region 124, an n-type source region 125, and a p-type body contact region 126.
　ドレイン領域１２１は、窒化物半導体層１２０の下面に露出する位置に設けられており、ドレイン電極１３２にオーミック接触している。ドレイン領域１２１は、ｎ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。 The drain region 121 is provided at a position exposed on the lower surface of the nitride semiconductor layer 120, and is in ohmic contact with the drain electrode 132. The drain region 121 is made of gallium nitride (GaN) containing n-type impurities.
　ドリフト領域１２２は、ドレイン領域１２１上に設けられており、ドレイン領域１２１とボディ領域１２４の間に配置されている。ドリフト領域１２２は、ｎ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。 The drift area 122 is provided on the drain area 121, and is arranged between the drain area 121 and the body area 124. The drift region 122 is made of gallium nitride (GaN) containing n-type impurities.
　ボディ領域１２４は、ドリフト領域１２２上に設けられており、高濃度ボディ領域１２４ａ及び低濃度ボディ領域１２４ｂを有している。ボディ領域１２４は、ｐ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。 The body region 124 is provided on the drift region 122, and has a high-concentration body region 124a and a low-concentration body region 124b. The body region 124 is made of gallium nitride (GaN) containing p-type impurities.
　高濃度ボディ領域１２４ａは、ドリフト領域１２２と低濃度ボディ領域１２４ｂの間に配置されているとともに、絶縁ゲート部１３６の側面から離反して設けられている。高濃度ボディ領域１２４ａは、低濃度ボディ領域１２４ｂよりもｐ型不純物を高濃度に含んでおり、オフのときに絶縁ゲート部１３６の底面角部の電界を緩和するために設けられている。 The high-concentration body region 124a is arranged between the drift region 122 and the low-concentration body region 124b, and is provided away from the side surface of the insulated gate portion 136. The high-concentration body region 124a contains p-type impurities at a higher concentration than the low-concentration body region 124b, and is provided to relax the electric field at the bottom corner of the insulating gate portion 136 when it is off.
　低濃度ボディ領域１２４ｂは、高濃度ボディ領域１２４ａ上に設けられており、窒化物半導体層１２０の上面に露出する位置に設けられており、絶縁ゲート部１３６の側面に接している。低濃度ボディ領域１２４ｂの不純物濃度は、所望のゲート閾値電圧となるように調整されている。絶縁ゲート部１３６の側面に接する位置にあるとともにドリフト領域１２２とソース領域１２５の間に位置する低濃度ボディ領域１２４ｂの一部を特にチャネル領域ＣＨという。 The low-concentration body region 124b is provided on the high-concentration body region 124a, is provided at a position exposed on the upper surface of the nitride semiconductor layer 120, and is in contact with the side surface of the insulating gate portion 136. The impurity concentration in the low concentration body region 124b is adjusted to a desired gate threshold voltage. A part of the low-concentration body region 124b located in contact with the side surface of the insulated gate portion 136 and between the drift region 122 and the source region 125 is particularly referred to as a channel region CH.
　ソース領域１２５は、低濃度ボディ領域１２４ｂ上に設けられており、窒化物半導体層１２０の上面に露出する位置に設けられており、低濃度ボディ領域１２４ｂによってドリフト領域１２２から隔てられている。ソース領域１２５は、ｎ型不純物を含む窒化ガリウム（ＧａＮ）を材料としている。ソース領域１２５は、ソース電極１３４にオーミック接触している。 The source region 125 is provided on the low-concentration body region 124b, is provided at a position exposed on the upper surface of the nitride semiconductor layer 120, and is separated from the drift region 122 by the low-concentration body region 124b. The source region 125 is made of gallium nitride (GaN) containing n-type impurities. The source region 125 is in ohmic contact with the source electrode 134.
　ボディコンタクト領域１２６は、低濃度ボディ領域１２４ｂ上に配置されており、窒化物半導体層１２０の上面に露出する位置に設けられている。ボディコンタクト領域１２６は、ｐ型不純物を含む窒化ガリウム（ＧａＮ）を材料とする。ボディコンタクト領域１２６は、ソース電極１３４にオーミック接触している。 The body contact region 126 is arranged on the low-concentration body region 124b, and is provided at a position exposed on the upper surface of the nitride semiconductor layer 120. The body contact region 126 is made of gallium nitride (GaN) containing p-type impurities. The body contact region 126 is in ohmic contact with the source electrode 134.
　絶縁ゲート部１３６は、窒化物半導体層１２０の上面の一部に形成されたトレンチ内に設けられており、酸化シリコンのゲート絶縁膜１３６ａ及びポリシリコンのゲート電極１３６ｂを有する。ゲート電極１３６ｂは、ドリフト領域１２２とソース領域１２５を隔てる部分の低濃度ボディ領域１２４ｂのチャネル領域ＣＨにゲート絶縁膜１３６ａを介して対向している。 The insulated gate portion 136 is provided in a trench formed in a part of the upper surface of the nitride semiconductor layer 120, and has a silicon oxide gate insulating film 136a and a polysilicon gate electrode 136b. The gate electrode 136b faces the channel region CH of the low-concentration body region 124b of the portion separating the drift region 122 and the source region 125 via the gate insulating film 136a.
　次に、窒化物半導体装置２の動作を説明する。使用時には、ドレイン電極１３２に正電圧が印加され、ソース電極１３４が接地される。ゲート電極１３６ｂにゲート閾値電圧よりも高い正電圧が印加されると、ドリフト領域１２２とソース領域１２５の間のチャネル領域ＣＨに反転層が形成され、その反転層を介してソース領域１２５からドリフト領域１２２に電子が流入する。ドリフト領域１２２に流入した電子は、そのドリフト領域１２２を縦方向に流れてドレイン電極１３２に向かう。これにより、ドレイン電極１３２とソース電極１３４が導通し、窒化物半導体装置２がターンオンする。ゲート電極１３６ｂが接地されると、反転層が消失し、窒化物半導体装置２がターンオフする。このように、窒化物半導体装置２は、ゲート電極１３６ｂに印加する電圧に基づいてドレイン電極１３２とソース電極１３４の間のオンとオフを切り換えるスイッチング動作を実行することができる。 Next, the operation of the nitride semiconductor device 2 will be described. At the time of use, a positive voltage is applied to the drain electrode 132, and the source electrode 134 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 136b, an inversion layer is formed in the channel region CH between the drift region 122 and the source region 125, and an inversion layer is formed from the source region 125 to the drift region via the inversion layer. Electrons flow into 122. The electrons that have flowed into the drift region 122 flow vertically through the drift region 122 and head toward the drain electrode 132. As a result, the drain electrode 132 and the source electrode 134 become conductive, and the nitride semiconductor device 2 turns on. When the gate electrode 136b is grounded, the inversion layer disappears and the nitride semiconductor device 2 turns off. In this way, the nitride semiconductor device 2 can execute a switching operation of switching on and off between the drain electrode 132 and the source electrode 134 based on the voltage applied to the gate electrode 136b.
（第２実施形態の窒化物半導体装置２の製造方法）
　まず、図９Ａに示されるように、エピタキシャル成長技術を利用して、ＧａＮ基板であるドレイン領域１２１の表面からｎ型ＧａＮのドリフト領域１２２をエピタキシャル成長させ、窒化物半導体層１２０を形成する。 (Manufacturing Method of Nitride Semiconductor Device 2 of the Second Embodiment)
First, as shown in FIG. 9A, an n-type GaN drift region 122 is epitaxially grown from the surface of a drain region 121, which is a GaN substrate, to form a nitride semiconductor layer 120 by using an epitaxial growth technique.
　次に、図９Ｂに示されるように、イオン注入技術を利用して、窒化物半導体層１２０にｐ型ドーパントとしてマグネシウムをイオン注入し、高濃度ボディ領域１２４ａを形成する。このとき、マグネシウムの注入範囲に水素もイオン注入してもよい。 Next, as shown in FIG. 9B, magnesium is ion-implanted into the nitride semiconductor layer 120 as a p-type dopant by using an ion implantation technique to form a high-concentration body region 124a. At this time, hydrogen may also be ion-implanted into the magnesium injection range.
　次に、図９Ｃに示されるように、エピタキシャル成長技術を利用して、ドリフト領域１２２の表面からｐ型ＧａＮの低濃度ボディ領域１２４ｂをエピタキシャル成長させる。このエピタキシャル再成長では、エピタキシャル再成長工程で用いられる材料由来の水素が、高濃度ボディ領域１２４ａ及び低濃度ボディ領域１２４ｂに取り込まれる。 Next, as shown in FIG. 9C, the low-concentration body region 124b of p-type GaN is epitaxially grown from the surface of the drift region 122 by using the epitaxial growth technique. In this epitaxial regrowth, hydrogen derived from the material used in the epitaxial regrowth step is taken into the high-concentration body region 124a and the low-concentration body region 124b.
　次に、図９Ｄに示されるように、イオン注入技術を利用して、窒化物半導体層２０にｎ型ドーパントとしてシリコン又はゲルマニウムをイオン注入し、ソース領域１２５を形成する。さらに、イオン注入技術を利用して、窒化物半導体層２０にｐ型ドーパントとしてマグネシウムをイオン注入し、ボディコンタクト領域１２６を形成する。 Next, as shown in FIG. 9D, silicon or germanium is ion-implanted into the nitride semiconductor layer 20 as an n-type dopant by using the ion implantation technique to form the source region 125. Further, using the ion implantation technique, magnesium is ion-implanted into the nitride semiconductor layer 20 as a p-type dopant to form the body contact region 126.
　次に、窒化物半導体層１２０の表面上にアニール用保護膜を成膜する。アニール用保護膜は、第１の製造方法のアニール用保護膜４２、第２の製造方法のアニール用保護膜４６又は第３の製造方法のアニール用保護膜４８のいずれを適用してもよい。 Next, a protective film for annealing is formed on the surface of the nitride semiconductor layer 120. As the protective film for annealing, any of the protective film 42 for annealing in the first manufacturing method, the protective film 46 for annealing in the second manufacturing method, or the protective film 48 for annealing in the third manufacturing method may be applied.
　次に、ｎ型ドーパント及びｐ型ドーパントを活性化させるために、アニール処理を実施する。このアニール処理の温度は、１２００℃以上である。より具体的には、アニール処理の温度は１２００～１５００℃である。アニール処理の雰囲気ガス及び圧力は、特に限定されるものではない。例えば、このアニール処理工程は、第１実施形態の窒化物半導体装置１の第１～第４の製造方法のいずれかのアニール処理工程と同一とすることができる。 Next, an annealing treatment is performed in order to activate the n-type dopant and the p-type dopant. The temperature of this annealing treatment is 1200 ° C. or higher. More specifically, the temperature of the annealing treatment is 1200 to 1500 ° C. The atmospheric gas and pressure of the annealing treatment are not particularly limited. For example, this annealing treatment step can be the same as the annealing treatment step of any one of the first to fourth manufacturing methods of the nitride semiconductor device 1 of the first embodiment.
　上記したように、この製造方法では、エピタキシャル再成長のときに、材料由来の水素が高濃度ボディ領域１２４ａ及び低濃度ボディ領域１２４ｂに取り込まれる。このため、アニール処理工程を実施すると、高濃度ボディ領域１２４ａ及び低濃度ボディ領域１２４ｂに取り込まれた水素は、ｐ型ドーパントであるマグネシウムと結合することができる。水素が結合したマグネシウムは、Ｇａサイトに取り込められ易くなるという性質がある。このため、アニール処理工程を実施すると、マグネシウムを効率的にＧａサイトに取り込むことができる。この結果、ｐ型ドーパントの活性化率を高くすることができるので、高活性なｐ型領域を形成することができる。 As described above, in this production method, hydrogen derived from the material is incorporated into the high-concentration body region 124a and the low-concentration body region 124b at the time of epitaxial regrowth. Therefore, when the annealing treatment step is carried out, the hydrogen incorporated in the high-concentration body region 124a and the low-concentration body region 124b can be bonded to magnesium, which is a p-type dopant. Magnesium to which hydrogen is bound has the property of being easily taken up by Ga sites. Therefore, when the annealing treatment step is carried out, magnesium can be efficiently incorporated into the Ga site. As a result, the activation rate of the p-type dopant can be increased, so that a highly active p-type region can be formed.
　次に、図９Ｅに示されるように、ドライエッチング技術を利用して、窒化物半導体層１２０の上面からソース領域１２５及び低濃度ボディ領域１２４ｂを貫通してドリフト領域１２２に達するトレンチＴＲ１を形成する。 Next, as shown in FIG. 9E, a dry etching technique is used to form a trench TR1 that penetrates the source region 125 and the low-concentration body region 124b from the upper surface of the nitride semiconductor layer 120 and reaches the drift region 122. ..
　次に、図９Ｆに示されるように、蒸着技術を利用して、トレンチＴＲ１の内壁面を含む窒化物半導体層１２０の上面を被覆するようにゲート絶縁膜１３６ａを成膜する。蒸着技術としては、原子層堆積法又はプラズマＣＶＤ法が利用される。次に、ポストアニール（Post Deposition Annealing: PDA）処理を実施してゲート絶縁膜１３６ａの膜質を改善する。ポストアニール処理工程については、第１実施形態の窒化物半導体装置１の第１の製造方法のポストアニール処理工程と同一とすることができる。 Next, as shown in FIG. 9F, a gate insulating film 136a is formed so as to cover the upper surface of the nitride semiconductor layer 120 including the inner wall surface of the trench TR1 by using a thin film deposition technique. As the vapor deposition technique, an atomic layer deposition method or a plasma CVD method is used. Next, a post-deposition annealing (PDA) treatment is performed to improve the film quality of the gate insulating film 136a. The post-annealing process can be the same as the post-annealing process of the first manufacturing method of the nitride semiconductor device 1 of the first embodiment.
　次に、図９Ｇに示されるように、蒸着技術を利用して、トレンチＴＲ１内に充填されるようにゲート絶縁膜１３６ａの表面上にゲート電極１３６ｂを成膜する。さらに、エッチング技術を利用して、ゲート絶縁膜１３６ａ及びゲート電極１３６ｂを加工し、絶縁ゲート部１３６を形成する。この後、既知の製造技術を利用して、ドレイン電極１３２及びソース電極１３４を形成することで、図８に示す窒化物半導体装置２を製造することができる。 Next, as shown in FIG. 9G, a gate electrode 136b is formed on the surface of the gate insulating film 136a so as to be filled in the trench TR1 by using a thin film deposition technique. Further, the gate insulating film 136a and the gate electrode 136b are processed by using the etching technique to form the insulated gate portion 136. After that, the nitride semiconductor device 2 shown in FIG. 8 can be manufactured by forming the drain electrode 132 and the source electrode 134 by using a known manufacturing technique.
　エピタキシャル再成長により材料由来の水素を取り込ませる技術は、ボディ領域以外のｐ型領域にも適用可能であり、例えば、ガードリング又はリサーフ層といった周辺耐圧構造にも適用可能である。エピタキシャル再成長により形成されるエピタキシャル成長層は、形成しようとする構造に応じてｎ型、ｐ型又はｉ型とすることができる。また、エピタキシャル再成長により形成されるエピタキシャル成長層は、必要に応じて除去してもよい。 The technique of incorporating hydrogen derived from a material by epitaxial regrowth can be applied to a p-type region other than the body region, and can also be applied to a peripheral pressure resistant structure such as a guard ring or a resurf layer. The epitaxial growth layer formed by epitaxial regrowth can be n-type, p-type or i-type depending on the structure to be formed. Further, the epitaxial growth layer formed by epitaxial regrowth may be removed if necessary.
　本明細書が開示する技術要素について、以下に列記する。なお、以下の各技術要素は、それぞれ独立して有用なものである。 The technical elements disclosed in this specification are listed below. The following technical elements are useful independently.
（１）窒化物半導体装置の製造方法は、窒化物半導体層にｐ型ドーパントをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層の表面上に保護膜を成膜する保護膜成膜工程と、前記保護膜成膜工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記アニール処理工程は、１２００℃以上の温度であって、アンモニア雰囲気下、且つ、標準気圧（１００ｋＰａ）よりも低い圧力で前記窒化物半導体層を加熱する加熱工程、を有することができる。ｐ型ドーパントの種類は特に限定されない。一例ではあるが、ｐ型ドーパントはマグネシウムであってもよい。 (1) The method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step. The annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher under an ammonia atmosphere and at a pressure lower than the standard atmospheric pressure (100 kPa). The type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
（２）窒化物半導体装置の製造方法は、窒化物半導体層にｐ型ドーパントをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層の表面上に保護膜を成膜する保護膜成膜工程と、前記保護膜成膜工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記保護膜成膜工程では、前記窒化物半導体層の一対の主面の間を延びる側面を被覆するように、前記保護膜が前記窒化物半導体層の表面に成膜される。ｐ型ドーパントの種類は特に限定されない。一例ではあるが、ｐ型ドーパントはマグネシウムであってもよい。 (2) The method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step. In the protective film forming step, the protective film is formed on the surface of the nitride semiconductor layer so as to cover the side surfaces extending between the pair of main surfaces of the nitride semiconductor layer. The type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
（３）窒化物半導体装置の製造方法は、窒化物半導体層にｐ型ドーパントをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層の表面上に保護膜を成膜する保護膜成膜工程と、前記保護膜成膜工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記保護膜成膜工程は、前記窒化物半導体層の表面上に窒化アルミニウム膜を成膜する第１成膜工程と、前記窒化アルミニウム膜の表面上に酸化膜を成膜する第２成膜工程と、を有することができる。ｐ型ドーパントの種類は特に限定されない。一例ではあるが、ｐ型ドーパントはマグネシウムであってもよい。 (3) The method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. After the protective film film forming step, an annealing treatment step of annealing the nitride semiconductor layer can be provided. The protective film film forming step includes a first film forming step of forming an aluminum nitride film on the surface of the nitride semiconductor layer and a second film forming step of forming an oxide film on the surface of the aluminum nitride film. And can have. The type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
（４）窒化物半導体装置の製造方法は、窒化物半導体層にｐ型ドーパントをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記アニール処理工程は、１２００℃以上の温度で前記窒化物半導体層を加熱する加熱工程、を有することができる。前記イオン注入工程では、前記ｐ型ドーパントのイオン注入とアニール処理の組み合わせの複数回が実施される。前記イオン注入工程の前記アニール処理の温度は、前記加熱工程の温度よりも低い。ｐ型ドーパントの種類は特に限定されない。一例ではあるが、ｐ型ドーパントはマグネシウムであってもよい。 (4) The method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into the nitride semiconductor layer, an annealing step of annealing the nitride semiconductor layer after the ion implantation step, and an annealing step. Can be provided. The annealing treatment step can include a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher. In the ion implantation step, a combination of ion implantation and annealing treatment of the p-type dopant is carried out a plurality of times. The temperature of the annealing treatment in the ion implantation step is lower than the temperature of the heating step. The type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
（５）窒化物半導体装置の製造方法は、窒化物半導体層の一方の主面にｐ型ドーパントをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層の前記一方の主面上に窒化物半導体をエピタキシャル成長させるピタキシャル成長工程と、エピタキシャル成長工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記ｐ型ドーパントがマグネシウムである。 (5) The method for manufacturing a nitride semiconductor device includes an ion injection step of ion-injecting a p-type dopant into one main surface of the nitride semiconductor layer, and the one of the nitride semiconductor layers after the ion injection step. It is possible to include a pivotal growth step of epitaxially growing a nitride semiconductor on the main surface, and an annealing treatment step of annealing the nitride semiconductor layer after the epitaxial growth step. The p-type dopant is magnesium.
（６）窒化物半導体装置の製造方法は、窒化物半導体層にｐ型ドーパントをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層の表面上に保護膜を成膜する保護膜成膜工程と、前記保護膜成膜工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記アニール処理工程は、初期圧力を５０ＭＰａ以上とした後に、前記窒化物半導体層を１２００℃の温度にまで昇温する工程、を有することができる。ｐ型ドーパントの種類は特に限定されない。一例ではあるが、ｐ型ドーパントはマグネシウムであってもよい。 (6) The method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting a p-type dopant into a nitride semiconductor layer, and a protective film formed on the surface of the nitride semiconductor layer after the ion implantation step. It is possible to provide a protective film forming step and an annealing step of annealing the nitride semiconductor layer after the protective film forming step. The annealing treatment step can include a step of raising the temperature of the nitride semiconductor layer to a temperature of 1200 ° C. after setting the initial pressure to 50 MPa or more. The type of p-type dopant is not particularly limited. As an example, the p-type dopant may be magnesium.
（７）窒化物半導体装置の製造方法は、窒化物半導体層にｐ型ドーパントとしてマグネシウムをイオン注入するイオン注入工程と、前記イオン注入工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えることができる。前記イオン注入工程では、前記マグネシウムの導入範囲に水素もイオン注入される。 (7) The method for manufacturing a nitride semiconductor device includes an ion implantation step of ion-implanting magnesium as a p-type dopant into the nitride semiconductor layer, and an annealing treatment step of annealing the nitride semiconductor layer after the ion implantation step. And can be provided. In the ion implantation step, hydrogen is also ion-implanted into the magnesium introduction range.
（８）窒化物半導体装置の製造方法は、窒化物半導体層の表面上にゲート絶縁膜を成膜するゲート絶縁膜成膜工程と、前記ゲート絶縁膜成膜工程の後に、ポストアニール（Post Deposition Annealing: PDA）処理するポストアニール処理工程と、を備えることができる。前記ポストアニール処理工程の温度及び圧力は、前記窒化物半導体層を構成する窒化物半導体の状態図に基づいて、前記状態図の固相が維持される条件に設定されている。 (8) The method for manufacturing a nitride semiconductor device is as follows: a gate insulating film film forming step of forming a gate insulating film on the surface of the nitride semiconductor layer, and a post annealing (Post Deposition) after the gate insulating film film forming step. Annealing: PDA) can be provided with a post-annealing process for processing. The temperature and pressure in the post-annealing treatment step are set under conditions in which the solid phase of the state diagram is maintained based on the state diagram of the nitride semiconductor constituting the nitride semiconductor layer.
　以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、請求の範囲を限定するものではない。請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims (9)

  1. 　窒化物半導体装置の製造方法であって、
    　窒化物半導体層にｐ型ドーパントをイオン注入するイオン注入工程と、
    　前記イオン注入工程の後に、前記窒化物半導体層の表面上に保護膜を成膜する保護膜成膜工程と、
    　前記保護膜成膜工程の後に、前記窒化物半導体層をアニール処理するアニール処理工程と、を備えており、
    　前記アニール処理工程は、
    　　１２００℃以上の温度であって、アンモニア雰囲気下、且つ、１０ｋＰａよりも低い圧力で前記窒化物半導体層を加熱する加熱工程、を有する、窒化物半導体装置の製造方法。     A method for manufacturing nitride semiconductor devices.
    An ion implantation process in which a p-type dopant is ion-implanted into a nitride semiconductor layer,
    After the ion implantation step, a protective film forming step of forming a protective film on the surface of the nitride semiconductor layer, and a protective film forming step.
    After the protective film film forming step, an annealing treatment step of annealing the nitride semiconductor layer is provided.
    The annealing treatment step is
    A method for manufacturing a nitride semiconductor device, comprising a heating step of heating the nitride semiconductor layer at a temperature of 1200 ° C. or higher, under an ammonia atmosphere, and at a pressure lower than 10 kPa.
  2. 　前記保護膜成膜工程では、前記窒化物半導体層の一対の主面の間を延びる側面を被覆するように、前記保護膜が前記窒化物半導体層の表面に成膜される、請求項１に記載の窒化物半導体装置の製造方法。 According to claim 1, in the protective film film forming step, the protective film is formed on the surface of the nitride semiconductor layer so as to cover the side surfaces extending between the pair of main surfaces of the nitride semiconductor layer. The method for manufacturing a nitride semiconductor device according to the description.
  3. 　前記保護膜成膜工程は、
    　　前記窒化物半導体層の表面上に窒化アルミニウム膜を成膜する第１成膜工程と、
    　　前記窒化アルミニウム膜の表面上に酸化膜を成膜する第２成膜工程と、を有する、請求項１又は２に記載の窒化物半導体装置の製造方法。     The protective film film forming step is
    The first film forming step of forming an aluminum nitride film on the surface of the nitride semiconductor layer, and
    The method for manufacturing a nitride semiconductor device according to claim 1 or 2, further comprising a second film forming step of forming an oxide film on the surface of the aluminum nitride film.
  4. 　前記イオン注入工程では、前記ｐ型ドーパントのイオン注入とアニール処理の組み合わせの複数回が実施され、
    　前記イオン注入工程の前記アニール処理の温度は、前記加熱工程の温度よりも低い、請求項１～３のいずれか一項に記載の窒化物半導体装置の製造方法。     In the ion implantation step, a combination of ion implantation and annealing treatment of the p-type dopant is carried out a plurality of times.
    The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 3, wherein the temperature of the annealing treatment in the ion implantation step is lower than the temperature of the heating step.
  5. 　前記アニール処理工程はさらに、
    　　初期圧力を５０ＭＰａ以上とした後に、前記窒化物半導体層を１２００℃の温度にまで昇温する昇温工程、を有する、請求項１～４のいずれか一項に記載の窒化物半導体装置の製造方法。     The annealing step further
    The production of the nitride semiconductor apparatus according to any one of claims 1 to 4, further comprising a step of raising the temperature of the nitride semiconductor layer to a temperature of 1200 ° C. after setting the initial pressure to 50 MPa or more. Method.
  6. 　前記イオン注入工程と前記保護膜成膜工程の間に、前記窒化物半導体層の表面上に窒化物半導体をエピタキシャル成長させるピタキシャル成長工程、をさらに備えている、請求項１～５のいずれか一項に記載の窒化物半導体装置の製造方法。 Any one of claims 1 to 5, further comprising a pivotal growth step of epitaxially growing a nitride semiconductor on the surface of the nitride semiconductor layer between the ion implantation step and the protective film film forming step. The method for manufacturing a nitride semiconductor device according to the above.
  7. 　前記アニール処理工程の後に、前記保護膜を除去する保護膜除去工程と、
    　前記保護膜除去工程の後に、前記窒化物半導体層の表面上にゲート絶縁膜を成膜するゲート絶縁膜成膜工程と、
    　前記ゲート絶縁膜成膜工程の後に、ポストアニール（Post Deposition Annealing: PDA）処理するポストアニール処理工程と、をさらに備えており、
    　前記ポストアニール処理工程の温度及び圧力は、前記窒化物半導体層を構成する窒化物半導体の状態図に基づいて、前記状態図の固相が維持される条件に設定されている、請求項１～６のいずれか一項に記載の窒化物半導体装置の製造方法。     After the annealing treatment step, a protective film removing step of removing the protective film and a protective film removing step
    After the protective film removing step, a gate insulating film forming step of forming a gate insulating film on the surface of the nitride semiconductor layer, and a gate insulating film forming step.
    After the gate insulating film film forming step, a post-annealing treatment step of performing a post-annealing (PDA) treatment is further provided.
    The temperature and pressure of the post-annealing treatment step are set under the condition that the solid phase of the state diagram is maintained based on the state diagram of the nitride semiconductor constituting the nitride semiconductor layer. The method for manufacturing a nitride semiconductor device according to any one of 6.
  8. 　前記ｐ型ドーパントがマグネシウムである、請求項１～７のいずれか一項に記載の窒化物半導体装置の製造方法。 The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 7, wherein the p-type dopant is magnesium.
  9. 　前記イオン注入工程では、前記ｐ型ドーパントであるマグネシウムの注入範囲に水素もイオン注入される、請求項８に記載の窒化物半導体装置の製造方法。 The method for manufacturing a nitride semiconductor device according to claim 8, wherein in the ion implantation step, hydrogen is also ion-implanted into the implantation range of magnesium, which is the p-type dopant.
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