WO2021147101A1 - 一种芯片装置和无线通信装置 - Google Patents

一种芯片装置和无线通信装置 Download PDF

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Publication number
WO2021147101A1
WO2021147101A1 PCT/CN2020/074025 CN2020074025W WO2021147101A1 WO 2021147101 A1 WO2021147101 A1 WO 2021147101A1 CN 2020074025 W CN2020074025 W CN 2020074025W WO 2021147101 A1 WO2021147101 A1 WO 2021147101A1
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Prior art keywords
capacitor
coupled
mos transistor
radio frequency
pin
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PCT/CN2020/074025
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English (en)
French (fr)
Inventor
池毓宋
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20914902.0A priority Critical patent/EP4084069A4/en
Priority to CN202080094219.6A priority patent/CN115004366A/zh
Priority to PCT/CN2020/074025 priority patent/WO2021147101A1/zh
Publication of WO2021147101A1 publication Critical patent/WO2021147101A1/zh
Priority to US17/870,800 priority patent/US20220359475A1/en

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]

Definitions

  • This application relates to the field of integrated circuits, and in particular to a chip device and a wireless communication device.
  • the power supply for the circuit modules plays a very important role.
  • the noise performance of the power supply is also an important indicator that needs to be considered.
  • the noise brought by the power supply will enter the circuit module through the power supply network and cause interference to the operation of the circuit module.
  • the high-frequency circuit modules in the chip are more sensitive to the noise brought by the power supply.
  • Common circuit modules include a local oscillator (LO), a low noise amplifier (LNA) and so on in a radio frequency transceiver chip.
  • the present application provides a chip device and a wireless communication device, which can improve the power noise performance of the chip.
  • a chip device includes: a die, a first bonding pin, a second bonding pin, and a first bonding pin; wherein the first bonding pin and the second bonding pin
  • the bonding pin is provided on the upper surface of the die, the die is provided with a first power module and a second power module, the first power module is coupled with the first bonding pin, the The second power module is coupled with the second bonding pin; the first welding pins are respectively coupled with the external power supply of the chip device, and the first bonding pin and the second bonding pin are coupled .
  • the chip device further includes: a rewiring layer, the rewiring layer is provided on the upper surface of the die; the first soldering pin is provided on the rewiring layer Upper surface; the rewiring layer is provided with a first rewiring metal and a second rewiring metal; the first soldering pin is coupled with the first bonding pin through the first rewiring metal, so The first welding pin is coupled with the second bonding pin through the second rewiring metal.
  • the length of the wire connecting the bonding pin and the welding pin is more flexible and controllable, and it is easier to adjust the equivalent inductance in the power supply path, thereby improving the noise performance of the chip device.
  • one end of the first rewiring metal is connected to the upper surface of the first bonding pin, and the other end of the first rewiring metal is connected to the upper surface of the first bonding pin.
  • a first capacitor is provided in the die, and the first terminal and the second terminal of the first capacitor are respectively coupled to a high level and a low level.
  • the first capacitor includes a first MOS transistor, a second MOS transistor, and a first passive capacitor; the first MOS transistor and the first passive capacitor are coupled in series to the Between the first terminal and the second terminal of the first capacitor, the gate of the first MOS transistor is used to receive a first control signal, and the first control signal is used to control the on and off of the first MOS transistor
  • the gate of the second MOS tube is coupled to the connection end of the first passive capacitor and the first MOS tube, and the source and drain of the second MOS tube are commonly coupled to the first capacitor The first end.
  • the first capacitor includes a first MOS transistor, a second MOS transistor, a first passive capacitor, and a second passive capacitor; the first MOS transistor and the first passive capacitor The capacitor is coupled in series between the first terminal and the second terminal of the first capacitor, the gate of the first MOS transistor is used to receive a first control signal, and the first control signal is used to control the first MOS transistor The on and off; the gate of the second MOS tube is coupled to the connection end of the first passive capacitor and the first MOS tube, and the second MOS tube and the second passive capacitor are connected in series It is coupled between the first end and the second end of the first capacitor; the gate of the first MOS transistor is coupled to the connection end of the second passive capacitor and the second MOS transistor.
  • the first capacitor further includes a third MOS transistor, the aspect ratio of the third MOS is smaller than that of the first MOS transistor and the second MOS transistor, and the third MOS transistor
  • the source and drain of the tube are coupled to both ends of the first passive capacitor, the gate of the third MOS tube is used to receive a second control signal, and the second control signal is used to control the third MOS tube On and off.
  • the chip device further includes a third bonding pin, the third bonding pin is disposed on the upper surface of the die, and a third bonding pin is disposed in the rewiring layer.
  • Rewiring metal the first soldering pin is connected to the third bonding pin through the third rewiring metal; one end of the first capacitor is coupled to the third bonding pin, the The other end of the first capacitor is grounded; the length of the third rewiring metal is smaller than the length of the first rewiring metal and the length of the second rewiring metal.
  • the die is further provided with a first inductor, one end of the first inductor is coupled to the first bonding pin, and the other end of the first inductor is coupled to the first bonding pin.
  • the input terminal of the first power supply module is a possible implementation, by introducing an on-chip inductor, and introducing an additional series inductor in the power supply path of the power supply, the performance of the power supply can be further improved.
  • a second capacitor is further provided in the die, one end of the second capacitor is coupled to the input end of the first power module, and the other end of the second capacitor is grounded.
  • the die is further provided with a first radio frequency receiving channel and a second radio frequency receiving channel; the first radio frequency receiving channel is used to receive the first component carrier signal, and the second radio frequency The receiving channel is used to receive a second component carrier signal, and the first component carrier signal and the second component carrier signal together form a downlink carrier aggregation; the first radio frequency receiving channel and the second radio frequency receiving channel are provided with Multiple radio frequency modules; the first power module and the second power module are respectively used to supply power to one or more of the multiple radio frequency modules.
  • the die is further provided with a second inductor, one end of the second inductor is coupled to the second bonding pin, and the other end of the second inductor is coupled to the second bonding pin.
  • the first power module is a low-dropout linear regulator
  • the first power module is a low-dropout linear regulator
  • the first power module is used to provide The first local oscillator of the radio frequency receiving channel provides power
  • the second power module is a low dropout linear regulator
  • the second power module is used to power the low pass filter of the first radio frequency receiving channel.
  • this application proposes a wireless communication device, including a baseband processing chip and a chip device in any possible implementation manner, and the chip device is coupled with the baseband processing chip.
  • the wireless communication device further includes: a printed circuit board and an antenna, the baseband processing chip and the chip device are fixed to the printed circuit board; the antenna is used to provide the chip device Radio frequency signal.
  • the present application proposes an integrated circuit.
  • the integrated circuit is provided with a capacitor module.
  • the capacitor module includes a first terminal and a second terminal.
  • the capacitor module passes through the first terminal and the second terminal. The two ends are connected to an external circuit;
  • the capacitor module includes a first MOS tube, a second MOS tube, and a first passive capacitor;
  • the first MOS tube and the first passive capacitor are coupled in series to the capacitor module
  • the first MOS transistor is used to receive a control signal, and the control signal is used to control the on and off of the first MOS transistor;
  • the gate of the second MOS transistor is coupled to A connection end with the first passive capacitor and the first MOS transistor, and the source and drain of the second MOS transistor are commonly coupled to the first end of the capacitor module.
  • the capacitor module has higher capacitance density and ESD resistance.
  • the present application proposes an integrated circuit.
  • the integrated circuit is provided with a capacitor module.
  • the capacitor module includes a first terminal and a second terminal.
  • the capacitor module passes through the first terminal and the second terminal. The two ends are connected to an external circuit;
  • the capacitor module includes a first MOS tube, a second MOS tube, a first passive capacitor, and a second passive capacitor;
  • the first MOS tube and the first passive capacitor are coupled in series
  • the first MOS transistor is used to receive a first control signal, and the first control signal is used to control the on and off of the first MOS transistor;
  • the gate of the second MOS transistor is coupled to the connection end of the first passive capacitor and the first MOS transistor, and the second MOS transistor and the second passive capacitor are coupled in series to the first passive capacitor of the capacitor module. Between one end and the second end.
  • the wireless communication device may be a wireless communication device, or part of the device in the wireless communication device, such as a chip, a combination of chips, or integrated circuit products such as a module containing a chip. These integrated circuits
  • the product may include the chip device provided in the embodiment of the present application.
  • the wireless communication device may be a terminal such as a smart phone, or a wireless access network device such as a base station.
  • the chips used for wireless communication can be divided into baseband chips and radio frequency chips.
  • the baseband chip is also called a modem (modem) or a baseband processing chip.
  • the radio frequency chip is also called a transceiver chip, a radio frequency transceiver (transceiver) or a radio frequency processing chip. Therefore, the wireless communication device may be a single chip or a combination of multiple chips, such as a system chip, a chip platform, or a chip package.
  • a system chip is also called a system on a chip (SoC), or SoC chip for short, which can be understood as packaging multiple chips together to form a larger chip.
  • SoC system on a chip
  • the baseband chip can be further packaged in the SoC chip.
  • a chip platform or chip set piece can be understood as multiple chips that need to be used in conjunction. These multiple chips are often packaged independently, but the chips need to cooperate with each other to complete the wireless communication function together.
  • the baseband chip (or SoC chip integrated with the baseband chip) and the radio frequency chip are usually packaged separately, but they need to be used together.
  • FIG. 1 is a schematic structural diagram of a wireless communication system provided by an embodiment of this application.
  • FIG. 2 is a schematic diagram of carrier configuration of a wireless communication system provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a wireless communication device provided by an embodiment of this application.
  • FIG. 4 is a schematic diagram of a radio frequency chip provided by an embodiment of the present application.
  • FIG. 5 is a schematic side view of a chip device provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a chip device provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of another chip device provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a chip architecture provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another chip architecture provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a capacitor provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • devices can be divided into devices that provide wireless network services and devices that use wireless network services.
  • Devices that provide wireless network services refer to those devices that make up a wireless communication network, which can be referred to as network equipment (network equipment) or network element (network element) for short.
  • Network equipment usually belongs to operators or infrastructure providers, and these vendors are responsible for operation or maintenance.
  • Network equipment can be further divided into radio access network (RAN) equipment and core network (CN) equipment.
  • RAN radio access network
  • CN core network
  • a typical RAN device includes a base station (base station, BS).
  • the base station may sometimes be referred to as a wireless access point (access point, AP), or a transmission reception point (transmission reception point, TRP).
  • the base station may be a generation Node B (gNB) in a 5G new radio (NR) system, or an evolution node B (evolutional Node B, eNB) in a 4G long term evolution (LTE) system.
  • gNB generation Node B
  • NR new radio
  • eNB evolution node B
  • LTE long term evolution
  • the base station can be divided into a macro base station or a micro base station. Micro base stations are sometimes called small base stations or small cells.
  • a device that uses wireless network services can be referred to as a terminal for short.
  • the terminal can establish a connection with the network device, and provide users with specific wireless communication services based on the service of the network device. It should be understood that since the relationship between the terminal and the user is closer, it is sometimes called a user equipment (UE) or a subscriber unit (SU).
  • UE user equipment
  • SU subscriber unit
  • MS mobile stations
  • some network devices such as relay nodes (RN) or wireless routers, may also be regarded as terminals because they have UE identities or belong to users.
  • RN relay nodes
  • RN relay nodes
  • wireless routers may also be regarded as terminals because they have UE identities or belong to users.
  • the terminal may be a mobile phone, a tablet computer, a laptop computer, a wearable device (such as a smart watch, smart bracelet, smart helmet, smart glasses), and others Devices with wireless access capabilities, such as smart cars, various Internet of Things (IOT) devices, including various smart home devices (such as smart meters and smart home appliances) and smart city devices (such as security or monitoring equipment, Intelligent road traffic facilities) and so on.
  • IOT Internet of Things
  • smart home devices such as smart meters and smart home appliances
  • smart city devices such as security or monitoring equipment, Intelligent road traffic facilities
  • FIG. 1 is a schematic structural diagram of a wireless communication system provided by an embodiment of this application.
  • the wireless communication system includes a terminal and a base station. According to different transmission directions, the transmission link from the terminal to the base station is recorded as uplink (UL), and the transmission link from the base station to the terminal is recorded as downlink (DL).
  • UL uplink
  • DL downlink
  • data transmission in the uplink can be abbreviated as uplink data transmission or uplink transmission
  • data transmission in the downlink can be abbreviated as downlink data transmission or downlink transmission.
  • the base station can provide communication coverage for a specific geographic area through an integrated or external antenna device.
  • One or more terminals located within the communication coverage area of the base station can all access the base station.
  • a base station can manage one or more cells. Each cell has an identification (identification), which is also called a cell identity (cell ID). From the perspective of radio resources, a cell is a combination of downlink radio resources and uplink radio resources (not necessary) paired with it.
  • the wireless communication system can comply with the wireless communication standards of the third generation partnership project (3GPP), and can also comply with other wireless communication standards, such as the Institute of Electrical and Electronics Engineers, IEEE ) 802 series (such as 802.11, 802.15, or 802.20) wireless communication standards. Although only one base station and one terminal are shown in FIG. 1, the wireless communication system may also include other numbers of terminals and base stations. In addition, the wireless communication system may also include other network equipment, such as core network equipment.
  • 3GPP Third generation partnership project
  • other wireless communication standards such as the Institute of Electrical and Electronics Engineers, IEEE 802 series (such as 802.11, 802.15, or 802.20) wireless communication standards.
  • the wireless communication system may also include other numbers of terminals and base stations.
  • the wireless communication system may also include other network equipment, such as core network equipment.
  • the terminal and the base station should know the predefined configuration of the wireless communication system, including the radio access technology (RAT) supported by the system and the radio resource configuration specified by the system, such as the basic configuration of the radio frequency band and carrier.
  • the carrier is a frequency range that complies with the system regulations. This section of frequency range can be determined by the center frequency of the carrier (denoted as carrier frequency) and the bandwidth of the carrier.
  • the pre-defined configuration of these systems can be used as a part of the standard protocol of the wireless communication system, or determined by the interaction between the terminal and the base station.
  • the content of the relevant standard protocol may be pre-stored in the memory of the terminal and the base station, or embodied in the hardware circuit or software code of the terminal and the base station.
  • the terminal and the base station support one or more of the same RAT, such as 5G NR, 4G LTE, or the RAT of the future evolution system.
  • the terminal and the base station use the same air interface parameters, coding scheme, modulation scheme, etc., and communicate with each other based on the wireless resources specified by the system.
  • FIG. 2 is a schematic diagram of carrier configuration of a wireless communication system provided by an embodiment of the application.
  • the base station configures two carrier sets for the terminal, which are respectively denoted as the first carrier set and the second carrier set.
  • the first carrier set may be used for downlink carrier aggregation (DLCA)
  • the second carrier set may be used for uplink carrier aggregation (ULCA).
  • the frequency ranges of the carriers included in the two carrier sets may be different, such as terminals in FDD (frequency duplex division) mode; the frequency ranges of the carriers included in the two carrier sets may be the same, such as in TDD ( Terminal in time duplex division (frequency division duplex) mode.
  • FDD frequency duplex division
  • TDD Terminal in time duplex division (frequency division duplex) mode.
  • the first carrier set includes 6 component carriers (CC), which are sequentially denoted as CC1 to CC6.
  • the second carrier set includes 4 component carriers, including CC1 to CC4. It should be understood that the number of CCs included in the first carrier set and the second carrier set is for illustrative purposes only. In the embodiment of the present application, the first carrier set and the second carrier set may also include other numbers of CCs.
  • These CCs can be continuous or non-continuous in the frequency domain. Different CCs can be in the same frequency band and can correspond to intra-band carrier aggregation (intra-band CA). Different CCs can also be in different frequency bands, which can correspond to inter-band carrier aggregation (inter-band CA).
  • one component carrier may correspond to one serving cell of the terminal.
  • a component carrier is sometimes also translated as a component carrier, which can be referred to as a carrier, and a serving cell can be referred to as a cell.
  • carrier can be referred to as a carrier
  • serving cell can be referred to as a cell.
  • the terms “carrier”, “component carrier”, “aggregated carrier”, “aggregated component carrier”, “serving cell”, “cell”, “one of PCell or SCell”, “PCC or SCC” and “aggregated carrier” can be used interchangeably.
  • FIG. 3 is a schematic structural diagram of a wireless communication device provided by an embodiment of the application.
  • the wireless communication device may be a terminal or a base station in the embodiment of the present application.
  • the wireless communication equipment may include application subsystems, memory, mass storage, baseband subsystems, radio frequency intergreted circuit (RFIC), and radio frequency front end (radio frequency).
  • RFIC radio frequency intergreted circuit
  • RFFE radio frequency front end
  • antennas antennas
  • ANT_1 represents the first antenna
  • ANT_N represents the Nth antenna
  • N is a positive integer greater than 1.
  • Tx represents the transmission path
  • Rx represents the reception path
  • different numbers represent different paths.
  • FBRx represents the feedback receiving path
  • PRx represents the main receiving path
  • DRx represents the diversity receiving path.
  • HB stands for high frequency
  • LB stands for low frequency. Both refer to the relative high and low of the frequency.
  • BB stands for baseband. It should be understood that the marks and components in FIG. 3 are for illustrative purposes only, and are only used as a possible implementation manner, and the embodiments of the present application also include other implementation manners.
  • Radio frequency integrated circuits can be further divided into radio frequency receiving channel (RF receive path) and radio frequency transmitting channel (RF transmit path).
  • the radio frequency receiving channel can receive the radio frequency signal through the antenna, and process the radio frequency signal (such as amplifying, filtering and down-converting) to obtain the baseband signal, and pass it to the baseband subsystem.
  • the radio frequency transmission channel can receive the baseband signal from the baseband subsystem, perform radio frequency processing (such as up-conversion, amplification and filtering) on the baseband signal to obtain the radio frequency signal, and finally radiate the radio frequency signal into the space through the antenna.
  • the radio frequency subsystem may include an antenna switch, an antenna tuner, a low noise amplifier (LNA), a power amplifier (PA), a mixer (mixer), and a local oscillator (LO). ), filters and other electronic devices, which can be integrated into one or more chips as required.
  • the antenna can sometimes be considered part of the radio frequency subsystem.
  • the baseband subsystem can extract useful information or data bits from the baseband signal, or convert the information or data bits into a baseband signal to be sent. These information or data bits can be data representing user data or control information such as voice, text, and video.
  • the baseband subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding. Different wireless access technologies, such as 5G NR and 4G LTE, often have different baseband signal processing operations. Therefore, in order to support the integration of multiple mobile communication modes, the baseband subsystem can include multiple processing cores or multiple HACs at the same time.
  • the baseband subsystem is generally integrated into one or more chips, and the chip integrated with the baseband subsystem is generally called a baseband processor chip (baseband intergreted circuit, BBIC).
  • BBIC baseband intergreted circuit
  • the radio frequency signal is an analog signal
  • the signal processed by the baseband subsystem is mainly a digital signal
  • an analog-to-digital conversion device is also required in the wireless communication equipment.
  • the analog-to-digital conversion device includes an analog-to-digital converter (ADC) that converts an analog signal into a digital signal, and a digital-to-analog converter (DAC) that converts a digital signal into an analog signal.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • the analog-to-digital conversion device may be arranged in the baseband subsystem or the radio frequency subsystem.
  • the application subsystem can be used as the main control system or main computing system of the wireless communication device, used to run the main operating system and application programs, manage the software and hardware resources of the entire wireless communication device, and provide users with a user operation interface.
  • the application subsystem may include one or more processing cores.
  • the application subsystem may also include driver software related to other subsystems (such as the baseband subsystem).
  • the baseband subsystem may also include one or more processing cores, as well as a hardware accelerator (HAC) and cache.
  • HAC hardware accelerator
  • the radio frequency subsystem may include an independent antenna, an independent radio frequency front end (RF front end, RFFE) device, and an independent radio frequency chip.
  • Radio frequency chips are sometimes called receivers, transmitters, or transceivers. Antennas, RF front-end devices and RF processing chips can all be manufactured and sold separately.
  • the radio frequency subsystem can also adopt different devices or different integration methods based on power consumption and performance requirements. For example, part of the RF front-end components are integrated into the RF chip, and even the antenna and the RF front-end device are integrated into the RF chip.
  • the RF chip can also be called a RF antenna module or an antenna module.
  • FIG. 4 is a schematic diagram of a radio frequency chip provided by an embodiment of the present application. It should be understood that although FIG. 4 only has two receiving channels and one transmitting channel, the present embodiment may be more than this.
  • the radio frequency integrated circuit may include two or more transmitting channels and receiving channels and other channel numbers.
  • the radio frequency receiving channel is generally used to process the received RF signal into an intermediate frequency signal.
  • the radio frequency transmission channel is generally used to process the intermediate frequency signal into the transmitted radio frequency signal.
  • a radio frequency chip includes a first radio frequency receiving channel, a second radio frequency receiving channel, and a first radio frequency transmitting channel.
  • the first radio frequency receiving channel includes a first low noise amplifier (LNA1), a first mixer (mixer 1, MIX1), a first receiving local oscillator (LO_Rx1), a first filter (Filter1), The first analog-to-digital converter (analog to digital converter 1, ADC1).
  • the second radio frequency receiving channel includes a second low noise amplifier (LNA2), a second mixer (mixer 2, MIX2), a second receiving local oscillator (LO_Rx2), a second filter (Filter2), The second analog to digital converter (analog to digital converter 2, ADC2).
  • the low noise amplifier in the radio frequency receiving channel amplifies the received radio frequency signal, and the mixer mixes the radio frequency signal amplified by the low noise amplifier with the local oscillator signal provided by LO_RX, and the intermediate frequency signal is obtained after mixing.
  • the intermediate frequency signal is supplied to the ADC after passing through the filter.
  • the first RF transmission channel shown in Figure 4 includes a digital to analog converter (DAC), a third filter (Filter3), a third mixer (mixer 3, MIX3), and a transmitter local oscillator (LO_Tx). ) And power amplifier (PA).
  • the DAC in the radio frequency transmitting channel converts the digital signal into an analog signal and sends it to the filter.
  • the filter filters the signal.
  • the mixer mixes the analog signal after the filter and the signal provided by the local oscillator and shifts it to radio frequency.
  • Signal, PA then amplifies the power of the radio frequency signal.
  • PA and LNA can also be used as separate RF front-end chip devices outside of the RF channel.
  • the signal to noise ratio (S/N) is an important indicator.
  • the radio frequency module in the radio frequency receiving channel needs the power supply module to provide power to work.
  • the power noise introduced by the power supply module is an important factor that affects the S/N of the radio frequency receiving channel.
  • the second is the crosstalk between the two RF modules.
  • the same power supply module will supply power to multiple radio frequency modules at the same time.
  • the RF signals between the two RF channels will couple crosstalk through the power supply path provided by the same power supply module.
  • the measures currently adopted to increase the noise of the power supply are to optimize the design of the circuit structure of the power supply module itself, and improve the signal-to-noise ratio of the power supply itself.
  • this requires too high an external power supply, which increases the cost.
  • the problem of noise crosstalk on the same power supply path cannot be alleviated.
  • FIG. 5 is a schematic side view of a chip device provided by an embodiment of the application.
  • the chip includes a die and a package layer.
  • Die includes a substrate and a polysilicon (poly) layer located on the substrate.
  • the active area of the chip is provided in the substrate and the polysilicon, that is, the area where the transistor of the chip is realized.
  • Complementary metal oxide semiconductor (CMOS) chip as an example, the active area will be provided with positive channel metal oxide semiconductor (PMOS) and negative channel metal oxide semiconductor (negative channel metal oxide semiconductor).
  • PMOS positive channel metal oxide semiconductor
  • NMOS negative channel metal oxide semiconductor
  • An interconnection metal layer is provided in Die above the poly layer.
  • the interconnection metal layer of Die mainly provides interconnection metal lines for the circuit components integrated on the Die.
  • the interconnection metal lines may include metal lines or metal surfaces on the respective metal layers and via holes between the respective metal layers that are connected to each other.
  • an encapsulation layer may be provided on Die.
  • the encapsulation layer is used to encapsulate Die and encapsulate Die into the final chip product form.
  • the encapsulation layer shown in FIG. 5 may be a rewiring layer.
  • the rewiring layer is disposed on the upper surface of the die, and the rewiring layer may include bonding pins (Bond pad or Bonding pad) and redistribution layer metal (RDL metal, redistribution layer metal).
  • the bonding pins are arranged on the upper surface of Die. The upper surface of the bonding pin is exposed to realize the external connection of Die. It should be understood that the heights of the bonding pins obtained by different processes can be different.
  • the upper surface of the bonding pins may be higher than the dielectric layer of the die and directly exposed, or the upper surfaces of the bonding pins may also be parallel or The dielectric layer below the die is exposed through a windowing process.
  • the input port pins, output port pins, grounding pins, power supply pins, and test pins of the chip will all form corresponding bonding pins on the upper surface of Die.
  • RDL metal can be provided on the bonding pins.
  • Soldering pins solder pad or Soldering pad
  • the solder pad is arranged on the upper surface of the RDL metal and is used to provide solder joints at the chip packaging level to achieve further fixed connection between the chip and the PCB board or other packaging substrates.
  • Solder pads can be classified into solder balls or solder bumps according to their size and process, or solder joints with similar functions.
  • Different rewiring metals may be provided in the rewiring layer to provide electrical connections between different solder pins and solder pins.
  • the RDL metal is arranged between the Bond pad and the Solder pad, one end is connected to the upper surface of the Bond pad, and the other end is connected to the lower surface of the Solder pad.
  • FIG. 6 is a schematic diagram of a chip device provided by an embodiment of the application. As shown in Figure 6, the bonding pins are square, and the welding pins are round. FIG. 6 is only a schematic diagram, and the shapes of the bonding pins and the welding pins in the embodiments of the present application may not be limited to this, and there may be more choices. As shown in Fig. 6, generally speaking, since the solder pins are used for the connection and fixation of the chip and the external packaging substrate or the PCB board, they need to bear more rigid force, so they have a larger area than the bonding pins. Different solder pins and bonding pins are connected by different rewiring metals.
  • the chip structure shown in FIG. 6 is provided with a first bonding pin, a second bonding pin and a first welding pin.
  • the first bonding pin and the second bonding pin are arranged on the upper surface of the die, and the first soldering pin is arranged on the upper surface of the rewiring layer.
  • a plurality of rewiring metals are provided in the rewiring layer to realize the connection of bonding pins and soldering pins.
  • a first power module and a second power module are provided in the die, the first power module is coupled with the first bonding pin, and the second power module is coupled with the second bonding pin.
  • the first soldering pin is coupled with an external power source of the chip device, and is used to provide power to the chip device.
  • the external power supply may include, but is not limited to, a power supply chip, a battery, a USB power supply, and a power supply device or module with similar ability to provide voltage or current.
  • the external power supply may be a system-level power supply that integrates multiple power supply modules, such as a low-dropout regulator (LDO) or a direct current to direct current converter (DCDC). It can be a separate module-level power supply such as LDO or DCDC.
  • LDO low-dropout regulator
  • DCDC direct current to direct current converter
  • the external power supply may be soldered to the same packaging substrate or PCB board as the chip device, and the power supply pin of the external power supply may be connected to the first soldering pin through the wiring of the packaging substrate or the PCB board.
  • the external power supply can also be packaged with the chip device in a plastic packaging (molding) manner, and the power supply pins of the external power supply can pass through silicon vias (TSV) or through dielectric vias. , TDV) and other special processes generated through holes connected to the first welding pin.
  • TSV silicon vias
  • TDV dielectric vias
  • the encapsulation layer is provided with a first rewiring metal and a second rewiring metal; the first soldering pin is connected to the first bonding pin through the first rewiring metal, and the first soldering The pin is connected to the second bonding pin through the second rewiring metal.
  • both ends of the first rewiring metal can be connected to the first bonding pin and the first soldering pin, respectively, and both ends of the second rewiring metal can be connected to the second bonding pin and the first bonding pin, respectively.
  • the first welding pin In a specific chip wiring structure, one end of the first rewiring metal is located on the upper surface of the first bonding pin, and the other end of the first rewiring metal is located on the lower surface of the first bonding pin; One end of the second rewiring metal is located on the upper surface of the first bonding pin, and the other end is located on the lower surface of the first bonding pin.
  • Different bonding pins are used to connect different power modules, and then the different bonding pins are connected to the external power supply through different rewiring metals through soldering pins, which has better power supply noise performance.
  • the rewired metal wiring has less noise interference from other modules caused by the internal wiring of the die, and the interference of the substrate noise, so it will bring better Power supply performance.
  • FIG. 7 is a schematic diagram of another chip device provided by an embodiment of the application.
  • the second rewiring metal in this embodiment may have another connection method.
  • both ends of the first rewiring metal are connected to the first bonding pin and the first soldering pin, respectively, and both ends of the second rewiring metal are connected to the second bonding pin and the first bonding pin, respectively. Bond the pins.
  • one end of the first rewiring metal is located on the upper surface of the first bonding pin, and the other end of the first rewiring metal is located on the lower surface of the first bonding pin;
  • One end of the second rewiring metal is located on the upper surface of the first bonding pin, and the other end is located on the upper surface of the second bonding pin.
  • This chip structure in Figure 6 and Figure 7 can connect different bonding pins to the same power supply welding pin by introducing different rewiring metal connection methods, which improves the connection between different power modules. Isolation also improves the equivalent inductance of different power modules on the power supply path. This can have a better filtering effect on the power supply path, which can filter the noise of the power supply transmitted on the power supply path, or filter the noise caused by the crosstalk between the modules on the power supply path, thereby improving the chip device The power supply noise performance.
  • the chip structure shown in FIG. 6 and FIG. 7 is a wafer level chip scale package (WLCSP).
  • WLCSP wafer level chip scale package
  • the chip structure in the embodiment of the present application may not be limited to this, and the chip structure in the present application may also be based on the existing wirebond or copper pillar and other similar forms of chip packaging technology. structure.
  • the bond pad of the chip will be connected to the Solder pad of the chip through the wire bond.
  • the bond pad of the chip will be connected to the Solder pad through a similar copper pillar.
  • the chip structure may include a first bonding pin, a second bonding pin, a first bonding wire, a second bonding wire, and a first bonding pin.
  • the first welding pin may be connected to the first bonding pin through the first bonding wire, and the first welding pin may be connected to the second bonding pin through the second bonding wire.
  • the first power module is coupled with the first bonding pin, and the second power module is coupled with the second bonding pin.
  • the first welding pin is coupled with the external power supply.
  • different bonding pins can be connected to the same power supply welding pin, which improves the isolation between power supply modules connected to different power supply bonding pins, which has an impact on the noise that propagates on the power supply path. It can also achieve a better filtering effect, thereby improving the power noise performance of the chip device.
  • Rewiring metals, bonding wires and copper pillars and other similar packaging forms have different advantages in different application scenarios.
  • rewiring metal is more advantageous; for multi-chip packaging with higher thickness requirements, copper pillar packaging has more advantages; for large chips, cost requirements are higher, and keys are used.
  • the encapsulation of the bonding wire has more advantages.
  • FIG. 8 is a schematic diagram of a chip architecture provided by an embodiment of the present application.
  • the chip device may also be provided with a third bonding pin.
  • the third bonding pin is connected to the first welding pin through the third rewiring metal.
  • a third capacitor may be provided in the die of the chip device, one end of the third capacitor is grounded, and the other end is coupled to the third bonding pin.
  • the third bond pin Since the main function of the third bond pin is to provide a grounding capacitor for the external power supply instead of power supply, the third bond pin that is coupled between the third bond pin and the first welding pin can be reduced in the chip layout.
  • the equivalent inductance of the rewired metal Since the main function of the third bond pin is to provide a grounding capacitor for the external power supply instead of power supply, the third bond pin that is coupled between the third bond pin and the first welding pin can be reduced in the chip layout. The equivalent inductance of the rewired metal.
  • the length of the third rewiring metal may be less than the length of the first rewiring metal and the length of the first rewiring metal.
  • the third bonding pin can be arranged below the first soldering pin, and the third rewiring metal direction is only for the longitudinal connection in the packaging layer, similar to the connection method of vias or through holes, so as to make the connection as much as possible. Reduce the length of the third rewiring metal.
  • the die in the chip device may also be provided with a first capacitor, one end of the first capacitor is grounded, and the other end of the first capacitor is connected to the first bonding pin.
  • the first capacitor is used to provide a grounding capacitor for the power supply path of the first bonding pin, and forms a first-order LC (inductance capacitor) filter network with the first rewiring metal with equivalent inductance, thereby optimizing the power supply of the first power module Power supply noise on the path.
  • the first inductor may also be provided in the die of the chip device. One end of the first inductor is connected to the first bonding pin, and the other end of the first inductor is connected to the first power module.
  • the first inductance can be realized by a metal coil on one or more metal layers in the chip.
  • the first inductor can form an LCL (Inductance Capacitance Inductance) " ⁇ " filter network with the first rewiring metal and the first capacitor, thereby further improving the noise performance on the power supply path of the first power module.
  • LCL Inductance Capacitance Inductance
  • a fourth capacitor may be provided in the die of the chip device. One end of the fourth capacitor is grounded, and the other end of the fourth capacitor is connected to the first power module.
  • the fourth capacitor is used to provide a grounding capacitor for the first power module, and forms a second-order LC filter network with the first rewiring metal, the first capacitor, and the first inductance, so as to further optimize the power supply noise on the power supply path of the first power module .
  • one or more of the second capacitor, the second inductor, and the fifth capacitor may also be provided in the die of the chip device.
  • the second capacitor, the second inductor, and the fifth capacitor can form a first-order LC filter network, an LCL " ⁇ " filter network or a second-order LC filter network with the second rewiring metal with equivalent inductance for optimization Power supply noise on the power supply path of the second power supply module.
  • the first to fifth capacitors shown in FIG. 8 can be simple passive capacitors such as metal oxide metal (MOM) capacitors and metal insulator metal (MIM) capacitors; they can be metal oxide A semiconductor (metal oxide semiconductor, MOS) capacitor; it can also be a circuit topology with capacitive characteristics, such as an electrostatic discharge (ESD) clamp circuit.
  • MOM metal oxide metal
  • MOS metal oxide semiconductor
  • ESD electrostatic discharge
  • grounding of the grounding terminals of the first capacitor to the fifth capacitor in this application means that the first to fifth capacitors are connected to one or more ground bonding pins dedicated to grounding in the chip device, and the grounding The bonding pins are then connected to the external reference ground of the chip device.
  • the first power supply module and the second power supply module may be circuit modules with similar power supply functions, such as LDO or DCDC, for supplying power to one or more circuit function modules in the chip device.
  • FIG. 9 is a schematic diagram of another chip architecture provided by an embodiment of the present application.
  • a typical module that is highly sensitive to power supply noise is a radio frequency module of the receiving channel under DLCA.
  • the first receiving radio frequency channel is used to receive the first carrier CC1
  • the second receiving radio frequency channel is used to receive the second carrier CC2.
  • the radio frequency module in the second receiving channel and the radio frequency module in the first receiving channel may consider introducing the architecture for reducing power supply noise in the embodiments of the present application.
  • the first power module LDO1 can be used to supply power to LO_Rx1 in the first radio frequency receiving channel
  • the second power module LDO2 can be used to supply power to LO_Rx2 in the second radio frequency receiving channel.
  • LDO1 can be used to supply power to LO_Rx1 in the first radio frequency receiving channel
  • LDO2 can be used to supply power to LO_LNA2 in the second radio frequency receiving channel.
  • LDO1 can be used to supply power to LO_Rx1 in the first radio frequency receiving channel
  • LDO2 can be used to supply power to Filter1 in the first radio frequency receiving channel
  • the chip architecture for reducing power supply noise in the embodiment of the present application can be introduced.
  • FIG. 10 is a schematic diagram of a capacitor provided by an embodiment of the present application.
  • the capacitor includes a switch and a passive capacitor, and the switch and the passive capacitor are coupled in series between the first terminal and the second terminal of the capacitor.
  • Passive capacitors can be MOM capacitors or MIM capacitors.
  • the switch is realized by a MOS tube, which can be a PMOS tube or an NMOS tube.
  • the gate of the MOS is used to couple with the control signal, and the control signal is used to control the on and off of the MOS switch.
  • the capacitor shown in FIG. 10 can be used as the capacitor in each embodiment of the present application.
  • the capacitance value between the first end and the second end of the capacitor is C1, which is the capacitance value of the passive capacitor itself.
  • C1 the capacitance value of the passive capacitor itself.
  • the size of the MOS tube used as the switch is usually relatively large, and a certain area is wasted, so that the capacitance density will be reduced to a certain extent.
  • FIG. 11 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • the capacitor includes a passive capacitor and a MOS tube, and the passive capacitor and the MOS tube are connected in parallel between the first terminal and the second terminal of the capacitor.
  • passive capacitors can be MOM capacitors or MIM capacitors.
  • the MOS tube can be a PMOS tube or an NMOS tube.
  • the MOS tube When the first terminal of the capacitor is low level and the second terminal is connected to high level, the MOS tube is a PMOS tube, the gate of the PMOS tube is connected to a low level through the first terminal, and the source and drain of the PMOS tube go through the second terminal Connect to high level; when the second end of the capacitor is connected to low level and the first end is connected to high level, the MOS tube is an NMOS tube, the gate of the NMOS tube is connected to a high level through the first end, and the source of the NMOS tube is connected to The drain is connected to a low level through the second terminal.
  • the capacitance value between the first terminal and the second terminal of the capacitor is C1+Cm1, which means that in addition to the capacitance value (C1) of the passive capacitor, the capacitance between the gate and the source and drain of the MOS tube is also introduced.
  • Parasitic capacitance value (Cm1). Therefore, the capacitor shown in FIG. 11 has a greater density of capacitors than the above-mentioned embodiment.
  • the gate of the MOS transistor shown in FIG. 11 is directly connected to the power supply or the ground through the first end of the capacitor, it will bring the risk of ESD. Therefore, the capacitor shown in Figure 11 has certain safety defects.
  • FIG. 12 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • the capacitor includes a first MOS transistor and a first passive capacitor, and the first passive capacitor and the first MOS transistor are connected in series between the first end and the second end of the capacitor.
  • the gate of the first MOS transistor is used to receive a control signal, and the first MOS transistor is turned on and off by the control signal, so as to realize the function of a switch.
  • the gate of the second MOS transistor is connected to the connecting end of the first passive capacitor and the first MOS transistor, and the source and drain of the second MOS transistor are commonly coupled to the first end of the capacitor.
  • the first passive capacitor can be a MOM capacitor or a MIM capacitor.
  • the MOS tube can be a PMOS tube or an NMOS tube.
  • the first MOS transistor is NMOS and the second MOS transistor is PMOS.
  • the control signal is active at high level.
  • the first MOS transistor is turned on, the second MOS transistor and the first passive capacitor are connected between the first end and the second end of the capacitor.
  • the first MOS transistor is PMOS and the second MOS transistor is NMOS.
  • the control signal is active at low level, the first MOS transistor is turned on, and the second MOS transistor and the first passive capacitor are connected between the first end and the second end of the capacitor.
  • FIG. 13 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • the embodiment shown in FIG. 13 further includes a second passive capacitor.
  • the second passive capacitor and the second MOS tube are connected in series between the first end and the second end of the capacitor.
  • the gate of the second MOS transistor is connected to the connection end of the first passive capacitor and the first MOS transistor, and the source and drain are respectively connected to the second passive capacitor and the first end of the capacitor.
  • the gate of the first MOS transistor is further connected to the connection end of the second passive capacitor and the second MOS transistor.
  • the first MOS transistor when the first terminal of the capacitor is connected to a high level and the second terminal is connected to a low level, the first MOS transistor is NMOS, the second MOS transistor is PMOS, and the control signal is active at high level, so that the first MOS transistor is conductive.
  • the gate of the second MOS is connected to ground, so the second MOS tube is also turned on, and the gate of the first MOS tube is connected to high level, and the source and drain are connected to low level.
  • the gate of the second MOS tube is connected to low level, and the source and drain are connected to high level.
  • the capacitance between the first terminal and the second terminal also has the parasitic capacitance (Cm1) between the gate and source and drain of the first MOS transistor, and the gate of the second MOS transistor.
  • Parasitic capacitance between source and drain (Cm2) The capacitance value between the first terminal and the second terminal of the capacitor is C1+C2+Cm1+Cm2.
  • the first terminal of the capacitor is connected to low level and the second terminal is connected to high level
  • the first MOS transistor is PMOS
  • the second MOS transistor is NMOS.
  • the control signal is active at low level, so that the first MOS tube is turned on, and the second MOS gate is connected to a high level. Therefore, the second MOS tube is also turned on, and the gate of the first MOS tube is connected to a low level.
  • the source and drain are connected to high level.
  • the gate of the second MOS tube is connected to high level, and the source and drain are connected to low level.
  • the capacitance value between the first terminal and the second terminal of the capacitor is also C1+C2+Cm1+Cm2.
  • the capacitance values of the first terminal and the second terminal are C1+C2+Cm1+Cm2, which further optimizes the capacitance density compared with the above-mentioned capacitor embodiment.
  • FIG. 14 is a schematic diagram of another capacitor provided by an embodiment of the present application.
  • the capacitor shown in FIG. 14 further includes a third MOS transistor.
  • the source and drain electrodes of the third MOS transistor are respectively coupled to the first end of the capacitor and the connection end of the first passive capacitor and the first MOS transistor (that is, the gate of the second MOS transistor).
  • the gate of the third MOS tube is used to receive the second control signal.
  • the second control signal is used to turn on the third MOS transistor, so that the gate of the second MOS transistor is connected to the determined potential connected to the first terminal. This can make the capacitor work in a more certain state, and can improve the stability of the capacitor when the capacitor is used more strictly.
  • the second control signal is used to turn off the third MOS transistor, so that the third MOS transistor will not affect the normal operation of each component of the capacitor.
  • the first MOS transistor is NMOS
  • the third MOS transistor is PMOS
  • the second control signal is in phase with the first control signal.
  • the first MOS transistor is PMOS
  • the third MOS transistor is NMOS
  • the second control signal is in phase with the first control signal.
  • the introduction of the third MOS transistor is only to improve the stability of the capacitor so that the potential of the gate of the second MOS transistor maintains a fixed potential when the capacitor is not working. Therefore, the introduction of the third MOS tube does not improve the capacitance density between the first end and the second section of the capacitor and the ESD resistance. Therefore, the aspect ratio of the third MOS tube can be smaller than that of the first MOS tube and the second MOS tube.

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Abstract

本申请提供了一种芯片装置，包括裸片，第一键合管脚，第二键合管脚，以及第一焊接管脚。其中，所述第一键合管脚和所述第二键合管脚设置于所述裸片的上表面，所述裸片中设置有第一电源模块和第二电源模块，所述第一电源模块与所述第一键合管脚耦合，所述第二电源模块与所述第二键合管脚耦合；所述第一焊接管脚分别与所述芯片装置的外接电源，所述第一键合管脚以及所述第二键合管脚耦合。采用上述技术方案，提升了不同的电源模块之间的隔离度，对于供电路径上的传播的噪声可以起到更好的滤波效果，改善芯片装置的电源噪声性能。

Description

一种芯片装置和无线通信装置 技术领域
本申请涉及集成电路领域，尤其涉及一种芯片装置和无线通信装置。
背景技术
随着更多的电路模块在芯片中的集成，给电路模块供电的电源扮演着十分重要的角色。除了电源的供电能力之外，电源的噪声性能也是需要考虑的一个重要指标。电源带来的噪声会通过供电网络进入到电路模块中，给电路模块的工作带来干扰。特别是芯片中高频的电路模块，对于电源带来的噪声更加敏感。常见的电路模块包括射频收发机芯片中的本地振荡器(local oscillator,LO),低噪声放大器(low noise amplifier,LNA)等等。
现有的用于提升芯片电源噪声性能的方案主要是电源本身的设计改进，但是这种改进设计往往一方面带来的收益有限，另一方面也有一定的局限性。
发明内容
本申请提供了一种芯片装置和无线通信装置，能够提升芯片的电源噪声性能。
第一方面，一种芯片装置，包括：裸片，第一键合管脚，第二键合管脚，以及第一焊接管脚；其中，所述第一键合管脚和所述第二键合管脚设置于所述裸片的上表面，所述裸片中设置有第一电源模块和第二电源模块，所述第一电源模块与所述第一键合管脚耦合，所述第二电源模块与所述第二键合管脚耦合；所述第一焊接管脚分别与所述芯片装置的外接电源，所述第一键合管脚以及所述第二键合管脚耦合。采用上述技术方案，不同的电源模块通过不同的键合管脚连接到同一个焊接管脚，既提升了不同的电源模块之间的隔离度，改善芯片装置的电源噪声性能，也节省了芯片的面积。
在一种可能的实现方式中，所述芯片装置还包括：重新布线层，所述重新布线层设置于所述裸片的上表面；所述第一焊接管脚设置于所述重新布线层的上表面；所述重新布线层中设置有第一重新布线金属和第二重新布线金属；所述第一焊接管脚通过所述第一重新布线金属与所述第一键合管脚耦合，所述第一焊接管脚通过所述第二重新布线金属与所述第二键合管脚耦合。采用上述技术方案，通过引入重新布线金属，连接键合管脚和焊接管脚的走线的长度更加的灵活可控，更容易调节供电路径中的等效电感，从而改善芯片装置的噪声性能。
在一种可能的实现方式中，所述第一重新布线金属的一端连接于第一键合管脚的上表面，所述第一重新布线金属的另一端连接于所述第一焊接管脚的下表面；所述第二重新布线金属一端连接于所述第一键合管脚的上表面，所述第二重新布线金属的另一端连接于所述第二键合管脚的上表面。采用上述技术方案，使得第一焊接管脚和第二键合管脚之间连接有第一重新布线金属和第二重新布线金属，进一步的提升了第二电源模块的在供电路径 上的等效电感，改善了噪声性能。
在一种可能的实现方式中，所述裸片中设置有第一电容，所述第一电容的第一端和第二端分别耦合于高电平和低电平。本申请通过此技术方案，进一步的提升了第一电源模块在供电路径上的对地的电容，改善了噪声性能。
在一种可能的实现方式中，所述第一电容包括第一MOS管、第二MOS管和第一无源电容；所述第一MOS管和所述第一无源电容串联耦合于所述第一电容的第一端和第二端之间，所述第一MOS管的栅极用于接收第一控制信号，所述第一控制信号用于控制第一MOS管的导通和断开；所述第二MOS管的栅极耦合于与所述第一无源电容和第一MOS管的连接端，所述第二MOS管的源极和漏极共同耦合于所述第一电容的第一端。采用上述技术方案，进一步提升了第一电容的电容密度，也提升了电容的抗ESD性能。
在一种可能的实现方式中，所述第一电容包括第一MOS管、第二MOS管、第一无源电容和第二无源电容；所述第一MOS管和所述第一无源电容串联耦合于所述第一电容的第一端和第二端之间，所述第一MOS管的栅极用于接收第一控制信号，所述第一控制信号用于控制第一MOS管的导通和断开；所述第二MOS管的栅极耦合于与所述第一无源电容和第一MOS管的连接端，所述第二MOS管和所述第二无源电容串联耦合于所述第一电容的第一端和第二端之间；所述第一MOS管的栅极耦合于与所述第二无源电容和第二MOS管的连接端。采用上述技术方案，进一步提升了第一电容的电容密度和抗ESD性能。
在一种可能的实现方式中，所述第一电容还包括第三MOS管，所述第三MOS的宽长比小于所述第一MOS管和所述第二MOS管，所述第三MOS管的源极和漏极耦合于所述第一无源电容的两端，所述第三MOS管的栅极用于接收第二控制信号，所述第二控制信号用于控制第三MOS管的导通和断开。采用上述技术方案，通过引入小尺寸的第三MOS管，可以去除缺陷电容，提高良率，同时也不会降低电容的密度，进一步的提升了芯片装置的性能。
在一种可能的实现方式中，所述芯片装置还包括第三键合管脚，所述第三键合管脚设置于所述裸片的上表面，所述重新布线层中设置有第三重新布线金属，所述第一焊接管脚通过所述第三重新布线金属与所述第三键合管脚连接；所述第一电容的一端耦合于所述第三键合管脚，所述第一电容的另一端接地；所述第三重新布线金属的长度小于第一重新布线金属的长度和第二重新布线金属的长度。采用上述技术方案，通过引入带有接地电容的第三键合管脚，可以带来额外的接地电容，通过引入更短的连接线长度，可以带来更小的与接地电容的串联电感，从而进一步提升了电源性能。
在一种可能的实现方式中，所述裸片中还设置有第一电感，所述第一电感的一端耦合于所述第一键合管脚，所述第一电感的另一端耦合于所述第一电源模块的输入端。采用上述技术方案，通过引入片上电感，在电源的供电路径中引入额外的串联的电感，可以进一步提升电源性能。
在一种可能的实现方式中，所述裸片中还设置有第二电容，所述第二电容的一端与耦合于第一电源模块的输入端，所述第二电容的另一端接地。采用上述技术方案，通过引入第二电容，在电源的供电路径中引入额外的接地电容，可以进一步提升电源噪声性能。
在一种可能的实现方式中，所述裸片中还设置有第一射频接收通道和第二射频接收通道；所述第一射频接收通道用于接收第一成员载波信号，所述第二射频接收通道用于接收第二成员载波信号，所述第一成员载波信号和所述第二成员载波信号共同构成下行载波聚合；所述第一射频接收通道和所述第二射频接收通道中设置有多个射频模块；所述第一电源模块和所述第二电源模块分别用于为所述多个射频模块中的一个或者多个供电。采用上述技术方案，通过这种提升电源噪声性能的供电架构的设计，可以引入更小的噪声，从而带来对电源噪声敏感的射频接收通道性能的改善。
在一种可能的实现方式中，所述裸片中还设置有第二电感，所述第二电感的一端耦合于所述第二键合管脚，所述第二电感的另一端耦合于所述第二电源模块的输入端；所述第一电源模块为低压差线性稳压器，所述第一电源模块用于为所述第一射频接收通道的第一本地振荡器供电；所述第二电源模块为低压差线性稳压器，所述第二电源模块用于为所述第二射频接收通道的第二本地振荡器供电。采用上述技术方案，通过带有片上电感的独立低压差线性稳压器的设计，可以进一步的提升电源噪声性能，同时采用给本地振荡器分离供电的方式，也可以降低噪声串扰，从而进一步改善本地振荡器的性能。
在一种可能的实现方式中，所述第一电源模块为低压差线性稳压器，所述第一电源模块为低压差线性稳压器，所述第一电源模块用于为所述第一射频接收通道的第一本地振荡器供电；所述第二电源模块为低压差线性稳压器，所述第二电源模块用于为所述第一射频接收通道的低通滤波器供电。采用上述技术方案，通过低通滤波器和本地振荡器分别供电的方式，进一步的提升电源噪声性能。
第二方面，本申请提出了一种无线通信装置，包括基带处理芯片和在任何一种可能的实现方式中的芯片装置，所述芯片装置和所述基带处理芯片耦合。
在一种可能的实现方式中，无线通信装置还包括：印刷电路板和天线，所述基带处理芯片和所述芯片装置固定于所述印刷电路板；所述天线用于为所述芯片装置提供射频信号。
第三方面，本申请提出了一种集成电路，所述集成电路中设置有电容模块，所述电容模块包括第一端和第二端，所述电容模块通过所述第一端和所述第二端连接于外部电路；所述电容模块包括第一MOS管、第二MOS管和第一无源电容；所述第一MOS管和所述第一无源电容串联耦合于所述电容模块的第一端和第二端之间，所述第一MOS管用于接收控制信号，所述控制信号用于控制第一MOS管的导通和断开；所述第二MOS管的栅极耦合于与所述第一无源电容和第一MOS管的连接端，所述第二MOS管的源极和漏极共同耦合于所述电容模块的第一端。采用上述技术方案，所述电容模块具有更高的电容密度和 抗ESD性能。
第四方面，本申请提出了一种集成电路，所述集成电路中设置有电容模块，所述电容模块包括第一端和第二端，所述电容模块通过所述第一端和所述第二端连接于外部电路；所述电容模块包括第一MOS管、第二MOS管、第一无源电容和第二无源电容；所述第一MOS管和所述第一无源电容串联耦合于所述电容模块的第一端和第二端之间，所述第一MOS管用于接收第一控制信号，所述第一控制信号用于控制第一MOS管的导通和断开；所述第二MOS管的栅极耦合于与所述第一无源电容和第一MOS管的连接端，所述第二MOS管和所述第二无源电容串联耦合于所述电容模块的第一端和第二端之间。采用上述技术方案，进一步提升了电容模块的电容密度和抗ESD性能。
应理解，本申请提供的方案中，无线通信装置可以是无线通信设备，也可以是无线通信设备中的部分器件，例如芯片，芯片组合，或包含芯片的模组等集成电路产品，这些集成电路产品可以包括本申请实施例提供的芯片装置。
具体地，无线通信设备可以是诸如智能手机这样的终端，也可以是诸如基站这样的无线接入网设备。从功能上来说，用于无线通信的芯片可分为基带芯片和射频芯片。基带芯片也称为调制解调器(modem)或基带处理芯片。射频芯片也称为收发器芯片，射频收发机(transceiver)或射频处理芯片。因此，该无线通信装置可以是单个芯片，也可以是多个芯片的组合，例如***芯片，芯片平台或芯片套片。
***芯片也称为片上***(system on a chip，SoC)，或简称为SoC芯片，可以理解为将多个芯片封装在一起，组成一个更大的芯片。例如基带芯片就可以进一步封装在SoC芯片中。芯片平台或芯片套片可以理解为需要配套使用的多个芯片，这多个芯片往往是独立封装，但芯片工作时需要相互配合，共同完成无线通信功能。例如，基带芯片(或集成了基带芯片的SoC芯片)和射频芯片通常是独立封装的，但需要配套使用。
附图说明
图1为本申请实施例提供的一种无线通信***的结构示意图；
图2为本申请实施例提供的一种无线通信***的载波配置示意图；
图3为本申请实施例提供的一种无线通信设备的结构示意图；
图4本申请实施例提供的一种射频芯片示意图；
图5为本申请实施例提供的一种芯片装置侧视图示意图；
图6为本申请实施例提供的一种芯片装置示意图；
图7为本申请实施例提供的另一种芯片装置示意图；
图8是本申请实施例提供的一种芯片架构示意图；
图9是本申请实施例提供的另一种芯片架构示意图；
图10是本申请实施例提供的一种电容示意图；
图11是本申请实施例提供的另一种电容示意图；
图12是本申请实施例提供的另一种电容示意图；
图13是本申请实施例提供的另一种电容示意图；
图14是本申请实施例提供的另一种电容示意图。
具体实施方式
下面结合附图并举实施例，对本申请提供的技术方案作进一步说明。应理解，本申请实施例中提供的***结构和业务场景主要是为了解释本申请的技术方案的一些可能的实施方式，不应被解读为对本申请的技术方案的唯一性限定。本领域普通技术人员可以知晓，随着***的演进，以及更新的业务场景的出现，本申请提供的技术方案对于相同或类似的技术问题仍然可以适用。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
无线通信***中，设备可分为提供无线网络服务的设备和使用无线网络服务的设备。提供无线网络服务的设备是指那些组成无线通信网络的设备，可简称为网络设备(network equipment)，或网络单元(network element)。网络设备通常归属于运营商或基础设施提供商，并由这些厂商负责运营或维护。网络设备还可进一步分为无线接入网(radio access network，RAN)设备以及核心网(core network，CN)设备。典型的RAN设备包括基站(base station，BS)。
应理解，基站有时也可以被称为无线接入点(access point，AP)，或发送接收点(transmission reception point，TRP)。具体地，基站可以是5G新无线(new radio，NR)***中的通用节点B(generation Node B，gNB)，4G长期演进(long term evolution，LTE)***的演进节点B(evolutional Node B，eNB)。根据基站的物理形态或发射功率的不同，基站可被分为宏基站(macro base station)或微基站(micro base station)。微基站有时也被称为小基站或小小区(small cell)。
使用无线网络服务的设备，可简称为终端(terminal)。终端能够与网络设备建立连接，并基于网络设备的服务为用户提供具体的无线通信业务。应理解，由于终端与用户的关系更加紧密，有时也被称为用户设备(user equipment，UE)，或订户单元(subscriber unit，SU)。此外，相对于通常在固定地点放置的基站，终端往往随着用户一起移动，有时也被称为移动台(mobile station，MS)。此外，有些网络设备，例如中继节点(relay node，RN)或者无线路由器等，由于具备UE身份，或者归属于用户，有时也可被认为是终端。
具体地，终端可以是移动电话(mobile phone)，平板电脑(tablet computer)，膝上型电脑(laptop computer)，可穿戴设备(比如智能手表，智能手环，智能头盔，智能眼镜)，以及其他具备无线接入能力的设备，如智能汽车，各种物联网(internet of thing，IOT)设备，包括各种智能家居设备(比如智能电表和智能家电)以及智能城市设备(比如安防或监控设备，智能道路交通设施)等。
为了便于表述，本申请中将以基站和终端为例，详细说明本申请实施例的技术方案。
图1为本申请实施例提供的一种无线通信***的结构示意图。如图1所示，无线通信***包括终端和基站。按照传输方向的不同，从终端到基站的传输链路记为上行链路(uplink，UL)，从基站到终端的传输链路记为下行链路(downlink，DL)。相类似地，上行链路中的数据传输可简记为上行数据传输或上行传输，下行链路中的数据传输可简记为下行数据传输或下行传输。
该无线通信***中，基站可通过集成或外接的天线设备，为特定地理区域提供通信覆盖。位于基站的通信覆盖范围内的一个或多个终端，均可以接入基站。一个基站可以管理 一个或多个小区(cell)。每个小区具有一个身份证明(identification)，该身份证明也被称为小区标识(cell identity，cell ID)。从无线资源的角度看，一个小区是下行无线资源，以及与其配对的上行无线资源(非必需)的组合。
应理解，该无线通信***可以遵从第三代合作伙伴计划(third generation partnership project，3GPP)的无线通信标准，也可以遵从其他无线通信标准，例如电气电子工程师学会(Institute of Electrical and Electronics Engineers，IEEE)的802系列(如802.11，802.15，或者802.20)的无线通信标准。图1中虽然仅示出了一个基站和一个终端，该无线通信***也可包括其他数目的终端和基站。此外，该无线通信***还可包括其他的网络设备，比如核心网设备。
终端和基站应知晓该无线通信***预定义的配置，包括***支持的无线电接入技术(radio access technology，RAT)以及***规定的无线资源配置等，比如无线电的频段和载波的基本配置。载波是符合***规定的一段频率范围。这段频率范围可由载波的中心频率(记为载频)和载波的带宽共同确定。这些***预定义的配置可作为无线通信***的标准协议的一部分,或者通过终端和基站间的交互确定。相关标准协议的内容，可能会预先存储在终端和基站的存储器中，或者体现为终端和基站的硬件电路或软件代码。
该无线通信***中，终端和基站支持一种或多种相同的RAT，例如5G NR，4G LTE，或未来演进***的RAT。具体地，终端和基站采用相同的空口参数、编码方案和调制方案等，并基于***规定的无线资源相互通信。
图2为本申请实施例提供的一种无线通信***的载波配置示意图。该无线通信***中，基站为终端配置了两个载波集合，分别记为第一载波集合和第二载波集合。其中，第一载波集合可以用于下行载波聚合(downlink carrier aggregation，DLCA)，第二载波集合可以用于上行载波聚合(uplink carrier aggregation，ULCA)。这两个载波集合所包括的载波的频率范围可以不同比如在FDD(frequency duplex division:频分双工)模式下的终端；这两个载波集合所包括的载波的频率范围可以相同比如在TDD(time duplex division，频分双工)模式下的终端。
如图2所示，第一载波集合包括6个成员载波(component carrier，CC)，依次记为CC1至CC6。第二载波集合包括4个成员载波，包括CC1至CC4。应理解，第一载波集合和第二载波集合所包括的CC数目仅为示意目的，本申请实施例中，第一载波集合和第二载波集合中也可以包括其他数目的CC。这些CC在频域中既可以是连续的，也可以是非连续的。不同的CC可以在相同的频带，可对应带内载波聚合(intra-band CA)。不同的CC也可以在不同的频带，可对应带间载波聚合(inter-band CA)。
应理解，本申请中，一个成员载波可对应终端的一个服务小区(serving cell)。在中文语境下，成员载波有时也被翻译为分量载波，可简称为载波，服务小区可简称为小区。如非特别说明，在本申请中，术语“载波”、“分量载波”、“聚合载波”、“聚合分量载波”、“服务小区”、“小区”、“PCell或SCell中的一种”、“PCC或SCC中的一种”、“聚合载波”可以互换使用。
图3为本申请实施例提供的一种无线通信设备的结构示意图。该无线通信设备可以是本申请实施例中的终端或者基站。如图2所示，该无线通信设备可包括应用子***，内存 (memory)，大容量存储器(massive storge)，基带子***，射频集成电路(radio frequency intergreted circuit，RFIC)，射频前端(radio frequency front end，RFFE)器件，以及天线(antenna，ANT)，这些器件可以通过各种互联总线或其他电连接方式耦合。
图3中，ANT_1表示第一天线，ANT_N表示第N天线，N为大于1的正整数。Tx表示发送路径，Rx表示接收路径，不同的数字表示不同的路径。FBRx表示反馈接收路径，PRx表示主接收路径，DRx表示分集接收路径。HB表示高频，LB表示低频，两者是指频率的相对高低。BB表示基带。应理解，图3中的标记和组件仅为示意目的，仅作为一种可能的实现方式，本申请实施例还包括其他的实现方式。
射频集成电路可以进一步分为射频接收通道(RF receive path)和射频发射通道(RF transmit path)。射频接收通道可通过天线接收射频信号，对该射频信号进行处理(如放大、滤波和下变频)以得到基带信号，并传递给基带子***。射频发送通道可接收来自基带子***的基带信号，对基带信号进行射频处理(如上变频、放大和滤波)以得到射频信号，并最终通过天线将该射频信号辐射到空间中。具体地，射频子***可包括天线开关，天线调谐器，低噪声放大器(low noise amplifier，LNA)，功率放大器(power amplifier，PA)，混频器(mixer)，本地振荡器(local oscillator，LO)、滤波器(filter)等电子器件，这些电子器件可以根据需要集成到一个或多个芯片中。天线有时也可以认为是射频子***的一部分。
基带子***可以从基带信号中提取有用的信息或数据比特，或者将信息或数据比特转换为待发送的基带信号。这些信息或数据比特可以是表示语音、文本、视频等用户数据或控制信息的数据。例如，基带子***可以实现诸如调制和解调，编码和解码等信号处理操作。对于不同的无线接入技术，例如5G NR和4G LTE，往往具有不完全相同的基带信号处理操作。因此，为了支持多种移动通信模式的融合，基带子***可同时包括多个处理核心，或者多个HAC。基带子***一般集成到一个或者多个芯片中，集成基带子***的芯片一般称为基带处理器芯片(baseband intergreted circuit,BBIC)。
此外，由于射频信号是模拟信号，基带子***处理的信号主要是数字信号，无线通信设备中还需要有模数转换器件。模数转换器件包括将模拟信号转换为数字信号的模数转换器(analog to digital converter，ADC)，以及将数字信号转换为模拟信号的数模转换器(digital to analog converter，DAC)。本申请实施例中，模数转换器件可以设置在基带子***中，也可以设置在射频子***中。
其中，应用子***可作为无线通信设备的主控制***或主计算***，用于运行主操作***和应用程序，管理整个无线通信设备的软硬件资源，并可为用户提供用户操作界面。应用子***可包括一个或多个处理核心。此外，应用子***中也可包括与其他子***(例如基带子***)相关的驱动软件。基带子***也可包括以及一个或多个处理核心，以及硬件加速器(hardware accelerator，HAC)和缓存等。
本申请实施例中，射频子***可包括独立的天线，独立的射频前端(RF front end，RFFE)器件，以及独立的射频芯片。射频芯片有时也被称为接收机(receiver)、发射机(transmitter)或收发机(transceiver)。天线、射频前端器件和射频处理芯片都可以单独制造和销售。当然，射频子***也可以基于功耗和性能的需求，采用不同的器件或者不同的集成方式。例如，将属于射频前端的部分器件集成在射频芯片中，甚至将天线和射频前端器件都集成射 频芯片中，该射频芯片也可以称为射频天线模组或天线模组。
图4本申请实施例提供的一种射频芯片示意图。应当理解，虽然图4仅有两条接收通道和一条发射通道，但是本实施例可以不止于此，射频集成电路可以包括两条或者两条以上的发射通道和接收通道以及其他的通道数量。射频接收通道一般用于将接收RF的信号处理为中频信号。射频发送通道一般用于将中频信号处理为发送的射频信号。如图4所示，射频芯片(RFIC)包括第一射频接收通道、第二射频接收通道和第一射频发射通道。第一射频接收通道包括第一低噪声放大器(low noise amplifier 1,LNA1)、第一混频器(mixer 1,MIX1)、第一接收本地振荡器(LO_Rx1)、第一滤波器(Filter1)、第一模拟数字转换器(analog to digital converter 1,ADC1)。第二射频接收通道包括第二低噪声放大器(low noise amplifier 2,LNA2)、第二混频器(mixer 2,MIX2)、第二接收本地振荡器(LO_Rx2)、第二滤波器(Filter2)、第二模拟数字转换器(analog to digital converter 2,ADC2)。射频接收通道中的低噪声放大器将接收到的射频信号进行放大，混频器将低噪声放大器放大后的射频信号与LO_RX提供的本振信号进行混频，混频后得到中频信号。中频信号经过滤波器后提供给ADC。图4所示的第一射频发送通道包括数字模拟转换器(digital to analog converter,DAC)、第三滤波器(Filter3)、第三混频器(mixer 3,MIX3)、发射本地振荡器(LO_Tx)和功率放大器(power amplifier,PA)。射频发射通道中的DAC将数字信号转换为模拟信号后发送给滤波器，滤波器将信号进行滤波处理，混频器将滤波器后的模拟信号和本地振荡器提供的信号进行混频搬移为射频信号，PA再对射频信号进行功率放大。PA和LNA也可以在射频通道之外，作为射频芯片之外单独的射频前端芯片器件。
对于射频接收通道来说，信号噪声比(signal to noise ratio,S/N)是一个重要指标。射频接收通道中的射频模块都需要供电模块提供电源才能工作。供电模块引入的电源噪声是影响射频接收通道S/N的一个重要因素。电源噪声主要有两个主要来源，第一是射频芯片外部电源本身的电源噪声，比如，射频芯片的外部电源非理想特性带来的高频噪声会通过供电模块传导给供电的射频模块。
第二是两个射频模块之间的串扰。一般来说，同一个供电模块会给多个射频模块同时供电。当两个射频通道同时工作时，两个射频通道之间的射频信号会通过同一个供电模块提供的供电路径耦合串扰。
目前采用的提升电源噪声的措施是优化电源模块本身电路结构的设计，提升电源本身信噪比。但是这样对外部电源的要求过高，提升了成本，另外对于同一供电路径上的噪声串扰的问题也无法缓解。
图5为本申请实施例提供的一种芯片装置侧视图示意图。如图5所示，芯片包括裸片(Die)和封装层(Package layer)。Die包括衬底以及位于衬底之上的多晶硅(poly)层，在衬底和多晶硅中设置有芯片的有源区，也就是实现芯片晶体管的区域。互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)芯片为例，有源区上会设置有正沟道金属氧化物半导体(positive channel metal oxide semiconductor,PMOS)和负沟道金属氧化物半导体(negative channel metal oxide semiconductor,NMOS)管的源极、漏极和栅极。在poly层之上在Die中设置有互联金属层。Die的互联金属层主要给Die上集成的电路元器件提供互联金属线。互联金属线可以包括彼此连接的位于各个金属层上的金属线或者金属 面以及各个金属层之间的过孔。
进一步的，在Die之上可以设置有封装层。封装层用于对Die进行封装，将Die封装成最终的芯片产品形式。如图5所示的封装层可以为重新布线层。重新布线层设置于所述裸片的上表面，重新布线层可以包括键合管脚(Bond pad或者Bonding pad)和重新布线层金属(RDL metal，redistribution layer metal)。键合管脚设置于Die的上表面。键合管脚的上表面裸露设置，以实现Die对外连接。应理解，不同的工艺流程得到的键合管脚的高度可以不同，比如键合管脚的上表面可以高于裸片的介质层而直接裸露，或者键合管脚的上表面也可以平行或者低于裸片的介质层，通过开窗的工艺裸露出来。芯片的输入端口的管脚、输出端口的管脚、接地的管脚、电源的管脚以及测试管脚都会在Die的上表面形成相应的键合管脚。
键合管脚之上可以设置有RDL metal。RDL metal之上设置有焊接管脚(Solder pad或者Soldering pad)。Solder pad设置于RDL metal的上表面，用于提供芯片封装级的焊点，以实现芯片与PCB板或者其他的封装基板的进一步固定连接。Solder pad根据其大小和工艺可以分为焊球(solder ball)或者焊点突起(solder bump)，或者具有类似功能的焊点。重新布线层中可以设置有不同的重新布线金属以提供不同的焊接管脚与焊接管脚之间的电连接。RDL metal设置于Bond pad与Solder pad之间，一端连接于Bond pad的上表面，另一端连接于Solder pad的下表面。
图6为本申请实施例提供的一种芯片装置示意图。如图6所示，键合管脚为方形,焊接管脚为圆形。图6仅作为示意图，本申请实施例中的键合管脚与焊接管脚的形状可以不限于此，可以有更多的选择。如图6所示，一般来说，由于焊接管脚用于芯片与外部封装基板或者PCB板的连接固定，需要承受更大的硬力，所以具有比键合管脚更大的面积。不同的焊接管脚和键合管脚之间通过不同的重新布线金属实现连接。
如图6所示的芯片结构设置有第一键合管脚、第二键合管脚和第一焊接管脚。第一键合管脚和所述第二键合管脚设置于裸片的上表面，所述第一焊接管脚设置在所述重新布线层的上表面。重新布线层中设置有多条重新布线金属用于实现键合管脚和焊接管脚的连接。裸片中设置有第一电源模块和第二电源模块，所述第一电源模块与所述第一键合管脚耦合，所述第二电源模块与所述第二键合管脚耦合。
所述第一焊接管脚与所述芯片装置的外接电源耦合，用于为所述芯片装置提供电源。应理解，外接电源可以包括但是不限于电源芯片、电池、USB电源以及具有类似能够提供电压或者电流能力的供电装置或者模块。应理解，外接电源可以是集成了多个供电模块，比如低压差稳压器(low-dropout regulator，LDO)或者直流-直流转换器(direct current to direct current converter，DCDC)的***级电源，也可以是LDO或者DCDC等单独的模块级电源。
可选的，外接电源可以跟所述芯片装置焊接于同一个封装基板或者PCB板，外接电源的供电管脚可以通过封装基板或者PCB板的走线连接到第一焊接管脚。
可选的，外接电源也可以采用塑封(molding)的方式跟所述芯片装置封装在一起，外接电源的供电管脚可以通过硅过孔(through silicon via,TSV)或者介质过孔(through Dielectric via,TDV)等专门的工艺生成的通孔连接到第一焊接管脚。
所述封装层中设置有第一重新布线金属和第二重新布线金属；所述第一焊接管脚通过 所述第一重新布线金属与所述第一键合管脚连接，所述第一焊接管脚通过所述第二重新布线金属与所述第二键合管脚连接。
如图6所示，第一重新布线金属的两端可以分别连接于第一键合管脚和第一焊接管脚，第二重新布线金属的两端可以分别连接于第二键合管脚和第一焊接管脚。在具体的芯片布线结构上，第一重新布线金属的一端位于所述第一键合管脚的上表面，所述第一重新布线金属的另一端位于所述第一焊接管脚的下表面；所述第二重新布线金属一端位于所述第一键合管脚的上表面，另一端位于所述第一焊接管脚的下表面。
采用不同的键合管脚分别连接不同的电源模块，然后不同的键合管脚由不同的重新布线金属通过焊接管脚连接到外部电源，具有更好的电源噪声性能。相比于在芯片内部的走线供电结构，重新布线金属的走线具有更少的裸片内部走线带来的其他模块的噪声干扰，以及衬底噪声的干扰，因此会带来更好的供电性能。
图7为本申请实施例提供的另一种芯片装置示意图。在图6实施例的基础上，本实施例中第二重新布线金属可以有另外的连接方式。
如图7所示，第一重新布线金属的两端分别连接于第一键合管脚和第一焊接管脚，第二重新布线金属的两端分别连接于第二键合管脚和第一键合管脚。
在具体的芯片布线结构上，第一重新布线金属的一端位于所述第一键合管脚的上表面，所述第一重新布线金属的另一端位于所述第一焊接管脚的下表面；所述第二重新布线金属一端位于所述第一键合管脚的上表面，另一端位于所述第二键合管脚的上表面。通过第二重新布线金属与第一键合管脚和第二键合管脚之间的连接，也同样可以实现第一焊接管脚与第二键合管脚的连接。跟图六的连接方式相比，图7中第二重新布线金属的这种间接的连接方式，可以充分的利用第一键合管脚和第二键合管脚之间的在重新布线层空间走线距离，这样第二键合管脚与第一焊接管脚之间的等效走线的长度更长，带来更大的等效电感，从而可以在供电路径上带来更好的滤波效果，从而可以更好的改善芯片装置的电源噪声性能。
图6和图7中这种芯片结构的设置，通过引入不同的重新布线金属的连接方式，可以将不同的键合管脚连接到同一电源焊接管脚，既提升了不同的电源模块之间的隔离度，也提升了不同的电源模块的在供电路径上的等效电感。这可以在供电路径上起到更好的滤波效果，既可以对供电路径上传输的电源本身的噪声进行滤波，也可以对供电路径上模块之间串扰带来的噪声进行滤波，从而改善芯片装置的电源噪声性能。
应理解，图6和图7所示的芯片结构为晶圆级芯片封装(wafer level chip scale package，WLCSP)。本申请中的实施例中的芯片结构也可以不限于此，本申请中的芯片结构也可以是基于现有的键合线(wirebond)或者铜柱(copper pillar)等其他类似形式的芯片封装工艺结构。例如，当芯片基于wirebond的封装工艺时，芯片的Bond pad会通过wire bond连接到芯片的Solder pad上。当芯片基于copper pillar等封装结构时，芯片的Bond pad会通过类似的铜柱连接到Solder pad。
例如，当本申请实施例基于wirebond的芯片封装时，芯片结构可以包括第一键合管脚、第二键合管脚、第一键合线、第二键合线、第一焊接管脚。第一焊接管脚可以通过所述第一键合线与所述第一键合管脚连接，第一焊接管脚可以通过所述第二键合线与所述第二键合管脚连接。第一电源模块与第一键合管脚耦合，第二电源模块与第二键合管脚耦合。第 一焊接管脚与外接电源耦合。通过引入不同的键合线，可以将不同的键合管脚连接到同一电源焊接管脚，提升了不同电源键合管脚连接的电源模块之间的隔离度，这对于供电路径上传播的噪声也可以起到更好的滤波效果，从而改善芯片装置的电源噪声性能。
重新布线金属，键合线以及铜柱等类似的封装形式在不同的应用场景体现不同的优势。在对于小芯片电源性能要求高的场景下，重新布线金属更有优势；对于厚度要求更高的多芯片封装的场景，铜柱封装更具备优势；而对于大芯片，成本要求更高，采用键合线的封装更具有优势。
图8是本申请实施例提供的一种芯片架构示意图。在上述实施例的基础上，如图8所示，芯片装置还可以设置有第三键合管脚。第三键合管脚通过第三重新布线金属连接于第一焊接管脚。芯片装置的裸片中可以设置有第三电容，第三电容一端接地，另一端与第三键合管脚耦合。通过跟设置有接地第三电容的第三键合管脚耦合，与外接电源耦合的第一焊接管脚上的电源噪声性能会得到进一步的改善，从而进一步提升整体芯片装置的性能。由于第三键合管脚的主要功能是为外接电源提供接地的电容而不是用于供电，因此在芯片布局上可以减少耦合于第三键合管脚与第一焊接管脚之间的第三重新布线金属的等效电感。
优选的，第三重新布线金属的长度可以小于第一重新布线金属的长度和第一重新布线金属的长度。
优选的，第三键合管脚可以设置于第一焊接管脚的下方，第三重新布线金属走向仅为在封装层的纵向连接，类似于过孔或者通孔的连接方式，从而尽可能的减少第三重新布线金属的长度。
进一步的，芯片装置中的裸片中还可以设置有第一电容，第一电容的一端接地，第一电容的另一端与第一键合管脚连接。第一电容用于为第一键合管脚的供电路径提供接地的电容，与具有等效电感的第一重新布线金属构成一阶LC(电感电容)滤波器网络，从而优化第一电源模块供电路径上的电源噪声。
进一步的，芯片装置的裸片中还可以设置有第一电感。第一电感的一端与第一键合管脚连接，第一电感的另一端连接于第一电源模块。第一电感可以由芯片中一层或者多层金属层上的金属线圈实现。第一电感，可以与第一重新布线金属、第一电容构成LCL(电感电容电感)“π”型的滤波器网络，从而进一步的提升第一电源模块供电路径上噪声性能。
进一步的，芯片装置的裸片中还可以设置有第四电容。第四电容的一端接地，第四电容的另一端连接于第一电源模块。第四电容用于为第一电源模块提供接地的电容，与第一重新布线金属、第一电容、第一电感构成二阶LC滤波器网络，从而可以进一步优化第一电源模块供电路径上电源噪声。
类似的，位于第二键合管脚与第二电源模块之间，在芯片装置的裸片中也可以设置第二电容、第二电感、第五电容中的一个或者多个组件。第二电容、第二电感、第五电容可以与具有等效电感的第二重新布线金属构成一阶LC滤波器网络，LCL“π”型滤波器网络或者二阶LC滤波器网络，用于优化第二电源模块供电路径上的电源噪声。
图8所示的第一电容到第五电容，可以是简单无源电容比如金属氧化物金属(metal oxide metal，MOM)电容、金属绝缘金属(metal insulator metal,MIM)电容；可以是金属氧 化物半导体(metal oxide semiconductor，MOS)电容；也可以是具有电容特性的电路拓扑，比如静电放电(Electrostatic discharge，ESD)钳位(clamp)电路。
应理解，本申请中的第一电容到第五电容的接地端接地，是指第一到第五电容连接到芯片装置中专门用于接地的一个或者多个接地键合管脚，所述接地键合管脚再连接到芯片装置的外部参考地。
第一电源模块和第二电源模块可以是LDO或者DCDC等具有类似供电功能的电路模块，用于为芯片装置中一个或者多个电路功能模块供电。
应理解，本申请提出的用于提升电源噪声的架构，虽然可以提升芯片装置电源的性能，但是需要付出额外的键合管脚、重新布线金属、片上电容或者片上电感，这会给芯片装置带来额外的面积和成本。因此定位出芯片装置中对于电源噪声的敏感度高的电路模块使用本申请提供的用于降低电源噪声的结构，也是需要考虑的因素之一。
图9是本申请实施例提供的另一种芯片架构示意图。如图9所示，在上述实施例的基础上，对于电源噪声敏感度高的典型模块是DLCA下接收通道的射频模块。如图9所示，第一接收射频通道用于接收第一载波CC1，第二接收射频通道用于接收第二载波CC2。比如，第二接收通道中的射频模块与第一接收通道中的射频模块可以考虑引入本申请实施例中降低电源噪声的架构。
可选的，如图9所示,第一电源模块LDO1可以用于为第一射频接收通道中的LO_Rx1供电，第二电源模块LDO2可以用于为第二射频接收通道中的LO_Rx2供电。
可选的，LDO1可以用于为第一射频接收通道中的LO_Rx1供电，LDO2用于为第二射频接收通道中的LO_LNA2供电。
可选的，LDO1可以用于为第一射频接收通道中的LO_Rx1供电，LDO2用于为第一射频接收通道中的Filter1供电。
类似的，混频器1与LO_RX2之间,LNA1与LNA2之间都可以引入本申请实施例中降低电源噪声的芯片架构。
图10是本申请实施例提供的一种电容示意图。如图10所示，电容包括开关和无源电容，所述开关和无源电容串联耦合于电容的第一端和第二端之间。无源电容可以是MOM电容，也可以是MIM电容。开关由MOS管来实现，可以是PMOS管，也可以是NMOS管。MOS的栅极用于跟控制信号耦合，控制信号用于控制MOS管开关的导通和断开。图10所示的电容可以作为本申请各个实施例中的电容使用。理想情况下，开关导通时，电容第一端和第二端之间的电容值为C1，也就是本身无源电容的电容值。图10所示的电容结构，为了降低导通电阻，作为开关的MOS管的尺寸通常会比较大，浪费一定的面积，从而使得电容密度会有一定的下降。
图11是本申请实施例提供的另一种电容示意图。如图11所示，电容包括无源电容和MOS管，所述无源电容和MOS管并联于电容的第一端和第二端之间。类似的，无源电容可以是MOM电容，也可以是MIM电容。MOS管可以是PMOS管，也可以是NMOS管。当电容的第一端低电平，第二端接高电平时，MOS管为PMOS管，PMOS管的栅极通过第一端接低电平，PMOS管的源极和漏极通过第二端接高电平；当电容的第二端接低电平， 第一端接高电平时，MOS管为NMOS管，NMOS管的栅极通过第一端接高电平，NMOS管的源极和漏极通过第二端接低电平。
电容第一端和第二端之间的电容值为C1+Cm1，也就是说除了引入无源电容的容值(C1)之外，还引入了MOS管的栅极与源漏极之间的寄生电容值(Cm1)。因此图11所示的电容跟上述实施例相比，电容的密度更大。但是由于图11所示的MOS管的栅极会通过电容的第一端直接连接到电源或者地，因此会带来ESD的风险。因此图11所示的电容存在一定的安全缺陷。
图12是本申请实施例提供的另一种电容示意图。如图12所示，电容包括第一MOS管和第一无源电容，所述第一无源电容和第一MOS管串联于电容的第一端和第二端之间。第一MOS管的栅极用于接收控制信号，通过控制信号来实现第一MOS管的导通和断开，以实现开关的功能。第二MOS管的栅极连接于所述第一无源电容和第一MOS管的连接端，第二MOS管的源级和漏极共同耦合于电容的第一端。
类似的，第一无源电容可以是MOM电容，也可以是MIM电容。
MOS管可以是PMOS管，也可以是NMOS管。当电容的第一端接高电平，第二端接低电平时，第一MOS管为NMOS，第二MOS管为PMOS。控制信号为高电平有效，第一MOS管导通时，将第二MOS管和第一无源电容接到电容的第一端和第二端之间。
类似的，当电容的第一端接低电平，第二端接高电平时，第一MOS管为PMOS，第二MOS管为NMOS。此时控制信号为低电平有效，第一MOS管导通，将第二MOS管和第一无源电容接到电容的第一端和第二端之间。
如图12所示的实施例中的这种架构，第一MOS管导通时，第一端和第二端的电容值为C1+Cm2,而且MOS管的栅极不会直接连接到电源或者地，因此相比于上述的图11和图10中的电容实施例，优化了电容密度和抗ESD的性能。
图13是本申请实施例提供的另一种电容示意图。在上述实施例的基础上，图13所示的实施例又进一步包括第二无源电容。第二无源电容跟第二MOS管串联于电容的第一端和第二端之间。第二MOS管的栅极连接于所述第一无源电容和第一MOS管的连接端，源极和漏极分别连接第二无源电容和电容的第一端。第一MOS管的栅极也进一步的连接于第二无源电容和第二MOS管的连接端。
具体的，当电容的第一端接高电平，第二端接低电平时，第一MOS管为NMOS，第二MOS管为PMOS,控制信号为高电平有效，使得第一MOS管导通，实现了第二MOS栅极接地，因此第二MOS管也导通，同时第一MOS管的栅极接高电平，源漏极接低电平。第二MOS管的栅极接低电平，源漏极接高电平。因此第一端和第二端之间的电容除了并联的C1和C2之外，还有第一MOS管的栅极和源漏极之间的寄生电容(Cm1)，第二MOS管的栅极和源漏极之间的寄生电容(Cm2)。电容的第一端和第二端之间的电容值为C1+C2+Cm1+Cm2。
类似的，当电容的第一端接低电平，第二端接高电平时，当第一MOS管为PMOS，第二MOS管为NMOS。控制信号为低电平有效，使得第一MOS管导通，实现了第二MOS栅极接高电平，因此第二MOS管也导通，同时第一MOS管的栅极接低电平，源漏极接高电平。第二MOS管的栅极接高电平，源漏极接低电平。电容的第一端和第二端之间的电 容值也同样为C1+C2+Cm1+Cm2。
如图12所示的实施例中的这种架构，第一端和第二端的电容值为C1+C2+Cm1+Cm2,相比于上述的电容实施例，进一步的优化了电容密度。
同时，当开关断开时，此电容的第一端到第二端之间多个电容的串联,也就是C1到Cm2到C2的串联，也降低了单个电容上的分压，从而也提升了抗ESD的能力。
图14是本申请实施例提供的另一种电容示意图。在上述实施例的基础上，如图14所示的电容还进一步包括一个第三MOS管。第三MOS管源漏两极分别耦合于所述电容的第一端和第一无源电容与第一MOS管的连接端(也就是第二MOS管的栅极)。第三MOS管的栅极用于接收第二控制信号。
当第一MOS管断开时，第二控制信号用于导通第三MOS管，使得第二MOS管的栅极连接到确定的第一端所连接的电位。这样可以使得电容工作在更加确定的状态，在对电容使用更严格的场合，可以提升电容的稳定性。
当第一MOS管导通时，第二控制信号用于断开第三MOS管，使得第三MOS管不会影响电容各个部件的正常工作。
具体的，当电容第一端接高电平，第二端接低电平时，第一MOS管为NMOS，第三MOS管为PMOS,第二控制信号与第一控制信号同相。
当电容第一端接低电平，第二端接高电平时，第一MOS管为PMOS，第三MOS管为NMOS,第二控制信号与第一控制信号同相。
第三MOS管的引入仅仅是为了提升电容的稳定性，使得第二MOS管栅极的电位在电容不工作时保持固定电位。因此第三MOS管引入并不会改善电容第一端和第二段之间的电容密度和抗ESD的能力，因此第三MOS的宽长比可以小于第一MOS管和第二MOS管。
应理解，在本申请中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。本申请提到的“耦合”一词，用于表达不同组件之间的互通或互相作用，可以包括直接相连或通过其他组件间接相连。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种芯片装置，其特征在于，包括：
    裸片，第一键合管脚，第二键合管脚，以及第一焊接管脚；
    其中，所述第一键合管脚和所述第二键合管脚设置于所述裸片的上表面，所述裸片中设置有第一电源模块和第二电源模块，所述第一电源模块与所述第一键合管脚耦合，所述第二电源模块与所述第二键合管脚耦合；
    所述第一焊接管脚分别与所述芯片装置的外接电源，所述第一键合管脚以及所述第二键合管脚耦合。
  2. 如权利要求1所述的芯片装置，其特征在于，还包括：
    重新布线层，所述重新布线层设置于所述裸片的上表面；
    所述第一焊接管脚设置于所述重新布线层的上表面；
    所述重新布线层中设置有第一重新布线金属和第二重新布线金属；所述第一焊接管脚通过所述第一重新布线金属与所述第一键合管脚耦合，所述第一焊接管脚通过所述第二重新布线金属与所述第二键合管脚耦合。
  3. 如权利要求2所述的芯片装置，其特征在于：
    所述第一重新布线金属的一端连接于第一键合管脚的上表面，所述第一重新布线金属的另一端连接于所述第一焊接管脚的下表面；所述第二重新布线金属一端连接于所述第一键合管脚的上表面，所述第二重新布线金属的另一端连接于所述第二键合管脚的上表面。
  4. 如权利要求1至3任一项所述的芯片装置，其特征在于：
    所述裸片中设置有第一电容，所述第一电容的第一端和第二端分别耦合于高电平和低电平。
  5. 如权利要求4所述的芯片装置，其特征在于：
    所述第一电容包括第一金属氧化物半导体MOS管、第二MOS管和第一无源电容；
    所述第一MOS管和所述第一无源电容串联耦合于所述第一电容的第一端和第二端之间，所述第一MOS管的栅极用于接收第一控制信号，所述第一控制信号用于控制所述第一MOS管的导通和断开；
    所述第二MOS管的栅极耦合于与所述第一无源电容和所述第一MOS管的连接端，所述第二MOS管的源极和漏极共同耦合于所述第一电容的第一端。
  6. 如权利要求4所述的芯片装置，其特征在于：
    所述第一电容包括第一MOS管、第二MOS管、第一无源电容和第二无源电容；
    所述第一MOS管和所述第一无源电容串联耦合于所述第一电容的第一端和第二端之间，所述第一MOS管的栅极用于接收第一控制信号，所述第一控制信号用于控制第一MOS管的导通和断开；
    所述第二MOS管的栅极耦合于与所述第一无源电容和所述第一MOS管的连接端，所 述第二MOS管和所述第二无源电容串联耦合于所述第一电容的第一端和第二端之间；
    所述第一MOS管的栅极耦合于与所述第二无源电容和所述第二MOS管的连接端。
  7. 如权利要求5至6任一项所述的芯片装置，其特征在于：
    所述第一电容还包括第三MOS管，所述第三MOS的宽长比小于所述第一MOS管和所述第二MOS管，所述第三MOS管的源极和漏极耦合于所述第一无源电容的两端，所述第三MOS管的栅极用于接收第二控制信号，所述第二控制信号用于控制第三MOS管的导通和断开。
  8. 如权利要求5至7任一项所述的芯片装置，其特征在于：
    所述第一无源电容或所述第二无源电容为金属氧化物金属MOM电容。
  9. 如权利要求4至8任一项所述的芯片装置，其特征在于，还包括：
    第三键合管脚，所述第三键合管脚设置于所述裸片的上表面，所述重新布线层中设置有第三重新布线金属，所述第一焊接管脚通过所述第三重新布线金属与所述第三键合管脚连接；
    所述第一电容的一端耦合于所述第三键合管脚，所述第一电容的另一端接地；
    所述第三重新布线金属的长度小于第一重新布线金属的长度和第二重新布线金属的长度。
  10. 如权利要求1至9任一项所述的芯片装置，其特征在于，还包括：
    所述裸片中还设置有第一电感，所述第一电感的一端耦合于所述第一键合管脚，所述第一电感的另一端耦合于所述第一电源模块的输入端。
  11. 如权利要求10所述的芯片装置，其特征在于：
    所述裸片中还设置有第二电容，所述第二电容的一端耦合于所述第一电源模块的输入端，所述第二电容的另一端接地。
  12. 如权利要求1至11任一项所述的芯片装置，其特征在于：
    所述裸片中还设置有第一射频接收通道和第二射频接收通道；
    所述第一射频接收通道用于接收第一成员载波信号，所述第二射频接收通道用于接收第二成员载波信号，所述第一成员载波信号和所述第二成员载波信号共同构成下行载波聚合；
    所述第一射频接收通道和所述第二射频接收通道中设置有多个射频模块，所述第一电源模块和所述第二电源模块分别用于为所述多个射频模块中的一个或者多个供电。
  13. 如权利要求12所述的芯片装置，其特征在于：
    所述裸片中还设置有第二电感，所述第二电感的一端耦合于所述第二键合管脚，所述第二电感的另一端耦合于所述第二电源模块的输入端；
    所述第一电源模块为低压差线性稳压器，所述第一电源模块用于为所述第一射频接收 通道的第一本地振荡器供电；
    所述第二电源模块为低压差线性稳压器，所述第二电源模块用于为所述第二射频接收通道的第二本地振荡器供电。
  14. 如权利要求12所述的芯片装置，其特征在于：
    所述第一电源模块为低压差线性稳压器，所述第一电源模块用于为所述第一射频接收通道的第一本地振荡器供电；
    所述第二电源模块为低压差线性稳压器，所述第二电源模块用于为所述第一射频接收通道的低通滤波器供电。
  15. 一种无线通信装置，其特征在于，包括：
    基带处理芯片和权利要求1至14任一项所述的芯片装置，所述芯片装置和所述基带处理芯片耦合。
  16. 如权利要求15所述的无线通信装置，其特征在于，还包括：
    印刷电路板和天线，所述基带处理芯片和所述芯片装置固定于所述印刷电路板；所述天线用于为所述芯片装置提供射频信号。
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