JP7326470B2 - 表示装置 - Google Patents
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- JP7326470B2 JP7326470B2 JP2021561577A JP2021561577A JP7326470B2 JP 7326470 B2 JP7326470 B2 JP 7326470B2 JP 2021561577 A JP2021561577 A JP 2021561577A JP 2021561577 A JP2021561577 A JP 2021561577A JP 7326470 B2 JP7326470 B2 JP 7326470B2
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- electrode pads
- display device
- power supply
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- 229910052782 aluminium Inorganic materials 0.000 description 5
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- ZYECOAILUNWEAL-NUDFZHEQSA-N (4z)-4-[[2-methoxy-5-(phenylcarbamoyl)phenyl]hydrazinylidene]-n-(3-nitrophenyl)-3-oxonaphthalene-2-carboxamide Chemical compound COC1=CC=C(C(=O)NC=2C=CC=CC=2)C=C1N\N=C(C1=CC=CC=C1C=1)/C(=O)C=1C(=O)NC1=CC=CC([N+]([O-])=O)=C1 ZYECOAILUNWEAL-NUDFZHEQSA-N 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/02—Details
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Description
前記第1面上に位置する複数の画素部と、
前記第2面上に位置し、前記複数の画素部に印加される第1電源電圧、および前記第1電源電圧よりも低電位である第2電源電圧を出力する電源電圧供給部と、を備え、
前記電源電圧供給部と前記複数の画素部とを電気的に接続し、前記第1電源電圧を前記複数の画素部に印加する第1配線導体と前記第2電源電圧を前記複数の画素部に印加する第2配線導体とを有し、
前記第1配線導体と前記第2配線導体との少なくとも一方が、前記第1面を覆う面状導体部を含んでおり、
前記面状導体部は前記基板のうち少なくとも2つの辺において前記電源電圧供給部との接続部を有する。
前記第1面上に位置する複数の画素部と、
前記第2面上に位置し、前記複数の画素部に印加される第1電源電圧、および前記第1電源電圧よりも低電位である第2電源電圧を出力する電源電圧供給部と、を備える表示装置であって、
前記電源電圧供給部と前記複数の画素部とを電気的に接続し、前記第1電源電圧を前記複数の画素部に印加する第1配線導体と前記第2電源電圧を前記複数の画素部に印加する第2配線導体とを有し、
前記第1配線導体と前記第2配線導体との少なくとも一方が、前記第1面を覆う面状導体部を含んでおり、
前記面状導体部は前記基板のうち少なくとも2つの辺において前記電源電圧供給部との接続部を有する。
2 基板
2a 第1面
2aa 第1辺
2ab 第2辺
2b 第2面
2c 第3面
2d 第4面
21 第1領域
21a,21b 第1部分領域
22 第2領域
22a,22b 第2部分領域
23 第3領域
23a,23b 第3部分領域
24 第4領域
24a,24b 第4部分領域
25 第5領域
26 第6領域
3 画素部
31,31R,31G,31B 発光素子
31a 正電極
31b 負電極
32 アノードパッド
33 カソードパッド
34 引き回し配線導体
34a 一端部
34b 他端部
35 TFT
35a ゲート電極
35b ソース電極
35c ドレイン電極
36 導電接続部材
4 電源電圧供給部
5 第1配線導体
51 第1側面導体
52 第2側面導体
53 第1電極パッド
53a,53b 金属層
54 第2電極パッド
55 第3電極パッド
56 第4電極パッド
57 第1配線パターン
58 第2配線パターン
6 第2配線導体
61 第3側面導体
62 第4側面導体
63 第5電極パッド
64 第6電極パッド
65 第7電極パッド
66 第8電極パッド
67 第3配線パターン
68 第4配線パターン
7 走査信号線
71 電極パッド
8 発光制御信号線
81 電極パッド
10 下層絶縁層
11,12,13,14,15,16 絶縁層
17 透明導電層
100 マルチディスプレイ
Claims (12)
- 第1面と前記第1面とは反対側の第2面とを有する基板と、
前記第1面上に位置する複数の画素部と、
前記第2面上に位置し、前記複数の画素部に印加される第1電源電圧、および前記第1電源電圧よりも低電位である第2電源電圧を出力する電源電圧供給部と、を備え、
前記電源電圧供給部と前記複数の画素部とを電気的に接続し、前記第1電源電圧を前記複数の画素部に印加する第1配線導体と前記第2電源電圧を前記複数の画素部に印加する第2配線導体とを有し、
前記第1配線導体および前記第2配線導体はそれぞれ、前記第1面を覆う面状導体部を含んでおり、
前記面状導体部は前記基板のうち少なくとも2つの辺において前記電源電圧供給部との接続部を有する表示装置。 - 前記基板は、前記第1面の第1辺において前記第1面と前記第2面とを接続する第3面、および前記第3面とは反対側の第4面を有し、
前記第1配線導体は、
前記第1面における前記第1辺に沿った縁部から前記第3面および前記第2面にかけての第1領域に位置する複数の第1側面導体と、
前記第1面における、前記第1辺に対向する第2辺に沿った縁部から前記第4面および前記第2面にかけての第2領域に位置する複数の第2側面導体とを有し、
前記第2配線導体は、
前記第1面における前記第1辺に沿った縁部から前記第3面および前記第2面にかけての第3領域に位置する複数の第3側面導体と、
前記第1面における前記第2辺に沿った縁部から前記第4面および前記第2面にかけての第4領域に位置する複数の第4側面導体を含む第2配線導体とを有する、請求項1に記載の表示装置。 - 前記第1配線導体は、
前記第1面における前記第1領域に位置する複数の第1電極パッドと、
前記第2面における前記第1領域に位置し、平面視で前記複数の第1電極パッドとそれぞれ重なる複数の第2電極パッドと、
前記第1面における前記第2領域に位置する複数の第3電極パッドと、
前記第2面における前記第2領域に位置し、平面視で前記複数の第3電極パッドとそれぞれ重なる複数の第4電極パッドと、
前記第1面上に位置し、前記複数の画素部を前記複数の第1電極パッドおよび前記複数の第3電極パッドに電気的に接続する第1配線パターンと、
前記第2面上に位置し、前記電源電圧供給部を前記複数の第2電極パッドおよび前記複数の第4電極パッドに電気的に接続する第2配線パターンとをさらに含み、
前記複数の第1側面導体は、前記複数の第1電極パッドと前記複数の第2電極パッドとをそれぞれ接続し、
前記複数の第2側面導体は、前記複数の第3電極パッドと前記複数の第4電極パッドとをそれぞれ接続している、請求項2に記載の表示装置。 - 前記第2配線導体は、
前記第1面における前記第3領域に位置する複数の第5電極パッドと、
前記第2面における前記第3領域に位置し、平面視で前記複数の第5電極パッドにそれぞれ重なる複数の第6電極パッドと、
前記第1面における前記第4領域に位置する複数の第7電極パッドと、
前記第2面における前記第4領域に位置し、平面視で前記複数の第7電極パッドとそれぞれ重なる複数の第8電極パッドと、
前記第1面上に位置し、前記複数の画素部を前記複数の第5電極パッドおよび前記複数の第7電極パッドに電気的に接続する第3配線パターンと、
前記第2面上に位置し、前記電源電圧供給部を前記複数の第6電極パッドおよび前記複数の第8電極パッドに電気的に接続する第4配線パターンとをさらに含み、
前記複数の第3側面導体は、前記複数の第5電極パッドと前記複数の第6電極パッドとをそれぞれ接続し、
前記複数の第4側面導体は、前記複数の第7電極パッドと前記複数の第8電極パッドとをそれぞれ接続している、請求項2に記載の表示装置。 - 前記第1領域と前記第3領域とは互いに離隔しており、前記第2領域と前記第4領域とは互いに離隔している、請求項3または4に記載の表示装置。
- 前記第3面に直交する方向に見たときに、前記第1領域と前記第4領域とは互いに離隔しており、前記第3領域と前記第2領域とは互いに離隔している、請求項5に記載の表示装置。
- 前記第3面に直交する方向に見たときに、前記第1領域は前記第2領域に重なっており、前記第3領域は前記第4領域に重なっている、請求項6に記載の表示装置。
- 前記第3面に直交する方向に見たときに、前記第1領域と前記第2領域は互いに離隔しており、前記第3領域と前記第4領域とは互いに離隔している、請求項6に記載の表示装置。
- 前記第1面上に位置する複数の走査信号線をさらに備え、
前記基板は、前記第1面における前記第1辺に沿った縁部に位置する一対の第5領域であって、前記第1辺に沿った方向において前記第1領域および前記第3領域を挟む一対の第5領域を有し、
前記一対の第5領域には、前記複数の走査信号線にそれぞれ電気的に接続される複数の電極パッドが配置されている、請求項1~8のいずれかに記載の表示装置。 - 前記板状の基板は矩形であり、前記第1面は長方形状であり、前記第1辺および前記第2辺は短辺である、請求項1~9のいずれかに記載の表示装置。
- 前記複数の画素部の各々は、少なくとも1つのマイクロLED素子を含む、請求項1~10のいずれかに記載の表示装置。
- 前記面状導体部は、画素部において、前記マイクロLED素子の少なくとも一方の電極部位に開口が形成されている請求項11に記載の表示装置。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003058074A (ja) | 2001-08-09 | 2003-02-28 | Toshiba Corp | マトリックス型表示パネル |
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CN109003996A (zh) | 2018-07-27 | 2018-12-14 | 上海天马微电子有限公司 | 显示面板、显示面板的检修方法及显示装置 |
WO2019167966A1 (ja) | 2018-02-28 | 2019-09-06 | 京セラ株式会社 | 表示装置、ガラス基板およびガラス基板の製造方法 |
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US9671635B2 (en) * | 2014-02-07 | 2017-06-06 | E Ink Corporation | Electro-optic display backplane structures with drive components and pixel electrodes on opposed surfaces |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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