WO2021128748A1 - 一种碳化硅mosfet器件的元胞结构及功率半导体器件 - Google Patents

一种碳化硅mosfet器件的元胞结构及功率半导体器件 Download PDF

Info

Publication number
WO2021128748A1
WO2021128748A1 PCT/CN2020/095251 CN2020095251W WO2021128748A1 WO 2021128748 A1 WO2021128748 A1 WO 2021128748A1 CN 2020095251 W CN2020095251 W CN 2020095251W WO 2021128748 A1 WO2021128748 A1 WO 2021128748A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
cell structure
conductivity type
silicon carbide
jfet
Prior art date
Application number
PCT/CN2020/095251
Other languages
English (en)
French (fr)
Inventor
王亚飞
陈喜明
郑昌伟
焦莎莎
李诚瞻
罗海辉
Original Assignee
株洲中车时代半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株洲中车时代半导体有限公司 filed Critical 株洲中车时代半导体有限公司
Priority to US17/781,374 priority Critical patent/US20230006044A1/en
Publication of WO2021128748A1 publication Critical patent/WO2021128748A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This embodiment relates to the technical field of power semiconductor devices, and in particular to a silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device integrated with a Schottky diode (SBD) and its cell structure.
  • MOSFET silicon carbide metal oxide semiconductor field effect transistor
  • SBD Schottky diode
  • SiC semiconductor silicon carbide
  • the existing planar gate N-channel structure MOSFET also has a parasitic body diode, as shown in Figure 1, including: N+ substrate layer 101, N- drift region 102, P well region 103, N+ source region 104, P+ region 105, JFET Region 106, gate oxide layer 107, gate polysilicon 108, source metal 109, drain metal 110, body PIN diode 111.
  • the embodiments herein provide an SBD-integrated silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device, and provide the cell structure of the silicon carbide MOSFET device.
  • MOSFET metal oxide semiconductor field effect transistor
  • the embodiments herein provide a cell structure of a silicon carbide MOSFET device, including a first conductivity type drift region located on a first conductivity type substrate layer; at one end laterally extending along the surface of the cell structure, the drift region is A second conductivity type well region and a first JFET region that are laterally adjacent to the surface of the cell structure are arranged on the surface; on the side of the well region away from the first JFET region, the surface of the well region is provided with an enhanced
  • the enhanced region includes a first conductivity type enhanced region and a second conductivity type enhanced region laterally adjacent to the surface of the cell structure, wherein the first conductivity type enhanced region is closer to the second conductivity type enhanced region
  • the first JFET region; the first conductivity type enhancement region, the surface of the well region not covered by the enhancement region, and the first JFET region are provided with a gate insulating layer that is in contact with them at the same time,
  • the gate insulating layer is provided with a gate; the enhanced region is provided with
  • the embodiments herein also provide a silicon carbide MOSFET device, including the cell structure of the silicon carbide MOSFET device described above.
  • Figure 1 shows a cross-sectional view of a traditional planar gate N-channel MOSFET and parasitic body diode structure
  • FIG. 2 is a schematic diagram of a cell structure of an SBD-integrated three-dimensional MOSFET device according to an embodiment of this document;
  • FIG. 3 is an overall top view of the cell structure of the SBD-integrated three-dimensional MOSFET device of the embodiment of this document;
  • Fig. 5 is a cross-sectional view of the cell structure A-A' of the three-dimensional MOSFET integrated with SBD according to the embodiment of this document;
  • Fig. 6 is a B-B' cross-sectional view of the SBD-integrated three-dimensional MOSFET cell structure of an embodiment of this document;
  • FIG. 7 is a cross-sectional view of the C-C' cross-sectional view of the three-dimensional MOSFET cell structure integrated with SBD according to an embodiment of this document;
  • Fig. 8 is a cross-sectional view of the cell structure D-D' of the three-dimensional MOSFET integrated with SBD according to the embodiment of this document.
  • FIG. 2 is a schematic diagram of the cell structure of the three-dimensional MOSFET device integrated with SBD according to this embodiment. As shown in FIG. 2, it includes: a first conductivity type substrate layer 2, a first conductivity type drift region 3, and a second conductivity type well region 4 , The first JFET region 51, the second JFET region 52, the first conductivity type enhanced region 6, the second conductivity type enhanced region 7, the gate insulating layer 8, the gate 9, the source metal 10, the Schottky metal 11, Drain metal 12.
  • FIG. 3 is an overall top view of the cell structure of the SBD-integrated three-dimensional MOSFET device of the embodiment of this document;
  • Fig. 5 is a cross-sectional view of the cell structure A-A' of the three-dimensional MOSFET integrated with SBD according to the embodiment of this document;
  • Fig. 6 is a B-B' cross-sectional view of the SBD-integrated three-dimensional MOSFET cell structure of an embodiment of this document;
  • FIG. 7 is a cross-sectional view of the C-C' cross-sectional view of the three-dimensional MOSFET cell structure integrated with SBD according to an embodiment of this document;
  • Fig. 8 is a cross-sectional view of the cell structure D-D' of the three-dimensional MOSFET integrated with SBD according to the embodiment of this document.
  • the cell structure of the SBD-integrated three-dimensional MOSFET device is described with the first JFET region 51 in the front view as the base point and the starting end, the corresponding other end is the end, and the lateral direction of the cell structure is defined as the front view.
  • the horizontal direction of the figure, where the horizontal starting end is the rightmost end in the horizontal direction of the front view, the horizontal end is the leftmost end in the horizontal direction of the front view, and the horizontal direction of the right view is defined as the longitudinal direction of the cell structure, where the vertical starting end is The leftmost end in the horizontal direction of the right view, and the longitudinal end is the rightmost end in the horizontal direction of the right view.
  • the first conductivity type substrate layer 2 in this specification may include various semiconductor elements, such as silicon or silicon germanium with a single crystal, polycrystalline or amorphous structure, and may also include a mixed semiconductor structure, such as silicon carbide, gallium nitride, Indium phosphide, gallium arsenide, alloy semiconductor or a combination thereof are not limited here.
  • the first conductive type substrate layer 2 preferably adopts a silicon carbide substrate, and can adopt an N-type or P-type silicon carbide substrate.
  • an N-type substrate is taken as an example for description.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • JFET is the abbreviation of Junction Field-Effect Transistor (Junction Field-Effect Transistor, JFET).
  • This embodiment provides a cell structure of a silicon carbide MOSFET device, including a first conductivity type drift region 3 located on a first conductivity type substrate layer 2; at one end extending laterally along the surface of the cell structure, the drift region 3
  • the second conductivity type well region 4 and the first JFET region 51 are arranged laterally adjacent to the surface of the cell structure on the surface of the cell structure; on the side of the well region away from the first JFET region 51, the surface of the well region 4 is provided with an enhanced region ,
  • the enhanced region includes a first conductivity type enhanced region 6 and a second conductivity type enhanced region 7 laterally adjacent to the surface of the cell structure, wherein the first conductivity type enhanced region 6 is closer to the first JFET than the second conductivity type enhanced region 7 Region 51; the first conductivity type enhanced region 6, the surface of the well region 4 that is not covered by the enhanced region, and the first JFET region 51 are provided with a gate insulating layer 8 that is in contact with them at the same time, and the gate
  • the Schottky metal 11 also extends above the second conductivity type enhanced region 7 to form an ohmic contact with the second conductivity type enhanced region 7.
  • the Schottky metal 11 and the source metal 10 are in direct contact; or, the Schottky metal 11 and the source metal 10 are arranged separately, and the connection is made through the secondary metal provided on the surface of the cell structure.
  • the drift region 3 is provided with a second JFET region 52 in the surface of the region not covered by the well region 4, the second conductivity type enhancement region 7 and the Schottky metal 11.
  • the boundary of the Schottky metal 11 is in contact with or close to the boundary of the second JFET region 52.
  • the first JFET region 51 and the well region 4 extend longitudinally along the surface of the cell structure in the drift region 3 to the other end of the surface of the cell structure in the longitudinal direction.
  • the enhanced region extends longitudinally from the cell structure surface in the well region 4 to the other end of the cell structure surface longitudinally on the surface of the drift zone 3, and accordingly, the source metal 10 extends along the cell structure on the surface of the enhanced region.
  • the surface extends longitudinally to the other end of the longitudinal direction of the cell structure surface, and the gate insulating layer 8 extends along the cell structure on the surface of the first JFET region 51, the well region 4 not covered by the enhanced region, and the surface of the first conductivity type enhanced region 6 The surface extends longitudinally to the other end of the longitudinal direction of the surface of the cell structure.
  • the depth of the enhanced region 7 of the second conductivity type is greater than or equal to the depth of the enhanced region 6 of the first conductivity type.
  • the concentration of the first JFET region 51 and the second JFET region 52 are equal and higher than the concentration of the drift region 3.
  • the first conductivity type drift region 3 is provided on the first conductivity type substrate layer 2, and at the initial end along the longitudinal direction of the cell structure surface, a second conductivity type adjacent to the cell structure surface is provided in the surface of the drift region 3.
  • the first JFET region 51 is located at the beginning end of the cell structure in the lateral direction, that is, the rightmost end in the horizontal direction of the front view of the cell structure.
  • the second conductivity type well region 4 and the first JFET The region 5 is in contact in the lateral direction of the cell structure; an enhanced region is provided in the surface of the well region 4, wherein the surface of the well region 4 is not completely covered by the enhanced region, and the enhanced region includes the first conductivity type enhanced region 6 and the second conductivity Type enhancement area 7, and the first conductivity type enhancement area 6 and the second conductivity type enhancement area 7 adjoin and contact in the lateral direction of the cell structure, the first conductivity type enhancement area 6 is closer to the first conductivity type enhancement area 7 than the second conductivity type enhancement area 7
  • the second conductivity type enhanced region 7 is located at the lateral end of the cell structure away from the first JFET region 51, that is, the leftmost end of the cell structure in the horizontal direction in the front view.
  • the first JFET region 51 and the well region 4 extend from the initial end of the drift region 3 along the longitudinal direction of the cell structure surface to the longitudinal end of the cell structure surface.
  • the second conductivity type enhancement zone 7 extends from the longitudinal starting end of the cell structure to the longitudinal end of the cell structure on the surface of the drift zone 3 from the well zone 4 along the cell structure surface, that is, the leftmost end in the horizontal direction from the right view of the cell structure Extend to the far right end.
  • the MOSFET device includes a relatively high concentration of the first conductivity type substrate 2 with a concentration ranging from 1 ⁇ 10 18 to 1 ⁇ 10 19 cm -3 .
  • a drift region 3 of the first conductivity type is provided on the substrate layer 2 of the first conductivity type.
  • the concentration of the drift region 3 ranges from 1 ⁇ 10 14 to 5 ⁇ 10 16 cm -3 .
  • the specific concentration can be determined according to the withstand voltage requirements of the device. Make optimized settings.
  • the concentration range of the second conductivity type well region 4 is set to 1 ⁇ 10 16 ⁇ 5 ⁇ 10 18 cm -3 ; the concentration range of the first JFET region 51 and the second JFET region 52 is set to 1 ⁇ 10 15 ⁇ 5 ⁇ 10 17 cm -3 , and the concentration of the two JFET regions is set to be higher than the concentration of the drift region 3, which is beneficial to improve the bipolar degradation of silicon carbide and improve the reliability of the device; the concentration range of the enhancement region in the cell structure is set to be greater than 1. ⁇ 10 19 cm -3 , and the depth of the second conductivity type enhanced region 7 is set to be greater than the depth of the first conductivity type enhanced region 6.
  • the gate insulating layer 8 located on the first JFET region 51, the second conductivity type well region 4, and the first conductivity type enhanced region 6 and in contact with them at the same time has a thickness of ⁇ 50 nm, and the gate insulating layer
  • the electrode 9 is deposited on the gate insulating layer 8, the doping type is N-type, the gate material is set to metal or polysilicon, and the concentration of the gate 9 is greater than or equal to 1 ⁇ 10 18 cm -3 .
  • the gate 9 and the source metal 10 are isolated by a highly insulating interlayer dielectric.
  • the first conductivity type enhanced region 6 is arranged on the surface of the well region 4 to extend from the longitudinal start end to the end along the surface of the cell structure, that is, extend from the leftmost end to the right end in the right view of the cell structure. In this embodiment, Extend to the longitudinal end of the cell structure.
  • a source metal 10 for forming an ohmic contact is provided on the enhanced region.
  • the source metal 10 contacts the first conductivity type enhanced region 6 and the second conductivity type 7 at the same time, and is not in contact with the drift region 3, nor does the source metal 10 In contact with the gate insulating layer 8 and the gate 9, the source metal 10 extends from the longitudinal start to the end along the surface of the cell structure, that is, extends from the leftmost end to the rightmost end in the right view of the cell structure; the source metal ohmic contact
  • the material is set to a metal or alloy with low contact resistivity, preferably aluminum, nickel, or aluminum-nickel alloy.
  • a second JFET region 52 is provided on the surface of the drift region 3 that is not covered by the well region 4, and the drift region 3 is located between the well regions 4 and
  • the surface covered by the second JFET region 52 and the surface of the second conductivity type enhancement region 7 not covered by the source metal 10 are provided with Schottky metal 11, and the Schottky metal 11 and the drift region 3 below it form a low barrier
  • the Schottky contact forms an ohmic contact with the second conductivity type enhanced region 7, which reduces the on-resistance of a part of the SBD.
  • the Schottky metal 11 is in contact with the source metal 10, and the contact portion between the Schottky metal 11 and the source metal 10 is located on the second conductivity type enhanced region 7.
  • the second JFET region 52 is disposed in the middle part of the drift region 3 on the surface not covered by the well region 4.
  • the drift region is at least divided into two parts by the second JFET region on the surface not covered by the second JFET region and the second conductivity type enhanced region,
  • the Schottky metal is also divided into at least two parts.
  • the Schottky metal contact material is set as a metal or alloy with low contact resistivity, preferably titanium, aluminum, nickel, or an alloy composed of any components of titanium, aluminum, and nickel.
  • the enhancement region extends from the longitudinal start end of the cell structure surface in the well region 4 to the longitudinal end of the cell structure surface on the surface of the drift region 3, and accordingly, the gate insulating layer 8 is in the first JFET region 51 and the well region 4
  • the reinforcing area covers the surface and the first conductivity type reinforcing area 6 extends from the initial end of the cell structure surface longitudinally to the end of the cell structure surface longitudinal direction, and the source metal 10 extends along the cell structure surface longitudinally on the surface of the reinforcing area
  • the starting end of the cell structure extends to the longitudinal end of the surface of the cell structure.
  • the Schottky metal 11 and the doped region of the second JFET region 52 are arranged at a staggered interval, and the boundary of the Schottky metal 11 can be set to be in contact with or close to the boundary of the doped region of the second JFET region 52 to reduce the SBD conduction. resistance. Since there is no JFET doped region under the Schottky metal, the leakage current during reverse bias of the SBD can be reduced, so as to achieve a better compromise relationship between the on-state resistance of the SBD and the reverse bias leakage current.
  • the first JFET region 51 and the well region 4 extend in the drift region 3 along the longitudinal starting end of the cell structure surface to the longitudinal end of the cell structure surface. Since the SBD is integrated in the JFET region of the MOSFET cell structure, In turn, the area utilization rate of the device is improved, and the overall power density of the device is increased.
  • a drain metal 12 is also provided under the substrate 2.
  • the drain metal 12, the first conductivity type substrate layer 2, the first conductivity type drift region 3, the second conductivity type well region 4, and the Schottky metal 11 constitute the built-in SBD of the MOSFET cell, which can be used as a MOSFET reverse bias
  • the MOSFET module does not need to be packaged with an additional SBD, which reduces the packaging cost of the device and also reduces the parasitic inductance caused by the bonding wire.
  • the SBD is integrated in the cell, the turn-on voltage of the body diode of the MOSFET device is increased, the degradation of the electrical characteristics of the MOSFET device is improved, and the reliability of the device is improved.
  • the Schottky metal 11 can also be set to cover the source metal 10 for connection, or the Schottky metal 11 can be set to be separated from the source metal 10, and The connection is made through the secondary metal on the surface of the cell structure.
  • This embodiment provides a three-dimensional silicon carbide MOSFET cell structure. By integrating SBD at the cell level, it is used as a freewheeling diode when the device is reverse biased, which effectively suppresses the turn-on of the body diode and improves the MOSFET device. Degradation of electrical characteristics improves device reliability,
  • the SBD part and the MOSFET part share part of the active area and terminal area, which improves the utilization of the device area and increases the overall power density of the device.
  • And Schottky metal and JFET doped regions are spaced in a three-dimensional direction, which optimizes the distribution of each region, reduces the on-resistance of the SBD and reduces the leakage current when the SBD is reverse biased, achieving a good compromise relationship.
  • the present invention also provides a silicon carbide MOSFET power semiconductor device.
  • the power semiconductor device is provided with a cell structure of any one of the above-mentioned silicon carbide MOSFET devices; wherein the shape of the cell structure is a strip, a quadrilateral, or a hexagon. Polygonal.
  • the gates of the MOSFET devices are arranged separately, which is beneficial to reduce the parasitic capacitance of the chip.
  • This embodiment integrates the SBD in the cell, so that there is no need to package the SBD when the module is packaged, thereby reducing the parasitic inductance of the bonding wire and the module packaging cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种碳化硅MOSFET器件的元胞结构，包括，位于衬底层（2）上的漂移区（3），位于漂移区（3）内的第二导电类型阱区（4）和第一JFET区（51），位于阱区（4）表面内的增强区，位于第一导电类型增强区（6）、阱区（4）以及第一JFET区（51）上且与它们同时接触的栅极绝缘层（8）及其之上的栅极（9），位于增强区上的源极金属（10），位于第二电类型增强区（7）和漂移区（3）上的肖特基金属（11），位于肖特基金属（11）之间漂移区（3）表面的第二JFET区（52），以及漏极金属（12）。

Description

一种碳化硅MOSFET器件的元胞结构及功率半导体器件
本文要求享有与2019年12月26日提交的名称为“一种碳化硅MOSFET器件的元胞结构及功率半导体器件”的中国专利申请CN 201911370082.8的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本实施例涉及功率半导体器件技术领域，尤其涉及一种集成了肖特基二极管(SBD)的碳化硅金属氧化物半导体场效应晶体管(MOSFET)器件及其元胞结构。
背景技术
随着节能减排、新能源并网、智能电网的发展，第三代半导体碳化硅(SiC)功率器件日益得到重视，其主要优势在于其击穿电场强度是传统硅器件的10倍，或相同电压/电流等级下，比导通电阻是硅器件的近千分之一。SiC器件开关频率是硅器件的20倍，可减小电路中储能元件的体积。理论上，SiC器件可以在600摄氏度以上的高温环境下工作，且具有优异的抗辐射性能，可大大提高***的可靠性。
然而受限于现有制程技术，在碳化硅双极器件中的双极退化现象会导致器件载流子寿命显著降低并使器件的压降增大、反向偏置漏电流增大，不利于碳化硅器件的可靠性。现有的平面栅N型沟道结构MOSFET还寄生了一个体二极管，如图1，包括：N+衬底层101、N-漂移区102、P阱区103、N+源区104、P+区105、JFET区106、栅极氧化层107、栅极多晶硅108、源极金属109、漏极金属110、体PIN二极管111。
在MOSFET反向偏置时，为抑制体二极管开启引起双极退化，需采用SBD与MOSFET反并联使用，作为其续流二极管。正常情况下，在芯片级别反并联SBD会增加模块封装的成本并会在SBD端引入额外的键合线及杂散电感，导致模块电气性能的下降。
因此有必要提出一种新的MOSFET器件来改善以上技术问题。
发明内容
为了解决在一些情况下的上述问题，本文实施例提供了一种集成SBD的碳化硅金属氧化物半导体场效应晶体管(MOSFET)器件，并提供了这种碳化硅MOSFET器件的元胞结构。
本文实施例提供了一种碳化硅MOSFET器件的元胞结构，包括，位于第一导电类型衬底层上的第一导电类型漂移区；在沿元胞结构表面横向延伸的一端，所述漂移区的表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区和第一JFET区；在所述阱区远离所述第一JFET区的一侧，所述阱区的表面内设置有增强区，所述增强区包括沿元胞结构表面横向邻接的第一导电类型增强区和第二导电类型增强区，其中，所述第一导电类型增强区比所述第二导电类型增强区更加靠近所述第一JFET区；所述第一导电类型增强区、所述阱区的未被所述增强区覆盖的表面以及所述第一JFET区上设置有与它们同时接触的栅极绝缘层，所述栅极绝缘层上设置有栅极；所述增强区上设置有源极金属，其中，所述源极金属与其下方的所述增强区形成欧姆接触，同时不与所述漂移区和所述栅极接触；在沿元胞结构表面横向延伸的另一端，所述漂移区于未被所述阱区和所述第二JFET区覆盖的表面上设置有肖特基金属，所述肖特基金属与其下方的所述漂移区形成肖特基接触；以及位于所述衬底下方的漏极金属。
本文实施例还提供了一种碳化硅MOSFET器件，包括以上内容中的碳化硅MOSFET器件的元胞结构。
本文的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本文而了解。本文的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本文的进一步理解，并且构成说明书的一部分，与本文的实施例共同用于解释本文，并不构成对本文的限制。在附图中：
图1示出了传统的平面栅N沟道型MOSFET及寄生体二极管结构剖面图；
图2是本文实施例的集成了SBD的三维MOSFET器件的元胞结构示意图；
图3是本文实施例的集成了SBD的三维MOSFET器件的元胞结构整体俯视图；
图4是本文实施例的MOSFET器件的元胞结构漂移区表面的剖面俯视图；
图5是本文实施例的集成了SBD的三维MOSFET元胞结构A-A’剖面图；
图6是本文实施例的集成了SBD的三维MOSFET元胞结构B-B’剖面图；
图7是本文实施例的集成了SBD的三维MOSFET元胞结构C-C’剖面图；
图8是本文实施例的集成了SBD的三维MOSFET元胞结构D-D’剖面图。
具体实施方式
为使本文的目的、技术方案和优点更加清楚，以下结合附图对本文作进一步地详细说明，借此对本文如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，在本文的精神和原则之内，本文中的各个实施例以及各实施例中的各个特征可以相互结合，本领域人员所做的任何修改、等同替换、改进等所形成的技术方案均应在本文的保护范围之内。
第一实施例
图2为本实施例集成了SBD的三维MOSFET器件的元胞结构示意图，如图2所示，包括：第一导电类型衬底层2、第一导电类型漂移区3、第二导电类型阱区4、第一JFET区51、第二JFET区52、第一导电类型增强区6、第二导电类型增强区7、栅极绝缘层8、栅极9、源极金属10、肖特基金属11、漏极金属12。
图3是本文实施例的集成了SBD的三维MOSFET器件的元胞结构整体俯视图；
图4是本文实施例的MOSFET器件的元胞结构漂移区表面的剖面俯视图；
图5是本文实施例的集成了SBD的三维MOSFET元胞结构A-A’剖面图；
图6是本文实施例的集成了SBD的三维MOSFET元胞结构B-B’剖面图；
图7是本文实施例的集成了SBD的三维MOSFET元胞结构C-C’剖面图；
图8是本文实施例的集成了SBD的三维MOSFET元胞结构D-D’剖面图。
在一实施方式中，集成了SBD的三维MOSFET器件的元胞结构以正视图的第一JFET区51为基点和起始端进行描述，对应的另一端为末端，元胞结构的横向方向定义为正视图的水平方向，其中，横向起始端为正视图水平方向的最右端，横向末端为正视图水平方向的最左端，右视图的水平方向定义为元胞结构的纵向方向，其中，纵向起始端为右视图水平方向的最左端，纵向末端为右视图水平方向的最右端。
本说明书中的第一导电类型衬底层2可以包括各种半导体元素，例如单晶、多晶或非晶结构的硅或硅锗，也可以包括混合的半导体结构，例如碳化硅、氮化镓、磷化铟、砷化镓、合金半导体或其组合，在此不做限定。在本实施例中的第一导电类型衬底层2优选采用碳化硅衬底，可采用N型或P型碳化硅衬底，在本实施例中以N型衬底为例进行说明。
本实施例第一导电类型为N型，第二导电类型为P型。
其中JFET为结型场效应晶体管的缩写(Junction Field-Effect Transistor，JFET)。
本实施例提供了一种碳化硅MOSFET器件的元胞结构，包括，位于第一导电类型衬底层2上的第一导电类型漂移区3；在沿元胞结构表面横向延伸的一端，漂移区3的表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区4和第一JFET区51；在阱区远离第一JFET区51的一侧，阱区4的表面内设置有增强区，增强区包括沿元胞结构表面横向邻接的第一导电类型增强区6和第二导电类型增强区7，其中，第一导电类型增强区6比第二导电类型增强区7更加靠近第一JFET区51；第一导电类型增强区6、阱区4的未被增强区覆盖的表面以及第一JFET区51上设置有与它们同时接触的栅极绝缘层8，栅极绝缘层8上设置有栅极9；增强区上设置有源极金属10，其中，源极金属10与其下方的增强区形成欧姆接触，同时不与漂移区3和栅极9接触；在沿元胞结构表面横向延伸的另一端，漂移区3于未被阱区4和第二JFET区52覆盖的表面上设置有肖特基金属11，肖特基金属11与其下方的漂移区3形成肖特基接触，同时肖特基金属11与源极金属10接触；以及位于衬底2下方的漏极金属12。
在一实施方式中，肖特基金属11还延伸至所述第二导电类型增强区7的上方，与所述第二导电类型增强区7形成欧姆接触。
在一实施方式中，肖特基金属11与源极金属10直接接触；或者，肖特基金 属11与源极金属10分隔设置，通过设置在元胞结构表面的二次金属进行连接。
在一实施方式中，漂移区3在未被所述阱区4、第二导电类型增强区7和肖特基金属11覆盖的的区域的表面内设置有第二JFET区52。
在一实施方式中，肖特基金属11的边界与所述第二JFET区52的边界接触或接近。
在一实施方式中，第一JFET区51和阱区4在漂移区3沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
在一实施方式中，增强区在漂移区3表面从阱区4内元胞结构表面纵向延伸至元胞结构表面纵向的另一端，相应地，源极金属10在增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端，栅极绝缘层8在第一JFET区51、阱区4未被所述增强区覆盖表面及第一导电类型增强区6表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
在一实施方式中，第二导电类型增强区7的深度大于或等于第一导电类型增强区6的深度。
在一实施方式中，第一JFET区51和第二JFET区52的浓度相等且高于漂移区3的浓度。
具体地，在第一导电类型衬底层2上设置有第一导电类型漂移区3，在沿元胞结构表面纵向的起始端，在漂移区3表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区4和第一JFET区51，第一JFET区51位于元胞结构横向的起始端，即元胞结构正视图水平方向的最右端，第二导电类型阱区4与第一JFET区5在元胞结构的横向方向上接触；在阱区4表面内设置有增强区，其中阱区4的表面未被增强区完全覆盖，增强区包含第一导电类型增强区6和第二导电类型增强区7，且第一导电类型增强区6和第二导电类型增强区7在元胞结构的横向上邻接及接触，第一导电类型增强区6比第二导电类型增强区7更加靠近第一JFET区51，第二导电类型增强区7位于远离第一JFET区51的元胞结构横向的末端，即元胞结构正视图水平方向的最左端。其中，第一JFET区51和阱区4在漂移区3沿元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端。
第二导电类型增强区7在漂移区3表面从阱区4内沿元胞结构表面从元胞结构纵向起始端延伸至元胞结构纵向的末端，即从元胞结构右视图水平方向的最左 端延伸至最右端。
在一实施方式中，MOSFET器件包含一个较高浓度的第一导电类型衬底2，浓度范围为1×10 18～1×10 19cm -3。在第一导电类型衬底层2上设置有第一导电类型漂移区3，该漂移区3浓度范围为1×10 14～5×10 16cm -3，具体的浓度可以根据器件的耐压要求来进行优化设置。第二导电类型阱区4的浓度范围设置为1×10 16～5×10 18cm -3；第一JFET区51及第二JFET区52浓度范围设置为1×10 15～5×10 17cm -3，且两个JFET区浓度设置为高于漂移区3的浓度，有利于改善碳化硅双极退化现象，并提高器件的可靠性；元胞结构中的增强区浓度范围均设置为大于1×10 19cm -3，且第二导电类型增强区7的深度设置为大于所述第一导电类型增强区6的深度。
在一实施方式中，位于第一JFET区51、第二导电类型阱区4以及第一导电类型增强区6之上且与它们同时接触的栅极绝缘层8，其厚度设置为≥50nm，栅极9沉积在栅极绝缘层8之上，掺杂类型为N型，栅极材料设置为金属或多晶硅，栅极9浓度为大于等于1×10 18cm -3。栅极9与源极金属10通过高绝缘的层间介质进行隔离。其中第一导电类型增强区6在阱区4表面设置为沿元胞结构表面从纵向的起始端向末端延伸，即从元胞结构右视图的最左端向右端延伸，在本实施例中，一直延伸到元胞结构纵向的末端。
在增强区上设置有用于形成欧姆接触的源极金属10，源极金属10同时接触第一导电类型增强区6和第二导电类型7，且不与漂移区3接触，源极金属10也不与栅极绝缘层8和栅极9接触，源极金属10沿元胞结构表面从纵向的起始端延伸至末端，即从元胞结构右视图的最左端延伸到最右端；源极金属欧姆接触材料设置为具有低接触电阻率的金属或合金，优选为铝、镍，或铝镍合金。
在元胞结构横向的末端，即元胞结构正视图的最左端，在没有被阱区4覆盖的漂移区3的表面上设置有第二JFET区52，漂移区3于未被阱区4和第二JFET区52覆盖的表面与第二导电类型增强区7未被源极金属10覆盖的表面上设置有肖特基金属11，肖特基金属11与其下方的漂移区3形成低势垒的肖特基接触，并与第二导电类型增强区7形成欧姆接触，降低了SBD一部分的导通电阻。同时肖特基金属11与源极金属10接触，肖特基金属11与源极金属10接触部位于第二导电类型增强区7之上。其中，在沿元胞结构表面横向延伸的另一端，第二JFET区52设置于漂移区3于未被阱区4覆盖的表面的中间部位。在沿元胞结构表面 横向延伸的另一端，所述漂移区于未被所述第二JFET区和所述第二导电类型增强区覆盖的表面被所述第二JFET区至少分隔为两部分，在本实施例中，相应地，所述肖特基金属也至少分隔设置为两部分。肖特基金属接触材料设置为具有低接触电阻率的金属或合金，优选为钛、铝、镍，或钛铝镍任意组份合成的合金。
增强区在漂移区3表面从阱区4内元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端，相应地，栅极绝缘层8在第一JFET区51、阱区4未被所述增强区覆盖表面及第一导电类型增强区6表面上沿元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端，源极金属10在增强区表面上沿元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端。
肖特基金属11与第二JFET区52掺杂区域进行错位的间隔设置，肖特基金属11的边界可设置为与第二JFET区52掺杂区域的边界接触或接近，可降低SBD导通电阻。由于肖特基金属下方并没有设置JFET掺杂区，可以降低SBD反向偏置时的漏电流，以实现SBD通态电阻与反向偏置漏电流之间较好的折中关系。
在一实施方式中，第一JFET区51和阱区4在漂移区3沿元胞结构表面纵向起始端延伸至元胞结构表面纵向的末端，由于把SBD集成于MOSFET元胞结构的JFET区，进而提高了器件的面积利用率，增加了器件整体功率密度。
在衬底2下方还设置有漏极金属12。
漏极金属12、第一导电类型衬底层2、第一导电类型漂移区3、第二导电类型阱区4、肖特基金属11即构成了MOSFET元胞内置的SBD，可以用作MOSFET反偏时的续流二极管，使得MOSFET模块封装时无需额外封装SBD，降低了器件的封装成本，同时也减少了因键合引线产生的寄生电感。同时由于在元胞内集成了SBD，提高了MOSFET器件体二极管的开启电压，改善了MOSFET器件电特性退化情况，提高了器件可靠性。
此外，根据器件的具体应用场合或者基于不同的设计考虑，肖特基金属11还能设置为覆盖在源极金属10上方进行连接，或者肖特基金属11设置为与源极金属10分离，并通过元胞结构表面的二次金属进行连接。
综上所述，
1、本实施例提供了一种三维结构的碳化硅MOSFET元胞结构，通过在元胞级别集成SBD，用作器件反偏时的续流二极管，有效抑制了体二极管的开启，改 善了MOSFET器件电特性退化情况，提高了器件可靠性，
2、本实施例通过将SBD集成于MOSFET元胞结构的的P+增强区之间，SBD部分和MOSFET部分共用部分有源区和终端区面积，提高了器件面积利用率，增加了器件整体功率密度，而肖特基金属与JFET掺杂区域在三维方向进行间隔设置，优化了各区域的分布，降低了SBD导通电阻以及降低SBD反向偏置时的漏电流，实现了较好的折中关系。
第二实施例
本发明还提供了一种碳化硅MOSFET功率半导体器件，功率半导体器件设置有若干以上内容中任一项的碳化硅MOSFET器件的元胞结构；其中，元胞结构的形状为条形、四边形或六边形。
综上所述，
1、本实施例通过将MOSFET器件的栅极分开设置，有利于降低芯片寄生电容。
2、本实施例通过在元胞内集成SBD，使模块封装时无需额外再封装SBD，降低了键合线的寄生电感及模块封装成本。
还需要说明的是，实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。除非有所知名为相反之意，本文及所附权利要求中的数值参数是近似值，能够根据通过本文的内容所得的所需特性改变。具体而言，所有使用于说明书及权利要求中表示组成的含量、反应条件等的数字，应理解为在所有情况中是受到「约」的用语所修饰。一般情况下，其表达的含义是指包含由特定数量在一些实施例中±10％的变化、在一些实施例中±5％的变化、在一些实施例中±1％的变化、在一些实施例中±0.5％的变化。再者，单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
虽然本文公开的实施方式如上，但所述的内容只是为了便于理解本文而采用 的实施方式，并非用以限定本文。任何本文所述技术领域内的技术人员，在不脱离本文所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，本文的保护范围并不局限于文中公开的特定实施例，而是包括落入权利要求范围内的所有技术方案。

Claims (11)

  1. 一种碳化硅MOSFET器件的元胞结构，其中，包括：
    位于第一导电类型衬底层上的第一导电类型漂移区；
    在沿元胞结构表面横向延伸的一端，所述漂移区的表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区和第一JFET区；
    在所述阱区远离所述第一JFET区的一侧，所述阱区的表面内设置有增强区，所述增强区包括沿元胞结构表面横向邻接的第一导电类型增强区和第二导电类型增强区，其中，所述第一导电类型增强区比所述第二导电类型增强区更加靠近所述第一JFET区；
    所述第一导电类型增强区、所述阱区的未被所述增强区覆盖的表面以及所述第一JFET区上设置有与它们同时接触的栅极绝缘层，所述栅极绝缘层上设置有栅极；
    所述增强区上设置有源极金属，其中，所述源极金属与其下方的所述增强区形成欧姆接触，同时不与所述漂移区和所述栅极接触；
    在沿元胞结构表面横向延伸的另一端，所述漂移区于未被所述阱区和所述第二JFET区覆盖的表面上设置有肖特基金属，所述肖特基金属与其下方的所述漂移区形成肖特基接触；以及
    位于所述衬底下方的漏极金属。
  2. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中，
    所述肖特基金属还延伸至所述第二导电类型增强区的上方，与所述第二导电类型增强区形成欧姆接触。
  3. 根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其中，
    所述肖特基金属与所述源极金属直接接触；
    或者，所述肖特基金属与所述源极金属分隔设置，通过设置在元胞结构表面的二次金属进行连接。
  4. 根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其中，
    所述漂移区在未被所述阱区、所述第二导电类型增强区和所述肖特基金属覆 盖的的区域的表面内设置有第二JFET区。
  5. 根据权利要求4所述的碳化硅MOSFET器件的元胞结构，其中，所述肖特基金属的边界与所述第二JFET区的边界接触或接近。
  6. 根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其中，
    所述第一JFET区和所述阱区在所述漂移区沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
  7. 根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其中，
    所述增强区在所述漂移区表面从所述阱区内元胞结构表面纵向延伸至元胞结构表面纵向的另一端，相应地，所述源极金属在所述增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端，所述栅极绝缘层在所述第一JFET区、所述阱区未被所述增强区覆盖表面及所述第一导电类型增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
  8. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中，所述第二导电类型增强区的深度大于或等于所述第一导电类型增强区的深度。
  9. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中，所述第一和第二JFET区的浓度相等且高于所述漂移区的浓度。
  10. 根据权利要求9所述的碳化硅MOSFET器件的元胞结构，其中，
    所述衬底的浓度范围为1×10 18～1×10 19cm -3；
    所述漂移区的浓度范围为1×10 14～5×10 16cm -3；
    所述阱区的浓度范围为1×10 16～5×10 18cm -3；
    所述第一和第二JFET区的浓度范围为1×10 15～5×10 17cm -3；
    所述增强区的浓度范围为大于1×10 19cm -3；
    所述栅极的浓度为大于等于1×10 18cm -3。
  11. 一种碳化硅MOSFET功率半导体器件，其中，所述功率半导体器件设置有若干如权利要求1至10中任一项所述的碳化硅MOSFET器件的元胞结构；其中，所述元胞结构的形状为条形、四边形或六边形。
PCT/CN2020/095251 2019-12-26 2020-06-10 一种碳化硅mosfet器件的元胞结构及功率半导体器件 WO2021128748A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/781,374 US20230006044A1 (en) 2019-12-26 2020-06-10 Cell structure of silicon carbide mosfet device, and power semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911370082.8 2019-12-26
CN201911370082.8A CN113054016B (zh) 2019-12-26 2019-12-26 一种碳化硅mosfet器件的元胞结构及功率半导体器件

Publications (1)

Publication Number Publication Date
WO2021128748A1 true WO2021128748A1 (zh) 2021-07-01

Family

ID=76505660

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/095251 WO2021128748A1 (zh) 2019-12-26 2020-06-10 一种碳化硅mosfet器件的元胞结构及功率半导体器件

Country Status (3)

Country Link
US (1) US20230006044A1 (zh)
CN (1) CN113054016B (zh)
WO (1) WO2021128748A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113644133B (zh) * 2021-07-28 2023-09-05 清纯半导体(宁波)有限公司 一种半导体器件及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100295101A1 (en) * 2009-05-21 2010-11-25 Richtek Technology Corporation, R.O.C Integrated jfet and schottky diode
US20150084118A1 (en) * 2013-09-20 2015-03-26 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
CN106783851A (zh) * 2017-01-19 2017-05-31 北京世纪金光半导体有限公司 集成肖特基二极管的SiCJFET器件及其制作方法
CN106784008A (zh) * 2017-01-22 2017-05-31 北京世纪金光半导体有限公司 一种集成肖特基二极管的SiC MOSFET器件
CN109244137A (zh) * 2018-09-19 2019-01-18 电子科技大学 一种高可靠性SiC MOSFET器件
CN109742135A (zh) * 2018-12-03 2019-05-10 北京大学深圳研究生院 一种碳化硅mosfet器件及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5465937B2 (ja) * 2009-07-02 2014-04-09 トヨタ自動車株式会社 半導体装置、半導体装置の制御方法、半導体モジュール
US8368140B2 (en) * 2009-12-03 2013-02-05 Diodes Incorporated Trench MOS device with Schottky diode and method for manufacturing same
JP6021032B2 (ja) * 2014-05-28 2016-11-02 パナソニックＩｐマネジメント株式会社 半導体素子およびその製造方法
US9583482B2 (en) * 2015-02-11 2017-02-28 Monolith Semiconductor Inc. High voltage semiconductor devices and methods of making the devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100295101A1 (en) * 2009-05-21 2010-11-25 Richtek Technology Corporation, R.O.C Integrated jfet and schottky diode
US20150084118A1 (en) * 2013-09-20 2015-03-26 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
CN106783851A (zh) * 2017-01-19 2017-05-31 北京世纪金光半导体有限公司 集成肖特基二极管的SiCJFET器件及其制作方法
CN106784008A (zh) * 2017-01-22 2017-05-31 北京世纪金光半导体有限公司 一种集成肖特基二极管的SiC MOSFET器件
CN109244137A (zh) * 2018-09-19 2019-01-18 电子科技大学 一种高可靠性SiC MOSFET器件
CN109742135A (zh) * 2018-12-03 2019-05-10 北京大学深圳研究生院 一种碳化硅mosfet器件及其制备方法

Also Published As

Publication number Publication date
CN113054016A (zh) 2021-06-29
CN113054016B (zh) 2023-04-07
US20230006044A1 (en) 2023-01-05

Similar Documents

Publication Publication Date Title
WO2021088232A1 (zh) 一种碳化硅mosfet器件及其元胞结构
US8872264B2 (en) Semiconductor device having a floating semiconductor zone
US10388737B2 (en) Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) devices having an optimization layer
EP1699083B1 (en) Termination for SIC trench devices
TWI521718B (zh) 接面位障蕭特基二極體嵌於金氧半場效電晶體單元陣列之整合元件
CN112234095B (zh) 含有增强元胞设计的功率mosfet器件
WO2021088231A1 (zh) 碳化硅mosfet器件的元胞结构及碳化硅mosfet器件
CN114937693B (zh) 一种具有双沟道二极管的沟槽栅SiC MOSFET器件及其制备方法
CN112786680B (zh) 一种碳化硅mosfet器件的元胞结构及功率半导体器件
WO2016101134A1 (zh) 一种双向mos型器件及其制造方法
CN109768090A (zh) 一种具有内嵌异质结二极管自保护的碳化硅槽型场氧功率mos器件
CN204130542U (zh) 功率半导体器件
WO2021128748A1 (zh) 一种碳化硅mosfet器件的元胞结构及功率半导体器件
CN111933711B (zh) 一种集成sbd的超结mosfet
CN208422922U (zh) 一种优化开关速度的沟槽栅超结半导体器件
KR102572266B1 (ko) 실리콘 카바이드 소자
CN213366599U (zh) 带有栅极沟槽结构的碳化硅mosfet
CN204885170U (zh) 具有自适应性的场截止电流控制型功率器件
CN113053992B (zh) 一种碳化硅mosfet器件的元胞结构及功率半导体器件
CN110828555A (zh) 一种非对称异质结碳化硅槽型场氧功率mos器件
US20240097050A1 (en) Semiconductor device and fabrication method thereof
CN212342640U (zh) 沟槽mos场效应晶体管
CN219873542U (zh) 一种沟槽型mosfet器件
CN212161822U (zh) 功率mosfet器件
CN211654830U (zh) 沟槽型大功率mosfet器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20904406

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20904406

Country of ref document: EP

Kind code of ref document: A1