WO2021124991A1 - Procédé de fabrication de cellule solaire - Google Patents

Procédé de fabrication de cellule solaire Download PDF

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Publication number
WO2021124991A1
WO2021124991A1 PCT/JP2020/045730 JP2020045730W WO2021124991A1 WO 2021124991 A1 WO2021124991 A1 WO 2021124991A1 JP 2020045730 W JP2020045730 W JP 2020045730W WO 2021124991 A1 WO2021124991 A1 WO 2021124991A1
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semiconductor layer
layer
surface side
material film
forming step
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PCT/JP2020/045730
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English (en)
Japanese (ja)
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真悟 渡邉
末崎　恭
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株式会社カネカ
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Priority to JP2021565502A priority Critical patent/JP7365430B2/ja
Priority to CN202080088050.3A priority patent/CN114830357B/zh
Publication of WO2021124991A1 publication Critical patent/WO2021124991A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Definitions

  • the present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell.
  • Patent Document 1 discloses a back electrode type solar cell.
  • a back electrode type solar cell includes a semiconductor substrate that functions as a photoelectric conversion layer, and a first intrinsic semiconductor layer, a first conductive semiconductor layer, and a first electrode that are sequentially laminated on a part of the back surface side of the semiconductor substrate.
  • a layer and a second intrinsic semiconductor layer, a second conductive semiconductor layer, and a second electrode layer, which are sequentially laminated on the other part on the back surface side of the semiconductor substrate, are provided.
  • this solar cell includes a third intrinsic semiconductor layer and an optical adjustment layer which are sequentially laminated on the light receiving surface side of the semiconductor substrate.
  • an etching method using a photolithography technique is used.
  • photolithography technology for example, photoresist coating by spin coating, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using a photoresist as a mask, and photoresist peeling can be performed. A process was required and the process was complicated.
  • Patent Document 1 describes a technique for simplifying the patterning process by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning.
  • the inventors of the present application have devised to use a pattern printing resist by a pattern printing method in the first patterning. As a result, the number of exposure and development steps can be reduced as compared with the case of using the photoresist (photolithography method) by the spin coating method, and the patterning process can be further simplified.
  • the third intrinsic semiconductor layer on the light receiving surface side of the semiconductor substrate is formed before the patterning (first patterning) of the first conductive type semiconductor layer. Then, in the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light receiving surface side of the semiconductor substrate as well as the back surface side to protect the third intrinsic semiconductor layer from the etching solution.
  • the thermal history of the pattern print resist on the back side becomes twice.
  • the pattern print resist on the back side is difficult to peel off. Therefore, the pattern print resist on the back side is left unpeeled.
  • the third intrinsic semiconductor layer on the light receiving surface side of the semiconductor substrate is formed before the patterning of the first conductive type semiconductor layer (first patterning), the third intrinsic semiconductor layer is damaged in the subsequent manufacturing process. It ends up.
  • An object of the present invention is to provide a method for manufacturing a solar cell, which reduces the peeling residue of a pattern printing resist and reduces the damage of the third intrinsic semiconductor layer in the manufacturing process.
  • the method for manufacturing a solar cell according to the present invention includes a semiconductor substrate, a first intrinsic semiconductor layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a first intrinsic semiconductor layer.
  • the first conductive semiconductor layer, the second intrinsic semiconductor layer and the second conductive semiconductor layer sequentially laminated in the second region which is another part on the other main surface side of the semiconductor substrate, and the semiconductor substrate.
  • a method for manufacturing a back-contact type solar cell including a third intrinsic semiconductor layer laminated on one main surface side, wherein a material film of the first intrinsic semiconductor layer is formed on the other main surface side of the semiconductor substrate.
  • the first semiconductor layer material film forming step of forming the material film of the first conductive semiconductor layer, and the material film of the first conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate A resist forming step of forming a pattern printing resist on the semiconductor substrate and not forming a pattern printing resist on the one main surface side of the semiconductor substrate, and using the pattern printing resist to form the other main surface side of the semiconductor substrate.
  • the pattern is patterned in the first region on the other main surface side of the semiconductor substrate.
  • the third semiconductor layer forming step of forming the semiconductor layer and the process of forming the semiconductor layer are included in this order.
  • the present invention in the method for manufacturing a solar cell, it is possible to reduce the peeling residue of the pattern printing resist, and it is possible to reduce the damage to the third intrinsic semiconductor layer in the manufacturing process.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is a figure which shows the 1st semiconductor layer material film forming process, the temporary semiconductor layer forming process, and the lift-off layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the resist forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the resist removal process in the manufacturing method of the solar cell which concerns on this embodiment.
  • FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the rear side.
  • the solar cell 1 shown in FIG. 1 is a back electrode type (also referred to as a back contact type or back surface bonding type) solar cell.
  • the solar cell 1 includes an n-type (second conductive type) semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
  • the first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to the comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth.
  • the bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
  • the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth.
  • the bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
  • the finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
  • the first region 7 and the second region 8 may be formed in a striped shape.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG.
  • the solar cell 1 is an intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 laminated in order on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side.
  • the solar cell 1 is an intrinsic semiconductor layer laminated in order on a part of the back surface side (mainly, the first region 7) which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. It includes a (first intrinsic semiconductor layer) 23, a p-type (first conductive type) semiconductor layer 25, and a first electrode layer 27.
  • the solar cell 1 has an intrinsic semiconductor layer (second intrinsic semiconductor layer) 33, n-type (second conductive) laminated in order on another part (mainly, the second region 8) on the back surface side of the semiconductor substrate 11.
  • Type A semiconductor layer 35 and a second electrode layer 37 are provided.
  • the semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon.
  • the semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
  • the semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
  • the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the recovery efficiency of light that has passed through without being absorbed by the semiconductor substrate 11 is increased.
  • the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect on the semiconductor substrate 11 is improved.
  • the intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layers 13, 23, 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
  • the intrinsic semiconductor layers 13, 23, 33 function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the carrier recovery efficiency.
  • the optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11.
  • the optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light, and also functions as a protective layer for protecting the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13.
  • the optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
  • the p-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the p-type semiconductor layer 25 is formed of, for example, an amorphous silicon material.
  • the p-type semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
  • the n-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the n-type semiconductor layer 35 is formed of, for example, an amorphous silicon material.
  • the n-type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
  • the first electrode layer 27 is formed on the p-type semiconductor layer 25, and the second electrode layer 37 is formed on the n-type semiconductor layer 35.
  • the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 that are sequentially laminated on the p-type semiconductor layer 25.
  • the second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 which are sequentially laminated on the n-type semiconductor layer 35.
  • the transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide).
  • the metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.
  • the inventors of the present application have devised the use of a pattern printing resist by a pattern printing method in the patterning of the p-type semiconductor layer (first patterning). As a result, the number of exposure and development steps can be reduced as compared with the case of using the photoresist (photolithography method) by the spin coating method, and the manufacturing process of the solar cell can be simplified.
  • pattern printing is not printing that goes through processes such as exposure and development after forming a resist film (non-patterned resist film) before patterning, as in the photolithography method, but screen printing or gravure. It means a printing method in which a patterned resist (printing material) is directly adhered to a resist adhering surface such as press printing such as printing or ejection printing such as inkjet printing. Further, the pattern printing resist means a printing material (resist material) used for pattern printing.
  • the inventors of the present application have devised to adopt an inexpensive alkaline solution as a solution for removing the pattern printing resist in the patterning of the p-type semiconductor layer. This makes it possible to reduce the cost of the solar cell.
  • the inventors of the present application have devised to adopt a lift-off method using a lift-off layer (sacrificial layer) in the patterning of the n-type semiconductor layer (second patterning). This makes it possible to simplify the manufacturing process of solar cells.
  • the inventors of the present application have devised a two-layer structure in which the lift-off layer has a lower layer and an upper layer having characteristics for an acidic solution as shown below.
  • the upper layer which has a slow etching rate, etches while suppressing the peeling of the lift-off layer in the substrate cleaning step after patterning the p-type semiconductor layer (first patterning).
  • the high-speed lower layer makes it possible to improve the lift-off property in the lift-off step of patterning the n-type semiconductor layer (second patterning).
  • the inventors of the present application have devised the use of a metal electrode layer as a mask in the patterning of the transparent electrode layer. As a result, it is not necessary to use a resist obtained by a photolithography method or the like as a mask, and the solar cell manufacturing process can be simplified.
  • FIG. 4A is a diagram showing a first semiconductor layer material film forming step, a third semiconductor layer forming step, and a lift-off layer forming step in the method for manufacturing a solar cell of Comparative Example
  • FIG. 4B is a diagram showing manufacturing of a solar cell of Comparative Example. It is a figure which shows the resist forming process in the method.
  • FIG. 4C is a diagram showing a first semiconductor layer forming step in the solar cell manufacturing method of the comparative example, and FIG.
  • FIG. 4D is a diagram showing a resist removing step in the solar cell manufacturing method of the comparative example.
  • FIG. 4E is a diagram showing a second semiconductor layer material film forming step in the solar cell manufacturing method of the comparative example
  • FIG. 4F shows a second semiconductor layer forming step in the solar cell manufacturing method of the comparative example. It is a figure.
  • FIG. 4G is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method of the comparative example
  • FIGS. 4H and 4I are diagrams showing an electrode layer forming step in the solar cell manufacturing method of the comparative example. is there.
  • the entire surface of the back surface side of the semiconductor substrate 11X having a concavo-convex structure (texture structure) on the light receiving surface side and / or the back surface side is applied.
  • the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX are laminated (film-formed) in this order (first semiconductor layer material film forming step).
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X is laminated (film-formed) on the entire surface of the semiconductor substrate 11X on the light receiving surface side (third semiconductor layer forming step).
  • the order of film formation of the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer 13X is not limited.
  • a lift-off layer (sacrificial layer) 41X is laminated (film-formed) on the entire surface of the semiconductor substrate 11X on the back surface side, specifically, on the entire surface of the p-type semiconductor layer material film 25ZX. (Lift-off layer forming process).
  • the lift-off layer 41X is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).
  • the film thickness of the lift-off layer 41X is preferably, for example, 1 nm or more and 1 ⁇ m or less.
  • the lift-off layer 41X may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11X side.
  • the lower and upper layers have properties for acidic solutions as shown below.
  • the value of x when the main component is expressed as SiOx satisfies the following relational expression.
  • the lift-off layer 41X, the p-type semiconductor layer material film 25ZX, and the intrinsic semiconductor layer material in the second region 8 on the back surface side of the semiconductor substrate 11X using the pattern printing resist 90X By removing the film 23ZX, a patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23X, a p-type semiconductor layer 25X, and a lift-off layer 41X are formed in the first region 7.
  • a pattern printing resist 90X is applied on the p-type semiconductor layer material film 25ZX and the lift-off layer 41X in the first region 7 by using a pattern printing method.
  • Form resist forming step
  • a pattern printing resist 90X is formed on the entire surface of the semiconductor substrate 11X on the light receiving surface side by using a pattern printing method (resist forming step).
  • the film thickness of the pattern print resist is, for example, 1 ⁇ m or more and 50 ⁇ m or less.
  • the lift-off layer 41X in the second region 8 is etched on the back surface side of the semiconductor substrate 11X using the pattern printing resist 90X as a mask, whereby the lift-off patterned in the first region 7 is performed.
  • Layer 41X is formed.
  • an acidic solution such as hydrofluoric acid is used.
  • the pattern printing resist 90X as a mask, the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX in the second region 8 are etched on the back surface side of the semiconductor substrate 11X to form a pattern in the first region 7.
  • the formed intrinsic semiconductor layer 23X and the p-type semiconductor layer 25X are formed (first semiconductor layer forming step).
  • the etching solution for the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX for example, an acidic solution such as a mixed solution in which ozone is dissolved in hydrofluoric acid is used.
  • the pattern printing resist 90X on the back surface side and the light receiving surface side is removed (resist removing step).
  • etching solution for the pattern printing resist 90X an inexpensive alkaline solution such as KOH is used (cost reduction). At this time, a second problem arises (details will be described later).
  • first cleaning step clean both sides of the semiconductor substrate 11X (first cleaning step).
  • ozone treatment is followed by hydrofluoric acid treatment.
  • the hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid containing another kind of acid (for example, hydrochloric acid in the first washing step).
  • peeling of the lift-off layer 41X can be suppressed by the upper layer having a slow etching rate in the lift-off layer 41X.
  • a second problem arises (details will be described later).
  • the intrinsic semiconductor layer is formed on the entire surface of the back surface side of the semiconductor substrate 11X, specifically on the lift-off layer 41X in the first region 7 and on the second region 8.
  • the material film 33ZX and the n-type semiconductor layer material film 35ZX are laminated (film-formed) in order (second semiconductor layer material film forming step).
  • the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer in the first region 7 on the back surface side of the semiconductor substrate 11X by using the lift-off method using the lift-off layer (sacrificial layer).
  • a patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33X and an n-type semiconductor layer 35X are formed in the second region 8 (second semiconductor layer forming step).
  • the lift-off layer 41X by removing the lift-off layer 41X, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX on the lift-off layer 41X are removed, and the intrinsic semiconductor layer 33X and the n-type semiconductor are removed in the second region 8.
  • Layer 35X is formed.
  • an acidic solution such as hydrofluoric acid is used. At this time, the lift-off property can be improved by the lower layer having a high etching rate in the lift-off layer 41X.
  • the optical adjustment layer 15X is formed on the entire surface of the semiconductor substrate 11X on the light receiving surface side (optical adjustment layer forming step).
  • the first electrode layer 27X and the second electrode layer 37X are formed on the back surface side of the semiconductor substrate 11X (electrode layer forming step). Specifically, for example, by using a PVD method (physical vapor deposition method) such as a sputtering method, these are placed on the first conductive semiconductor layer 25X and the second conductive semiconductor layer 35X on the back surface side of the semiconductor substrate 11X.
  • the transparent electrode layer material film 28ZX is laminated (film-formed) across the (transparent electrode layer material film forming step).
  • a metal electrode layer 29X is formed on the first conductive semiconductor layer 25X via the transparent electrode layer material film 28ZX, and a second metal electrode layer 29X is formed via the transparent electrode layer material film 28ZX.
  • a metal electrode layer 39X is formed on the conductive semiconductor layer 35X (metal electrode layer forming step).
  • the metal electrode layer 29X and the metal electrode layer 39X as masks and patterning the transparent electrode layer material film 28ZX, the first transparent electrode layer 28X and the second transparent electrode layer 38X separated from each other are formed ( Transparent electrode layer forming step).
  • the etching solution for the transparent electrode layer material film 28ZX for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • the transparent electrode layer is formed (patterned) after the formation of the transparent electrode layer material film and before the formation of the metal electrode layer.
  • the transparent electrode layer material film is patterned by using a photolithography method to form a first transparent electrode layer and a second transparent electrode layer separated from each other.
  • photolithography ⁇ Apply resist on the transparent electrode layer material film and ⁇ By exposing the resist to light, an opening is formed in the resist. -By etching the transparent electrode layer material film exposed at the opening using a resist as a mask, a first transparent electrode layer and a second transparent electrode layer separated from each other are formed. -Remove the resist.
  • the formation of the metal electrode layer and the formation (patterning) of the transparent electrode layer are included in this order, and the transparent electrode layer is formed.
  • the first transparent electrode layer 28X and the second transparent electrode layer 28X and the second transparent electrode layer separated from each other by patterning the transparent electrode layer material film 28ZX using the first metal electrode layer 29X and the second metal electrode layer 39X as masks.
  • the electrode layer 38X is formed.
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X on the light receiving surface side is formed before the first semiconductor layer forming step (first patterning). Then, in the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light receiving surface side as well as the back surface side to protect the intrinsic semiconductor layer 13X from the etching solution and to protect the intrinsic semiconductor layer 13X. Was left.
  • the intrinsic semiconductor layer 13X on the light receiving surface side is formed before the first semiconductor layer forming step (first patterning), the intrinsic semiconductor layer 13X will be damaged in the subsequent manufacturing process.
  • the intrinsic semiconductor layer 13X on the light receiving surface side is damaged by the contact with the pattern printing resist, the contact with the resist stripping solution (alkali solution), and the contact with the cleaning solution (hydrofluoric acid).
  • the inventors of the present application did not form a pattern printing resist on the light receiving surface side in the resist forming step for the first semiconductor layer forming step (first patterning), and the first semiconductor layer.
  • the temporary intrinsic semiconductor layer on the light receiving surface side formed at this stage is peeled off.
  • the second semiconductor layer material film forming step it is devised to re-form the intrinsic semiconductor layer on the light receiving surface side.
  • FIG. 3A is a diagram showing a first semiconductor layer material film forming step, a temporary semiconductor layer forming step, and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIG. 3B is a diagram showing a solar cell according to the present embodiment. It is a figure which shows the resist forming process in the manufacturing method of a battery.
  • FIG. 3C is a diagram showing a first semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG.
  • FIG. 3D is a diagram showing a resist removing step in the solar cell manufacturing method according to the present embodiment. Is. Further, FIG. 3E is a diagram showing a second semiconductor layer material film forming step and a third semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 3F is a diagram showing the solar cell according to the present embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method. Further, FIG. 3G is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method according to the present embodiment, and FIGS. 3H and 3I are electrodes layer forming steps in the solar cell manufacturing method according to the present embodiment. It is a figure which shows.
  • the p-type semiconductor layer material film 25Z is laminated (film-formed) in order (first semiconductor layer material film forming step).
  • a temporary semiconductor layer 13Z may be laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by using a CVD method (temporary semiconductor layer forming step).
  • the temporary semiconductor layer 13Z is, for example, an intrinsic semiconductor layer.
  • an contamination source organic substance or the like
  • the temporary semiconductor layer 13Z on the light receiving surface side does not have to be formed.
  • the order of film formation of the intrinsic semiconductor layer material film 23Z and the p-type semiconductor layer material film 25Z and the temporary semiconductor layer 13Z is not limited.
  • a lift-off layer (sacrificial layer) 41 is laminated (film-formed) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the p-type semiconductor layer material film 25Z. (Lift-off layer forming process).
  • the lift-off layer 41 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).
  • the film thickness of the lift-off layer 41 is preferably, for example, 1 nm or more and 1 ⁇ m or less.
  • the lift-off layer 41 may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11 side.
  • the lower and upper layers have properties for acidic solutions as shown below.
  • Etching rate of upper layer when the lift-off layer 41 is a film containing silicon oxide as a main component, the value of x when the main component is expressed as SiOx satisfies the following relational expression.
  • the lift-off layer 41, the p-type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material in the second region 8 are used on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90.
  • a patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23, a p-type semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7.
  • the pattern printing resist 90 is applied on the p-type semiconductor layer material film 25Z and the lift-off layer 41 in the first region 7 by using a pattern printing method.
  • Form resist forming step
  • the film thickness of the pattern print resist 90 is, for example, 1 ⁇ m or more and 50 ⁇ m or less. According to the pattern printing resist using the pattern printing method, exposure and development of the resist in the photoresist (photolithography method) using the conventional spin coating method become unnecessary (simplification of the manufacturing process).
  • the pattern printed resist is not formed on the light receiving surface side of the semiconductor substrate 11 (resist forming step).
  • resist forming step it is not necessary to print and bake (dry) the pattern print resist 90 on the back side, and then print and bake (dry) the pattern print resist on the light receiving side, and the heat of the pattern print resist 90 on the back side does not need to be printed.
  • the history is once.
  • the thermal history of the pattern print resist 90 on the back side can be reduced, the difficulty of peeling the pattern print resist 90 on the back side is reduced in the resist removing step described later, and the peeling residue of the pattern print resist 90 on the back side is reduced. Is reduced (first problem solution).
  • the pattern print resist is not formed on the light receiving surface side and the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described later, the intrinsic semiconductor layer 13 on the light receiving surface side is damaged by the contact with the pattern printing resist. There is no (solving the second problem).
  • the lift-off layer 41 in the second region 8 is etched on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90 as a mask, so that the lift-off layer patterned in the first region 7 is patterned.
  • the layer 41 is formed.
  • an acidic solution such as hydrofluoric acid is used.
  • the pattern printing resist 90 as a mask, the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z in the second region 8 are etched on the back surface side of the semiconductor substrate 11 to form a pattern in the first region 7.
  • the formed intrinsic semiconductor layer (first intrinsic semiconductor layer) 23 and the p-type semiconductor layer 25 are formed (first semiconductor layer forming step).
  • the etching solution for the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z for example, an acidic solution such as a mixed solution in which ozone is dissolved in hydrofluoric acid is used.
  • the temporary semiconductor layer 13Z formed on the light receiving surface side of the semiconductor substrate 11 is removed.
  • the pattern printing resist 90 is removed (resist removing step).
  • an inexpensive alkaline solution such as KOH is used (cost reduction).
  • first cleaning step both sides of the semiconductor substrate 11 are cleaned.
  • the hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid containing another kind of acid (for example, hydrochloric acid in the first washing step).
  • peeling of the lift-off layer 41 can be suppressed by the upper layer having a slow etching rate in the lift-off layer 41.
  • the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described later, there is no damage to the intrinsic semiconductor layer 13 on the light receiving surface side due to contact with the cleaning solution (hydrofluoric acid) (second).
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side, for example, by using the CVD method (third semiconductor). Layer formation step).
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer are placed on the entire surface of the back surface side of the semiconductor substrate 11, specifically on the lift-off layer 41 and the second region 8 in the first region 7.
  • the material films 35Z are laminated (film-formed) in order (second semiconductor layer material film forming step).
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer in the first region 7 on the back surface side of the semiconductor substrate 11 by using the lift-off method using the lift-off layer (sacrificial layer).
  • a patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33 and an n-type semiconductor layer 35 are formed in the second region 8 (second semiconductor layer forming step).
  • the lift-off layer 41 by removing the lift-off layer 41, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z on the lift-off layer 41 are removed, and the intrinsic semiconductor layer 33 and the n-type semiconductor are removed in the second region 8.
  • the layer 35 is formed.
  • an acidic solution such as hydrofluoric acid is used. At this time, the lift-off property can be improved by the lower layer having a high etching rate in the lift-off layer 41.
  • the optical adjustment layer 15 is formed on the entire surface of the semiconductor substrate 11 on the light receiving surface side (optical adjustment layer forming step).
  • the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
  • electrode layer forming step Specifically, for example, using a PVD method such as a sputtering method, a transparent electrode layer material straddles the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 on the back surface side of the semiconductor substrate 11.
  • the film 28Z is laminated (film-formed) (transparent electrode layer material film forming step).
  • a metal electrode layer 29 is formed on the first conductive semiconductor layer 25 via the transparent electrode layer material film 28Z, and a second metal electrode layer 29 is formed via the transparent electrode layer material film 28Z.
  • a metal electrode layer 39 is formed on the conductive semiconductor layer 35 (metal electrode layer forming step).
  • the metal electrode layer 29 and the metal electrode layer 39 as masks and patterning the transparent electrode layer material film 28Z, the first transparent electrode layer 28 and the second transparent electrode layer 38 separated from each other are formed (. Transparent electrode layer forming step).
  • the etching solution for the transparent electrode layer material film 28Z for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.
  • the pattern printing resist is not formed on the light receiving surface side, so that the pattern printing on the back surface side is performed.
  • the thermal history of the pattern printing resist 90 on the back surface side is one.
  • the thermal history of the pattern printing resist 90 on the back surface side can be reduced, and the difficulty of peeling off the pattern printing resist 90 on the back surface side is reduced. Therefore, the peeling residue of the pattern print resist 90 on the back surface side is reduced. There is no peeling residue of the pattern print resist on the light receiving surface side.
  • the first semiconductor layer forming step (first patterning) is performed.
  • the temporary semiconductor layer 13Z on the light receiving surface side formed before the patterning) is removed.
  • the second semiconductor layer forming step (second patterning)
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 on the light receiving surface side is re-formed. As a result, it is possible to prevent the intrinsic semiconductor layer 13 on the light receiving surface side from being damaged in the manufacturing process.
  • the intrinsic semiconductor layer 13 on the light receiving surface side is damaged. Is suppressed. As a result, the performance of the solar cell is improved.
  • the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made.
  • the first conductive semiconductor layer 25 is a p-type semiconductor layer and the second conductive semiconductor layer 35 is an n-type semiconductor layer, but the first conductive semiconductor layer 25 is an n-type semiconductor layer.
  • the second conductive type semiconductor layer 35 may be replaced with a p-type semiconductor layer.
  • the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.
  • the n-type semiconductor substrate is exemplified as the semiconductor substrate 11, but the semiconductor substrate 11 is a p-type semiconductor in which a p-type dopant (for example, the above-mentioned boron (B)) is doped in a crystalline silicon material. It may be a substrate.
  • a p-type dopant for example, the above-mentioned boron (B)
  • B boron
  • a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this.
  • a solar cell may have a gallium arsenide (GaAs) substrate.
  • GaAs gallium arsenide

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

La présente invention aborde le problème de fournir un procédé de fabrication de cellule solaire qui réduit les résidus de pelage d'une réserve d'impression de motifs ainsi que l'endommagement d'une troisième couche semi-conductrice intrinsèque pendant le processus de fabrication. Le procédé de fabrication de cellule solaire selon la présente invention comprend, dans cet ordre : une étape consistant à former, sur un côté surface arrière d'un substrat semi-conducteur (11), un film de matériau destiné à une première couche semi-conductrice intrinsèque et un film de matériau destiné à une couche semi-conductrice d'un premier type de conductivité ; une étape consistant à former une réserve d'impression de motifs sur le film de matériau destiné à la couche semi-conductrice du premier type de conductivité dans une première région (7) sur le côté surface arrière du substrat semi-conducteur (11), et à ne pas former la réserve d'impression de motifs sur un côté surface de réception de lumière du substrat semi-conducteur (11) ; une étape consistant à former, à l'aide de la réserve d'impression de motifs dans la première région (7) sur le côté surface arrière du substrat semi-conducteur (11), une première couche semi-conductrice intrinsèque (23) et une couche semi-conductrice du premier type de conductivité (25) qui sont structurées ; une étape consistant à éliminer la réserve d'impression de motifs ; et une étape consistant à former une troisième couche semi-conductrice intrinsèque (13) sur le côté surface de réception de lumière du substrat semi-conducteur (11).
PCT/JP2020/045730 2019-12-19 2020-12-08 Procédé de fabrication de cellule solaire WO2021124991A1 (fr)

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Citations (6)

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JP2012089829A (ja) * 2010-09-21 2012-05-10 Rohm & Haas Electronic Materials Llc 半導体上からホットメルトエッチングレジストを剥離する改良された方法
JP2013509695A (ja) * 2009-10-30 2013-03-14 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング 選択エミッタを含む、ソーラーセルの製造のための工程
JP2013239476A (ja) * 2012-05-11 2013-11-28 Mitsubishi Electric Corp 光起電力装置およびその製造方法、光起電力モジュール
WO2015189878A1 (fr) * 2014-06-13 2015-12-17 国立大学法人福島大学 Cellule solaire et son procédé de fabrication
US20180198002A1 (en) * 2017-01-06 2018-07-12 Lg Electronics Inc. Method for manufacturing solar cell
WO2019216339A1 (fr) * 2018-05-08 2019-11-14 株式会社カネカ Procédé de fabrication d'une cellule solaire, et support utilisé pour celui-ci

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Publication number Priority date Publication date Assignee Title
JP2014075526A (ja) * 2012-10-05 2014-04-24 Sharp Corp 光電変換素子および光電変換素子の製造方法
JP2018163999A (ja) * 2017-03-27 2018-10-18 国立大学法人福島大学 太陽電池およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013509695A (ja) * 2009-10-30 2013-03-14 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング 選択エミッタを含む、ソーラーセルの製造のための工程
JP2012089829A (ja) * 2010-09-21 2012-05-10 Rohm & Haas Electronic Materials Llc 半導体上からホットメルトエッチングレジストを剥離する改良された方法
JP2013239476A (ja) * 2012-05-11 2013-11-28 Mitsubishi Electric Corp 光起電力装置およびその製造方法、光起電力モジュール
WO2015189878A1 (fr) * 2014-06-13 2015-12-17 国立大学法人福島大学 Cellule solaire et son procédé de fabrication
US20180198002A1 (en) * 2017-01-06 2018-07-12 Lg Electronics Inc. Method for manufacturing solar cell
WO2019216339A1 (fr) * 2018-05-08 2019-11-14 株式会社カネカ Procédé de fabrication d'une cellule solaire, et support utilisé pour celui-ci

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CN114830357B (zh) 2024-03-15

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