WO2021124991A1 - Solar cell manufacturing method - Google Patents

Solar cell manufacturing method Download PDF

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Publication number
WO2021124991A1
WO2021124991A1 PCT/JP2020/045730 JP2020045730W WO2021124991A1 WO 2021124991 A1 WO2021124991 A1 WO 2021124991A1 JP 2020045730 W JP2020045730 W JP 2020045730W WO 2021124991 A1 WO2021124991 A1 WO 2021124991A1
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Prior art keywords
semiconductor layer
layer
surface side
material film
forming step
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PCT/JP2020/045730
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French (fr)
Japanese (ja)
Inventor
真悟 渡邉
末崎　恭
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株式会社カネカ
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Priority to CN202080088050.3A priority Critical patent/CN114830357B/en
Priority to JP2021565502A priority patent/JP7365430B2/en
Publication of WO2021124991A1 publication Critical patent/WO2021124991A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Definitions

  • the present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell.
  • Patent Document 1 discloses a back electrode type solar cell.
  • a back electrode type solar cell includes a semiconductor substrate that functions as a photoelectric conversion layer, and a first intrinsic semiconductor layer, a first conductive semiconductor layer, and a first electrode that are sequentially laminated on a part of the back surface side of the semiconductor substrate.
  • a layer and a second intrinsic semiconductor layer, a second conductive semiconductor layer, and a second electrode layer, which are sequentially laminated on the other part on the back surface side of the semiconductor substrate, are provided.
  • this solar cell includes a third intrinsic semiconductor layer and an optical adjustment layer which are sequentially laminated on the light receiving surface side of the semiconductor substrate.
  • an etching method using a photolithography technique is used.
  • photolithography technology for example, photoresist coating by spin coating, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using a photoresist as a mask, and photoresist peeling can be performed. A process was required and the process was complicated.
  • Patent Document 1 describes a technique for simplifying the patterning process by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning.
  • the inventors of the present application have devised to use a pattern printing resist by a pattern printing method in the first patterning. As a result, the number of exposure and development steps can be reduced as compared with the case of using the photoresist (photolithography method) by the spin coating method, and the patterning process can be further simplified.
  • the third intrinsic semiconductor layer on the light receiving surface side of the semiconductor substrate is formed before the patterning (first patterning) of the first conductive type semiconductor layer. Then, in the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light receiving surface side of the semiconductor substrate as well as the back surface side to protect the third intrinsic semiconductor layer from the etching solution.
  • the thermal history of the pattern print resist on the back side becomes twice.
  • the pattern print resist on the back side is difficult to peel off. Therefore, the pattern print resist on the back side is left unpeeled.
  • the third intrinsic semiconductor layer on the light receiving surface side of the semiconductor substrate is formed before the patterning of the first conductive type semiconductor layer (first patterning), the third intrinsic semiconductor layer is damaged in the subsequent manufacturing process. It ends up.
  • An object of the present invention is to provide a method for manufacturing a solar cell, which reduces the peeling residue of a pattern printing resist and reduces the damage of the third intrinsic semiconductor layer in the manufacturing process.
  • the method for manufacturing a solar cell according to the present invention includes a semiconductor substrate, a first intrinsic semiconductor layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a first intrinsic semiconductor layer.
  • the first conductive semiconductor layer, the second intrinsic semiconductor layer and the second conductive semiconductor layer sequentially laminated in the second region which is another part on the other main surface side of the semiconductor substrate, and the semiconductor substrate.
  • a method for manufacturing a back-contact type solar cell including a third intrinsic semiconductor layer laminated on one main surface side, wherein a material film of the first intrinsic semiconductor layer is formed on the other main surface side of the semiconductor substrate.
  • the first semiconductor layer material film forming step of forming the material film of the first conductive semiconductor layer, and the material film of the first conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate A resist forming step of forming a pattern printing resist on the semiconductor substrate and not forming a pattern printing resist on the one main surface side of the semiconductor substrate, and using the pattern printing resist to form the other main surface side of the semiconductor substrate.
  • the pattern is patterned in the first region on the other main surface side of the semiconductor substrate.
  • the third semiconductor layer forming step of forming the semiconductor layer and the process of forming the semiconductor layer are included in this order.
  • the present invention in the method for manufacturing a solar cell, it is possible to reduce the peeling residue of the pattern printing resist, and it is possible to reduce the damage to the third intrinsic semiconductor layer in the manufacturing process.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is a figure which shows the 1st semiconductor layer material film forming process, the temporary semiconductor layer forming process, and the lift-off layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the resist forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the resist removal process in the manufacturing method of the solar cell which concerns on this embodiment.
  • FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the rear side.
  • the solar cell 1 shown in FIG. 1 is a back electrode type (also referred to as a back contact type or back surface bonding type) solar cell.
  • the solar cell 1 includes an n-type (second conductive type) semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
  • the first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to the comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth.
  • the bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
  • the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth.
  • the bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
  • the finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
  • the first region 7 and the second region 8 may be formed in a striped shape.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG.
  • the solar cell 1 is an intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 laminated in order on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side.
  • the solar cell 1 is an intrinsic semiconductor layer laminated in order on a part of the back surface side (mainly, the first region 7) which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. It includes a (first intrinsic semiconductor layer) 23, a p-type (first conductive type) semiconductor layer 25, and a first electrode layer 27.
  • the solar cell 1 has an intrinsic semiconductor layer (second intrinsic semiconductor layer) 33, n-type (second conductive) laminated in order on another part (mainly, the second region 8) on the back surface side of the semiconductor substrate 11.
  • Type A semiconductor layer 35 and a second electrode layer 37 are provided.
  • the semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon.
  • the semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
  • the semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
  • the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the recovery efficiency of light that has passed through without being absorbed by the semiconductor substrate 11 is increased.
  • the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect on the semiconductor substrate 11 is improved.
  • the intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layers 13, 23, 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
  • the intrinsic semiconductor layers 13, 23, 33 function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the carrier recovery efficiency.
  • the optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11.
  • the optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light, and also functions as a protective layer for protecting the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13.
  • the optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
  • the p-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the p-type semiconductor layer 25 is formed of, for example, an amorphous silicon material.
  • the p-type semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
  • the n-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the n-type semiconductor layer 35 is formed of, for example, an amorphous silicon material.
  • the n-type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
  • the first electrode layer 27 is formed on the p-type semiconductor layer 25, and the second electrode layer 37 is formed on the n-type semiconductor layer 35.
  • the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 that are sequentially laminated on the p-type semiconductor layer 25.
  • the second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 which are sequentially laminated on the n-type semiconductor layer 35.
  • the transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide).
  • the metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.
  • the inventors of the present application have devised the use of a pattern printing resist by a pattern printing method in the patterning of the p-type semiconductor layer (first patterning). As a result, the number of exposure and development steps can be reduced as compared with the case of using the photoresist (photolithography method) by the spin coating method, and the manufacturing process of the solar cell can be simplified.
  • pattern printing is not printing that goes through processes such as exposure and development after forming a resist film (non-patterned resist film) before patterning, as in the photolithography method, but screen printing or gravure. It means a printing method in which a patterned resist (printing material) is directly adhered to a resist adhering surface such as press printing such as printing or ejection printing such as inkjet printing. Further, the pattern printing resist means a printing material (resist material) used for pattern printing.
  • the inventors of the present application have devised to adopt an inexpensive alkaline solution as a solution for removing the pattern printing resist in the patterning of the p-type semiconductor layer. This makes it possible to reduce the cost of the solar cell.
  • the inventors of the present application have devised to adopt a lift-off method using a lift-off layer (sacrificial layer) in the patterning of the n-type semiconductor layer (second patterning). This makes it possible to simplify the manufacturing process of solar cells.
  • the inventors of the present application have devised a two-layer structure in which the lift-off layer has a lower layer and an upper layer having characteristics for an acidic solution as shown below.
  • the upper layer which has a slow etching rate, etches while suppressing the peeling of the lift-off layer in the substrate cleaning step after patterning the p-type semiconductor layer (first patterning).
  • the high-speed lower layer makes it possible to improve the lift-off property in the lift-off step of patterning the n-type semiconductor layer (second patterning).
  • the inventors of the present application have devised the use of a metal electrode layer as a mask in the patterning of the transparent electrode layer. As a result, it is not necessary to use a resist obtained by a photolithography method or the like as a mask, and the solar cell manufacturing process can be simplified.
  • FIG. 4A is a diagram showing a first semiconductor layer material film forming step, a third semiconductor layer forming step, and a lift-off layer forming step in the method for manufacturing a solar cell of Comparative Example
  • FIG. 4B is a diagram showing manufacturing of a solar cell of Comparative Example. It is a figure which shows the resist forming process in the method.
  • FIG. 4C is a diagram showing a first semiconductor layer forming step in the solar cell manufacturing method of the comparative example, and FIG.
  • FIG. 4D is a diagram showing a resist removing step in the solar cell manufacturing method of the comparative example.
  • FIG. 4E is a diagram showing a second semiconductor layer material film forming step in the solar cell manufacturing method of the comparative example
  • FIG. 4F shows a second semiconductor layer forming step in the solar cell manufacturing method of the comparative example. It is a figure.
  • FIG. 4G is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method of the comparative example
  • FIGS. 4H and 4I are diagrams showing an electrode layer forming step in the solar cell manufacturing method of the comparative example. is there.
  • the entire surface of the back surface side of the semiconductor substrate 11X having a concavo-convex structure (texture structure) on the light receiving surface side and / or the back surface side is applied.
  • the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX are laminated (film-formed) in this order (first semiconductor layer material film forming step).
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X is laminated (film-formed) on the entire surface of the semiconductor substrate 11X on the light receiving surface side (third semiconductor layer forming step).
  • the order of film formation of the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer 13X is not limited.
  • a lift-off layer (sacrificial layer) 41X is laminated (film-formed) on the entire surface of the semiconductor substrate 11X on the back surface side, specifically, on the entire surface of the p-type semiconductor layer material film 25ZX. (Lift-off layer forming process).
  • the lift-off layer 41X is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).
  • the film thickness of the lift-off layer 41X is preferably, for example, 1 nm or more and 1 ⁇ m or less.
  • the lift-off layer 41X may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11X side.
  • the lower and upper layers have properties for acidic solutions as shown below.
  • the value of x when the main component is expressed as SiOx satisfies the following relational expression.
  • the lift-off layer 41X, the p-type semiconductor layer material film 25ZX, and the intrinsic semiconductor layer material in the second region 8 on the back surface side of the semiconductor substrate 11X using the pattern printing resist 90X By removing the film 23ZX, a patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23X, a p-type semiconductor layer 25X, and a lift-off layer 41X are formed in the first region 7.
  • a pattern printing resist 90X is applied on the p-type semiconductor layer material film 25ZX and the lift-off layer 41X in the first region 7 by using a pattern printing method.
  • Form resist forming step
  • a pattern printing resist 90X is formed on the entire surface of the semiconductor substrate 11X on the light receiving surface side by using a pattern printing method (resist forming step).
  • the film thickness of the pattern print resist is, for example, 1 ⁇ m or more and 50 ⁇ m or less.
  • the lift-off layer 41X in the second region 8 is etched on the back surface side of the semiconductor substrate 11X using the pattern printing resist 90X as a mask, whereby the lift-off patterned in the first region 7 is performed.
  • Layer 41X is formed.
  • an acidic solution such as hydrofluoric acid is used.
  • the pattern printing resist 90X as a mask, the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX in the second region 8 are etched on the back surface side of the semiconductor substrate 11X to form a pattern in the first region 7.
  • the formed intrinsic semiconductor layer 23X and the p-type semiconductor layer 25X are formed (first semiconductor layer forming step).
  • the etching solution for the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX for example, an acidic solution such as a mixed solution in which ozone is dissolved in hydrofluoric acid is used.
  • the pattern printing resist 90X on the back surface side and the light receiving surface side is removed (resist removing step).
  • etching solution for the pattern printing resist 90X an inexpensive alkaline solution such as KOH is used (cost reduction). At this time, a second problem arises (details will be described later).
  • first cleaning step clean both sides of the semiconductor substrate 11X (first cleaning step).
  • ozone treatment is followed by hydrofluoric acid treatment.
  • the hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid containing another kind of acid (for example, hydrochloric acid in the first washing step).
  • peeling of the lift-off layer 41X can be suppressed by the upper layer having a slow etching rate in the lift-off layer 41X.
  • a second problem arises (details will be described later).
  • the intrinsic semiconductor layer is formed on the entire surface of the back surface side of the semiconductor substrate 11X, specifically on the lift-off layer 41X in the first region 7 and on the second region 8.
  • the material film 33ZX and the n-type semiconductor layer material film 35ZX are laminated (film-formed) in order (second semiconductor layer material film forming step).
  • the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer in the first region 7 on the back surface side of the semiconductor substrate 11X by using the lift-off method using the lift-off layer (sacrificial layer).
  • a patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33X and an n-type semiconductor layer 35X are formed in the second region 8 (second semiconductor layer forming step).
  • the lift-off layer 41X by removing the lift-off layer 41X, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX on the lift-off layer 41X are removed, and the intrinsic semiconductor layer 33X and the n-type semiconductor are removed in the second region 8.
  • Layer 35X is formed.
  • an acidic solution such as hydrofluoric acid is used. At this time, the lift-off property can be improved by the lower layer having a high etching rate in the lift-off layer 41X.
  • the optical adjustment layer 15X is formed on the entire surface of the semiconductor substrate 11X on the light receiving surface side (optical adjustment layer forming step).
  • the first electrode layer 27X and the second electrode layer 37X are formed on the back surface side of the semiconductor substrate 11X (electrode layer forming step). Specifically, for example, by using a PVD method (physical vapor deposition method) such as a sputtering method, these are placed on the first conductive semiconductor layer 25X and the second conductive semiconductor layer 35X on the back surface side of the semiconductor substrate 11X.
  • the transparent electrode layer material film 28ZX is laminated (film-formed) across the (transparent electrode layer material film forming step).
  • a metal electrode layer 29X is formed on the first conductive semiconductor layer 25X via the transparent electrode layer material film 28ZX, and a second metal electrode layer 29X is formed via the transparent electrode layer material film 28ZX.
  • a metal electrode layer 39X is formed on the conductive semiconductor layer 35X (metal electrode layer forming step).
  • the metal electrode layer 29X and the metal electrode layer 39X as masks and patterning the transparent electrode layer material film 28ZX, the first transparent electrode layer 28X and the second transparent electrode layer 38X separated from each other are formed ( Transparent electrode layer forming step).
  • the etching solution for the transparent electrode layer material film 28ZX for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • the transparent electrode layer is formed (patterned) after the formation of the transparent electrode layer material film and before the formation of the metal electrode layer.
  • the transparent electrode layer material film is patterned by using a photolithography method to form a first transparent electrode layer and a second transparent electrode layer separated from each other.
  • photolithography ⁇ Apply resist on the transparent electrode layer material film and ⁇ By exposing the resist to light, an opening is formed in the resist. -By etching the transparent electrode layer material film exposed at the opening using a resist as a mask, a first transparent electrode layer and a second transparent electrode layer separated from each other are formed. -Remove the resist.
  • the formation of the metal electrode layer and the formation (patterning) of the transparent electrode layer are included in this order, and the transparent electrode layer is formed.
  • the first transparent electrode layer 28X and the second transparent electrode layer 28X and the second transparent electrode layer separated from each other by patterning the transparent electrode layer material film 28ZX using the first metal electrode layer 29X and the second metal electrode layer 39X as masks.
  • the electrode layer 38X is formed.
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X on the light receiving surface side is formed before the first semiconductor layer forming step (first patterning). Then, in the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light receiving surface side as well as the back surface side to protect the intrinsic semiconductor layer 13X from the etching solution and to protect the intrinsic semiconductor layer 13X. Was left.
  • the intrinsic semiconductor layer 13X on the light receiving surface side is formed before the first semiconductor layer forming step (first patterning), the intrinsic semiconductor layer 13X will be damaged in the subsequent manufacturing process.
  • the intrinsic semiconductor layer 13X on the light receiving surface side is damaged by the contact with the pattern printing resist, the contact with the resist stripping solution (alkali solution), and the contact with the cleaning solution (hydrofluoric acid).
  • the inventors of the present application did not form a pattern printing resist on the light receiving surface side in the resist forming step for the first semiconductor layer forming step (first patterning), and the first semiconductor layer.
  • the temporary intrinsic semiconductor layer on the light receiving surface side formed at this stage is peeled off.
  • the second semiconductor layer material film forming step it is devised to re-form the intrinsic semiconductor layer on the light receiving surface side.
  • FIG. 3A is a diagram showing a first semiconductor layer material film forming step, a temporary semiconductor layer forming step, and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIG. 3B is a diagram showing a solar cell according to the present embodiment. It is a figure which shows the resist forming process in the manufacturing method of a battery.
  • FIG. 3C is a diagram showing a first semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG.
  • FIG. 3D is a diagram showing a resist removing step in the solar cell manufacturing method according to the present embodiment. Is. Further, FIG. 3E is a diagram showing a second semiconductor layer material film forming step and a third semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 3F is a diagram showing the solar cell according to the present embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method. Further, FIG. 3G is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method according to the present embodiment, and FIGS. 3H and 3I are electrodes layer forming steps in the solar cell manufacturing method according to the present embodiment. It is a figure which shows.
  • the p-type semiconductor layer material film 25Z is laminated (film-formed) in order (first semiconductor layer material film forming step).
  • a temporary semiconductor layer 13Z may be laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by using a CVD method (temporary semiconductor layer forming step).
  • the temporary semiconductor layer 13Z is, for example, an intrinsic semiconductor layer.
  • an contamination source organic substance or the like
  • the temporary semiconductor layer 13Z on the light receiving surface side does not have to be formed.
  • the order of film formation of the intrinsic semiconductor layer material film 23Z and the p-type semiconductor layer material film 25Z and the temporary semiconductor layer 13Z is not limited.
  • a lift-off layer (sacrificial layer) 41 is laminated (film-formed) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the p-type semiconductor layer material film 25Z. (Lift-off layer forming process).
  • the lift-off layer 41 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).
  • the film thickness of the lift-off layer 41 is preferably, for example, 1 nm or more and 1 ⁇ m or less.
  • the lift-off layer 41 may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11 side.
  • the lower and upper layers have properties for acidic solutions as shown below.
  • Etching rate of upper layer when the lift-off layer 41 is a film containing silicon oxide as a main component, the value of x when the main component is expressed as SiOx satisfies the following relational expression.
  • the lift-off layer 41, the p-type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material in the second region 8 are used on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90.
  • a patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23, a p-type semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7.
  • the pattern printing resist 90 is applied on the p-type semiconductor layer material film 25Z and the lift-off layer 41 in the first region 7 by using a pattern printing method.
  • Form resist forming step
  • the film thickness of the pattern print resist 90 is, for example, 1 ⁇ m or more and 50 ⁇ m or less. According to the pattern printing resist using the pattern printing method, exposure and development of the resist in the photoresist (photolithography method) using the conventional spin coating method become unnecessary (simplification of the manufacturing process).
  • the pattern printed resist is not formed on the light receiving surface side of the semiconductor substrate 11 (resist forming step).
  • resist forming step it is not necessary to print and bake (dry) the pattern print resist 90 on the back side, and then print and bake (dry) the pattern print resist on the light receiving side, and the heat of the pattern print resist 90 on the back side does not need to be printed.
  • the history is once.
  • the thermal history of the pattern print resist 90 on the back side can be reduced, the difficulty of peeling the pattern print resist 90 on the back side is reduced in the resist removing step described later, and the peeling residue of the pattern print resist 90 on the back side is reduced. Is reduced (first problem solution).
  • the pattern print resist is not formed on the light receiving surface side and the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described later, the intrinsic semiconductor layer 13 on the light receiving surface side is damaged by the contact with the pattern printing resist. There is no (solving the second problem).
  • the lift-off layer 41 in the second region 8 is etched on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90 as a mask, so that the lift-off layer patterned in the first region 7 is patterned.
  • the layer 41 is formed.
  • an acidic solution such as hydrofluoric acid is used.
  • the pattern printing resist 90 as a mask, the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z in the second region 8 are etched on the back surface side of the semiconductor substrate 11 to form a pattern in the first region 7.
  • the formed intrinsic semiconductor layer (first intrinsic semiconductor layer) 23 and the p-type semiconductor layer 25 are formed (first semiconductor layer forming step).
  • the etching solution for the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z for example, an acidic solution such as a mixed solution in which ozone is dissolved in hydrofluoric acid is used.
  • the temporary semiconductor layer 13Z formed on the light receiving surface side of the semiconductor substrate 11 is removed.
  • the pattern printing resist 90 is removed (resist removing step).
  • an inexpensive alkaline solution such as KOH is used (cost reduction).
  • first cleaning step both sides of the semiconductor substrate 11 are cleaned.
  • the hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid containing another kind of acid (for example, hydrochloric acid in the first washing step).
  • peeling of the lift-off layer 41 can be suppressed by the upper layer having a slow etching rate in the lift-off layer 41.
  • the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described later, there is no damage to the intrinsic semiconductor layer 13 on the light receiving surface side due to contact with the cleaning solution (hydrofluoric acid) (second).
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side, for example, by using the CVD method (third semiconductor). Layer formation step).
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer are placed on the entire surface of the back surface side of the semiconductor substrate 11, specifically on the lift-off layer 41 and the second region 8 in the first region 7.
  • the material films 35Z are laminated (film-formed) in order (second semiconductor layer material film forming step).
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer in the first region 7 on the back surface side of the semiconductor substrate 11 by using the lift-off method using the lift-off layer (sacrificial layer).
  • a patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33 and an n-type semiconductor layer 35 are formed in the second region 8 (second semiconductor layer forming step).
  • the lift-off layer 41 by removing the lift-off layer 41, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z on the lift-off layer 41 are removed, and the intrinsic semiconductor layer 33 and the n-type semiconductor are removed in the second region 8.
  • the layer 35 is formed.
  • an acidic solution such as hydrofluoric acid is used. At this time, the lift-off property can be improved by the lower layer having a high etching rate in the lift-off layer 41.
  • the optical adjustment layer 15 is formed on the entire surface of the semiconductor substrate 11 on the light receiving surface side (optical adjustment layer forming step).
  • the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
  • electrode layer forming step Specifically, for example, using a PVD method such as a sputtering method, a transparent electrode layer material straddles the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 on the back surface side of the semiconductor substrate 11.
  • the film 28Z is laminated (film-formed) (transparent electrode layer material film forming step).
  • a metal electrode layer 29 is formed on the first conductive semiconductor layer 25 via the transparent electrode layer material film 28Z, and a second metal electrode layer 29 is formed via the transparent electrode layer material film 28Z.
  • a metal electrode layer 39 is formed on the conductive semiconductor layer 35 (metal electrode layer forming step).
  • the metal electrode layer 29 and the metal electrode layer 39 as masks and patterning the transparent electrode layer material film 28Z, the first transparent electrode layer 28 and the second transparent electrode layer 38 separated from each other are formed (. Transparent electrode layer forming step).
  • the etching solution for the transparent electrode layer material film 28Z for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.
  • the pattern printing resist is not formed on the light receiving surface side, so that the pattern printing on the back surface side is performed.
  • the thermal history of the pattern printing resist 90 on the back surface side is one.
  • the thermal history of the pattern printing resist 90 on the back surface side can be reduced, and the difficulty of peeling off the pattern printing resist 90 on the back surface side is reduced. Therefore, the peeling residue of the pattern print resist 90 on the back surface side is reduced. There is no peeling residue of the pattern print resist on the light receiving surface side.
  • the first semiconductor layer forming step (first patterning) is performed.
  • the temporary semiconductor layer 13Z on the light receiving surface side formed before the patterning) is removed.
  • the second semiconductor layer forming step (second patterning)
  • the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 on the light receiving surface side is re-formed. As a result, it is possible to prevent the intrinsic semiconductor layer 13 on the light receiving surface side from being damaged in the manufacturing process.
  • the intrinsic semiconductor layer 13 on the light receiving surface side is damaged. Is suppressed. As a result, the performance of the solar cell is improved.
  • the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made.
  • the first conductive semiconductor layer 25 is a p-type semiconductor layer and the second conductive semiconductor layer 35 is an n-type semiconductor layer, but the first conductive semiconductor layer 25 is an n-type semiconductor layer.
  • the second conductive type semiconductor layer 35 may be replaced with a p-type semiconductor layer.
  • the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.
  • the n-type semiconductor substrate is exemplified as the semiconductor substrate 11, but the semiconductor substrate 11 is a p-type semiconductor in which a p-type dopant (for example, the above-mentioned boron (B)) is doped in a crystalline silicon material. It may be a substrate.
  • a p-type dopant for example, the above-mentioned boron (B)
  • B boron
  • a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this.
  • a solar cell may have a gallium arsenide (GaAs) substrate.
  • GaAs gallium arsenide

Abstract

The present invention addresses the problem of providing a solar cell manufacturing method that reduces peeling residue of a pattern printing resist, and that reduces damage to a third intrinsic semiconductor layer during the manufacturing process. The solar cell manufacturing method according to the present invention comprises, in this order: a step for forming, on a back surface side of a semiconductor substrate (11), a material film for a first intrinsic semiconductor layer and a material film for a first conductivity-type semiconductor layer; a step for forming a pattern printing resist on the material film for the first conductivity-type semiconductor layer in a first region (7) on the back surface side of the semiconductor substrate (11), and not forming the pattern printing resist on a light-receiving surface side of the semiconductor substrate (11); a step for forming, using the pattern printing resist in the first region (7) on the back surface side of the semiconductor substrate (11), a first intrinsic semiconductor layer (23) and a first conductivity-type semiconductor layer (25) that are patterned; a step for removing the pattern printing resist; and a step for forming a third intrinsic semiconductor layer (13) on the light-receiving surface side of the semiconductor substrate (11).

Description

太陽電池の製造方法How to manufacture solar cells
　本発明は、裏面電極型（バックコンタクト型）の太陽電池の製造方法に関する。 The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell.
　特許文献１には、裏面電極型の太陽電池が開示されている。このような裏面電極型の太陽電池は、光電変換層として機能する半導体基板と、半導体基板の裏面側の一部に順に積層された第１真性半導体層、第１導電型半導体層および第１電極層と、半導体基板の裏面側の他の一部に順に積層された第２真性半導体層、第２導電型半導体層および第２電極層とを備える。また、この太陽電池は、半導体基板の受光面側に順に積層された第３真性半導体層および光学調整層を備える。 Patent Document 1 discloses a back electrode type solar cell. Such a back electrode type solar cell includes a semiconductor substrate that functions as a photoelectric conversion layer, and a first intrinsic semiconductor layer, a first conductive semiconductor layer, and a first electrode that are sequentially laminated on a part of the back surface side of the semiconductor substrate. A layer and a second intrinsic semiconductor layer, a second conductive semiconductor layer, and a second electrode layer, which are sequentially laminated on the other part on the back surface side of the semiconductor substrate, are provided. Further, this solar cell includes a third intrinsic semiconductor layer and an optical adjustment layer which are sequentially laminated on the light receiving surface side of the semiconductor substrate.
　一般に、第１導電型半導体層のパターニング（１回目のパターニング）および第２導電型半導体層のパターニング（２回目のパターニング）において、フォトリソグラフィ技術を用いたエッチング法が用いられる。しかし、フォトリソグラフィ技術を用いたエッチング法では、例えばスピンコート法によるフォトレジスト塗布、フォトレジスト乾燥、フォトレジスト露光、フォトレジスト現像、フォトレジストをマスクとして用いた半導体層のエッチング、およびフォトレジスト剥離のプロセスが必要であり、プロセスが複雑であった。 Generally, in the patterning of the first conductive semiconductor layer (first patterning) and the patterning of the second conductive semiconductor layer (second patterning), an etching method using a photolithography technique is used. However, in the etching method using photolithography technology, for example, photoresist coating by spin coating, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using a photoresist as a mask, and photoresist peeling can be performed. A process was required and the process was complicated.
　この点に関し、特許文献１には、２回目のパターニングにおいて、リフトオフ層（犠牲層）を用いたリフトオフ法により、パターニングのプロセスの簡略化を図る技術が記載されている。 Regarding this point, Patent Document 1 describes a technique for simplifying the patterning process by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning.
特開２０１４－７５５２６号公報Japanese Unexamined Patent Publication No. 2014-75526
　本願発明者らは、１回目のパターニングにおいて、パターン印刷法によるパターン印刷レジストを用いることを考案している。これにより、スピンコート法によるフォトレジスト（フォトリソグラフィ法）を用いた場合と比較して、露光および現像の工程を削減することができ、パターニングのプロセスの更なる簡略化が可能となる。 The inventors of the present application have devised to use a pattern printing resist by a pattern printing method in the first patterning. As a result, the number of exposure and development steps can be reduced as compared with the case of using the photoresist (photolithography method) by the spin coating method, and the patterning process can be further simplified.
　ところで、半導体基板の受光面側の第３真性半導体層は、第１導電型半導体層のパターニング（１回目のパターニング）の前に製膜される。そして、第１半導体層形成工程（１回目のパターニング）では、裏面側と同様に、半導体基板の受光面側にもパターン印刷レジストを形成し、エッチング溶液から第３真性半導体層を保護する。 By the way, the third intrinsic semiconductor layer on the light receiving surface side of the semiconductor substrate is formed before the patterning (first patterning) of the first conductive type semiconductor layer. Then, in the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light receiving surface side of the semiconductor substrate as well as the back surface side to protect the third intrinsic semiconductor layer from the etching solution.
　しかし、裏面側のパターン印刷レジストを印刷して焼成（乾燥）した後に、受光面側のパターン印刷レジストを印刷して焼成（乾燥）すると、裏面側のパターン印刷レジストの熱履歴が２回となり、裏面側のパターン印刷レジストが剥離し難くなってしまう。そのため、裏面側のパターン印刷レジストの剥離残りが発生してしまう。 However, when the pattern print resist on the back side is printed and fired (dried), and then the pattern print resist on the light receiving side is printed and fired (dried), the thermal history of the pattern print resist on the back side becomes twice. The pattern print resist on the back side is difficult to peel off. Therefore, the pattern print resist on the back side is left unpeeled.
　また、第１導電型半導体層のパターニング（１回目のパターニング）の前に、半導体基板の受光面側の第３真性半導体層を形成すると、その後の製造プロセスにおいて第３真性半導体層がダメージを受けてしまう。 Further, if the third intrinsic semiconductor layer on the light receiving surface side of the semiconductor substrate is formed before the patterning of the first conductive type semiconductor layer (first patterning), the third intrinsic semiconductor layer is damaged in the subsequent manufacturing process. It ends up.
　本発明は、パターン印刷レジストの剥離残りを低減し、製造プロセスにおける第３真性半導体層のダメージを低減する太陽電池の製造方法を提供することを目的とする。 An object of the present invention is to provide a method for manufacturing a solar cell, which reduces the peeling residue of a pattern printing resist and reduces the damage of the third intrinsic semiconductor layer in the manufacturing process.
　本発明に係る太陽電池の製造方法は、半導体基板と、前記半導体基板の一方主面側と反対側の他方主面側の一部である第１領域に順に積層された第１真性半導体層および第１導電型半導体層と、前記半導体基板の前記他方主面側の他の一部である第２領域に順に積層された第２真性半導体層および第２導電型半導体層と、前記半導体基板の前記一方主面側に積層された第３真性半導体層とを備えるバックコンタクト型の太陽電池の製造方法であって、前記半導体基板の前記他方主面側に、前記第１真性半導体層の材料膜および前記第１導電型半導体層の材料膜を形成する第１半導体層材料膜形成工程と、前記半導体基板の前記他方主面側の前記第１領域における前記第１導電型半導体層の材料膜の上にパターン印刷レジストを形成し、前記半導体基板の前記一方主面側にはパターン印刷レジストを形成しないレジスト形成工程と、前記パターン印刷レジストを用いて、前記半導体基板の前記他方主面側の前記第２領域における前記第１導電型半導体層の材料膜および前記第１真性半導体層の材料膜を除去することにより、前記半導体基板の前記他方主面側の前記第１領域にパターン化された前記第１真性半導体層および前記第１導電型半導体層を形成する第１半導体層形成工程と、前記パターン印刷レジストを除去するレジスト除去工程と、前記半導体基板の前記一方主面側に前記第３真性半導体層を形成する第３半導体層形成工程と、をこの順で含む。 The method for manufacturing a solar cell according to the present invention includes a semiconductor substrate, a first intrinsic semiconductor layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a first intrinsic semiconductor layer. The first conductive semiconductor layer, the second intrinsic semiconductor layer and the second conductive semiconductor layer sequentially laminated in the second region which is another part on the other main surface side of the semiconductor substrate, and the semiconductor substrate. A method for manufacturing a back-contact type solar cell including a third intrinsic semiconductor layer laminated on one main surface side, wherein a material film of the first intrinsic semiconductor layer is formed on the other main surface side of the semiconductor substrate. And the first semiconductor layer material film forming step of forming the material film of the first conductive semiconductor layer, and the material film of the first conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate. A resist forming step of forming a pattern printing resist on the semiconductor substrate and not forming a pattern printing resist on the one main surface side of the semiconductor substrate, and using the pattern printing resist to form the other main surface side of the semiconductor substrate. By removing the material film of the first conductive semiconductor layer and the material film of the first intrinsic semiconductor layer in the second region, the pattern is patterned in the first region on the other main surface side of the semiconductor substrate. A first semiconductor layer forming step for forming the first intrinsic semiconductor layer and the first conductive semiconductor layer, a resist removing step for removing the pattern printing resist, and the third intrinsic on the one main surface side of the semiconductor substrate. The third semiconductor layer forming step of forming the semiconductor layer and the process of forming the semiconductor layer are included in this order.
　本発明によれば、太陽電池の製造方法において、パターン印刷レジストの剥離残りを低減することができ、製造プロセスにおける第３真性半導体層のダメージを低減することができる。 According to the present invention, in the method for manufacturing a solar cell, it is possible to reduce the peeling residue of the pattern printing resist, and it is possible to reduce the damage to the third intrinsic semiconductor layer in the manufacturing process.
本実施形態に係る太陽電池を背面側からみた図である。It is the figure which looked at the solar cell which concerns on this embodiment from the back side. 図１の太陽電池におけるII－II線断面図である。FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. 本実施形態に係る太陽電池の製造方法における第１半導体層材料膜形成工程、仮半導体層形成工程およびリフトオフ層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer material film forming process, the temporary semiconductor layer forming process, and the lift-off layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法におけるレジスト形成工程を示す図である。It is a figure which shows the resist forming process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第１半導体層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法におけるレジスト除去工程を示す図である。It is a figure which shows the resist removal process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第２半導体層材料膜形成工程および第３半導体層形成工程を示す図である。It is a figure which shows the 2nd semiconductor layer material film formation process and 3rd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である。It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における光学調整層形成工程を示す図である。It is a figure which shows the optical adjustment layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における電極層形成工程を示す図である。It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における電極層形成工程を示す図である。It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 比較例の太陽電池の製造方法における第１半導体層材料膜形成工程、第３真性半導体層形成工程およびリフトオフ層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer material film formation process, the 3rd intrinsic semiconductor layer formation process, and the lift-off layer formation process in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法におけるレジスト形成工程を示す図である。It is a figure which shows the resist forming process in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法における第１半導体層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法におけるレジスト除去工程を示す図である。It is a figure which shows the resist removal process in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法における第２半導体層材料膜形成工程を示す図である。It is a figure which shows the process of forming the 2nd semiconductor layer material film in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法における第２半導体層形成工程を示す図である。It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法における光学調整層形成工程を示す図である。It is a figure which shows the optical adjustment layer forming process in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法における電極層形成工程を示す図である。It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell of the comparative example. 比較例の太陽電池の製造方法における電極層形成工程を示す図である。It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell of the comparative example.
　以下、添付の図面を参照して本発明の実施形態の一例について説明する。なお、各図面において同一または相当の部分に対しては同一の符号を附すこととする。また、便宜上、ハッチングや部材符号等を省略する場合もあるが、かかる場合、他の図面を参照するものとする。 Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. In addition, for convenience, hatching, member codes, and the like may be omitted, but in such cases, other drawings shall be referred to.
（太陽電池）
　図１は、本実施形態に係る太陽電池を背面側からみた図である。図１に示す太陽電池１は、裏面電極型（バックコンタクト型、裏面接合型ともいう。）の太陽電池である。太陽電池１は、２つの主面を備えるｎ型（第２導電型）半導体基板１１を備え、半導体基板１１の主面において第１領域７と第２領域８とを有する。 (Solar cell)
FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the rear side. The solar cell 1 shown in FIG. 1 is a back electrode type (also referred to as a back contact type or back surface bonding type) solar cell. The solar cell 1 includes an n-type (second conductive type) semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
　第１領域７は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部７ｆと、櫛歯の支持部に相当するバスバー部７ｂとを有する。バスバー部７ｂは、半導体基板１１の一方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部７ｆは、バスバー部７ｂから、第１方向（Ｘ方向）に交差する第２方向（Ｙ方向）に延在する。 The first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to the comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
　同様に、第２領域８は、いわゆる櫛型の形状であり、櫛歯に相当する複数のフィンガー部８ｆと、櫛歯の支持部に相当するバスバー部８ｂとを有する。バスバー部８ｂは、半導体基板１１の一方の辺部に対向する他方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部８ｆは、バスバー部８ｂから、第２方向（Ｙ方向）に延在する。 Similarly, the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
　フィンガー部７ｆとフィンガー部８ｆとは、第１方向（Ｘ方向）に交互に設けられている。なお、第１領域７および第２領域８は、ストライプ状に形成されてもよい。 The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction). The first region 7 and the second region 8 may be formed in a striped shape.
　図２は、図１の太陽電池におけるII－II線断面図である。図２に示すように、太陽電池１は、半導体基板１１の主面のうちの受光する側の一方の主面である受光面側に順に積層された真性半導体層（第３真性半導体層）１３および光学調整層１５を備える。また、太陽電池１は、半導体基板１１の主面のうちの受光面の反対側の他方の主面である裏面側の一部（主に、第１領域７）に順に積層された真性半導体層（第１真性半導体層）２３、ｐ型（第１導電型）半導体層２５および第１電極層２７を備える。また、太陽電池１は、半導体基板１１の裏面側の他の一部（主に、第２領域８）に順に積層された真性半導体層（第２真性半導体層）３３、ｎ型（第２導電型）半導体層３５および第２電極層３７を備える。 FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 2, the solar cell 1 is an intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 laminated in order on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. And an optical adjustment layer 15. Further, the solar cell 1 is an intrinsic semiconductor layer laminated in order on a part of the back surface side (mainly, the first region 7) which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. It includes a (first intrinsic semiconductor layer) 23, a p-type (first conductive type) semiconductor layer 25, and a first electrode layer 27. Further, the solar cell 1 has an intrinsic semiconductor layer (second intrinsic semiconductor layer) 33, n-type (second conductive) laminated in order on another part (mainly, the second region 8) on the back surface side of the semiconductor substrate 11. Type) A semiconductor layer 35 and a second electrode layer 37 are provided.
　半導体基板１１は、単結晶シリコンまたは多結晶シリコン等の結晶シリコン材料で形成される。半導体基板１１は、例えば結晶シリコン材料にｎ型ドーパントがドープされたｎ型の半導体基板である。ｎ型ドーパントとしては、例えばリン（Ｐ）が挙げられる。
　半導体基板１１は、受光面側からの入射光を吸収して光キャリア（電子および正孔）を生成する光電変換基板として機能する。 The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
　半導体基板１１の材料として結晶シリコンが用いられることにより、暗電流が比較的に小さく、入射光の強度が低い場合であっても比較的高出力（照度によらず安定した出力）が得られる。 By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.
　半導体基板１１は、裏面側に、テクスチャ構造と呼ばれるピラミッド型の微細な凹凸構造を有していてもよい。これにより、半導体基板１１に吸収されず通過してしまった光の回収効率が高まる。 The semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the recovery efficiency of light that has passed through without being absorbed by the semiconductor substrate 11 is increased.
　また、半導体基板１１は、受光面側に、テクスチャ構造と呼ばれるピラミッド型の微細な凹凸構造を有していてもよい。これにより、受光面において入射光の反射が低減し、半導体基板１１における光閉じ込め効果が向上する。 Further, the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect on the semiconductor substrate 11 is improved.
　真性半導体層１３は、半導体基板１１の受光面側に形成されている。真性半導体層２３は、半導体基板１１の裏面側の第１領域７に形成されている。真性半導体層３３は、半導体基板１１の裏面側の第２領域８に形成されている。真性半導体層１３，２３，３３は、例えば真性（ｉ型）アモルファスシリコンを主成分とする材料で形成される。
　真性半導体層１３，２３，３３は、いわゆるパッシベーション層として機能し、半導体基板１１で生成されたキャリアの再結合を抑制し、キャリアの回収効率を高める。 The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layers 13, 23, 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
The intrinsic semiconductor layers 13, 23, 33 function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the carrier recovery efficiency.
　光学調整層１５は、半導体基板１１の受光面側の真性半導体層１３上に形成されている。光学調整層１５は、入射光の反射を防止する反射防止層として機能するとともに、半導体基板１１の受光面側および真性半導体層１３を保護する保護層として機能する。光学調整層１５は、例えば酸化珪素（ＳｉＯ）、窒化珪素（ＳｉＮ）、または酸窒化珪素（ＳｉＯＮ）のようなそれらの複合物等の絶縁体材料で形成される。 The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light, and also functions as a protective layer for protecting the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
　ｐ型半導体層２５は、真性半導体層２３上に、すなわち半導体基板１１の裏面側の第１領域７に形成されている。ｐ型半導体層２５は、例えばアモルファスシリコン材料で形成される。ｐ型半導体層２５は、例えばアモルファスシリコン材料にｐ型ドーパントがドープされたｐ型の半導体層である。ｐ型ドーパントとしては、例えばホウ素（Ｂ）が挙げられる。 The p-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. The p-type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The p-type semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
　ｎ型半導体層３５は、真性半導体層３３上に、すなわち半導体基板１１の裏面側の第２領域８に形成されている。ｎ型半導体層３５は、例えばアモルファスシリコン材料で形成される。ｎ型半導体層３５は、例えばアモルファスシリコン材料にｎ型ドーパント（例えば、上述したリン（Ｐ））がドープされたｎ型半導体層である。 The n-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. The n-type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The n-type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
　第１電極層２７は、ｐ型半導体層２５上に形成されており、第２電極層３７は、ｎ型半導体層３５上に形成されている。第１電極層２７は、ｐ型半導体層２５上に順に積層された透明電極層２８と金属電極層２９とを有する。第２電極層３７は、ｎ型半導体層３５上に順に積層された透明電極層３８と金属電極層３９とを有する。
　透明電極層２８，３８は、透明な導電性材料で形成される。透明導電性材料としては、ＩＴＯ（Indium Tin Oxide：酸化インジウムおよび酸化スズの複合酸化物）等が挙げられる。金属電極層２９，３９は、銀等の金属粉末を含有する導電性ペースト材料で形成される。 The first electrode layer 27 is formed on the p-type semiconductor layer 25, and the second electrode layer 37 is formed on the n-type semiconductor layer 35. The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 that are sequentially laminated on the p-type semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 which are sequentially laminated on the n-type semiconductor layer 35.
The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide). The metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.
（比較例の太陽電池の製造方法）
　本願発明者らは、ｐ型半導体層のパターニング（１回目のパターニング）において、パターン印刷法によるパターン印刷レジストを用いることを考案している。これにより、スピンコート法によるフォトレジスト（フォトリソグラフィ法）を用いた場合と比較して、露光および現像の工程を削減することができ、太陽電池の製造プロセスの簡略化が可能となる。 (Manufacturing method of solar cell of comparative example)
The inventors of the present application have devised the use of a pattern printing resist by a pattern printing method in the patterning of the p-type semiconductor layer (first patterning). As a result, the number of exposure and development steps can be reduced as compared with the case of using the photoresist (photolithography method) by the spin coating method, and the manufacturing process of the solar cell can be simplified.
　なお、パターン印刷とは、フォトリソグラフィ法のように、一度、パターン化前のレジスト膜（非パターンレジスト膜）を形成した後に、露光・現像のような工程を経る印刷ではなく、スクリーン印刷若しくはグラビア印刷のようなプレス印刷、または、インクジェット印刷のような吐出印刷のような、レジスト付着面に対して、直接、パターン化したレジスト(印刷材料）を付着させる印刷法を意味する。また、パターン印刷レジストとは、パターン印刷に使用される印刷材料（レジスト材料）を意味する。 Note that pattern printing is not printing that goes through processes such as exposure and development after forming a resist film (non-patterned resist film) before patterning, as in the photolithography method, but screen printing or gravure. It means a printing method in which a patterned resist (printing material) is directly adhered to a resist adhering surface such as press printing such as printing or ejection printing such as inkjet printing. Further, the pattern printing resist means a printing material (resist material) used for pattern printing.
　更に、本願発明者らは、ｐ型半導体層のパターニングにおいて、パターン印刷レジストを除去する溶液として安価なアルカリ溶液を採用することを考案している。これにより、太陽電池の低コスト化が可能となる。 Furthermore, the inventors of the present application have devised to adopt an inexpensive alkaline solution as a solution for removing the pattern printing resist in the patterning of the p-type semiconductor layer. This makes it possible to reduce the cost of the solar cell.
　また、本願発明者らは、ｎ型半導体層のパターニング（２回目のパターニング）において、リフトオフ層（犠牲層）を用いたリフトオフ法を採用することを考案している。これにより、太陽電池の製造プロセスの簡略化が可能となる。 Further, the inventors of the present application have devised to adopt a lift-off method using a lift-off layer (sacrificial layer) in the patterning of the n-type semiconductor layer (second patterning). This makes it possible to simplify the manufacturing process of solar cells.
　更に、本願発明者らは、リフトオフ層を、以下に示すような酸性溶液に対する特性を有する下層と上層とを有する２層構造とすることを考案している。
下層のエッチング速度＞上層のエッチング速度
これによれば、エッチング速度が遅い上層により、ｐ型半導体層のパターニング（１回目のパターニング）後の基板洗浄工程において、リフトオフ層の剥離を抑制しつつ、エッチング速度が速い下層により、ｎ型半導体層のパターニング（２回目のパターニング）のリフトオフ工程において、リフトオフ性を高めることができる。 Furthermore, the inventors of the present application have devised a two-layer structure in which the lift-off layer has a lower layer and an upper layer having characteristics for an acidic solution as shown below.
Etching rate of lower layer> Etching rate of upper layer According to this, the upper layer, which has a slow etching rate, etches while suppressing the peeling of the lift-off layer in the substrate cleaning step after patterning the p-type semiconductor layer (first patterning). The high-speed lower layer makes it possible to improve the lift-off property in the lift-off step of patterning the n-type semiconductor layer (second patterning).
　また、本願発明者らは、透明電極層のパターニングにおいて、金属電極層をマスクとして用いることを考案している。これにより、フォトリソグラフィ法等によるレジストをマスクとして用いる必要がなく、太陽電池の製造プロセスの簡略化が可能となる。 Further, the inventors of the present application have devised the use of a metal electrode layer as a mask in the patterning of the transparent electrode layer. As a result, it is not necessary to use a resist obtained by a photolithography method or the like as a mask, and the solar cell manufacturing process can be simplified.
　以下に、図４Ａ～図４Ｉを参照して、本願発明者らの考案に基づく比較例の太陽電池１Ｘの製造方法、およびその課題について説明する。図４Ａは、比較例の太陽電池の製造方法における第１半導体層材料膜形成工程、第３半導体層形成工程およびリフトオフ層形成工程を示す図であり、図４Ｂは、比較例の太陽電池の製造方法におけるレジスト形成工程を示す図である。また、図４Ｃは、比較例の太陽電池の製造方法における第１半導体層形成工程を示す図であり、図４Ｄは、比較例の太陽電池の製造方法におけるレジスト除去工程を示す図である。また、図４Ｅは、比較例の太陽電池の製造方法における第２半導体層材料膜形成工程を示す図であり、図４Ｆは、比較例の太陽電池の製造方法における第２半導体層形成工程を示す図である。また、図４Ｇは、比較例の太陽電池の製造方法における光学調整層形成工程を示す図であり、図４Ｈおよび図４Ｉは、比較例の太陽電池の製造方法における電極層形成工程を示す図である。 Hereinafter, a method for manufacturing the solar cell 1X of the comparative example based on the invention of the inventors of the present application and its problems will be described with reference to FIGS. 4A to 4I. FIG. 4A is a diagram showing a first semiconductor layer material film forming step, a third semiconductor layer forming step, and a lift-off layer forming step in the method for manufacturing a solar cell of Comparative Example, and FIG. 4B is a diagram showing manufacturing of a solar cell of Comparative Example. It is a figure which shows the resist forming process in the method. Further, FIG. 4C is a diagram showing a first semiconductor layer forming step in the solar cell manufacturing method of the comparative example, and FIG. 4D is a diagram showing a resist removing step in the solar cell manufacturing method of the comparative example. Further, FIG. 4E is a diagram showing a second semiconductor layer material film forming step in the solar cell manufacturing method of the comparative example, and FIG. 4F shows a second semiconductor layer forming step in the solar cell manufacturing method of the comparative example. It is a figure. Further, FIG. 4G is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method of the comparative example, and FIGS. 4H and 4I are diagrams showing an electrode layer forming step in the solar cell manufacturing method of the comparative example. is there.
　まず、図４Ａに示すように、例えばＣＶＤ法（化学気相堆積法）を用いて、受光面側および／または裏面側に凹凸構造（テクスチャ構造）を有する半導体基板１１Ｘの裏面側の全面に、真性半導体層材料膜２３ＺＸおよびｐ型半導体層材料膜２５ＺＸを順に積層（製膜）する（第１半導体層材料膜形成工程）。 First, as shown in FIG. 4A, for example, by using a CVD method (chemical vapor deposition method), the entire surface of the back surface side of the semiconductor substrate 11X having a concavo-convex structure (texture structure) on the light receiving surface side and / or the back surface side is applied. The intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX are laminated (film-formed) in this order (first semiconductor layer material film forming step).
　また、例えばＣＶＤ法を用いて、半導体基板１１Ｘの受光面側の全面に、真性半導体層（第３真性半導体層）１３Ｘを積層（製膜）する（第３半導体層形成工程）。なお、真性半導体層材料膜２３ＺＸおよびｐ型半導体層材料膜２５ＺＸと、真性半導体層１３Ｘとの製膜の順序は限定されない。 Further, for example, using the CVD method, the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X is laminated (film-formed) on the entire surface of the semiconductor substrate 11X on the light receiving surface side (third semiconductor layer forming step). The order of film formation of the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer 13X is not limited.
　次に、例えばＣＶＤ法を用いて、半導体基板１１Ｘの裏面側の全面に、具体的にはｐ型半導体層材料膜２５ＺＸ上の全面に、リフトオフ層（犠牲層）４１Ｘを積層（製膜）する（リフトオフ層形成工程）。
　リフトオフ層４１Ｘは、酸化珪素（ＳｉＯ）、窒化珪素（ＳｉＮ）、または酸窒化珪素（ＳｉＯＮ）のようなそれらの複合物等の材料で形成される。リフトオフ層４１Ｘの膜厚は、例えば１ｎｍ以上１μｍ以下であると好ましい。 Next, for example, using a CVD method, a lift-off layer (sacrificial layer) 41X is laminated (film-formed) on the entire surface of the semiconductor substrate 11X on the back surface side, specifically, on the entire surface of the p-type semiconductor layer material film 25ZX. (Lift-off layer forming process).
The lift-off layer 41X is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON). The film thickness of the lift-off layer 41X is preferably, for example, 1 nm or more and 1 μm or less.
　リフトオフ層４１Ｘは、半導体基板１１Ｘ側から下層と上層とを有する２層構造であってもよい。下層および上層は、以下に示すような酸性溶液に対する特性を有する。
下層のエッチング速度＞上層のエッチング速度
例えば、リフトオフ層４１Ｘが酸化珪素を主成分とする膜である場合、その主成分をＳｉＯｘと表したときのｘの値は、以下の関係式を満たす。
下層のｘ＞上層のｘ The lift-off layer 41X may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11X side. The lower and upper layers have properties for acidic solutions as shown below.
Etching rate of lower layer> Etching rate of upper layer For example, when the lift-off layer 41X is a film containing silicon oxide as a main component, the value of x when the main component is expressed as SiOx satisfies the following relational expression.
Lower layer x> Upper layer x
　次に、図４Ｂ～図４Ｄに示すように、パターン印刷レジスト９０Ｘを用いて、半導体基板１１Ｘの裏面側において、第２領域８におけるリフトオフ層４１Ｘ、ｐ型半導体層材料膜２５ＺＸおよび真性半導体層材料膜２３ＺＸを除去することにより、第１領域７に、パターン化された真性半導体層（第１真性半導体層）２３Ｘ、ｐ型半導体層２５Ｘおよびリフトオフ層４１Ｘを形成する。 Next, as shown in FIGS. 4B to 4D, the lift-off layer 41X, the p-type semiconductor layer material film 25ZX, and the intrinsic semiconductor layer material in the second region 8 on the back surface side of the semiconductor substrate 11X using the pattern printing resist 90X. By removing the film 23ZX, a patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23X, a p-type semiconductor layer 25X, and a lift-off layer 41X are formed in the first region 7.
　具体的には、図４Ｂに示すように、半導体基板１１Ｘの裏面側において、第１領域７におけるｐ型半導体層材料膜２５ＺＸおよびリフトオフ層４１Ｘ上に、パターン印刷法を用いてパターン印刷レジスト９０Ｘを形成する（レジスト形成工程）。また、半導体基板１１Ｘの受光面側の全面に、パターン印刷法を用いてパターン印刷レジスト９０Ｘを形成する（レジスト形成工程）。パターン印刷レジストの膜厚は、例えば１μｍ以上５０μｍ以下である。パターン印刷法を用いたパターン印刷レジストによれば、従来のスピンコート法を用いたフォトレジスト（フォトリソグラフィ法）におけるレジストの露光および現像が不要となる（製造プロセスの簡略化）。このとき、第１の課題および第２の課題が生じる（詳細は後述する）。 Specifically, as shown in FIG. 4B, on the back surface side of the semiconductor substrate 11X, a pattern printing resist 90X is applied on the p-type semiconductor layer material film 25ZX and the lift-off layer 41X in the first region 7 by using a pattern printing method. Form (resist forming step). Further, a pattern printing resist 90X is formed on the entire surface of the semiconductor substrate 11X on the light receiving surface side by using a pattern printing method (resist forming step). The film thickness of the pattern print resist is, for example, 1 μm or more and 50 μm or less. According to the pattern printing resist using the pattern printing method, the exposure and development of the resist in the photoresist (photolithography method) using the conventional spin coating method become unnecessary (simplification of the manufacturing process). At this time, a first problem and a second problem occur (details will be described later).
　その後、図４Ｃに示すように、パターン印刷レジスト９０Ｘをマスクとして、半導体基板１１Ｘの裏面側において、第２領域８におけるリフトオフ層４１Ｘをエッチングすることにより、第１領域７に、パターン化されたリフトオフ層４１Ｘを形成する。リフトオフ層４１Ｘに対するエッチング溶液としては、例えばフッ酸等の酸性溶液が用いられる。
　その後、パターン印刷レジスト９０Ｘをマスクとして、半導体基板１１Ｘの裏面側において、第２領域８におけるｐ型半導体層材料膜２５ＺＸおよび真性半導体層材料膜２３ＺＸをエッチングすることにより、第１領域７に、パターン化された真性半導体層２３Ｘおよびｐ型半導体層２５Ｘを形成する（第１半導体層形成工程）。ｐ型半導体層材料膜２５ＺＸおよび真性半導体層材料膜２３ＺＸに対するエッチング溶液としては、例えばオゾンをフッ酸に溶解させた混合液等の酸性溶液が用いられる。 Then, as shown in FIG. 4C, the lift-off layer 41X in the second region 8 is etched on the back surface side of the semiconductor substrate 11X using the pattern printing resist 90X as a mask, whereby the lift-off patterned in the first region 7 is performed. Layer 41X is formed. As the etching solution for the lift-off layer 41X, for example, an acidic solution such as hydrofluoric acid is used.
Then, using the pattern printing resist 90X as a mask, the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX in the second region 8 are etched on the back surface side of the semiconductor substrate 11X to form a pattern in the first region 7. The formed intrinsic semiconductor layer 23X and the p-type semiconductor layer 25X are formed (first semiconductor layer forming step). As the etching solution for the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX, for example, an acidic solution such as a mixed solution in which ozone is dissolved in hydrofluoric acid is used.
　その後、図４Ｄに示すように、裏面側および受光面側のパターン印刷レジスト９０Ｘを除去する（レジスト除去工程）。パターン印刷レジスト９０Ｘに対するエッチング溶液としては、ＫＯＨ等の安価なアルカリ溶液が用いられる（低コスト化）。このとき、第２の課題が生じる（詳細は後述する）。 After that, as shown in FIG. 4D, the pattern printing resist 90X on the back surface side and the light receiving surface side is removed (resist removing step). As the etching solution for the pattern printing resist 90X, an inexpensive alkaline solution such as KOH is used (cost reduction). At this time, a second problem arises (details will be described later).
　次に、半導体基板１１Ｘの両面側をクリーニングする（第１洗浄工程）。第１洗浄工程では、例えばオゾン処理を行った後、フッ酸処理が行われる。フッ酸処理とは、フッ酸のみならず、フッ酸に他の種類の酸（第１洗浄工程では、例えば塩酸）を含めた混合物での処理も含むものとする。このとき、リフトオフ層４１Ｘにおけるエッチング速度が遅い上層により、リフトオフ層４１Ｘの剥離を抑制することができる。このとき、第２の課題が生じる（詳細は後述する）。 Next, clean both sides of the semiconductor substrate 11X (first cleaning step). In the first cleaning step, for example, ozone treatment is followed by hydrofluoric acid treatment. The hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid containing another kind of acid (for example, hydrochloric acid in the first washing step). At this time, peeling of the lift-off layer 41X can be suppressed by the upper layer having a slow etching rate in the lift-off layer 41X. At this time, a second problem arises (details will be described later).
　次に、図４Ｅに示すように、例えばＣＶＤ法を用いて、半導体基板１１Ｘの裏面側の全面に、具体的には第１領域７におけるリフトオフ層４１Ｘ上および第２領域８に、真性半導体層材料膜３３ＺＸおよびｎ型半導体層材料膜３５ＺＸを順に積層（製膜）する（第２半導体層材料膜形成工程）。 Next, as shown in FIG. 4E, for example, by using the CVD method, the intrinsic semiconductor layer is formed on the entire surface of the back surface side of the semiconductor substrate 11X, specifically on the lift-off layer 41X in the first region 7 and on the second region 8. The material film 33ZX and the n-type semiconductor layer material film 35ZX are laminated (film-formed) in order (second semiconductor layer material film forming step).
　次に、図４Ｆに示すように、リフトオフ層（犠牲層）を用いたリフトオフ法を利用して、半導体基板１１Ｘの裏面側において、第１領域７における真性半導体層材料膜３３ＺＸおよびｎ型半導体層材料膜３５ＺＸを除去することにより、第２領域８に、パターン化された真性半導体層（第２真性半導体層）３３Ｘおよびｎ型半導体層３５Ｘを形成する（第２半導体層形成工程）。 Next, as shown in FIG. 4F, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer in the first region 7 on the back surface side of the semiconductor substrate 11X by using the lift-off method using the lift-off layer (sacrificial layer). By removing the material film 35ZX, a patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33X and an n-type semiconductor layer 35X are formed in the second region 8 (second semiconductor layer forming step).
　具体的には、リフトオフ層４１Ｘを除去することにより、リフトオフ層４１Ｘ上の真性半導体層材料膜３３ＺＸおよびｎ型半導体層材料膜３５ＺＸを除去し、第２領域８に真性半導体層３３Ｘおよびｎ型半導体層３５Ｘを形成する。リフトオフ層４１Ｘの除去溶液としては、例えばフッ酸等の酸性溶液が用いられる。このとき、リフトオフ層４１Ｘにおけるエッチング速度が速い下層により、リフトオフ性を高めることができる。 Specifically, by removing the lift-off layer 41X, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX on the lift-off layer 41X are removed, and the intrinsic semiconductor layer 33X and the n-type semiconductor are removed in the second region 8. Layer 35X is formed. As the removal solution for the lift-off layer 41X, for example, an acidic solution such as hydrofluoric acid is used. At this time, the lift-off property can be improved by the lower layer having a high etching rate in the lift-off layer 41X.
　次に、図４Ｇに示すように、半導体基板１１Ｘの受光面側の全面に、光学調整層１５Ｘを形成する（光学調整層形成工程）。 Next, as shown in FIG. 4G, the optical adjustment layer 15X is formed on the entire surface of the semiconductor substrate 11X on the light receiving surface side (optical adjustment layer forming step).
　次に、図４Ｈおよび図４Ｉに示すように、半導体基板１１Ｘの裏面側に、第１電極層２７Ｘおよび第２電極層３７Ｘを形成する（電極層形成工程）。
　具体的には、例えばスパッタリング法等のＰＶＤ法（物理気相成長法）を用いて、半導体基板１１Ｘの裏面側において、第１導電型半導体層２５Ｘおよび第２導電型半導体層３５Ｘの上にこれらに跨って透明電極層材料膜２８ＺＸを積層（製膜）する（透明電極層材料膜形成工程）。 Next, as shown in FIGS. 4H and 4I, the first electrode layer 27X and the second electrode layer 37X are formed on the back surface side of the semiconductor substrate 11X (electrode layer forming step).
Specifically, for example, by using a PVD method (physical vapor deposition method) such as a sputtering method, these are placed on the first conductive semiconductor layer 25X and the second conductive semiconductor layer 35X on the back surface side of the semiconductor substrate 11X. The transparent electrode layer material film 28ZX is laminated (film-formed) across the (transparent electrode layer material film forming step).
　その後、例えばパターン印刷法または塗布法を用いて、透明電極層材料膜２８ＺＸを介して第１導電型半導体層２５Ｘ上に金属電極層２９Ｘを形成し、透明電極層材料膜２８ＺＸを介して第２導電型半導体層３５Ｘ上に金属電極層３９Ｘを形成する（金属電極層形成工程）。 Then, for example, using a pattern printing method or a coating method, a metal electrode layer 29X is formed on the first conductive semiconductor layer 25X via the transparent electrode layer material film 28ZX, and a second metal electrode layer 29X is formed via the transparent electrode layer material film 28ZX. A metal electrode layer 39X is formed on the conductive semiconductor layer 35X (metal electrode layer forming step).
　その後、金属電極層２９Ｘおよび金属電極層３９Ｘをマスクとして用いて、透明電極層材料膜２８ＺＸをパターニングすることにより、互いに分離された第１透明電極層２８Ｘおよび第２透明電極層３８Ｘを形成する（透明電極層形成工程）。透明電極層材料膜２８ＺＸに対するエッチング溶液としては、例えば塩酸または塩化第二鉄水溶液が用いられる。 Then, by using the metal electrode layer 29X and the metal electrode layer 39X as masks and patterning the transparent electrode layer material film 28ZX, the first transparent electrode layer 28X and the second transparent electrode layer 38X separated from each other are formed ( Transparent electrode layer forming step). As the etching solution for the transparent electrode layer material film 28ZX, for example, hydrochloric acid or an aqueous ferric chloride solution is used.
　ここで、従来の太陽電池の製造方法では、透明電極層材料膜の形成後であって金属電極層の形成前に、透明電極層の形成（パターニング）を行う。
　透明電極層の形成（パターニング）では、例えばフォトリソグラフィ法を用いて透明電極層材料膜をパターニングすることにより、互いに分離された第１透明電極層および第２透明電極層を形成する。フォトリソグラフィ法では、
・透明電極層材料膜の上にレジストを塗布し、
・レジストを感光させることにより、レジストに開口を形成し、
・レジストをマスクとして開口において露出した透明電極層材料膜をエッチングすることにより、互いに分離された第１透明電極層および第２透明電極層を形成し、
・レジストを除去する。 Here, in the conventional method for manufacturing a solar cell, the transparent electrode layer is formed (patterned) after the formation of the transparent electrode layer material film and before the formation of the metal electrode layer.
In the formation (patterning) of the transparent electrode layer, for example, the transparent electrode layer material film is patterned by using a photolithography method to form a first transparent electrode layer and a second transparent electrode layer separated from each other. In photolithography,
・ Apply resist on the transparent electrode layer material film and
・ By exposing the resist to light, an opening is formed in the resist.
-By etching the transparent electrode layer material film exposed at the opening using a resist as a mask, a first transparent electrode layer and a second transparent electrode layer separated from each other are formed.
-Remove the resist.
　これに対し、比較例の太陽電池の製造方法によれば、透明電極層材料膜の形成後に、金属電極層の形成および透明電極層の形成（パターニング）をこの順で含み、透明電極層の形成（パターニング）では、第１金属電極層２９Ｘおよび第２金属電極層３９Ｘをマスクとして用いて、透明電極層材料膜２８ＺＸをパターニングすることにより、互いに分離された第１透明電極層２８Ｘおよび第２透明電極層３８Ｘを形成する。これにより、比較例の太陽電池の製造方法によれば、従来のように、マスクを用いたフォトリソグラフィ法等を用いる必要がなく、透明電極層の形成の簡略化および短縮化が可能である。 On the other hand, according to the method for manufacturing a solar cell of the comparative example, after the formation of the transparent electrode layer material film, the formation of the metal electrode layer and the formation (patterning) of the transparent electrode layer are included in this order, and the transparent electrode layer is formed. In (patterning), the first transparent electrode layer 28X and the second transparent electrode layer 28X and the second transparent electrode layer separated from each other by patterning the transparent electrode layer material film 28ZX using the first metal electrode layer 29X and the second metal electrode layer 39X as masks. The electrode layer 38X is formed. As a result, according to the solar cell manufacturing method of the comparative example, it is not necessary to use a photolithography method or the like using a mask as in the conventional case, and the formation of the transparent electrode layer can be simplified and shortened.
　以上の工程により、比較例の裏面電極型の太陽電池１Ｘが完成する。 Through the above steps, the back electrode type solar cell 1X of the comparative example is completed.
　ここで、比較例の太陽電池の製造方法では、第１半導体層形成工程（１回目のパターニング）の前に、受光面側の真性半導体層（第３真性半導体層）１３Ｘを製膜する。そして、第１半導体層形成工程（１回目のパターニング）では、裏面側と同様に、受光面側にもパターン印刷レジストを形成し、エッチング溶液から真性半導体層１３Ｘを保護しつつ、真性半導体層１３Ｘを残していた。 Here, in the solar cell manufacturing method of the comparative example, the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X on the light receiving surface side is formed before the first semiconductor layer forming step (first patterning). Then, in the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light receiving surface side as well as the back surface side to protect the intrinsic semiconductor layer 13X from the etching solution and to protect the intrinsic semiconductor layer 13X. Was left.
（第１の課題）
　しかし、裏面側のパターン印刷レジストを印刷して焼成（乾燥）した後に、受光面側のパターン印刷レジストを印刷して焼成（乾燥）すると、裏面側のパターン印刷レジストの熱履歴が２回となり、裏面側のパターン印刷レジストが剥離し難くなってしまう。そのため、裏面側のパターン印刷レジストの剥離残りが発生してしまう。 (First issue)
However, when the pattern print resist on the back side is printed and fired (dried), and then the pattern print resist on the light receiving side is printed and fired (dried), the thermal history of the pattern print resist on the back side becomes twice. The pattern print resist on the back side is difficult to peel off. Therefore, the pattern print resist on the back side is left unpeeled.
（第２の課題）
　また、第１半導体層形成工程（１回目パターニング）の前に、受光面側の真性半導体層１３Ｘを形成すると、その後の製造プロセスにおいて真性半導体層１３Ｘがダメージを受けてしまう。
　例えば、パターン印刷レジストとの接触により、レジスト剥離溶液（アルカリ溶液）との接触により、洗浄溶液（フッ酸）との接触により、受光面側の真性半導体層１３Ｘがダメージを受けてしまう。 (Second issue)
Further, if the intrinsic semiconductor layer 13X on the light receiving surface side is formed before the first semiconductor layer forming step (first patterning), the intrinsic semiconductor layer 13X will be damaged in the subsequent manufacturing process.
For example, the intrinsic semiconductor layer 13X on the light receiving surface side is damaged by the contact with the pattern printing resist, the contact with the resist stripping solution (alkali solution), and the contact with the cleaning solution (hydrofluoric acid).
　第１の課題および第２の課題に関し、本願発明者らは、第１半導体層形成工程（１回目のパターニング）に対するレジスト形成工程において受光面側にパターン印刷レジストを形成せず、第１半導体層形成工程（１回目のパターニング）においてこの段階で形成された受光面側の仮の真性半導体層を剥離する。そして、第２半導体層材料膜形成工程において、受光面側の真性半導体層を製膜し直すことを考案する。 Regarding the first problem and the second problem, the inventors of the present application did not form a pattern printing resist on the light receiving surface side in the resist forming step for the first semiconductor layer forming step (first patterning), and the first semiconductor layer. In the forming step (first patterning), the temporary intrinsic semiconductor layer on the light receiving surface side formed at this stage is peeled off. Then, in the second semiconductor layer material film forming step, it is devised to re-form the intrinsic semiconductor layer on the light receiving surface side.
（本実施形態の太陽電池の製造方法）
　以下、図３Ａ～図３Ｉを参照して、図１および図２に示す本実施形態の太陽電池１の製造方法について説明する。図３Ａは、本実施形態に係る太陽電池の製造方法における第１半導体層材料膜形成工程、仮半導体層形成工程およびリフトオフ層形成工程を示す図であり、図３Ｂは、本実施形態に係る太陽電池の製造方法におけるレジスト形成工程を示す図である。また、図３Ｃは、本実施形態に係る太陽電池の製造方法における第１半導体層形成工程を示す図であり、図３Ｄは、本実施形態に係る太陽電池の製造方法におけるレジスト除去工程を示す図である。また、図３Ｅは、本実施形態に係る太陽電池の製造方法における第２半導体層材料膜形成工程および第３半導体層形成工程を示す図であり、図３Ｆは、本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である。また、図３Ｇは、本実施形態に係る太陽電池の製造方法における光学調整層形成工程を示す図であり、図３Ｈおよび図３Ｉは、本実施形態に係る太陽電池の製造方法における電極層形成工程を示す図である。 (Manufacturing method of solar cell of this embodiment)
Hereinafter, the method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3I. FIG. 3A is a diagram showing a first semiconductor layer material film forming step, a temporary semiconductor layer forming step, and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 3B is a diagram showing a solar cell according to the present embodiment. It is a figure which shows the resist forming process in the manufacturing method of a battery. Further, FIG. 3C is a diagram showing a first semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 3D is a diagram showing a resist removing step in the solar cell manufacturing method according to the present embodiment. Is. Further, FIG. 3E is a diagram showing a second semiconductor layer material film forming step and a third semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 3F is a diagram showing the solar cell according to the present embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method. Further, FIG. 3G is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method according to the present embodiment, and FIGS. 3H and 3I are electrodes layer forming steps in the solar cell manufacturing method according to the present embodiment. It is a figure which shows.
　まず、図３Ａに示すように、例えばＣＶＤ法を用いて、受光面側および／または裏面側に凹凸構造（テクスチャ構造）を有する半導体基板１１の裏面側の全面に、真性半導体層材料膜２３Ｚおよびｐ型半導体層材料膜２５Ｚを順に積層（製膜）する（第１半導体層材料膜形成工程）。 First, as shown in FIG. 3A, for example, by using the CVD method, the intrinsic semiconductor layer material film 23Z and / or the intrinsic semiconductor layer material film 23Z and the entire surface of the back surface side of the semiconductor substrate 11 having the uneven structure (texture structure) on the light receiving surface side and / or the back surface side The p-type semiconductor layer material film 25Z is laminated (film-formed) in order (first semiconductor layer material film forming step).
　また、例えばＣＶＤ法を用いて、半導体基板１１の受光面側の全面に、仮の半導体層１３Ｚを積層（製膜）してもよい（仮半導体層形成工程）。仮の半導体層１３Ｚは、例えば真性半導体層である。仮の半導体層１３Ｚを形成すると、後述するレジスト形成工程時などにおいて、半導体基板１１の受光面側に意図せず汚染源（有機物質等）が付着してしまうことを防ぐことができる。なお、受光面側の仮の半導体層１３Ｚは形成されなくてもよい。なお、真性半導体層材料膜２３Ｚおよびｐ型半導体層材料膜２５Ｚと、仮の半導体層１３Ｚとの製膜の順序は限定されない。 Further, for example, a temporary semiconductor layer 13Z may be laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by using a CVD method (temporary semiconductor layer forming step). The temporary semiconductor layer 13Z is, for example, an intrinsic semiconductor layer. By forming the temporary semiconductor layer 13Z, it is possible to prevent an contamination source (organic substance or the like) from unintentionally adhering to the light receiving surface side of the semiconductor substrate 11 during a resist forming step described later. The temporary semiconductor layer 13Z on the light receiving surface side does not have to be formed. The order of film formation of the intrinsic semiconductor layer material film 23Z and the p-type semiconductor layer material film 25Z and the temporary semiconductor layer 13Z is not limited.
　次に、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、具体的にはｐ型半導体層材料膜２５Ｚ上の全面に、リフトオフ層（犠牲層）４１を積層（製膜）する（リフトオフ層形成工程）。
　リフトオフ層４１は、酸化珪素（ＳｉＯ）、窒化珪素（ＳｉＮ）、または酸窒化珪素（ＳｉＯＮ）のようなそれらの複合物等の材料で形成される。リフトオフ層４１の膜厚は、例えば１ｎｍ以上１μｍ以下であると好ましい。 Next, for example, using a CVD method, a lift-off layer (sacrificial layer) 41 is laminated (film-formed) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the p-type semiconductor layer material film 25Z. (Lift-off layer forming process).
The lift-off layer 41 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON). The film thickness of the lift-off layer 41 is preferably, for example, 1 nm or more and 1 μm or less.
　リフトオフ層４１は、半導体基板１１側から下層と上層とを有する２層構造であってもよい。下層および上層は、以下に示すような酸性溶液に対する特性を有する。
下層のエッチング速度＞上層のエッチング速度
例えば、リフトオフ層４１が酸化珪素を主成分とする膜である場合、その主成分をＳｉＯｘと表したときのｘの値は、以下の関係式を満たす。
下層のｘ＞上層のｘ The lift-off layer 41 may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11 side. The lower and upper layers have properties for acidic solutions as shown below.
Etching rate of lower layer> Etching rate of upper layer For example, when the lift-off layer 41 is a film containing silicon oxide as a main component, the value of x when the main component is expressed as SiOx satisfies the following relational expression.
Lower layer x> Upper layer x
　次に、図３Ｂ～図３Ｄに示すように、パターン印刷レジスト９０を用いて、半導体基板１１の裏面側において、第２領域８におけるリフトオフ層４１、ｐ型半導体層材料膜２５Ｚおよび真性半導体層材料膜２３Ｚを除去することにより、第１領域７に、パターン化された真性半導体層（第１真性半導体層）２３、ｐ型半導体層２５およびリフトオフ層４１を形成する。 Next, as shown in FIGS. 3B to 3D, the lift-off layer 41, the p-type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material in the second region 8 are used on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90. By removing the film 23Z, a patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23, a p-type semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7.
　具体的には、図３Ｂに示すように、半導体基板１１の裏面側において、第１領域７におけるｐ型半導体層材料膜２５Ｚおよびリフトオフ層４１上に、パターン印刷法を用いてパターン印刷レジスト９０を形成する（レジスト形成工程）。パターン印刷レジスト９０の膜厚は、例えば１μｍ以上５０μｍ以下である。パターン印刷法を用いたパターン印刷レジストによれば、従来のスピンコート法を用いたフォトレジスト（フォトリソグラフィ法）におけるレジストの露光および現像が不要となる（製造プロセスの簡略化）。 Specifically, as shown in FIG. 3B, on the back surface side of the semiconductor substrate 11, the pattern printing resist 90 is applied on the p-type semiconductor layer material film 25Z and the lift-off layer 41 in the first region 7 by using a pattern printing method. Form (resist forming step). The film thickness of the pattern print resist 90 is, for example, 1 μm or more and 50 μm or less. According to the pattern printing resist using the pattern printing method, exposure and development of the resist in the photoresist (photolithography method) using the conventional spin coating method become unnecessary (simplification of the manufacturing process).
　一方、半導体基板１１の受光面側には、パターン印刷レジストを形成しない（レジスト形成工程）。これにより、裏面側のパターン印刷レジスト９０を印刷して焼成（乾燥）した後に、受光面側のパターン印刷レジストを印刷して焼成（乾燥）する必要がなく、裏面側のパターン印刷レジスト９０の熱履歴は１回となる。これにより、裏面側のパターン印刷レジスト９０の熱履歴を低減でき、後述するレジスト除去工程において、裏面側のパターン印刷レジスト９０の剥離し難さが低減され、裏面側のパターン印刷レジスト９０の剥離残りが低減される（第１の課題解決）。
　また、受光面側にパターン印刷レジストを形成せず、後述するように受光面側の真性半導体層１３は形成されていないので、パターン印刷レジストとの接触による受光面側の真性半導体層１３のダメージが無い（第２の課題解決）。 On the other hand, the pattern printed resist is not formed on the light receiving surface side of the semiconductor substrate 11 (resist forming step). As a result, it is not necessary to print and bake (dry) the pattern print resist 90 on the back side, and then print and bake (dry) the pattern print resist on the light receiving side, and the heat of the pattern print resist 90 on the back side does not need to be printed. The history is once. As a result, the thermal history of the pattern print resist 90 on the back side can be reduced, the difficulty of peeling the pattern print resist 90 on the back side is reduced in the resist removing step described later, and the peeling residue of the pattern print resist 90 on the back side is reduced. Is reduced (first problem solution).
Further, since the pattern print resist is not formed on the light receiving surface side and the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described later, the intrinsic semiconductor layer 13 on the light receiving surface side is damaged by the contact with the pattern printing resist. There is no (solving the second problem).
　その後、図３Ｃに示すように、パターン印刷レジスト９０をマスクとして、半導体基板１１の裏面側において、第２領域８におけるリフトオフ層４１をエッチングすることにより、第１領域７に、パターン化されたリフトオフ層４１を形成する。リフトオフ層４１に対するエッチング溶液としては、例えばフッ酸等の酸性溶液が用いられる。
　その後、パターン印刷レジスト９０をマスクとして、半導体基板１１の裏面側において、第２領域８におけるｐ型半導体層材料膜２５Ｚおよび真性半導体層材料膜２３Ｚをエッチングすることにより、第１領域７に、パターン化された真性半導体層（第１真性半導体層）２３、ｐ型半導体層２５を形成する（第１半導体層形成工程）。ｐ型半導体層材料膜２５Ｚおよび真性半導体層材料膜２３Ｚに対するエッチング溶液としては、例えばオゾンをフッ酸に溶解させた混合液等の酸性溶液が用いられる。
　このとき、半導体基板１１の受光面側にパターン印刷レジストが形成されていないので、半導体基板１１の受光面側に形成された仮の半導体層１３Ｚが除去される。 Then, as shown in FIG. 3C, the lift-off layer 41 in the second region 8 is etched on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90 as a mask, so that the lift-off layer patterned in the first region 7 is patterned. The layer 41 is formed. As the etching solution for the lift-off layer 41, for example, an acidic solution such as hydrofluoric acid is used.
Then, using the pattern printing resist 90 as a mask, the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z in the second region 8 are etched on the back surface side of the semiconductor substrate 11 to form a pattern in the first region 7. The formed intrinsic semiconductor layer (first intrinsic semiconductor layer) 23 and the p-type semiconductor layer 25 are formed (first semiconductor layer forming step). As the etching solution for the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z, for example, an acidic solution such as a mixed solution in which ozone is dissolved in hydrofluoric acid is used.
At this time, since the pattern printed resist is not formed on the light receiving surface side of the semiconductor substrate 11, the temporary semiconductor layer 13Z formed on the light receiving surface side of the semiconductor substrate 11 is removed.
　その後、図３Ｄに示すように、パターン印刷レジスト９０を除去する（レジスト除去工程）。パターン印刷レジスト９０に対するエッチング溶液としては、ＫＯＨ等の安価なアルカリ溶液が用いられる（低コスト化）。
　このとき、後述するように受光面側の真性半導体層１３は形成されていないので、レジスト剥離溶液（アルカリ溶液）との接触による受光面側の真性半導体層１３のダメージが無い（第２の課題解決）。 Then, as shown in FIG. 3D, the pattern printing resist 90 is removed (resist removing step). As the etching solution for the pattern printing resist 90, an inexpensive alkaline solution such as KOH is used (cost reduction).
At this time, since the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described later, there is no damage to the intrinsic semiconductor layer 13 on the light receiving surface side due to contact with the resist stripping solution (alkali solution) (second problem). Solution).
　次に、半導体基板１１の両面側をクリーニングする（第１洗浄工程）。第１洗浄工程では、例えばオゾン処理を行った後、フッ酸処理が行われる。フッ酸処理とは、フッ酸のみならず、フッ酸に他の種類の酸（第１洗浄工程では、例えば塩酸）を含めた混合物での処理も含むものとする。このとき、リフトオフ層４１におけるエッチング速度が遅い上層により、リフトオフ層４１の剥離を抑制することができる。
　また、このとき、後述するように受光面側の真性半導体層１３は形成されていないので、洗浄溶液（フッ酸）との接触による受光面側の真性半導体層１３のダメージがない（第２の課題解決）。 Next, both sides of the semiconductor substrate 11 are cleaned (first cleaning step). In the first cleaning step, for example, ozone treatment is followed by hydrofluoric acid treatment. The hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid containing another kind of acid (for example, hydrochloric acid in the first washing step). At this time, peeling of the lift-off layer 41 can be suppressed by the upper layer having a slow etching rate in the lift-off layer 41.
Further, at this time, since the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described later, there is no damage to the intrinsic semiconductor layer 13 on the light receiving surface side due to contact with the cleaning solution (hydrofluoric acid) (second). Problem solving).
　次に、図３Ｅに示すように、例えばＣＶＤ法を用いて、半導体基板１１の受光面側の全面に、真性半導体層（第３真性半導体層）１３を積層（製膜）する（第３半導体層形成工程）。 Next, as shown in FIG. 3E, the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side, for example, by using the CVD method (third semiconductor). Layer formation step).
　また、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、具体的には第１領域７におけるリフトオフ層４１上および第２領域８に、真性半導体層材料膜３３Ｚおよびｎ型半導体層材料膜３５Ｚを順に積層（製膜）する（第２半導体層材料膜形成工程）。 Further, for example, by using a CVD method, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer are placed on the entire surface of the back surface side of the semiconductor substrate 11, specifically on the lift-off layer 41 and the second region 8 in the first region 7. The material films 35Z are laminated (film-formed) in order (second semiconductor layer material film forming step).
　次に、図３Ｆに示すように、リフトオフ層（犠牲層）を用いたリフトオフ法を利用して、半導体基板１１の裏面側において、第１領域７における真性半導体層材料膜３３Ｚおよびｎ型半導体層材料膜３５Ｚを除去することにより、第２領域８に、パターン化された真性半導体層（第２真性半導体層）３３およびｎ型半導体層３５を形成する（第２半導体層形成工程）。 Next, as shown in FIG. 3F, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer in the first region 7 on the back surface side of the semiconductor substrate 11 by using the lift-off method using the lift-off layer (sacrificial layer). By removing the material film 35Z, a patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33 and an n-type semiconductor layer 35 are formed in the second region 8 (second semiconductor layer forming step).
　具体的には、リフトオフ層４１を除去することにより、リフトオフ層４１上の真性半導体層材料膜３３Ｚおよびｎ型半導体層材料膜３５Ｚを除去し、第２領域８に真性半導体層３３およびｎ型半導体層３５を形成する。リフトオフ層４１の除去溶液としては、例えばフッ酸等の酸性溶液が用いられる。このとき、リフトオフ層４１におけるエッチング速度が速い下層により、リフトオフ性を高めることができる。 Specifically, by removing the lift-off layer 41, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z on the lift-off layer 41 are removed, and the intrinsic semiconductor layer 33 and the n-type semiconductor are removed in the second region 8. The layer 35 is formed. As the removal solution for the lift-off layer 41, for example, an acidic solution such as hydrofluoric acid is used. At this time, the lift-off property can be improved by the lower layer having a high etching rate in the lift-off layer 41.
　次に、図３Ｇに示すように、半導体基板１１の受光面側の全面に、光学調整層１５を形成する（光学調整層形成工程）。 Next, as shown in FIG. 3G, the optical adjustment layer 15 is formed on the entire surface of the semiconductor substrate 11 on the light receiving surface side (optical adjustment layer forming step).
　次に、図３Ｈおよび図３Ｉに示すように、半導体基板１１の裏面側に、第１電極層２７および第２電極層３７を形成する（電極層形成工程）。
　具体的には、例えばスパッタリング法等のＰＶＤ法を用いて、半導体基板１１の裏面側において、第１導電型半導体層２５および第２導電型半導体層３５の上にこれらに跨って透明電極層材料膜２８Ｚを積層（製膜）する（透明電極層材料膜形成工程）。 Next, as shown in FIGS. 3H and 3I, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, using a PVD method such as a sputtering method, a transparent electrode layer material straddles the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 on the back surface side of the semiconductor substrate 11. The film 28Z is laminated (film-formed) (transparent electrode layer material film forming step).
　その後、例えばパターン印刷法または塗布法を用いて、透明電極層材料膜２８Ｚを介して第１導電型半導体層２５上に金属電極層２９を形成し、透明電極層材料膜２８Ｚを介して第２導電型半導体層３５上に金属電極層３９を形成する（金属電極層形成工程）。 Then, for example, using a pattern printing method or a coating method, a metal electrode layer 29 is formed on the first conductive semiconductor layer 25 via the transparent electrode layer material film 28Z, and a second metal electrode layer 29 is formed via the transparent electrode layer material film 28Z. A metal electrode layer 39 is formed on the conductive semiconductor layer 35 (metal electrode layer forming step).
　その後、金属電極層２９および金属電極層３９をマスクとして用いて、透明電極層材料膜２８Ｚをパターニングすることにより、互いに分離された第１透明電極層２８および第２透明電極層３８を形成する（透明電極層形成工程）。透明電極層材料膜２８Ｚに対するエッチング溶液としては、例えば塩酸または塩化第二鉄水溶液が用いられる。これにより、上述したように、従来のようにマスクを用いたフォトリソグラフィ法等を用いる必要がなく、透明電極層の形成の簡略化および短縮化が可能である。 Then, by using the metal electrode layer 29 and the metal electrode layer 39 as masks and patterning the transparent electrode layer material film 28Z, the first transparent electrode layer 28 and the second transparent electrode layer 38 separated from each other are formed (. Transparent electrode layer forming step). As the etching solution for the transparent electrode layer material film 28Z, for example, hydrochloric acid or an aqueous ferric chloride solution is used. As a result, as described above, it is not necessary to use a photolithography method or the like using a mask as in the conventional case, and the formation of the transparent electrode layer can be simplified and shortened.
　以上の工程により、図１および図２に示す本実施形態の裏面電極型の太陽電池１が得られる。 Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.
　以上説明したように、本実施形態の太陽電池の製造方法によれば、第１半導体層形成工程（１回目のパターニング）において、受光面側にパターン印刷レジストを形成しないので、裏面側のパターン印刷レジスト９０を印刷して焼成（乾燥）した後に、受光面側のパターン印刷レジストを印刷して焼成（乾燥）する必要がなく、裏面側のパターン印刷レジスト９０の熱履歴は１回となる。これにより、裏面側のパターン印刷レジスト９０の熱履歴を低減でき、裏面側のパターン印刷レジスト９０の剥離し難さが低減される。そのため、裏面側のパターン印刷レジスト９０の剥離残りが低減される。なお、受光面側のパターン印刷レジストの剥離残りは無い。 As described above, according to the method for manufacturing a solar cell of the present embodiment, in the first semiconductor layer forming step (first patterning), the pattern printing resist is not formed on the light receiving surface side, so that the pattern printing on the back surface side is performed. After printing and firing (drying) the resist 90, it is not necessary to print and fire (dry) the pattern printing resist on the light receiving surface side, and the thermal history of the pattern printing resist 90 on the back surface side is one. As a result, the thermal history of the pattern printing resist 90 on the back surface side can be reduced, and the difficulty of peeling off the pattern printing resist 90 on the back surface side is reduced. Therefore, the peeling residue of the pattern print resist 90 on the back surface side is reduced. There is no peeling residue of the pattern print resist on the light receiving surface side.
　また、本実施形態の太陽電池の製造方法によれば、第１半導体層形成工程（１回目のパターニング）において受光面側にパターン印刷レジストを形成しないので、第１半導体層形成工程（１回目のパターニング）の前に形成された受光面側の仮の半導体層１３Ｚは除去される。そして、第２半導体層形成工程（２回目のパターニング）において、受光面側の真性半導体層（第３真性半導体層）１３を製膜し直す。これにより、製造プロセスにおいて受光面側の真性半導体層１３がダメージを受けることを抑制することができる。具体的には、パターン印刷レジストとの接触が無く、レジスト剥離溶液（アルカリ溶液）との接触が無く、洗浄溶液（フッ酸）との接触が無いので、受光面側の真性半導体層１３がダメージを受けることが抑制される。その結果、太陽電池の性能が向上する。 Further, according to the method for manufacturing a solar cell of the present embodiment, since the pattern printing resist is not formed on the light receiving surface side in the first semiconductor layer forming step (first patterning), the first semiconductor layer forming step (first patterning) is performed. The temporary semiconductor layer 13Z on the light receiving surface side formed before the patterning) is removed. Then, in the second semiconductor layer forming step (second patterning), the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 on the light receiving surface side is re-formed. As a result, it is possible to prevent the intrinsic semiconductor layer 13 on the light receiving surface side from being damaged in the manufacturing process. Specifically, since there is no contact with the pattern printing resist, no contact with the resist stripping solution (alkali solution), and no contact with the cleaning solution (hydrofluoric acid), the intrinsic semiconductor layer 13 on the light receiving surface side is damaged. Is suppressed. As a result, the performance of the solar cell is improved.
　以上、本発明の実施形態について説明したが、本発明は上述した実施形態に限定されることなく、種々の変更および変形が可能である。例えば、上述した実施形態では、第１導電型半導体層２５をｐ型半導体層、第２導電型半導体層３５をｎ型半導体層としたが、第１導電型半導体層２５をｎ型半導体層、第２導電型半導体層３５をｐ型半導体層に置き換えてもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, the first conductive semiconductor layer 25 is a p-type semiconductor layer and the second conductive semiconductor layer 35 is an n-type semiconductor layer, but the first conductive semiconductor layer 25 is an n-type semiconductor layer. The second conductive type semiconductor layer 35 may be replaced with a p-type semiconductor layer.
　また、上述した実施形態では、図２に示すようにヘテロ接合型の太陽電池１の製造方法を例示したが、本発明の特徴は、ヘテロ接合型の太陽電池に限らず、ホモ接合型の太陽電池等の種々の太陽電池の製造方法に適用可能である。 Further, in the above-described embodiment, the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.
　また、上述した実施形態では、半導体基板１１としてｎ型半導体基板を例示したが、半導体基板１１は、結晶シリコン材料にｐ型ドーパント（例えば、上述したホウ素（Ｂ））がドープされたｐ型半導体基板であってもよい。 Further, in the above-described embodiment, the n-type semiconductor substrate is exemplified as the semiconductor substrate 11, but the semiconductor substrate 11 is a p-type semiconductor in which a p-type dopant (for example, the above-mentioned boron (B)) is doped in a crystalline silicon material. It may be a substrate.
　また、上述した実施形態では、結晶シリコン基板を有する太陽電池を例示したが、これに限定されない。例えば、太陽電池は、ガリウムヒ素（ＧａＡｓ）基板を有していてもよい。 Further, in the above-described embodiment, a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this. For example, a solar cell may have a gallium arsenide (GaAs) substrate.
　１，１Ｘ　太陽電池
　７　第１領域
　７ｂ，８ｂ　バスバー部
　７ｆ，８ｆ　フィンガー部
　８　第２領域
　１１，１１Ｘ　半導体基板
　１３，１３Ｘ　真性半導体層（第３真性半導体層）
　１３Ｚ　仮の半導体層
　１５，１５Ｘ　光学調整層
　２３，２３Ｘ　真性半導体層（第１真性半導体層）
　２３Ｚ，２３ＺＸ　真性半導体層材料膜（第１真性半導体層材料膜）
　２５，２５Ｘ　ｐ型半導体層（第１導電型半導体層）
　２５Ｚ，２５ＺＸ　ｐ型半導体層材料膜（第１導電型半導体層材料膜）
　２７，２７Ｘ　第１電極層
　２８，２８Ｘ　第１透明電極層
　２９，２９Ｘ　第１金属電極層
　３３，３３Ｘ　真性半導体層（第２真性半導体層）
　３３Ｚ，３３ＺＸ　真性半導体層材料膜（第２真性半導体層材料膜）
　３５，３５Ｘ　第２導電型半導体層
　３５Ｚ，３５ＺＸ　第２導電型半導体層材料膜
　３７，３７Ｘ　第２電極層
　３８，３８Ｘ　第２透明電極層
　３９，３９Ｘ　第２金属電極層
　４１，４１Ｘ　リフトオフ層
　９０，９０Ｘ　パターン印刷レジスト 1,1X Solar cell 7 1st region 7b, 8b Bus bar 7f, 8f Finger part 8 2nd region 11, 11X Semiconductor substrate 13,13X Intrinsic semiconductor layer (3rd intrinsic semiconductor layer)
13Z Temporary semiconductor layer 15,15X Optical adjustment layer 23,23X Intrinsic semiconductor layer (first intrinsic semiconductor layer)
23Z, 23ZX Intrinsic semiconductor layer material film (first intrinsic semiconductor layer material film)
25,25Xp-type semiconductor layer (first conductive type semiconductor layer)
25Z, 25ZX p-type semiconductor layer material film (first conductive type semiconductor layer material film)
27,27X 1st electrode layer 28,28X 1st transparent electrode layer 29,29X 1st metal electrode layer 33,33X Intrinsic semiconductor layer (2nd intrinsic semiconductor layer)
33Z, 33ZX Intrinsic semiconductor layer material film (second intrinsic semiconductor layer material film)
35, 35X Second Conductive Semiconductor Layer 35Z, 35ZX Second Conductive Semiconductor Layer Material Film 37, 37X Second Electrode Layer 38, 38X Second Transparent Electrode Layer 39, 39X Second Metal Electrode Layer 41, 41X Lift Off Layer 90, 90X pattern printing resist

Claims (5)

  1. 　半導体基板と、前記半導体基板の一方主面側と反対側の他方主面側の一部である第１領域に順に積層された第１真性半導体層および第１導電型半導体層と、前記半導体基板の前記他方主面側の他の一部である第２領域に順に積層された第２真性半導体層および第２導電型半導体層と、前記半導体基板の前記一方主面側に積層された第３真性半導体層とを備えるバックコンタクト型の太陽電池の製造方法であって、
    　前記半導体基板の前記他方主面側に、前記第１真性半導体層の材料膜および前記第１導電型半導体層の材料膜を形成する第１半導体層材料膜形成工程と、
    　前記半導体基板の前記他方主面側の前記第１領域における前記第１導電型半導体層の材料膜の上にパターン印刷レジストを形成し、前記半導体基板の前記一方主面側にはパターン印刷レジストを形成しないレジスト形成工程と、
    　前記パターン印刷レジストを用いて、前記半導体基板の前記他方主面側の前記第２領域における前記第１導電型半導体層の材料膜および前記第１真性半導体層の材料膜を除去することにより、前記半導体基板の前記他方主面側の前記第１領域にパターン化された前記第１真性半導体層および前記第１導電型半導体層を形成する第１半導体層形成工程と、
    　前記パターン印刷レジストを除去するレジスト除去工程と、
    　前記半導体基板の前記一方主面側に前記第３真性半導体層を形成する第３半導体層形成工程と、
    をこの順で含む、太陽電池の製造方法。     A semiconductor substrate, a first intrinsic semiconductor layer and a first conductive semiconductor layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the semiconductor substrate. The second intrinsic semiconductor layer and the second conductive semiconductor layer, which are sequentially laminated in the second region which is the other part on the other main surface side of the above, and the third laminated on the one main surface side of the semiconductor substrate. A method for manufacturing a back-contact type solar cell including an intrinsic semiconductor layer.
    A first semiconductor layer material film forming step of forming a material film of the first intrinsic semiconductor layer and a material film of the first conductive type semiconductor layer on the other main surface side of the semiconductor substrate.
    A pattern printing resist is formed on the material film of the first conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate, and a pattern printing resist is formed on the one main surface side of the semiconductor substrate. Resist forming process that does not form and
    The pattern printing resist is used to remove the material film of the first conductive semiconductor layer and the material film of the first intrinsic semiconductor layer in the second region on the other main surface side of the semiconductor substrate. A first semiconductor layer forming step of forming the first intrinsic semiconductor layer and the first conductive semiconductor layer patterned in the first region on the other main surface side of the semiconductor substrate.
    A resist removing step for removing the pattern printing resist and
    A third semiconductor layer forming step of forming the third intrinsic semiconductor layer on the one main surface side of the semiconductor substrate, and a third semiconductor layer forming step.
    A method of manufacturing a solar cell, which includes the above in this order.
  2. 　前記レジスト形成工程の前に、前記半導体基板の前記一方主面側に仮の半導体層を形成する仮半導体層形成工程を更に含み、
    　前記仮の半導体層は、前記第１半導体層形成工程において除去される、
    請求項１に記載の太陽電池の製造方法。     Prior to the resist forming step, a temporary semiconductor layer forming step of forming a temporary semiconductor layer on the one main surface side of the semiconductor substrate is further included.
    The temporary semiconductor layer is removed in the first semiconductor layer forming step.
    The method for manufacturing a solar cell according to claim 1.
  3. 　前記レジスト除去工程では、アルカリ溶液を用いて前記パターン印刷レジストを剥離する、請求項１または２に記載の太陽電池の製造方法。 The method for manufacturing a solar cell according to claim 1 or 2, wherein in the resist removing step, the pattern printing resist is peeled off using an alkaline solution.
  4. 　前記第１半導体層材料膜形成工程の後に、リフトオフ層形成工程を更に含み、
    　前記レジスト除去工程の後に、第２半導体層材料膜形成工程と第２半導体層形成工程とを更に含み、
    　前記リフトオフ層形成工程では、前記第１導電型半導体層の材料膜の上にリフトオフ層を形成し、
    　前記レジスト形成工程では、前記半導体基板の前記他方主面側の前記第１領域における前記リフトオフ層の上に前記パターン印刷レジストを形成し、
    　前記第１半導体層形成工程では、前記パターン印刷レジストを用いて、前記半導体基板の前記他方主面側の前記第２領域における前記リフトオフ層、前記第１導電型半導体層の材料膜および前記第１真性半導体層の材料膜を除去することにより、前記半導体基板の前記他方主面側の前記第１領域にパターン化された前記第１真性半導体層、前記第１導電型半導体層および前記リフトオフ層を形成し、
    　前記第２半導体層材料膜形成工程では、前記半導体基板の前記他方主面側の前記第１領域における前記リフトオフ層の上、および前記半導体基板の前記他方主面側の前記第２領域に、前記第２真性半導体層の材料膜および前記第２導電型半導体層の材料膜を形成し、
    　前記第２半導体層形成工程では、前記リフトオフ層を除去することにより、前記半導体基板の前記他方主面側の前記第１領域における前記第２真性半導体層の材料膜および前記第２導電型半導体層の材料膜を除去し、前記半導体基板の前記他方主面側の前記第２領域の上にパターン化された前記第２真性半導体層および前記第２導電型半導体層を形成する、
    請求項１～３のいずれか１項に記載の太陽電池の製造方法。     After the first semiconductor layer material film forming step, a lift-off layer forming step is further included.
    After the resist removing step, a second semiconductor layer material film forming step and a second semiconductor layer forming step are further included.
    In the lift-off layer forming step, a lift-off layer is formed on the material film of the first conductive semiconductor layer.
    In the resist forming step, the pattern printing resist is formed on the lift-off layer in the first region on the other main surface side of the semiconductor substrate.
    In the first semiconductor layer forming step, using the pattern printing resist, the lift-off layer in the second region on the other main surface side of the semiconductor substrate, the material film of the first conductive semiconductor layer, and the first first. By removing the material film of the intrinsic semiconductor layer, the first intrinsic semiconductor layer, the first conductive semiconductor layer, and the lift-off layer patterned in the first region on the other main surface side of the semiconductor substrate are formed. Form and
    In the second semiconductor layer material film forming step, the above-mentioned lift-off layer in the first region on the other main surface side of the semiconductor substrate and the second region on the other main surface side of the semiconductor substrate. The material film of the second intrinsic semiconductor layer and the material film of the second conductive semiconductor layer are formed.
    In the second semiconductor layer forming step, the material film of the second intrinsic semiconductor layer and the second conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate are removed by removing the lift-off layer. The material film is removed to form the second intrinsic semiconductor layer and the second conductive semiconductor layer patterned on the second region on the other main surface side of the semiconductor substrate.
    The method for manufacturing a solar cell according to any one of claims 1 to 3.
  5. 　前記第３半導体層形成工程および前記第２半導体層形成工程の後に、前記第１導電型半導体層に対応する第１透明電極層および第１金属電極層と、前記第２導電型半導体層に対応する第２透明電極層および第２金属電極層とを形成する電極層形成工程を更に含み、
    　前記電極層形成工程は、
    　前記第１導電型半導体層および前記第２導電型半導体層の上にこれらに跨って透明電極層の材料膜を形成する透明電極層材料膜形成工程と、
    　前記透明電極層の材料膜を介して前記第１導電型半導体層の上に前記第１金属電極層を形成し、前記透明電極層の材料膜を介して前記第２導電型半導体層の上に前記第２金属電極層を形成する金属電極層形成工程と、
    　前記第１金属電極層および前記第２金属電極層をマスクとして用いて、前記透明電極層の材料膜をパターニングすることにより、互いに分離された前記第１透明電極層および前記第２透明電極層を形成する透明電極層形成工程と、
    をこの順で含む、
    請求項４に記載の太陽電池の製造方法。     After the third semiconductor layer forming step and the second semiconductor layer forming step, the first transparent electrode layer and the first metal electrode layer corresponding to the first conductive type semiconductor layer and the second conductive type semiconductor layer are supported. Further includes an electrode layer forming step of forming the second transparent electrode layer and the second metal electrode layer.
    The electrode layer forming step is
    A transparent electrode layer material film forming step of forming a material film of a transparent electrode layer straddling the first conductive type semiconductor layer and the second conductive type semiconductor layer.
    The first metal electrode layer is formed on the first conductive semiconductor layer via the material film of the transparent electrode layer, and is placed on the second conductive semiconductor layer via the material film of the transparent electrode layer. The metal electrode layer forming step of forming the second metal electrode layer and
    By using the first metal electrode layer and the second metal electrode layer as masks and patterning the material film of the transparent electrode layer, the first transparent electrode layer and the second transparent electrode layer separated from each other can be obtained. The process of forming the transparent electrode layer to be formed and
    In this order,
    The method for manufacturing a solar cell according to claim 4.
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