WO2021114385A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021114385A1
WO2021114385A1 PCT/CN2019/127547 CN2019127547W WO2021114385A1 WO 2021114385 A1 WO2021114385 A1 WO 2021114385A1 CN 2019127547 W CN2019127547 W CN 2019127547W WO 2021114385 A1 WO2021114385 A1 WO 2021114385A1
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Prior art keywords
gate
base substrate
substrate
array
array substrate
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PCT/CN2019/127547
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English (en)
French (fr)
Inventor
胡小波
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Tcl华星光电技术有限公司
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Priority to US16/627,812 priority Critical patent/US20210375951A1/en
Publication of WO2021114385A1 publication Critical patent/WO2021114385A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display panel.
  • a liquid crystal display panel generally includes a CF substrate 12 and a TFT substrate 11 arranged oppositely, without a border.
  • the display product design needs to face the TFT substrate 11 side outwards in order to perform the bonding of the printed circuit board.
  • the metal layer (such as the gate) in the TFT substrate 11 is not blocked by the light-blocking layer, and the ambient light entering the TFT substrate 11 (the direction indicated by the arrow in Figure 1 is the direction in which the light enters) has a higher reflectivity on the metal surface. Great, affect the visual effect.
  • the embodiment of the present application provides an array substrate to solve the technical problem that the ambient light entering the array substrate has a large reflectivity on the metal surface and affects the visual effect.
  • an embodiment of the present application provides an array substrate, which includes a base substrate and an array layer disposed on the base substrate;
  • the array layer includes a gate disposed above the base substrate, and the gate includes a first side surface disposed close to the base substrate and a second side surface disposed opposite to the first side surface , The roughness of the first side surface is greater than the roughness of the second side surface.
  • a plurality of grooves are provided on the first side surface of the gate.
  • a plurality of protrusions are provided on the side of the base substrate close to the gate, and the orthographic projection of the gate on the base substrate covers the protrusions on the liner. Orthographic projection on the bottom substrate.
  • the protrusions are located in the grooves and correspond to the grooves one-to-one.
  • the shape of the protrusion is the same as the shape of the groove, and the size of the protrusion is the same as the size of the groove.
  • the protrusion and the base substrate are integrally formed.
  • a buffer layer is further provided between the base substrate and the gate, and the bump is located on a side of the buffer layer close to the gate, and the bump is connected to the gate.
  • the buffer layer is integrally formed.
  • the overall longitudinal section of the first side surface of the gate is wavy.
  • the present invention also provides a method for manufacturing an array substrate, including the following steps:
  • step S20 includes:
  • a gate is formed above the first part of the base substrate, the gate includes a first side surface disposed close to the base substrate and a second side surface disposed opposite to the first side surface, forming The roughness of the first side surface is greater than the roughness of the second side surface.
  • the preparation method of the array substrate further includes:
  • the gate is formed on a first part of the base substrate, and the gate is located on a side of the first part with protrusions.
  • the preparation method of the array substrate further includes:
  • the gate is formed on the surface of the second part of the buffer layer.
  • the present invention also provides a display panel, which includes a color filter substrate and an array substrate.
  • the color filter substrate is arranged opposite to the array substrate, and a liquid crystal is arranged between the color filter substrate and the array substrate.
  • Layer; the array substrate includes a base substrate and an array layer disposed on the base substrate;
  • the array layer includes a gate disposed above the base substrate, and the gate includes a first side surface disposed close to the base substrate and a second side surface disposed opposite to the first side surface , The roughness of the first side surface is greater than the roughness of the second side surface.
  • a plurality of grooves are provided on the first side surface of the gate.
  • a plurality of protrusions are provided on the side of the base substrate close to the gate, and the orthographic projection of the gate on the base substrate covers the protrusions on the liner. Orthographic projection on the bottom substrate.
  • the protrusions are located in the grooves and correspond to the grooves one-to-one.
  • the shape of the protrusion is the same as the shape of the groove, and the size of the protrusion is the same as the size of the groove.
  • the protrusion and the base substrate are integrally formed.
  • a buffer layer is further provided between the base substrate and the gate, and the bump is located on a side of the buffer layer close to the gate, and the bump is connected to the gate.
  • the buffer layer is integrally formed.
  • the overall longitudinal section of the first side surface of the gate is wavy.
  • the first side surface of the gate is formed with grooves matching the protrusions, thereby increasing the first side of the gate.
  • the roughness of one side surface can increase the diffuse reflection when natural light is irradiated on the first side surface, reduce the specular reflection of the first side surface, thereby reducing the reflectivity of light on the first side surface, and prevent the ambient light entering the array substrate from being
  • the high reflectivity of the first side surface of the grid causes the visual effect to be adversely affected.
  • FIG. 1 is a schematic diagram of the structure of a liquid crystal display panel in the background of the present invention
  • FIG. 2 is a schematic diagram of the structure of an array substrate in an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the structure of an array substrate in another embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of step S20 in an embodiment of the present invention.
  • 5 to 10 are schematic diagrams of the preparation process of the array substrate in an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of the structure of a display panel in an embodiment of the present invention.
  • Array substrate 21. Base substrate; 211, first part; 22, buffer layer; 221, second part; 23, gate; 231, first side; 232, second side; 24, gate insulating layer 25. Active layer; 26. Source and drain metal layer; 27. Passivation layer; 28. Pixel electrode; 291. Groove; 292. Protrusion; 30. Color film substrate; 40. Liquid crystal layer; 50. Photoresist Layer; 60, conductive metal layer.
  • the present application provides an array substrate, a preparation method thereof, and a display panel.
  • the present application addresses the technical problem that in the existing display panel, the metal layer (such as the gate) in the array substrate is not blocked by the light blocking layer, and the ambient light entering the array substrate has a large reflectivity on the metal surface, which affects the visual effect.
  • the present invention can solve the above-mentioned problems.
  • the array substrate 20 includes a base substrate 21 and an array layer disposed on the base substrate 21.
  • the array layer includes a gate 23 arranged above the base substrate 21, a gate insulating layer 24 covering the gate 23, and an active layer arranged on the gate insulating layer 24 25 and the source/drain metal layer 26 electrically connected to the active layer 25, the passivation layer 27 covering the active layer 25 and the source/drain metal layer 26, and pixels disposed on the passivation layer 27 An electrode 28.
  • the pixel electrode 28 is electrically connected to the source/drain metal layer 26 through a lap hole.
  • the preparation material of the gate 23 includes, but is not limited to, one or more of copper, molybdenum, aluminum, silver, and titanium.
  • the gate 23 includes a first side surface 231 disposed close to the base substrate 21 and a second side surface 232 disposed opposite to the first side surface 231.
  • the roughness of the first side surface 231 is greater than that of the first side surface 231.
  • the roughness of the second side surface 232 is described.
  • the gate 23 is made of metal. It is known to those skilled in the art that by processing the first side surface 231 of the gate 23 in the array substrate 20, the roughness of the first side surface 231 can be increased. Increase the diffuse reflection when natural light is irradiated on the first side surface 231, reduce the specular reflection of the first side surface 231, thereby reducing the reflectivity of the light on the first side surface 231, and prevent the ambient light entering the array substrate 20 from being on the grid 23 The high reflectivity of the first side surface 231 causes the visual effect to be adversely affected.
  • a plurality of grooves 291 are provided on the first side surface 231 of the gate 23.
  • a plurality of grooves 291 are provided on the first side surface 231 of the gate 23 so that the first side surface 231 has an uneven structure, thereby increasing the roughness of the first side surface 231.
  • the grooves 291 may be arranged in an orderly manner (such as an array distribution), or may be arranged in a disorderly manner (such as a scattered distribution).
  • a plurality of protrusions 292 are provided on the side of the base substrate 21 close to the gate 23, and the orthographic projection of the gate 23 on the base substrate 21 covers the protrusions 292.
  • the base substrate 21 is a transparent substrate, and the base substrate 21 may be a plastic transparent substrate or a glass transparent substrate; the light passes through the area on the base substrate 21 corresponding to the gate 23 At this time, the protrusion 292 can deflect the light emitted from the protrusion 292 at a large angle, thereby reducing the light incident on the base substrate 21, and preventing the ambient light entering the array substrate 20 from being on the first side surface 231 of the gate 23. Reflection occurs and affects the visual effect.
  • protrusions 292 are located in the grooves 291 and correspond to the grooves 291 one-to-one.
  • the shape of the protrusion 292 is the same as the shape of the groove 291, and the size of the protrusion 292 is the same as the size of the groove 291.
  • Utilizing the protrusions 292 and the grooves 291 can reduce the reflectance of light on the first side surface 231 of the gate 23, and at the same time, by the cooperation of the protrusions 292 and the grooves 291, it is possible to prevent the protrusions 292 from increasing the overall thickness of the array layer.
  • the adhesion of the gate 23 on the base substrate 21 can be improved.
  • the protrusion 292 and the base substrate 21 are integrally formed.
  • the base substrate 21 includes a first portion 211 corresponding to the gate 23, the gate 23 is disposed on the first portion 211 of the base substrate 21, and the protrusion 292 Extend into the groove 291.
  • protrusions 292 may be provided only on the first portion 211, and no protrusions 292 are provided on the rest of the base substrate 21 to prevent adverse effects on the functions of other film layers.
  • a buffer layer 22 is further provided between the base substrate 21 and the gate 23, and the protrusion 292 is located on the buffer layer 22 close to the gate. On one side of 23, the protrusion 292 and the buffer layer 22 are integrally formed.
  • the preparation material of the buffer layer 22 includes but is not limited to one or more of silicon nitride, silicon oxide, silicon oxynitride, and polyimide, so as to prevent the metal in the gate 23 from facing the substrate.
  • the substrate 21 spreads.
  • the buffer layer 22 includes a second portion 221 corresponding to the gate 23, the gate 23 is disposed on the second portion 221 of the buffer layer 22, and the protrusion 292 Extend into the groove 291.
  • protrusions 292 may be provided only on the second portion 221, and no protrusions 292 are provided on the rest of the buffer layer 22 to prevent adverse effects on the functions of other film layers.
  • the overall longitudinal section of the first side surface of the gate is wavy.
  • the shape of the longitudinal section of the first side surface of the gate may be a continuous wave shape or a discontinuous wave shape.
  • the present invention also provides a method for manufacturing the array substrate 20, which includes the following steps:
  • the step S20 includes:
  • a gate 23 is formed above the first portion 211 of the base substrate 21, and the gate 23 includes a first side surface 231 disposed close to the base substrate 21 and a first side surface 231 disposed opposite to the first side surface 231.
  • the roughness of the first side surface 231 formed by the second side surface 232 is greater than the roughness of the second side surface 232.
  • step S20 further includes:
  • the preparation method of the array substrate 20 further includes:
  • the gate 23 is formed on the first part 211 of the base substrate 21, and the gate 23 is located on the side of the first part 211 with the protrusion 292.
  • the gate 23 is formed on the first portion 211, due to the existence of the protrusion 292, a groove 291 matching the protrusion 292 is formed on the first side surface 231 of the gate 23, so that the The first side surface 231 has an uneven structure, so that the roughness of the first side surface 231 is greater than the roughness of the second side surface 232, and the reflectance of light on the first side surface 231 is reduced.
  • the patterning process on the first part 211 of the base substrate 21 may use processes such as plasma treatment, laser laser, chemical liquid etching, or sandblasting etching.
  • the preparation method of the array substrate 20 further includes:
  • the gate 23 is formed on the surface of the second portion 221 of the buffer layer 22.
  • FIG. 5 to FIG. 10 are schematic diagrams of the preparation process of the array substrate 20 in an embodiment of the present invention.
  • a base substrate 21 is provided, and a photoresist layer 50 is formed on the base substrate 21 using a photoresist material.
  • the photoresist layer 50 is processed to remove the area on the photoresist layer 50 corresponding to the first part 211, and the surface of the first part 211 is patterned to form a A protrusion 292.
  • the photoresist layer 50 on the base substrate 21 is removed, and a metal material is used to form a conductive metal layer 60 covering the entire surface on the base substrate 21.
  • a metal material is used to form a conductive metal layer 60 covering the entire surface on the base substrate 21.
  • a groove 291 matching the protrusion 292 is simultaneously formed on the bottom surface of the conductive metal layer 60 in an area corresponding to the first portion 211.
  • the conductive metal layer 60 is patterned to form the gate 23 on the first portion 211.
  • a gate insulating layer 24 covering the gate 23 is formed on the base substrate 21, and an active layer 25 is formed on the gate insulating layer 24.
  • a layer covering the active layer 25 and the source-drain metal layer 26 is formed.
  • the passivation layer 27 is formed on the passivation layer 27 to pass through the passivation layer 27 and extend to the surface of the source and drain metal layer 26 to form a lap hole, and a filling lap is formed on the passivation layer 27
  • the pixel electrode 28 is electrically connected to the source and drain metal layer 26 through a hole.
  • the preparation process of the array substrate 20 is the same as the preparation process when the bumps 292 are formed on the base substrate 21 Similar, the only difference is: the base substrate 21 is not provided with bumps 292, a buffer layer 22 is formed on the base substrate 21, and bumps 292 are formed on the surface of the second portion 221 of the buffer layer 22 After that, the gate 23 is formed on the buffer layer 22.
  • the present invention also provides a display panel.
  • the display panel includes a color filter substrate 30 and the array substrate 20 described in any of the above embodiments. It is arranged opposite to the array substrate 20, and a liquid crystal layer 40 is arranged between the color filter substrate 30 and the array substrate 20.
  • the beneficial effect of the present invention is: by processing the surface of the base substrate 21 or the buffer layer 22, a plurality of protrusions 292 are formed on the base substrate 21 or the buffer layer 22, so that the first side surface of the gate 23 231 forms a groove 291 matching the protrusion 292, thereby increasing the roughness of the first side surface 231, increasing the diffuse reflection of natural light irradiating the first side surface 231, and reducing the specular reflection of the first side surface 231, thereby reducing
  • the reflectivity of the light on the first side surface 231 prevents the ambient light entering the array substrate 20 from having a high reflectivity on the first side surface 231 of the gate 23, which may adversely affect the visual effect.

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Abstract

一种阵列基板(20)及其制备方法、显示面板，阵列基板(20)包括衬底基板(21)以及设置于所述衬底基板(21)的上方的栅极(23)，所述栅极(23)包括靠近所述衬底基板(21)设置的第一侧面(231)以及与所述第一侧面(231)背向设置的第二侧面(232)，所述第一侧面(231)的粗糙度大于所述第二侧面(232)的粗糙度。

Description

阵列基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
 背景技术
随着液晶显示装置生产技术不断的发展，液晶显示装置逐步趋向窄边框化，乃至于无边框化；如图1所示，液晶显示面板一般包括相对设置的CF基板12和TFT基板11，无边框显示产品设计需要将TFT基板11侧朝外，以便进行印刷电路板的绑定。
然而，TFT基板11中的金属层（如栅极）没有挡光层遮挡，进入TFT基板11中的环境光（图1中箭头指示的方向为光射入的方向）在金属表面的反射率较大，影响视觉效果。
 技术问题
本申请实施例提供一种阵列基板，以解决进入阵列基板中的环境光在金属表面的反射率较大，影响视觉效果的技术问题。
 技术解决方案
第一方面，本申请实施例提供一种阵列基板，其包括衬底基板以及设置于所述衬底基板上的阵列层；
其中，所述阵列层包括设置于所述衬底基板的上方的栅极，所述栅极包括靠近所述衬底基板设置的第一侧面以及与所述第一侧面背向设置的第二侧面，所述第一侧面的粗糙度大于所述第二侧面的粗糙度。
在一些实施例中，所述栅极的第一侧面上设置有多个凹槽。
在一些实施例中，所述衬底基板靠近所述栅极的一侧上设置有多个凸起，所述栅极在所述衬底基板上的正投影覆盖所述凸起在所述衬底基板上的正投影。
在一些实施例中，所述凸起位于所述凹槽中并与所述凹槽一一对应。
在一些实施例中，所述凸起的形状与所述凹槽的形状相同，所述凸起的大小与所述凹槽的大小相同。
在一些实施例中，所述凸起与所述衬底基板一体成型。
在一些实施例中，所述衬底基板与所述栅极之间还设置有缓冲层，所述凸起位于所述缓冲层靠近所述栅极的一侧上，所述凸起与所述缓冲层一体成型。
在一些实施例中，所述栅极的第一侧面的纵截面整体呈波状。
第二方面，本发明还提供一种阵列基板的制备方法，包括以下步骤：
S10、提供一衬底基板；
S20、在所述衬底基板上形成阵列层；
其中，所述步骤S20包括：
S21、在所述衬底基板的第一部分的上方形成栅极，所述栅极包括靠近所述衬底基板设置的第一侧面以及与所述第一侧面背向设置的第二侧面，形成的所述第一侧面的粗糙度大于所述第二侧面的粗糙度。
在一些实施例中，在所述步骤S10后，并且所述步骤S21前，所述阵列基板的制备方法还包括：
S30、对所述衬底基板的第一部分的表面进行图案化处理，以形成多个凸起；
其中，所述栅极形成于所述衬底基板的第一部分上，并且所述栅极位于所述第一部分具有凸起的一侧。
在一些实施例中，在所述步骤S10后，并且所述步骤S21前，所述阵列基板的制备方法还包括：
S40、在所述衬底基板上形成缓冲层；
S50、对所述缓冲层的第二部分的表面进行图案化处理，以形成多个凸起，所述缓冲层的第二部分与所述衬底基板的第一部分对应。
其中，所述栅极形成于所述缓冲层的第二部分的表面上。
第三方面，本发明还提供一种显示面板，其包括彩膜基板和阵列基板，所述彩膜基板与所述阵列基板相对设置，所述彩膜基板与所述阵列基板之间设置有液晶层；所述阵列基板包括衬底基板以及设置于所述衬底基板上的阵列层；
其中，所述阵列层包括设置于所述衬底基板的上方的栅极，所述栅极包括靠近所述衬底基板设置的第一侧面以及与所述第一侧面背向设置的第二侧面，所述第一侧面的粗糙度大于所述第二侧面的粗糙度。
在一些实施例中，所述栅极的第一侧面上设置有多个凹槽。
在一些实施例中，所述衬底基板靠近所述栅极的一侧上设置有多个凸起，所述栅极在所述衬底基板上的正投影覆盖所述凸起在所述衬底基板上的正投影。
在一些实施例中，所述凸起位于所述凹槽中并与所述凹槽一一对应。
在一些实施例中，所述凸起的形状与所述凹槽的形状相同，所述凸起的大小与所述凹槽的大小相同。
在一些实施例中，所述凸起与所述衬底基板一体成型。
在一些实施例中，所述衬底基板与所述栅极之间还设置有缓冲层，所述凸起位于所述缓冲层靠近所述栅极的一侧上，所述凸起与所述缓冲层一体成型。
在一些实施例中，所述栅极的第一侧面的纵截面整体呈波状。
 有益效果
通过对衬底基板或缓冲层的表面进行处理，以在衬底基板上或缓冲层上形成多个凸起，从而使得栅极的第一侧面形成与凸起匹配的凹槽，从而增大第一侧面的粗糙度，可以增大自然光照射到第一侧面时的漫反射，减小第一侧面的镜面反射，从而降低光在第一侧面上的反射率，防止进入阵列基板中的环境光在栅极的第一侧面的反射率较大导致视觉效果受到不良影响。
 附图说明
图1为本发明背景技术中液晶显示面板的结构示意图；
图2为本发明一实施方式中阵列基板的结构示意图；
图3为本发明另一实施方式中阵列基板的结构示意图；
图4为本发明一实施方式中步骤S20的流程示意图；
图5至图10为本发明一实施方式中阵列基板的制备流程示意图；
图11为本发明一实施方式中显示面板的结构示意图。
附图标记：
11、TFT基板；12、CF基板；
20、阵列基板；21、衬底基板；211、第一部分；22、缓冲层；221、第二部分；23、栅极；231、第一侧面；232、第二侧面；24、栅极绝缘层；25、有源层；26、源漏金属层；27、钝化层；28、像素电极；291、凹槽；292、凸起；30、彩膜基板；40、液晶层；50、光阻层；60、导电金属层。
 本发明的实施方式
本申请提供一种阵列基板及其制备方法、显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请针对现有的显示面板中，阵列基板中的金属层（如栅极）没有挡光层遮挡，进入阵列基板中的环境光在金属表面的反射率较大，影响视觉效果的技术问题。本发明可以解决上述问题。
一种阵列基板，如图2所示，所述阵列基板20包括衬底基板21以及设置于所述衬底基板21上的阵列层。
具体的，所述阵列层包括设置于所述衬底基板21的上方的栅极23、覆盖所述栅极23的栅极绝缘层24、设置于所述栅极绝缘层24上的有源层25和与所述有源层25电连接的源漏金属层26、覆盖所述有源层25和所述源漏金属层26的钝化层27以及设置于所述钝化层27上的像素电极28，所述像素电极28通过搭接孔与所述源漏金属层26电连接。
其中，所述栅极23的制备材料包括但不限于铜、钼、铝、银和钛中的一种或多种。
具体的，所述栅极23包括靠近所述衬底基板21设置的第一侧面231以及与所述第一侧面231背向设置的第二侧面232，所述第一侧面231的粗糙度大于所述第二侧面232的粗糙度。
需要说明的是，栅极23由金属制成，对于本领域技术人员可知，通过对阵列基板20中的栅极23的第一侧面231进行处理，以加大第一侧面231的粗糙度，可以增大自然光照射到第一侧面231时的漫反射，减小第一侧面231的镜面反射，从而降低光在第一侧面231上的反射率，防止进入阵列基板20中的环境光在栅极23的第一侧面231的反射率较大导致视觉效果受到不良影响。
具体的，所述栅极23的第一侧面231上设置有多个凹槽291。通过在所述栅极23的第一侧面231设置多个凹槽291，以使得第一侧面231上具有凹凸不平的结构，从而增大第一侧面231的粗糙度。
其中，所述凹槽291可以呈有序排布（如阵列分布），也可以呈无序排布（如零散分布）。
具体的，所述衬底基板21靠近所述栅极23的一侧上设置有多个凸起292，所述栅极23在所述衬底基板21上的正投影覆盖所述凸起292在所述衬底基板21上的正投影。
需要说明的是，所述衬底基板21为透明基板，所述衬底基板21可以为塑料透明基板，也可以为玻璃透明基板；光穿过衬底基板21上与栅极23对应的区域处时，凸起292可以使得射出凸起292的光线发生大角度的偏转，从而减少射入到衬底基板21上的光线，防止进入阵列基板20中的环境光在栅极23的第一侧面231发生反射影响视觉效果。
进一步的，所述凸起292位于所述凹槽291中并与所述凹槽291一一对应。
进一步的，所述凸起292的形状与所述凹槽291的形状相同，所述凸起292的大小与所述凹槽291的大小相同。
利用凸起292与凹槽291可以降低光在栅极23的第一侧面231的反射率，同时通过凸起292与凹槽291的配合，可以避免凸起292导致阵列层的整体厚度增加，也可以提升栅极23在衬底基板21上的附着力。
在一实施方式中，所述凸起292与所述衬底基板21一体成型。
需要说明的是，所述衬底基板21包括与所述栅极23对应的第一部分211，所述栅极23设置于所述衬底基板21的所述第一部分211上，所述凸起292伸入所述凹槽291中。
其中，可以仅在所述第一部分211上设置凸起292，所述衬底基板21的其余部分上均未设置凸起292，以防止对其他膜层的功能造成不良影响。
在另一实施方式中，如图3所示，所述衬底基板21与所述栅极23之间还设置有缓冲层22，所述凸起292位于所述缓冲层22靠近所述栅极23的一侧上，所述凸起292与所述缓冲层22一体成型。
其中，所述缓冲层22的制备材料包括但不限于氮化硅、氧化硅、氮氧化硅和聚酰亚胺中的一种或多种，以防止所述栅极23中的金属向衬底基板21扩散。
需要说明的是，所述缓冲层22包括与所述栅极23对应的第二部分221，所述栅极23设置于所述缓冲层22的所述第二部分221上，所述凸起292伸入所述凹槽291中。
其中，可以仅在所述第二部分221上设置凸起292，所述缓冲层22的其余部分上均未设置凸起292，以防止对其他膜层的功能造成不良影响。
具体的，所述栅极的第一侧面的纵截面整体呈波状。
需要说明的是，所述栅极的第一侧面的纵截面的形状可以为连续的波状，也可以为非连续的波状。
基于上述阵列基板20，本发明还提供一种阵列基板20的制备方法，包括以下步骤：
S10、提供一衬底基板21；
S20、在所述衬底基板21上形成阵列层；
其中，如图4所示，所述步骤S20包括：
S21、在所述衬底基板21的第一部分211的上方形成栅极23，所述栅极23包括靠近所述衬底基板21设置的第一侧面231以及与所述第一侧面231背向设置的第二侧面232，形成的所述第一侧面231的粗糙度大于所述第二侧面232的粗糙度。
具体的，所述步骤S20还包括：
S22、形成覆盖所述栅极23的栅极绝缘层24；
S23、在所述栅极绝缘层24上形成有源层25；
S24、在所述栅极绝缘层24上形成与所述有源层25电连接的源漏金属层26；
S25、形成覆盖所述有源层25和所述源漏金属层26的钝化层27；
S26、在所述钝化层27上形成与所述源漏金属层26电连接的像素电极28。
在一实施方式中，在所述步骤S10后，并且所述步骤S21前，所述阵列基板20的制备方法还包括：
S30、对所述衬底基板21的第一部分211的表面进行图案化处理，以形成多个凸起292；
其中，所述栅极23形成于所述衬底基板21的第一部分211上，并且所述栅极23位于所述第一部分211具有凸起292的一侧。
需要说明的是，在所述第一部分211上形成栅极23时，由于凸起292的存在，栅极23的第一侧面231上会形成与凸起292配合的凹槽291，从而在所述第一侧面231上具有凹凸不平的结构，以使得所述第一侧面231的粗糙度大于所述第二侧面232的粗糙度，降低光在所述第一侧面231的反射率。
需要说明的是，对所述衬底基板21的第一部分211进行图案化处理可以采用等离子体处理、激光镭射、药液蚀刻或喷砂蚀刻等工艺。
在另一实施方式中，在所述步骤S10后，并且所述步骤S21前，所述阵列基板20的制备方法还包括：
S40、在所述衬底基板21上形成缓冲层22；
S50、对所述缓冲层22的第二部分221的表面进行图案化处理，以形成多个凸起292，所述缓冲层22的第二部分221与所述衬底基板21的第一部分211对应。
其中，所述栅极23形成于所述缓冲层22的第二部分221的表面上。
参见图5至图10，图5至图10为本发明一实施方式中阵列基板20的制备流程示意图。
如图5所示，提供一衬底基板21，在所述衬底基板21上使用光阻材料形成光阻层50。
如图6所示，对所述光阻层50进行处理，去除所述光阻层50上与所述第一部分211对应的区域，对所述第一部分211的表面进行图案化处理，以形成多个凸起292。
如图7所示，去除所述衬底基板21上的光阻层50，在所述衬底基板21上使用金属材料形成整面覆盖的导电金属层60，形成所述导电金属层60时，导电金属层60的底面上与所述第一部分211对应的区域处同时形成与凸起292匹配的凹槽291。
如图8所示，对导电金属层60进行图案化处理，以形成位于所述第一部分211上的栅极23。
如图9所示，在所述衬底基板21上形成覆盖所述栅极23的栅极绝缘层24，在所述栅极绝缘层24上形成有源层25。
如图10所示，在所述栅极绝缘层24上形成与所述有源层25电连接的源漏金属层26后，形成覆盖所述有源层25和所述源漏金属层26的钝化层27，在所述钝化层27上形成贯穿所述钝化层27并延伸至所述源漏金属层26的表面的搭接孔，在所述钝化层27上形成填充搭接孔并与所述源漏金属层26电连接的像素电极28。
需要说明的是，在另一实施方式中，所述凸起292形成于所述缓冲层22上时，阵列基板20的制备流程与上述凸起292形成于所述衬底基板21时的制备流程类似，不同点仅在于：所述衬底基板21上未设置凸起292，在所述衬底基板21上形成缓冲层22，在所述缓冲层22的第二部分221的表面形成凸起292后，在所述缓冲层22上形成所述栅极23。
基于上述阵列基板20，本发明还提供一种显示面板，如图11所示，所述显示面板包括彩膜基板30和上述任一实施方式中所述的阵列基板20，所述彩膜基板30与所述阵列基板20相对设置，所述彩膜基板30与所述阵列基板20之间设置有液晶层40。
本发明的有益效果为：通过对衬底基板21或缓冲层22的表面进行处理，以在衬底基板21上或缓冲层22上形成多个凸起292，从而使得栅极23的第一侧面231形成与凸起292匹配的凹槽291，从而增大第一侧面231的粗糙度，可以增大自然光照射到第一侧面231时的漫反射，减小第一侧面231的镜面反射，从而降低光在第一侧面231上的反射率，防止进入阵列基板20中的环境光在栅极23的第一侧面231的反射率较大导致视觉效果受到不良影响。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (19)

  1. 一种阵列基板，其中，所述阵列基板包括衬底基板以及设置于所述衬底基板上的阵列层；
    其中，所述阵列层包括设置于所述衬底基板的上方的栅极，所述栅极包括靠近所述衬底基板设置的第一侧面以及与所述第一侧面背向设置的第二侧面，所述第一侧面的粗糙度大于所述第二侧面的粗糙度。
  2. 根据权利要求1所述的阵列基板，其中，所述栅极的第一侧面上设置有多个凹槽。
  3. 根据权利要求2所述的阵列基板，其中，所述衬底基板靠近所述栅极的一侧上设置有多个凸起，所述栅极在所述衬底基板上的正投影覆盖所述凸起在所述衬底基板上的正投影。
  4. 根据权利要求3所述的阵列基板，其中，所述凸起位于所述凹槽中并与所述凹槽一一对应。
  5. 根据权利要求4所述的阵列基板，其中，所述凸起的形状与所述凹槽的形状相同，所述凸起的大小与所述凹槽的大小相同。
  6. 根据权利要求3所述的阵列基板，其中，所述凸起与所述衬底基板一体成型。
  7. 根据权利要求3所述的阵列基板，其中，所述衬底基板与所述栅极之间还设置有缓冲层，所述凸起位于所述缓冲层靠近所述栅极的一侧上，所述凸起与所述缓冲层一体成型。
  8. 根据权利要求3所述的阵列基板，其中，所述栅极的第一侧面的纵截面整体呈波状。
  9. 一种阵列基板的制备方法，其中，包括以下步骤：
    S10、提供一衬底基板；
    S20、在所述衬底基板上形成阵列层；
    其中，所述步骤S20包括：
    S21、在所述衬底基板的第一部分的上方形成栅极，所述栅极包括靠近所述衬底基板设置的第一侧面以及与所述第一侧面背向设置的第二侧面，形成的所述第一侧面的粗糙度大于所述第二侧面的粗糙度。
  10. 根据权利要求9所述的阵列基板的制备方法，其中，在所述步骤S10后，并且所述步骤S21前，所述阵列基板的制备方法还包括：
    S30、对所述衬底基板的第一部分的表面进行图案化处理，以形成多个凸起；
    其中，所述栅极形成于所述衬底基板的第一部分上，并且所述栅极位于所述第一部分具有凸起的一侧。
  11. 根据权利要求9所述的阵列基板的制备方法，其中，在所述步骤S10后，并且所述步骤S21前，所述阵列基板的制备方法还包括：
    S40、在所述衬底基板上形成缓冲层；
    S50、对所述缓冲层的第二部分的表面进行图案化处理，以形成多个凸起，所述缓冲层的第二部分与所述衬底基板的第一部分对应。
    其中，所述栅极形成于所述缓冲层的第二部分的表面上。
  12. 一种显示面板，其中，所述显示面板包括彩膜基板和阵列基板，所述彩膜基板与所述阵列基板相对设置，所述彩膜基板与所述阵列基板之间设置有液晶层；所述阵列基板包括衬底基板以及设置于所述衬底基板上的阵列层；
    其中，所述阵列层包括设置于所述衬底基板的上方的栅极，所述栅极包括靠近所述衬底基板设置的第一侧面以及与所述第一侧面背向设置的第二侧面，所述第一侧面的粗糙度大于所述第二侧面的粗糙度。
  13. 根据权利要求12所述的显示面板，其中，所述栅极的第一侧面上设置有多个凹槽。
  14. 根据权利要求13所述的显示面板，其中，所述衬底基板靠近所述栅极的一侧上设置有多个凸起，所述栅极在所述衬底基板上的正投影覆盖所述凸起在所述衬底基板上的正投影。
  15. 根据权利要求14所述的显示面板，其中，所述凸起位于所述凹槽中并与所述凹槽一一对应。
  16. 根据权利要求15所述的显示面板，其中，所述凸起的形状与所述凹槽的形状相同，所述凸起的大小与所述凹槽的大小相同。
  17. 根据权利要求14所述的显示面板，其中，所述凸起与所述衬底基板一体成型。
  18. 根据权利要求14所述的显示面板，其中，所述衬底基板与所述栅极之间还设置有缓冲层，所述凸起位于所述缓冲层靠近所述栅极的一侧上，所述凸起与所述缓冲层一体成型。
  19. 根据权利要求14所述的显示面板，其中，所述栅极的第一侧面的纵截面整体呈波状。
PCT/CN2019/127547 2019-12-13 2019-12-23 阵列基板及其制备方法、显示面板 WO2021114385A1 (zh)

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