WO2021097690A1 - 显示基板及其制作方法和显示装置 - Google Patents

显示基板及其制作方法和显示装置 Download PDF

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Publication number
WO2021097690A1
WO2021097690A1 PCT/CN2019/119581 CN2019119581W WO2021097690A1 WO 2021097690 A1 WO2021097690 A1 WO 2021097690A1 CN 2019119581 W CN2019119581 W CN 2019119581W WO 2021097690 A1 WO2021097690 A1 WO 2021097690A1
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Prior art keywords
layer
display area
substrate
cathode
display
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PCT/CN2019/119581
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English (en)
French (fr)
Inventor
徐鹏
邓江涛
丁渭渭
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19946248.2A priority Critical patent/EP4064358A4/en
Priority to US17/051,129 priority patent/US11997890B2/en
Priority to PCT/CN2019/119581 priority patent/WO2021097690A1/zh
Priority to CN201980002494.8A priority patent/CN113141779A/zh
Publication of WO2021097690A1 publication Critical patent/WO2021097690A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the electroluminescent display substrate has the advantages of active light emission, wide visual range, fast response, etc., and is widely used in display devices.
  • a display substrate has a display area and a non-display area adjacent to the display area.
  • the display substrate includes a substrate, a voltage signal line provided on the first side of the substrate, a drive circuit structure provided on the first side of the substrate, and a side of the voltage signal line and the drive circuit structure away from the substrate.
  • the cathode overlap layer and the cathode layer provided on the first side of the substrate.
  • the voltage signal line is located in the non-display area and arranged around the display area.
  • the driving circuit structure is located in the non-display area, and is located on the side of the voltage signal line close to the display area.
  • the cathode strapping layer is located in the non-display area and arranged around the display area; the cathode strapping layer includes a first part away from the display area and a second part extending in a direction closer to the display area, the first part and the second part are connected At least part of the surface of the first part close to the substrate is in electrical contact with the corresponding part of the voltage signal line; the orthographic projection of the second part on the substrate and the orthographic projection of the drive circuit structure on the substrate at least partially overlap.
  • the cathode layer extends from the display area to the non-display area, and the edge of the cathode layer is located in the non-display area, and the cathode layer is in electrical contact with at least a part of the surface of the second part of the cathode lap layer away from the substrate.
  • the display substrate further includes a pixel definition layer disposed on the first side of the substrate.
  • the pixel definition layer includes a main body of the pixel definition layer located on the side of the cathode layer close to the substrate, the main body of the pixel definition layer extends from the display area to the non-display area, and the edge of the main body of the pixel definition layer is located in the non-display area.
  • the main body of the pixel definition layer covers the edge of the cathode bonding layer close to the display area, and covers the surface of the second part of the cathode bonding layer away from the substrate; the edge of the main body of the pixel definition layer is closer to the display area than the edge of the cathode layer.
  • the portion of the main body of the pixel definition layer located in the display area has a plurality of openings, and the plurality of openings are configured to define light-emitting regions of a plurality of sub-pixels.
  • the display substrate further includes: a source and drain metal layer disposed on the first side of the substrate, the source and drain in the voltage signal line and the driving circuit structure are located in the source and drain metal layer;
  • the flat layer on the first side of the flat layer includes a flat layer body disposed between the source and drain metal layer, the pixel definition layer body and the cathode lap layer.
  • the flat layer body extends from the display area to the non-display area and is flat The edge of the layer body is located in the non-display area.
  • the flat layer main body completely covers the driving circuit structure; the cathode lap layer covers the edge of the flat layer main body away from the display area, and covers at least part of the surface of the flat layer main body away from the substrate.
  • the cathode overlap layer has a plurality of through holes distributed in an array, at least one through hole of the plurality of through holes penetrates the cathode overlap layer, and at least part of the through holes of the plurality of through holes are on the substrate
  • the orthographic projection of is within the range of the orthographic projection of the main body of the flat layer on the substrate.
  • the display substrate further includes a plurality of fillers filled in the plurality of through holes in a one-to-one correspondence, and the material of at least one filler of the plurality of fillers is the same as the material of the main body of the pixel definition layer.
  • the display substrate further includes: a first barrier dam disposed on the first side of the substrate, the first barrier dam is located in the non-display area, and the source and drain metal layers extend from the display area to the non-display area.
  • the first barrier dam is close to the side of the display area; the cathode strap extends from the display area to the non-display area to the side of the first barrier dam near the display area, and the portion of the cathode strap that is in electrical contact with the voltage signal line Located between the main body of the flat layer and the first blocking dam.
  • the material of the first barrier dam includes a material that forms the main body of the pixel definition layer and/or a material that forms the main body of the flat layer.
  • the display substrate further includes: an inorganic insulating layer disposed on the first side of the substrate, the inorganic insulating layer includes an interlayer dielectric layer closer to the substrate than the source and drain metal layer; the interlayer dielectric layer extends from the display area Extending to the non-display area, and the edge of the interlayer dielectric layer is located on the side of the first barrier dam away from the display area, and the portion of the interlayer dielectric layer extending to the side of the first barrier dam away from the display area is formed with at least one groove, at least one The groove is arranged around the first blocking dam.
  • the display substrate further includes: an anode layer disposed between the flat layer main body and the pixel definition layer main body and located in the display area, the anode layer includes a plurality of anodes, and the plurality of anodes correspond to the plurality of openings in a one-to-one manner; At least one organic functional layer disposed on the side of the main body of the pixel definition layer away from the substrate, the at least one organic functional layer extends from the display area to the non-display area, and the edge of the at least one organic functional layer is located in the non-display area, The edge of at least one organic functional layer is closer to the display area than the edge of the main body of the pixel definition layer.
  • the at least one organic functional layer includes at least one of an electron transport layer, an electron injection layer, a hole transport layer, or a hole injection layer.
  • the display area is substantially rectangular, and the cathode lap layer is arranged around two long sides and one short side of the rectangle.
  • the width of the contact portion of the cathode layer and the cathode bonding layer in the first direction is D 1 , D 1 is greater than or equal to 150 ⁇ m, and Less than or equal to 350 ⁇ m; in the non-display area corresponding to a short side, the width of the contact portion of the cathode layer and the cathode overlap layer in the first direction is D 2 , D 2 is less than D 1 and greater than zero.
  • the first direction is a direction parallel to the substrate and perpendicular to the interface between the display area and the non-display area.
  • the display substrate further includes: a light extraction layer disposed on the side of the cathode layer away from the substrate, the light extraction layer extends from the display area to the non-display area, and the edge of the light extraction layer is located in the non-display area.
  • the orthographic projection of at least part of the edge of the take-out layer on the substrate is within the scope of the orthographic projection of the cathode layer on the substrate.
  • the orthographic projection of the edge of the light extraction layer on the substrate substantially coincides with the orthographic projection of the edge of the cathode layer on the substrate.
  • the display substrate further includes: an anti-reflection layer disposed on the side of the light extraction layer away from the cathode layer, the anti-reflection layer extends from the display area to the non-display area, and the edge of the anti-reflection layer is located in the non-display area,
  • the orthographic projection of the antireflection layer on the substrate is within the scope of the orthographic projection of the cathode layer on the substrate.
  • the antireflection layer includes a lithium fluoride layer.
  • the display substrate further includes: a second barrier dam disposed on the surface of the cathode lap layer away from the substrate, the second barrier dam and the cathode layer, the light extraction layer and the antireflection layer are perpendicular to the substrate. There is no overlap in the direction.
  • the distance between the edge of the cathode layer and the second barrier dam in the first direction is greater than or equal to 80 ⁇ m; the distance between the edge of the antireflection layer and the second barrier dam in the first direction is greater than or equal to 250 ⁇ m;
  • One direction is a direction parallel to the substrate and perpendicular to the interface between the display area and the non-display area.
  • the display substrate further includes an encapsulation layer
  • the encapsulation layer includes: a first inorganic barrier layer disposed on the side of the antireflection layer away from the light extraction layer, the first inorganic barrier layer covers the second barrier dam; The organic barrier layer of an inorganic barrier layer far from the antireflection layer, the organic barrier layer is located at least within the area enclosed by the second barrier dam; and the organic barrier layer is arranged on the side of the organic barrier layer away from the first inorganic barrier layer The second inorganic barrier layer covers the second barrier dam.
  • a method for manufacturing a display substrate includes a display area and a non-display area adjacent to the display area.
  • the manufacturing method includes: providing a substrate; forming a voltage signal line and a drive circuit structure on the first side of the substrate, the voltage signal line is located in the non-display area and arranged around the display area, and the drive circuit structure is located in the non-display area and is located on the voltage signal line
  • the cathode lap layer is formed on the substrate on which the voltage signal line and the drive circuit structure are formed, the cathode lap layer is located in the non-display area and is arranged around the display area;
  • the cathode lap layer includes a distance away from the display area
  • the first part and the second part extending in the direction close to the display area are connected to the second part; at least part of the surface of the first part close to the substrate is in electrical contact with the corresponding part of the voltage signal line; the second part is on the substrate
  • the method before the step of forming a cathode lap layer on the substrate on which the voltage signal line and the driving circuit structure are formed, the method further includes: forming a patterned flat layer on the first side of the substrate, and the patterned flat layer is formed on the first side of the substrate.
  • the flat layer includes a flat layer body and a first barrier layer.
  • the flat layer main body extends from the display area to the non-display area, and the edge of the flat layer main body is located in the non-display area, and there is no overlap between the flat layer main body and the voltage signal line in the direction perpendicular to the substrate.
  • the first barrier layer is located on a side of the voltage signal line away from the display area.
  • the method before the step of forming the cathode layer on the substrate on which the cathode layer lap layer is formed, the method further comprises: forming a patterned pixel definition layer on the first side of the substrate, and the patterned pixel definition layer
  • the layer includes a pixel definition layer body, a plurality of fillers, a second barrier layer, and a third barrier layer.
  • the main body of the pixel definition layer extends from the display area to the non-display area, and the edge of the main body of the pixel definition layer is located in the non-display area; the main body of the pixel definition layer covers the edge of the cathode bonding layer close to the display area, and covers the edge of the cathode bonding layer.
  • the second part is far away from part of the surface of the substrate; the edge of the main body of the pixel definition layer is closer to the display area than the edge of the cathode layer; the part of the main body of the pixel definition layer in the display area has a plurality of openings, and the plurality of openings are configured to define a plurality of sub-pixels The light-emitting area.
  • the cathode lap layer is provided with a plurality of through holes distributed in an array, and at least one through hole of the plurality of through holes penetrates the surface of the cathode lap layer away from the substrate and the surface of the cathode lap layer close to the substrate; and The fillers are filled into the multiple through holes in a one-to-one correspondence.
  • the second barrier layer is located on the side of the cathode bonding layer and the voltage signal line away from the display area.
  • the third barrier layer is located on the surface of the cathode overlap layer away from the substrate, and the second barrier dam has no overlap with the cathode layer, the light extraction layer and the antireflection layer in the direction perpendicular to the substrate.
  • a display device in another aspect, includes the display substrate as described in any of the above-mentioned embodiments.
  • FIG. 1 is a top view of a display substrate according to some embodiments of the present disclosure
  • FIG. 2 is a cross-sectional view showing a partial structure of the substrate along the AA direction in FIG. 1;
  • 3-13 are top views corresponding to each step in the manufacturing process of the display substrate provided according to some embodiments of the present disclosure.
  • FIG. 14 is a flowchart of a manufacturing method of a display substrate according to some embodiments of the present disclosure.
  • FIG. 15 is a flowchart of another method for manufacturing a display substrate according to some embodiments of the present disclosure.
  • FIG. 16 is a structural diagram of a display device provided according to some embodiments of the present disclosure.
  • the display substrate has a display area and a non-display area.
  • the display area is provided with multiple sub-pixels.
  • Each sub-pixel includes at least a pixel circuit structure, an anode, a light-emitting part, and a cathode, which are sequentially superimposed.
  • a driving voltage is applied to the light-emitting part through the anode and the cathode, so that the light-emitting part can emit light under the action of the driving voltage.
  • Screen display can be realized by emitting light from the light-emitting parts of multiple sub-pixels.
  • the non-display area is adjacent to the display area, and the non-display area surrounds the display area in a full circle.
  • the non-display area is provided with a voltage signal line and a cathode bonding layer, and the voltage signal line is in electrical contact with the lower surface of the cathode bonding layer.
  • the cathodes of multiple sub-pixels constitute the cathode layer (the cathode layer is a whole layer, or the cathode layer has a pattern in the display area), and the cathode layer extends from the display area to the non-display area and overlaps on the upper surface of the cathode lap layer Therefore, the plurality of cathodes of the cathode layer can be electrically connected to the voltage signal line.
  • some embodiments of the present disclosure provide a display substrate 100.
  • the display substrate 100 has a display area Q 1 and a non-display area Q 2 adjacent to the display area.
  • the non-display area Q 2 is arranged in a circle around the display area Q 1.
  • the display substrate 100 includes a substrate 11, a voltage signal line 13, a driving circuit structure 14, a cathode bonding layer 17 and a cathode layer 24.
  • the voltage signal line 13 is arranged on the first side of the substrate 11, and the voltage signal line 13 is located in the non-display area Q 2 and is arranged around the display area Q 1 .
  • the display region Q 1 is substantially rectangular, the voltage of the signal line 13 surrounding the display area Q long sides and two short sides 1 a, and the portion extending from the other short side along the a direction away from the display region Q 1 'lead.
  • the driving circuit structure 14 is disposed on the first side of the substrate 11, and the driving circuit structure 14 is located in the non-display area Q 2 , and is located on the side of the voltage signal line 13 close to the display area Q 1 . Illustratively, as shown in FIG. 3, around the display region Q 1 'is provided with a ring of driving circuit structure 14. It should be noted that the driving circuit structure 14 is configured to drive the pixel circuit structure in each sub-pixel as described above, so that the light-emitting portion in each sub-pixel emits light.
  • the driving circuit structure 14 includes a GOA (Gate Driver On Array, array substrate row drive) circuit, for example, includes two sets of GOAs of EM GOA and Gate GOA, where EM GOA outputs EM (luminescence) signals, and Gate GOA outputs Gate signals.
  • GOA Gate Driver On Array, array substrate row drive
  • the cathode lap layer 17 is disposed on the first side of the substrate 11, and the cathode lap layer 17 is disposed on the side of the voltage signal line 13 and the driving circuit structure 14 away from the substrate 11, and the cathode lap layer 17 is located in the non-display area.
  • Q 2 is set around the display area Q 1 .
  • the cathode layer 17 overlap may be a complete circle, the edge portion may be provided around the display region surrounding the display region Q 1 is provided.
  • the display region Q 1 is substantially rectangular, overlapping layers of the cathode 17 surrounding the display area Q long sides and two short sides 1 a. It will be appreciated, in other examples, the cathode layer 17 may be overlapped around the sides of the display region only two Q 1 is long.
  • the cathode strapping layer 17 includes a first portion 171 away from the display area Q 1 and a second portion 172 extending in a direction closer to the display area Q 1 , and the first portion 171 and the second portion 172 are connected. At least part of the surface of the first part 171 close to the substrate 11 is in electrical contact with the corresponding part of the voltage signal line 13, for example, the voltage signal line 13 is overlapped on at least part of the surface of the first part 171 close to the substrate 11 to achieve electrical connection;
  • the orthographic projection of the portion 172 on the substrate 11 and the orthographic projection of the drive circuit structure 14 on the substrate 11 at least partially overlap.
  • the second portion 172 of the cathode strapping layer 17 is closer to the display area Q 1 , so that it is electrically connected to the cathode layer 24 to reduce the area of the cathode layer.
  • the cathode strapping layer 17 and the anode layer in the display area Q 1 of the display substrate 100 are made of the same layer and the same material, which facilitates simplification The manufacturing process of the display substrate 100.
  • the material of the cathode bonding layer 17 includes at least one of metal or conductive metal oxide.
  • the cathode layer 24 is disposed on the first side of the substrate 11, the cathode layer 24 extends from the display area Q 1 to the non-display area Q 2 , and the edge z 2 of the cathode layer 24 is located in the non-display area Q 2 Inside.
  • the cathode layer 24 is in electrical contact with at least a part of the surface of the second portion 172 of the cathode bonding layer 17 away from the substrate 11, for example, the cathode layer 24 is overlapped on at least a part of the surface of the second portion 172 away from the substrate to achieve electrical connection.
  • This design can ensure that the cathode layer 24 is electrically connected to the voltage signal line 13 while reducing the area of the cathode layer 24, thereby ensuring the reliability of the packaging while correspondingly reducing the area of the packaging layer 27, so that the display substrate 100
  • the size of the non-display area Q 2 in the first direction X is reduced, that is , the proportion of the non-display area Q 2 in the entire display substrate is reduced, which will enable the frame of the display device using the display substrate 100 to be reduced accordingly. Small, which improves the screen-to-body ratio of the display device.
  • the first direction X parallel to the substrate 11, and is perpendicular to the display area and the non-display region Q 1 Q 2 interface (i.e. the display area of a boundary surface Q M).
  • the material of the cathode layer 24 includes, but is not limited to, one or a combination of silver, magnesium, and ytterbium.
  • the width of the contact portion of the cathode layer 24 and the cathode lap layer 17 in the first direction X is D 1 , as shown in Fig.
  • D 1 is greater than or equal to 150 ⁇ m and less than or equal to 350 ⁇ m; in the non-display area Q 2 In the region corresponding to the one short side, the width of the contact portion of the cathode layer 24 and the cathode lap layer 17 in the first direction X is D 2 , D 2 is less than D 1 and greater than zero.
  • D 1 ranges from 150 ⁇ m to 250 ⁇ m, for example, 150 ⁇ m, 180 ⁇ m, 200 ⁇ m, 210 ⁇ m, 230 ⁇ m, or 250 ⁇ m. In other examples, D 1 ranges from 250 ⁇ m to 350 ⁇ m, for example, 260 ⁇ m, 280 ⁇ m, 300 ⁇ m, 310 ⁇ m, 330 ⁇ m, or 350 ⁇ m.
  • the width of the voltage signal line 13 along the first direction X is 150 ⁇ m ⁇ 250 ⁇ m.
  • the cathode layer in a first direction X overlap width should be greater than or equal to 300 m (which comprises The cathode layer 24 is in electrical contact with 150 ⁇ m and the voltage signal line is in electrical contact with 150 ⁇ m).
  • the display can guarantee long-range uniformity, reliability of the package substrate 100, and it helps to reduce the non-display region of the substrate 100 along a first direction X Q 2 the width L, such that the non-display area occupied by Q 2
  • the reduced ratio reduces the frame of the display device using the display substrate 100 and increases the screen-to-body ratio.
  • the display substrate 100 further includes a pixel definition layer.
  • a pixel defining layer disposed on the first side of the substrate 11, the pixel defining layer comprises a layer adjacent to the cathode substrate main body 11 side of the pixel defining layer 24 of 20, the pixel defining layer extends from the body 20 to a non-display region Q 1 Display area Q 2 .
  • Q display area extends to a boundary of the pixel defining layer body portion Q 2 non-display area from the display area 20 may be a mesh structure similar to the opening is formed, the whole layer structure may be provided without an opening, a display region Q a pixel defining layer and the body region Q displaying a boundary extending to the non-display region Q pixel definition layer 2 from the main body are integral.
  • the edge z 1 of the pixel definition layer main body 20 is located in the non-display area Q 2 .
  • a pixel defining layer covers the edges of the body 20 near the display region overlapping the cathode layer 17 Q 1 ', and the cover portion away from the substrate surface 172 of the second portion 11 of the cathode 17 overlapping layers.
  • the surface of the second portion 172 of the bonding layer 17 away from the substrate 11 is exposed to prevent the main body 20 of the pixel definition layer from influencing the electrical contact between the cathode layer 24 and the cathode bonding layer 17.
  • the cathode layer 24 includes a part covering the main body 20 of the pixel definition layer and a part covering the cathode bonding layer 17, and these two parts are continuous.
  • the body portion of the pixel defining layer 20 of the display area Q 1 has a plurality of openings 202, 202 of the light emitting area of the pixel is configured to define a plurality of sub-plurality of openings, and therefore the pixel defining layer 20 in the body within a substantially reticular structure display region Q .
  • the display substrate 100 can display a picture by controlling the light emission of a plurality of sub-pixels.
  • part of the non-display region Q 2 pixel defining layer body 20 is located may have an opening, which is located in the non-display region Q of the opening 2 can be used as dummy pixels, in order to ensure the display region Q 1 subpixels reliable Or balance the load of each row or column. It is used to increase the display brightness at the edge of the display area Q 1.
  • the display substrate 100 further includes a source and drain metal layer and a flat layer.
  • the source and drain metal layers are disposed on the first side of the substrate 11, and the source and drain electrodes in the voltage signal line 13 and the driving circuit structure 14 are all located in the source and drain metal layers.
  • the structure of the display substrate 100 is simplified, and the display substrate 100 is easier to manufacture.
  • the source and drain metal layers are patterned.
  • the source and drain in the voltage signal line 13 and the drive circuit structure 14 are both located in the source and drain metal layers, the voltage signal line 13 and the drive circuit There is a gap between the source and drain in the structure 14, that is, the voltage signal line 13 is disconnected from the source and drain in the driving circuit structure 14, and there is no electrical contact.
  • the display area 100 Q of the substrate 1 in each sub-pixel includes a pixel circuit configuration, the source and drain of the pixel circuit configuration is also provided to the source-drain metal layer.
  • the planarization layer includes a planarization layer main body 15 disposed between the source and drain metal layer, the pixel definition layer main body 20, and the cathode bonding layer 17, and the planarization layer main body 15 extends from the display area Q 1 to the non- The display area Q 2 , and the edge of the flat layer main body 15 is located in the non-display area Q 2 .
  • the flat layer body 15 completely covers the driving circuit structure.
  • the cathode layer 17 overlapping edge of the flat cover layer remote from the display region Q 1 of the main body 15, and covers at least a portion of the substrate 15 remote from the surface of the main body 11 of the planarization layer.
  • the film layer on the flat layer main body 15 (for example, the pixel defining layer main body 20, part of the cathode overlap layer 17, and the multiple anodes 18 shown in FIGS. 6 and 7) can be made more flat .
  • the cathode lap layer 17 has a plurality of through holes 173 distributed in an array, and at least one through hole 173 of the plurality of through holes 173 penetrates the cathode lap layer 17. .
  • the orthographic projection of at least part of the through-holes 173 among the plurality of through-holes 173 on the substrate 11 is within the range of the orthographic projection of the flat layer body 15 on the substrate 11. In this way, in the process of manufacturing the display substrate 100, the gas generated in the film layer (such as the flat layer main body 15) under the cathode lap layer 17 can be released, which improves the reliability of the display substrate.
  • the display substrate 100 further includes a plurality of fillers 201.
  • the plurality of fillers 201 are filled in the plurality of through holes 173 in a one-to-one correspondence, and the material of at least one filler 201 of the plurality of fillers 201 is the same as the material of the pixel definition layer main body 20.
  • the upper surface of the cathode lap layer 17 can be flattened, which is convenient for making other film layers on the cathode lap layer 17; on the other hand, multiple fillers 201 and the pixel definition layer 20 can be made in the same layer, which is convenient Advantages of production.
  • the cathode layer 24 is overlapped with the cathode overlap layer 17, the actual electrical connection area is grid-shaped, and the through hole 173 filled with filler is non-conductive.
  • the through hole 173 is a square hole or a round hole or other irregularly shaped holes.
  • the display substrate 100 further includes a first blocking dam 16.
  • the first barrier dam 16 is disposed on the first side of the substrate 11, and the first barrier dam 16 is located in the non-display area Q 2 .
  • Source-drain metal layer i.e., in FIG. 2 includes a voltage source signal line 14 in the source and drain electrodes 13 and the driving circuit structure drain metal layer
  • first a direction X extends into a first barrier dam 16 near the side of the display region Q 1 '.
  • the cathode layer 17 overlapping the first barrier dam 16 extends close to the side of the display region Q 1 'Q 1 direction from the display area to the non-display region Q 2 in the direction (i.e., a first direction X), and the cathode layer 17 and overlapping The part (for example, the first part 171) that the voltage signal line 13 electrically contacts is located between the flat layer body 15 and the first barrier dam 16.
  • the first barrier dam 16 can be used to define the manufacturing positions of the voltage signal lines 13 and the cathode lap layer 17 in the source-drain metal layer, so as to achieve the purpose of simplifying the manufacturing process of the display substrate.
  • the first annular barrier dam 16 surrounding the display area Q 1 and disposed in a circle.
  • the first barrier dam 16 downward tapered shape (i.e., the area near the surface of the substrate 11 which is larger than the surface area of the substrate 11 away), so that the first side barrier dam 16 near the display region Q 1 'is beveled. In this way, after the source-drain metal layer and the cathode strapping layer 17 are fabricated, the source-drain metal layer and the cathode strapping layer 17 may partially overlap with the first barrier dam 16.
  • the material of the first barrier dam 16 includes the material forming the pixel definition layer main body 20 and/or the material forming the flat layer main body 15.
  • the first barrier dam 16 includes a first barrier layer 161 made of the same material and the same layer as the flat layer main body 15, and the same material and the same material as the pixel definition layer main body 20
  • the second barrier layer 162 made in the same layer, the first barrier layer 161 and the second barrier layer 162 are sequentially stacked to form the first barrier dam 16.
  • the first barrier dam 16 may also include only one of the first barrier layer 161 and the second barrier layer 162.
  • the first barrier dam 16 only includes the above-mentioned first barrier layer 161; or, The barrier dam 16 only includes the second barrier layer 162 described above.
  • the first barrier dam 16 may include three or more barrier layers, that is, the first barrier dam 16 may include the first barrier layer 161 and the second barrier layer 162, as well as those shown in FIG. 2
  • One or more barrier layers made of the same material as the interlayer dielectric layer 12, gate insulation layer (not shown), passivation layer and other inorganic insulation layers.
  • the first barrier dam 16 can also be combined with the gate metal layer ( (Not shown in the figure), active semiconductor layer (not shown in the figure) and other functional layers are overlapped to form the required height of the first barrier dam.
  • the barrier layer is located between the first barrier layer 161 and the substrate 11.
  • At least part of the barrier layer included in the first barrier dam 16 is made of organic materials.
  • a baking process may be included. For example, after the first barrier layer 161 and the second barrier layer 162 are fabricated, The baking process causes the first barrier layer 161 and the second barrier layer 162 to form an integrated structure.
  • the display substrate 100 further includes an inorganic insulating layer disposed on the first side of the substrate 11.
  • the inorganic insulating layer includes an interlayer dielectric that is closer to the substrate 11 than the source/drain metal layer.
  • Layer 12 gate insulating layer (not shown), passivation layer (not shown), and the like.
  • the display substrate 100 further includes a gate metal layer, an active semiconductor layer, etc., which are disposed on the first side of the substrate 11.
  • the interlayer dielectric layer 12 extends from the display area Q 1 to the non-display area Q 2 , and the edge of the interlayer dielectric layer 12 is located on the side of the first barrier dam 16 away from the display area Q 1 , and the interlayer dielectric layer 12 extends to the first At least one groove 121 is formed at a portion of the barrier dam 16 on the side away from the display area Q 1 , and the at least one groove 121 is disposed around the first barrier dam 16. In this way, in the process of manufacturing the display substrate 100, at least one groove 121 can block the inward propagation of cracks on the inorganic insulating layer (including the interlayer dielectric layer 12) from affecting the display area, thereby improving the reliability of the display substrate 100.
  • the display substrate 100 is an electroluminescence display substrate.
  • the display substrate 100 further comprising: disposed between the pixel defining layer 15 and the planarization layer main body 20, and the display area Q of the anode layer 1, the anode The layer includes a plurality of anodes 18, and the plurality of anodes 18 correspond to the plurality of openings 202 in a one-to-one manner.
  • the display substrate 100 further includes at least one organic functional layer disposed on the side of the pixel definition layer main body 20 away from the substrate 11, and the at least An organic functional layer extends from the display area Q 1 to the non-display area Q 2 , and the edge of the at least one organic functional layer is located in the non-display area Q 2 , and the edge of the at least one organic functional layer is greater than The edge z 1 of the pixel definition layer main body 20 is closer to the display area Q 1 .
  • the distance d 1 between the edge of the at least one organic functional layer and the display area Q 1 is greater than or equal to 100 ⁇ m, for example, d 1 is 100 ⁇ m or 110 ⁇ m or 120 ⁇ m or 130 ⁇ m or 150 ⁇ m
  • the distance d 2 between the edge of the at least one organic functional layer and the edge z 1 of the pixel definition layer main body 20 is greater than or equal to 50 ⁇ m, for example, d 2 is 50 ⁇ m or 60 ⁇ m or 70 ⁇ m or 80 ⁇ m or 100 ⁇ m.
  • the width L along the first direction X reduces the proportion of the non-display area Q 2 and also reduces the frame of the display device using the display substrate 100 and increases the screen-to-body ratio.
  • the at least one organic functional layer includes at least one of an electron transport layer 23, an electron injection layer, an organic light emitting layer 22, a hole transport layer 21, or a hole injection layer.
  • an electron transport layer 23, the electron injection layer, the hole transport layer 21, and the hole injection layer carriers can be uniformly injected into the organic light emitting layer 22, and the luminous efficiency of the display substrate 100 is improved.
  • At least one of the electron transport layer 23, the electron injection layer, the hole transport layer 21, and the hole injection layer may be a film layer made by using an open mask (OPM, Open Mask), because edge shadow effect, the boundary layer is thin, but the display substrate 100 formed in the outermost layer of the edge positions of these layers is defined in the body than the pixel edge 20 is closer to the display region Q 1 '.
  • OPM Open Mask
  • the organic light-emitting layer 22 may be formed by an evaporation process using a fine metal mask (FMM, Fine Metal Mask), and a pre-designed effective opening area is left on the high-precision metal mask through which the effective opening area
  • FMM Fine Metal Mask
  • the material for forming the organic light-emitting layer can be deposited at the corresponding opening 202 on the pixel definition layer body 20, thereby forming a plurality of light-emitting parts 221 of the organic light-emitting layer 22.
  • the area of the orthographic projection of at least one of the plurality of light-emitting portions 221 on the substrate 11 is larger than the area of the opening of the pixel definition layer body corresponding to it (at this time by designing finely
  • the area of the effective opening area on the metal mask is larger than the area of the corresponding opening on the main body of the pixel definition layer, that is, the area of the orthographic projection of the formed light-emitting portion 221 on the substrate 11 is larger than that of the main body of the pixel definition layer.
  • the area of the opening ).
  • the edge (that is, the outer edge of the entire organic light-emitting layer 22) of the smallest pattern area (such as a rectangular area) where the plurality of light-emitting parts 221 are located is closer to the display area Q 1 than the edge of the pixel definition layer main body 20.
  • Such a design will not easily affect the production of other film layers.
  • the light-emitting portion 221 will not be formed on the cathode overlap layer 17, so that the contact effect of the cathode layer 24 and the cathode overlap layer 17 will not be affected.
  • the area of the orthographic projection of the formed light-emitting portion 221 on the substrate 11 is larger than the area of the opening of the corresponding pixel definition layer body, the light-emitting area of the sub-pixels defined by each opening of the pixel definition layer body can also be made uniform. Luminous, which helps to improve the luminous effect.
  • the display substrate 100 further includes a light extraction layer 25.
  • the light extraction layer 25 is disposed on the side of the cathode layer 24 away from the substrate 11, the light extraction layer 25 extends from the display area Q 1 to the non-display area Q 2 , and the edge z 3 of the light extraction layer 25 is located in the non-display area Q 2 ,
  • the orthographic projection of at least part of the edge of the light extraction layer 25 on the substrate 11 is within the range of the orthographic projection of the cathode layer 24 on the substrate 11.
  • the light extraction efficiency of the display substrate 100 can be improved through the light extraction layer 25, and it is not easy to increase the area of the packaging layer 27 to achieve effective packaging due to the excessively large area of the light extraction layer 25.
  • the layer 27 can effectively protect the light extraction layer 25 from external moisture, dust and other impurities.
  • the orthographic projection of all edges of the light extraction layer 25 on the substrate 11 is within the range of the orthographic projection of the cathode layer 24 on the substrate 11.
  • the edge of the light extraction layer 25 z 3 M and Q border display area 1 i.e., the display area and the non-display region Q 1 Q 2 interface
  • the spacing between the edge of the cathode layer 12 is 2 and Z the spacing between the display region Q M boundary 1, so that the package need not ensure that the edge of the light extraction layer 27 of the edge layer 25 z 3 pitch in the first direction X, as long as the edge of the encapsulation layer and the cathode layer 24
  • the distance between the edge z 2 in the first direction X can ensure the reliability of the packaging, and therefore it is beneficial to reduce the distance between the edge of the packaging layer 27 and the boundary M of the display area Q 1 , thereby reducing the size of the display substrate 100.
  • the size of the non-display area Q 2 in the first direction X reduces the proportion of the non-display area Q 2 in the entire display substrate, so that the frame of the display device using the display substrate 100 is reduced, and the screen-to-body ratio of the display device is increased .
  • the orthographic projection of a part of the edge of the light extraction layer 25 on the substrate 11 is within the range of the orthographic projection of the cathode layer 24 on the substrate 11. For example, for a rectangular display area, it can be within two lengths. At the border of the side, the orthographic projection of the edge of the light extraction layer 25 on the substrate 11 is within the scope of the orthographic projection of the cathode layer 24 on the substrate 11, which can ensure that a narrow frame is realized in the opposite side direction.
  • the orthographic projection of the edge z 3 of the light extraction layer 25 on the substrate 11 and the orthographic projection of the edge z 2 of the cathode layer 24 on the substrate 11 roughly coincide. This helps reduce the area of the encapsulation layer, reducing the proportion of non-display 2 display region Q of the substrate 100, and the display area 3 can be avoided between the boundary Q M-1 due to light extraction layer 25 to the edge of z The small spacing reduces the light extraction efficiency of the display substrate 100.
  • the orthographic projection of the edge z 3 of the light extraction layer 25 on the substrate 11 and the orthographic projection of the edge z 2 of the cathode layer 24 on the substrate 11 are both located in the portion where the cathode lap layer 17 covers the flat layer body 15 (Ie, the second portion 172) is within the range of the orthographic projection on the substrate 11. In this way, effective electrical contact between the cathode layer 24 and the cathode overlap layer 17 can be ensured, and the light extraction efficiency of the display substrate 100 can be effectively improved through the light extraction layer 25.
  • the material of the light extraction layer 25 includes an organic substance
  • the material of the cathode layer 24 includes an inorganic substance.
  • the actual position of the edge of the corresponding layer in the formed display substrate 100 can be obtained.
  • the foregoing embodiments of the present disclosure define the design position of the edge z 2 of the cathode layer 24 and the design position of the edge z 3 of the light extraction layer 25, so that the proportion of the non-display area Q 2 of the display substrate 100 produced can be reduced. It is small and can ensure the packaging reliability of the display substrate 100 at the same time.
  • the display substrate 100 further includes an anti-reflection layer 26.
  • the anti-reflection layer 26 is disposed on the side of the light extraction layer 25 away from the cathode layer 24, the anti-reflection layer 26 extends from the display area Q 1 to the non-display area Q 2 , and the edge z 4 of the anti-reflection layer 26 is located in the non-display area Q 2 , the orthographic projection of the antireflection layer 26 on the substrate 11 is within the scope of the orthographic projection of the cathode layer 24 on the substrate 11.
  • the anti-reflection layer 26 can be used to enhance the light emission rate, and the large area of the anti-reflection layer 26 will not cause the package to be unreliable, so there is no need to increase the encapsulation layer 27. area to ensure sealing effectiveness, tends to reduce the proportion of non-display region of the display substrate 100 Q 2 share the use of the display frame of the display device substrate 100 is reduced, improving the proportion of the screen of the display device.
  • the edges of the anti-reflection layer 26, the light extraction layer 25, and the cathode layer 24 are farther away from the display area Q 1 than the edge of the pixel definition layer main body 20, so that the brightness of the display area Q 1 can be improved while ensuring the display area Q 1 brightness uniformity.
  • the position of the edge z 4 of the anti-reflection layer 26 mentioned above refers to the design position.
  • the anti-reflection layer 26 is formed by using an open mask (OPM, Open Mask) and is formed by an evaporation process.
  • OPM Open mask
  • the anti-reflection layer can be determined according to the material characteristics of the anti-reflection layer 26 26 The diffusion rate during the evaporation process, and then according to the design position of the antireflection layer 26 and the diffusion rate during the evaporation process, the actual position of the edge z 4 of the antireflection layer 26 in the formed display substrate 100 can be obtained .
  • the above-mentioned embodiments of the present disclosure limit the design position of the edge z 4 of the anti-reflection layer 26, so that the proportion of the non-display area Q 2 of the display substrate 100 produced can be reduced, and at the same time, the packaging of the display substrate 100 can be ensured. Sex.
  • the anti-reflection layer 26 is located between the light extraction layer 25 and the encapsulation layer 27.
  • the anti-reflection layer 26 can make the light that enters the anti-reflection layer 26 through the light extraction layer 25 and reflect multiple times in the anti-reflection layer 26. Then, an interference stack is formed and then emitted to the encapsulation layer 27 and emitted from the encapsulation layer 27. Therefore, the light extraction efficiency of the display substrate 100 can be enhanced.
  • the orthographic projection of the edge z 4 of the antireflection layer 26 on the substrate 11 is within the range of the orthographic projection of the overlapped portion of the cathode layer 24 and the cathode overlap layer 17 on the substrate 11. In this way, the light extraction efficiency of the display area Q 1 of the display substrate 100 can be effectively ensured.
  • the distance between the edge z 4 of the anti-reflection layer 26 and the boundary M of the display area is greater than or equal to 120 ⁇ m.
  • 120 ⁇ m or 130 ⁇ m or 140 ⁇ m or 150 ⁇ m or 160 ⁇ m Such design will help to ensure that the display area 100 of the substrate 1 of the light extraction efficiency Q.
  • the antireflection layer 26 is a lithium fluoride layer.
  • the display substrate 100 further includes a second blocking dam 19.
  • the second barrier dam 19 is disposed on the surface of the cathode lap layer 17 away from the substrate 11, and the second barrier dam 19 and the cathode layer 24, the light extraction layer 25 and the antireflection layer 26 are not in the direction perpendicular to the substrate 11. overlap. That is to say, 24, the edges of the cathode layer 25 and light extraction layer antireflective layer a second barrier 26 are located close to one side of the display area 19 of the dam Q 1 '.
  • the second barrier dam surrounding the display area 19 is provided a full circle Q 1; a second barrier dam 19 and the cathode layer 17 and the overlapping signal lines 13 are overlapped voltage.
  • the material of the second barrier dam 19 includes the material that forms the main body 20 of the pixel definition layer.
  • the second barrier dam 19 may include the second material made of the same layer and the same material as the main body 20 of the pixel definition layer. Blocking the dam layer is beneficial to simplify the manufacturing process of the display substrate.
  • the second barrier dam 19 overlaps the inorganic insulating layer between the source and drain metal layer and the substrate 11, such as a gate insulating layer, a passivation layer, and one or more layers of the interlayer insulating layer.
  • the barrier dam 19 may also overlap with other functional layers such as a gate metal layer (not shown in the figure), an active semiconductor layer (not shown in the figure), etc., to form the required height of the second barrier dam.
  • the arrangement of the second blocking dam 19 can also prevent the organic material in the encapsulation layer from overflowing, thereby ensuring the reliability of the encapsulation.
  • the organic layer in the encapsulation layer can be formed by printing organic material ink. In actual production, a small part of the organic material may overflow the second barrier dam 19, so in some embodiments, the first barrier dam 16 Part of the organic layer in the encapsulation layer is included between the second barrier dam 19 and the second barrier dam 19. For example, the farthest boundary of the organic layer in the encapsulation layer away from the display area does not exceed the area defined by the first barrier dam 16, that is, on the side of the first barrier dam 16 close to the display area.
  • the distance d 4 between the edge z 2 of the cathode layer 24 and the second barrier dam 19 in the first direction X (that is, the edge z 2 of the cathode layer 24 and the second barrier dam 19 The distance between the sides of the dam 19 close to the display area) is greater than or equal to 80 ⁇ m.
  • a cathode layer 24 is not easy to cover the second barrier dam 19, i.e., the actual edge of the cathode layer 24 side of the second barrier dam is still located close to the display region 19 Q 1 ', it is possible that the second The blocking dam 19 is in contact with the packaging layer 27, thereby ensuring packaging reliability.
  • the anti-reflection layer 26 adopts an open mask (OPM, Open Mask) and is formed by an evaporation process
  • OPM Open Mask
  • the anti-reflection layer 26 (for example, a lithium fluoride layer) is deposited on the In the process, the movement stroke is far, that is, the diffusion speed is faster.
  • the distance d 4 in the first direction X between the edge z 2 of the cathode layer 24 and the second barrier dam 19 is greater than or equal to 80 ⁇ m
  • the orthographic projection of the anti-reflection layer 26 on the substrate is The cathode layer 24 is within the range of the orthographic projection on the substrate 11, so that in the formed display substrate 100, the antireflection layer 26 (for example, a lithium fluoride layer) is not easily covered on the second barrier dam 19, and thus it is not easy to cause packaging.
  • barrier layer 27 is separated from the second dam 19, resulting in package leakage, oxidation of the substrate 100 displayed in the display area of the substrate 100 is formed does not emit light Q 1 of the phenomenon of black groups.
  • the distance d 5 between the edge z 4 of the anti-reflection layer 26 and the second barrier dam 19 in the first direction X is greater than or equal to 250 ⁇ m.
  • d 5 is 250 ⁇ m or 260 ⁇ m or 270 ⁇ m or 280 ⁇ m or 290 ⁇ m.
  • the display substrate 100 further includes an encapsulation layer 27, and the encapsulation layer 27 includes a first inorganic barrier layer 271, an organic barrier layer 272, and a second inorganic barrier layer 273.
  • the first inorganic barrier layer 271 is provided on the side of the antireflection layer 26 away from the light extraction layer 25, the first inorganic barrier layer 271 covers the second barrier dam 19;
  • the organic barrier layer 272 is provided on the side of the first inorganic barrier layer 271 On the side away from the antireflection layer 26, the organic barrier layer 272 is located at least within the area enclosed by the second barrier dam 19;
  • the second inorganic barrier layer 273 is disposed on a side of the organic barrier layer 272 away from the first inorganic barrier layer 271 On the side, the second inorganic barrier layer 273 covers the second barrier dam 19.
  • the first inorganic barrier layer 271 and the second inorganic barrier layer 273 have the function of blocking water vapor and oxygen, while the organic barrier layer 272 has a certain degree of flexibility, so that the formed encapsulation layer 27 can make the display substrate 100 achieve a good encapsulation effect.
  • the package leakage is not easy to occur.
  • the second barrier dam 19 in the process of forming the organic barrier layer 272, the second barrier dam 19 can be used to prevent the material forming the organic barrier layer from overflowing beyond the area enclosed by the second barrier dam 19 , So as to help ensure the reliability of the package.
  • the display substrate 100 includes a first barrier dam 16 and a second barrier dam 19 at the same time.
  • There is a gap between the first barrier dam 16 and the second barrier dam 19 for example, a gap between 30 ⁇ m and 50 ⁇ m).
  • the first inorganic barrier layer 271 and the second inorganic barrier layer 273 simultaneously cover the first barrier dam 16 and the second barrier dam 19, which is beneficial to improve the reliability of the package.
  • the material of this part of the organic barrier layer 272 can be more effectively prevented from overflowing to the periphery of the first barrier dam 16.
  • the height of the first barrier dam 16 and the second barrier dam 19 may be the same or different.
  • the surface of the second barrier dam 19 away from the substrate is lower than the surface of the first barrier dam 16 away from the substrate.
  • the first barrier dam 16 can block the material of the organic barrier layer 272. Therefore, it can be understood that the greater the number of barrier dams (ie, the first barrier dam 16 and the second barrier dam 19), the more beneficial it is to prevent the material forming the organic barrier layer 152 from overflowing, and to ensure packaging reliability. However, too many barrier dam, also affect the size of the non-display region of the display substrate 100 along a first direction X Q 2, and increasing the proportion of non-display area occupied by Q 2.
  • only the first barrier dam 16 and the second barrier dam 19 are provided, which can effectively block the material forming the organic barrier layer 152 during the manufacturing process without affecting the display substrate.
  • the width of the non-display area Q 2 of 9 in the first direction X has a greater influence.
  • the material of the first inorganic barrier layer 271 includes one or a combination of one or more of silicon nitride SiNx, silicon dioxide SiOx, and silicon oxynitride SiON.
  • the first inorganic barrier layer 271 is formed by a chemical vapor deposition (CVD, Chemical Vapor Deposition) process.
  • the material of the organic barrier layer 272 includes one or more polymer combinations of acrylic-based polymers, silicon-based polymers, and epoxy-based polymers, and inkjet printing (IJP) is adopted. ) Method to fabricate the above-mentioned materials on the first inorganic barrier layer 271 and perform ultraviolet (UV) curing to form the organic barrier layer 272.
  • the material of the second inorganic barrier layer 273 includes one or a combination of silicon nitride SiNx, silicon dioxide SiOx, and silicon oxynitride SiON.
  • the second inorganic barrier layer 273 is formed by a chemical vapor deposition (CVD, Chemical Vapor Deposition) process.
  • Some embodiments of the present disclosure provide a manufacturing method of a display substrate. Referring to Figs. 2-11 and Fig. 14, the manufacturing method includes:
  • S20 is formed on a first side of the substrate 13 and the voltage of the signal line driving circuit structure 14, voltage signal lines 13 is located in the non-display area surrounding the display area Q 2 and Q 1 is provided, the circuit configuration of the drive 14 is located in the non-display region Q 2, and voltage signal lines located near a side of the display region Q 13.
  • cathode lap layer 17 is located in the non-display area Q 2 and is arranged around the display area Q 1 ; the cathode lap layer 17 Q away from the display region including a first portion 171 and second portion 172 of first portion 171 is connected to a second portion 172 extending in the direction toward the display region Q 1; and at least part of the surface 171 close to the substrate 11 and the voltage of the first portion Corresponding parts of the signal line 13 are in electrical contact; the orthographic projection of the second portion 172 on the substrate 11 and the orthographic projection of the driving circuit structure 14 on the substrate 11 at least partially overlap.
  • cathode layer 24 on the substrate 11 on which the cathode layer lap layer 17 is formed, the cathode layer 24 extends from the display area Q 1 to the non-display area Q 2 , and the edge z 2 of the cathode layer 24 is located in the non-display area Q 2 inside; the cathode layer 24 and the second portion 172 of the cathode lap layer 17 are in electrical contact with at least part of the surface away from the substrate 11.
  • the display substrate formed by the above manufacturing method can reduce the area of the cathode layer 24 while ensuring the electrical connection between the cathode layer 24 and the voltage signal line 13, thereby reducing the area of the packaging layer while ensuring the reliability of the packaging.
  • the size of the non-display area Q 2 of the display substrate 100 in the first direction X is reduced, that is , the proportion of the non-display area Q 2 in the entire display substrate is reduced, which will make the display device using the display substrate 100 more effective
  • the frame can be reduced accordingly, which increases the screen-to-body ratio of the display device.
  • the method further includes:
  • a patterned flat layer is formed on the first side of the substrate 11, and the patterned flat layer includes the flat layer main body 15 and the first barrier layer 161.
  • the flat layer main body 15 extends from the display area Q 1 to the non-display area Q 2 , and the edge of the flat layer main body 15 is located in the non-display area Q 2.
  • the flat layer main body 15 and the voltage signal line 13 are in a direction perpendicular to the substrate 11 There is no overlap, and the flat layer body 15 completely covers the driving circuit structure 14.
  • the film layer on the flat layer main body 15 (for example, the pixel defining layer main body 20, part of the cathode overlap layer 17, and the multiple anodes 18 shown in FIGS. 6 and 7) can be made more flat .
  • the first barrier layer 161 is located on the side of the voltage signal line 13 away from the display area Q 1 , and the first barrier layer 161 constitutes a part of the first barrier dam 16.
  • the method further includes:
  • the patterned pixel definition layer includes a pixel definition layer main body 20, a plurality of fillers 201, a second barrier layer 162, and a third barrier layer.
  • the pixel definition layer main body 20 extends from the display area Q 1 to the non-display area Q 2 , and the edge z 1 of the pixel definition layer main body 20 is located in the non-display area Q 2.
  • the pixel definition layer main body 20 covers the cathode bonding layer 17 near the display area The edge of Q 1 and the part of the surface of the second portion 172 that covers the cathode lap layer 17 away from the substrate 11.
  • the surface of the second portion 172 of the bonding layer 17 away from the substrate 11 is exposed to prevent the main body 20 of the pixel definition layer from influencing the electrical contact between the cathode layer 24 and the cathode bonding layer 17.
  • the cathode layer 24 includes a part covering the main body 20 of the pixel definition layer and a part covering the cathode bonding layer 17, and these two parts are continuous.
  • the body portion of the pixel defining layer 20 located in the display region Q 1 'having a plurality of openings 202, the light emitting region 202 is configured to define a plurality of sub-pixels of a plurality of openings, so that by controlling a plurality of light emitting sub-pixel, a display screen 100 on the display substrate.
  • the cathode lap layer 17 has a plurality of through holes 173 distributed in an array, and at least one through hole 173 of the plurality of through holes 173 penetrates the surface of the cathode lap layer 17 away from the substrate 11 and the cathode.
  • a plurality of fillers 201 are filled into the plurality of through holes 173 one by one.
  • the upper surface of the cathode overlap layer 17 can be flattened, which is convenient for the cathode overlap.
  • Other film layers are fabricated on the layer 17; on the other hand, by fabricating a plurality of fillers 201 and the main body 20 of the pixel definition layer in the same layer, the fabrication process of the display substrate 100 is simplified.
  • the second barrier layer 162 is located on the surface of the first barrier layer 161 away from the substrate 11, that is, the second barrier layer 162 constitutes a part of the first barrier dam 16.
  • the third barrier layer is located on the surface of the cathode lap layer 17 away from the substrate 11, the third barrier layer 17 constitutes the second barrier dam 19, or the second barrier layer constitutes a part of the second barrier dam 19.
  • the display device 200 includes the display substrate 100 described in any of the above embodiments.
  • the display device 200 is an electroluminescent display device, such as liquid crystal panels, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • electroluminescent display device such as liquid crystal panels, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • the non-display area Q 2 of the display substrate 100 occupies a small proportion. Therefore, installing it in the display device can reduce the frame 202 of the display device 200 and increase the screen occupancy of the display device 200.
  • the ratio is the ratio of the area of the display screen 201 to the total surface area of the display side (including the area of the screen 201 and the area of the frame 202) on the display side of the display device 200.

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Abstract

一种显示基板，包括衬底、电压信号线、驱动电路结构、阴极搭接层和阴极层。电压信号线位于非显示区并围绕显示区设置；驱动电路结构位于非显示区，并且位于电压信号线的靠近显示区一侧；阴极搭接层位于非显示区并围绕显示区设置，阴极搭接层的第一部分靠近衬底的至少部分表面与电压信号线的相应部分电接触，阴极搭接层的第二部分在衬底上的正投影与驱动电路结构在衬底上的正投影至少部分重叠；阴极层从显示区延伸到非显示区，并且阴极层的边缘位于非显示区，阴极层与阴极搭接层的第二部分远离衬底的至少部分表面电接触。

Description

显示基板及其制作方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法和显示装置。
背景技术
电致发光显示基板具有主动发光、可视范围广、响应快等优点，被广泛应用于显示装置中。
发明内容
一方面，提供一种显示基板。所述显示基板具有显示区和与显示区邻接的非显示区。所述显示基板包括衬底、设置于衬底的第一侧的电压信号线、设置于衬底的第一侧的驱动电路结构、设置于电压信号线及驱动电路结构的远离衬底的一侧的阴极搭接层、以及设置于衬底的第一侧的阴极层。所述电压信号线位于非显示区并围绕显示区设置。所述驱动电路结构位于非显示区，并且位于电压信号线的靠近显示区一侧。所述阴极搭接层位于非显示区并围绕显示区设置；所述阴极搭接层包括远离显示区的第一部分以及向靠近显示区的方向延伸的第二部分，第一部分与第二部分相连接；第一部分靠近衬底的至少部分表面与电压信号线的相应部分电接触；第二部分在衬底上的正投影与驱动电路结构在衬底上的正投影至少部分重叠。所述阴极层从显示区延伸到非显示区，并且阴极层的边缘位于非显示区，阴极层与阴极搭接层的第二部分远离衬底的至少部分表面电接触。
在一些实施例中，显示基板还包括设置于衬底的第一侧的像素定义层。像素定义层包括位于阴极层的靠近衬底一侧的像素定义层主体，像素定义层主体从显示区延伸到非显示区，像素定义层主体的边缘位于非显示区。像素定义层主体覆盖阴极搭接层的靠近显示区的边缘，并且覆盖阴极搭接层的第二部分远离衬底的部分表面；像素定义层主体的边缘比阴极层的边缘更靠近显示区。像素定义层主***于显示区的部分具有多个开口，多个开口被配置为限定多个子像素的发光区域。
在一些实施例中，显示基板还包括：设置于衬底的第一侧的源漏金属层，电压信号线及驱动电路结构中的源极和漏极位于源漏金属层中；设置于衬底的第一侧的平坦层，平坦层包括设置于源漏金属层、像素定义层主体及阴极搭接层三者之间的平坦层主体，平坦层主体从显示区延伸到非显示区，并且平坦层主体的边缘位于非显示区。平坦层主体完全覆盖驱动电路结构；阴极 搭接层覆盖平坦层主体的远离显示区的边缘，并且覆盖平坦层主体的远离衬底的至少部分表面。
在一些实施例中，阴极搭接层上具有阵列分布的多个通孔，多个通孔中的至少一个通孔贯通阴极搭接层，多个通孔中的至少部分通孔在衬底上的正投影位于平坦层主体在衬底上的正投影的范围之内。显示基板还包括：多个填充物，一一对应地填充于多个通孔内，多个填充物中的至少一个填充物的材料与像素定义层主体的材料相同。
在一些实施例中，显示基板还包括：设置于衬底的第一侧的第一阻挡坝，第一阻挡坝位于非显示区，源漏金属层沿从显示区到非显示区的方向延伸到第一阻挡坝靠近显示区的侧面；阴极搭接层沿从显示区到非显示区的方向延伸到第一阻挡坝靠近显示区的侧面，并且阴极搭接层的与电压信号线电接触的部分位于平坦层主体和第一阻挡坝之间。
在一些实施例中，第一阻挡坝的材料包括形成像素定义层主体的材料和/或形成平坦层主体的材料。
在一些实施例中，显示基板还包括：设置于衬底的第一侧的无机绝缘层，无机绝缘层包括比源漏金属层更靠近衬底的层间介质层；层间介质层从显示区延伸到非显示区，并且层间介质层的边缘位于第一阻挡坝远离显示区的一侧，层间介质层延伸到第一阻挡坝远离显示区一侧的部分形成有至少一个槽，至少一个槽围绕第一阻挡坝设置。
在一些实施例中，显示基板还包括：设置于平坦层主体与像素定义层主体之间、且位于显示区的阳极层，阳极层包括多个阳极，多个阳极与多个开口一一对应；设置于像素定义层主体的远离衬底一侧的至少一层有机功能层，至少一层有机功能层从显示区延伸到非显示区，并且至少一层有机功能层的边缘位于非显示区内，至少一层有机功能层的边缘比像素定义层主体的边缘更靠近显示区。
在一些实施例中，至少一层有机功能层包括电子传输层、电子注入层、空穴传输层或空穴注入层中的至少一种。
在一些实施例中，显示区大致呈矩形，阴极搭接层围绕该矩形的两个长边及一个短边设置。
在一些实施例中，在非显示区的对应于两个长边的区域内，阴极层与阴极搭接层的接触部位在第一方向上的宽度为D 1，D 1大于或等于150μm，且小于或等于350μm；在非显示区的对应于一个短边的区域内，阴极层与阴极搭接层的接触部位在第一方向上的宽度为D 2，D 2小于D 1，且大于零。第一方 向为平行于衬底、且垂直于显示区与非显示区的分界面的方向。
在一些实施例中，显示基板还包括：设置于阴极层的远离衬底一侧的光取出层，光取出层从显示区延伸到非显示区，并且光取出层的边缘位于非显示区，光取出层的至少部分边缘在衬底上的正投影处于阴极层在衬底上的正投影的范围之内。
在一些实施例中，光取出层的边缘在衬底上的正投影与阴极层的边缘在衬底上的正投影大致重合。
在一些实施例中，显示基板还包括：设置于光取出层的远离阴极层一侧的增透层，增透层从显示区延伸到非显示区，并且增透层的边缘位于非显示区，增透层在衬底上的正投影处于阴极层在衬底上的正投影的范围之内。
在一些实施例中，增透层包括氟化锂层。
在一些实施例中，显示基板还包括：设置于阴极搭接层的远离衬底的表面上的第二阻挡坝，第二阻挡坝与阴极层、光取出层及增透层在垂直于衬底的方向上无交叠。
在一些实施例中，阴极层的边缘与第二阻挡坝在第一方向上的间距大于或等于80μm；增透层的边缘与第二阻挡坝在第一方向上的间距大于或等于250μm；第一方向为平行于衬底、且垂直于显示区与非显示区的分界面的方向。
在一些实施例中，显示基板还包括封装层，封装层包括：设置于增透层的远离光取出层一侧的第一无机阻隔层，第一无机阻隔层覆盖第二阻挡坝；设置于第一无机阻隔层的远离增透层一侧的有机阻隔层，有机阻隔层至少位于第二阻挡坝围设出的区域之内；以及，设置于有机阻隔层的远离第一无机阻隔层一侧的第二无机阻隔层，第二无机阻隔层覆盖第二阻挡坝。
另一方面，提供一种显示基板的制作方法。显示基板包括显示区和与显示区邻接的非显示区。制作方法包括：提供衬底；在衬底的第一侧形成电压信号线和驱动电路结构，电压信号线位于非显示区并围绕显示区设置，驱动电路结构位于非显示区、并且位于电压信号线的靠近显示区一侧；在形成有电压信号线和驱动电路结构的衬底上形成阴极搭接层，阴极搭接层位于非显示区并围绕显示区设置；阴极搭接层包括远离显示区的第一部分以及向靠近显示区的方向延伸的第二部分，第一部分与第二部分相连接；第一部分靠近衬底的至少部分表面与电压信号线的相应部分电接触；第二部分在衬底上的正投影与驱动电路结构在衬底上的正投影至少部分重叠；在形成有阴极层搭接层的衬底上形成阴极层，阴极层从显示区延伸到非显示区，并且阴极层的 边缘位于非显示区内；阴极层与阴极搭接层的第二部分远离衬底的至少部分表面电接触。
在一些实施例中，所述在形成有电压信号线和驱动电路结构的衬底上形成阴极搭接层的步骤之前还包括：在衬底的第一侧形成图案化的平坦层，图案化的平坦层包括平坦层主体和第一阻挡层。所述平坦层主体从显示区延伸到非显示区，并且平坦层主体的边缘位于非显示区内，平坦层主体与电压信号线在垂直于衬底的方向上无交叠。所述第一阻挡层位于电压信号线的远离显示区的一侧。
在一些实施例中，所述在形成有阴极层搭接层的衬底上形成阴极层的步骤之前，还包括：在衬底的第一侧形成图案化的像素定义层，图案化的像素定义层包括像素定义层主体、多个填充物、第二阻挡层和第三阻挡层。所述像素定义层主体从显示区延伸到非显示区，像素定义层主体的边缘位于非显示区内；像素定义层主体覆盖阴极搭接层的靠近显示区的边缘，并且覆盖阴极搭接层的第二部分远离衬底的部分表面；像素定义层主体的边缘比阴极层的边缘更靠近显示区；像素定义层主***于显示区的部分具有多个开口，多个开口被配置为限定多个子像素的发光区域。所述阴极搭接层上具有阵列分布的多个通孔，多个通孔中的至少一个通孔贯穿阴极搭接层的远离衬底的表面和阴极搭接层的靠近衬底的表面；多个填充物一一对应地填充至多个通孔中。所述第二阻挡层位于阴极搭接层及电压信号线的远离显示区的一侧。所述第三阻挡层位于阴极搭接层的远离衬底的表面上，第二阻挡坝与阴极层、光取出层及增透层在垂直于衬底的方向上无交叠。
再一方面，提供一种显示装置，所述显示装置包括如上述任一实施例所述的显示基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程的限制。
图1为根据本公开的一些实施例提供一种显示基板的俯视图；
图2为图1中显示基板沿AA向的局部结构的剖视图；
图3～图13为根据本公开一些实施例提供的显示基板制作过程中各步骤 对应的俯视图；
图14为根据本公开一些实施例提供的一种显示基板的制作方法的流程图；
图15为根据本公开一些实施例提供的另一种显示基板的制作方法的流程图；
图16为根据本公开一些实施例提供的一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
显示基板具有显示区和非显示区。显示区设置有多个子像素，各子像素至少包括依次叠加设置的像素电路结构、阳极、发光部和阴极，通过阳极和阴极向发光部施加驱动电压，可以使发光部在驱动电压的作用下发光，通过多个子像素的发光部发光可以实现画面显示。非显示区与显示区邻接，并且非显示区围绕显示区一整圈，非显示区内设置有电压信号线和阴极搭接层，电压信号线与阴极搭接层的下表面电接触。
多个子像素的阴极构成阴极层(阴极层是一整层，或者阴极层在显示区的部分有图案)，阴极层从显示区延伸至非显示区并搭接在阴极搭接层的上表面上，从而可以使阴极层的多个阴极与电压信号线电连接。
目前，如何减小显示装置的边框，提高显示装置的屏占比(即显示装置显示侧的屏幕面积占该显示侧表面的总面积的比例，其中显示侧表面的总面积包括屏幕面积和边框面积)，是领域内研究的趋势之一。本公开的发明人经研究发现：上述显示基板中，为了保证阴极层与阴极搭接层良好接触，将阴极层延伸至阴极搭接层上方并使其覆盖阴极搭接层的全部上表面，这样导致阴极层的面积较大。这种情况下，显示基板的封装层的面积必须设置的更大，才能保证封装可靠性。然而，这将导致显示基板的非显示区占整个显示基板的比例增大，从而会导致采用该显示基板的显示装置的边框也相应的增大，屏占比降低。
参见图1和图2，本公开一些实施例提供一种显示基板100。显示基板100具有显示区Q 1，和与显示区邻接的非显示区Q 2，非显示区Q 2围绕显示区Q 1设置一圈。显示基板100包括：衬底11、电压信号线13、驱动电路结构14、阴极搭接层17和阴极层24。
电压信号线13设置于衬底11的第一侧，电压信号线13位于非显示区Q 2，并且围绕显示区Q 1设置。比如图3示出的显示基板100中，显示区Q 1大致呈矩形，电压信号线13围绕显示区Q 1的两个长边和一个短边设置，并且沿另一个短边延伸部分距离后向远离显示区Q 1的方向引出。
驱动电路结构14设置于衬底11的第一侧，驱动电路结构14位于非显示区Q 2，并且位于电压信号线13的靠近显示区Q 1一侧。示例性地，如图3所示，在显示区Q 1的周围设置有一圈驱动电路结构14。其中，需要说明的是，驱动电路结构14配置为驱动如上所述各子像素中的像素电路结构，以使各子像素中的发光部发光。驱动电路结构14包括GOA(Gate Driver On Array，阵列基板行驱动)电路，比如包括EM GOA和Gate GOA两组GOA，其中，EM GOA输出EM(发光)信号，Gate GOA输出Gate信号。
阴极搭接层17设置于衬底11的第一侧，并且阴极搭接层17设置于电压信号线13及驱动电路结构14的远离衬底11的一侧，阴极搭接层17位于非显示区Q 2并围绕显示区Q 1设置。需要说明的是，阴极搭接层17可以是完整的围绕显示区Q 1设置一圈，也可以是围绕显示区的部分边设置。比如图5示出的显示基板100中，显示区Q 1大致呈矩形，阴极搭接层17围绕显示区Q 1的两个长边和一个短边设置。可以理解，在另一些示例中，阴极搭接层17也可以仅围绕显示区Q 1的两个长边设置。
参见图2，阴极搭接层17包括远离显示区Q 1的第一部分171以及向靠近显示区Q 1的方向延伸的第二部分172，第一部分171与第二部分172相连接。第一部分171靠近衬底11的至少部分表面与电压信号线13的相应部分电接触，例如电压信号线13搭接于第一部分171的靠近衬底11的至少部分表面上以实现电连接；第二部分172在衬底11上的正投影与驱动电路结构14在衬底11上的正投影至少部分重叠。这样设计，使阴极搭接层17的第二部分172更靠近显示区Q 1，从而便于将其与阴极层24电连接以减小阴极层的面积。示例性地，阴极搭接层17与显示基板100显示区Q 1内的阳极层(如图6和图7示出的多个阳极18构成的阳极层)同层同材料制作，这样有利于简化显示基板100的制作工艺。示例性地，阴极搭接层17的材料包括金属或导电金属氧化物中的至少一种。
参见图2和图11，阴极层24设置于衬底11的第一侧，阴极层24从显示区Q 1延伸到非显示区Q 2，并且阴极层24的边缘z 2位于非显示区Q 2内。阴极层24与阴极搭接层17的第二部分172远离衬底11的至少部分表面电接触，例如阴极层24搭接于第二部分172的远离衬底的至少部分表面上以实现电连 接。这样设计，可以在保证阴极层24与电压信号线13电连接的同时，减小阴极层24的面积，进而可以在保证封装可靠性的同时相应的减小封装层27的面积，使显示基板100的非显示区Q 2在第一方向X上的尺寸减小，也即减小非显示区Q 2占整个显示基板的比例，这将使得采用该显示基板100的显示装置的边框可以相应的减小，提高了显示装置的屏占比。其中，第一方向X平行于衬底11、且垂直于显示区Q 1与非显示区Q 2的分界面(也即显示区Q 1的边界面M)。示例性地，阴极层24的材料包括但不限于银、镁、镱中的一种或多种的组合。
在上述显示区Q 1大致呈矩形，阴极搭接层17围绕该矩形的两个长边及一个短边设置的情况下，示例性地，在非显示区Q 2的对应于两个长边的区域内，阴极层24与阴极搭接层17的接触部位在第一方向X上的宽度为D 1，参见图2，D 1大于或等于150μm，且小于或等于350μm；在非显示区Q 2的对应于所述一个短边的区域内，阴极层24与阴极搭接层17的接触部位在第一方向X上的宽度为D 2，D 2小于D 1，且大于零。这样设计，一方面可以保证两者的接触面积，减小接触电阻，从而可以保证显示基板100的长程均一性(LRU，Long Reach Uniformity)，即，可以使显示基板100的显示区Q 1内各位置处亮度均匀显示；另一方面有利于减小显示基板100的非显示区Q 2沿第一方向X的宽度。在一些示例中，D 1的范围为150μm～250μm，例如，150μm、180μm、200μm、210μm、230μm或250μm。在另一些示例中，D 1的范围为250μm～350μm，例如，260μm、280μm、300μm、310μm、330μm或350μm。
示例性地，电压信号线13沿第一方向X的宽度为150μm～250μm。因此，在非显示区Q 2的对应于两个长边的区域内，为了使阴极搭接层满足电接触要求，阴极搭接层沿第一方向X的宽度应大于或等于300μm(包括其与阴极层24电接触的150μm和其与电压信号线电接触的150μm)。
参见图2，显示基板100的非显示区Q 2沿第一方向X的宽度为L，L＝L 1+L 2，其中，L 2是为了满足封装可靠性而保留的尺寸；L 1＝d 1+d 2+D 1+d 4。因此，在D 1＝150μm，的情况下，L 1的值较小。此时既可以保证显示基板100的长程均一性、封装可靠性，又有利于减小显示基板100的非显示区Q 2沿第一方向X的宽度L，从而使非显示区Q 2所占的比例减小，使采用该显示基板100的显示装置的边框减小，屏占比提高。
在一些实施例中，参见图2和图7，显示基板100还包括像素定义层。像素定义层设置于衬底11的第一侧，像素定义层包括位于阴极层24的靠近所 述衬底11一侧的像素定义层主体20，像素定义层主体20从显示区Q 1延伸到非显示区Q 2。从显示区Q 1的边界延伸到非显示区Q 2部分的像素定义层主体20可以是与显示区类似的形成开口的网状结构，也可以是不设置开口的整层结构，显示区Q 1的像素定义层主体和从显示区Q 1的边界延伸到非显示区Q 2的像素定义层主体是一体的。像素定义层主体20的边缘z 1位于非显示区Q 2。
像素定义层主体20覆盖阴极搭接层17的靠近显示区Q 1的边缘，并且覆盖阴极搭接层17的第二部分172远离衬底11的部分表面。像素定义层主体20的边缘z 1比阴极层24的边缘z 2更靠近显示区Q 1，这样一方面可以通过像素定义层主体20限定阴极搭接层17的位置；另一方面可以使阴极搭接层17第二部分172的远离衬底11的部分表面露出，避免像素定义层主体20影响阴极层24与阴极搭接层17电接触。此时，阴极层24包括覆盖像素定义层主体20的部分和覆盖阴极搭接层17的部分，且这两部分是连续的。
像素定义层主体20位于显示区Q 1的部分具有多个开口202，多个开口202被配置为限定多个子像素的发光区域，因此像素定义层主体20在显示区Q 1内大致呈网状结构。这样可以通过控制多个子像素发光，使显示基板100显示画面。此处，需要说明的是，像素定义层主体20位于非显示区Q 2的部分也可以具有开口，这些位于非显示区Q 2的开口可以作为dummy像素，以保证显示区Q 1内子像素的可靠性或者平衡各行或各列的负载。用以提高显示区Q 1边沿的显示亮度。
在一些实施例中，显示基板100还包括源漏金属层和平坦层。参见图2，源漏金属层设置于衬底11的第一侧，电压信号线13及驱动电路结构14中的源极和漏极均位于源漏金属层中。通过将电压信号线13及驱动电路结构14中的源极和漏极同层设置，简化了显示基板100的结构，使显示基板100更加容易制作。此处，需要说明的是，源漏金属层是图案化的，虽然电压信号线13与驱动电路结构14中的源极和漏极均位于源漏金属层中，但电压信号线13与驱动电路结构14中的源极和漏极之间具有间隙，也即，电压信号线13与驱动电路结构14中的源极和漏极之间是断开的，并没有电接触。示例性地，显示基板100的显示区Q 1中各子像素包括像素电路结构，像素电路结构中的源极和漏极也设置于该源漏金属层中。
参见图2和图4，平坦层包括设置于源漏金属层、像素定义层主体20及阴极搭接层17三者之间的平坦层主体15，平坦层主体15从显示区Q 1延伸到非显示区Q 2，并且平坦层主体15的边缘位于非显示区Q 2。平坦层主体15完全覆盖驱动电路结构。阴极搭接层17覆盖平坦层主体15的远离显示区Q 1的 边缘，并且覆盖平坦层主体15的远离衬底11的至少部分表面。通过设置平坦层主体15，可以使位于平坦层主体15上的膜层(例如像素定义层主体20、部分阴极搭接层17、以及图6和图7中示出的多个阳极18)更加平整。
在一些实施例中，参见图2、图5和图6，阴极搭接层17上具有阵列分布的多个通孔173，多个通孔173中的至少一个通孔173贯通阴极搭接层17。多个通孔173中的至少部分通孔173在衬底11上的正投影位于平坦层主体15在衬底11上的正投影的范围之内。这样可以在制作显示基板100的过程中，释放阴极搭接层17下方膜层(比如平坦层主体15)中产生的气体，提高了显示基板的可靠性。
在此基础上，参加图2和图7，示例性地，显示基板100还包括多个填充物201。多个填充物201一一对应地填充于多个通孔173内，多个填充物201中的至少一个填充物201的材料与像素定义层主体20的材料相同。这样，一方面可以使阴极搭接层17的上表面平整，便于在阴极搭接层17上制作其它膜层；另一方面可以将多个填充物201与像素定义层20同层制作，具有便于制作的优点。此处，需要说明的是，阴极层24与阴极搭接层17搭接时，实际电连接的区域是网格状的，中间填充有填充物的通孔173是不导电的。
示例性地，通孔173为方形孔或圆形孔或其它不规则形状的孔。
在一些实施例中，参见图2，显示基板100还包括第一阻挡坝16。第一阻挡坝16设置于衬底11的第一侧，且第一阻挡坝16位于非显示区Q 2。源漏金属层(即图2中包括电压信号线13及驱动电路结构14中的源极和漏极的源漏金属层)沿从显示区Q 1到非显示区Q 2的方向(也即第一方向X)延伸到第一阻挡坝16靠近显示区Q 1的侧面。
阴极搭接层17沿从显示区Q 1到非显示区Q 2的方向(也即第一方向X)延伸到第一阻挡坝16靠近显示区Q 1的侧面，并且阴极搭接层17的与电压信号线13电接触的部分(比如第一部分171)位于平坦层主体15和第一阻挡坝16之间。
本实施例中，可以通过第一阻挡坝16来限定源漏金属层中电压信号线13及阴极搭接层17的制作位置，从而达到简化显示基板制作工艺的目的。需要说明的是，第一阻挡坝16呈环状且围绕显示区Q 1设置一圈。在实际制作中，第一阻挡坝16呈正梯形(即其靠近衬底11的表面面积大于其远离衬底11的表面面积)，因此第一阻挡坝16靠近显示区Q 1的侧面为斜面。这样，在制作完源漏金属层和阴极搭接层17后，源漏金属层和阴极搭接层17可能会与第一阻挡坝16存在部分交叠。
在一些实施例中，第一阻挡坝16的材料包括形成像素定义层主体20的材料和/或形成平坦层主体15的材料。示例性地，如图2、图4～图13所示，第一阻挡坝16包括与平坦层主体15同材料且同层制作的第一阻挡层161，以及与像素定义层主体20同材料且同层制作的第二阻挡层162，第一阻挡层161与第二阻挡层162依次叠加形成第一阻挡坝16。
需要说明的是，第一阻挡坝16也可以仅包括第一阻挡层161和第二阻挡层162中的一者，比如，第一阻挡坝16仅包括上述第一阻挡层161；或者，第一阻挡坝16仅包括上述第二阻挡层162。而且在另一些示例中，第一阻挡坝16可以包括三个或更多个阻挡层，即第一阻挡坝16除包括上述第一阻挡层161和第二阻挡层162以外，还可以包括与图2中层间介质层12、栅绝缘层(未示出)、钝化层等无机绝缘层中的一层或多层同材料制作的阻挡层，第一阻挡坝16也可以与栅金属层(图中未示出)、有源半导体层(图中未示出)等其他功能层有交叠，以形成第一阻挡坝需要的高度。
该阻挡层位于第一阻挡层161与衬底11之间。
第一阻挡坝16所包括的至少部分阻挡层为有机材料，在制作第一阻挡坝16时，可以包括烘烤工艺，例如，在制作完第一阻挡层161和第二阻挡层162后，由于烘烤工艺使得第一阻挡层161和第二阻挡层162形成呈一体结构。
在一些实施例中，如图2所示，显示基板100还包括设置于衬底11的第一侧的无机绝缘层，该无机绝缘层包括比源漏金属层更靠近衬底11的层间介质层12、栅绝缘层(未示出)、钝化层(未示出)等。在一些实施例中，显示基板100还包括设置于衬底11的第一侧的栅金属层、有源半导体层等。
层间介质层12从显示区Q 1延伸到非显示区Q 2，并且层间介质层12的边缘位于第一阻挡坝16远离显示区Q 1的一侧，层间介质层12延伸到第一阻挡坝16远离显示区Q 1一侧的部分形成有至少一个槽121，所述至少一个槽121围绕第一阻挡坝16设置。这样在制作显示基板100的过程中，可以通过至少一个槽121阻挡无机绝缘层(包括层间介质层12)上的裂纹向内扩展影响到显示区，从而可以提高显示基板100的可靠性。
示例性地，显示基板100为电致发光显示基板。
在一些实施例中，如图6和图7所示，显示基板100还包括：设置于平坦层主体15与所述像素定义层主体20之间、且位于显示区Q 1的阳极层，该阳极层包括多个阳极18，多个阳极18与多个开口202一一对应。
在一些实施例中，如图2、图8～图10所示，显示基板100还包括设置于所述像素定义层主体20的远离衬底11一侧的至少一层有机功能层，所述至 少一层有机功能层从显示区Q 1延伸到非显示区Q 2，并且所述至少一层有机功能层的边缘位于所述非显示区Q 2内，所述至少一层有机功能层的边缘比所述像素定义层主体20的边缘z 1更靠近所述显示区Q 1。
示例性地，如图2所示，所述至少一层有机功能层的边缘与显示区Q 1之间的间距d 1大于或等于100μm，比如，d 1为100μm或110μm或120μm或130μm或150μm；所述至少一层有机功能层的边缘与像素定义层主体20的边缘z 1之间的间距d 2大于或等于50μm，比如d 2为50μm或60μm或70μm或80μm或100μm。由于L 1＝d 1+d 2+D 1+d 4，因此在d 1＝100μm，d 2＝50μm的情况下，L 1的值较小，从而减小了显示基板100的非显示区Q 2沿第一方向X的宽度L，使非显示区Q 2所占的比例减小，也使采用该显示基板100的显示装置的边框减小，屏占比提高。
示例性地，所述至少一层有机功能层包括电子传输层23、电子注入层、有机发光层22、空穴传输层21或空穴注入层中的至少一种。通过设置电子传输层23、电子注入层、空穴传输层21和空穴注入层，可以使载流子均匀地注入至有机发光层22，提高了显示基板100的发光效率。
需要说明的是，电子传输层23、电子注入层、空穴传输层21和空穴注入层中的至少一层可以为通过利用开放式掩膜板(OPM，Open Mask)制作的膜层，因为边缘shadow效应，边界膜层较薄，但在所形成的显示基板100中，这几个膜层的最外边缘位置是比像素定义层主体20的边缘更靠近显示区Q 1的。
示例性地，有机发光层22可以采用精细金属掩膜板(FMM，Fine Metal Mask)通过蒸镀工艺形成，高精度金属掩膜板上留有预先设计好的有效开口区域，通过该有效开口区域使形成有机发光层材料可以沉积到像素定义层主体20上对应的开口202处，从而形成有机发光层22的多个发光部221。
示例性地，如图8所示，多个发光部221中的至少一个发光部221在衬底11上的正投影的面积大于与其对应的像素定义层主体的开口的面积(此时通过设计精细金属掩膜板上的有效开口区域的面积大于像素定义层主体上对应的开口的面积，即可使所形成的发光部221在衬底11上的正投影的面积大于与其对应的像素定义层主体的开口的面积)。多个发光部221所在的最小图形区域(比如矩形区域)的边缘(也即整个有机发光层22的外边缘)比像素定义层主体20的边缘更靠近显示区Q 1。这样设计，不容易影响其它膜层的制作，比如发光部221不会形成在阴极搭接层17上，从而不会对阴极层24与阴极搭接层17的接触效果造成影响。此外，由于所形成的发光部221在衬 底11上的正投影的面积大于与其对应的像素定义层主体的开口的面积，还可以使像素定义层主体的各开口限定的子像素的发光区域均匀发光，有利于提高发光效果。
在一些实施例中，参见图2和图12，显示基板100还包括光取出层25。光取出层25设置于阴极层24的远离衬底11的一侧，光取出层25从显示区Q 1延伸到非显示区Q 2，并且光取出层25的边缘z 3位于非显示区Q 2，光取出层25的至少部分边缘在衬底11上的正投影处于阴极层24在衬底11上的正投影的范围之内。这样设计，既可以通过光取出层25提高显示基板100的出光效率，又不容易因光取出层25的面积过大，而导致需要大幅增大封装层27的面积才能实现有效的封装，使封装层27可以有效保护光取出层25不受外部水汽和灰尘等杂质侵蚀。
示例性地，光取出层25的全部边缘在衬底11上的正投影处于阴极层24在衬底11上的正投影的范围之内。此时，光取出层25的边缘z 3与显示区Q 1的边界M(即显示区Q 1与非显示区Q 2的分界面)之间的间距小于或等于阴极层12的边缘z 2与显示区Q 1的边界M之间的间距，这样，无需保证封装层27的边缘与光取出层25的边缘z 3在第一方向X上的间距，只要保证封装层的边缘与阴极层24的边缘z 2在第一方向X上的间距，即可保证封装可靠性，因此有利于减小封装层27的边缘与显示区Q 1的边界M之间的间距，从而能够减小显示基板100的非显示区Q 2在第一方向X上的尺寸，减小非显示区Q 2占显示基板整体的比例，使采用该显示基板100的显示装置的边框减小，提高了显示装置的屏占比。在一些实施例中，光取出层25的部分边缘在衬底11上的正投影处于阴极层24在衬底11上的正投影的范围之内，例如对于矩形的显示区域，可以在两个长边的边界处，光取出层25的边缘在衬底11上的正投影处于阴极层24在衬底11上的正投影的范围之内，可以保证在该对边方向上实现窄边框。
示例性地，如图2和图12所示，光取出层25的边缘z 3在衬底11上的正投影与阴极层24的边缘z 2在衬底11上的正投影大致重合。这样既有利于减小封装层的面积，减小显示基板100的非显示区Q 2所占的比例，又可以避免因光取出层25的边缘z 3与显示区Q 1的边界M之间的间距较小而降低显示基板100的出光效率。
示例性地，光取出层25的边缘z 3在衬底11上的正投影和阴极层24的边缘z 2在衬底11上的正投影均位于阴极搭接层17覆盖平坦层主体15的部分(即第二部分172)在衬底11上的正投影的范围之内。这样既可以保证阴极 层24与阴极搭接层17有效的电接触，又可以通过光取出层25有效的提高显示基板100的出光效率。
示例性地，光取出层25的材料包括有机物，阴极层24的材料包括无机物。这样设计，可以改善光取出层25与阴极层24的粘附性，从而能够减小膜层之间的应力，提高封装可靠性。
需要说明的是，本公开一些实施例中所述的光取出层25的边缘z 3的位置、阴极层24的边缘z 2的位置均指的是设计位置。示例性地，阴极层24和光取出层25均利用开放式掩膜板(OPM，Open Mask)且通过蒸镀工艺形成，在制作该显示基板100的过程中，可以根据阴极层24的材料特性确定阴极层24在蒸镀过程中的扩散速度，根据光取出层25的材料特性确定光取出层25在蒸镀过程中的扩散速度。然后，根据各层的设计位置及其在蒸镀过程中的扩散速度，可以得到所形成的显示基板100中对应层的边缘的实际位置。本公开上述实施例通过限定阴极层24的边缘z 2的设计位置、光取出层25的边缘z 3的设计位置，可以使所制作出的显示基板100的非显示区Q 2所占的比例减小，同时能够保证显示基板100的封装可靠性。
在一些实施例中，如图2和图13所示，显示基板100还包括增透层26。增透层26设置于光取出层25的远离阴极层24的一侧，增透层26从显示区Q 1延伸到非显示区Q 2，并且增透层26的边缘z 4位于非显示区Q 2，增透层26在衬底11上的正投影处于阴极层24在衬底11上的正投影的范围之内。
这样设计，使得增透层26的边缘z 4在第一方向X上位于阴极层24的边缘z 2与显示区Q 1之间，减小了增透层26的边缘z 4与显示区Q 1的边界M之间的距离，此时，既可以利用增透层26增强光的出射率，又不会因增透层26面积较大而导致封装不可靠，从而不需要通过增大封装层27的面积来保证封装效果，有利于减小显示基板100的非显示区Q 2所占的比例，使采用该显示基板100的显示装置的边框减小，提高了显示装置的屏占比。
示例性地，增透层26、光取出层25和阴极层24的边缘比像素定义层主体20的边缘更远离显示区Q 1，这样可以在提高显示区Q 1亮度的同时，保证显示区Q 1的亮度均匀性。
需要说明的是，上述增透层26的边缘z 4的位置指的是设计位置。示例性地，增透层26利用开放式掩膜板(OPM，Open Mask)且通过蒸镀工艺形成，在制作该显示基板100的过程中，可以根据增透层26的材料特性确定增透层26在蒸镀过程中的扩散速度，然后根据增透层26的设计位置及其在蒸镀过程中的扩散速度，可以得到所形成的显示基板100中增透层26的边缘z 4的实际 位置。本公开上述实施例通过限定增透层26的边缘z 4的设计位置，可以使所制作出的显示基板100的非显示区Q 2所占的比例减小，同时能够保证显示基板100的封装可靠性。
参见图2，增透层26位于光取出层25和封装层27之间，增透层26可以使经光取出层25射入增透层26的光线，在增透层26内多次反射，然后形成干涉叠加后射向封装层27，从封装层27射出。因此可以增强显示基板100的出光效率。示例性地，增透层26的边缘z 4在衬底11上的正投影位于阴极层24与阴极搭接层17搭接的部分在衬底11上的正投影的范围之内。这样可以有效保证显示基板100的显示区Q 1的出光效率。
示例性地，增透层26的边缘z 4与显示区的边界M之间的间距大于或等于120μm。例如，120μm或130μm或140μm或150μm或160μm。这样设计，有利于保证显示基板100的显示区Q 1的出光效率。
示例性地，增透层26为氟化锂层。
在一些实施例中，参见图2、图7～图13，显示基板100还包括第二阻挡坝19。第二阻挡坝19设置于阴极搭接层17的远离衬底11的表面上，第二阻挡坝19与阴极层24、光取出层25及增透层26在垂直于衬底11的方向上无交叠。也就是说，阴极层24、光取出层25及增透层26的边缘均位于第二阻挡坝19的靠近显示区Q 1的一侧。示例性地，第二阻挡坝19围绕显示区Q 1设置一整圈；第二阻挡坝19与阴极搭接层17和电压信号线13均有交叠。
示例性地，如图2所示，第二阻挡坝19的材料包括形成像素定义层主体20的材料，例如，第二阻挡坝19可以包括与像素定义层主体20同层同材料制作的第二阻挡坝子层，这样有利于简化显示基板的制作工艺。例如，第二阻挡坝19与位于源漏金属层和衬底11之间的无机绝缘层，例如栅绝缘层、钝化层，层间绝缘层中的一层或多层有交叠，第二阻挡坝19也可以与栅金属层(图中未示出)、有源半导体层(图中未示出)等其他功能层有交叠，以形成第二阻挡坝需要的高度。
第二阻挡坝19的设置，还可以阻挡封装层中的有机材料溢出，从而保证封装可靠性。需要说明的是，封装层中的有机层可以通过打印有机材料墨水形成，在实际制作中，可能有少部分有机材料溢出第二阻挡坝19，所以在一些实施例中，在第一阻挡坝16和第二阻挡坝19之间包括部分封装层中的有机层的材料。例如，封装层中的有机层的远离显示区的最远的边界不超出第一阻挡坝16限定的区域，即在第一阻挡坝16靠近显示区的一侧。
在一些实施例中，参见图2和图12，阴极层24的边缘z 2与第二阻挡坝19在第一方向X上的间距d 4(也即阴极层24的边缘z 2与第二阻挡坝19的靠近显示区的侧面之间的距离)大于或等于80μm。这样，在形成显示基板100后，阴极层24不易覆盖到第二阻挡坝19，即阴极层24的实际边缘仍位于第二阻挡坝19的靠近显示区Q 1的一侧，因而可以使第二阻挡坝19与封装层27相接触，从而保证封装可靠性。示例性地，d 4为80μm或90μm或100μm或110μm或120μm。由于L 1＝d 1+d 2+D 1+d 4，因此在d 4＝80μm的情况下，L 1的值较小。如上所述，d 1最小值为100μm，d 2最小值为50μm，D 1最小值为150μm，因此L 1最小值为380μm。这样，有利于减小显示基板100的非显示区Q 2沿第一方向X的宽度L，从而使非显示区Q 2所占的比例减小，使采用该显示基板100的显示装置的边框减小，屏占比提高。
此处，需要说明的是，在增透层26采用开放式掩膜板(OPM，Open Mask)且通过蒸镀工艺形成的情况下，增透层26(例如氟化锂层)在蒸镀的过程中运动行程较远，即扩散速度较快。本公开上述一些实施例中，通过阴极层24的边缘z 2与第二阻挡坝19在第一方向X上的间距d 4大于或等于80μm，且增透层26在衬底上的正投影处于阴极层24在衬底11上的正投影的范围之内，使所形成的显示基板100中，增透层26(例如氟化锂层)不易覆盖到第二阻挡坝19上，因而不易导致封装层27与第二阻挡坝19分离，造成封装漏气，显示基板100氧化，在显示基板100的显示区Q 1形成不发光黑团的现象。
在此基础上，示例性地，如图2和图13所示，增透层26的边缘z 4与所述第二阻挡坝19在第一方向X上的间距d 5(也即增透层26的边缘z 4与第二阻挡坝19的靠近显示区的侧面之间的距离)大于或等于250μm。这样可以更有效的避免增透层26蒸镀到第二阻挡坝19上，从而保证封装效果。示例性地，d 5为250μm或260μm或270μm或280μm或290μm。
在一些实施例中，参见图1和图2，显示基板100还包括封装层27，封装层27包括第一无机阻隔层271、有机阻隔层272和第二无机阻隔层273。其中，第一无机阻隔层271设置于增透层26的远离光取出层25的一侧，第一无机阻隔层271覆盖第二阻挡坝19；有机阻隔层272设置于第一无机阻隔层271的远离增透层26的一侧，有机阻隔层272至少位于第二阻挡坝19围设出的区域之内；第二无机阻隔层273设置于有机阻隔层272的远离第一无机阻隔层271的一侧，第二无机阻隔层273覆盖第二阻挡坝19。
第一无机阻隔层271和第二无机阻隔层273具有阻隔水汽和氧气的作用，而有机阻隔层272具有一定的柔性，从而使所形成的封装层27可以使显示基 板100达到良好的封装效果，不易出现封装漏气现象。此外，通过设置第二阻挡坝19，可以在形成有机阻隔层272的过程中，利用第二阻挡坝19阻挡形成有机阻隔层的材料溢流至第二阻挡坝19所围设出的区域之外，从而有利于保证封装可靠性。
示例性地，显示基板100同时包括第一阻挡坝16和第二阻挡坝19，第一阻挡坝16和第二阻挡坝19之间具有间隙(比如具有30μm～50μm的间隙)，封装层27中的第一无机阻隔层271第二无机阻隔层273同时覆盖第一阻挡坝16和第二阻挡坝19，这样有利于提高封装可靠性。其中，由于工艺的原因，在第一阻挡坝16和第二阻挡坝19之间也有可能存在部分有机阻隔层272的材料。此时通过在第二阻挡坝19的***设置一圈第一阻挡坝16，能够更有效的阻止这部分有机阻隔层272的材料溢出至第一阻挡坝16的***。示例性地，第一阻挡坝16和第二阻挡坝19高度可以相同，也可以不同，例如第二阻挡坝19远离基板的表面低于第一阻挡坝16远离基板的表面。
需要说明的是，由于在有机阻隔层272的材料溢流至第二阻挡坝19所围设出的区域外之后，第一阻挡坝16可以阻挡有机阻隔层272的材料。因此，可以理解，阻挡坝(即第一阻挡坝16和第二阻挡坝19)的数量越多，越有利于阻挡形成有机阻隔层152的材料溢流，保证封装可靠性。但是，阻挡坝的数量太多，也会影响显示基板100的非显示区Q 2沿第一方向X的尺寸，增大非显示区Q 2所占的比例。因而，本公开一些实施例中，仅设置第一阻挡坝16和第二阻挡坝19，这样既能在制作过程中对形成有机阻隔层152的材料产生有效的阻挡作用，又不会对显示基板9的非显示区Q 2沿第一方向X的宽度产生较大影响。
示例性地，第一无机阻隔层271的材料包括氮化硅SiNx、二氧化硅SiOx、氮氧化硅SiON中的一种或多种的组合。第一无机阻隔层271采用化学气相沉积(CVD，Chemical Vapor Deposition)工艺形成。
示例性地，有机阻隔层272的材料包括丙烯酸基聚合物、硅基聚合物及环氧基聚合物中的一种或多种的聚合物(polymer)组合，采用喷墨打印(Ink Jet Printing IJP)方式将上述材料制作在第一无机阻隔层271上，并进行紫外线(UV，ultraviolet)固化，以形成该有机阻隔层272。
示例性地，第二无机阻隔层273的材料包括氮化硅SiNx、二氧化硅SiOx、氮氧化硅SiON中的一种或多种的组合。第二无机阻隔层273采用化学气相沉积(CVD，Chemical Vapor Deposition)工艺形成。
本公开一些实施例提供一种显示基板的制作方法，参见图2～图11、以及 图14，该制作方法包括：
S10，提供衬底11。
S20，在衬底的第一侧形成电压信号线13和驱动电路结构14，电压信号线13位于非显示区Q 2并围绕显示区Q 1设置，驱动电路结构14位于非显示区Q 2、并且位于电压信号线13的靠近显示区Q 1一侧。
S30，在形成有电压信号线13和驱动电路结构14的衬底11上形成阴极搭接层17，阴极搭接层17位于非显示区Q 2并围绕显示区Q 1设置；阴极搭接层17包括远离显示区Q 1的第一部分171以及向靠近显示区Q 1的方向延伸的第二部分172，第一部分171与第二部分172相连接；第一部分171靠近衬底11的至少部分表面与电压信号线13的相应部分电接触；第二部分172在衬底11上的正投影与驱动电路结构14在衬底11上的正投影至少部分重叠。
S40，在形成有阴极层搭接层17的衬底11上形成阴极层24，阴极层24从显示区Q 1延伸到非显示区Q 2，并且阴极层24的边缘z 2位于非显示区Q 2内；阴极层24与阴极搭接层17的第二部分172远离衬底11的至少部分表面电接触。
通过上述制作方法形成的显示基板，可以在保证阴极层24与电压信号线13电连接的同时，减小阴极层24的面积，进而可以在保证封装可靠性的同时相应的减小封装层的面积，使显示基板100的非显示区Q 2在第一方向X上的尺寸减小，也即减小非显示区Q 2占整个显示基板的比例，这将使得采用该显示基板100的显示装置的边框可以相应的减小，提高了显示装置的屏占比。
在一些实施例中，参见图2、图4和图15，在S30之前还包括：
S21，在衬底11的第一侧形成图案化的平坦层，图案化的平坦层包括平坦层主体15和第一阻挡层161。
平坦层主体15从显示区Q 1延伸到非显示区Q 2，并且平坦层主体15的边缘位于非显示区Q 2内，平坦层主体15与电压信号线13在垂直于衬底11的方向上无交叠，平坦层主体15完全覆盖驱动电路结构14。通过设置平坦层主体15，可以使位于平坦层主体15上的膜层(例如像素定义层主体20、部分阴极搭接层17、以及图6和图7中示出的多个阳极18)更加平整。
第一阻挡层161位于电压信号线13的远离显示区Q 1的一侧，第一阻挡层161构成第一阻挡坝16的一部分。
在一些实施例中，参见图2、图7和图15，在S40之前还包括：
S31，在衬底11的第一侧形成图案化的像素定义层，图案化的像素定义层包括像素定义层主体20、多个填充物201、第二阻挡层162和第三阻挡层。
像素定义层主体20从显示区Q 1延伸到非显示区Q 2，像素定义层主体20的边缘z 1位于非显示区Q 2内.像素定义层主体20覆盖阴极搭接层17的靠近显示区Q 1的边缘，并且覆盖阴极搭接层17的第二部分172远离衬底11的部分表面。像素定义层主体20的边缘z 1比阴极层24的边缘z 2更靠近显示区Q 1；这样一方面可以通过像素定义层主体20限定阴极搭接层17的位置；另一方面可以使阴极搭接层17的第二部分172的远离衬底11的部分表面露出，避免像素定义层主体20影响阴极层24与阴极搭接层17电接触。此时，阴极层24包括覆盖像素定义层主体20的部分和覆盖阴极搭接层17的部分，且这两部分是连续的。像素定义层主体20位于显示区Q 1的部分具有多个开口202，多个开口202被配置为限定多个子像素的发光区域，这样可以通过控制多个子像素发光，使显示基板100显示画面。
参见图6和图7，阴极搭接层17上具有阵列分布的多个通孔173，多个通孔173中的至少一个通孔173贯穿阴极搭接层17的远离衬底11的表面和阴极搭接层17的靠近衬底11的表面，多个填充物201一一对应地填充至多个通孔173中，这样，一方面可以使阴极搭接层17的上表面平整，便于在阴极搭接层17上制作其它膜层；另一方面通过将多个填充物201与像素定义层主体20同层制作，简化了显示基板100的制作工艺。
参见图2第二阻挡层162位于第一阻挡层161的远离衬底11的表面上，也即第二阻挡层162构成第一阻挡坝16的一部分。第三阻挡层位于阴极搭接层17的远离衬底11的表面上，第三阻挡层17构成第二阻挡坝19，或者第二阻挡层构成第二阻挡坝19的一部分。
本公开一些实施例提供了一种显示装置。如图16所示，显示装置200包括上述任一实施例所述的显示基板100。
示例性地，显示装置200为电致发光显示装置，例如液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开一些实施例中的显示基板100的非显示区Q 2所占的比例较小，因此，将其安装于显示装置中，可以减小显示装置200的边框202，提高显示装置200的屏占比，即显示装置200的显示侧中，显示屏幕201的面积占该显示侧的表面总面积(包括屏幕201的面积和边框202的面积)的比例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的 保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种显示基板，具有显示区，和与所述显示区邻接的非显示区；所述显示基板包括：
    衬底；
    设置于所述衬底的第一侧的电压信号线，所述电压信号线位于所述非显示区并围绕所述显示区设置；
    设置于所述衬底的第一侧的驱动电路结构，所述驱动电路结构位于所述非显示区，并且位于所述电压信号线的靠近所述显示区一侧；
    设置于所述电压信号线及所述驱动电路结构的远离所述衬底的一侧的阴极搭接层，所述阴极搭接层位于所述非显示区并围绕所述显示区设置；所述阴极搭接层包括远离所述显示区的第一部分以及向靠近所述显示区的方向延伸的第二部分，所述第一部分与所述第二部分相连接；所述第一部分靠近所述衬底的至少部分表面与所述电压信号线的相应部分电接触；所述第二部分在所述衬底上的正投影与所述驱动电路结构在所述衬底上的正投影至少部分重叠；
    设置于所述衬底的第一侧的阴极层，所述阴极层从所述显示区延伸到所述非显示区，并且所述阴极层的边缘位于所述非显示区；所述阴极层与所述阴极搭接层的第二部分远离所述衬底的至少部分表面电接触。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    设置于所述衬底的第一侧的像素定义层，所述像素定义层包括位于所述阴极层的靠近所述衬底一侧的像素定义层主体，所述像素定义层主体从所述显示区延伸到所述非显示区，所述像素定义层主体的边缘位于所述非显示区；
    所述像素定义层主体覆盖所述阴极搭接层的靠近所述显示区的边缘，并且覆盖所述阴极搭接层的第二部分远离所述衬底的部分表面；所述像素定义层主体的边缘比所述阴极层的边缘更靠近所述显示区；
    所述像素定义层主***于所述显示区的部分具有多个开口，所述多个开口被配置为限定多个子像素的发光区域。
  3. 根据权利要求2所述的显示基板，其中，所述显示基板还包括：
    设置于所述衬底的第一侧的源漏金属层，所述电压信号线及所述驱动电路结构中的源极和漏极位于所述源漏金属层中；
    设置于所述衬底的第一侧的平坦层，所述平坦层包括设置于所述源漏金属层、所述像素定义层主体及所述阴极搭接层三者之间的平坦层主体，所述平坦层主体从所述显示区延伸到所述非显示区，并且所述平坦层主体的边缘位于所述非显示区；
    所述平坦层主体完全覆盖所述驱动电路结构；
    所述阴极搭接层覆盖所述平坦层主体的远离所述显示区的边缘，并且覆盖所述平坦层主体的远离所述衬底的至少部分表面。
  4. 根据权利要求3所述的显示基板，其中，
    所述阴极搭接层上具有阵列分布的多个通孔，所述多个通孔中的至少一个通孔贯通所述阴极搭接层；
    所述多个通孔中的至少部分通孔在所述衬底上的正投影位于所述平坦层主体在所述衬底上的正投影的范围之内；
    所述显示基板还包括：
    多个填充物，一一对应地填充于所述多个通孔内，所述多个填充物中的至少一个填充物的材料与所述像素定义层主体的材料相同。
  5. 根据权利要求3或4所述的显示基板，其中，所述显示基板还包括：
    设置于所述衬底的第一侧的第一阻挡坝，所述第一阻挡坝位于所述非显示区，所述源漏金属层沿从显示区到非显示区的方向延伸到所述第一阻挡坝靠近所述显示区的侧面；
    所述阴极搭接层沿从显示区到非显示区的方向延伸到所述第一阻挡坝靠近所述显示区的侧面，并且所述阴极搭接层的与所述电压信号线电接触的部分位于所述平坦层主体和所述第一阻挡坝之间。
  6. 根据权利要求5所述的显示基板，其中，
    所述第一阻挡坝的材料包括形成所述像素定义层主体的材料和/或形成所述平坦层主体的材料。
  7. 根据权利要求5或6所述的显示基板，其中，所述显示基板还包括：
    设置于所述衬底的第一侧的无机绝缘层，所述无机绝缘层包括比所述源漏金属层更靠近所述衬底的层间介质层；
    所述层间介质层从所述显示区延伸到所述非显示区，并且所述层间介质层的边缘位于所述第一阻挡坝远离所述显示区的一侧，所述层间介质层延伸到第一阻挡坝远离所述显示区一侧的部分形成有至少一个槽，所述至少一个槽围绕所述第一阻挡坝设置。
  8. 根据权利要求3～7中任一项所述的显示基板，其中，所述显示基板还包括：
    设置于所述平坦层主体与所述像素定义层主体之间、且位于所述显示区的阳极层；所述阳极层包括多个阳极，所述多个阳极与所述多个开口一一对应；
    设置于所述像素定义层主体的远离所述衬底一侧的至少一层有机功能层，所述至少一层有机功能层从所述显示区延伸到所述非显示区，并且所述至少一层有机功能层的边缘位于所述非显示区内，所述至少一层有机功能层的边缘比所述像素定义层主体的边缘更靠近所述显示区。
  9. 根据权利要求8所述的显示基板，其中，所述至少一层有机功能层包括电子传输层、电子注入层、有机发光层、空穴传输层或空穴注入层中的至少一种。
  10. 根据权利要求1～9中任一项所述的显示基板，其中，
    所述显示区大致呈矩形，所述阴极搭接层围绕该矩形的两个长边及一个短边设置。
  11. 根据权利要求10所述的显示基板，其中，
    在所述非显示区的对应于所述两个长边的区域内，所述阴极层与所述阴极搭接层的接触部位在第一方向上的宽度为D1，D1大于或等于150μm，且小于或等于350μm；
    在所述非显示区的对应于所述一个短边的区域内，所述阴极层与所述阴极搭接层的接触部位在所述第一方向上的宽度为D2，D2小于D1，且大于零；
    所述第一方向为平行于所述衬底、且垂直于所述显示区与所述非显示区的分界面的方向。
  12. 根据权利要求1～11中任一项所述的显示基板，其中，所述显示基板还包括：
    设置于所述阴极层的远离所述衬底一侧的光取出层，所述光取出层从所述显示区延伸到所述非显示区，并且所述光取出层的边缘位于所述非显示区，所述光取出层的至少部分边缘在所述衬底上的正投影处于所述阴极层在所述衬底上的正投影的范围之内。
  13. 根据权利要求12所述的显示基板，其中，所述光取出层的边缘在所述衬底上的正投影与所述阴极层的边缘在所述衬底上的正投影大致重合。
  14. 根据权利要求12或13所述的显示基板，其中，所述显示基板还包括：
    设置于所述光取出层的远离所述阴极层一侧的增透层，所述增透层从所述显示区延伸到所述非显示区，并且所述增透层的边缘位于所述非显示区，所述增透层在所述衬底上的正投影处于所述阴极层在所述衬底上的正投影的范围之内。
  15. 根据权利要求14所述的显示基板，其中，所述增透层包括氟化锂层。
  16. 根据权利要求14或15所述的显示基板，其中，所述显示基板还包括：
    设置于所述阴极搭接层的远离所述衬底的表面上的第二阻挡坝，所述第二阻挡坝与所述阴极层、所述光取出层及所述增透层在垂直于所述衬底的方向上无交叠。
  17. 根据权利要求16所述的显示基板，其中，所述阴极层的边缘与所述第二阻挡坝在第一方向上的间距大于或等于80μm；所述增透层的边缘与所述第二阻挡坝在第一方向上的间距大于或等于250μm；
    所述第一方向为平行于所述衬底、且垂直于所述显示区与所述非显示区的分界面的方向。
  18. 根据权利要求16或17所述的显示基板，其中，所述显示基板还包括封装层，所述封装层包括：
    设置于所述增透层的远离所述光取出层一侧的第一无机阻隔层，所述第一无机阻隔层覆盖所述第二阻挡坝；
    设置于所述第一无机阻隔层的远离所述增透层一侧的有机阻隔层，所述有机阻隔层至少位于所述第二阻挡坝围设出的区域之内；以及，
    设置于所述有机阻隔层的远离所述第一无机阻隔层一侧的第二无机阻隔层，所述第二无机阻隔层覆盖所述第二阻挡坝。
  19. 一种显示基板的制作方法，所述显示基板包括显示区和与所述显示区邻接的非显示区；所述制作方法包括：
    提供衬底；
    在所述衬底的第一侧形成电压信号线和驱动电路结构，所述电压信号线位于所述非显示区并围绕所述显示区设置，所述驱动电路结构位于所述非显示区、并且位于所述电压信号线的靠近所述显示区一侧；
    在形成有所述电压信号线和所述驱动电路结构的衬底上形成阴极搭接层，所述阴极搭接层位于所述非显示区并围绕所述显示区设置；所述阴极搭接层包括远离所述显示区的第一部分以及向靠近所述显示区的方向延伸的第二部分，所述第一部分与所述第二部分相连接；所述第一部分靠近所述衬底的至少部分表面与所述电压信号线的相应部分电接触；所述第二部分在所述衬底上的正投影与所述驱动电路结构在所述衬底上的正投影至少部分重叠；
    在形成有所述阴极层搭接层的衬底上形成阴极层，所述阴极层从所述显示区延伸到所述非显示区，并且所述阴极层的边缘位于所述非显示区内；所述阴极层与所述阴极搭接层的第二部分远离所述衬底的至少部分表面电接 触。
  20. 根据权利要求19所述的制作方法，其中，所述在形成有所述电压信号线和所述驱动电路结构的衬底上形成阴极搭接层的步骤之前还包括：
    在所述衬底的第一侧形成图案化的平坦层，所述图案化的平坦层包括平坦层主体和第一阻挡层；
    所述平坦层主体从所述显示区延伸到所述非显示区，并且所述平坦层主体的边缘位于所述非显示区内；所述平坦层主体与所述电压信号线在垂直于所述衬底的方向上无交叠；
    所述第一阻挡层位于所述电压信号线的远离所述显示区的一侧。
  21. 根据权利要求20所述的制作方法，其中，所述在形成有所述阴极层搭接层的衬底上形成阴极层的步骤之前，还包括：
    在所述衬底的第一侧形成图案化的像素定义层，所述图案化的像素定义层包括像素定义层主体、多个填充物、第二阻挡层和第三阻挡层；
    所述像素定义层主体从所述显示区延伸到所述非显示区，所述像素定义层主体的边缘位于所述非显示区内；所述像素定义层主体覆盖所述阴极搭接层的靠近所述显示区的边缘，并且覆盖所述阴极搭接层的第二部分远离所述衬底的部分表面；所述像素定义层主体的边缘比所述阴极层的边缘更靠近所述显示区；所述像素定义层主***于所述显示区的部分具有多个开口，所述多个开口被配置为限定多个子像素的发光区域；
    所述阴极搭接层上具有阵列分布的多个通孔，所述多个通孔中的至少一个通孔贯穿所述阴极搭接层的远离所述衬底的表面和所述阴极搭接层的靠近所述衬底的表面；所述多个填充物一一对应地填充至所述多个通孔中；
    所述第二阻挡层位于所述第一阻挡层的远离所述衬底的表面上；
    所述第三阻挡层位于所述阴极搭接层的远离所述衬底的表面上。
  22. 一种显示装置，包括如权利要求1～18中任一项所述的显示基板。
PCT/CN2019/119581 2019-11-20 2019-11-20 显示基板及其制作方法和显示装置 WO2021097690A1 (zh)

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