WO2021088156A1 - 一种功率半导体器件 - Google Patents

一种功率半导体器件 Download PDF

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WO2021088156A1
WO2021088156A1 PCT/CN2019/121254 CN2019121254W WO2021088156A1 WO 2021088156 A1 WO2021088156 A1 WO 2021088156A1 CN 2019121254 W CN2019121254 W CN 2019121254W WO 2021088156 A1 WO2021088156 A1 WO 2021088156A1
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gate
polysilicon
trench
true
dummy gate
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PCT/CN2019/121254
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English (en)
French (fr)
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苏元宏
王亚飞
王彦刚
戴小平
覃荣震
罗海辉
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株洲中车时代电气股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]

Definitions

  • This article relates to the technical field of power semiconductor devices, in particular to a split-gate trench power semiconductor device.
  • Insulated gate bipolar transistor is the only semiconductor device that combines MOSFET and bipolar transistor. It has the characteristics of high MOSFET input impedance and fast response speed. It is widely used in rail transit, smart grid, and electric Automobiles, new energy development and other fields.
  • trench gates can convert the current channel from horizontal to vertical in the body, effectively eliminating the JFET effect in the planar gate body, and reducing the cell size, so that the channel density is no longer affected by the surface area of the chip.
  • Limitations greatly increase the cell density, thereby greatly increasing the current density of the chip and reducing the on-state loss of the chip.
  • the trench gate density increases, it will lead to higher parasitic capacitance of the chip, which will adversely affect the turn-on and turn-off of the chip, increase the switching loss of the chip, and lead to a compromise between the on-state loss of the chip and the switching loss. Imbalance.
  • FIG. 1 is a cross-sectional view of a conventional trench gate IGBT device with a carrier storage layer, including: wafer substrate 101, N well region 102, P well region 103, N+ doped region 104, and P+ doped Region 105, polysilicon 106, first oxide layer 107, second oxide layer 108, emitter metal layer 109.
  • the second technical problem to be solved in this paper is that during the long-term use of traditional trench gate power semiconductor devices, the plasma in the body will repeatedly impact the oxide layer at the bottom of the trench during the chip switching process, and the oxide layer at the bottom of the trench will withstand high long-term Pressure will affect the long-term reliability of the chip.
  • this paper provides a split-gate trench power semiconductor device.
  • This article provides a split-gate trench power semiconductor device, including an active region provided on a semiconductor substrate, the active region including a first well region longitudinally stacked along the surface of the semiconductor substrate toward the bottom of the semiconductor substrate, and The second well region, wherein the multi-sub-conductivity types of the first well region and the second well region are complementary; one or more true gate trenches penetrating the first well region and the second well region; wherein, true gate trenches
  • the split polysilicon true gate includes a polysilicon main true gate and a polysilicon auxiliary true gate separately arranged near the top and bottom of the trench.
  • the polysilicon main true gate is used for connecting to an external gate circuit.
  • Figure 1 shows a cross-sectional view of an existing conventional trench gate IGBT device with a carrier storage layer
  • FIG. 2 is a schematic diagram of the structure of a trench power semiconductor device with a split gate according to an example of this article
  • FIG. 3 is a schematic diagram of a split-gate power semiconductor device with separately controllable polysilicon main gate metal connection according to an example of this article;
  • FIG. 4 is a schematic diagram of the structure of a power semiconductor device with a false gate split gate according to another example of this article;
  • 5a is a schematic structural diagram of a split gate power semiconductor device with a floating split gate according to another embodiment of this document;
  • Fig. 5b is a schematic structural diagram of a split gate power semiconductor device with a split false gate grounded according to another embodiment of this document;
  • FIG. 6 is a schematic diagram of the structure of a double split-gate power semiconductor device adopting a uniform thickness oxide layer according to a third embodiment of this document;
  • FIG. 7 is a schematic structural diagram of a split-gate power semiconductor device with a conventional dummy gate according to a third embodiment of this document.
  • This embodiment provides a split-gate trench power semiconductor device, which includes an active region provided on a semiconductor substrate, and the active region includes a first well vertically stacked along the surface of the semiconductor substrate toward the bottom of the semiconductor substrate. Region and the second well region, and one or more true gate trenches formed by etching that penetrate the first and second well regions; wherein, the polyconductors of the first and second well regions are conductive.
  • the types are complementary, where a split polysilicon true gate is provided in the true gate trench, and the split polysilicon true gate includes a polysilicon main true gate and a polysilicon auxiliary true gate separately arranged near the top and bottom of the trench, respectively, and the polysilicon main true gate
  • the gate is a control gate used to connect with an external gate circuit.
  • the thickness of the interlayer dielectric between the polysilicon main and true gate and the sidewall of the true gate trench is smaller than the thickness of the interlayer dielectric between the polysilicon auxiliary true gate and the sidewall of the true gate trench and the layer between the sidewall of the polysilicon auxiliary true gate and the true gate trench and the bottom of the true gate trench.
  • the thickness of the medium is smaller than the thickness of the interlayer dielectric between the polysilicon auxiliary true gate and the sidewall of the true gate trench and the layer between the sidewall of the polysilicon auxiliary true gate and the true gate trench and the bottom of the true gate trench.
  • the polysilicon main gate is connected to an external gate driving circuit through metal, and the polysilicon auxiliary gate is a floating gate structure that is not connected to any circuit.
  • the active region further includes one or more dummy gate trenches formed by etching and penetrating the first well region and the second well region, wherein the dummy gate trenches are on the periphery of the true gate trenches. It is arranged separately from the real gate trench, and a polysilicon dummy gate is arranged in the dummy gate trench.
  • the polysilicon dummy gate is a split polysilicon dummy gate
  • the split polysilicon dummy gate includes a polysilicon main dummy gate and a polysilicon auxiliary dummy gate separately arranged near the top and bottom of the trench, respectively.
  • the polysilicon main dummy gate is a floating gate structure that is not connected to any circuit, or the polysilicon main dummy gate is connected to the emitter metal layer; the polysilicon auxiliary dummy gate is a floating gate structure that is not connected to any circuit .
  • the thickness of the interlayer dielectric between the polysilicon main dummy gate and the sidewalls of the dummy gate trench is smaller than the thickness of the interlayer dielectric between the polysilicon auxiliary dummy gate and the sidewalls of the dummy gate trench and the bottom of the dummy gate trench.
  • the thickness of the medium is smaller than the thickness of the interlayer dielectric between the polysilicon auxiliary dummy gate and the sidewalls of the dummy gate trench and the bottom of the dummy gate trench.
  • both the polysilicon main dummy gate and the polysilicon auxiliary dummy gate include at least two separate sub-gates, and each sub-gate is isolated by an interlayer dielectric.
  • FIG. 2 is a schematic structural diagram of a power semiconductor device with a split gate trench according to the first embodiment. As shown in FIG. 2, it may include: a semiconductor substrate 2, an N+ region 3, a P+ region 4, an N-well region 5, a P-well region 6, a plurality of strip-shaped trench split polysilicon gates (including polysilicon main gate 11, polysilicon The auxiliary gate 12), the oxide layer 7, the emitter metal layer 8, the anode P region 9, and the collector metal layer 10.
  • the “inside the surface of the semiconductor substrate 2” in this specification refers to a region of a certain depth extending downward from the surface of the semiconductor substrate 1 and this region belongs to a part of the semiconductor substrate 2.
  • the semiconductor substrate 2 may include semiconductor elements, such as silicon or silicon germanium with a single crystal, polycrystalline or amorphous structure, and may also include a mixed semiconductor structure, such as silicon carbide, alloy semiconductor, or a combination thereof, which is not limited here. .
  • the semiconductor substrate 2 in this embodiment adopts a silicon substrate in one embodiment, and an N-type or P-type silicon substrate can be used. In this embodiment, an N-type substrate is used as an example for description.
  • a plurality of strip-shaped trench polysilicon gates wherein the inside of the strip-shaped trench polysilicon gate is separated to form a split gate, and the plurality of strip-shaped trench gates are respectively located on the surface of the semiconductor substrate and formed by downward etching And extend along the surface of the semiconductor substrate, and all the strip-shaped trench polysilicon gates extend downward from the surface of the semiconductor substrate once through the P-well region and the N-well region.
  • the split polysilicon gate is split into a polysilicon main gate 11 and a polysilicon auxiliary gate 12.
  • the polysilicon main gate 11 is close to the top of the trench, above the polysilicon auxiliary gate 12, and the polysilicon auxiliary gate 12 is close to At the bottom of the trench, under the polysilicon main gate 11, the polysilicon auxiliary gate 12 located at the bottom of the trench has a floating structure.
  • the interlayer dielectric between the split polysilicon gates is oxide 7.
  • the split gate setting reduces the parasitic capacitance in the power semiconductor device, reduces the gate charge, shortens the Miller platform, reduces the loss of the chip switch, and further optimizes the compromise between the conduction voltage drop and the switching loss of the power semiconductor device relationship.
  • the specific structure of the active region is similar to the structure of a traditional trench gate power semiconductor device, including an N+ region 3, a P+ region 4, an N-well region 5, and a P-well region 6.
  • the N+ region 3 is located on the surface of the active region.
  • the P+ region 4 is in contact with the N+ region 3, and its length is smaller than the distance between the strip-shaped trench polysilicon split gates.
  • the P-well region 6 is located below the P+ region 4, and its length is equal to the distance between the strip-shaped trench polysilicon split gates.
  • the N-well region 5 is located below the P-well region 5, and its length is equal to the distance between the strip-shaped trench polysilicon split gates.
  • a shallow groove (not marked in the figure) is provided between the two N+ regions 3, and the P+ region 4 is located below the shallow groove.
  • the provision of a shallow groove between the two N+ regions 3 is helpful for the reverse bias safe working area of the trench power semiconductor device, especially for medium and high voltage devices.
  • a carrier storage region N-well region 5 is also provided, and the polysilicon split gate trench passes through the N-well region.
  • the strip-shaped trench polysilicon main gate is a true gate 13 or a false gate 14, as shown in FIG. 3.
  • the false gate trench is arranged separately from the true gate trench on the periphery of the true gate trench, so A polysilicon dummy gate is arranged in the dummy gate trench.
  • the main gate 11 of the double-split strip-shaped trench polysilicon dummy gate is located above the strip-shaped trench dummy gate and auxiliary gate 12, the main gate is floating or grounded, and the number of dummy gate structures can be set For one or more.
  • the power semiconductor device structure of this embodiment includes a split true gate 13 and a false gate 14.
  • the metal is connected to the external gate drive circuit, as shown in FIG. 3.
  • two split polysilicon main control gates 15 and main control gates 16 are connected to the external gate drive by metal, and different gates are used.
  • the driving signal controls the polysilicon main control gate 15 and the main control gate 16 separately, and the trade-off relationship between the conduction voltage drop and the switching loss of the power semiconductor device can be further optimized.
  • the split polysilicon main gate in one embodiment is the true gate 13, and the true gate is the gate that plays a control role in the trench gate power semiconductor device cell. If the polysilicon split gate is applied to the dummy gate 14 again, the dummy gate is the gate that has no control function in the trench gate power semiconductor device cell, and is usually floating or grounded.
  • the number of false gates such as one or more, the current density of the chip can be adjusted, which is conducive to adjusting the trade-off relationship between the circuit current density and the short-circuit safe working area, and can further reduce the parasitic parameters to make this power semiconductor
  • the device is suitable for high voltage applications above 1200V.
  • the thickness of the oxide layer of the polysilicon main gate 11 and the sidewall of the trench is less than or equal to the thickness of the oxide layer of the polysilicon auxiliary gate 12, the bottom of the trench, and the sidewall.
  • the polysilicon auxiliary The thickness of the oxide layer at the bottom of the gate 12 and the trench is Moreover, the polysilicon auxiliary gate 12 at the bottom of the trench is set in the air.
  • the back structure of the split-gate trench power semiconductor device of this embodiment may be a punch-through type, a soft punch-through type, or a non-punch-through type structure.
  • the soft punch-through structure includes an N-type buffer layer (not shown in the figure), an anode P region 9 and a collector metal layer 10.
  • the N-type buffer layer is located below the N-type substrate 2
  • the anode P region 9 is located below the N-type buffer layer
  • the collector metal layer 10 is located below the anode P region 9.
  • the focus of this embodiment is that the above-mentioned split-gate trench power semiconductor device structure is only the basic structure of one cell of the device.
  • the so-called cell refers to the smallest repeating unit on the entire split-gate trench power semiconductor device, that is, the split gate provided herein.
  • the trench power semiconductor device is composed of a plurality of cells of the above-mentioned structure.
  • split gates are formed by separating part or all of the strip-shaped trench polysilicon gates inside the plurality of strip-shaped trench polysilicon gates to reduce the parasitic capacitance in the power semiconductor device and reduce the gate charge Qg. Shorten the Miller platform.
  • the chip's split-gate electrical connection mode is optimized. Through gate drive control, the trade-off relationship between chip conduction voltage drop and switching loss is effectively improved.
  • a thicker oxide layer is provided at the bottom of the trench, and the polysilicon auxiliary gate split at the bottom of the trench is floated to reduce the voltage force of the oxide layer at the bottom of the trench in the blocking state and the repetition of plasma during the switching process Impact, improve the reliability of the chip for long-term use.
  • FIG. 5a is a schematic structural diagram of a split-gate power semiconductor device with floating dual-split gates according to the second embodiment of this paper
  • FIG. 5b is a schematic structural diagram of a split-gate power semiconductor device with double-split dummy gates grounded according to the second embodiment of this paper. As shown in FIG.
  • a semiconductor substrate 2 may include: a semiconductor substrate 2, an N+ region 3, a P+ region 4, an N well region 5, a P well region 6, a strip trench double-split dummy gate 17 (including polysilicon main dummy gate 171 and Polysilicon auxiliary dummy gate 172), strip trench split true gate 13 (including polysilicon main gate 131 and polysilicon auxiliary gate 132), oxide layer 7, emitter metal layer 7, anode P region 9, and collector metal layer 10 .
  • the polysilicon main dummy gate 171 has a floating structure, which can change the input and output capacitance of the trench power semiconductor device, thereby adjusting the development speed of the trench power semiconductor device and the control of the switching speed by the gate resistance.
  • FIG. 5b it may include: a semiconductor substrate 2, an N+ region 3, a P+ region 4, an N well region 5, a P well region 6, a strip trench double-split dummy gate 17 (including polysilicon main dummy gate 171 and Polysilicon auxiliary dummy gate 172), strip trench split true gate 13 (including polysilicon main gate 131 and polysilicon auxiliary gate 132), oxide layer 7, emitter metal layer 8, anode P region 9, and collector metal layer 10 .
  • the polysilicon main dummy gate 171 is a grounded structure.
  • the N+ zone 3, P+ zone 4, and the polysilicon main dummy gate 171 are connected to the emitter metal layer 8, which significantly reduces the turn-on voltage drop of the trench gate power semiconductor device and changes the trench power semiconductor device.
  • the input and output capacitance of the device can adjust the development speed of trench power semiconductor devices and the control of the switching speed by the gate resistance.
  • the gate electrode of the dummy gate is in contact with the emitter metal layer, so that the dummy gate can be grounded well.
  • the interlayer dielectric between the split polysilicon gates in this embodiment is oxide 7.
  • the arrangement of the split gate reduces the density of the trench gate in disguised form, reduces the harmful parasitic effects in the power semiconductor device, reduces the gate charge, shortens the Miller platform, reduces the loss of the chip switch, and further optimizes the power semiconductor The trade-off relationship between device conduction voltage drop and switching loss.
  • the strip-shaped trench polysilicon main gate in this embodiment is a true gate 13 or a false gate 14, as shown in FIG. 3.
  • the false gate trench is separated from the true gate trench at the periphery of the true gate trench Arrangement, a polysilicon dummy gate is arranged in the dummy gate trench.
  • the main gate 171 of the double-split strip-shaped trench polysilicon dummy gate in this embodiment is located above the strip-shaped trench dummy gate auxiliary gate 172, and the main gate 171 of the dummy gate is floating or grounded.
  • the number of dummy gate structures can be one or more.
  • the dummy gate of the split-gate power semiconductor device may adopt a double split gate, that is, the dummy gate is only split into upper and lower gates, which are respectively a polysilicon main dummy gate 171 and a polysilicon auxiliary dummy gate 172.
  • the polysilicon main dummy gate 171 is in the polysilicon Above the auxiliary dummy gate 172, the polysilicon auxiliary dummy gate 172 is under the polysilicon main dummy gate 171, and the polysilicon auxiliary dummy gate 172 located at the lower part of the trench has a floating structure.
  • the polysilicon split gate is applied to the dummy gate 17.
  • the number of dummy gates such as one or more, the current density of the chip can be adjusted, which is beneficial to adjust the trade-off relationship between the circuit current density and the short-circuit safe working area.
  • the parasitic parameters can also be further reduced, so that the power semiconductor device is suitable for applications with high voltages above 1200V.
  • the thickness of the oxide layer on the sidewalls of the polysilicon main gate (171, 131) trench is less than or equal to the thickness of the oxide layer on the bottom and sidewalls of the polysilicon auxiliary gate (172, 132) trench.
  • the polysilicon The thickness of the oxide layer at the bottom of the auxiliary gate (172,132) trench is
  • the polysilicon auxiliary gates (172, 132) at the bottom of the trench are set in the air.
  • the back structure of the split-gate trench power semiconductor device of this embodiment may be a punch-through type, a soft punch-through type, or a non-punch-through type structure.
  • the soft punch-through structure includes an N-type buffer layer (not shown in the figure), an anode P region 9 and a collector metal layer 10.
  • the N-type buffer layer is located below the N-type substrate 2
  • the anode P region 9 is located below the N-type buffer layer
  • the collector metal layer 10 is located below the anode P region 9.
  • the focus of this embodiment is that the above-mentioned split-gate trench power semiconductor device structure is only the basic structure of one cell of the device.
  • the so-called cell refers to the smallest repeating unit on the entire split-gate trench power semiconductor device, that is, the split gate provided herein.
  • the trench power semiconductor device is composed of a plurality of cells of the above-mentioned structure.
  • split gates are formed by separating the true gates of multiple strip-shaped trench polysilicon gates, and part of the strip-shaped trench polysilicon dummy gates are separated up and down to form split gates, which reduces parasitic capacitance in power semiconductor devices and reduces The small gate charge Qg shortens the Miller plateau.
  • the chip split gate electrical connection mode is optimized.
  • the main gate of the polysilicon dummy gate can adopt a floating structure or a grounded structure as required, which effectively improves the trade-off relationship between chip conduction voltage drop and switching loss.
  • a thicker oxide layer is provided at the bottom of the trench, and the polysilicon auxiliary gate split at the bottom of the trench is floated to reduce the voltage force of the oxide layer at the bottom of the trench in the blocking state and the repetition of plasma during the switching process Impact, improve the reliability of the chip for long-term use.
  • FIG. 6 is a schematic diagram of the structure of a double split gate power semiconductor device using an oxide layer of uniform thickness according to another embodiment of this document
  • FIG. 6 is a schematic diagram of the structure of a split gate power semiconductor device according to the third embodiment of this document.
  • it may include: semiconductor substrate 2, N+ region 3, P+ region 4, N-well region 5, P-well region 6, strip trench split true gate 13 (including polysilicon main gate 131 and polysilicon auxiliary Gate 132), strip trench double-split dummy gate 18 (including polysilicon main dummy gate 181 and polysilicon auxiliary dummy gate 182), oxide layer 7, emitter metal layer 8, anode P region 9, and collector metal layer 10 .
  • the polysilicon main dummy gate 181 has a floating structure, which changes the input and output capacitance of the trench power semiconductor device, thereby adjusting the development speed of the trench power semiconductor device and the control of the switching speed by the gate resistance.
  • FIG. 7 is a schematic structural diagram of a split-gate power semiconductor device with a traditional dummy gate according to another embodiment of this document
  • FIG. 7 is a schematic structural diagram of a split-gate power semiconductor device according to the third embodiment of this document.
  • it may include: semiconductor substrate 2, N+ region 3, P+ region 4, N-well region 5, P-well region 6, strip-shaped trench split true gate 13 (including polysilicon main gate and polysilicon auxiliary gate ), the traditional dummy gate 19 without splitting of the strip trench, the oxide layer 7, the emitter metal layer 8, the anode P region 9, and the collector metal layer 10.
  • the polysilicon dummy gate 19 is a floating structure, which changes the input and output capacitance of the trench power semiconductor device, thereby adjusting the development speed of the trench power semiconductor device and the control of the switching speed by the gate resistance.
  • the thickness of the oxide layer of the main gate 181 and the sidewall of the trench of the double-split dummy gate of the strip trench is equal to the thickness of the oxide layer of the polysilicon auxiliary gate 182, the bottom of the trench, and the sidewall.
  • the conventional dummy gate 19 trenches The thickness of the oxide layer on the sidewall of the trench adopts a structure of an oxide layer of uniform thickness.
  • the polysilicon dummy gate is an integrated polysilicon dummy gate.
  • the thickness of the oxide layer at the bottom of the polysilicon trench is And the polysilicon gate at the bottom of the trench is set in the air.
  • the interlayer dielectric between the split polysilicon gates in this embodiment is oxide 7.
  • the arrangement of the split gate reduces the density of the trench gate in disguised form, reduces the harmful parasitic effects in the power semiconductor device, reduces the gate charge, shortens the Miller platform, reduces the loss of the chip switch, and further optimizes the power semiconductor The trade-off relationship between device conduction voltage drop and switching loss.
  • the strip-shaped trench split polysilicon main gate in this embodiment is a true gate 13, or a dummy gate 18, or a traditional dummy gate 19, as shown in FIG. 3, the dummy gate trench is on the periphery of the true gate trench It is arranged separately from the real gate trench, and a polysilicon dummy gate is arranged in the dummy gate trench.
  • the back structure of the split-gate trench power semiconductor device of this embodiment may be a punch-through type, a soft punch-through type, or a non-punch-through type structure.
  • the soft punch-through structure includes an N-type buffer layer (not shown in the figure), an anode P region 9 and a collector metal layer 10.
  • the N-type buffer layer is located below the N-type substrate 2
  • the anode P region 9 is located below the N-type buffer layer
  • the collector metal layer 10 is located below the anode P region 9.
  • the focus of this embodiment is that the above-mentioned split-gate trench power semiconductor device structure is only the basic structure of one cell of the device.
  • the so-called cell refers to the smallest repeating unit on the entire split-gate trench power semiconductor device, that is, the split gate provided herein.
  • the trench power semiconductor device is composed of a plurality of cells of the above-mentioned structure.
  • split gates are formed by separating the true gates of multiple strip-shaped trench polysilicon gates, and part of the strip-shaped trench polysilicon dummy gates are separated up and down to form split gates, which reduces parasitic capacitance in power semiconductor devices and reduces The small gate charge Qg shortens the Miller plateau.
  • the main gate of the polysilicon false gate adopts a floating structure as required, which can effectively improve the trade-off relationship between chip conduction voltage drop and switching loss.
  • the thickness of the oxide layer on the sidewall of the main gate trench of the strip-shaped trench dummy gate in this embodiment is equal to the thickness of the oxide layer on the bottom and sidewalls of the polysilicon auxiliary gate trench.
  • the gate is set in the air to reduce the voltage force of the oxide layer at the bottom of the trench in the blocking state and the repeated impact of the plasma during the switching process, thereby improving the reliability of the chip for long-term use.
  • the trench polysilicon split gate can also be applied to other power semiconductor devices, and in one embodiment is used for MOSFETs.
  • one or more of the embodiments herein may have the following advantages:
  • the traditional trench polysilicon gate is set as a split polysilicon gate, and a thicker oxide layer is arranged at the bottom of the trench gate to reduce parasitic capacitance, reduce harmful parasitic effects in power semiconductor devices, and reduce the gate
  • the extremely charge Qg shortens the Miller plateau, thereby reducing the switching loss.
  • This article optimizes the trade-off between the current density of the power semiconductor device and the short-circuit safe working area by setting the dummy gate of the traditional trench polysilicon gate as a split polysilicon gate, and setting it to one or more.
  • the thickness of the oxide layer of the polysilicon main gate and sidewalls is set to be smaller than that between the polysilicon auxiliary gate and the trench sidewall and the bottom of the trench.
  • the thickness of the oxide layer and the floating arrangement of the polysilicon auxiliary gate at the bottom of the trench effectively alleviate the pressure on the oxide layer at the bottom of the trench and improve the reliability of the chip for long-term use.
  • the polysilicon gate in the strip trench is split to form a split gate to reduce the parasitic capacitance, and then use different electrical connections and set oxide layer thicknesses to achieve overall optimization of chip performance.

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Abstract

本文公开了一种***栅沟槽功率半导体器件，包括，设置在半导体衬底上的有源区，有源区包括沿半导体衬底表面向半导体衬底底部方向纵向叠置的第一阱区和第二阱区，以及一个或多个穿透第一阱区和第二阱区的真栅沟槽；真栅沟槽中设置有***式多晶硅真栅，其包括分别靠近沟槽的顶部和底部分离设置的多晶硅主真栅和多晶硅辅真栅，所述多晶硅主真栅为用于与外部栅极驱动电路相连的控制栅；多晶硅主真栅与多晶硅辅真栅之间，多晶硅真栅与真栅沟槽的侧壁以及与真栅沟槽的底部之间通过层间介质隔离。本文通过对条形沟槽内多晶硅栅进行***形成***栅，减小了寄生电容，进而采用不同电连接和设置氧化层厚度，以实现芯片性能的总体优化。

Description

一种功率半导体器件
本申请要求享有与2019年11月8日提交的名称为“一种***栅沟槽功率半导体器件”的中国专利申请CN 201911089118.5的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本文涉及功率半导体器件技术领域，尤其涉及一种***栅沟槽功率半导体器件。
背景技术
绝缘栅双极晶体管(IGBT)是目前为止唯一将MOSFET和双极性晶体管结合在一起的半导体器件，具有MOSFET管输入阻抗高，响应速度快等特点，被广泛应用于轨道交通，智能电网，电动汽车，新能源开发等领域。
随着IGBT技术的快速发展，采用沟槽栅可以将电流沟道由表面横向转为体内纵向，有效消除平面栅体内的JFET效应，同时缩小了元胞尺寸，使沟道密度不再受芯片表面积限制，极大的提高了元胞密度，从而大幅度提升了芯片电流密度，降低了芯片通态损耗。但是随着沟槽栅密度的增大，会导致芯片较高的寄生电容，对芯片的开通和关断产生不利影响，增大芯片的开关损耗，导致芯片通态损耗和开关损耗的折中关系失衡。
此外，在功率半导体器件长期使用过程中，沟槽底部的氧化层长期承受较高的压力，并且在芯片开关过程中体内等离子体会反复冲击沟槽底部的氧化层，影响芯片长期使用的可靠性。图1为现有的具有载流子存储层的传统沟槽栅IGBT器件的剖面图，包括：晶圆基片101、N阱区102、P阱区103、N+掺杂区104、P+掺杂区105、多晶硅106、第一氧化层107、第二氧化层108、发射极金属层109。
因此，有必要采用新的结构来降低芯片内有害的寄生效应，降低寄生电容，优化芯片通态损耗和开关损耗的折中关系，并进一步提高芯片的可靠性。
发明内容
本文所要解决的技术问题之一是传统沟槽栅功率半导体器件随着沟槽栅密 度的增大，会导致芯片产生较高的寄生电容，对芯片的开通和关断产生不利影响，增大芯片开关损耗，导致芯片通态损耗和开关损耗的折中关系失衡。
本文所要解决的技术问题之二是在传统的沟槽栅功率半导体器件长期使用过程中，在芯片开关过程中体内等离子体会反复冲击沟槽底部的氧化层，沟槽底部的氧化层长期承受较高压力，会影响芯片长期使用的可靠性。
为了解决上述技术问题，本文提供了一种***栅沟槽功率半导体器件。
本文提供了一种***栅沟槽功率半导体器件，包括，设置在半导体衬底上的有源区，有源区包括沿半导体衬底表面向半导体衬底底部方向纵向叠置的第一阱区和第二阱区，其中，第一阱区与第二阱区的多子导电类型互补；一个或多个穿透第一阱区和第二阱区的真栅沟槽；其中，真栅沟槽中设置有***式多晶硅真栅，***式多晶硅真栅包括分别靠近所述沟槽的顶部和底部分离设置的多晶硅主真栅和多晶硅辅真栅，多晶硅主真栅为用于与外部栅极电路相连的控制栅；其中，多晶硅主真栅与多晶硅辅真栅之间，多晶硅主真栅与真栅沟槽的侧壁之间，多晶硅辅真栅与真栅沟槽的侧壁以及与真栅沟槽的底部之间通过层间介质隔离。
本文的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本文而了解。本文的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
图1示出了现有的具有载流子存储层的传统沟槽栅IGBT器件的剖面图；
图2是本文一示例的具有***栅的沟槽功率半导体器件结构示意图；
图3是根据本文一示例的可分别控制的多晶硅主栅金属连接的***栅功率半导体器件结构示意图；
图4是根据本文另一示例的具有假栅***栅的功率半导体器件结构示意图；
图5a是根据本文另一实施例的***假栅浮空的***栅功率半导体器件结构示意图；
图5b是根据本文另一实施例的***假栅接地的***栅功率半导体器件结构示意图；
图6是根据本文第三实施例的采用均匀厚度氧化层的双***栅功率半导体器件结构示意图；
图7是根据本文第三实施例的具有传统假栅的***栅功率半导体器件结构示意图。
附图用来提供对本文的进一步理解，并且构成说明书的一部分，与本文的实施例共同用于解释本文，并不构成对本文的限制。
具体实施方式
为使本文的目的、技术方案和优点更加清楚，以下结合附图对本文作进一步地详细说明，借此对本文如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本文中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本文的保护范围之内。
第一实施例
本实施例提供了一种***栅沟槽功率半导体器件，包括，设置在半导体衬底上的有源区，有源区包括沿半导体衬底表面向半导体衬底底部方向纵向叠置的第一阱区和第二阱区，以及一个或多个通过刻蚀而成的穿透第一阱区和第二阱区的真栅沟槽；其中，第一阱区与第二阱区的多子导电类型互补，其中，真栅沟槽中设置有***式多晶硅真栅，***式多晶硅真栅包括分别靠近所述沟槽的顶部和底部分离设置的多晶硅主真栅和多晶硅辅真栅，多晶硅主真栅为用于与外部栅极电路相连的控制栅，其中，多晶硅主真栅与多晶硅辅真栅之间，多晶硅主真栅与真栅沟槽的侧壁之间，多晶硅辅真栅与真栅沟槽的侧壁以及与真栅沟槽的底部之间通过层间介质隔离。
根据本实施例，多晶硅主真栅与真栅沟槽的侧壁之间的层间介质的厚度小于多晶硅辅真栅与真栅沟槽的侧壁以及与真栅沟槽的底部之间的层间介质的厚度。
根据本实施例，多晶硅主真栅通过金属与外部栅极驱动电路连接，所述多晶硅辅真栅为未与任何电路相连的浮空的栅结构。
根据本实施例，有源区还包括一个或多个通过刻蚀而成的穿透第一阱区和第二阱区的假栅沟槽，其中，假栅沟槽在真栅沟槽的周边与真栅沟槽分隔布置，假栅沟槽中设置有多晶硅假栅。
在一个实施例中，多晶硅假栅为***式多晶硅假栅，***式多晶硅假栅包括分别靠近沟槽的顶部和底部分离设置的多晶硅主假栅和多晶硅辅假栅。
其中，多晶硅主假栅与多晶硅辅假栅之间，多晶硅主假栅与假栅沟槽的侧壁之间，多晶硅辅假栅与假栅沟槽的侧壁以及与假栅沟槽的底部之间通过层间介质隔离。
根据本实施例，多晶硅主假栅为未与任何电路相连的浮空的栅结构，或多晶硅主假栅与发射极金属层连接；多晶硅辅假栅为未与任何电路相连的浮空的栅结构。
根据本实施例，多晶硅主假栅与假栅沟槽的侧壁之间的层间介质的厚度小于多晶硅辅假栅与假栅沟槽的侧壁以及与假栅沟槽的底部之间的层间介质的厚度。
根据本实施例，多晶硅主假栅和多晶硅辅假栅均包括至少两个分离设置的子栅，各子栅之间通过层间介质隔离。
图2为实施例一的具有***栅沟槽功率半导体器件的结构示意图。如图2所示，可以包括：半导体衬底2、N+区3、P+区4、N阱区5、P阱区6、多个条形沟槽***式多晶硅栅(包含多晶硅主栅11、多晶硅辅栅12)、氧化层7、发射极金属层8、阳极P区9、和集电极金属层10。
本说明书中的“半导体衬底2表面内”是指由半导体衬底1表面向下延伸的一定深度的区域，该区域属于半导体衬底2的一部分。
其中，半导体衬底2可以包括半导体元素，例如单晶、多晶或非晶结构的硅或硅锗，也可以包括混合的半导体结构，例如碳化硅、合金半导体或其组合，在此不做限定。在本实施例中的半导体衬底2在一实施方式中采用硅衬底，可采用N型或P型硅衬底，在本实施例中以N型衬底为例进行说明。
多个条形沟槽多晶硅栅，所述条形沟槽多晶硅栅内部分离形成***栅，多个条形沟槽栅极分别位于所述半导体衬底表面向下刻蚀而成的多个沟槽内，并沿所述半导体衬底表面延伸，全部所述条形沟槽多晶硅栅自所述半导体衬底表面向下延伸一次穿越了所述的P阱区和所述N阱区。
具体地，所述***式多晶硅栅***为多晶硅主栅11和多晶硅辅栅12，所述多晶硅主栅11靠近沟槽的顶部，在所述多晶硅辅栅12的上方，所述多晶硅辅栅12靠近沟槽的底部，在所述多晶硅主栅11的下方，位于沟槽下部的多晶硅辅栅12为浮空结构。所述***的多晶硅栅之间的层间介质为氧化物7。***栅的设置 降低了功率半导体器件内的寄生电容，减小了栅极电荷，缩短了米勒平台，降低了芯片开关的损耗，进一步优化了功率半导体器件导通压降和开关损耗的折中关系。
有源区的具体结构和传统沟槽栅功率半导体器件的结构类似，包括N+区3、P+区4、N阱区5和P阱区6。
具体地，N+区3位于有源区的表面。P+区4，其与N+区3接触,且其长度小于条形沟槽多晶硅***栅极之间的距离。P阱区6，其位于P+区4的下方，且其长度等于条形沟槽多晶硅***栅极之间的距离。N阱区5，其位于P阱区5的下方，且其长度等于条形沟槽多晶硅***栅极之间的距离。
在本实施例中，如图2所示，两个N+区3的之间位置设置有浅槽(图中未标示)，浅槽的下方为P+区4。在两个N+区3之间设置浅槽对沟槽功率半导体器件的反偏安全工作区有帮助，尤其对于中高压器件。本实施例中，还设置有载流子存储区N阱区5，且多晶硅***栅沟槽穿越了N阱区域。
所述条形沟槽多晶硅主栅为真栅13，或者为假栅14，如图3，所述假栅沟槽在所述真栅沟槽的周边与所述真栅沟槽分隔布置，所述假栅沟槽中设置有多晶硅假栅。
所述双***的条形沟槽多晶硅假栅的主栅11位于此条形沟槽假栅辅栅12之上，所述主栅栅极浮空或接地，所述假栅结构设置的数量可以为一条或多条。
具体地，本实施例的功率半导体器件结构包含了***式真栅13和假栅14，真栅沟槽中***的多条多晶硅主栅，在一实施例方式中为两条，共同或分别用金属与外部栅极驱动电路相连，如图3，在一实施例方式中为两条***的多晶硅主控制栅15和主控制栅16分别用金属与外部栅极驱动相连，并采用不同的栅极驱动信号对所述的多晶硅主控制栅15和主控制栅16分别进行控制，则可以进一步优化功率半导体器件导通压降和开关损耗的折中关系。
在本实施例中，如图4，在一实施方式中所述***的多晶硅主栅为真栅13，真栅即为沟槽栅功率半导体器件元胞中起控制作用的栅极。如果所述的多晶硅***栅再应用于假栅14，假栅即为沟槽栅功率半导体器件元胞中不起控制作用的栅极，通常浮空或者接地。通过调整假栅的数量，如设置为一条或多条，可以调整芯片的电流密度，有利于调整电路电流密度和短路安全工作区的折中关系，还可以进一步减小寄生参数，使此功率半导体器件适用于高压1200V以上的应用领域。
在本实施例中，所述多晶硅主栅11与沟槽侧壁的氧化层厚度小于等于所述多晶硅辅栅12与沟槽底部以及与侧壁的氧化层厚度，在一实施方式中，多晶硅辅栅12与沟槽底部氧化层厚度为
Figure PCTCN2019121254-appb-000001
且沟槽底部的所述多晶硅辅栅12进行浮空设置，当芯片在开关过程能抵抗芯片体内等离子体的反复冲击，有效的减缓了沟槽底部氧化层所承受的压力，提高了芯片长期使用的可靠性。
本实施例***栅沟槽功率半导体器件的背部结构可以为穿通型、软穿通型或非穿通型结构。软穿通型结构包括N型缓冲层(图中未标出)、阳极P区9和集电极金属层10。其中N型缓冲层位于N型衬底2的下方，阳极P区9位于N型缓冲层的下方，集电极金属层10位于阳极P区9的下方。
本实施例重点上述***栅沟槽功率半导体器件结构仅为该器件一个元胞的基本结构，所谓元胞是指在整个***栅沟槽功率半导体器件上的最小重复单元，即本文提供的***栅沟槽功率半导体器件是由多个上述结构的元胞构成的。
综上所述，本文实施例通过在多个条形沟槽多晶硅栅部分或全部所述条形沟槽多晶硅栅内部分离形成***栅，降低功率半导体器件内寄生电容，减小栅极电荷Qg，缩短米勒平台。根据不同应用需求对芯片***栅电连接方式进行优化，通过栅极驱动控制，有效改善芯片导通压降和开关损耗的折中关系。在沟槽底部设置较厚的氧化层，并对沟槽底部***的多晶硅辅栅进行浮空设置，降低沟槽底部氧化层在阻断态所承受的电压力及在开关过程中等离子体的反复冲击，提高芯片长期使用的可靠性。
第二实施例
图5a是根据本文实施例二的双***假栅浮空的***栅功率半导体器件结构示意图，图5b是根据本文实施例二的双***假栅接地的***栅功率半导体器件结构示意图。如图5a所示，可以包括：半导体衬底2、N+区3、P+区4、N阱区5、P阱区6、条形沟槽双***的假栅17(包含多晶硅主假栅171和多晶硅辅假栅172)、条形沟槽***的真栅13(包含多晶硅主栅131和多晶硅辅栅132)、氧化层7、发射极金属层7、阳极P区9、和集电极金属层10。多晶硅主假栅171为浮空结构，可以改变沟槽功率半导体器件的输入和输出电容，从而调解沟槽功率半导体器件的开发速度和栅电阻对开关速度的控制。
如图5b所示，可以包括：半导体衬底2、N+区3、P+区4、N阱区5、P阱 区6、条形沟槽双***的假栅17(包含多晶硅主假栅171和多晶硅辅假栅172)、条形沟槽***的真栅13(包含多晶硅主栅131和多晶硅辅栅132)、氧化层7、发射极金属层8、阳极P区9、和集电极金属层10。多晶硅主假栅171为接地结构，N+区3、P+区4、多晶硅主假栅171与发射极金属层8连接，显著降低了沟槽栅功率半导体器件的导通压降，改变沟槽功率半导体器件的输入和输出电容，从而调解沟槽功率半导体器件的开发速度和栅电阻对开关速度的控制。同时，将假栅的栅电极与发射极金属层相接触，可使假栅实现良好接地。
本实施例所述***的多晶硅栅之间的层间介质为氧化物7。***栅的设置变相的降低了沟槽栅的密度，降低了功率半导体器件内有害的寄生效应，减小了栅极电荷，缩短了米勒平台，降低了芯片开关的损耗，进一步优化了功率半导体器件导通压降和开关损耗的折中关系。
本实施例所述条形沟槽多晶硅主栅为真栅13，或者为假栅14，如图3，所述假栅沟槽在所述真栅沟槽的周边与所述真栅沟槽分隔布置，所述假栅沟槽中设置有多晶硅假栅。
本实施例所述双***的条形沟槽多晶硅假栅的主栅171位于此条形沟槽假栅辅栅172之上，所述假栅的主栅171栅极浮空或接地，所述假栅结构设置的数量可以为一条或多条。
具体地，***栅功率半导体器件假栅可以采用双***栅，即假栅仅***为上下栅，分别为多晶硅主假栅171和多晶硅辅假栅172，所述多晶硅主假栅171在所述多晶硅辅假栅172的上方，所述多晶硅辅假栅172在所述多晶硅主假栅171的下方，位于沟槽下部的多晶硅辅假栅172为浮空结构。
所述的多晶硅***栅应用于假栅17，通过调整假栅的数量，如设置为一条或多条，可以调整芯片的电流密度，有利于调整电路电流密度和短路安全工作区的折中关系，还可以进一步减小寄生参数，使此功率半导体器件适用于高压1200V以上的应用领域。
在本实施例中，所述多晶硅主栅(171,131)沟槽侧壁的氧化层厚度小于等于所述多晶硅辅栅(172,132)沟槽底部与侧壁的氧化层厚度，在一实施方式中，多晶硅辅栅(172,132)沟槽底部氧化层厚度为
Figure PCTCN2019121254-appb-000002
且沟槽底部的所述多晶硅辅栅(172,132)进行浮空设置，当芯片在开关过程能抵抗芯片体内等离子 体的反复冲击，有效的减缓了沟槽底部氧化层所承受的压力，提高了芯片长期使用的可靠性。
本实施例***栅沟槽功率半导体器件的背部结构可以为穿通型、软穿通型或非穿通型结构。软穿通型结构包括N型缓冲层(图中未标出)、阳极P区9和集电极金属层10。其中N型缓冲层位于N型衬底2的下方，阳极P区9位于N型缓冲层的下方，集电极金属层10位于阳极P区9的下方。
本实施例重点上述***栅沟槽功率半导体器件结构仅为该器件一个元胞的基本结构，所谓元胞是指在整个***栅沟槽功率半导体器件上的最小重复单元，即本文提供的***栅沟槽功率半导体器件是由多个上述结构的元胞构成的。
综上所述，本文实施例通过在多个条形沟槽多晶硅栅真栅进行分离形成***栅，部分条形沟槽多晶硅假栅内部上下分离形成***栅，降低功率半导体器件内寄生电容，减小栅极电荷Qg,缩短米勒平台。根据不同应用需求对芯片***栅电连接方式进行优化，多晶硅假栅的主栅可以根据需要采取浮空结构或接地结构，有效改善芯片导通压降和开关损耗的折中关系。在沟槽底部设置较厚的氧化层，并对沟槽底部***的多晶硅辅栅进行浮空设置，降低沟槽底部氧化层在阻断态所承受的电压力及在开关过程中等离子体的反复冲击，提高芯片长期使用的可靠性。
第三实施例
图6是根据本文另一实施例的采用均匀厚度氧化层的双***栅功率半导体器件结构示意图，图6是根据本文实施例三的***栅功率半导体器件结构示意图。如图6所示，可以包括：半导体衬底2、N+区3、P+区4、N阱区5、P阱区6、条形沟槽***式真栅13(包含多晶硅主栅131和多晶硅辅栅132)、条形沟槽双***的假栅18(包含多晶硅主假栅181和多晶硅辅假栅182)、氧化层7、发射极金属层8、阳极P区9、和集电极金属层10。多晶硅主假栅181均为浮空结构，改变沟槽功率半导体器件的输入和输出电容，从而调解沟槽功率半导体器件的开发速度和栅电阻对开关速度的控制。
图7是根据本文另一实施例的具有传统假栅的***栅功率半导体器件结构示意图，图7是根据本文实施例三的***栅功率半导体器件结构示意图。如图7所示，可以包括：半导体衬底2、N+区3、P+区4、N阱区5、P阱区6、条形沟槽 ***的真栅13(包含多晶硅主栅和多晶硅辅栅)、条形沟槽不***的传统假栅19、氧化层7、发射极金属层8、阳极P区9、和集电极金属层10。多晶硅假栅19为浮空结构，改变了沟槽功率半导体器件的输入和输出电容，从而调解沟槽功率半导体器件的开发速度和栅电阻对开关速度的控制。
本实施例条形沟槽双***的假栅的主栅181与沟槽侧壁的氧化层厚度等于所述多晶硅辅栅182与沟槽底部以及与侧壁的氧化层厚度，传统假栅19沟槽侧壁的氧化层厚度采用均匀厚度氧化层的结构，在实施例中，多晶硅假栅为一体式多晶硅假栅。在一实施方式中，多晶硅沟槽底部氧化层厚度为
Figure PCTCN2019121254-appb-000003
且沟槽底部的所述多晶硅栅进行浮空设置，当芯片在开关过程能抵抗芯片体内等离子体的反复冲击，有效的减缓了沟槽底部氧化层所承受的压力，提高了芯片长期使用的可靠性。
本实施例所述***的多晶硅栅之间的层间介质为氧化物7。***栅的设置变相的降低了沟槽栅的密度，降低了功率半导体器件内有害的寄生效应，减小了栅极电荷，缩短了米勒平台，降低了芯片开关的损耗，进一步优化了功率半导体器件导通压降和开关损耗的折中关系。
本实施例所述条形沟槽分列式多晶硅主栅为真栅13，或者为假栅18，或者为传统假栅19，如图3，所述假栅沟槽在所述真栅沟槽的周边与所述真栅沟槽分隔布置，所述假栅沟槽中设置有多晶硅假栅。
本实施例***栅沟槽功率半导体器件的背部结构可以为穿通型、软穿通型或非穿通型结构。软穿通型结构包括N型缓冲层(图中未标出)、阳极P区9和集电极金属层10。其中N型缓冲层位于N型衬底2的下方，阳极P区9位于N型缓冲层的下方，集电极金属层10位于阳极P区9的下方。
本实施例重点上述***栅沟槽功率半导体器件结构仅为该器件一个元胞的基本结构，所谓元胞是指在整个***栅沟槽功率半导体器件上的最小重复单元，即本文提供的***栅沟槽功率半导体器件是由多个上述结构的元胞构成的。
综上所述，本文实施例通过在多个条形沟槽多晶硅栅真栅进行分离形成***栅，部分条形沟槽多晶硅假栅内部上下分离形成***栅，降低功率半导体器件内寄生电容，减小栅极电荷Qg,缩短米勒平台。多晶硅假栅的主栅根据需要采取浮空结构，能有效改善芯片导通压降和开关损耗的折中关系。本实施例条形沟槽假 栅的主栅沟槽侧壁的氧化层厚度等于所述多晶硅辅栅沟槽底部与侧壁的氧化层厚度，采用均匀厚度氧化层的结构，并对沟槽多晶硅栅进行浮空设置，降低沟槽底部氧化层在阻断态所承受的电压力及在开关过程中等离子体的反复冲击，提高芯片长期使用的可靠性。
此外，在其他实施例中，所述沟槽多晶硅***栅极，也可应用于其他功率半导体器件，在一实施方式中用于MOSFET。
与在一些情况下相比，本文的一个或多个实施例可以具有如下优点：
1、本文通过把传统的沟槽多晶硅栅极设置为***式多晶硅栅，在沟槽栅底部设置较厚的氧化层，来减小寄生电容，降低功率半导体器件内有害的寄生效应，减小栅极电荷Qg，缩短米勒平台，从而降低了开关损耗。
2、本文通过把传统的沟槽多晶硅栅极的假栅也设置为***式多晶硅栅，并设置为1条或多条，从而优化了功率半导体器件电流密度与短路安全工作区的折中关系。
3、本文通过沟槽中***的各多晶硅主真栅用金属与外部栅极驱动电路相连，采用不同的栅极驱动信号对***的主真栅分别进行控制，进一步优化了功率半导体器件导通压降和开关损耗的折中关系。
4、本文通过在各***的多晶硅栅之间填充或生长氧化物作为层间介质，设置所述多晶硅主栅与侧壁的氧化层厚度小于多晶硅辅栅与沟槽侧壁以及与沟槽底部的氧化层厚度，并对沟槽底部的多晶硅辅栅进行浮空设置，有效的减缓了沟槽底部氧化层所承受的压力，提高了芯片长期使用的可靠性。
5、本文通过对条形沟槽内多晶硅栅进行***形成***栅，减小了寄生电容，进而采用不同电连接和设置氧化层厚度，以实现芯片性能的总体优化。
虽然本文公开的实施方式如上，但所述的内容只是为了便于理解本文而采用的实施方式，并非用以限定本文。任何本文所述技术领域内的技术人员，在不脱离本文所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，本文的保护范围并不局限于文中公开的特定实施例，而是包括落入权利要求范围内的所有技术方案。

Claims (10)

  1. 一种功率半导体器件，其中，包括，设置在半导体衬底上的有源区，所述有源区包括沿半导体衬底表面向半导体衬底底部方向纵向叠置的第一阱区和第二阱区，其中，所述第一阱区与所述第二阱区的多子导电类型互补；一个或多个穿透所述第一阱区和所述第二阱区的真栅沟槽；其中，所述真栅沟槽中设置有***式多晶硅真栅，所述***式多晶硅真栅包括分别靠近所述沟槽的顶部和底部分离设置的多晶硅主真栅和多晶硅辅真栅，所述多晶硅主真栅为用于与外部栅极驱动电路相连的控制栅；其中，所述多晶硅主真栅与所述多晶硅辅真栅之间，所述多晶硅主真栅与所述真栅沟槽的侧壁之间，所述多晶硅辅真栅与所述真栅沟槽的侧壁以及与所述真栅沟槽的底部之间通过层间介质隔离。
  2. 根据权利要求1所述的功率半导体器件，其中，所述多晶硅主真栅和所述多晶硅辅真栅均包括至少两个分离设置的子栅，各所述子栅之间通过层间介质隔离。
  3. 根据权利要求1所述的功率半导体器件，其中，所述多晶硅主真栅与所述真栅沟槽的侧壁之间的层间介质的厚度小于所述多晶硅辅真栅与所述真栅沟槽的侧壁以及与所述真栅沟槽的底部之间的层间介质的厚度。
  4. 根据权利要求1所述的功率半导体器件，其中，所述多晶硅主真栅通过金属与外部栅极驱动电路连接，所述多晶硅辅真栅为未与任何电路相连的浮空的栅结构。
  5. 根据权利要求1至4中任一项所述的功率半导体器件，其特征在于，还包括：一个或多个穿透所述第一阱区和所述第二阱区的假栅沟槽，其中，所述假栅沟槽在所述真栅沟槽的周边与所述真栅沟槽分隔布置，所述假栅沟槽中设置有多晶硅假栅。
  6. 根据权利要求5所述的功率半导体器件，其中，所述多晶硅假栅为***式多晶硅假栅，所述***式多晶硅假栅包括分别靠近所述沟槽的顶部和底部分离设置的多晶硅主假栅和多晶硅辅假栅；其中，所述多晶硅主假栅与所述多晶硅辅假栅之间，所述多晶硅主假栅与所述假栅沟槽的侧壁之间，所述多晶硅辅假栅与所述假栅沟槽的侧壁以及与所述假栅沟槽的底部之间通过层间介质隔离。
  7. 根据权利要求5所述的功率半导体器件，其中，所述多晶硅假栅为一体 式多晶硅假栅。
  8. 根据权利要求6所述的功率半导体器件，其中，所述多晶硅主假栅为未与任何电路相连的浮空的栅结构，或所述多晶硅主假栅与发射极金属层连接；所述多晶硅辅假栅为未与任何电路相连的浮空的栅结构。
  9. 根据权利要求6所述的功率半导体器件，其中，所述多晶硅主假栅与所述假栅沟槽的侧壁之间的层间介质的厚度小于所述多晶硅辅假栅与所述假栅沟槽的侧壁以及与所述假栅沟槽的底部之间的层间介质的厚度。
  10. 根据权利要求6所述的功率半导体器件，其中，所述多晶硅主假栅和所述多晶硅辅假栅均包括至少两个分离设置的子栅，各所述子栅之间通过层间介质隔离。
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