WO2021088023A1 - 一种电子设备及数字芯片 - Google Patents

一种电子设备及数字芯片 Download PDF

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Publication number
WO2021088023A1
WO2021088023A1 PCT/CN2019/116810 CN2019116810W WO2021088023A1 WO 2021088023 A1 WO2021088023 A1 WO 2021088023A1 CN 2019116810 W CN2019116810 W CN 2019116810W WO 2021088023 A1 WO2021088023 A1 WO 2021088023A1
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signal
digital
analog
cancellation
sampling
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PCT/CN2019/116810
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English (en)
French (fr)
Inventor
李晶
李兴文
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华为技术有限公司
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Priority to PCT/CN2019/116810 priority Critical patent/WO2021088023A1/zh
Publication of WO2021088023A1 publication Critical patent/WO2021088023A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • This application relates to the technical field of DPD correction, and in particular to an electronic device and a digital chip.
  • Digital pre-distortion (DPD) technology can eliminate non-linear products caused by power amplifier (PA), so it is often used in communication equipment.
  • the non-linear product includes a signal whose frequency point is different from that of the target signal, and the non-linear product is not conducive to improving the signal quality of the communication signal transmitted by the communication device.
  • the baseband chip of the communication device may be coupled with the transmission path of the communication device through a transmission path.
  • the transmission path may perform digital-to-analog conversion and power amplification on the digital baseband signal output by the baseband chip to obtain an analog baseband signal, which can then be passed through
  • the transmit path transmits the analog baseband signal. Since nonlinear products may be generated in the transmission path during power amplification, the baseband chip can obtain the sampling information of the analog baseband signal through the feedback path, and then perform DPD correction on the digital baseband signal to be sent based on the sampling information to offset subsequent power amplification Non-linear products produced during the period.
  • the current DPD correction has higher hardware requirements for the feedback path.
  • the feedback path cannot change the signal-to-noise ratio of the analog baseband signal, and for example, the feedback path cannot introduce other non-linear products that will affect the DPD correction, etc., which brings a lot of inconvenience to the design of the feedback path.
  • the present application provides an electronic device and a digital chip, which are used to reduce the hardware requirements for the feedback path in the DPD correction, which is conducive to the popularization of the DPD correction.
  • an embodiment of the present application provides an electronic device.
  • the electronic device mainly includes a digital chip, a transmission path, a feedback path, and a cancellation path.
  • the digital chip is connected to the input end of the transmission path, the output end of the feedback path, and The input end of the cancellation path is coupled, the input end of the feedback path is coupled with the output end of the transmission path, and the output end of the cancellation path is coupled with the input end of the feedback path.
  • the digital chip can output a digital output signal to the transmission path; the transmission path can convert the digital output signal into an analog output signal, and then output the analog output signal; the feedback path can obtain the analog sampling signal of the analog output signal, according to the analog sampling signal Obtain a digital sampling signal, and feed the digital sampling signal back to the digital chip; the digital chip can also perform DPD correction on the first digital signal to be sent based on the digital sampling signal, and output the DPD-corrected first digital signal as a digital output signal, and , Generate a digital cancellation signal according to the first digital signal, and send the digital cancellation signal to the cancellation path; the cancellation path can convert the digital cancellation signal corresponding to the first digital signal into an analog cancellation signal, and convert the analog cancellation signal
  • the cancellation signal is provided to the feedback path, and the analog cancellation signal is used to reduce the signal strength of the target sampling signal in the analog sampling signal.
  • the digital chip in the embodiment of this application can generate a digital cancellation signal, convert the cancellation signal into an analog cancellation signal through the cancellation path, and the cancellation path inputs the analog cancellation signal into the feedback path, so that the analog cancellation signal and the input feedback path
  • the analog sampling signal is mixed to reduce the signal strength of the target sampling signal in the analog sampling signal, thereby helping to reduce the requirements for the dynamic range of the hardware in the feedback path.
  • the signal strength of the nonlinear product is positively correlated with the strength of the input action signal.
  • the embodiment of the present application reduces the signal strength of the target sample signal in the analog sample signal through the analog cancellation signal, which is beneficial to reduce the feedback path generated when the target sample signal is amplified.
  • the non-linear product of which helps to reduce the linearity requirements of the hardware in the feedback path.
  • the embodiments of the present application are beneficial to reduce the hardware requirements for the feedback path.
  • the signal strength of the analog cancellation signal is less than the signal strength of the target sampling signal, and the phase difference between the analog cancellation signal and the target sampling signal is 180 degrees.
  • the analog cancellation signal and the analog sampling signal are mixed, that is, the two analog signals are superimposed. Since the difference between the phase of the analog cancellation signal and the phase of the target sampling signal is 180 degrees, the signal strengths of the two analog signals cancel each other out.
  • the signal strength of the analog cancellation signal is less than the signal strength of the target sampling signal, the analog cancellation signal does not completely cancel the target sampling signal.
  • the input signal of the feedback path 300 still retains the target sampling signal with reduced signal strength.
  • the digital chip can still use the digital sampling signal for DPD correction.
  • the electronic device further includes a first coupler and a second coupler; the feedback path is coupled to the output end of the transmission path through the first coupler, and one input end of the second coupler is coupled to the first coupler.
  • the other input end of the second coupler is coupled to the cancellation path, and the output end of the second coupler is coupled to the feedback path; among them, the first coupler can transmit part of the analog output signal as an analog sampling signal To the second coupler; the second coupler can receive the analog sampling signal and the analog cancellation signal, and output the mixed signal of the analog sampling signal and the analog cancellation signal to the feedback path.
  • the feedback path includes a first amplifier, a mixer, a local oscillator signal source, and an analog-to-digital converter;
  • the mixer is respectively coupled with the first amplifier, the analog-to-digital converter and the local oscillator signal source, and the analog-to-digital converter and Digital chip coupling; among them, the first amplifier can receive the mixed signal of the analog sampling signal and the analog cancellation signal, and power amplify the mixed signal to obtain the second analog signal;
  • the local oscillator signal source can generate the local oscillator signal;
  • the mixer It can receive the second analog signal and the local oscillator signal, and use the local oscillator signal to mix the second analog signal to obtain the third analog signal;
  • the analog-to-digital converter can perform analog-to-digital conversion on the third analog signal to obtain the above-mentioned digital sampling signal .
  • the transmission path includes a first digital-to-analog converter and a second amplifier; the first digital-to-analog converter is respectively coupled to the digital chip and the second amplifier; wherein, the first digital-to-analog converter can output the digital output of the digital chip
  • the signal undergoes digital-to-analog conversion to obtain a fourth analog signal; the second amplifier can perform power amplification on the fourth analog signal to obtain an analog output signal.
  • the cancellation path includes a second digital-to-analog converter, the input terminal of the second digital-to-analog converter is coupled with the digital chip, and the output terminal of the second digital-to-analog converter is coupled with the feedback path; the second digital-to-analog converter may Convert the digital cancellation signal to an analog cancellation signal.
  • the embodiments of the present application provide a digital chip, which can be applied to the electronic device provided in any possible implementation manner in the above-mentioned first aspect, and the digital chip includes: a digital predistortion DPD circuit , A calculation circuit and a cancellation signal generation circuit, the calculation circuit is respectively coupled with the DPD circuit and the cancellation signal generation circuit; wherein the calculation circuit can update the cancellation coefficient of the cancellation signal generation circuit according to the first digital signal to be sent;
  • the cancellation signal generation circuit is coupled with the cancellation path, and can generate a digital cancellation signal according to the updated cancellation coefficient and the first digital signal to be sent, and output the digital cancellation signal to the cancellation path; the DPD circuit can be based on the received
  • the digital sampling signal is subjected to predistortion processing on the first digital signal to be sent, and the predistorted first digital signal is output to the transmission path as the next digital output signal.
  • the digital chip may be a chip dedicated to DPD correction.
  • the digital chip can be coupled with a signal source chip that does not have the DPD correction function, and the output signal of the signal source chip can be input to the digital chip as the first digital signal, and the digital chip performs DPD correction on the first digital signal input by the signal source chip .
  • the digital chip may also include a main signal generating circuit, which is respectively coupled with the DPD circuit, the calculation circuit, and the cancellation signal generating circuit; the main signal generating circuit may generate the first digital signal .
  • the calculation circuit may update the cancellation coefficient in the following manner: obtain M-1 first digital signals that are M-1 sampling points before the current sampling point, and according to M- The time of 1 sampling point is from late to early, and the digital sampling signal corresponding to the (M-1)/2th transmitted first digital signal is obtained, and M is an odd number greater than 1, according to the waiting time of the current sampling point.
  • the first digital signal sent, the M-1 sent first digital signal, and the digital sampling signal corresponding to the (M-1)/2th sent first digital signal update the M of the cancellation signal generating circuit Cancellation coefficients.
  • the cancellation signal generating circuit may be a digital filter.
  • the cancellation coefficient may be the filter coefficient of the digital filter, and M may be the order of the digital filter.
  • the updated M cancellation coefficients may satisfy the following formula:
  • Ch(i+1) M-1 to Ch(i+1) 0 are the updated M cancellation coefficients
  • Ch(i) M-1 to Ch(i) 0 are the M cancellation coefficients before the update Coefficient
  • i is the number of times M cancellation coefficients have been updated
  • ⁇ is the iteration step factor of the cancellation signal generating circuit
  • D 1 (n) is the current first digital signal to be sent
  • D 1 [n-M+1] is the M-1th transmitted first digital signal
  • It is the digital sampling signal corresponding to the (M-1)/2th transmitted first digital signal.
  • the digital cancellation signal can satisfy the following formula:
  • D x (n) is the digital cancellation signal corresponding to the first digital signal to be sent at the current sampling point
  • Ch m is the m+1th cancellation coefficient
  • m is taken from [0, M-1] Integer
  • D 1 (nm) is the mth first digital signal sent.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the application.
  • FIG. 2a is a schematic diagram of a first digital signal provided by an embodiment of this application.
  • 2b is a schematic diagram of an analog output signal provided by an embodiment of the application.
  • FIG. 2c is a schematic diagram of a digital cancellation signal provided by an embodiment of this application.
  • Figure 2d is a schematic diagram of a mixed signal provided by an embodiment of the application.
  • the "coupling" in the embodiments of the present application refers to the energy transfer relationship.
  • the coupling of A and B means that energy can be transferred between A and B, which is reflected in the circuit connection relationship, that is, A and B B can be electrically connected directly or indirectly through other conductors or circuit elements.
  • Power amplifier is a common analog signal processing method, which can generally be realized by an amplifier. However, in the process of power amplification, some non-linear products may be produced. For example, if the amplifier performs power amplification on the target analog signal at frequency A, the output signal of the power amplifier includes not only the target analog signal at frequency A and after power amplification, but also signals at other frequency points. These signals at other frequency points can be understood as non-linear products of power amplification.
  • Non-linear products will have a negative impact on the signal quality of the output signal of the amplifier. Therefore, digital pre-distortion (DPD) technology appears.
  • DPD digital pre-distortion
  • the DPD technology can reduce the signal strength of the non-linear products in the output signal of the power amplifier.
  • FIG. 1 exemplarily shows a schematic diagram of an electronic device architecture to which an embodiment of the present application is applicable.
  • the electronic device may be a device with a signal transmission function, such as a base station or a terminal.
  • the electronic device mainly includes a digital chip 100, a transmission path 200, and a feedback path 300.
  • the digital chip 100 is respectively coupled with the transmission path 200 and the feedback path 300
  • the feedback path 300 is coupled with the transmission path 200.
  • the digital chip 100 may be a chip with a DPD function and capable of outputting a digital output signal D o .
  • the digital chip 100 may be a baseband chip.
  • the digital output signal D o of the digital chip 100 may be a digital baseband signal.
  • the transmission path 200 can convert the digital output signal D o of the digital chip 100 into an analog output signal A o , and output the analog output signal A o .
  • the transmission path 200 may include a first digital-to-analog converter (DAC) 201 and a second amplifier 202.
  • the input terminal of the first digital-to-analog converter 201 is coupled to the digital chip 100, and the output terminal of the first digital-to-analog converter 201 is coupled to the input terminal of the second amplifier 202.
  • the first digital-to-analog converter 201 can perform digital-to-analog conversion on the digital output signal D o output by the digital chip 100 to obtain a fourth analog signal A 4 .
  • the second amplifier 202 can amplify the power of the fourth analog signal A 4 to obtain the analog output signal A o .
  • the electronic device may further include a transceiver channel 400.
  • the second amplifier 202 can output the analog output signal A o to the transceiving path 400, and the transceiving path 400 transmits the analog output signal A o .
  • the transceiver path 400 may include a unidirectional isolator 401, a bidirectional filter 402, and an antenna 403.
  • the one-way isolator 401 can prevent the signal from being output to the transmission path 200 from the transceiver channel 400, and the two-way filter 402 can filter the signal to be transmitted and the signal received by the antenna 403, and the antenna 403 can receive or transmit the signal.
  • the analog output signal A o output by the second amplifier 202 may be transmitted to the bidirectional filter 402 through the unidirectional isolator 401, and after being filtered by the bidirectional filter 402, it is transmitted by the antenna 403.
  • the analog output signal A o output by the second amplifier 202 includes both the amplified fourth analog signal, that is, The target analog signal also includes non-linear products.
  • the digital chip 100 is also coupled with the feedback path 300, and the feedback path 300 is coupled with the transmission path 200.
  • the feedback path 300 may be coupled with the transmission path 200 through the first coupler 600.
  • the input terminal of the first coupler 600 is coupled with the transmission path 200
  • the output terminal of the first coupler 600 is coupled with the feedback path 300.
  • the first coupler 600 may be directed to transport path 200 outputs the analog output signal A o, in which part of A T signal transmitted as an analog signal sampled analog output signal A o to another portion of the feedback path 300, the analog output signal A o is The analog output signal is output to the transmission and reception path 400. It should be understood that the first coupler 600 divides the analog output signal A o into two parts from the perspective of signal power, that is, the frequency, phase, and waveform of the two parts of the analog output signal A o are the same, and the difference lies only in the two parts of the analog output signal A o. The signal strength of the output signal A o may be different.
  • the feedback path 300 can obtain the digital sampling signal D T according to the analog sampling signal AT of the analog output signal A o , and feedback the digital sampling signal D T to the digital chip 100.
  • the feedback path 300 includes a first amplifier 304, a mixer 302, a local oscillator signal source 303 and an analog-to-digital converter (ADC) 301.
  • ADC analog-to-digital converter
  • the input terminal of the first amplifier 304 is coupled with the transmission path 200 (also can be understood as coupling with the transmission path 200 through the first coupler 600), and the output terminal of the first amplifier 304 is coupled with an input terminal of the mixer 302,
  • the other input end of the mixer 302 is coupled to the local oscillator signal source 303, the output end of the mixer 302 is coupled to the input end of the analog-to-digital converter 301, and the output end of the analog-to-digital converter 301 is coupled to the digital chip 100.
  • the first amplifier 304 may perform power amplification on the analog sampling signal AT to obtain the second analog signal A 2 .
  • the local oscillator signal source 303 can generate a local oscillator signal Lo.
  • the mixer 302 may receive the second analog signal A 2 from the first amplifier 304, receive the local oscillator signal Lo from the local oscillator signal source 303, and mix the second analog signal A 2 according to the local oscillator signal Lo to obtain the third Analog signal A 3 .
  • the third analog signal A 3 obtained by mixing has the same frequency as the digital output signal D o of the digital chip 100.
  • the analog-to-digital converter 301 can perform analog-to-digital conversion on the third analog signal A 3 to obtain a digital sampling signal D T.
  • the analog-to-digital converter 301 provides the digital sampling signal D T to the digital chip 100 so that the digital chip 100 can perform DPD correction according to the digital sampling signal D T.
  • the digital samples may be sampled signal D T 100 transmitting information to a digital chip analog output signal A o, for example, the analog output signal A o product nonlinear frequency information, signal strength information and the like.
  • the digital chip 100 may be corrected DPD first digital signal to be transmitted next D 1 T D digital signal samples, to offset subsequent non-linear power amplification product generated in the process.
  • the first digital signal D 1 can be understood as a digital signal that has not been DPD corrected. After the digital chip 100 completes the DPD correction on the first digital signal D 1 , it can output the DPD corrected first digital signal D 1 as the digital output signal D o .
  • DETAILED digital implementation of the first chip 100 for digital signal D 1 DPD correction may refer to the prior art, and is not repeated.
  • a first digital signal D 1 corresponding to the digital output signal D O, D is the first digital signal by the DPD than n 1, via the transmission path 200 after converted into an analog output signal A o.
  • the feedback path 300 converts the analog sampling signal AT of the analog output signal A o into a digital sampling signal D T
  • the digital sampling signal D T is provided to the digital chip 100 so that the digital chip 100 can be based on the digital sampling signal D T subsequent first digital signal DPD correction for D 1.
  • the current sampling point is sampling point n
  • the first digital signal to be sent is D 1 (n)
  • D 1 (n) After the first digital signal D 1 (n) is corrected by DPD, a digital output signal D o (n) is obtained.
  • the digital output signal D o (n) is converted into an analog output signal A o (n) via the transmission path 200.
  • the feedback path 300 obtains the analog sampling signal AT (n) of the analog output signal A o (n), and converts the analog sampling signal AT (n) into a digital sampling signal D T (n).
  • the feedback path 300 provides the digital sampling signal D T (n) to the digital chip 100 so that the digital chip 100 can use the digital sampling signal D T (n) to correct the subsequent DPD of the first digital signal D 1.
  • the digital chip 100 may use the digital sampling signal D T (n) to perform DPD correction on the first digital signal D 1 (n+k) at the subsequent k-th sampling point (that is, the sampling point n+k).
  • k can be any integer greater than or equal to 1, which is not limited in the embodiment of the present application.
  • the feedback path 300 should try to avoid introducing additional nonlinear products, and the feedback path 300 should not change the signal to noise ratio (SNR) of the analog sampling signal AT. Therefore, it is often necessary to use high-dynamic and high-linearity hardware to form the feedback path 300 at present.
  • high dynamic refers to the large dynamic range between the maximum operating power and minimum operating power of the hardware
  • high linearity refers to the small nonlinear products or nonlinearities that can be generated after the signal passes through the hardware. The product will not affect the accuracy of DPD calibration.
  • an embodiment of the present application provides an electronic device and a digital chip 100 that mix the analog sampling signal AT with the analog cancellation signal A x to reduce the signal strength of the target sampling signal in the analog sampling signal AT, thereby It is beneficial to reduce the hardware requirements for the feedback path 300.
  • the target sampling signal can be understood as the sampling signal corresponding to the target analog signal in the analog output signal A o.
  • the electronic device further includes a cancellation path 500, one end of the cancellation path 500 is coupled to the digital chip 100, and the other end is coupled to the feedback path 300.
  • the digital chip 100 may also generate a digital cancellation signal D x according to the first digital signal D 1 to be sent, and send the digital cancellation signal D x to the cancellation path 500.
  • the digital chip 100 may generate a digital cancellation signal D x according to the first digital signal D 1 to be sent and the received digital sampling signal D T.
  • the digital chip 100 can be D 1 (n) according to the first digital signal and the received digital sampling signal D T ( nh) Generate a digital cancellation signal D x (n), where the digital sampling signal D T (nh) can be understood as the hth sampling point before the current sampling point n, that is, the sampling point nh, which is to be sent The digital sampling signal D T (nh) corresponding to the first digital signal D 1 (nh), where h is an integer greater than or equal to 1.
  • the correspondence between the first digital signal D 1 (nh) and the digital sampling signal D T (nh) can be understood as that after the digital chip 100 performs DPD correction on the first digital signal D 1 (nh), the digital Output signal D o (nh).
  • the transmission path 200 converts the digital output signal D o (nh) to obtain the analog output signal A o (nh).
  • the feedback path 300 obtains the analog sampling signal AT (nh) of the analog output signal A o (nh), and then obtains the digital sampling signal D T corresponding to the first digital signal D 1 (nh) according to the analog sampling signal AT (nh) (nh).
  • the cancellation path 500 can convert the digital cancellation signal D x (n) corresponding to the first digital signal D 1 (n) into an analog cancellation signal A x (n), and provide the analog cancellation signal A x (n) Give the feedback path 300.
  • the signal strength of the target sampling signal in the sampling signal AT (n) corresponding to the first digital signal D 1 (n) in the feedback path 300 can be reduced by the analog cancellation signal A x (n).
  • the corresponding relationship between the first digital signal D 1 (n) and the sampling signal AT (n) can be understood as that after the digital chip performs DPD correction on the first digital signal D 1 (n), it sends the signal to the transmission path 200
  • the digital output signal D o (n) is output.
  • Transmission path 200 to the digital output signal D o (n) into an analog output signal A o (n) the feedback path 300 fetches the analog output signal A o (n) of the sampling signal A T (n) from a transmission path 200, i.e.
  • the cancellation path 500 includes a second digital-to-analog converter (DAC) 501.
  • the input terminal of the second digital-to-analog converter 501 is coupled to the digital chip 100, and the output terminal of the second digital-to-analog converter 501 is connected to the feedback path 300. coupling.
  • the second digital-to-analog converter 501 can perform digital-to-analog conversion on the digital cancellation signal D x (n), and convert the digital cancellation signal D x (n) into an analog cancellation signal A x (n).
  • the cancellation path 500 may be coupled to the feedback path 300 through the second coupler 700.
  • the input terminal of the second coupler 700 is respectively coupled with the output terminal of the first coupler 600 and the cancellation path 500, and the output terminal of the second coupler 700 is coupled with the feedback path 300.
  • the second coupler 700 can receive the analog sampling signal A T (n) of the analog output signal A o (n) provided by the first coupler 600 and the analog cancellation signal A x (n), and output the analog to the feedback path 300 A mixed signal of the sampled signal A T (n) and the analog cancellation signal A x (n).
  • the analog cancellation signal A x (n) can reduce the signal strength of the target sample signal in the analog sample signal A T (n).
  • the signal strength of the analog cancellation signal A x (n) is less than the signal strength of the target sampling signal in the analog sampling signal AT (n), and the phase of the analog cancellation signal A x (n) is equal to that of the analog sampling signal.
  • the phase difference of the target sampling signal in the signal AT (n) is 180 degrees.
  • the analog cancellation signal A x (n) and the analog sampling signal AT (n) are mixed, that is, the two analog signals are superimposed. Since the difference between the phase of the analog cancellation signal A x (n) and the phase of the target sampling signal is 180 degrees, the signal strengths of the two analog signals cancel each other out. In addition, since the signal strength of the analog cancellation signal A x (n) is less than the signal strength of the target sampling signal, the analog cancellation signal A x (n) does not completely cancel the target sampling signal.
  • the mixed signal output by the second coupler 700 The (input signal of the feedback path 300) still retains the target sampling signal with reduced signal strength, so that the digital chip 100 can still use the digital sampling signal D T (n) to perform DPD correction.
  • FIGS. 2a to 2d exemplarily show the first digital signal, the analog output signal, the digital cancellation signal, and the mixed signal in sequence.
  • the horizontal direction represents the frequency domain
  • the vertical direction represents the signal strength.
  • Fig. 2b shows the analog output signal A o in the form of a digital signal, which actually represents the analog output signal A o .
  • Figure 2d is the same, showing the mixed signal in the form of a digital signal.
  • the first digital signal D 1 (n) is located at frequency point a and frequency point b.
  • the analog output signal A o (n) corresponding to the first digital signal D 1 (n) may be as shown in Fig. 2b.
  • the signal within the dashed box represents the amplified target signal
  • the signal outside the dashed box represents the nonlinear product.
  • the amplified target signal is located at frequency point a and frequency point b. Signals also appear at other frequency points except frequency point a and frequency point b. These signals are non-linear products.
  • FIG. 2b may also represent the signal distribution in the analog sampling signal AT (n). In this case, the signal in the dashed frame in FIG. 2b may represent the target sampling signal.
  • the digital chip 100 can produce a digital cancellation signal D x (n) according to the first digital signal D 1 (n), as shown in FIG. 2c.
  • the frequency point of the digital cancellation signal D x (n) is the same as the first digital signal D 1 (n)
  • the signal strength direction of the digital cancellation signal D x (n) is the same as the signal strength of the first digital signal D 1 (n)
  • the directions are opposite, and the absolute value of the signal strength of the digital cancellation signal D x (n) is smaller than the absolute value of the signal strength of the first digital signal D 1 (n).
  • the cancellation path 500 converts the digital cancellation signal D x (n) into an analog cancellation signal A x (n), and the analog sampling signal A T (n) corresponding to the first digital signal D 1 (n) ,
  • the phase of the target sampling signal and the phase of the analog cancellation signal A x (n) differ by 180 degrees, and the signal strength of the target sampling signal is greater than the signal strength of the analog cancellation signal A x (n).
  • the analog cancellation signal A x (n) can cancel part of the signal strength of the target sampled signal, as shown in 2d.
  • Figure 2d shows the signal distribution in the mixed signal of the analog cancellation signal A x (n) and the analog sampling signal A T (n) in the form of a digital signal.
  • the signal in the dashed box in Figure 2d is after the signal strength of the canceled part The target sample signal.
  • the digital chip 100 may further digital cancellation signals D x (n) for delay adjustment, so that the corresponding analog digital cancellation signals D x (n) cancellation signals A x (n)
  • the analog sampling signal AT (n) can be input into the feedback path 300 at the same time, which helps to more accurately cancel the signal strength of the target sampling signal.
  • the embodiment of the present application can reduce the signal strength of the target sampling signal passing through the feedback path 300, the embodiment of the present application is beneficial to reduce the hardware requirements for the feedback path 300.
  • the signal strength of the nonlinear product of the hardware is positively correlated with the signal strength of the input signal.
  • the embodiment of the present application reduces the signal strength of the input signal of the feedback path 300 (that is, the mixed signal provided by the second coupler 700). Therefore, the signal strength of the non-linear product of the feedback path 300 can be reduced, thereby helping to reduce the linearity requirement of the feedback path 300.
  • reducing the signal strength of the input signal of the feedback path 300 is also conducive to reducing the dynamic requirements on the feedback path 300.
  • the digital chip 100 in the embodiment of the present application includes a DPD circuit 101, a calculation circuit 103, and a cancellation signal generation circuit 104, and the calculation circuit 103 is coupled to the DPD circuit 101 and the cancellation signal generation circuit 104, respectively. among them:
  • the DPD circuit 101 may be a dedicated circuit module integrated in the digital chip 100.
  • the DPD circuit 101 may perform DPD correction on the first digital signal D1 to be sent according to the received digital sampling signal D T , and then perform DPD correction on the first digital signal D 1 after DPD correction.
  • the digital signal is output to the transmission path 200 as the next digital output signal.
  • the digital chip 100 may be a chip dedicated to DPD correction.
  • chip 100 may be coupled to the digital signal source does not have a chip DPD correction function
  • the output signal of the signal source as the first chip may be a digital signal D 1 input digital chip 100
  • the source chip 100 of the input digital signal a first chip
  • the digital signal D 1 performs DPD correction.
  • the digital chip 100 may also include a main signal generating circuit 102.
  • the main signal generating circuit 102 is respectively coupled with the DPD circuit 101, the calculation circuit 103 and the cancellation signal generating circuit 104.
  • the main signal generating circuit 102 may generate the above-mentioned first digital signal D 1 .
  • the calculation circuit 103 may be a processor, a microprocessor, etc. in the digital chip 100, and the calculation circuit 103 may update the cancellation coefficient of the cancellation signal generation circuit 104 according to the first digital signal D 1 to be sent.
  • the cancellation signal generating circuit 104 may generate a digital cancellation signal D x according to the updated cancellation coefficient and the first digital signal D 1 to be sent, and output the digital cancellation signal D x to the cancellation path 500.
  • the cancellation signal generating circuit 104 may be a digital filter, such as a finite impulse response (FIR) filter.
  • the cancellation coefficient can be understood as the filter coefficient of the digital filter.
  • the digital filter is a multi-order filter, for example, the digital filter is an M-order filter, and M is an odd number greater than 1.
  • the cancellation signal generation circuit 104 has M cancellation coefficients, and the calculation circuit 103 can update the M cancellation coefficients of the cancellation signal generation circuit 104 according to the first digital signal D 1 to be sent.
  • the calculation circuit 103 may store the digital sampling signal D T received from the feedback path 300 and the transmitted first digital signal D 1 . Updating cancellation coefficient, adaptively so that after complete extinction coefficient when can 1, a first digital signal D 1 has been transmitted and the digital sampled signal T D is calculated updated according to the received first digital signal to be transmitted D The cancellation coefficient is calculated, and the updated cancellation coefficient is written into the cancellation signal generating circuit 104.
  • the feedback path 300 is multiplexed for the calculation of the cancellation coefficient, so that the calculation circuit 103 can work together with the existing DPD circuit 101 and the feedback path 300.
  • the calculation circuit 103 may obtain M-1 first digital signals of M-1 sampling points before the current sampling point of the DPD circuit 101, for example, the first digital signal to be sent Is D 1 (n), the M-1 first digital signals of M-1 sampling points before the sampling point are D 1 (n-1), D 1 (n-2), ... D 1 (n -M+1).
  • the calculation circuit 103 can obtain the digital sampling signal D T corresponding to the (M-1)/2th first digital signal D 1 according to the time of the M-1 sampling points in descending order, and the digital sampling signal D T It can be expressed as
  • the calculation circuit 103 can then be based on the first digital signal D 1 (n), D 1 (n-1), D 1 (n-2), ... D 1 (n-M+1), and the digital sampling signal
  • the M cancellation coefficients of the cancellation signal generating circuit 104 are updated.
  • the updated M cancellation coefficients can satisfy the following formula:
  • Ch(i+1) M-1 to Ch(i+1) 0 are the updated M cancellation coefficients
  • Ch(i) M-1 to Ch(i) 0 are the M cancellation coefficients before the update Coefficient
  • i is the number of times that M cancellation coefficients have been updated, that is to say, formula 1 represents the i+1th update of M cancellation coefficients, during which the M cancellation coefficients have been i Updates.
  • ⁇ is the iteration step factor of the cancellation signal generating circuit 104.
  • the cancellation signal generating circuit 104 may further generate a digital cancellation signal D x (n) according to the updated cancellation coefficient and the first digital signal D 1 (n) to be sent.
  • the cancellation signal D x (n) satisfies the following formula:
  • Ch m is the m+1th cancellation coefficient among the M cancellation coefficients
  • m takes the integers in [0, M-1]
  • D 1 (nm) is the order of sampling points from morning to night .
  • the digital chip 100 in the embodiment of the present application can generate a digital cancellation signal D x , and convert the cancellation signal D x into an analog cancellation signal A x through the cancellation path 500, and the cancellation path 500 converts the analog cancellation signal A x is input to the feedback path 300, and the analog cancellation signal A x is mixed with the analog sampling signal AT of the input feedback path 300 to reduce the signal strength of the target sampling signal in the analog sampling signal AT , which is beneficial to reduce the hardware of the feedback path.

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Abstract

本申请公开了一种电子设备及数字芯片，该数字芯片可以是基带芯片。数字芯片可以对待输出的第一数字信号进行DPD校正。数字芯片还可以输出数字对消信号，经对消通路将数字对消信号转换为模拟对消信号后，将模拟对消信号输入反馈通路。模拟对消信号可以降低反馈通路所获得的模拟采样信号中，目标采样信号的信号强度，从而有利于降低对反馈通路的硬件要求。

Description

一种电子设备及数字芯片 技术领域
本申请涉及DPD校正技术领域，尤其涉及一种电子设备及数字芯片。
背景技术
数字预失真技术(digital pre-distortion，DPD)可以消除功率放大(power amplifier，PA)带来的非线性产物，因此常用于通信设备中。其中，非线性产物包括与目标信号的频点不同的信号，非线性产物不利于提高通信设备所发射的通信信号的信号质量。
示例性的，通信设备的基带芯片可以通过传输通路与通信设备的发射通路耦合，该传输通路可以对基带芯片输出的数字基带信号进行数模转换和功率放大，从而得到模拟基带信号，进而可以通过发射通路发射该模拟基带信号。由于在进行功率放大期间，传输通路中有可能产生非线性产物，因此基带芯片可以通过反馈通路获取模拟基带信号的采样信息，进而根据采样信息对待发送的数字基带信号进行DPD校正，抵消后续功率放大期间所产生的非线性产物。
然而，为了保持DPD电路的DPD校正效果，目前DPD校正对反馈通路的硬件要求较高。例如，反馈通路不能改变模拟基带信号的信噪比，又例如，反馈通路不能引入其它会影响DPD校正的非线性产物，等等，为反馈通路的设计带来了诸多不便。
发明内容
本申请提供一种电子设备及数字芯片，用于降低DPD校正中对反馈通路的硬件要求，有利于DPD校正的普及。
第一方面，本申请实施例提供一种电子设备，该电子设备主要包括数字芯片、传输通路、反馈通路和对消通路，其中，数字芯片分别与传输通路的输入端、反馈通路的输出端和对消通路的输入端耦合，反馈通路的输入端与传输通路的输出端耦合，对消通路的输出端与反馈通路的输入端耦合。电子设备中，数字芯片可以向传输通路输出数字输出信号；传输通路可以将数字输出信号转换为模拟输出信号后，输出模拟输出信号；反馈通路可以获取模拟输出信号的模拟采样信号，根据模拟采样信号得到数字采样信号，并将数字采样信号反馈给数字芯片；数字芯片还可以根据数字采样信号对待发送的第一数字信号进行DPD校正，将DPD校正后的第一数字信号作为数字输出信号输出，以及，根据第一数字信号生成数字对消信号，并向对消通路发送数字对消信号；对消通路，可以将第一数字信号对应的数字对消信号转换为模拟对消信号，并将模拟对消信号提供给反馈通路，模拟对消信号用于降低模拟采样信号中目标采样信号的信号强度。
本申请实施例中数字芯片可以生成数字对消信号，通过对消通路将对消信号转换为模拟对消信号，对消通路将模拟对消信号输入反馈通路，使模拟对消信号与输入反馈通路的模拟采样信号混合，以降低模拟采样信号中目标采样信号的信号强度，从而有利于降低对反馈通路中硬件动态范围的要求。而且，非线性产物的信号强度与输入行动信号强度正相关，本申请实施例通过模拟对消信号降低模拟采样信号中目标采样信号的信号强度有利于 降低反馈通路在对目标采样信号进行放大时产生的非线性产物，从而有利于降低对反馈通路中硬件的线性度的要求。综上，本申请实施例有利于降低对反馈通路的硬件要求。
示例性的，模拟对消信号的信号强度，小于目标采样信号的信号强度，且，模拟对消信号的相位，与目标采样信号的相位之差为180度。模拟对消信号和模拟采样信号混合，也就是两个模拟信号相叠加。由于模拟对消信号的相位与目标采样信号的相位之差为180度，因此两个模拟信号的信号强度相互抵消。又由于模拟对消信号的信号强度小于目标采样信号的信号强度，因此模拟对消信号并不会完全抵消目标采样信号，反馈通路300的输入信号中依旧保留了信号强度降低了的目标采样信号，使得数字芯片依旧可以利用数字采样信号进行DPD校正。
在一种可能的实现方式中，电子设备还包括第一耦合器和第二耦合器；反馈通路通过第一耦合器与传输通路的输出端耦合，第二耦合器的一个输入端与第一耦合器耦合，第二耦合器的另一个输入端与对消通路耦合，第二耦合器的输出端与反馈通路耦合；其中，第一耦合器可以将模拟输出信号中的一部分信号作为模拟采样信号传输给第二耦合器；第二耦合器可以接收模拟采样信号和模拟对消信号，将模拟采样信号和模拟对消信号的混合信号输出给反馈通路。
示例性的，反馈通路包括第一放大器、混频器、本振信号源和模数转换器；混频器分别与第一放大器、模数转换器和本振信号源耦合，模数转换器与数字芯片耦合；其中，第一放大器可以而接收模拟采样信号和模拟对消信号的混合信号，对混合信号进行功率放大，得到第二模拟信号；本振信号源可以产生本振信号；混频器可以接收第二模拟信号和本振信号，采用本振信号对第二模拟信号进行混频，得到第三模拟信号；模数转换器可以对第三模拟信号进行模数转换，得到上述数字采样信号。
示例性的，传输通路包括第一数模转换器和第二放大器；第一数模转换器分别与数字芯片和第二放大器耦合；其中，第一数模转换器可以对数字芯片输出的数字输出信号进行数模转换，得到第四模拟信号；第二放大器可以对第四模拟信号进行功率放大，得到模拟输出信号。
示例性的，对消通路包括第二数模转换器，第二数模转换器的输入端与数字芯片耦合，第二数模转换器的输出端与反馈通路耦合；第二数模转换器可以将数字对消信号转换为模拟对消信号。
第二方面，本申请实施例提供一种数字芯片，该数字芯片可以应用于如上述第一方面中，任一种可能的实现方式所提供的电子设备，该数字芯片包括：数字预失真DPD电路、计算电路和对消信号生成电路，计算电路分别与DPD电路和对消信号生成电路耦合；其中，计算电路可以根据待发送的第一数字信号，更新对消信号生成电路的对消系数；对消信号生成电路与对消通路耦合，可以根据更新后的对消系数和待发送的第一数字信号生成数字对消信号，并向对消通路输出数字对消信号；DPD电路可以根据接收到的数字采样信号对待发送的第一数字信号进行预失真处理，将预失真处理后的第一数字信号作为接下来的数字输出信号输出给传输通路。
在一种可能的实现方式中，数字芯片可以是专用于DPD校正的芯片。例如，数字芯片可以与不具备DPD校正功能的信号源芯片耦合，信号源芯片的输出信号可以作为上述第一数字信号输入数字芯片，由数字芯片对信号源芯片输入的第一数字信号进行DPD校正。
在另一种可能的实现方式中，数字芯片还可以包括主信号生成电路，该主信号生成电路分别与DPD电路、计算电路和对消信号生成电路耦合；主信号生成电路可以生成第一数字信号。
在一种可能的实现方式中，计算电路可以通过以下方式更新对消系数：获取在当前采样点之前的M-1个采样点的M-1个已发送的第一数字信号，以及根据M-1个采样点的时间由晚至早的顺序，获取其中第(M-1)/2个已发送的第一数字信号对应的数字采样信号，M为大于1的奇数；根据当前采样点的待发送的第一数字信号、M-1个已发送的第一数字信号、以及第(M-1)/2个已发送的第一数字信号对应的数字采样信号，更新对消信号生成电路的M个对消系数。
在一种可能的实现方式中，对消信号生成电路可以为数字滤波器，在此情况下，对消系数可以为数字滤波器的滤波系数，M可以为所述数字滤波器的阶数。
示例性的，更新后的M个对消系数可以满足以下公式：
Figure PCTCN2019116810-appb-000001
其中，Ch(i+1) M-1至Ch(i+1) 0为更新后的M个对消系数，Ch(i) M-1至Ch(i) 0为更新前的M个对消系数，i为已更新M个对消系数的次数，μ为对消信号生成电路的迭代步长因子，D 1(n)为当前的待发送的第一数字信号，
Figure PCTCN2019116810-appb-000002
为第(M-1)/2个已发送的第一数字信号，D 1[n-M+1]为第M-1个已发送的第一数字信号，
Figure PCTCN2019116810-appb-000003
为第(M-1)/2个已发送的第一数字信号对应的数字采样信号。
在一种可能的实现方式中，数字对消信号可以满足以下公式：
Figure PCTCN2019116810-appb-000004
其中，D x(n)为当前采样点的待发送的第一数字信号对应的数字对消信号，Ch m为第m+1个对消系数，m取遍[0，M-1]中的整数，D 1(n-m)为第m个已发送的第一数字信号。
附图说明
图1为本申请实施例提供的一种电子设备结构示意图；
图2a为本申请实施例提供的一种第一数字信号示意图；
图2b为本申请实施例提供的一种模拟输出信号示意图；
图2c为本申请实施例提供的一种数字对消信号示意图；
图2d为本申请实施例提供的一种混合信号示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或***实施例中。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两 个以上。鉴于此，本发明实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
需要指出的是，本申请实施例中“耦合”指的是能量传递关系，例如，A与B耦合，指的是A与B之间能够传递能量，反应在电路连接关系上，便是A与B之间可以直接电连接，也可以通过其它导体或电路元件间接电连接。
下面将结合附图，对本申请实施例进行详细描述。
功率放大(power amplifier，PA)是一种常见的模拟信号处理方式，一般可以由放大器实现。然而，在功率放大的过程中，有可能会产生一些非线性产物。例如，放大器对频点为A的目标模拟信号进行功率放大，则功率放大器的输出信号中不仅包括了位于频点A的、功率放大后的目标模拟信号，还包括了位于其它频点的信号，这些位于其它频点的信号便可以理解为功率放大的非线性产物。
非线性产物会对放大器的输出信号的信号质量产生负面影响，因此出现了数字预失真(digital pre-distortion，DPD)技术，通过DPD技术可以降低功率放大器的输出信号中非线性产物的信号强度。
示例性的，图1示例性示出了本申请实施例适用的一种电子设备架构示意图。该电子设备可以是基站、终端等具备信号发射功能的设备。如图1所示，电子设备主要包括数字芯片100、传输通路200、反馈通路300。其中，数字芯片100分别与传输通路200和反馈通路300耦合，反馈通路300与传输通路200耦合。
在本申请实施例中，数字芯片100可以是具备DPD功能的、能够输出数字输出信号D o的芯片。例如，该数字芯片100可以是基带芯片，在此情况下，数字芯片100的数字输出信号D o可以是数字基带信号。
传输通路200可以将数字芯片100的数字输出信号D o转换为模拟输出信号A o，并输出该模拟输出信号A o。示例性的，如图1所示，传输通路200可以包括第一数模转换器(digital-to-analog converter，DAC)201和第二放大器202。其中，第一数模转换器201的输入端与数字芯片100耦合，第一数模转换器201的输出端与第二放大器202的输入端耦合。第一数模转换器201可以对数字芯片100输出的数字输出信号D o进行数模转换，得到第四模拟信号A 4。第二放大器202可以对第四模拟信号A 4进行功率放大，从而得到模拟输出信号A o。
在一种可能的实现方式中，如图1所示，电子设备还可以包括收发通路400。第二放大器202可以将模拟输出信号A o输出给收发通路400，由收发通路400发射该模拟输出信号A o。示例性的，收发通路400可以包括单向隔离器401、双向滤波器402和天线403。其中，单向隔离器401可以防止信号由收发通路400向传输通路200输出，双向滤波器402可以对待发送信号和天线403接收到的信号进行滤波，天线403可以接收或发送信号。示例性的，第二放大器202输出的模拟输出信号A o可以经单向隔离器401传输至双向滤波器402，经双向滤波器402滤波后，由天线403发射。
需要指出的是，由于第二放大器202在功率放大期间，会产生额外的非线性产物，因 此，第二放大器202输出的模拟输出信号A o中既包括了放大后的第四模拟信号，也就是目标模拟信号，也包括了非线性产物。
有鉴于此，如图1所示，数字芯片100还与反馈通路300耦合，反馈通路300与传输通路200耦合。示例性的，反馈通路300可以通过第一耦合器600与传输通路200耦合。具体来说，第一耦合器600的输入端与传输通路200耦合，第一耦合器600的输出端与反馈通路300耦合。
第一耦合器600可以针对传输通路200输出的模拟输出信号A o，将其中的一部分信号作为模拟输出信号A o的模拟采样信号A T传输给反馈通路300，模拟输出信号A o中的另一部分模拟输出信号被输出至收发通路400。应理解，第一耦合器600是从信号功率的角度将模拟输出信号A o分为两部分，也就是说，两部分模拟输出信号A o的频率、相位、波形相同，区别仅在于两部分模拟输出信号A o的信号强度有可能存在不同。
反馈通路300可以根据模拟输出信号A o的模拟采样信号A T得到数字采样信号D T，并将数字采样信号D T反馈给数字芯片100。示例性的，如图1所示，反馈通路300包括第一放大器304、混频器302、本振信号源303和模数转换器(analog-to-digital converter，ADC)301。其中，第一放大器304的输入端与传输通路200耦合(也可以理解为通过第一耦合器600与传输通路200耦合)，第一放大器304的输出端与混频器302的一个输入端耦合，混频器302的另一个输入端与本振信号源303耦合，混频器302的输出端与模数转换器301的输入端耦合，模数转换器301的输出端与数字芯片100耦合。
具体来说，第一放大器304可以对模拟采样信号A T进行功率放大，得到第二模拟信号A 2。本振信号源303可以产生本振信号Lo。混频器302可以从第一放大器304接收第二模拟信号A 2，从本振信号源303接收本振信号Lo，根据本振信号Lo对第二模拟信号A 2进行混频，从而得到第三模拟信号A 3。经过混频得到的第三模拟信号A 3，与数字芯片100的数字输出信号D o具有相同的频点。模数转换器301可以对第三模拟信号A 3进行模数转换，从而得到数字采样信号D T。模数转换器301将数字采样信号D T提供给数字芯片100，使得数字芯片100可以根据数字采样信号D T进行DPD校正。
具体来说，数字采样信号D T可以向数字芯片100传递模拟输出信号A o的采样信息，例如模拟输出信号A o中非线性产物的频点信息、信号强度信息等。因此，数字芯片100可以根据数字采样信号D T对接下来待发送的第一数字信号D 1进行DPD校正，以抵消后续功率放大过程中产生的非线性产物。
其中，第一数字信号D 1可以理解为还未经过DPD校正的数字信号。数字芯片100对第一数字信号D 1完成DPD校正后，便可以将经过DPD校正的第一数字信号D 1作为数字输出信号D o输出。数字芯片100对第一数字信号D 1进行DPD校正的具体实现方式可以参考现有技术，对此不再赘述。
第一数字信号D 1对应的数字输出信号D o，也就是经DPD较正后的第一数字信号D 1，经传输通路200后转换为模拟输出信号A o。反馈通路300将该模拟输出信号A o的模拟采样信号A T转换为数字采样信号D T后，将数字采样信号D T提供给数字芯片100，以使数字芯片100可以根据该数字采样信号D T对后续的第一数字信号D 1进行DPD校正。
例如，当前采样点为采样点n，待发送的第一数字信号为D 1(n)。第一数字信号D 1(n)经DPD校正后，得到数字输出信号D o(n)。数字输出信号D o(n)经传输通路200，转换为模拟输出信号A o(n)。反馈通路300获取模拟输出信号A o(n)的模拟采样信号A T(n)，并将模 拟采样信号A T(n)转换为数字采样信号D T(n)。
反馈通路300将数字采样信号D T(n)提供给数字芯片100，使得数字芯片100可以使用该数字采样信号D T(n)对后续的第一数字信号D 1的DPD校正。例如，数字芯片100可以使用数字采样信号D T(n)对后续第k个采样点(也就是采样点n+k)的第一数字信号D 1(n+k)进行DPD校正。其中，k可以为任一大于或等于1的整数，本申请实施例对此并不多作限制。
为了保证DPD校正精度，反馈通路300应尽量避免引入额外的非线性产物，且，反馈通路300不应改变模拟采样信号A T的信噪比(signal to noise ratio，SNR)。因此，目前往往需要采用高动态和高线性度的硬件来构成反馈通路300。其中，高动态指的是硬件的最大工作功率和最小工作功率之间的动态范围较大，高线性度指的是信号经过硬件后，可以产生较小的非线性产物，或所产生的非线性产物不会影响DPD校正精度。
由于目前反馈通路300的硬件要求较高，不利于DPD技术的推广。有鉴于此，本申请实施例提供一种电子设备和数字芯片100，通过将模拟采样信号A T与模拟对消信号A x混合，以降低模拟采样信号A T中目标采样信号的信号强度，从而有利于降低对反馈通路300的硬件要求。其中，目标采样信号可以理解为模拟输出信号A o中目标模拟信号对应的采样信号。
示例性的，如图1所示，电子设备中还包括对消通路500，对消通路500的一端与数字芯片100耦合，另一端与反馈通路300耦合。
在本申请实施例中，数字芯片100还可以根据待发送的第一数字信号D 1生成数字对消信号D x，并向对消通路500发送该数字对消信号D x。示例性的，数字芯片100可以根据待发送的第一数字信号D 1以及已接收到的数字采样信号D T生成数字对消信号D x。
举例说明，假设当前采样点为n，待发送的第一数字信号为D 1(n)，数字芯片100可以根据第一数字信号为D 1(n)和已接收到的数字采样信号D T(n-h)生成数字对消信号D x(n)，其中，数字采样信号D T(n-h)可以理解为，在当前的采样点n之前的第h个采样点，也就是采样点n-h，待发送的第一数字信号D 1(n-h)所对应的数字采样信号D T(n-h)，h为大于或等于1的整数。
其中，第一数字信号D 1(n-h)与数字采样信号D T(n-h)之间的对应关系，可以理解为，数字芯片100对第一数字信号D 1(n-h)进行DPD校正之后，得到数字输出信号D o(n-h)。传输通路200对数字输出信号D o(n-h)进行转换，得到模拟输出信号A o(n-h)。反馈通路300获取模拟输出信号A o(n-h)的模拟采样信号A T(n-h)，进而根据模拟采样信号A T(n-h)得到了第一数字信号D 1(n-h)对应的数字采样信号D T(n-h)。
对消通路500可以将第一数字信号D 1(n)对应的数字对消信号D x(n)转换为模拟对消信号A x(n)，并将模拟对消信号A x(n)提供给反馈通路300。在本申请实施例中，可以通过模拟对消信号A x(n)降低反馈通路300中，第一数字信号D 1(n)对应的采样信号A T(n)中目标采样信号的信号强度。
其中，第一数字信号D 1(n)和采样信号A T(n)之间的对应关系，可以理解为，数字芯片对第一数字信号D 1(n)进行DPD校正后，向传输通路200输出数字输出信号D o(n)。传输通路200将数字输出信号D o(n)转换为模拟输出信号A o(n)，反馈通路300从传输通路200获取模拟输出信号A o(n)的采样信号A T(n)，也就是第一数字信号D 1(n)对应的采样信号A T(n)。
示例性的，对消通路500包括第二数模转换器(DAC)501，第二数模转换器501的 输入端与数字芯片100耦合，第二数模转换器501的输出端与反馈通路300耦合。第二数模转换器501可以对数字对消信号D x(n)进行数模转换，将数字对消信号D x(n)转换为模拟对消信号A x(n)。
在一种可能的实现方式中，如图1所示，对消通路500可以通过第二耦合器700与反馈通路300耦合。具体来说，第二耦合器700的输入端分别与第一耦合器600的输出端和对消通路500耦合，第二耦合器700的输出端与反馈通路300耦合。第二耦合器700可以接收第一耦合器600提供的模拟输出信号A o(n)的模拟采样信号A T(n)，以及模拟对消信号A x(n)，并向反馈通路300输出模拟采样信号A T(n)和模拟对消信号A x(n)的混合信号。
在本申请实施例中，模拟对消信号A x(n)可以降低模拟采样信号A T(n)中目标采样信号的信号强度。示例性的，模拟对消信号A x(n)的信号强度小于模拟采样信号A T(n)中目标采样信号的信号强度，且，模拟对消信号A x(n)的相位，与模拟采样信号A T(n)中目标采样信号的相位之差为180度。
模拟对消信号A x(n)和模拟采样信号A T(n)混合，也就是两个模拟信号相叠加。由于模拟对消信号A x(n)的相位与目标采样信号的相位之差为180度，因此两个模拟信号的信号强度相互抵消。又由于模拟对消信号A x(n)的信号强度小于目标采样信号的信号强度，因此模拟对消信号A x(n)并不会完全抵消目标采样信号，第二耦合器700输出的混合信号(反馈通路300的输入信号)中依旧保留了信号强度降低了的目标采样信号，使得数字芯片100依旧可以利用数字采样信号D T(n)进行DPD校正。
举例说明，如图2a至2d依次示例性示出了第一数字信号、模拟输出信号、数字对消信号和混合信号，图2a至2d中，横向表示频域，纵向表示信号强度。需要指出的是，图2b是以数字信号的形式示出了模拟输出信号A o，其实际上表示的是模拟输出信号A o。图2d同理，是以数字信号的形式示出了混合信号。
如图2a所示，第一数字信号D 1(n)位于频点a和频点b。第一数字信号D 1(n)对应的模拟输出信号A o(n)可以如图2b所示。其中，虚线框以内的信号表示放大后的目标信号，虚线框之外的信号表示非线性产物。如图2b所示，放大后的目标信号位于频点a和频点b，在除频点a和频点b之外的其它频点也出现了信号，这些信号便是非线性产物。可以理解，图2b也可以表示模拟采样信号A T(n)中的信号分布，在此情况下，图2b中虚线框内的信号可以表示目标采样信号。
在本申请实施例中，数字芯片100可以根据第一数字信号D 1(n)生产数字对消信号D x(n)，如图2c所示。数字对消信号D x(n)的频点与第一数字信号D 1(n)相同，数字对消信号D x(n)的信号强度方向与第一数字信号D 1(n)的信号强度方向相反，且数字对消信号D x(n)的信号强度的绝对值小于第一数字信号D 1(n)的信号强度的绝对值。
在此基础上，对消通路500将数字对消信号D x(n)转换为模拟对消信号A x(n)，第一数字信号D 1(n)对应的模拟采样信号A T(n)中，目标采样信号的相位与模拟对消信号A x(n)的相位之间相差180度，且目标采样信号的信号强度大于模拟对消信号A x(n)的信号强度。模拟对消信号A x(n)可以抵消目标采样信号的部分信号强度，如2d所示。图2d以数字信号的形式示出了模拟对消信号A x(n)和模拟采样信号A T(n)的混合信号中信号分布情况，图2d中虚线框内的信号为抵消部分信号强度之后的目标采样信号。
在一种可能的实现方式中，数字芯片100还可以对数字对消信号D x(n)进行时延调整，使数字对消信号D x(n)对应的模拟对消信号A x(n)和模拟采样信号A T(n)可以同时输入反馈 通路300，有利于更精确地抵消目标采样信号的信号强度。
由于本申请实施例可以降低经过反馈通路300的目标采样信号的信号强度，因此本申请实施例有利于降低对反馈通路300的硬件要求。具体来说，硬件的非线性产物的信号强度与输入信号的信号强度正相关，本申请实施例降低了反馈通路300的输入信号(也就是第二耦合器700提供的混合信号)的信号强度，因此可以降低反馈通路300的非线性产物的信号强度，进而有利于降低对反馈通路300的线性度要求。同时，降低反馈通路300的输入信号的信号强度，也有利于降低对反馈通路300的动态要求。
接下来，对本申请实施例所提供的数字芯片100作进一步的示例性说明。
如图1所示，本申请实施例中数字芯片100包括DPD电路101、计算电路103和对消信号生成电路104，计算电路103分别与DPD电路101和对消信号生成电路104耦合。其中：
DPD电路101可以是在数字芯片100中集成的专用电路模块，DPD电路101可以根据接收到的数字采样信号D T对待发送的第一数字信号D 1进行DPD校正，将经DPD校正后的第一数字信号作为接下来的数字输出信号输出给传输通路200。
在一种可能的实现方式中，数字芯片100可以是专用于DPD校正的芯片。例如，数字芯片100可以与不具备DPD校正功能的信号源芯片耦合，信号源芯片的输出信号可以作为上述第一数字信号D 1输入数字芯片100，由数字芯片100对信号源芯片输入的第一数字信号D 1进行DPD校正。
在另一种可能的实现方式中，如图1所示，数字芯片100也可以包括主信号生成电路102。主信号生成电路102分别与DPD电路101、计算电路103和对消信号生成电路104耦合。主信号生成电路102可以生成上述第一数字信号D 1。
计算电路103可以是数字芯片100中的处理器、微处理器等，计算电路103可以根据待发送的第一数字信号D 1，更新对消信号生成电路104的对消系数。对消信号生成电路104可以根据更新后的对消系数和待发送的第一数字信号D 1生成数字对消信号D x，并向对消通路500输出数字对消信号D x。
示例性的，对消信号生成电路104可以是数字滤波器，如有限长单位冲激响应(finite impulse response，FIR)滤波器。在此情况下，对消系数可以理解为数字滤波器的滤波系数。一般来说，数字滤波器为多阶滤波，例如，数字滤波器为M阶滤波，M为大于1的奇数。对消信号生成电路104具有M个对消系数，计算电路103可以根据待发送的第一数字信号D 1，分别更新对消信号生成电路104的M个对消系数。
具体来说，如图1所示，计算电路103可以存储从反馈通路300接收到的数字采样信号D T，以及已发送的第一数字信号D 1。在更新对消系数时，可以根据待发送的第一数字信号D 1、已发送的第一数字信号D 1和已接收的数字采样信号D T计算更新后的对消系数，从而自适应地完成对消系数计算，并将更新后的对消系数写入对消信号生成电路104。本申请实施例中，对消系数的计算复用了反馈通路300，使得计算电路103可以与现有的DPD电路101、反馈通路300协同工作。
示例性的，假设当前采样点为n，计算电路103可以获取DPD电路101在当前采样点之前的M-1个采样点的M-1个第一数字信号，例如，待发送的第一数字信号为D 1(n)，在采样点之前的M-1个采样点的M-1个第一数字信号为D 1(n-1)、D 1(n-2)、……D 1(n-M+1)。计算电路103可以根据M-1个采样点的时间由晚至早顺序，获取其中第(M-1)/2个第一数 字信号D 1对应的数字采样信号D T，该数字采样信号D T可以表示为
Figure PCTCN2019116810-appb-000005
计算电路103继而可以根据第一数字信号D 1(n)、D 1(n-1)、D 1(n-2)、……D 1(n-M+1)，以及数字采样信号
Figure PCTCN2019116810-appb-000006
更新对消信号生成电路104的M个对消系数。
例如，更新后的M个对消系数可以满足以下公式：
Figure PCTCN2019116810-appb-000007
其中，Ch(i+1) M-1至Ch(i+1) 0为更新后的M个对消系数，Ch(i) M-1至Ch(i) 0为更新前的M个对消系数，i为已更新M个对消系数的次数，也就是说，公式一表示的是第i+1次更新M个对消系数，在此之间，已对M个对消系数进行了i次更新。μ为对消信号生成电路104的迭代步长因子。
对消信号生成电路104进而可以根据更新后的对消系数和待发送的第一数字信号D 1(n)生成数字对消信号D x(n)。示例性的，对消信号D x(n)满足以下公式：
Figure PCTCN2019116810-appb-000008
其中，Ch m为M个对消系数中的第m+1个对消系数，m取遍[0，M-1]中的整数，D 1(n-m)为按照采样点由早到晚的顺序，M-1个已发送的第一数字信号中的第m个第一数字信号。
综上，本申请实施例中数字芯片100可以生成数字对消信号D x，通过对消通路500将对消信号D x转换为模拟对消信号A x，对消通路500将模拟对消信号A x输入反馈通路300，使模拟对消信号A x与输入反馈通路300的模拟采样信号A T混合，以降低模拟采样信号A T中目标采样信号的信号强度，从而有利于降低对反馈通路的硬件要求。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种电子设备，其特征在于，包括：数字芯片、传输通路、反馈通路和对消通路，所述数字芯片分别与所述传输通路的输入端、所述反馈通路的输出端和所述对消通路的输入端耦合，所述反馈通路的输入端与所述传输通路的输出端耦合，所述对消通路的输出端与所述反馈通路的输入端耦合；
    所述数字芯片，用于向所述传输通路输出数字输出信号；
    所述传输通路，用于将所述数字输出信号转换为模拟输出信号后，输出所述模拟输出信号；
    所述反馈通路，用于获取所述模拟输出信号的模拟采样信号，根据所述模拟采样信号得到数字采样信号，并将所述数字采样信号反馈给所述数字芯片；
    所述数字芯片，还用于根据所述数字采样信号对待发送的第一数字信号进行数字预失真DPD校正，将DPD校正后的所述第一数字信号作为数字输出信号输出，以及，根据所述第一数字信号生成数字对消信号，并向所述对消通路发送所述数字对消信号；
    所述对消通路，用于将所述第一数字信号对应的数字对消信号转换为模拟对消信号，并将所述模拟对消信号提供给所述反馈通路，所述模拟对消信号用于降低所述模拟采样信号中目标采样信号的信号强度。
  2. 根据权利要求1所述的电子设备，其特征在于，所述模拟对消信号的信号强度，小于所述目标采样信号的信号强度，且，所述模拟对消信号的相位，与所述目标采样信号的相位之差为180度。
  3. 根据权利要求1或2所述的电子设备，其特征在于，所述电子设备还包括第一耦合器和第二耦合器；
    所述反馈通路通过所述第一耦合器与所述传输通路的输出端耦合，所述第二耦合器的一个输入端与所述第一耦合器耦合，所述第二耦合器的另一个输入端与所述对消通路耦合，所述第二耦合器的输出端与所述反馈通路耦合；
    所述第一耦合器，用于将所述模拟输出信号中的一部分信号作为所述模拟采样信号传输给所述第二耦合器；
    所述第二耦合器，用于接收所述模拟采样信号和所述模拟对消信号，将所述模拟采样信号和所述模拟对消信号的混合信号输出给所述反馈通路。
  4. 根据权利要求1至3中任一项所述的电子设备，其特征在于，所述反馈通路包括第一放大器、混频器、本振信号源和模数转换器；
    所述混频器分别与所述第一放大器、所述模数转换器和所述本振信号源耦合，所述模数转换器与所述数字芯片耦合；
    所述第一放大器，用于接收所述模拟采样信号和所述模拟对消信号的混合信号，对所述混合信号进行功率放大，得到第二模拟信号；
    所述本振信号源，用于产生本振信号；
    所述混频器，用于接收所述第二模拟信号和本振信号，采用所述本振信号对所述第二模拟信号进行混频，得到第三模拟信号；
    所述模数转换器，用于对所述第三模拟信号进行模数转换，得到所述数字采样信号。
  5. 根据权利要求1至4中任一项所述的电子设备，其特征在于，所述传输通路包括 第一数模转换器和第二放大器；
    所述第一数模转换器分别与所述数字芯片和所述第二放大器耦合；
    所述第一数模转换器，用于对所述数字芯片输出的数字输出信号进行数模转换，得到第四模拟信号；
    所述第二放大器，用于对所述第四模拟信号进行功率放大，得到所述模拟输出信号。
  6. 根据权利要求1至5中任一项所述的电子设备，其特征在于，所述对消通路包括第二数模转换器，所述第二数模转换器的输入端与所述数字芯片耦合，所述第二数模转换器的输出端与所述反馈通路耦合；
    所述第二数模转换器，用于将所述数字对消信号转换为所述模拟对消信号。
  7. 一种数字芯片，其特征在于，应用于如权利要求1至6中任一项所述的电子设备，所述数字芯片包括：数字预失真DPD电路、计算电路和对消信号生成电路，所述计算电路分别与所述DPD电路和所述对消信号生成电路耦合；
    所述计算电路，用于根据所述待发送的第一数字信号，更新所述对消信号生成电路的对消系数；
    所述对消信号生成电路，用于与所述对消通路耦合，根据更新后的对消系数和所述待发送的第一数字信号生成数字对消信号，并向所述对消通路输出所述数字对消信号；
    所述DPD电路，用于根据接收到的数字采样信号对所述待发送的第一数字信号进行预失真处理，将预失真处理后的第一数字信号作为接下来的数字输出信号输出给所述传输通路。
  8. 根据权利要求7所述的数字芯片，其特征在于，所述数字芯片还包括主信号生成电路，所述主信号生成电路分别与所述DPD电路、所述计算电路和所述对消信号生成电路耦合；
    所述主信号生成电路，用于生成所述第一数字信号。
  9. 根据权利要求7或8所述的数字芯片，其特征在于，所述计算电路，具体用于：
    获取在当前采样点之前的M-1个采样点的M-1个已发送的第一数字信号，以及根据所述M-1个采样点的时间由晚至早的顺序，获取其中第(M-1)/2个已发送的第一数字信号对应的数字采样信号，M为大于1的奇数；
    根据当前采样点的待发送的第一数字信号、所述M-1个已发送的第一数字信号、以及所述第(M-1)/2个已发送的第一数字信号对应的数字采样信号，更新所述对消信号生成电路的M个对消系数。
  10. 根据权利要求9所述的数字芯片，其特征在于，所述对消信号生成电路为数字滤波器，所述对消系数为所述数字滤波器的滤波系数，M为所述数字滤波器的阶数。
  11. 根据权利要求9或10所述的数字芯片，其特征在于，更新后的M个对消系数满足以下公式：
    Figure PCTCN2019116810-appb-100001
    其中，Ch(i+1) M-1至Ch(i+1) 0为更新后的M个对消系数，Ch(i) M-1至Ch(i) 0为更新前的M个对消系数，i为已更新所述M个对消系数的次数，μ为所述对消信号生成电路的迭 代步长因子，D 1(n)为当前采样点的待发送的第一数字信号，
    Figure PCTCN2019116810-appb-100002
    为所述第(M-1)/2个已发送的第一数字信号，D 1[n-M+1]为第M-1个已发送的第一数字信号，
    Figure PCTCN2019116810-appb-100003
    为所述第(M-1)/2个已发送的第一数字信号对应的数字采样信号。
  12. 根据权利要求9至11中任一项所述的数字芯片，其特征在于，所述数字对消信号满足以下公式：
    Figure PCTCN2019116810-appb-100004
    其中，D x(n)为当前采样点的待发送的第一数字信号对应的数字对消信号，Ch m为第m+1个对消系数，m取遍[0，M-1]中的整数，D 1(n-m)为第m个已发送的第一数字信号。
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Publication number Priority date Publication date Assignee Title
CN101895260A (zh) * 2009-05-21 2010-11-24 株式会社Ntt都科摩 幂级数型数字预失真器及其控制方法
CN102014090A (zh) * 2010-12-13 2011-04-13 中兴通讯股份有限公司 数字预失真方法及装置
CN102763325A (zh) * 2010-02-16 2012-10-31 住友电气工业株式会社 放大器装置、包括放大器装置的无线电发送装置、和调整放大器装置的增益的方法
WO2015081573A1 (zh) * 2013-12-06 2015-06-11 华为技术有限公司 一种信号转换的方法及装置

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Publication number Priority date Publication date Assignee Title
CN101895260A (zh) * 2009-05-21 2010-11-24 株式会社Ntt都科摩 幂级数型数字预失真器及其控制方法
CN102763325A (zh) * 2010-02-16 2012-10-31 住友电气工业株式会社 放大器装置、包括放大器装置的无线电发送装置、和调整放大器装置的增益的方法
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