WO2021077337A1 - Light-emitting diode and manufacturing method therefor - Google Patents

Light-emitting diode and manufacturing method therefor Download PDF

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Publication number
WO2021077337A1
WO2021077337A1 PCT/CN2019/112818 CN2019112818W WO2021077337A1 WO 2021077337 A1 WO2021077337 A1 WO 2021077337A1 CN 2019112818 W CN2019112818 W CN 2019112818W WO 2021077337 A1 WO2021077337 A1 WO 2021077337A1
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Prior art keywords
electrode
layer
type semiconductor
semiconductor layer
metal structure
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PCT/CN2019/112818
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French (fr)
Chinese (zh)
Inventor
毕东升
徐凯
徐胜娟
蔡家豪
黄照明
张家豪
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安徽三安光电有限公司
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Priority to PCT/CN2019/112818 priority Critical patent/WO2021077337A1/en
Priority to CN201980038660.XA priority patent/CN112424960B/en
Publication of WO2021077337A1 publication Critical patent/WO2021077337A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the invention belongs to the field of semiconductors, and particularly relates to a light emitting diode for improving metal migration and a manufacturing method thereof.
  • LED chips are widely used in various fields such as lighting, indoor and outdoor display screens, backlight sources, and display lamps due to their advantages of high brightness, low voltage, low energy consumption, and long life.
  • the use conditions and environments are various, especially the use environment of indoor and outdoor display screens is more stringent. It is affected by high temperature, water vapor, chemical corrosion and other environmental impacts during the terminal application of the display.
  • the chip When the chip is powered on (positive current) and off (negative voltage), the metal elements are electrolyzed into an ion state, and migration occurs under the action of the electric field of the positive current and the negative voltage, resulting in a dead lamp abnormality.
  • the traditional light-emitting diode (Light-Emitting Diode, LED) chip structure usually includes a substrate 10', an N-type layer 21', a light-emitting layer 22', a P-type layer 23', a transparent conductive layer 30', and a metal
  • the metal electrode includes an N electrode 41' and a P electrode 42', wherein the electrons provided by the N-type layer 21' and the holes provided by the P-type layer 23' recombine and emit light in the light-emitting layer 22'.
  • the present invention provides a metal structure located under the P electrode and/or N electrode to weaken the electric field strength between the P electrode and the N electrode through shunting, thereby improving the problem of metal migration in the electrode.
  • a light emitting diode includes at least: a substrate; an epitaxial layer stacked on the substrate, the epitaxial layer including an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked in sequence.
  • the epitaxial layer is etched to expose the N-type semiconductor layer to form a first groove; the P electrode is electrically connected to the P-type semiconductor layer; the N electrode is located in the first groove and is electrically connected to the N-type semiconductor layer; A first metal structure electrically connected to the N-type semiconductor layer is provided below the P electrode, a first insulating isolation layer is provided between the first metal structure and the P electrode, and a first metal structure electrically connected to the P-type semiconductor layer is provided below the N electrode.
  • the second metal structure has a second insulating isolation layer between the second metal structure and the N electrode.
  • the P-type semiconductor layer is etched to the N-type semiconductor layer to form a second groove, the first metal structure is disposed in the second groove, and the first metal structure is electrically connected to the N-type semiconductor layer.
  • sexual conduction; the first insulating isolation layer wraps the surface of the first metal structure, and the P electrode wraps the surface of the first insulating isolation layer.
  • the second metal structure is located on the surface of the P-type semiconductor layer on the sidewall of the first groove, and the second metal structure is electrically connected to the P-type semiconductor layer.
  • the second insulating isolation layer wraps the second metal structure and extends to the sidewall of the first groove.
  • the N electrode extends along the surface of the second insulating isolation layer to above the second metal structure.
  • the P electrode and the N electrode and the first metal structure respectively form a first electric field and a second electric field.
  • the second electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode.
  • a first electric field and a third electric field are respectively formed between the N electrode and the P electrode and the second metal structure.
  • the third electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode.
  • the opening diameter of the second groove is smaller than the diameter of the P electrode; the top of the first metal structure is higher or flush with or lower than the surface of the P-type semiconductor layer; the shape of the second groove is cylindrical Or V-shaped.
  • the first metal structure and the second metal structure are the same or different.
  • the first metal structure and the second metal structure are both a single-layer structure or a multi-layer structure.
  • the first metal structure and the second metal structure are both selected from one or a combination of nickel, chromium, aluminum, platinum, silver, gold, and titanium.
  • the first insulating isolation layer and the second insulating isolation layer are both selected from one or a combination of silicon dioxide, silicon nitride, and aluminum oxide.
  • a transparent conductive layer is also provided on the surface of the P-type semiconductor layer.
  • the manufacturing method of the above-mentioned light-emitting diode includes the following steps:
  • a first insulating isolation layer is made on the surface of the first metal structure, and the first insulating isolation layer wraps the first metal structure;
  • a second insulating isolation layer is made on the surface of the second metal structure, and the second insulating isolation layer wraps the first metal structure.
  • a P electrode is made on the surface of the first insulating isolation layer, and the P electrode is electrically connected to the P-type semiconductor layer; an N electrode is made in the second groove, and the N electrode extends along the surface of the second insulating isolation layer to the first Above the two metal structures, the N electrode is electrically connected to the N-type semiconductor layer.
  • the first groove and the second groove are made by the same etching process step.
  • the etching method includes dry etching, wet etching or a combination of the two.
  • the first metal structure and the second metal structure are made in the same evaporation process step.
  • the first insulating isolation layer and the second insulating isolation layer are made in the same CVD process.
  • a light emitting diode includes at least: a substrate; an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a transparent conductive layer stacked on the substrate in sequence, and the transparent conductive layer is etched to
  • the N-type semiconductor layer forms the first groove;
  • the P electrode is located on the surface of the transparent conductive layer and is in electrical contact with the P-type semiconductor layer;
  • the N electrode is located in the first groove and is in electrical contact with the N-type semiconductor layer;
  • a first metal structure electrically connected to the N-type semiconductor layer is arranged under the P electrode, and a first insulating isolation layer is provided between the first metal structure and the P electrode.
  • the transparent conductive layer is etched to the N-type semiconductor layer to form a second groove, the first metal structure is disposed in the second groove, and the first metal structure is electrically connected to the N-type semiconductor layer.
  • Conduction; the first insulating isolation layer is wrapped on the surface of the first metal structure, and the P electrode is wrapped on the surface of the first insulating isolation layer.
  • the P electrode and the N electrode and the first metal structure respectively form a first electric field and a second electric field.
  • the second electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode.
  • the manufacturing method of the above-mentioned light-emitting diode includes the following steps:
  • a P electrode and an N electrode are respectively formed on the surface of the first insulating isolation layer and in the second groove, the P electrode is electrically connected to the P type semiconductor layer, and the N electrode is electrically connected to the N type semiconductor layer.
  • a light emitting diode includes at least: a substrate; an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a transparent conductive layer stacked on the substrate in sequence, and the transparent conductive layer is etched to
  • the N-type semiconductor layer forms the first groove;
  • the P electrode is located on the surface of the transparent conductive layer and is in electrical contact with the P-type semiconductor layer;
  • the N electrode is located in the first groove and is in electrical contact with the N-type semiconductor layer;
  • a second metal structure electrically connected to the P-type semiconductor layer is arranged under the N electrode, and a second insulating isolation layer is provided between the second metal structure and the N electrode.
  • the second metal structure is located on the surface of the P-type semiconductor layer on the sidewall of the first groove, and the second metal structure is electrically connected to the P-type semiconductor layer.
  • the second insulating isolation layer wraps the second metal structure and extends to the sidewall of the first groove.
  • the N electrode extends along the surface of the second insulating isolation layer to above the second metal structure.
  • a first electric field and a third electric field are respectively formed between the N electrode and the P electrode and the second metal structure. The third electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode.
  • the manufacturing method of the above-mentioned light-emitting diode includes the following steps:
  • P and N electrodes are made on the surface of the P-type semiconductor layer and in the second groove respectively, the P electrode is electrically connected to the P-type semiconductor layer, and the N electrode extends along the surface of the second insulating isolation layer to above the second metal structure , The N electrode is electrically connected to the N-type semiconductor layer.
  • the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED;
  • the sum of the intensity values of the first electric field and the third electric field in the present invention is equal to N. Therefore, the first electric field intensity between the P electrode and the N electrode is smaller than that between the two in the traditional LED. Therefore, the third electric field can be used to shunt the intensity of the first electric field.
  • the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED;
  • the first electric field in this embodiment can be weakened by using the shunt benefit of the second electric field and the third electric field.
  • the metal migration of the electrode is directly affected by the intensity of the electric field between the two. Therefore, the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a conventional light emitting diode.
  • FIG. 2 is a schematic top view of the structure of a light emitting diode according to an embodiment of the present invention.
  • Fig. 3 is a schematic cross-sectional view of a light emitting diode according to an embodiment of the present invention.
  • 4 to 6 are schematic structural diagrams of a method for manufacturing a light emitting diode according to another embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a cross-sectional structure of a light emitting diode according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a cross-sectional structure of a light emitting diode according to another embodiment of the present invention.
  • a gallium nitride-based III-V compound semiconductor refers to a nitride semiconductor of a group III element of the periodic table including gallium, such as GaN, GaAlN, InGaN, and InAlGaN.
  • gallium such as GaN, GaAlN, InGaN, and InAlGaN.
  • These compound semiconductors can be represented by the chemical formula In x Al y GaN 1-xy , where 0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1, and X+Y ⁇ 1.
  • FIG. 2 shows a schematic top view of the structure of the light-emitting diode of this embodiment
  • FIG. 3 shows a schematic cross-sectional structure of the light-emitting diode of this embodiment.
  • This embodiment discloses a light-emitting diode, which at least includes: a substrate 10; an epitaxial layer laminated on the substrate 10, which includes an N-type semiconductor layer 21, a light-emitting layer 22, a P-type semiconductor layer 23, and a transparent conductive layer 30 in sequence .
  • the material of the substrate 10 can be selected from any one or a combination of Al 2 O 3 , SiC, GaAs, GaN, AlN, GaP, Si, ZnO, and MnO.
  • a sapphire substrate 10 (sapphire substrate) is taken as an example for illustration.
  • the crystal lattice direction may be, for example, (0001), but the present invention does not limit the material and crystal lattice direction of the substrate 10 used. It is also possible to perform patterning processing on the substrate 10 to change the propagation path of light and improve the light-emitting efficiency of the light-emitting element.
  • the P-type semiconductor layer 23, the light-emitting layer 22, and the N-type semiconductor layer 21 are all formed by stacking multiple III-V group compound semiconductor layers, wherein the P-type semiconductor layer 23 and/or the N-type semiconductor layer 21 may have a single-layer structure or Multi-layer structure.
  • the p-type doping impurity type may be Mg, Zn, Ca, Sr, or Ba
  • the n-type doping impurity type may be Si, Ge, or Sn.
  • the present invention does not exclude the equivalent substitution of other elements.
  • each group III compound semiconductor layer is not particularly limited, such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), sputtering, ion plating, Electronic spray method, etc.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • HVPE halide vapor phase epitaxy
  • sputtering ion plating
  • Electronic spray method etc.
  • the present invention adopts the conventional MOCVD method to fabricate on the substrate 10.
  • the light-emitting layer 22 emits light when driven by a voltage, and the color of the light depends on the material of the compound semiconductor layer.
  • the P-type semiconductor layer 23 or the N-type semiconductor layer 21 may be made of gallium nitride-based, gallium arsenide-based or gallium phosphide-based material.
  • the light-emitting layer 22 is a material capable of providing light radiation, and the specific radiation band is between 390-950 nm, such as blue, green, red, yellow, orange, and infrared light.
  • the light-emitting layer 22 can be a single quantum well or a multiple quantum well structure.
  • a buffer layer (not shown in the figure) may be grown between the substrate 10 and the N-type semiconductor layer 21, and a stress relief layer may be grown between the N-type semiconductor layer 21 and the light-emitting layer 22. (Not shown in the figure), and an electron blocking layer (not shown in the figure) is grown between the light-emitting layer 22 and the P-type semiconductor layer 23. It depends on the production needs.
  • the transparent conductive layer 30 is used for spreading current and covers a part of the second conductive type semiconductor layer.
  • the area of the transparent conductive layer 30 is smaller than the area of the second conductive type semiconductor layer.
  • the transparent conductive layer 30 is an indium tin oxide layer.
  • it may also be a zinc oxide layer, a zinc indium tin oxide layer, an indium zinc oxide layer, a zinc tin oxide layer, a gallium indium tin oxide layer, and a gallium oxide layer.
  • the P electrode 71 is electrically connected to the P-type semiconductor layer 23 through the transparent conductive layer 30.
  • the P electrode 71 may include a pad portion and an extension portion.
  • the extension portion is used to expand the current of the pad portion and prevent the current from concentrating on the pad portion.
  • the N electrode 72 is electrically connected to the N-type semiconductor layer 21.
  • a first metal structure 51 electrically connected to the N-type semiconductor layer 21 is provided under the P electrode 71, a first insulating isolation layer 61 is provided between the first metal structure 51 and the P electrode 71, and a first insulating isolation layer 61 is provided under the N electrode 72.
  • the second metal structure 52 electrically connected to the semiconductor layer 23 has a second insulating isolation layer 62 between the second metal structure 52 and the N electrode 72.
  • the first groove 41 and the second groove 42 are provided in the epitaxial layer, which can be formed by an etching method.
  • the etching method can be dry etching, wet etching or a combination of the two. This embodiment Dry etching is used in the process.
  • the opening diameter of the second groove 42 is smaller than the diameter of the P electrode 71. Further, the opening diameter of the second groove 42 is smaller than the diameter of the pad portion of the P electrode 71, and its shape may be cylindrical or V-shaped.
  • the position of the second groove 42 corresponds to the P electrode 71, the first metal structure 51 is disposed in the second groove 42, and there is a gap between the side wall of the second groove 42 and the side wall of the second groove 42, so the two will not be connected. . Since the bottom of the first metal structure 51 is in contact with the N-type semiconductor layer 21, the first metal structure 51 and the N-type semiconductor layer 21 are electrically connected.
  • the top of the first metal structure 51 is higher or flush with or lower than the surface of the P-type semiconductor layer 23. In this embodiment, the top of the first metal structure 51 is preferably higher than the surface of the P-type semiconductor layer 23.
  • the first insulating isolation layer 61 wraps the surface of the first metal structure 51, and can wrap the top and sidewalls of the first metal structure 51, so that the semiconductor layer and the P electrode 71 on the sidewalls of the first metal structure 51 and the second groove 42 are completely insulated isolation.
  • the P electrode 71 wraps the surface of the first insulating isolation layer 61, the middle part of the P electrode 71 is in contact with the first insulating isolation layer 61, and the outer edge is in contact with the transparent conductive layer 30, so that the P electrode 71 can pass through the transparent conductive layer 30 and the P type
  • the semiconductor layer 23 is electrically connected.
  • the N electrode 72 is located in the first groove 41, the second metal structure 52 is located on the surface of the P-type semiconductor layer 23 on the sidewall of the first groove 41, and the second metal structure 52 is electrically connected to the P-type semiconductor layer 23.
  • the second insulating isolation layer 62 wraps the second metal structure 52, includes the top and sidewalls of the second metal structure 52, and extends to the sidewalls of the first groove 41.
  • the second insulating isolation layer 62 extends from the surface of the second metal structure 52 along the semiconductor layer on the sidewall of the first groove 41 to the bottom of the first groove 41, while the N electrode 72 extends along the surface of the second insulating isolation layer 62 to the bottom of the first groove 41.
  • the N electrode 72 is completely insulated and isolated from the semiconductor layer on the sidewall of the first groove 41 and the second metal structure 52 through the second insulating isolation layer 62.
  • first metal structure 51 and the second metal structure 52 are the same or different.
  • the first metal structure 51 and the second metal structure 52 are both a single-layer structure or a multi-layer structure.
  • Both the first metal structure 51 and the second metal structure 52 can be selected from one or a combination of nickel, chromium, aluminum, platinum, silver, gold, and titanium.
  • the first metal structure 51 and the N electrode 72 have the same structure
  • the second metal structure 52 and the P electrode 71 have the same structure.
  • Both the first insulating isolation layer 61 and the second insulating isolation layer 62 may be selected from one or a combination of silicon dioxide, silicon nitride, and aluminum oxide. In this embodiment, it is preferable that the first insulating isolation layer 61 and the second insulating isolation layer 62 are both silicon dioxide layers.
  • the P electrode 71 is electrically connected to the P-type semiconductor layer 23
  • the first metal structure 51 and the N electrode 72 are both electrically connected to the N-type semiconductor layer 21
  • the N electrode 72 is electrically connected to the N-type semiconductor layer. 21 is electrically connected
  • the P electrode 71 and the second metal structure 52 are both electrically connected to the P-type semiconductor layer 23; therefore, a first electric field can be formed between the P electrode 71 and the N electrode 72, and the P electrode 71 and the first A second electric field may also be formed between the metal structures 51, and a third electric field may be formed between the N electrode 72 and the second metal structure 52.
  • the first electric field in this embodiment can be weakened by using the shunting benefit of the second electric field and the third electric field.
  • the metal migration of the N electrode 72 is directly affected by the intensity of the electric field between the two. Therefore, the present invention can reduce the metal mobility and improve the abnormal phenomenon of “dead light” caused by the metal migration of the LED.
  • this embodiment provides a fabrication method, which specifically includes the following steps:
  • step 1) provides a substrate 10 on which an N-type semiconductor layer 21, a light-emitting layer 22, and a P semiconductor layer 23 are sequentially grown on the substrate 10 to form an epitaxial layer.
  • Step 2) Form the first groove 41 and the second groove 42 in the epitaxial layer.
  • the P-type semiconductor layer 23 to the N-type semiconductor layer 21 are etched to form the first groove 41 and the second groove 42, and then the transparent conductive layer 30 is formed on the surface of the P-type semiconductor layer 23;
  • a transparent conductive layer 30 is formed on the surface of the layer 23, and then the transparent conductive layer 30 is etched to the N-type semiconductor layer 21 to form a first groove 41 and a second groove 42.
  • the positions of the first groove 41 and the second groove 42 are opposite, for example, they may be located at the two ends corresponding to the substrate 10, or at the diagonal, so increasing the distance between the two can prolong the current injected by the subsequent electrodes. The path, using light.
  • the first groove 41 and the second groove 42 can be formed by the same etching process step, and they can be formed at the same time.
  • the etching method includes dry etching, wet etching or a combination of the two. This embodiment preferably adopts The dry etching simultaneously etches the first groove and the second groove.
  • a first metal structure 51 is formed in the second groove 42, and a second metal structure 52 is formed on the surface of the P-type semiconductor layer 23.
  • the second metal structure 52 is fabricated on the surface of the P-type semiconductor layer 23 on the sidewall of the first groove 41, and the two are arranged opposite to each other.
  • the purpose of this design is to make the second metal structure 52 and the first metal 51 separate
  • the increase of the distance can extend the path of the current injected by the subsequent electrodes and utilize light emission.
  • the first metal structure 51 and the second metal structure 52 are made in the same step process, and they can be made at the same time by an evaporation method.
  • the first metal structure 51 and the second metal structure 52 may be the same structure, for example, both are a single-layer metal structure or a multi-layer metal structure, and their materials are all from nickel, chromium, aluminum, platinum, silver, gold, and titanium. kind or a combination of several.
  • step 4) a first insulating isolation layer 61 is formed on the surface of the first metal structure 51, the first insulating isolation layer 61 wraps the first metal structure 51; a second insulating isolation layer 62 is formed on the surface of the second metal structure 52 , The second insulating isolation layer 62 wraps the second metal structure 52.
  • the first insulating isolation layer 61 can wrap the top and sidewalls of the first metal structure 51, so that the first metal structure 51 is completely insulated from the epitaxial layer on the sidewalls of the second groove 42; the second insulating isolation layer can also wrap the second The top and side walls of the metal structure 52.
  • the first insulating isolation layer 61 and the second insulating isolation layer 62 may be formed in the same deposition step, and they may be manufactured at the same time.
  • a PECVD method is used to simultaneously deposit an insulating isolation layer 61 and a second insulating isolation layer 62.
  • the materials of the first insulating isolation layer 61 and the second insulating isolation layer 62 may be the same, for example, both are selected from one or a combination of silicon dioxide, silicon nitride, and aluminum oxide. In this embodiment, it is preferable that both materials are silica.
  • step 5 P electrode 71 is formed on the surface of the first insulating isolation layer 61, and the P electrode 71 is electrically connected to the P-type semiconductor layer 23; an N electrode 72 is formed in the second groove 42 The N electrode 72 extends along the surface of the second insulating isolation layer 62 to above the second metal structure 52, and the N electrode 72 is electrically connected to the N-type semiconductor layer 21.
  • the light-emitting diode provided by this embodiment includes: a substrate 10; an epitaxial layer laminated on the substrate 10, wherein the epitaxial layer includes an N-type semiconductor layer 21, a light-emitting layer 22, and a P-type semiconductor layered in sequence. Layer 23; and a transparent conductive layer 30.
  • the specific structure of each layer has been described in detail in Embodiment 1, and will not be repeated here.
  • a first metal structure 51 electrically connected to the N-type semiconductor layer 21 is provided under the P electrode 71, and a first insulating isolation layer 61 is provided between the first metal structure 51 and the P electrode 71.
  • the second groove 42 is formed by etching in the epitaxial layer.
  • the etching method may be dry etching, wet etching or a combination of the two. In this embodiment, dry etching is used, and the second groove
  • the diameter of the opening of 42 is smaller than the diameter of the P electrode 71. Further, the diameter of the opening of the second groove 42 is smaller than the diameter of the pad portion of the P electrode 71, and its shape may be cylindrical or V-shaped.
  • the position of the second groove 42 corresponds to the P electrode 71, the first metal structure 51 is disposed in the second groove 42, and there is a gap between the side wall of the second groove 42 and the side wall of the second groove 42, so the two will not conduct . Since the bottom of the first metal structure 51 is in contact with the N-type semiconductor layer 21, the first metal structure 51 and the N-type semiconductor layer 21 are electrically connected.
  • the top of the first metal structure 51 is higher or flush with or lower than the surface of the P-type semiconductor layer 23. In this embodiment, the top of the first metal structure 51 is preferably higher than the surface of the P-type semiconductor layer 23.
  • the first insulating isolation layer 61 wraps the surface of the first metal structure 51, and can wrap the top and sidewalls of the first metal structure 51, so that the semiconductor layer and the P electrode 71 on the sidewalls of the first metal structure 51 and the second groove 42 are completely insulated isolation.
  • the P electrode 71 wraps the surface of the first insulating isolation layer 61, the middle part of the P electrode 71 is in contact with the first insulating isolation layer 61, and the outer edge is in contact with the transparent conductive layer 30, so that the P electrode 71 can pass through the transparent conductive layer 30 and the P type
  • the semiconductor layer 23 is electrically connected.
  • the P electrode 71 is electrically connected to the P-type semiconductor layer 23
  • the first metal structure 51 and the N electrode 72 are both electrically connected to the N-type semiconductor layer 21. Therefore, a first electric field can be formed between the P electrode 71 and the N electrode 72, and a second electric field can also be formed between the P electrode 71 and the first metal structure 51. Therefore, compared with the traditional LED with only a pair of P electrode 71 and N electrode 72, the first electric field in this embodiment can be weakened by using the shunting benefit of the second electric field.
  • the metal migration of 72 is directly affected by the intensity of the electric field between the two. Therefore, the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED.
  • this embodiment provides a fabrication method, which specifically includes the following steps:
  • a substrate 10 is provided, and an N-type semiconductor layer 21, a light-emitting layer 22, and a P semiconductor layer 23 are sequentially grown on the substrate 10 to form an epitaxial layer;
  • the P-type semiconductor layer 23 to the N-type semiconductor layer 21 are etched to form the first groove 41 and the second groove 42, and then the transparent conductive layer 30 is formed on the surface of the P-type semiconductor layer 23; A transparent conductive layer 30 is formed on the surface of the layer 23, and then the transparent conductive layer 30 is etched to the N-type semiconductor layer 21 to form a first groove 41 and a second groove 42.
  • a first insulating isolation layer 61 is formed on the surface of the first metal structure 51, and the first insulating isolation layer 61 wraps the first metal structure 51;
  • P-electrodes 71 and N-electrodes 72 are formed on the surface of the first insulating isolation layer 61 and in the second groove 42 respectively.
  • the P-electrodes 71 are electrically connected to the P-type semiconductor layer 23, and the N-electrodes 72 are electrically connected to the N-type semiconductor layer 21. Sexual connection.
  • the first groove 41 and the second groove 42 are formed by the same etching process, and the etching method may be dry etching, wet etching or a combination of the two. In this embodiment, dry etching is preferred. Etching.
  • the second groove 42 may have an L-shaped step shape. In this embodiment, the first groove 41 is formed while the second groove 42 is etched, and no process steps are added, so the LED manufacturing cost will not increase.
  • the light-emitting diode in this embodiment includes: a substrate 10; an epitaxial layer laminated on the substrate 10, wherein the epitaxial layer includes an N-type semiconductor layer 21, a light-emitting layer 22, and a P-type semiconductor layered in sequence. Layer 23; and a transparent conductive layer 30.
  • the specific structure of each layer has been described in detail in Embodiment 1, and will not be repeated here.
  • a second metal structure 52 electrically connected to the P-type semiconductor layer 23 is provided under the N electrode 72, and a second insulating isolation layer 62 is provided between the second metal structure 52 and the N electrode 72.
  • the second metal structure 52 is located on the surface of the P-type semiconductor layer 23 on the sidewall of the first groove 41, and the second metal structure 52 is electrically connected to the P-type semiconductor layer 23.
  • the second insulating isolation layer 62 wraps the second metal structure 52, includes the top and sidewalls of the second metal structure 52, and extends to the sidewalls of the first groove 41.
  • the second insulating isolation layer 62 extends from the surface of the second metal structure 52 along the semiconductor layer on the sidewall of the first groove 41 to the bottom of the first groove 41, while the N electrode 72 extends along the surface of the second insulating isolation layer 62 to the bottom of the first groove 41. Above the two metal structures 52, the N electrode 72 is completely insulated and isolated from the semiconductor layer on the sidewall of the first groove 41 and the second metal structure 52 through the second insulating isolation layer 62.
  • the N electrode 72 is electrically connected to the N-type semiconductor layer 21, and both the P electrode 71 and the second metal structure 52 are electrically connected to the P-type semiconductor layer 23, the P electrode 71 and the N electrode 72 can form a first With an electric field, a third electric field can also be formed between the N electrode 72 and the second metal structure 52.
  • the present invention In the traditional LED structure, there is only a pair of P electrode 71 and N electrode 72. Assuming that the electric field strength between the P electrode 71 and the N electrode 72 is N, the present invention has the first electric field and the third electric field in comparison with the traditional LED structure. The sum of the intensity values of is equal to N. Therefore, the intensity of the first electric field between the P electrode 71 and the N electrode 72 is smaller than the intensity between the two in a conventional LED, so that the intensity of the first electric field can be shunted by the third electric field. In addition, because the metal migration of the P electrode 71 and/or the N electrode 72 is directly affected by the electric field strength between the two, the present invention can reduce the metal mobility and improve the abnormal phenomenon of “dead light” caused by the metal migration of the LED.
  • this embodiment provides a fabrication method, which specifically includes the following steps:
  • a substrate 10 is provided, and an N-type semiconductor layer 21, a light-emitting layer 22, and a P semiconductor layer are sequentially grown on the substrate 10 to form an epitaxial layer;
  • the P-type semiconductor layer 23 to the N-type semiconductor layer 21 are etched to form the first groove 41, and then a transparent conductive layer 30 is formed on the surface of the P-type semiconductor layer 23; or, a transparent conductive layer is formed on the surface of the P-type semiconductor layer 23 first. Then, the transparent conductive layer 30 is etched to the N-type semiconductor layer 21 to form the first groove 41.
  • the comparison of this embodiment is not particularly limited.
  • P-electrodes 71 and N-electrodes 72 are fabricated on the surface of the P-type semiconductor layer 23 and in the second groove 42 respectively.
  • the P-electrodes 71 are electrically connected to the P-type semiconductor layer 23, and the N-electrodes 72 are along the surface of the second insulating isolation layer 62 Extending above the second metal structure 52, the N electrode 72 is electrically connected to the N-type semiconductor layer 21.

Abstract

A light-emitting diode and a manufacturing method therefor. Said method comprises: providing a first metal structure (51) and/or a second metal structure (52) below a P electrode (71) and/or an N electrode (72), the first metal structure (51) being insulated from the P electrode (71), and the second metal structure (52) being insulated from the N electrode (72), so as to form a first electric field between the P electrode (71) and the N electrode (72), form a second electric field between the P electrode (71) and the first metal structure (51), and form a third electric field between the N electrode (72) and the second metal structure (52). The first electric field is weakened due to the shunting of the second electric field and/or third electric field, further reducing metal migration in the P and N electrodes, thereby improving the short-circuit "light damage" abnormity caused by the metal migration.

Description

发光二极管及其制作方法Light-emitting diode and manufacturing method thereof 技术领域Technical field
本发明属于半导体领域，尤其涉及改善金属迁移的发光二极管及其制作方法。The invention belongs to the field of semiconductors, and particularly relates to a light emitting diode for improving metal migration and a manufacturing method thereof.
背景技术Background technique
LED芯片因其高亮度、低电压、低能耗、寿命长等优点广泛的应用在照明、户内外显示屏、背光源、显示灯等各个领域。所面临的使用条件和环境各种各样，尤其是在户内外显示屏使用环境更加严苛。在显示屏终端应用过程中受到高温、水汽、化学腐蚀等环境影响。芯片通电点亮(正向电流)及关闭(负向电压)的状态下，金属元素被电解成离子状态，在正向电流及负向电压的电场作用下发生迁移的现象，导致死灯异常。LED chips are widely used in various fields such as lighting, indoor and outdoor display screens, backlight sources, and display lamps due to their advantages of high brightness, low voltage, low energy consumption, and long life. The use conditions and environments are various, especially the use environment of indoor and outdoor display screens is more stringent. It is affected by high temperature, water vapor, chemical corrosion and other environmental impacts during the terminal application of the display. When the chip is powered on (positive current) and off (negative voltage), the metal elements are electrolyzed into an ion state, and migration occurs under the action of the electric field of the positive current and the negative voltage, resulting in a dead lamp abnormality.
参看附图1，传统的发光二极管(Light-Emitting diode，LED)芯片结构通常包括衬底10’、N型层21’、发光层22’、P型层23’、透明导电层30’、金属电极，金属电极包括N电极41’和P电极42’，其中N型层21’提供的电子和P型层23’提供的空穴在发光层22’中复合发光。Referring to FIG. 1, the traditional light-emitting diode (Light-Emitting Diode, LED) chip structure usually includes a substrate 10', an N-type layer 21', a light-emitting layer 22', a P-type layer 23', a transparent conductive layer 30', and a metal The metal electrode includes an N electrode 41' and a P electrode 42', wherein the electrons provided by the N-type layer 21' and the holes provided by the P-type layer 23' recombine and emit light in the light-emitting layer 22'.
由于P/N电极41’、42’之间形成电场，LED芯粒在使用过程中，电极下的金属受电场作用发生金属迁移现象。当金属不断迁移后，P/N电极之间直接导通形成短路，出现“死灯”的异常现象。Since an electric field is formed between the P/N electrodes 41' and 42', during the use of the LED chip, the metal under the electrodes is subjected to the electric field to cause metal migration. When the metal continues to migrate, the P/N electrodes are directly connected to form a short circuit, and the abnormal phenomenon of "dead light" appears.
发明概述Summary of the invention
技术问题technical problem
问题的解决方案The solution to the problem
技术解决方案Technical solutions
为了改善金属迁移的问题，本发明提供了一种利用位于P电极和/或N电极下方的金属结构通过分流而削弱P电极和N电极之间的电场强度，从而改善电极中金属迁移的问题。具体的技术方案如下：In order to improve the problem of metal migration, the present invention provides a metal structure located under the P electrode and/or N electrode to weaken the electric field strength between the P electrode and the N electrode through shunting, thereby improving the problem of metal migration in the electrode. The specific technical solutions are as follows:
根据本发明的第一方面，发光二极管，至少包括：衬底；层叠于所述衬底上的外延层，所述外延层包括依次层叠的N型半导体层、发光层和P型半导体层，刻蚀 外延层露出N型半导体层形成第一凹槽；P电极，与P型半导体层电性连接；N电极，位于第一凹槽内，与N型半导体层电性连接；其特征在于：所述P电极下方设置与N型半导体层电性连接的第一金属结构，第一金属结构与P电极之间具有第一绝缘隔离层，所述N电极下方设置与P型半导体层电性连接的第二金属结构，第二金属结构与N电极之间具有第二绝缘隔离层。According to the first aspect of the present invention, a light emitting diode includes at least: a substrate; an epitaxial layer stacked on the substrate, the epitaxial layer including an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked in sequence. The epitaxial layer is etched to expose the N-type semiconductor layer to form a first groove; the P electrode is electrically connected to the P-type semiconductor layer; the N electrode is located in the first groove and is electrically connected to the N-type semiconductor layer; A first metal structure electrically connected to the N-type semiconductor layer is provided below the P electrode, a first insulating isolation layer is provided between the first metal structure and the P electrode, and a first metal structure electrically connected to the P-type semiconductor layer is provided below the N electrode. The second metal structure has a second insulating isolation layer between the second metal structure and the N electrode.
在本发明的一些实施例中，刻蚀所述P型半导体层至N型半导体层形成第二凹槽，第一金属结构设置于第二凹槽内，第一金属结构与N型半导体层电性导通；所述第一绝缘隔离层包裹第一金属结构表面，所述P电极包裹第一绝缘隔离层表面。In some embodiments of the present invention, the P-type semiconductor layer is etched to the N-type semiconductor layer to form a second groove, the first metal structure is disposed in the second groove, and the first metal structure is electrically connected to the N-type semiconductor layer. Sexual conduction; the first insulating isolation layer wraps the surface of the first metal structure, and the P electrode wraps the surface of the first insulating isolation layer.
所述第二金属结构位于第一凹槽侧壁的P型半导体层表面，第二金属结构与P型半导体层电性导通。所述第二绝缘隔离层包裹第二金属结构，并延伸至第一凹槽的侧壁。所述N电极沿第二绝缘隔离层表面延伸至第二金属结构的上方。The second metal structure is located on the surface of the P-type semiconductor layer on the sidewall of the first groove, and the second metal structure is electrically connected to the P-type semiconductor layer. The second insulating isolation layer wraps the second metal structure and extends to the sidewall of the first groove. The N electrode extends along the surface of the second insulating isolation layer to above the second metal structure.
所述P电极与N电极和第一金属结构分别形成第一电场和第二电场，第二电场削弱第一电场的强度，降低P电极和N电极之间的金属迁移。所述N电极与P电极和第二金属结构之间分别形成第一电场和第三电场，第三电场削弱第一电场的强度，降低P电极和N电极之间的金属迁移。The P electrode and the N electrode and the first metal structure respectively form a first electric field and a second electric field. The second electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode. A first electric field and a third electric field are respectively formed between the N electrode and the P electrode and the second metal structure. The third electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode.
其中，所述第二凹槽的开口直径小于P电极的直径；所述第一金属结构的顶部高于或齐平于或低于P型半导体层的表面；第二凹槽的形状为圆柱形或者V形。所述第一金属结构和第二金属结构相同或者不同。所述第一金属结构和第二金属结构均为单层结构或者多层结构。所述第一金属结构和第二金属结构均选自镍、铬、铝、铂、银、金、钛中的一种或者几种的组合。所述第一绝缘隔离层和第二绝缘隔离层均选自二氧化硅、氮化硅、氧化铝中的一种或者几种的组合。Wherein, the opening diameter of the second groove is smaller than the diameter of the P electrode; the top of the first metal structure is higher or flush with or lower than the surface of the P-type semiconductor layer; the shape of the second groove is cylindrical Or V-shaped. The first metal structure and the second metal structure are the same or different. The first metal structure and the second metal structure are both a single-layer structure or a multi-layer structure. The first metal structure and the second metal structure are both selected from one or a combination of nickel, chromium, aluminum, platinum, silver, gold, and titanium. The first insulating isolation layer and the second insulating isolation layer are both selected from one or a combination of silicon dioxide, silicon nitride, and aluminum oxide.
进一步地，所述P型半导体层表面还设置有透明导电层。Further, a transparent conductive layer is also provided on the surface of the P-type semiconductor layer.
根据本发明的第二方面，上述发光二极管的制作方法，包括如下步骤：According to the second aspect of the present invention, the manufacturing method of the above-mentioned light-emitting diode includes the following steps:
1)提供一衬底，于所述衬底上依次生长N型半导体层、发光层和P半导体层，形成外延层；1) Provide a substrate on which an N-type semiconductor layer, a light-emitting layer and a P semiconductor layer are sequentially grown on the substrate to form an epitaxial layer;
2)于所述外延层内制作形成第一凹槽和第二凹槽，所述第一凹槽和第二凹槽的 底部均位于N型半导体层内；2) Forming a first groove and a second groove in the epitaxial layer, and the bottoms of the first groove and the second groove are both located in the N-type semiconductor layer;
3)于所述第二凹槽内制作第一金属结构，于所述P型半导体层表面制作第二金属结构；3) Fabricating a first metal structure in the second groove, and fabricating a second metal structure on the surface of the P-type semiconductor layer;
4)于所述第一金属结构表面制作第一绝缘隔离层，第一绝缘隔离层包裹第一金属结构；于所述第二金属结构表面制作第二绝缘隔离层，第二绝缘隔离层包裹第二金属结构；4) A first insulating isolation layer is made on the surface of the first metal structure, and the first insulating isolation layer wraps the first metal structure; a second insulating isolation layer is made on the surface of the second metal structure, and the second insulating isolation layer wraps the first metal structure. Two metal structure;
5)于所述第一绝缘隔离层表面制作P电极，P电极与P型半导体层电性连接；于所述第二凹槽内制作N电极，N电极沿第二绝缘隔离层表面延伸至第二金属结构的上方，N电极与N型半导体层电性连接。5) A P electrode is made on the surface of the first insulating isolation layer, and the P electrode is electrically connected to the P-type semiconductor layer; an N electrode is made in the second groove, and the N electrode extends along the surface of the second insulating isolation layer to the first Above the two metal structures, the N electrode is electrically connected to the N-type semiconductor layer.
在本发明的一些实施例中，所述第一凹槽和第二凹槽为同一刻蚀工艺步骤制成。所述的刻蚀方法包括干法刻蚀、湿法刻蚀或者两者的组合。所述第一金属结构和第二金属结构为同一蒸镀工艺步骤制成。所述第一绝缘隔离层和第二绝缘隔离层为同一CVD工艺步骤制成。In some embodiments of the present invention, the first groove and the second groove are made by the same etching process step. The etching method includes dry etching, wet etching or a combination of the two. The first metal structure and the second metal structure are made in the same evaporation process step. The first insulating isolation layer and the second insulating isolation layer are made in the same CVD process.
根据本发明的第三个方面，发光二极管，至少包括：衬底；依次层叠于所述衬底上的N型半导体层、发光层、P型半导体层和透明导电层，刻蚀透明导电层至N型半导体层形成第一凹槽；P电极，位于透明导电层表面，与P型半导体层电性接触；N电极，位于第一凹槽内，与N型半导体层电性接触；其特征在于：所述P电极下方设置与N型半导体层电性连接的第一金属结构，第一金属结构与P电极之间具有第一绝缘隔离层。According to the third aspect of the present invention, a light emitting diode includes at least: a substrate; an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a transparent conductive layer stacked on the substrate in sequence, and the transparent conductive layer is etched to The N-type semiconductor layer forms the first groove; the P electrode is located on the surface of the transparent conductive layer and is in electrical contact with the P-type semiconductor layer; the N electrode is located in the first groove and is in electrical contact with the N-type semiconductor layer; : A first metal structure electrically connected to the N-type semiconductor layer is arranged under the P electrode, and a first insulating isolation layer is provided between the first metal structure and the P electrode.
在本发明的一些实施例中，刻蚀所述透明导电层至N型半导体层形成第二凹槽，第一金属结构设置于第二凹槽内，第一金属结构与N型半导体层电性导通；所述第一绝缘隔离层包裹于第一金属结构表面，所述P电极包裹于第一绝缘隔离层表面。所述P电极与N电极和第一金属结构分别形成第一电场和第二电场，第二电场削弱第一电场的强度，降低P电极和N电极之间的金属迁移。In some embodiments of the present invention, the transparent conductive layer is etched to the N-type semiconductor layer to form a second groove, the first metal structure is disposed in the second groove, and the first metal structure is electrically connected to the N-type semiconductor layer. Conduction; the first insulating isolation layer is wrapped on the surface of the first metal structure, and the P electrode is wrapped on the surface of the first insulating isolation layer. The P electrode and the N electrode and the first metal structure respectively form a first electric field and a second electric field. The second electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode.
根据本发明的第四个方面，上述发光二极管的制作方法，包括如下步骤：According to the fourth aspect of the present invention, the manufacturing method of the above-mentioned light-emitting diode includes the following steps:
1)提供一衬底，于所述衬底上依次生长N型半导体层、发光层和P半导体层，形成外延层；1) Provide a substrate on which an N-type semiconductor layer, a light-emitting layer and a P semiconductor layer are sequentially grown on the substrate to form an epitaxial layer;
2)于所述外延层内制作第一凹槽和第二凹槽，所述第一凹槽和第二凹槽的底部 均位于N型半导体层内；2) Making a first groove and a second groove in the epitaxial layer, and the bottoms of the first groove and the second groove are both located in the N-type semiconductor layer;
3)于所述第二凹槽内制作第一金属结构；3) Making a first metal structure in the second groove;
4)于所述第一金属结构表面制作第一绝缘隔离层，第一绝缘隔离层包裹第一金属结构；4) Making a first insulating isolation layer on the surface of the first metal structure, and the first insulating isolation layer wraps the first metal structure;
5)分别于所述第一绝缘隔离层表面和第二凹槽内制作P电极和N电极，所述P电极与P型半导体层电性连接，N电极与N型半导体层电性连接。5) A P electrode and an N electrode are respectively formed on the surface of the first insulating isolation layer and in the second groove, the P electrode is electrically connected to the P type semiconductor layer, and the N electrode is electrically connected to the N type semiconductor layer.
根据本发明的第五个方面，发光二极管，至少包括：衬底；依次层叠于所述衬底上的N型半导体层、发光层、P型半导体层和透明导电层，刻蚀透明导电层至N型半导体层形成第一凹槽；P电极，位于透明导电层表面，与P型半导体层电性接触；N电极，位于第一凹槽内，与N型半导体层电性接触；其特征在于：所述N电极下方设置与P型半导体层电性连接的第二金属结构，第二金属结构与N电极之间具有第二绝缘隔离层。According to a fifth aspect of the present invention, a light emitting diode includes at least: a substrate; an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a transparent conductive layer stacked on the substrate in sequence, and the transparent conductive layer is etched to The N-type semiconductor layer forms the first groove; the P electrode is located on the surface of the transparent conductive layer and is in electrical contact with the P-type semiconductor layer; the N electrode is located in the first groove and is in electrical contact with the N-type semiconductor layer; : A second metal structure electrically connected to the P-type semiconductor layer is arranged under the N electrode, and a second insulating isolation layer is provided between the second metal structure and the N electrode.
在本发明的一些实施例中，所述第二金属结构位于第一凹槽侧壁的P型半导体层表面，第二金属结构与P型半导体层电性导通。所述第二绝缘隔离层包裹第二金属结构，并延伸至第一凹槽的侧壁。所述N电极沿第二绝缘隔离层表面延伸至第二金属结构的上方。所述N电极与P电极和第二金属结构之间分别形成第一电场和第三电场，第三电场削弱第一电场的强度，降低P电极和N电极之间的金属迁移。In some embodiments of the present invention, the second metal structure is located on the surface of the P-type semiconductor layer on the sidewall of the first groove, and the second metal structure is electrically connected to the P-type semiconductor layer. The second insulating isolation layer wraps the second metal structure and extends to the sidewall of the first groove. The N electrode extends along the surface of the second insulating isolation layer to above the second metal structure. A first electric field and a third electric field are respectively formed between the N electrode and the P electrode and the second metal structure. The third electric field weakens the strength of the first electric field and reduces metal migration between the P electrode and the N electrode.
根据本发明的第六个方面，上述发光二极管的制作方法，包括如下步骤：According to the sixth aspect of the present invention, the manufacturing method of the above-mentioned light-emitting diode includes the following steps:
1)提供一衬底，于所述衬底上依次生长N型半导体层、发光层和P半导体层，形成外延层；1) Provide a substrate on which an N-type semiconductor layer, a light-emitting layer and a P semiconductor layer are sequentially grown on the substrate to form an epitaxial layer;
2)于所述外延层内制作第一凹槽，第一凹槽的底部位于N型半导体层内；2) Making a first groove in the epitaxial layer, and the bottom of the first groove is located in the N-type semiconductor layer;
3)于所述第一凹槽侧壁的P型半导体层表面制作第二金属结构；3) Fabricating a second metal structure on the surface of the P-type semiconductor layer on the sidewall of the first groove;
4)于所述第二金属结构表面制作第二绝缘隔离层；4) Fabricating a second insulating isolation layer on the surface of the second metal structure;
5)分别于P型半导体层表面和第二凹槽内制作P电极和N电极，P电极与P型半导体层电性连接，N电极沿第二绝缘隔离层表面延伸至第二金属结构的上方，N电极与N型半导体层电性连接。5) P and N electrodes are made on the surface of the P-type semiconductor layer and in the second groove respectively, the P electrode is electrically connected to the P-type semiconductor layer, and the N electrode extends along the surface of the second insulating isolation layer to above the second metal structure , The N electrode is electrically connected to the N-type semiconductor layer.
发明的有益效果The beneficial effects of the invention
有益效果Beneficial effect
本发明至少具有以下有益效果：The present invention has at least the following beneficial effects:
1)本发明与传统的LED结构相比，第一电场和第二电场的强度值总和等于N，因此，P电极和N电极之间的第一电场强度则小于传统的LED中两者之间的强度，从而可以利用第二电场分流第一电场的强度。又因为P电极和/或N电极的金属迁移受两者之间电场强度的直接影响，因此本发明可以降低金属迁移率，改善LED因金属迁移导致的“死灯”异常现象；1) Compared with the traditional LED structure, the sum of the intensity values of the first electric field and the second electric field is equal to N. Therefore, the first electric field intensity between the P electrode and the N electrode is smaller than that between the two in the traditional LED. Therefore, the second electric field can be used to shunt the intensity of the first electric field. In addition, because the metal migration of the P electrode and/or the N electrode is directly affected by the electric field strength between the two, the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED;
2)本发明与传统的LED结构相比，第一电场和第三电场的强度值总和等于N，因此，P电极和N电极之间的第一电场强度则小于传统的LED中两者之间的强度，从而可以利用第三电场分流第一电场的强度。又因为P电极和/或N电极的金属迁移受两者之间电场强度的直接影响，因此本发明可以降低金属迁移率，改善LED因金属迁移导致的“死灯”异常现象；2) Compared with the traditional LED structure, the sum of the intensity values of the first electric field and the third electric field in the present invention is equal to N. Therefore, the first electric field intensity between the P electrode and the N electrode is smaller than that between the two in the traditional LED. Therefore, the third electric field can be used to shunt the intensity of the first electric field. In addition, because the metal migration of the P electrode and/or the N electrode is directly affected by the electric field strength between the two, the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED;
3)与传统的只有一对P电极和N电极的LED相比，本实施例中的第一电场可以利用第二电场和第三电场的分流效益而得到削弱，又因为P电极和/或N电极的金属迁移受两者之间电场强度的直接影响，因此本发明可以降低金属迁移率，改善LED因金属迁移导致的“死灯”异常现象。3) Compared with the traditional LED with only a pair of P electrode and N electrode, the first electric field in this embodiment can be weakened by using the shunt benefit of the second electric field and the third electric field. The metal migration of the electrode is directly affected by the intensity of the electric field between the two. Therefore, the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED.
对附图的简要说明Brief description of the drawings
附图说明Description of the drawings
图1是依据传统的发光二极管剖视结构示意图。FIG. 1 is a schematic diagram of a cross-sectional structure of a conventional light emitting diode.
图2是依据本发明的一个实施例的发光二极管俯视结构示意图。FIG. 2 is a schematic top view of the structure of a light emitting diode according to an embodiment of the present invention.
图3是依据本发明的一个实施例的发光二极管剖视结构示意图。Fig. 3 is a schematic cross-sectional view of a light emitting diode according to an embodiment of the present invention.
图4～6是依据本发明的另一个实施例的发光二极管制作方法的结构示意图。4 to 6 are schematic structural diagrams of a method for manufacturing a light emitting diode according to another embodiment of the present invention.
图7是依据本发明的另一个实施例的发光二极管剖视结构示意图。FIG. 7 is a schematic diagram of a cross-sectional structure of a light emitting diode according to another embodiment of the present invention.
图8是依据本发明的另一个实施例的发光二极管剖视结构示意图。FIG. 8 is a schematic diagram of a cross-sectional structure of a light emitting diode according to another embodiment of the present invention.
发明实施例Invention embodiment
本发明的实施方式Embodiments of the present invention
以下结合附图和具体实施例对本发明进行详细说明。需说明的是，本发明的附图均采用非常简化的非精准比例，仅用以方便、明晰的辅助说明本发明。The present invention will be described in detail below with reference to the drawings and specific embodiments. It should be noted that the drawings of the present invention all adopt very simplified non-precision ratios, which are only used to facilitate and clearly assist in explaining the present invention.
关于本发明，氮化镓系III-V族化合物半导体是指例如GaN、GaAlN、InGaN、InAlGaN等的包括镓在内的周期表第III族元素的氮化物半导体。这些化合物半导体可用化学式In xAl yGaN 1-x-y表示，其中0≤X≤1、0≤Y≤1，X+Y≤1。 Regarding the present invention, a gallium nitride-based III-V compound semiconductor refers to a nitride semiconductor of a group III element of the periodic table including gallium, such as GaN, GaAlN, InGaN, and InAlGaN. These compound semiconductors can be represented by the chemical formula In x Al y GaN 1-xy , where 0≤X≤1, 0≤Y≤1, and X+Y≤1.
实施例1Example 1
参看附图2和3，其中图2示出了本实施例发光二极管的俯视结构示意图；图3示出了本实施例发光二极管的剖视结构示意图。Referring to FIGS. 2 and 3, FIG. 2 shows a schematic top view of the structure of the light-emitting diode of this embodiment; FIG. 3 shows a schematic cross-sectional structure of the light-emitting diode of this embodiment.
本实施例公开了发光二极管，至少包括：衬底10；层叠于衬底10上的外延层，其包括依次的N型半导体层21、发光层22、P型半导体层23，以及透明导电层30。This embodiment discloses a light-emitting diode, which at least includes: a substrate 10; an epitaxial layer laminated on the substrate 10, which includes an N-type semiconductor layer 21, a light-emitting layer 22, a P-type semiconductor layer 23, and a transparent conductive layer 30 in sequence .
其中，衬底10的材质可以选自Al 2O 3、SiC、GaAs、GaN、AlN、GaP、Si、ZnO、MnO中的任意一种或者几种的组合。本实施例以蓝宝石衬底10(sapphire substrate)为例说明，晶格方向可以例如为(0001)，但本发明不限制所使用的衬底10材质与晶格方向。也可以对衬底10进行图形化处理，改变光的传播路径，提升发光元件的出光效率。 The material of the substrate 10 can be selected from any one or a combination of Al 2 O 3 , SiC, GaAs, GaN, AlN, GaP, Si, ZnO, and MnO. In this embodiment, a sapphire substrate 10 (sapphire substrate) is taken as an example for illustration. The crystal lattice direction may be, for example, (0001), but the present invention does not limit the material and crystal lattice direction of the substrate 10 used. It is also possible to perform patterning processing on the substrate 10 to change the propagation path of light and improve the light-emitting efficiency of the light-emitting element.
P型半导体层23、发光层22和N型半导体层21均是由多层III-V族化合物半导体层层叠形成，其中P型半导体层23和/或N型半导体层21可以具有单层结构或多层结构。p型掺杂杂质类型可以为Mg、Zn、Ca、Sr、或者Ba，n型掺杂杂质类型可以为Si、Ge、或者Sn，本发明不排除其他的元素等效替代的掺杂。The P-type semiconductor layer 23, the light-emitting layer 22, and the N-type semiconductor layer 21 are all formed by stacking multiple III-V group compound semiconductor layers, wherein the P-type semiconductor layer 23 and/or the N-type semiconductor layer 21 may have a single-layer structure or Multi-layer structure. The p-type doping impurity type may be Mg, Zn, Ca, Sr, or Ba, and the n-type doping impurity type may be Si, Ge, or Sn. The present invention does not exclude the equivalent substitution of other elements.
形成每个III族化合物半导体层的方法没有特别限制，例如金属有机化学气相沉积(MOCVD)，分子束外延法(MBE)、卤化物气相外延法(HVPE法)、溅射法，离子镀法，电子喷淋法等。本发明采用常规的MOCVD法于衬底10上制作而成。发光层22受电压驱动时会发出光线，该光线的颜色取决于化合物半导体层的材料。P型半导体层23或N型半导体层21可以为氮化镓基、砷化镓基或者磷化镓基材质。发光层22为能够提供光辐射的材料，具体的辐射波段介于390～950nm，如蓝、绿、红、黄、橙、红外光，发光层22可以为单量子阱或多量子阱结构。The method of forming each group III compound semiconductor layer is not particularly limited, such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), sputtering, ion plating, Electronic spray method, etc. The present invention adopts the conventional MOCVD method to fabricate on the substrate 10. The light-emitting layer 22 emits light when driven by a voltage, and the color of the light depends on the material of the compound semiconductor layer. The P-type semiconductor layer 23 or the N-type semiconductor layer 21 may be made of gallium nitride-based, gallium arsenide-based or gallium phosphide-based material. The light-emitting layer 22 is a material capable of providing light radiation, and the specific radiation band is between 390-950 nm, such as blue, green, red, yellow, orange, and infrared light. The light-emitting layer 22 can be a single quantum well or a multiple quantum well structure.
为了提高半导体层的生长质量和性能，还可以在衬底10和N型半导体层21之间生长缓冲层(图中未显示)，以及N型半导体层21和发光层22之间生长应力释放 层(图中未显示)，以及发光层22和P型半导体层23之间生长电子阻挡层(图中未显示)。具体根据生产需要而定。In order to improve the growth quality and performance of the semiconductor layer, a buffer layer (not shown in the figure) may be grown between the substrate 10 and the N-type semiconductor layer 21, and a stress relief layer may be grown between the N-type semiconductor layer 21 and the light-emitting layer 22. (Not shown in the figure), and an electron blocking layer (not shown in the figure) is grown between the light-emitting layer 22 and the P-type semiconductor layer 23. It depends on the production needs.
透明导电层30，用于扩展电流，其覆盖于部分的第二导电型半导体层上，透明导电层30的面积小于第二导电型半导体层的面积。本实施例中透明导电层30为氧化铟锡层，在其他实施例中也可以为氧化锌层、氧化锌铟锡层、氧化铟锌层、氧化锌锡层、氧化镓铟锡层、氧化镓铟层、氧化镓锌层、掺杂铝的氧化锌层或掺杂氟的氧化锡层中的一种或者几种的组合。The transparent conductive layer 30 is used for spreading current and covers a part of the second conductive type semiconductor layer. The area of the transparent conductive layer 30 is smaller than the area of the second conductive type semiconductor layer. In this embodiment, the transparent conductive layer 30 is an indium tin oxide layer. In other embodiments, it may also be a zinc oxide layer, a zinc indium tin oxide layer, an indium zinc oxide layer, a zinc tin oxide layer, a gallium indium tin oxide layer, and a gallium oxide layer. One or a combination of indium layer, gallium zinc oxide layer, aluminum-doped zinc oxide layer, or fluorine-doped tin oxide layer.
P电极71，通过透明导电层30与P型半导体层23电性连接，P电极71可以包括焊盘部和延伸部，延伸部用于扩展焊盘部的电流，防止电流聚集于焊盘部。N电极72与N型半导体层21电性连接。The P electrode 71 is electrically connected to the P-type semiconductor layer 23 through the transparent conductive layer 30. The P electrode 71 may include a pad portion and an extension portion. The extension portion is used to expand the current of the pad portion and prevent the current from concentrating on the pad portion. The N electrode 72 is electrically connected to the N-type semiconductor layer 21.
其中，P电极71下方设置与N型半导体层21电性连接的第一金属结构51，第一金属结构51与P电极71之间具有第一绝缘隔离层61，N电极72下方设置与P型半导体层23电性连接的第二金属结构52，第二金属结构52与N电极72之间具有第二绝缘隔离层62。A first metal structure 51 electrically connected to the N-type semiconductor layer 21 is provided under the P electrode 71, a first insulating isolation layer 61 is provided between the first metal structure 51 and the P electrode 71, and a first insulating isolation layer 61 is provided under the N electrode 72. The second metal structure 52 electrically connected to the semiconductor layer 23 has a second insulating isolation layer 62 between the second metal structure 52 and the N electrode 72.
具体地，在外延层内设置第一凹槽41和第二凹槽42，可以采用刻蚀方法形成，刻蚀方法可以采用干法刻蚀、湿法刻蚀或者两者的组合，本实施例中采用干法刻蚀。Specifically, the first groove 41 and the second groove 42 are provided in the epitaxial layer, which can be formed by an etching method. The etching method can be dry etching, wet etching or a combination of the two. This embodiment Dry etching is used in the process.
第二凹槽42的开口直径小于P电极71的直径，进一步地，第二凹槽42的开口直径小于P电极71的焊盘部的直径，其形状可以为圆柱形或者V形。The opening diameter of the second groove 42 is smaller than the diameter of the P electrode 71. Further, the opening diameter of the second groove 42 is smaller than the diameter of the pad portion of the P electrode 71, and its shape may be cylindrical or V-shaped.
第二凹槽42位置与P电极71对应，第一金属结构51设置于第二凹槽42内，其侧壁与第二凹槽42的侧壁之间具有间隙，因此两者不会导通。由于第一金属结构51的底部与N型半导体层21接触，因此第一金属结构51与N型半导体层21电性导通。第一金属结构51的顶部高于或齐平于或低于P型半导体层23的表面，本实施例优选第一金属结构51的顶部高于P型半导体层23的表面。第一绝缘隔离层61包裹第一金属结构51表面，可以包裹第一金属结构51的顶部和侧壁，使第一金属结构51与第二凹槽42侧壁的半导体层和P电极71完全绝缘隔离。The position of the second groove 42 corresponds to the P electrode 71, the first metal structure 51 is disposed in the second groove 42, and there is a gap between the side wall of the second groove 42 and the side wall of the second groove 42, so the two will not be connected. . Since the bottom of the first metal structure 51 is in contact with the N-type semiconductor layer 21, the first metal structure 51 and the N-type semiconductor layer 21 are electrically connected. The top of the first metal structure 51 is higher or flush with or lower than the surface of the P-type semiconductor layer 23. In this embodiment, the top of the first metal structure 51 is preferably higher than the surface of the P-type semiconductor layer 23. The first insulating isolation layer 61 wraps the surface of the first metal structure 51, and can wrap the top and sidewalls of the first metal structure 51, so that the semiconductor layer and the P electrode 71 on the sidewalls of the first metal structure 51 and the second groove 42 are completely insulated isolation.
P电极71包裹第一绝缘隔离层61表面，P电极71的中间部分与第一绝缘隔离层61接触，外缘与透明导电层30接触，以实现P电极71可以通过透明导电层30与P型 半导体层23电性连接。The P electrode 71 wraps the surface of the first insulating isolation layer 61, the middle part of the P electrode 71 is in contact with the first insulating isolation layer 61, and the outer edge is in contact with the transparent conductive layer 30, so that the P electrode 71 can pass through the transparent conductive layer 30 and the P type The semiconductor layer 23 is electrically connected.
N电极72位于第一凹槽41内，第二金属结构52位于第一凹槽41侧壁的P型半导体层23表面，第二金属结构52与P型半导体层23电性导通。第二绝缘隔离层62包裹第二金属结构52，包括第二金属结构52的顶部和侧壁，并延伸至第一凹槽41的侧壁。第二绝缘隔离层62由第二金属结构52的表面沿第一凹槽41侧壁的半导体层延伸至第一凹槽41的底部，同时N电极72沿第二绝缘隔离层62表面延伸至第二金属结构52的上方，使得N电极72通过第二绝缘隔离层62与第一凹槽41侧壁的半导体层以及第二金属结构52完全绝缘隔离。The N electrode 72 is located in the first groove 41, the second metal structure 52 is located on the surface of the P-type semiconductor layer 23 on the sidewall of the first groove 41, and the second metal structure 52 is electrically connected to the P-type semiconductor layer 23. The second insulating isolation layer 62 wraps the second metal structure 52, includes the top and sidewalls of the second metal structure 52, and extends to the sidewalls of the first groove 41. The second insulating isolation layer 62 extends from the surface of the second metal structure 52 along the semiconductor layer on the sidewall of the first groove 41 to the bottom of the first groove 41, while the N electrode 72 extends along the surface of the second insulating isolation layer 62 to the bottom of the first groove 41. Above the two metal structures 52, the N electrode 72 is completely insulated and isolated from the semiconductor layer on the sidewall of the first groove 41 and the second metal structure 52 through the second insulating isolation layer 62.
进一步地，第一金属结构51和第二金属结构52相同或者不同。第一金属结构51和第二金属结构52均为单层结构或者多层结构。第一金属结构51和第二金属结构52均可以选自镍、铬、铝、铂、银、金、钛中的一种或者几种的组合。本实施例中优选，第一金属结构51与N电极72结构相同，第二金属结构52与P电极71结构相同。Further, the first metal structure 51 and the second metal structure 52 are the same or different. The first metal structure 51 and the second metal structure 52 are both a single-layer structure or a multi-layer structure. Both the first metal structure 51 and the second metal structure 52 can be selected from one or a combination of nickel, chromium, aluminum, platinum, silver, gold, and titanium. Preferably, in this embodiment, the first metal structure 51 and the N electrode 72 have the same structure, and the second metal structure 52 and the P electrode 71 have the same structure.
第一绝缘隔离层61和第二绝缘隔离层62均可以选自二氧化硅、氮化硅、氧化铝中的一种或者几种的组合。本实施例中优选第一绝缘隔离层61和第二绝缘隔离层62均为二氧化硅层。Both the first insulating isolation layer 61 and the second insulating isolation layer 62 may be selected from one or a combination of silicon dioxide, silicon nitride, and aluminum oxide. In this embodiment, it is preferable that the first insulating isolation layer 61 and the second insulating isolation layer 62 are both silicon dioxide layers.
本实施例中，由于P电极71与P型半导体层23电性导通，而第一金属结构51和N电极72均与N型半导体层21电性导通；N电极72与N型半导体层21电性导通，P电极71和第二金属结构52均与P型半导体层23电性导通；因此，P电极71和N电极72之间可以形成第一电场，P电极71和第一金属结构51之间也可以形成第二电场，N电极72和第二金属结构52之间可以形成第三电场。In this embodiment, since the P electrode 71 is electrically connected to the P-type semiconductor layer 23, the first metal structure 51 and the N electrode 72 are both electrically connected to the N-type semiconductor layer 21; the N electrode 72 is electrically connected to the N-type semiconductor layer. 21 is electrically connected, the P electrode 71 and the second metal structure 52 are both electrically connected to the P-type semiconductor layer 23; therefore, a first electric field can be formed between the P electrode 71 and the N electrode 72, and the P electrode 71 and the first A second electric field may also be formed between the metal structures 51, and a third electric field may be formed between the N electrode 72 and the second metal structure 52.
因此，与传统的只有一对P电极71和N电极72的LED相比，本实施例中的第一电场可以利用第二电场和第三电场的分流效益而得到削弱，又因为P电极71和/或N电极72的金属迁移受两者之间电场强度的直接影响，因此本发明可以降低金属迁移率，改善LED因金属迁移导致的“死灯”异常现象。Therefore, compared with the traditional LED with only a pair of P electrode 71 and N electrode 72, the first electric field in this embodiment can be weakened by using the shunting benefit of the second electric field and the third electric field. /Or the metal migration of the N electrode 72 is directly affected by the intensity of the electric field between the two. Therefore, the present invention can reduce the metal mobility and improve the abnormal phenomenon of “dead light” caused by the metal migration of the LED.
实施例2Example 2
为了制作实施例1中的发光二极管，本实施例提供了制作方法，具体包括如下步骤：In order to fabricate the light-emitting diode in Embodiment 1, this embodiment provides a fabrication method, which specifically includes the following steps:
参看附图4，步骤1)提供一衬底10，于所述衬底10上依次生长N型半导体层21、发光层22、P半导体层23，形成外延层。Referring to FIG. 4, step 1) provides a substrate 10 on which an N-type semiconductor layer 21, a light-emitting layer 22, and a P semiconductor layer 23 are sequentially grown on the substrate 10 to form an epitaxial layer.
步骤2)于外延层内制作第一凹槽41和第二凹槽42。Step 2) Form the first groove 41 and the second groove 42 in the epitaxial layer.
具体地，刻蚀P型半导体层23至N型半导体层21形成第一凹槽41和第二凹槽42，然后在P型半导体层23表面制作透明导电层30；或者，先在P型半导体层23表面制作透明导电层30，然后刻蚀透明导电层30至N型半导体层21形成第一凹槽41和第二凹槽42。第一凹槽41和第二凹槽42的位置相对，例如可以位于对应于衬底10的两端，或者对角线处，如此增大两者之间的距离，可以延长后续电极注入的电流的路径，利用发光。Specifically, the P-type semiconductor layer 23 to the N-type semiconductor layer 21 are etched to form the first groove 41 and the second groove 42, and then the transparent conductive layer 30 is formed on the surface of the P-type semiconductor layer 23; A transparent conductive layer 30 is formed on the surface of the layer 23, and then the transparent conductive layer 30 is etched to the N-type semiconductor layer 21 to form a first groove 41 and a second groove 42. The positions of the first groove 41 and the second groove 42 are opposite, for example, they may be located at the two ends corresponding to the substrate 10, or at the diagonal, so increasing the distance between the two can prolong the current injected by the subsequent electrodes. The path, using light.
第一凹槽41和第二凹槽42可以由同一刻蚀工艺步骤形成，其可以同时形成，刻蚀方法包括干法刻蚀、湿法刻蚀或者两者的组合，本实施例优选为采用干法刻蚀同时刻蚀形成第一凹槽和第二凹槽。The first groove 41 and the second groove 42 can be formed by the same etching process step, and they can be formed at the same time. The etching method includes dry etching, wet etching or a combination of the two. This embodiment preferably adopts The dry etching simultaneously etches the first groove and the second groove.
参看附图5，步骤3)于第二凹槽42内制作第一金属结构51，于P型半导体层23表面制作第二金属结构52。Referring to FIG. 5, in step 3), a first metal structure 51 is formed in the second groove 42, and a second metal structure 52 is formed on the surface of the P-type semiconductor layer 23.
具体地，第二金属结构52制作于第一凹槽41侧壁的P型半导体层23表面，且两者相对设置，如此设计的目的是，使第二金属结构52与第一金属51之间的距离增大，可以延长后续电极注入的电流的路径，利用发光。Specifically, the second metal structure 52 is fabricated on the surface of the P-type semiconductor layer 23 on the sidewall of the first groove 41, and the two are arranged opposite to each other. The purpose of this design is to make the second metal structure 52 and the first metal 51 separate The increase of the distance can extend the path of the current injected by the subsequent electrodes and utilize light emission.
第一金属结构51和第二金属结构52为同一步骤工艺制程，其可以采用蒸镀法同时制成。第一金属结构51和第二金属结构52可以为相同的结构，例如均为单层金属结构或者多层金属结构，其材料均自镍、铬、铝、铂、银、金、钛中的一种或者几种的组合。The first metal structure 51 and the second metal structure 52 are made in the same step process, and they can be made at the same time by an evaporation method. The first metal structure 51 and the second metal structure 52 may be the same structure, for example, both are a single-layer metal structure or a multi-layer metal structure, and their materials are all from nickel, chromium, aluminum, platinum, silver, gold, and titanium. Kind or a combination of several.
参看附图6，步骤4)于第一金属结构51表面制作第一绝缘隔离层61，第一绝缘隔离层61包裹第一金属结构51；于第二金属结构52表面制作第二绝缘隔离层62，第二绝缘隔离层62包裹第二金属结构52。Referring to FIG. 6, step 4) a first insulating isolation layer 61 is formed on the surface of the first metal structure 51, the first insulating isolation layer 61 wraps the first metal structure 51; a second insulating isolation layer 62 is formed on the surface of the second metal structure 52 , The second insulating isolation layer 62 wraps the second metal structure 52.
第一绝缘隔离层61可以包裹第一金属结构51的顶部和侧壁，使第一金属结构51与第二凹槽42侧壁的外延层完全绝缘隔离；第二绝缘隔离层也可以包裹第二金属结构52的顶部和侧壁。The first insulating isolation layer 61 can wrap the top and sidewalls of the first metal structure 51, so that the first metal structure 51 is completely insulated from the epitaxial layer on the sidewalls of the second groove 42; the second insulating isolation layer can also wrap the second The top and side walls of the metal structure 52.
第一绝缘隔离层61和第二绝缘隔离层62可以为同一沉积步骤形成，其可以同时 制作而成。例如采用PECVD法同时沉积形成一绝缘隔离层61和第二绝缘隔离层62。第一绝缘隔离层61和第二绝缘隔离层62的材料可以相同，例如均选自二氧化硅、氮化硅、氧化铝中的一种或者几种的组合。本实施例中优选两者的材料均为二氧化硅。The first insulating isolation layer 61 and the second insulating isolation layer 62 may be formed in the same deposition step, and they may be manufactured at the same time. For example, a PECVD method is used to simultaneously deposit an insulating isolation layer 61 and a second insulating isolation layer 62. The materials of the first insulating isolation layer 61 and the second insulating isolation layer 62 may be the same, for example, both are selected from one or a combination of silicon dioxide, silicon nitride, and aluminum oxide. In this embodiment, it is preferable that both materials are silica.
继续参看附图4，步骤5)于所述第一绝缘隔离层61表面制作P电极71，P电极71与P型半导体层23电性连接；于所述第二凹槽42内制作N电极72，N电极72沿第二绝缘隔离层62表面延伸至第二金属结构52的上方，N电极72与N型半导体层21电性连接。Continue to refer to FIG. 4, step 5) P electrode 71 is formed on the surface of the first insulating isolation layer 61, and the P electrode 71 is electrically connected to the P-type semiconductor layer 23; an N electrode 72 is formed in the second groove 42 The N electrode 72 extends along the surface of the second insulating isolation layer 62 to above the second metal structure 52, and the N electrode 72 is electrically connected to the N-type semiconductor layer 21.
实施例3Example 3
参看附图7，本实施例提供的发光二极管，其包括：衬底10；层叠于衬底10上的外延层，其中外延层包括依次层叠的N型半导体层21、发光层22和P型半导体层23；以及透明导电层30。每层的具体结构已在实施例1中详细描述，此处不再赘述。Referring to FIG. 7, the light-emitting diode provided by this embodiment includes: a substrate 10; an epitaxial layer laminated on the substrate 10, wherein the epitaxial layer includes an N-type semiconductor layer 21, a light-emitting layer 22, and a P-type semiconductor layered in sequence. Layer 23; and a transparent conductive layer 30. The specific structure of each layer has been described in detail in Embodiment 1, and will not be repeated here.
其中，P电极71下方设置与N型半导体层21电性连接的第一金属结构51，第一金属结构51与P电极71之间具有第一绝缘隔离层61。A first metal structure 51 electrically connected to the N-type semiconductor layer 21 is provided under the P electrode 71, and a first insulating isolation layer 61 is provided between the first metal structure 51 and the P electrode 71.
具体地，在外延层内刻蚀形成第二凹槽42，刻蚀方法可以采用干法刻蚀、湿法刻蚀或者两者的组合，本实施例中采用干法刻蚀，第二凹槽42的开口直径小于P电极71的直径，进一步地，第二凹槽42的开口直径小于P电极71的焊盘部的直径，其形状可以为圆柱形或者V形。Specifically, the second groove 42 is formed by etching in the epitaxial layer. The etching method may be dry etching, wet etching or a combination of the two. In this embodiment, dry etching is used, and the second groove The diameter of the opening of 42 is smaller than the diameter of the P electrode 71. Further, the diameter of the opening of the second groove 42 is smaller than the diameter of the pad portion of the P electrode 71, and its shape may be cylindrical or V-shaped.
第二凹槽42位置与P电极71对应，第一金属结构51设置于第二凹槽42内，其侧壁与第二凹槽42的侧壁之间具有间隙，因此两者不会导通。由于第一金属结构51的底部与N型半导体层21接触，因此第一金属结构51与N型半导体层21电性导通。第一金属结构51的顶部高于或齐平于或低于P型半导体层23的表面，本实施例优选第一金属结构51的顶部高于P型半导体层23的表面。第一绝缘隔离层61包裹第一金属结构51表面，可以包裹第一金属结构51的顶部和侧壁，使第一金属结构51与第二凹槽42侧壁的半导体层和P电极71完全绝缘隔离。P电极71包裹第一绝缘隔离层61表面，P电极71的中间部分与第一绝缘隔离层61接触，外缘与透明导电层30接触，以实现P电极71可以通过透明导电层30与P型半导体层23电性连 接。The position of the second groove 42 corresponds to the P electrode 71, the first metal structure 51 is disposed in the second groove 42, and there is a gap between the side wall of the second groove 42 and the side wall of the second groove 42, so the two will not conduct . Since the bottom of the first metal structure 51 is in contact with the N-type semiconductor layer 21, the first metal structure 51 and the N-type semiconductor layer 21 are electrically connected. The top of the first metal structure 51 is higher or flush with or lower than the surface of the P-type semiconductor layer 23. In this embodiment, the top of the first metal structure 51 is preferably higher than the surface of the P-type semiconductor layer 23. The first insulating isolation layer 61 wraps the surface of the first metal structure 51, and can wrap the top and sidewalls of the first metal structure 51, so that the semiconductor layer and the P electrode 71 on the sidewalls of the first metal structure 51 and the second groove 42 are completely insulated isolation. The P electrode 71 wraps the surface of the first insulating isolation layer 61, the middle part of the P electrode 71 is in contact with the first insulating isolation layer 61, and the outer edge is in contact with the transparent conductive layer 30, so that the P electrode 71 can pass through the transparent conductive layer 30 and the P type The semiconductor layer 23 is electrically connected.
本实施例中，由于P电极71与P型半导体层23电性导通，而第一金属结构51和N电极72均与N型半导体层21电性导通。因此，P电极71和N电极72之间可以形成第一电场，P电极71和第一金属结构51之间也可以形成第二电场。因此，与传统的只有一对P电极71和N电极72的LED相比，本实施例中的第一电场可以利用第二电场的分流效益而得到削弱，又因为P电极71和/或N电极72的金属迁移受两者之间电场强度的直接影响，因此本发明可以降低金属迁移率，改善LED因金属迁移导致的“死灯”异常现象。In this embodiment, since the P electrode 71 is electrically connected to the P-type semiconductor layer 23, the first metal structure 51 and the N electrode 72 are both electrically connected to the N-type semiconductor layer 21. Therefore, a first electric field can be formed between the P electrode 71 and the N electrode 72, and a second electric field can also be formed between the P electrode 71 and the first metal structure 51. Therefore, compared with the traditional LED with only a pair of P electrode 71 and N electrode 72, the first electric field in this embodiment can be weakened by using the shunting benefit of the second electric field. The metal migration of 72 is directly affected by the intensity of the electric field between the two. Therefore, the present invention can reduce the metal mobility and improve the abnormal phenomenon of "dead light" caused by the metal migration of the LED.
实施例4Example 4
为了制作实施例3中发光二极管，本实施例提供了制作方法，具体包括如下步骤：In order to fabricate the light-emitting diode in Embodiment 3, this embodiment provides a fabrication method, which specifically includes the following steps:
1)提供一衬底10，于衬底10上依次生长N型半导体层21、发光层22和P半导体层23，形成外延层；1) A substrate 10 is provided, and an N-type semiconductor layer 21, a light-emitting layer 22, and a P semiconductor layer 23 are sequentially grown on the substrate 10 to form an epitaxial layer;
2)于外延层内制作第一凹槽41和第二凹槽42；2) Making the first groove 41 and the second groove 42 in the epitaxial layer;
具体地，刻蚀P型半导体层23至N型半导体层21形成第一凹槽41和第二凹槽42，然后在P型半导体层23表面制作透明导电层30；或者，先在P型半导体层23表面制作透明导电层30，然后刻蚀透明导电层30至N型半导体层21形成第一凹槽41和第二凹槽42。Specifically, the P-type semiconductor layer 23 to the N-type semiconductor layer 21 are etched to form the first groove 41 and the second groove 42, and then the transparent conductive layer 30 is formed on the surface of the P-type semiconductor layer 23; A transparent conductive layer 30 is formed on the surface of the layer 23, and then the transparent conductive layer 30 is etched to the N-type semiconductor layer 21 to form a first groove 41 and a second groove 42.
3)于第二凹槽42内制作第一金属结构51；3) Fabricate the first metal structure 51 in the second groove 42;
4)于第一金属结构51表面制作第一绝缘隔离层61，第一绝缘隔离层61包裹第一金属结构51；4) A first insulating isolation layer 61 is formed on the surface of the first metal structure 51, and the first insulating isolation layer 61 wraps the first metal structure 51;
5)分别于第一绝缘隔离层61表面和第二凹槽42内制作P电极71和N电极72，P电极71与P型半导体层23电性连接，N电极72与N型半导体层21电性连接。5) P-electrodes 71 and N-electrodes 72 are formed on the surface of the first insulating isolation layer 61 and in the second groove 42 respectively. The P-electrodes 71 are electrically connected to the P-type semiconductor layer 23, and the N-electrodes 72 are electrically connected to the N-type semiconductor layer 21. Sexual connection.
其中步骤2)中第一凹槽41和第二凹槽42为同一步刻蚀工艺形成，刻蚀方法可以为干法刻蚀、湿法刻蚀或者两者的组合，本实施例优选干法刻蚀。第二凹槽42可以为L型的台阶状。本实施例在刻蚀第二凹槽42的同时形成第一凹槽41，未增加工艺步骤，因此不会增加LED制造成本。In step 2), the first groove 41 and the second groove 42 are formed by the same etching process, and the etching method may be dry etching, wet etching or a combination of the two. In this embodiment, dry etching is preferred. Etching. The second groove 42 may have an L-shaped step shape. In this embodiment, the first groove 41 is formed while the second groove 42 is etched, and no process steps are added, so the LED manufacturing cost will not increase.
实施例5Example 5
参看附图8，本实施例中的发光二极管，其包括：衬底10；层叠于衬底10上的外延层，其中外延层包括依次层叠的N型半导体层21、发光层22和P型半导体层23；以及透明导电层30。每层的具体结构已在实施例1中详细描述，此处不再赘述。Referring to FIG. 8, the light-emitting diode in this embodiment includes: a substrate 10; an epitaxial layer laminated on the substrate 10, wherein the epitaxial layer includes an N-type semiconductor layer 21, a light-emitting layer 22, and a P-type semiconductor layered in sequence. Layer 23; and a transparent conductive layer 30. The specific structure of each layer has been described in detail in Embodiment 1, and will not be repeated here.
其中，N电极72下方设置与P型半导体层23电性连接的第二金属结构52，第二金属结构52与N电极72之间具有第二绝缘隔离层62。具体地，第二金属结构52位于第一凹槽41侧壁的P型半导体层23表面，第二金属结构52与P型半导体层23电性导通。第二绝缘隔离层62包裹第二金属结构52，包括第二金属结构52的顶部和侧壁，并延伸至第一凹槽41的侧壁。第二绝缘隔离层62由第二金属结构52的表面沿第一凹槽41侧壁的半导体层延伸至第一凹槽41的底部，同时N电极72沿第二绝缘隔离层62表面延伸至第二金属结构52的上方，使得N电极72通过第二绝缘隔离层62与第一凹槽41侧壁的半导体层以及第二金属结构52完全绝缘隔离。A second metal structure 52 electrically connected to the P-type semiconductor layer 23 is provided under the N electrode 72, and a second insulating isolation layer 62 is provided between the second metal structure 52 and the N electrode 72. Specifically, the second metal structure 52 is located on the surface of the P-type semiconductor layer 23 on the sidewall of the first groove 41, and the second metal structure 52 is electrically connected to the P-type semiconductor layer 23. The second insulating isolation layer 62 wraps the second metal structure 52, includes the top and sidewalls of the second metal structure 52, and extends to the sidewalls of the first groove 41. The second insulating isolation layer 62 extends from the surface of the second metal structure 52 along the semiconductor layer on the sidewall of the first groove 41 to the bottom of the first groove 41, while the N electrode 72 extends along the surface of the second insulating isolation layer 62 to the bottom of the first groove 41. Above the two metal structures 52, the N electrode 72 is completely insulated and isolated from the semiconductor layer on the sidewall of the first groove 41 and the second metal structure 52 through the second insulating isolation layer 62.
由于N电极72与N型半导体层21电性导通，P电极71和第二金属结构52均与P型半导体层23电性导通，因此，P电极71和N电极72之间可以形成第一电场，N电极72和第二金属结构52之间也可以形成第三电场。Since the N electrode 72 is electrically connected to the N-type semiconductor layer 21, and both the P electrode 71 and the second metal structure 52 are electrically connected to the P-type semiconductor layer 23, the P electrode 71 and the N electrode 72 can form a first With an electric field, a third electric field can also be formed between the N electrode 72 and the second metal structure 52.
传统的LED结构中只有一对P电极71和N电极72，假设P电极71和N电极72之间的电场强度值为N，本发明与传统的LED结构相比，第一电场和第三电场的强度值总和等于N，因此，P电极71和N电极72之间的第一电场强度则小于传统的LED中两者之间的强度，从而可以利用第三电场分流第一电场的强度。又因为P电极71和/或N电极72的金属迁移受两者之间电场强度的直接影响，因此本发明可以降低金属迁移率，改善LED因金属迁移导致的“死灯”异常现象。In the traditional LED structure, there is only a pair of P electrode 71 and N electrode 72. Assuming that the electric field strength between the P electrode 71 and the N electrode 72 is N, the present invention has the first electric field and the third electric field in comparison with the traditional LED structure. The sum of the intensity values of is equal to N. Therefore, the intensity of the first electric field between the P electrode 71 and the N electrode 72 is smaller than the intensity between the two in a conventional LED, so that the intensity of the first electric field can be shunted by the third electric field. In addition, because the metal migration of the P electrode 71 and/or the N electrode 72 is directly affected by the electric field strength between the two, the present invention can reduce the metal mobility and improve the abnormal phenomenon of “dead light” caused by the metal migration of the LED.
实施例6Example 6
为了制作实施例5中的发光二极管，本实施例提供了制作方法，具体包括如下步骤：In order to fabricate the light-emitting diode in Embodiment 5, this embodiment provides a fabrication method, which specifically includes the following steps:
1)提供一衬底10，于衬底10上依次生长N型半导体层21、发光层22和P半导体层，形成外延层；1) A substrate 10 is provided, and an N-type semiconductor layer 21, a light-emitting layer 22, and a P semiconductor layer are sequentially grown on the substrate 10 to form an epitaxial layer;
2)于外延层内制作形成第一凹槽41；2) Making a first groove 41 in the epitaxial layer;
具体地，刻蚀P型半导体层23至N型半导体层21形成第一凹槽41，然后在P型半 导体层23表面制作透明导电层30；或者，先在P型半导体层23表面制作透明导电层30，然后刻蚀透明导电层30至N型半导体层21形成第一凹槽41，本实施例对比不作特别限制。Specifically, the P-type semiconductor layer 23 to the N-type semiconductor layer 21 are etched to form the first groove 41, and then a transparent conductive layer 30 is formed on the surface of the P-type semiconductor layer 23; or, a transparent conductive layer is formed on the surface of the P-type semiconductor layer 23 first. Then, the transparent conductive layer 30 is etched to the N-type semiconductor layer 21 to form the first groove 41. The comparison of this embodiment is not particularly limited.
3)于第一凹槽41侧壁的P型半导体层23表面制作第二金属结构52；3) Fabricating a second metal structure 52 on the surface of the P-type semiconductor layer 23 on the sidewall of the first groove 41;
4)于第二金属结构52表面制作第二绝缘隔离层62；4) Forming a second insulating isolation layer 62 on the surface of the second metal structure 52;
5)分别于P型半导体层23表面和第二凹槽42内制作P电极71和N电极72，P电极71与P型半导体层23电性连接，N电极72沿第二绝缘隔离层62表面延伸至第二金属结构52的上方，N电极72与N型半导体层21电性连接。5) P-electrodes 71 and N-electrodes 72 are fabricated on the surface of the P-type semiconductor layer 23 and in the second groove 42 respectively. The P-electrodes 71 are electrically connected to the P-type semiconductor layer 23, and the N-electrodes 72 are along the surface of the second insulating isolation layer 62 Extending above the second metal structure 52, the N electrode 72 is electrically connected to the N-type semiconductor layer 21.
应当理解的是，上述具体实施方案为本发明的优选实施例，本发明的范围不限于该实施例，凡依本发明所做的任何变更，皆属本发明的保护范围之内。It should be understood that the above-mentioned specific embodiments are preferred embodiments of the present invention, and the scope of the present invention is not limited to this embodiment. Any changes made according to the present invention fall within the protection scope of the present invention.

Claims (25)

  1. 发光二极管，至少包括：衬底；层叠于所述衬底上的外延层，所述外延层包括依次层叠的N型半导体层、发光层和P型半导体层，刻蚀外延层露出N型半导体层形成第一凹槽；P电极，与P型半导体层电性连接；N电极，位于第一凹槽内，与N型半导体层电性连接；The light emitting diode includes at least: a substrate; an epitaxial layer laminated on the substrate, the epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked in sequence, and the epitaxial layer is etched to expose the N-type semiconductor layer A first groove is formed; a P electrode is electrically connected to the P-type semiconductor layer; an N electrode is located in the first groove and is electrically connected to the N-type semiconductor layer;
    其特征在于：Its characteristics are:
    所述P电极下方设置与N型半导体层电性连接的第一金属结构，第一金属结构与P电极之间具有第一绝缘隔离层，所述N电极下方设置与P型半导体层电性连接的第二金属结构，第二金属结构与N电极之间具有第二绝缘隔离层。A first metal structure electrically connected to the N-type semiconductor layer is provided under the P electrode, a first insulating isolation layer is provided between the first metal structure and the P electrode, and a first metal structure is provided under the N electrode to be electrically connected to the P-type semiconductor layer The second metal structure is provided with a second insulating isolation layer between the second metal structure and the N electrode.
  2. 发光二极管，至少包括：衬底；层叠于所述衬底上的外延层，所述外延层包括依次层叠的N型半导体层、发光层和P型半导体层，刻蚀外延层露出N型半导体层形成第一凹槽；P电极，与P型半导体层电性接触；N电极，位于第一凹槽内，与N型半导体层电性接触；The light emitting diode includes at least: a substrate; an epitaxial layer laminated on the substrate, the epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked in sequence, and the epitaxial layer is etched to expose the N-type semiconductor layer A first groove is formed; a P electrode is in electrical contact with the P-type semiconductor layer; an N electrode is located in the first groove and is in electrical contact with the N-type semiconductor layer;
    其特征在于：Its characteristics are:
    所述P电极下方设置与N型半导体层电性连接的第一金属结构，第一金属结构与P电极之间具有第一绝缘隔离层。A first metal structure electrically connected to the N-type semiconductor layer is arranged under the P electrode, and a first insulating isolation layer is provided between the first metal structure and the P electrode.
  3. 发光二极管，至少包括：衬底；层叠于所述衬底上的外延层，所述外延层包括依次层叠的N型半导体层、发光层和P型半导体层，刻蚀外延层露出N型半导体层形成第一凹槽；P电极，与P型半导体层电性接触；N电极，位于第一凹槽内，与N型半导体层电性接触；The light emitting diode includes at least: a substrate; an epitaxial layer laminated on the substrate, the epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked in sequence, and the epitaxial layer is etched to expose the N-type semiconductor layer A first groove is formed; a P electrode is in electrical contact with the P-type semiconductor layer; an N electrode is located in the first groove and is in electrical contact with the N-type semiconductor layer;
    其特征在于：Its characteristics are:
    所述N电极下方设置与P型半导体层电性连接的第二金属结构，第二金属结构与N电极之间具有第二绝缘隔离层。A second metal structure electrically connected to the P-type semiconductor layer is arranged under the N electrode, and a second insulating isolation layer is provided between the second metal structure and the N electrode.
  4. 根据权利要求1或2所述的发光二极管，其特征在于：刻蚀所述P型 半导体层至N型半导体层形成第二凹槽，第一金属结构设置于第二凹槽内，第一金属结构与N型半导体层电性导通。The light emitting diode of claim 1 or 2, wherein the P-type semiconductor layer is etched to the N-type semiconductor layer to form a second groove, the first metal structure is disposed in the second groove, and the first metal The structure is electrically connected to the N-type semiconductor layer.
  5. 根据权利要求4所述的发光二极管，其特征在于：所述第一绝缘隔离层包裹第一金属结构表面，所述P电极包裹第一绝缘隔离层表面。4. The light emitting diode of claim 4, wherein the first insulating isolation layer wraps the surface of the first metal structure, and the P electrode wraps the surface of the first insulating isolation layer.
  6. 根据权利要求5所述的发光二极管，其特征在于：所述P电极与N电极和第一金属结构分别形成第一电场和第二电场，第二电场削弱第一电场的强度，降低P电极和N电极之间的金属迁移。The light emitting diode according to claim 5, wherein the P electrode and the N electrode and the first metal structure respectively form a first electric field and a second electric field, and the second electric field weakens the intensity of the first electric field and reduces the P electrode and the first metal structure. Metal migration between N electrodes.
  7. 根据权利要求4所述的发光二极管，其特征在于：所述第二凹槽的开口直径小于P电极的直径。4. The light emitting diode of claim 4, wherein the diameter of the opening of the second groove is smaller than the diameter of the P electrode.
  8. 根据权利要求1或3所述的发光二极管，其特征在于：所述第二金属结构位于第一凹槽侧壁的P型半导体层表面，第二金属结构与P型半导体层电性导通。3. The light emitting diode of claim 1 or 3, wherein the second metal structure is located on the surface of the P-type semiconductor layer on the sidewall of the first groove, and the second metal structure is electrically connected to the P-type semiconductor layer.
  9. 根据权利要求8所述的发光二极管，其特征在于：所述N电极与P电极和第二金属结构之间分别形成第一电场和第三电场，第三电场削弱第一电场的强度，降低P电极和N电极之间的金属迁移。8. The light emitting diode according to claim 8, wherein a first electric field and a third electric field are formed between the N electrode and the P electrode and the second metal structure, respectively, and the third electric field weakens the intensity of the first electric field and reduces P Metal migration between the electrode and the N electrode.
  10. 根据权利要求8所述的发光二极管，其特征在于：所述第二绝缘隔离层包裹第二金属结构，并延伸至第一凹槽的侧壁。8. The light emitting diode of claim 8, wherein the second insulating isolation layer wraps the second metal structure and extends to the sidewall of the first groove.
  11. 根据权利要求10所述的发光二极管，其特征在于：所述N电极沿第二绝缘隔离层表面延伸至第二金属结构的上方。10. The light emitting diode of claim 10, wherein the N electrode extends along the surface of the second insulating isolation layer to above the second metal structure.
  12. 根据权利要求1或2所述的发光二极管，其特征在于：所述第一金属结构的顶部高于或齐平于或低于P型半导体层的表面。The light emitting diode according to claim 1 or 2, wherein the top of the first metal structure is higher than or flush with or lower than the surface of the P-type semiconductor layer.
  13. 根据权利要求1所述的发光二极管，其特征在于：所述第一金属结构和第二金属结构相同或者不同。The light emitting diode of claim 1, wherein the first metal structure and the second metal structure are the same or different.
  14. 根据权利要求1所述的发光二极管，其特征在于：所述第一金属结构和第二金属结构均为单层结构或者多层结构。The light emitting diode according to claim 1, wherein the first metal structure and the second metal structure are both a single-layer structure or a multi-layer structure.
  15. 根据权利要求1所述的发光二极管，其特征在于：所述第一金属结构和第二金属结构均选自镍、铬、铝、铂、银、金、钛中的一种 或者几种的组合。The light emitting diode of claim 1, wherein the first metal structure and the second metal structure are both selected from one or a combination of nickel, chromium, aluminum, platinum, silver, gold, and titanium .
  16. 根据权利要求1所述的发光二极管，其特征在于：所述第一绝缘隔离层和第二绝缘隔离层均选自二氧化硅、氮化硅、氧化铝中的一种或者几种的组合。The light emitting diode according to claim 1, wherein the first insulating isolation layer and the second insulating isolation layer are both selected from one or a combination of silicon dioxide, silicon nitride, and aluminum oxide.
  17. 根据权利要求1～3任意一项所述的发光二极管，其特征在于：所述P型半导体层表面还设置有透明导电层。The light emitting diode according to any one of claims 1 to 3, wherein a transparent conductive layer is further provided on the surface of the P-type semiconductor layer.
  18. 发光二极管的制作方法，包括如下步骤：The manufacturing method of the light emitting diode includes the following steps:
    1)提供一衬底，于所述衬底上依次生长N型半导体层、发光层、P半导体层和透明导电层，形成外延层；1) Provide a substrate on which an N-type semiconductor layer, a light-emitting layer, a P semiconductor layer and a transparent conductive layer are sequentially grown on the substrate to form an epitaxial layer;
    2)于所述外延层内制作第一凹槽和第二凹槽，所述第一凹槽和第二凹槽的底部均位于N型半导体层内；2) Making a first groove and a second groove in the epitaxial layer, the bottoms of the first groove and the second groove are both located in the N-type semiconductor layer;
    3)于所述第二凹槽内制作第一金属结构，于所述P型半导体层表面制作第二金属结构；3) Fabricating a first metal structure in the second groove, and fabricating a second metal structure on the surface of the P-type semiconductor layer;
    4)于所述第一金属结构表面制作第一绝缘隔离层，第一绝缘隔离层包裹第一金属结构；于所述第二金属结构表面制作第二绝缘隔离层，第二绝缘隔离层包裹第二金属结构；4) A first insulating isolation layer is made on the surface of the first metal structure, and the first insulating isolation layer wraps the first metal structure; a second insulating isolation layer is made on the surface of the second metal structure, and the second insulating isolation layer wraps the first metal structure. Two metal structure;
    5)于所述第一绝缘隔离层表面制作P电极，P电极与P型半导体层电性连接；于所述第二凹槽内制作N电极，N电极沿第二绝缘隔离层表面延伸至第二金属结构的上方，N电极与N型半导体层电性连接。5) A P electrode is made on the surface of the first insulating isolation layer, and the P electrode is electrically connected to the P-type semiconductor layer; an N electrode is made in the second groove, and the N electrode extends along the surface of the second insulating isolation layer to the first Above the two metal structures, the N electrode is electrically connected to the N-type semiconductor layer.
  19. 发光二极管的制作方法，包括如下步骤：The manufacturing method of the light emitting diode includes the following steps:
    提供一衬底，于所述衬底上依次生长N型半导体层、发光层、P半导体层和透明导电层，形成外延层；Providing a substrate on which an N-type semiconductor layer, a light-emitting layer, a P semiconductor layer and a transparent conductive layer are sequentially grown on the substrate to form an epitaxial layer;
    于所述外延层内制作第一凹槽和第二凹槽，所述第一凹槽和第二凹槽的底部均位于N型半导体层内；Forming a first groove and a second groove in the epitaxial layer, the bottoms of the first groove and the second groove are both located in the N-type semiconductor layer;
    于所述第二凹槽内制作第一金属结构；Fabricating a first metal structure in the second groove;
    于所述第一金属结构表面制作第一绝缘隔离层，第一绝缘隔离层包裹第一金属结构；Forming a first insulating isolation layer on the surface of the first metal structure, and the first insulating isolation layer wraps the first metal structure;
    分别于所述第一绝缘隔离层表面和第二凹槽内制作P电极和N电极，所述P电极与P型半导体层电性连接，N电极与N型半导体层电性连接。A P electrode and an N electrode are respectively formed on the surface of the first insulating isolation layer and in the second groove. The P electrode is electrically connected to the P type semiconductor layer, and the N electrode is electrically connected to the N type semiconductor layer.
  20. 发光二极管的制作方法，包括如下步骤：The manufacturing method of the light emitting diode includes the following steps:
    提供一衬底，于所述衬底上依次生长N型半导体层、发光层、P半导体层和透明导电层，形成外延层；Providing a substrate on which an N-type semiconductor layer, a light-emitting layer, a P semiconductor layer and a transparent conductive layer are sequentially grown on the substrate to form an epitaxial layer;
    于所述外延层内制作第一凹槽，第一凹槽的底部位于N型半导体层内；Forming a first groove in the epitaxial layer, and the bottom of the first groove is located in the N-type semiconductor layer;
    于所述第一凹槽侧壁的P型半导体层表面制作第二金属结构；Fabricating a second metal structure on the surface of the P-type semiconductor layer on the sidewall of the first groove;
    于所述第二金属结构表面制作第二绝缘隔离层；Forming a second insulating isolation layer on the surface of the second metal structure;
    分别于P型半导体层表面和第二凹槽内制作P电极和N电极，P电极与P型半导体层电性连接，N电极沿第二绝缘隔离层表面延伸至第二金属结构的上方，N电极与N型半导体层电性连接。A P electrode and an N electrode are formed on the surface of the P-type semiconductor layer and in the second groove respectively. The P electrode is electrically connected to the P-type semiconductor layer. The N electrode extends along the surface of the second insulating isolation layer to above the second metal structure. The electrode is electrically connected to the N-type semiconductor layer.
  21. 根据权利要求18或19所述的发光二极管的制作方法，其特征在于：所述第一凹槽和第二凹槽为同一刻蚀工艺步骤制成。The method for manufacturing a light emitting diode according to claim 18 or 19, wherein the first groove and the second groove are made by the same etching process.
  22. 根据权利要求18～20任意一项所述的发光二极管的制作方法，其特征在于：所述的刻蚀方法包括干法刻蚀、湿法刻蚀或者两者的组合。The method for manufacturing a light emitting diode according to any one of claims 18 to 20, wherein the etching method comprises dry etching, wet etching or a combination of the two.
  23. 根据权利要求18所述的发光二极管的制作方法，其特征在于：所述第一金属结构和第二金属结构为同一蒸镀工艺步骤制成。18. The method of manufacturing a light emitting diode according to claim 18, wherein the first metal structure and the second metal structure are manufactured in the same vapor deposition process.
  24. 根据权利要求18所述的发光二极管的制作方法，其特征在于：所述第一绝缘隔离层和第二绝缘隔离层为同一CVD工艺步骤制成。18. The method of manufacturing a light emitting diode according to claim 18, wherein the first insulating isolation layer and the second insulating isolation layer are manufactured in the same CVD process.
  25. 根据权利要求18～20任意一项所述的发光二极管的制作方法，其特征在于：还包括于所述P型半导体层表面制作透明导电层的步骤。22. The method for manufacturing a light emitting diode according to any one of claims 18 to 20, further comprising the step of forming a transparent conductive layer on the surface of the P-type semiconductor layer.
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