WO2021062994A1 - 像素电路、显示装置及像素驱动方法 - Google Patents

像素电路、显示装置及像素驱动方法 Download PDF

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WO2021062994A1
WO2021062994A1 PCT/CN2020/085009 CN2020085009W WO2021062994A1 WO 2021062994 A1 WO2021062994 A1 WO 2021062994A1 CN 2020085009 W CN2020085009 W CN 2020085009W WO 2021062994 A1 WO2021062994 A1 WO 2021062994A1
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transistor
circuit
terminal
path
signal
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PCT/CN2020/085009
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English (en)
French (fr)
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王鸣昕
高威
黄洪涛
徐尚君
朱景辉
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南京中电熊猫液晶显示科技有限公司
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Publication of WO2021062994A1 publication Critical patent/WO2021062994A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • This application relates to the field of display, and in particular to pixel circuits, display devices, and pixel driving methods.
  • the original structure of the pixel drive circuit is 2T1C, that is, 2 TFTs (Thin Film Transistor, thin film transistors) and 1 capacitor , As shown in Figure 1.
  • Data is a data signal
  • Scan is a scan signal
  • ELVDD is a DC high level
  • Vss is a DC low level
  • T1 and T2 are both TFTs
  • C is a capacitor
  • Diode is a light-emitting diode.
  • the device is affected by Stress, and the phenomenon of Vth shift occurs; and OLED (Organic Light-Emitting Diode, organic light-emitting diode) is currently the main current driving backplane
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • the light-emitting element at the same time, due to the organic material properties of the light-emitting element OLED, it is susceptible to material degradation due to factors such as the environment, and the direct effect is the reduction of luminous efficiency.
  • the above two factors have caused the 2T1C circuit to not be used in mass-produced products, and more complicated circuits must be used to compensate for the impact of the above two problems.
  • the more efficient pixel compensation circuit is at least 4T or more.
  • Data is the data signal
  • SCAN1 and SCAN2 are the scan signals.
  • ELVDD is DC high level
  • T1, T2, T3 and T4 are all TFTs
  • C, C1 and C2 are capacitors.
  • All pixel compensation circuits (including the 4T2C structure) are roughly divided into four steps in time sequence: Reset, Compensation, Data input and Emission. Each row of pixels includes the above steps. As the pixel resolution continues to increase, the time allocated to each step is continuously reduced, which directly affects the compensation effect and luminous efficiency of the pixels.
  • the space required by MicroLED is much smaller than that of OLED, so for the MicroLED pixel compensation circuit, the original circuit structure can be modified under the condition of sufficient space to improve the circuit compensation effect and luminous efficiency .
  • the present application provides a pixel circuit, a display device, and a pixel driving method, which adopts two sub-circuits to work alternately to improve the circuit compensation effect and luminous efficiency.
  • the present application discloses a pixel circuit, including: a first sub-circuit, a second sub-circuit and a light-emitting device;
  • the first sub-circuit is connected to the first terminal, the scan line, the first data line and the first power terminal of the light-emitting device; the first sub-circuit is used to provide a scan signal and reference according to the scan line The signal outputs a reset signal to the circuit during the first period of time and performs a compensation action on the circuit, the first data signal provided by the first data line writes the data signal to the pixel unit, and during the second period of time to the light emitting device Output a corresponding drive current; the second sub-circuit is connected to the first end, the scan line, the second data line, and the first power end of the light-emitting device; the second sub-circuit is used to follow the scan line The provided scan signal and the second data signal provided by the second data line output a corresponding drive current to the light-emitting device during the first time period, and output a reset signal to the circuit and the counter circuit during the second time period. Performing compensation actions and writing data signals to the pixel unit;
  • the second terminal of the light-emitting device is connected to the second power terminal, and is used to emit light according to the received driving current.
  • the first sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor;
  • the control terminal of the first transistor inputs a first drive control signal, the first path terminal of the first transistor is connected to the first power terminal, and the second path terminal of the first transistor is connected to the first terminal of the fourth transistor.
  • the control terminal of the second transistor inputs a first data write control signal, the first path terminal of the second transistor is connected to the first data line, and the second path terminal of the second transistor is connected to the fourth transistor. Control terminal;
  • the control terminal of the third transistor inputs a first reset control signal, the first path end of the third transistor is connected to one end of the first capacitor, and the second path end of the third transistor is connected to a second power supply terminal;
  • the other end of the first capacitor is connected to the control end of the fourth transistor; the second pass end of the fourth transistor is connected to the first pass end of the sixth transistor;
  • the control terminal of the fifth transistor inputs a first compensation control signal, the first path terminal of the fifth transistor inputs a reference signal, and the second path terminal of the fifth transistor is connected to the control terminal of the fourth transistor;
  • One end of the second capacitor is connected to the first path end of the third transistor, and the other end of the second capacitor is connected to the first path end of the sixth transistor;
  • the control terminal of the sixth transistor inputs a first light-emitting control signal, and the second path of the sixth transistor is connected to the light-emitting device;
  • the second sub-circuit includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a third capacitor, and a fourth capacitor;
  • the control terminal of the eleventh transistor inputs a second drive control signal, the first path terminal of the eleventh transistor is connected to the first power terminal, and the second path terminal of the eleventh transistor is connected to the fourteenth The first path end of the transistor;
  • the control terminal of the twelfth transistor inputs a second data write control signal, the first path end of the twelfth transistor is connected to the second data line, and the second path end of the twelfth transistor is connected to the second data line.
  • the control terminal of the thirteenth transistor inputs a second reset control signal, the first path end of the thirteenth transistor is connected to one end of the third capacitor, and the second path end of the thirteenth transistor is connected to the second Power terminal
  • the other end of the third capacitor is connected to the control end of the fourteenth transistor; the second pass end of the fourteenth transistor is connected to the first pass end of the sixteenth transistor;
  • the control terminal of the fifteenth transistor inputs a second compensation control signal
  • the first path terminal of the fifteenth transistor inputs a reference signal
  • the second path terminal of the fifteenth transistor is connected to the fourteenth transistor Control end
  • One end of the fourth capacitor is connected to the first path end of the thirteenth transistor, and the other end of the fourth capacitor is connected to the first path end of the sixteenth transistor;
  • the control terminal of the sixteenth transistor inputs a second light-emitting control signal, and the second path terminal of the sixteenth transistor is connected to the light-emitting device.
  • one of the first time period and the second time period is an odd-numbered frame time period, and the other is an even-numbered frame time period.
  • the application also discloses a display device, including the pixel circuit.
  • the present application also discloses a pixel driving method, which is suitable for the above-mentioned pixel circuit, and includes:
  • Step 1 In the first time period, the first sub-circuit outputs a reset signal to the circuit according to the scan signal provided by the scan line and the first data signal provided by the first data line, performs a compensation action on the circuit, and provides The pixel unit writes a data signal; the second sub-circuit outputs a corresponding driving current to the light emitting device according to the scan signal provided by the scan line and the second data signal provided by the second data line;
  • Step 2 the first sub-circuit outputs a corresponding driving current to the light-emitting device according to the scan signal provided by the scan line and the first data signal provided by the first data line;
  • the circuit outputs a reset signal to the circuit according to the scan signal provided by the scan line and the second data signal provided by the second data line, performs a compensation action on the circuit, and writes a data signal to the pixel unit;
  • the step 1 and the step 2 are performed alternately.
  • the present application also discloses a pixel circuit, including: a first sub-circuit, a second sub-circuit and a light-emitting device;
  • the first sub-circuit is connected to the first terminal, the scan line, the first data line, and the first power terminal of the light-emitting device; the first sub-circuit is used for scanning signals provided by the scan line and the The first data signal provided by the first data line outputs a reset signal to the circuit during the first time period, performs a compensation action on the circuit, and outputs a corresponding driving current to the light-emitting device and to the pixel during the second time period.
  • Unit write data signal
  • the second sub-circuit is connected to the first terminal, the scan line, the second data line, and the first power terminal of the light-emitting device; the second sub-circuit is used for the scan signal provided by the scan line and the The second data signal provided by the second data line outputs a corresponding driving current to the light-emitting device and writes a data signal to the pixel unit during the first time period, and outputs a reset signal to the circuit and during the second time period. Compensate the circuit;
  • the second terminal of the light-emitting device is connected to the second power terminal, and is used to emit light according to the received driving current.
  • the first sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a sixth transistor, a first capacitor, and a second capacitor;
  • the control terminal of the first transistor inputs a first drive control signal, the first path terminal of the first transistor is connected to the first power terminal, and the second path terminal of the first transistor is connected to the first terminal of the fourth transistor.
  • the control terminal of the second transistor is connected to the control terminal of the third transistor and the first data writing control signal or the first compensation control signal is input, and the first path terminal of the second transistor is connected to the first data line ,
  • the first data line is used for time-sharing input of the first data signal or the first reset control signal, and the second path end of the second transistor is connected to the control end of the fourth transistor;
  • a first path end of the third transistor is connected to one end of the first capacitor, and a second path end of the third transistor is connected to a second power supply terminal;
  • the other end of the first capacitor is connected to the control end of the fourth transistor; the second pass end of the fourth transistor is connected to the first pass end of the sixth transistor;
  • One end of the second capacitor is connected to the first path end of the third transistor, and the other end of the second capacitor is connected to the first path end of the sixth transistor;
  • the control terminal of the sixth transistor inputs a first light-emitting control signal, and the second path terminal of the sixth transistor is connected to a second power terminal;
  • the second sub-circuit includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a sixteenth transistor, a third capacitor, and a fourth capacitor;
  • the control terminal of the eleventh transistor inputs a second drive control signal, the first path terminal of the eleventh transistor is connected to the first power terminal, and the second path terminal of the eleventh transistor is connected to the fourteenth The first path end of the transistor;
  • the control terminal of the twelfth transistor is connected to the control terminal of the thirteenth transistor and a second data writing control signal or a second compensation control signal is input.
  • the first path end of the twelfth transistor is connected to the control terminal of the thirteenth transistor.
  • the second data line, the second data line is used for time-sharing input of a second data signal or a second reset control signal, and the second path end of the twelfth transistor is connected to the control end of the fourteenth transistor;
  • a first path end of the thirteenth transistor is connected to one end of the third capacitor, and a second path end of the thirteenth transistor is connected to a second power supply end;
  • the other end of the third capacitor is connected to the control end of the fourteenth transistor; the second pass end of the fourteenth transistor is connected to the first pass end of the sixteenth transistor;
  • One end of the fourth capacitor is connected to the first path end of the thirteenth transistor, and the other end of the fourth capacitor is connected to the first path end of the sixteenth transistor;
  • the control terminal of the sixteenth transistor inputs a second light-emitting control signal, and the second path terminal of the sixteenth transistor is connected to the second power terminal.
  • one of the first time period and the second time period is an odd-numbered frame time period, and the other is an even-numbered frame time period.
  • the application also discloses a display device including the pixel circuit as described above.
  • the application also discloses a pixel driving method, which is suitable for the above-mentioned pixel circuit, and includes:
  • Step 1 In the first time period, the first sub-circuit outputs a reset signal to the circuit according to the scan signal provided by the scan line and the first data signal provided by the first data line and performs a compensation action on the circuit;
  • the two sub-circuits output corresponding driving currents to the light-emitting device and write data signals to the pixel unit according to the scan signal provided by the scan line and the second data signal provided by the second data line;
  • Step 2 the first sub-circuit outputs a corresponding driving current to the light-emitting device and to the pixel unit according to the scan signal provided by the scan line and the first data signal provided by the first data line.
  • the second sub-circuit outputs a reset signal to the circuit according to the scan signal provided by the scan line and the second data signal provided by the second data line, and performs a compensation action on the circuit;
  • the step 1 and the step 2 are performed alternately.
  • this application modifies the structure of the original 4T2C circuit and adopts two sub-circuits to work alternately. Circuit compensation and light emission do not occur at the same time within one frame, which improves the circuit compensation effect and luminous efficiency.
  • FIG. 1 is a schematic diagram of a 2T1C pixel driving circuit structure in the prior art
  • FIG. 2 is a schematic diagram of a 4T2C pixel compensation circuit in the prior art
  • FIG. 3 is a timing diagram of a 4T2C pixel compensation circuit in the prior art
  • FIG. 4 is a schematic diagram of a specific circuit structure of a pixel circuit provided by this application.
  • FIG. 5 is a timing diagram of a pixel circuit provided by this application.
  • FIG. 6 is a schematic diagram of a specific circuit structure of another pixel circuit provided by this application.
  • FIG. 7 is a timing diagram of another pixel circuit provided by this application.
  • a pixel circuit includes: a first sub-circuit (denoted as A in FIG. 4), a second sub-circuit (denoted as B in FIG. 4) ) And light emitting device D;
  • the first sub-circuit is connected to the first end of the light-emitting device, the scan line (not shown), the first data line, and the first power supply end; the first sub-circuit is used to connect to the scan signal and the reference signal Ref provided by the scan line
  • the reset signal is output to the circuit during the first time period and the circuit is compensated, the first data signal provided by the first data line writes the data signal to the pixel unit, and the corresponding driving current is output to the light-emitting device during the second time period , Where the reference signal Ref is provided by the circuit.
  • the second sub-circuit is connected to the first terminal, the scan line, the second data line and the first power terminal of the light-emitting device; the second sub-circuit is used for the scan signal provided by the scan line and the second data provided by the second data line
  • the signal outputs a corresponding driving current to the light emitting device during the first time period, and outputs a reset signal to the circuit during the second time period, performs a compensation action on the circuit, and writes a data signal to the pixel unit.
  • the second end of the light emitting device is connected to the second power supply end, and is used for emitting light according to the received driving current.
  • the first power terminal is connected to a high level
  • the second power terminal is connected to a low level
  • the first data line and the second data line are two adjacent data lines.
  • the first sub-circuit and the second sub-circuit of the pixel circuit in this embodiment adopt a symmetrical way of the circuit structure on both sides.
  • the left and right single-sided sub-circuits add a reference signal line and 2 TFTs on the basis of the original 4T2C. Used to control the writing of the reference signal and the driving signal input to the light emitting device.
  • the left side of the circuit is called the first sub-circuit, and the right side is called the second sub-circuit.
  • the first sub-circuit includes: a first transistor T1_A, a second transistor T2_A, a third transistor T3_A, a fourth transistor T4_A, a fifth transistor T5_A, a sixth transistor T6_A, a first capacitor C1_A, and The second capacitor C2_A;
  • the control terminal of the first transistor T1_A inputs the first drive control signal ScanA-1, the first channel terminal of the first transistor T1_A is connected to the first power terminal ELVDD, and the second channel terminal of the first transistor T1_A is connected to the first transistor T4_A. Access end
  • the control terminal of the second transistor T2_A inputs the first data write control signal ScanA-2, the first path end of the second transistor T2_A is connected to the first data line DataA, and the second path end of the second transistor T2_A is connected to the fourth transistor T4_A. Control terminal;
  • the control terminal of the third transistor T3_A inputs the first reset control signal ScanA-4, the first path end of the third transistor T3_A is connected to one end of the first capacitor C1_A, and the second path end of the third transistor T3_A is connected to the second power supply terminal Vss;
  • the other end of the first capacitor C1_A is connected to the control end of the fourth transistor T4_A; the second pass end of the fourth transistor T4_A is connected to the first pass end of the sixth transistor T6_A;
  • the control terminal of the fifth transistor T5_A inputs the first compensation control signal ScanA-3, the first path terminal of the fifth transistor T5_A inputs the reference signal Ref, and the second path terminal of the fifth transistor T5_A is connected to the control terminal of the fourth transistor T4_A;
  • One end of the second capacitor C2_A is connected to the first path end of the third transistor T3_A, and the other end of the second capacitor C2_A is connected to the first path end of the sixth transistor T6_A;
  • the control terminal of the sixth transistor T6_A inputs the first light-emitting control signal ScanA, and the second path of the sixth transistor T6_A is simply connected to the light-emitting device D.
  • the scan signal provided by the scan line of the first sub-circuit includes a first drive control signal ScanA-1, a first data writing control signal ScanA-2, a first reset control signal ScanA-4, a first compensation control signal ScanA-3, and The first light emission control signal ScanA.
  • the second sub-circuit includes: an eleventh transistor T1_B, a twelfth transistor T2_B, a thirteenth transistor T3_B, a fourteenth transistor T4_B, a fifteenth transistor T5_B, a sixteenth transistor T6_B, a third capacitor C1_B, and a fourth capacitor C2_B;
  • the control terminal of the eleventh transistor T1_B inputs the second drive control signal ScanB-1, the first path end of the eleventh transistor T1_B is connected to the first power supply terminal ELVDD, and the second path end of the eleventh transistor T1_B is connected to the fourteenth transistor The first channel end of T4_B;
  • the control terminal of the twelfth transistor T2_B inputs the second data write control signal ScanB-2, the first path end of the twelfth transistor T2_B is connected to the second data line DataB, and the second path end of the twelfth transistor T2_B is connected to the tenth
  • the control terminal of the thirteenth transistor T3_B inputs the second reset control signal ScanB-4, the first path end of the thirteenth transistor T3_B is connected to one end of the third capacitor C1_B, and the second path end of the thirteenth transistor T3_B is connected to the second power supply End Vss;
  • the other end of the third capacitor C1_B is connected to the control end of the fourteenth transistor T4_B; the second pass end of the fourteenth transistor T4_B is connected to the first pass end of the sixteenth transistor T6_B;
  • the control terminal of the fifteenth transistor T5_B inputs the second compensation control signal ScanB-3, the first channel terminal of the fifteenth transistor T5_B inputs the reference signal Ref, and the second channel terminal of the fifteenth transistor T5_B is connected to the fourteenth transistor T4_B Control end
  • One end of the fourth capacitor C2_B is connected to the first path end of the thirteenth transistor T3_B, and the other end of the fourth capacitor C2_B is connected to the first path end of the sixteenth transistor T6_B;
  • the control terminal of the sixteenth transistor T6_B inputs the second light-emitting control signal ScanB, and the second path terminal of the sixteenth transistor T6_B is connected to the light-emitting device D.
  • the scan signal provided by the scan line of the second sub-circuit includes a second drive control signal ScanB-1, a second data write control signal ScanB-2, a second reset control signal ScanB-4, a second compensation control signal ScanB-3, and The second light emission control signal ScanB.
  • the duration of a first time period and a second time period are the same, for example, both of them can be 1 frame, 2 frames, multiple frames or any suitable time period.
  • the two driving modules The aging speed of the driving transistors inside is basically the same.
  • one of the first time period and the second time period is an odd-numbered frame time period, and the other is an even-numbered frame time period (the duration of the first time period and the second time period are both the same) frame).
  • the following takes the first sub-circuit as an example to illustrate its operating mechanism.
  • the second transistor T2_A and the sixth transistor T6_A of all pixels are turned off, the first transistor T1_A, the third transistor T3_A, the fourth transistor T4_A, and the fifth transistor T5_A are turned on, and the circuit performs compensation; after the compensation is completed
  • the first transistor T1_A, the third transistor T3_A, the fifth transistor T5_A, and the sixth transistor T6_A are turned off, and then the second transistor T2_A is turned on by scanning row by row, and the data signal is written in sequence; after the data signal of the last row is written, the second transistor T2_A, the second transistor
  • the three transistors T3_A and the fifth transistor T5_A are turned off, the first transistor T1_A, the fourth transistor T4_A, and the sixth transistor T6_A are turned on, and the light emitting device enters the emission emission step.
  • FIG. 5 is a timing diagram of a pixel circuit of this application.
  • the circuit reset, circuit compensation, and data signal are written into Data input in one frame (Frame1), and the light emission is completed in one frame (Frame2) alone.
  • the first sub-circuit and the second sub-circuit are staggered to complete different steps. For example, when the first sub-circuit completes the circuit reset, circuit compensation, and data signal writing data input steps, the second sub-circuit completes the light emission step, The next frame is exchanged. In this way, the first sub-circuit or the second sub-circuit provides the light-emitting current to the light-emitting device in each frame, and the total running time of the four steps is doubled.
  • the application also discloses a display device including the above-mentioned pixel circuit.
  • the present application also discloses a pixel driving method.
  • the pixel driving method is suitable for the above-mentioned pixel circuit and includes:
  • Step 1 In the first time period (Frame1), the first sub-circuit outputs a reset signal to the circuit according to the scan signal provided by the scan line and the first data signal provided by the first data line, performs a compensation action on the circuit, and writes to the pixel unit Input data signal; the second sub-circuit outputs a corresponding driving current to the light emitting device according to the scan signal provided by the scan line and the second data signal provided by the second data line;
  • Step 2 In the second time period (Frame2), the first sub-circuit outputs the corresponding driving current to the light-emitting device according to the scan signal provided by the scan line and the first data signal provided by the first data line; the second sub-circuit provides the corresponding driving current according to the scan line
  • the second data signal provided by the second data line and the scan signal provided by the second data line output a reset signal to the circuit, perform a compensation action on the circuit, and write a data signal to the pixel unit;
  • Step 1 and step 2 are performed alternately.
  • FIG. 6 is a schematic circuit diagram of another pixel circuit of this application.
  • another pixel circuit includes: a first sub-circuit (denoted as A in FIG. 6), a second sub-circuit (denoted as B in FIG. 6) and a light-emitting device;
  • the first sub-circuit is connected to the first end of the light-emitting device, the scan line, the first data line, and the first power source; the first sub-circuit is used for the scan signal provided by the scan line and the first data provided by the first data line
  • the signal outputs a reset signal to the circuit during the first time period, performs a compensation action on the circuit, and outputs a corresponding driving current to the light-emitting device and writes a data signal to the pixel unit during the second time period;
  • the second sub-circuit is connected to the first terminal, the scan line, the second data line and the first power terminal of the light-emitting device; the second sub-circuit is used for the scan signal provided by the scan line and the second data provided by the second data line
  • the signal outputs a corresponding driving current to the light-emitting device and writes a data signal to the pixel unit during the first time period, and outputs a reset signal to the circuit and performs a compensation action on the circuit during the second time period;
  • the second end of the light emitting device is connected to the second power supply end for emitting light according to the received driving current.
  • the first sub-circuit includes: a first transistor T1_A, a second transistor T2_A, a third transistor T3_A, a fourth transistor T4_A, a fifth transistor T5_A, a sixth transistor T6_A, a first capacitor C1_A, and The second capacitor C2_A;
  • the control terminal of the first transistor T1_A inputs the first drive control signal ScanA-1, the first channel terminal of the first transistor T1_A is connected to the first power terminal, and the second channel terminal of the first transistor T1_A is connected to the first channel of the fourth transistor T4_A end;
  • the control terminal of the second transistor T2_A is connected to the control terminal of the third transistor T3_A and the first data writing control signal ScanA-2 or the first compensation control signal ScanA-3 is input.
  • the first path terminal of the second transistor T2_A is connected to the A data line, the first data line is used for time-sharing input of the first data signal Data A or the first reset control signal ScanA-4, and the second path end of the second transistor T2_A is connected to the control end of the fourth transistor T4_A;
  • the first path end of the third transistor T3_A is connected to one end of the first capacitor C1_A, and the second path end of the third transistor T3_A is connected to the second power supply terminal;
  • the other end of the first capacitor C1_A is connected to the control end of the fourth transistor T4_A; the second pass end of the fourth transistor T4_A is connected to the first pass end of the sixth transistor T6_A;
  • One end of the second capacitor C2_A is connected to the first path end of the third transistor T3_A, and the other end of the second capacitor C2_A is connected to the first path end of the sixth transistor T6_A;
  • the control terminal of the sixth transistor T6_A inputs the first light-emitting control signal ScanA, and the second path terminal of the sixth transistor T6_A is connected to the second power terminal.
  • the scan signal provided by the scan line of the first sub-circuit includes a first drive control signal ScanA-1, a first data writing control signal ScanA-2 or a first compensation control signal ScanA-3, and a first light emission control signal Scan.
  • the second sub-circuit includes: an eleventh transistor T1_B, a twelfth transistor T2_B, a thirteenth transistor T3_B, a fourteenth transistor T4_B, a sixteenth transistor T6_B, a third capacitor C1_A, and a fourth capacitor C2_A;
  • the control terminal of the eleventh transistor T1_B inputs the second drive control signal ScanB-1, the first path terminal of the eleventh transistor T1_B is connected to the first power terminal, and the second path terminal of the eleventh transistor T1_B is connected to the fourteenth transistor T4_B The first channel end;
  • the control terminal of the twelfth transistor T2_B is connected to the control terminal of the thirteenth transistor T3_B and the second data writing control signal ScanB-2 or the second compensation control signal ScanB-3 is input, the first path of the twelfth transistor T2_B
  • the second data line is used for time-sharing input of the second data signal Data B or the second reset control signal ScanB-4, and the second path end of the twelfth transistor T2_B is connected to the control of the fourteenth transistor T4_B end;
  • the first path end of the thirteenth transistor T3_B is connected to one end of the third capacitor C1_A, and the second path end of the thirteenth transistor T3_B is connected to the second power supply terminal;
  • the other end of the third capacitor C1_A is connected to the control end of the fourteenth transistor T4_B; the second pass end of the fourteenth transistor T4_B is connected to the first pass end of the sixteenth transistor T6_B;
  • One end of the fourth capacitor C2_B is connected to the first path end of the thirteenth transistor T3_B, and the other end of the fourth capacitor C2_B is connected to the first path end of the sixteenth transistor T6_B;
  • the control terminal of the sixteenth transistor T6_B inputs the second light-emitting control signal ScanB, and the second path terminal of the sixteenth transistor T6_B is connected to the second power terminal.
  • the scan signal provided by the scan line of the second sub-circuit includes a second drive control signal ScanB-1, a second data signal DataB or a second reset control signal ScanB-4, and a second light emission control signal ScanB.
  • the duration of a first time period and a second time period are the same, for example, both of them can be 1 frame, 2 frames, multiple frames or any suitable time period.
  • the two driving modules The aging speed of the driving transistors inside is basically the same.
  • one of the first time period and the second time period is an odd-numbered frame time period, and the other is an even-numbered frame time period (the duration of the first time period and the second time period are both the same) frame).
  • the following takes the first sub-circuit as an example to illustrate its operating mechanism.
  • the second transistor T2_A and the sixth transistor T6_A of all pixels are turned off, the first transistor T1_A, the third transistor T3_A, the fourth transistor T4_A, and the fifth transistor T5_A are turned on, and the circuit performs compensation; after the compensation is completed
  • the first transistor T1_A, the third transistor T3_A, the fifth transistor T5_A, and the sixth transistor T6_A are turned off, and then the second transistor T2_A is turned on by scanning row by row, and the data signal is written in sequence; after the data signal of the last row is written, the second transistor T2_A, the second transistor
  • the three transistors T3_A and the fifth transistor T5_A are turned off, the first transistor T1_A, the fourth transistor T4_A, and the sixth transistor T6_A are turned on, and the LED emits light and enters the emission Emission step.
  • Figure 7 is a timing diagram of another pixel circuit of this application. .
  • the circuit reset Reset, the circuit compensation Compensation in one frame, the data signal writing Data input and the light emission are completed in another frame.
  • the first sub-circuit and the second sub-circuit are interleaved to complete different steps. For example, when the first sub-circuit completes the circuit reset and circuit compensation steps, the second sub-circuit completes the data signal writing data input and light emission steps. Exchange in the next frame.
  • the advantage of this allocation is that there is no separate reference signal.
  • the data line provides the data signal and the reference signal in different time periods (that is, the signal line marked as Data A in Figure 7 provides the first data signal Data A or The first reset control signal ScanA-4 is marked as Data B.
  • the signal line provides the second data signal Data B or the second reset control signal ScanB-4) in time sharing.
  • the second transistor T2_A and the third transistor T3_A can share the same signal line.
  • the circuit scale is reduced, the compensation time is extended, and the light-emitting time is shortened, but the total running time of the four steps is still twice that before the improvement.
  • circuit reset, circuit compensation Compensation can be completed in the same frame, and data signal writing to Data input and light emission can be completed in another frame.
  • Circuit reset, circuit compensation Compensation, and data signal writing to Data input can also be completed in the same frame.
  • the frame is completed, and the light emission is completed in a single frame.

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Abstract

一种像素电路，包括：第一子电路(A)、第二子电路(B)和发光器件(D)；第一子电路(A)用于根据述扫描线提供的扫描信号(Scan A, Scan A-1, Scan A-2, Scan A-3,Scan A-4)和参考信号(Ref)在第一时间段时输出重置信号至电路并对电路进行补偿动作、第一数据线提供的第一数据信号(Data A)向像素单元写入数据信号、以及在第二时间段时向发光器件(D)输出相应的驱动电流；第二子电路(B)用于根据扫描线提供的扫描信号(Scan B, Scan B-1, Scan B-2, Scan B-3,Scan B-4)和第二数据线提供的第二数据信号(Data B)在第一时间段时向发光器件(D)输出相应的驱动电流，以及在第二时间段时输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；发光器件(D)，其第二端与第二电源端(Vss)连接，用于根据接收到的驱动电流进行发光。

Description

像素电路、显示装置及像素驱动方法
本申请要求于2019年09月30日提交中国国家知识产权局、申请号为201910938272.9、发明名称为“像素电路、显示装置及像素驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，尤其涉及像素电路、显示装置及像素驱动方法。
背景技术
在电流型显示器驱动背板工作过程中，需要在一帧的时间内向发光器件提供一个稳定的电流，以维持其一定的亮度，从而确保灰阶的可控性。在主动式电流驱动背板中为了保持逐行扫描的状态，避免不同像素间信号的干扰，其像素驱动电路最初的架构为2T1C，即2个TFT(Thin Film Transistor，薄膜晶体管)和1个电容，如图1，在图1中，Data为数据信号；Scan为扫描信号；ELVDD为直流高电平；Vss为直流低电平；T1和T2均为TFT；C为电容；Diode为发光二极管。但是由于其中驱动TFT T1长期维持在工作状态下，导致该器件受到Stress影响，从而发生Vth shift的现象；而OLED(Organic Light-Emitting Diode，有机发光二极管)为目前主要的电流型驱动背板的发光元件，同时又因发光元件OLED的有机材料属性，因此容易受到环境等因素的影响而发生材料的退化，其直接影响即为发光效率的降低。以上两种因素导致了2T1C电路无法在量产的产品上采用，必须采用更加复杂的电路来补偿上述两个问题带来的影响。目前比较有效率的像素补偿电路至少为4T以上，以如图2和图3 4T2C电路为例，即4个TFT和2个电容，在图2中，Data为数据信号；SCAN1和SCAN2为扫描信号；ELVDD为直流高电平；T1、T2、T3和T4均为TFT；C、C1和C2为电容。
所有像素补偿电路(包括所述4T2C结构)在时序上均大致分为四个步骤：重置(Reset)、补偿(Compensation)、写入(Data input)和发光(Emission)。每一行像素均包括上述步骤，随像素分辨率不断提高，划分 到每一个步骤的时间不断缩减，直接影响像素的补偿效果和发光效率。
由于在同样的发光效率下，MicroLED所需要的空间远远小于OLED，因此对于MicroLED像素补偿电路来说，可以在空间充裕的条件下通过修改原有电路的结构，以提高电路补偿效果和发光效率。
发明内容
为解决上述技术问题，本申请提供一种像素电路、显示装置及像素驱动方法，采用两个子电路交替工作，以提高电路补偿效果和发光效率。
本申请提供的技术方案如下：
本申请公开了一种像素电路，包括：第一子电路、第二子电路和发光器件；
所述第一子电路，与所述发光器件的第一端、扫描线、第一数据线和第一电源端连接；所述第一子电路用于根据所述扫描线提供的扫描信号和参考信号在第一时间段时输出重置信号至电路并对电路进行补偿动作、第一数据线提供的第一数据信号向像素单元写入数据信号、以及在第二时间段时向所述发光器件输出相应的驱动电流；所述第二子电路，与所述发光器件的第一端、扫描线、第二数据线和第一电源端连接；所述第二子电路用于根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号在第一时间段时向所述发光器件输出相应的驱动电流，以及在第二时间段时输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；
所述发光器件，其第二端与第二电源端连接，用于根据接收到的驱动电流进行发光。
可选的，所述第一子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第一电容以及第二电容；
所述第一晶体管的控制端输入第一驱动控制信号，所述第一晶体管的第一通路端连接第一电源端，所述第一晶体管的第二通路端连接所述第四晶体管的第一通路端；
所述第二晶体管的控制端输入第一数据写入控制信号，所述第二晶体 管的第一通路端连接第一数据线，所述第二晶体管的第二通路端连接所述第四晶体管的控制端；
所述第三晶体管的控制端输入第一复位控制信号，所述第三晶体管的第一通路端连接所述第一电容的一端，所述第三晶体管的第二通路端连接第二电源端；
所述第一电容的另一端连接至所述第四晶体管的控制端；所述第四晶体管的第二通路端连接至所述第六晶体管的第一通路端；
所述第五晶体管的控制端输入第一补偿控制信号，所述第五晶体管的第一通路端输入参考信号，所述第五晶体管的第二通路端连接至所述第四晶体管的控制端；
所述第二电容的一端连接至所述第三晶体管的第一通路端，所述第二电容的另一端连接至所述第六晶体管的第一通路端；
所述第六晶体管的控制端输入第一发光控制信号，所述第六晶体管的第二通路单连接至所述发光器件；
所述第二子电路包括：第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第三电容以及第四电容；
所述第十一晶体管的控制端输入第二驱动控制信号，所述第十一晶体管的第一通路端连接第一电源端，所述第十一晶体管的第二通路端连接所述第十四晶体管的第一通路端；
所述第十二晶体管的控制端输入第二数据写入控制信号，所述第十二晶体管的第一通路端连接所述第二数据线，所述第十二晶体管的第二通路端连接所述第十四晶体管的控制端；
所述第十三晶体管的控制端输入第二复位控制信号，所述第十三晶体管的第一通路端连接所述第三电容的一端，所述第十三晶体管的第二通路端连接第二电源端；
所述第三电容的另一端连接至所述第十四晶体管的控制端；所述第十四晶体管的第二通路端连接至所述第十六晶体管的第一通路端；
所述第十五晶体管的控制端输入第二补偿控制信号，所述第十五晶体管的第一通路端输入参考信号，所述第十五晶体管的第二通路端连接至所 述第十四晶体管的控制端；
所述第四电容的一端连接至所述第十三晶体管的第一通路端，所述第四电容的另一端连接至所述第十六晶体管的第一通路端；
所述第十六晶体管的控制端输入第二发光控制信号，所述第十六晶体管的第二通路端连接至所述发光器件。
可选的，所述第一时间段和所述第二时间段中的一者为奇数帧时间段，另一者为偶数帧时间段。
本申请还公开一种显示装置，包括所述的像素电路。
本申请还公开一种像素驱动方法，所述像素驱动方法适用于上述像素电路，包括：
步骤1、第一时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号向所述发光器件输出相应的驱动电流；
步骤2、第二时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号向所述发光器件输出相应的驱动电流；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；
所述步骤1和所述步骤2交替执行。
本申请还公开一种像素电路，包括：第一子电路、第二子电路和发光器件；
所述第一子电路，与所述发光器件的第一端、扫描线、第一数据线和第一电源端连接；所述第一子电路用于根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号在第一时间段时输出重置信号至电路、对电路进行补偿动作，以及在第二时间段时向所述发光器件输出相应的驱动电流和向像素单元写入数据信号；
所述第二子电路，与所述发光器件的第一端、扫描线、第二数据线和第一电源端连接；所述第二子电路用于根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号在第一时间段时向所述发光器件输出相应的驱动电流以及向像素单元写入数据信号，以及在第二时间段时输出重置信号至电路和对电路进行补偿动作；
所述发光器件，其第二端与第二电源端连接，用于根据接收到的驱动电流进行发光。
可选的，所述第一子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第六晶体管、第一电容以及第二电容；
所述第一晶体管的控制端输入第一驱动控制信号，所述第一晶体管的第一通路端连接第一电源端，所述第一晶体管的第二通路端连接所述第四晶体管的第一通路端；
所述第二晶体管的控制端与所述第三晶体管的控制端相连接并输入第一数据写入控制信号或第一补偿控制信号，所述第二晶体管的第一通路端连接第一数据线，所述第一数据线用于分时输入第一数据信号或第一复位控制信号，所述第二晶体管的第二通路端连接所述第四晶体管的控制端；
所述第三晶体管的第一通路端连接所述第一电容的一端，所述第三晶体管的第二通路端连接第二电源端；
所述第一电容的另一端连接至所述第四晶体管的控制端；所述第四晶体管的第二通路端连接至所述第六晶体管的第一通路端；
所述第二电容的一端连接所述第三晶体管的第一通路端，所述第二电容的另一端连接所述第六晶体管的第一通路端；
所述第六晶体管的控制端输入第一发光控制信号，所述第六晶体管的第二通路端连接第二电源端；
第二子电路包括：第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十六晶体管、第三电容以及第四电容；
所述第十一晶体管的控制端输入第二驱动控制信号，所述第十一晶体管的第一通路端连接第一电源端，所述第十一晶体管的第二通路端连接所述第十四晶体管的第一通路端；
所述第十二晶体管的控制端与所述第十三晶体管的控制端相连接并输入第二数据写入控制信号或第二补偿控制信号，所述第十二晶体管的第一通路端连接所述第二数据线，所述第二数据线用于分时输入第二数据信号或第二复位控制信号，所述第十二晶体管的第二通路端连接所述第十四晶体管的控制端；
所述第十三晶体管的第一通路端连接所述第三电容的一端，所述第十三晶体管的第二通路端连接第二电源端；
所述第三电容的另一端连接至所述第十四晶体管的控制端；所述第十四晶体管的第二通路端连接至所述第十六晶体管的第一通路端；
所述第四电容的一端连接所述第十三晶体管的第一通路端，所述第四电容的另一端连接所述第十六晶体管的第一通路端；
所述第十六晶体管的控制端输入第二发光控制信号，所述第十六晶体管的第二通路端连接第二电源端。
可选的，所述第一时间段和所述第二时间段中的一者为奇数帧时间段，另一者为偶数帧时间段。
本申请还公开了一种显示装置，包括如上述所述的像素电路。
本申请还公开了一种像素驱动方法，所述像素驱动方法适用于上述像素电路，包括：
步骤1、第一时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号输出重置信号至电路以及对电路进行补偿动作；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号向所述发光器件输出相应的驱动电流以及向像素单元写入数据信号；
步骤2、第二时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号向所述发光器件输出相应的驱动电流以及向像素单元写入数据信号；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号输出重置信号至电路以及对电路进行补偿动作；
所述步骤1和所述步骤2交替执行。
与现有技术相比，本申请通过修改原有4T2C电路的结构，采用两个子电路交替工作，电路补偿与发光不在一帧的时间内同时发生，提高电路补偿效果和发光效率。
附图说明
下面将以明确易懂的方式，结合附图说明可选实施方式，对本申请予以进一步说明。
图1为现有技术像素驱动电路架构为2T1C示意图；
图2为现有技术中一种4T2C像素补偿电路的示意图；
图3为现有技术中一种4T2C像素补偿电路的时序图；
图4为本申请提供的一种像素电路的具体电路结构示意图；
图5为本申请提供的一种像素电路的时序图；
图6为本申请提供的另一种像素电路的具体电路结构示意图；
图7为本申请提供的另一种像素电路的时序图。
具体实施方式
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对照附图说明本申请的具体实施方式。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。
为使图面简洁，各图中只示意性地表示出了与本申请相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
图4为本申请一种像素电路的电路示意图；如图4所示，一种像素电路，包括：第一子电路(图4中表示为A)、第二子电路(图4中表示为B)和发光器件D；
第一子电路，与发光器件的第一端、扫描线(图未示)、第一数据线和第一电源端连接；第一子电路用于根据扫描线提供的扫描信号和参考信号Ref在第一时间段时输出重置信号至电路并对电路进行补偿动作、第一数据线提供的第一数据信号向像素单元写入数据信号以及在第二时间段时向发光器件输出相应的驱动电流，其中参考信号Ref为电路提供的。
第二子电路，与发光器件的第一端、扫描线、第二数据线和第一电源端连接；第二子电路用于根据扫描线提供的扫描信号和第二数据线提供的第二数据信号在第一时间段时向发光器件输出相应的驱动电流，以及在第二时间段时输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号。
发光器件，其第二端与第二电源端连接，用于根据接收到的驱动电流进行发光。
其中，第一电源端接入高电平，第二电源端接入低电平；第一数据线和第二数据线为相邻的两个数据线。本实施例中像素电路的第一子电路和第二子电路为两侧电路架构对称方式，其中左右单侧的子电路在原来4T2C的基础上增加一条参考信号线，增加了2个TFT，分别用来控制参考信号的写入和输入到发光器件的驱动信号。电路左侧称为第一子电路，右侧称为第二子电路。
具体的，如图4所示，第一子电路包括：第一晶体管T1_A、第二晶体管T2_A、第三晶体管T3_A、第四晶体管T4_A、第五晶体管T5_A、第六晶体管T6_A、第一电容C1_A以及第二电容C2_A；
第一晶体管T1_A的控制端输入第一驱动控制信号ScanA-1，第一晶体管T1_A的第一通路端连接第一电源端ELVDD，第一晶体管T1_A的第二通路端连接第四晶体管T4_A的第一通路端；
第二晶体管T2_A的控制端输入第一数据写入控制信号ScanA-2，第二晶体管T2_A的第一通路端连接第一数据线DataA，第二晶体管T2_A的第二通路端连接第四晶体管T4_A的控制端；
第三晶体管T3_A的控制端输入第一复位控制信号ScanA-4，第三晶体管T3_A的第一通路端连接第一电容C1_A的一端，第三晶体管T3_A的第 二通路端连接第二电源端Vss；
第一电容C1_A的另一端连接至第四晶体管T4_A的控制端；第四晶体管T4_A的第二通路端连接至第六晶体管T6_A的第一通路端；
第五晶体管T5_A的控制端输入第一补偿控制信号ScanA-3，第五晶体管T5_A的第一通路端输入参考信号Ref，第五晶体管T5_A的第二通路端连接至第四晶体管T4_A的控制端；
第二电容C2_A的一端连接至第三晶体管T3_A的第一通路端，第二电容C2_A的另一端连接至第六晶体管T6_A的第一通路端；
第六晶体管T6_A的控制端输入第一发光控制信号ScanA，第六晶体管T6_A的第二通路单连接至发光器件D。
第一子电路的扫描线提供的扫描信号包括第一驱动控制信号ScanA-1、第一数据写入控制信号ScanA-2、第一复位控制信号ScanA-4、第一补偿控制信号ScanA-3和第一发光控制信号ScanA。
第二子电路包括：第十一晶体管T1_B、第十二晶体管T2_B、第十三晶体管T3_B、第十四晶体管T4_B、第十五晶体管T5_B、第十六晶体管T6_B、第三电容C1_B以及第四电容C2_B；
第十一晶体管T1_B的控制端输入第二驱动控制信号ScanB-1，第十一晶体管T1_B的第一通路端连接第一电源端ELVDD，第十一晶体管T1_B的第二通路端连接第十四晶体管T4_B的第一通路端；
第十二晶体管T2_B的控制端输入第二数据写入控制信号ScanB-2，第十二晶体管T2_B的第一通路端连接第二数据线DataB，第十二晶体管T2_B的第二通路端连接第十四晶体管T4_B的控制端；
第十三晶体管T3_B的控制端输入第二复位控制信号ScanB-4，第十三晶体管T3_B的第一通路端连接第三电容C1_B的一端，第十三晶体管T3_B的第二通路端连接第二电源端Vss；
第三电容C1_B的另一端连接至第十四晶体管T4_B的控制端；第十四晶体管T4_B的第二通路端连接至第十六晶体管T6_B的第一通路端；
第十五晶体管T5_B的控制端输入第二补偿控制信号ScanB-3，第十五晶体管T5_B的第一通路端输入参考信号Ref，第十五晶体管T5_B的第二 通路端连接至第十四晶体管T4_B的控制端；
第四电容C2_B的一端连接至第十三晶体管T3_B的第一通路端，第四电容C2_B的另一端连接至第十六晶体管T6_B的第一通路端；
第十六晶体管T6_B的控制端输入第二发光控制信号ScanB,第十六晶体管T6_B的第二通路端连接至发光器件D。
第二子电路的扫描线提供的扫描信号包括第二驱动控制信号ScanB-1、第二数据写入控制信号ScanB-2、第二复位控制信号ScanB-4、第二补偿控制信号ScanB-3和第二发光控制信号ScanB。本实施例中，可选地，一个第一时间段和一个第二时间段的时长相等，例如两者均可以为1帧、2帧、多帧或任何合适的时段，此时两个驱动模块内的驱动晶体管的老化速度基本一致。作为一种可选实施方案，第一时间段和第二时间段中的一者为奇数帧时间段，另一者为偶数帧时间段(第一时间段和第二时间段的时长均为一帧)。
下面以第一子电路为例说明其运行机制。
电路在重置Reset后，所有像素的第二晶体管T2_A与第六晶体管T6_A关闭，第一晶体管T1_A、第三晶体管T3_A、第四晶体管T4_A、第五晶体管T5_A打开，电路进行补偿动作；补偿完成后第一晶体管T1_A、第三晶体管T3_A、第五晶体管T5_A、第六晶体管T6_A关闭，然后逐行扫描打开第二晶体管T2_A，依次写入数据信号；最后一行数据信号写完后第二晶体管T2_A、第三晶体管T3_A、第五晶体管T5_A关闭，第一晶体管T1_A、第四晶体管T4_A、第六晶体管T6_A打开，发光器件进入发光Emission步骤。
将原来在一帧的时间中需要完成的电路重置Reset、电路补偿Compensation、数据信号写入Data input、发光Emission四个步骤分成2帧完成，图5为本申请一种像素电路的时序图。如图5所示，其中电路重置Reset、电路补偿Compensation、数据信号写入Data input在一帧(Frame1)，发光Emission单独用一帧(Frame2)完成。第一子电路与第二子电路交错完成不同的步骤，例如第一子电路在完成电路重置Reset、电路补偿Compensation、数据信号写入Data input步骤时，第二子电路在完成发光 Emission步骤，下一帧再交换，如此相对发光器件来说每一帧都有第一子电路或第二子电路对其提供发光电流，四个步骤的总运行时间变为原来的2倍。
本申请还公开一种显示装置，包括上述像素电路。
本申请还公开一种像素驱动方法，像素驱动方法适用于上述像素电路，包括：
步骤1、第一时间段(Frame1)，第一子电路根据扫描线提供的扫描信号和第一数据线提供的第一数据信号输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；第二子电路根据扫描线提供的扫描信号和第二数据线提供的第二数据信号向发光器件输出相应的驱动电流；
步骤2、第二时间段(Frame2)，第一子电路根据扫描线提供的扫描信号和第一数据线提供的第一数据信号向发光器件输出相应的驱动电流；第二子电路根据扫描线提供的扫描信号和第二数据线提供的第二数据信号输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；
步骤1和步骤2交替执行。
图6为本申请另一种像素电路的电路示意图。如图6所示，另一种像素电路，包括：第一子电路(图6中表示为A)、第二子电路(图6中表示为B)和发光器件；
第一子电路，与发光器件的第一端、扫描线、第一数据线和第一电源端连接；第一子电路用于根据扫描线提供的扫描信号和第一数据线提供的第一数据信号在第一时间段时输出重置信号至电路、对电路进行补偿动作，以及在第二时间段时向发光器件输出相应的驱动电流和向像素单元写入数据信号；
第二子电路，与发光器件的第一端、扫描线、第二数据线和第一电源端连接；第二子电路用于根据扫描线提供的扫描信号和第二数据线提供的第二数据信号在第一时间段时向发光器件输出相应的驱动电流以及向像素单元写入数据信号，以及在第二时间段时输出重置信号至电路和对电路进行补偿动作；
发光器件，其第二端与第二电源端连接，用于根据接收到的驱动电流 进行发光。
具体的，如图6所示，第一子电路包括：第一晶体管T1_A、第二晶体管T2_A、第三晶体管T3_A、第四晶体管T4_A、第五晶体管T5_A、第六晶体管T6_A、第一电容C1_A以及第二电容C2_A；
第一晶体管T1_A的控制端输入第一驱动控制信号ScanA-1，第一晶体管T1_A的第一通路端连接第一电源端，第一晶体管T1_A的第二通路端连接第四晶体管T4_A的第一通路端；
第二晶体管T2_A的控制端与第三晶体管T3_A的控制端相连接并输入第一数据写入控制信号ScanA-2或第一补偿控制信号ScanA-3，第二晶体管T2_A的第一通路端连接第一数据线，第一数据线用于分时输入第一数据信号Data A或第一复位控制信号ScanA-4，第二晶体管T2_A的第二通路端连接第四晶体管T4_A的控制端；
第三晶体管T3_A的第一通路端连接第一电容C1_A的一端，第三晶体管T3_A的第二通路端连接第二电源端；
第一电容C1_A的另一端连接至第四晶体管T4_A的控制端；第四晶体管T4_A的第二通路端连接至第六晶体管T6_A的第一通路端；
第二电容C2_A的一端连接第三晶体管T3_A的第一通路端，第二电容C2_A的另一端连接第六晶体管T6_A的第一通路端；
第六晶体管T6_A的控制端输入第一发光控制信号ScanA，第六晶体管T6_A的第二通路端连接第二电源端。
第一子电路的扫描线提供的扫描信号包括第一驱动控制信号ScanA-1、第一数据写入控制信号ScanA-2或第一补偿控制信号ScanA-3和第一发光控制信号Scan。
第二子电路包括：第十一晶体管T1_B、第十二晶体管T2_B、第十三晶体管T3_B、第十四晶体管T4_B、第十六晶体管T6_B、第三电容C1_A以及第四电容C2_A；
第十一晶体管T1_B的控制端输入第二驱动控制信号ScanB-1，第十一晶体管T1_B的第一通路端连接第一电源端，第十一晶体管T1_B的第二通路端连接第十四晶体管T4_B的第一通路端；
第十二晶体管T2_B的控制端与第十三晶体管T3_B的控制端相连接并输入第二数据写入控制信号ScanB-2或第二补偿控制信号ScanB-3，第十二晶体管T2_B的第一通路端连接第二数据线，第二数据线用于分时输入第二数据信号Data B或第二复位控制信号ScanB-4，第十二晶体管T2_B的第二通路端连接第十四晶体管T4_B的控制端；
第十三晶体管T3_B的第一通路端连接第三电容C1_A的一端，第十三晶体管T3_B的第二通路端连接第二电源端；
第三电容C1_A的另一端连接至第十四晶体管T4_B的控制端；第十四晶体管T4_B的第二通路端连接至第十六晶体管T6_B的第一通路端；
第四电容C2_B的一端连接第十三晶体管T3_B的第一通路端，第四电容C2_B的另一端连接第十六晶体管T6_B的第一通路端；
第十六晶体管T6_B的控制端输入第二发光控制信号ScanB，第十六晶体管T6_B的第二通路端连接第二电源端。
第二子电路的扫描线提供的扫描信号包括第二驱动控制信号ScanB-1、第二数据信号Data B或第二复位控制信号ScanB-4和第二发光控制信号ScanB。
本实施例中，可选地，一个第一时间段和一个第二时间段的时长相等，例如两者均可以为1帧、2帧、多帧或任何合适的时段，此时两个驱动模块内的驱动晶体管的老化速度基本一致。作为一种可选实施方案，第一时间段和第二时间段中的一者为奇数帧时间段，另一者为偶数帧时间段(第一时间段和第二时间段的时长均为一帧)。
下面以第一子电路为例说明其运行机制。
电路在重置Reset后，所有像素的第二晶体管T2_A与第六晶体管T6_A关闭，第一晶体管T1_A、第三晶体管T3_A、第四晶体管T4_A、第五晶体管T5_A打开，电路进行补偿动作；补偿完成后第一晶体管T1_A、第三晶体管T3_A、第五晶体管T5_A、第六晶体管T6_A关闭，然后逐行扫描打开第二晶体管T2_A，依次写入数据信号；最后一行数据信号写完后第二晶体管T2_A、第三晶体管T3_A、第五晶体管T5_A关闭，第一晶体管T1_A、第四晶体管T4_A、第六晶体管T6_A打开，LED发光进入发光Emission 步骤。
将原来在一帧的时间中需要完成的电路重置Reset、电路补偿Compensation、数据信号写入Data input、发光Emission四个步骤分成2帧完成，图7为本申请另一种像素电路的时序图。如图7所示。其中电路重置Reset、电路补偿Compensation在一帧，数据信号写入Data input和发光Emission在另一帧完成。第一子电路与第二子电路交错完成不同的步骤，例如第一子电路在完成电路重置Reset、电路补偿Compensation步骤时，第二子电路在完成数据信号写入Data input、发光Emission步骤，下一帧再交换，如此分配的优点在于没有单独引出参考信号，数据线分不同时间段提供数据信号和参考信号(即图7中标记为Data A信号线分时提供第一数据信号Data A或第一复位控制信号ScanA-4，标记为Data B信号线分时提供第二数据信号Data B或第二复位控制信号ScanB-4)，第二晶体管T2_A与第三晶体管T3_A可共用同一条信号线(即图7中标记为ScanA-2信号线分时提供第一数据写入控制信号ScanA-2或第一补偿控制信号ScanA-3,标记为ScanB-2信号线分时提供第二数据写入控制信号ScanB-2或第二补偿控制信号ScanB-3)，电路规模缩小，补偿时间延长，发光时间缩短，但是四个步骤的总运行时间仍然是改良前的2倍。
本申请以上两种像素电路基于相同的技术构思，即将原来在一帧的时间中需要完成的电路重置Reset、电路补偿Compensation、数据信号写入Data input、发光Emission四个步骤分成2帧完成，可以将电路重置Reset、电路补偿Compensation在同一帧完成，数据信号写入Data input、发光Emission在另一帧完成，也可以将电路重置Reset、电路补偿Compensation、数据信号写入Data input在同一帧完成，发光Emission单独一帧完成。通过第一子电路和第二子电路交替工作，提高发光效率，同时也提高电路补偿效果。
应当说明的是，上述实施例均可根据需要自由组合。以上所述仅是本申请的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种像素电路，其特征在于，包括：第一子电路、第二子电路和发光器件；
    所述第一子电路，与所述发光器件的第一端、扫描线、第一数据线和第一电源端连接；所述第一子电路用于根据所述扫描线提供的扫描信号和参考信号在第一时间段时输出重置信号至电路并对电路进行补偿动作、第一数据线提供的第一数据信号向像素单元写入数据信号、以及在第二时间段时向所述发光器件输出相应的驱动电流；所述第二子电路，与所述发光器件的第一端、扫描线、第二数据线和第一电源端连接；所述第二子电路用于根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号在第一时间段时向所述发光器件输出相应的驱动电流，以及在第二时间段时输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；
    所述发光器件，其第二端与第二电源端连接，用于根据接收到的驱动电流进行发光。
  2. 根据权利要求1所述的像素电路，其特征在于，所述第一子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第一电容以及第二电容；
    所述第一晶体管的控制端输入第一驱动控制信号，所述第一晶体管的第一通路端连接第一电源端，所述第一晶体管的第二通路端连接所述第四晶体管的第一通路端；
    所述第二晶体管的控制端输入第一数据写入控制信号，所述第二晶体管的第一通路端连接第一数据线，所述第二晶体管的第二通路端连接所述第四晶体管的控制端；
    所述第三晶体管的控制端输入第一复位控制信号，所述第三晶体管的第一通路端连接所述第一电容的一端，所述第三晶体管的第二通路端连接第二电源端；
    所述第一电容的另一端连接至所述第四晶体管的控制端；所述第四晶体管的第二通路端连接至所述第六晶体管的第一通路端；
    所述第五晶体管的控制端输入第一补偿控制信号，所述第五晶体管的第一通路端输入参考信号，所述第五晶体管的第二通路端连接至所述第四晶体管的控制端；
    所述第二电容的一端连接至所述第三晶体管的第一通路端，所述第二电容的另一端连接至所述第六晶体管的第一通路端；
    所述第六晶体管的控制端输入第一发光控制信号，所述第六晶体管的第二通路单连接至所述发光器件；
    所述第二子电路包括：第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第三电容以及第四电容；
    所述第十一晶体管的控制端输入第二驱动控制信号，所述第十一晶体管的第一通路端连接第一电源端，所述第十一晶体管的第二通路端连接所述第十四晶体管的第一通路端；
    所述第十二晶体管的控制端输入第二数据写入控制信号，所述第十二晶体管的第一通路端连接所述第二数据线，所述第十二晶体管的第二通路端连接所述第十四晶体管的控制端；
    所述第十三晶体管的控制端输入第二复位控制信号，所述第十三晶体管的第一通路端连接所述第三电容的一端，所述第十三晶体管的第二通路端连接第二电源端；
    所述第三电容的另一端连接至所述第十四晶体管的控制端；所述第十四晶体管的第二通路端连接至所述第十六晶体管的第一通路端；
    所述第十五晶体管的控制端输入第二补偿控制信号，所述第十五晶体管的第一通路端输入参考信号，所述第十五晶体管的第二通路端连接至所述第十四晶体管的控制端；
    所述第四电容的一端连接至所述第十三晶体管的第一通路端，所述第四电容的另一端连接至所述第十六晶体管的第一通路端；
    所述第十六晶体管的控制端输入第二发光控制信号，所述第十六晶体管的第二通路端连接至所述发光器件。
  3. 根据权利要求1所述的像素电路，其特征在于，所述第一时间段和所述第二时间段中的一者为奇数帧时间段，另一者为偶数帧时间段。
  4. 一种显示装置，其特征在于，包括如上述权利要求1-3任意一项所述的像素电路。
  5. 一种像素驱动方法，其特征在于，所述像素驱动方法适用于上述权利要求1-3中任一所述的像素电路，包括：
    步骤1、第一时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号向所述发光器件输出相应的驱动电流；
    步骤2、第二时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号向所述发光器件输出相应的驱动电流；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号输出重置信号至电路、对电路进行补偿动作以及向像素单元写入数据信号；
    所述步骤1和所述步骤2交替执行。
  6. 一种像素电路，其特征在于，包括：第一子电路、第二子电路和发光器件；
    所述第一子电路，与所述发光器件的第一端、扫描线、第一数据线和第一电源端连接；所述第一子电路用于根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号在第一时间段时输出重置信号至电路、对电路进行补偿动作，以及在第二时间段时向所述发光器件输出相应的驱动电流和向像素单元写入数据信号；
    所述第二子电路，与所述发光器件的第一端、扫描线、第二数据线和第一电源端连接；所述第二子电路用于根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号在第一时间段时向所述发光器件输出相应的驱动电流以及向像素单元写入数据信号，以及在第二时间段时输出重置信号至电路和对电路进行补偿动作；
    所述发光器件，其第二端与第二电源端连接，用于根据接收到的驱动电流进行发光。
  7. 根据权利要求6所述的像素电路，其特征在于：
    所述第一子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第六晶体管、第一电容以及第二电容；
    所述第一晶体管的控制端输入第一驱动控制信号，所述第一晶体管的第一通路端连接第一电源端，所述第一晶体管的第二通路端连接所述第四晶体管的第一通路端；
    所述第二晶体管的控制端与所述第三晶体管的控制端相连接并输入第一数据写入控制信号或第一补偿控制信号，所述第二晶体管的第一通路端连接第一数据线，所述第一数据线用于分时输入第一数据信号或第一复位控制信号，所述第二晶体管的第二通路端连接所述第四晶体管的控制端；
    所述第三晶体管的第一通路端连接所述第一电容的一端，所述第三晶体管的第二通路端连接第二电源端；
    所述第一电容的另一端连接至所述第四晶体管的控制端；所述第四晶体管的第二通路端连接至所述第六晶体管的第一通路端；
    所述第二电容的一端连接所述第三晶体管的第一通路端，所述第二电容的另一端连接所述第六晶体管的第一通路端；
    所述第六晶体管的控制端输入第一发光控制信号，所述第六晶体管的第二通路端连接第二电源端；
    第二子电路包括：第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十六晶体管、第三电容以及第四电容；
    所述第十一晶体管的控制端输入第二驱动控制信号，所述第十一晶体管的第一通路端连接第一电源端，所述第十一晶体管的第二通路端连接所述第十四晶体管的第一通路端；
    所述第十二晶体管的控制端与所述第十三晶体管的控制端相连接并输入第二数据写入控制信号或第二补偿控制信号，所述第十二晶体管的第一通路端连接所述第二数据线，所述第二数据线用于分时输入第二数据信号或第二复位控制信号，所述第十二晶体管的第二通路端连接所述第十四晶体管的控制端；
    所述第十三晶体管的第一通路端连接所述第三电容的一端，所述第十 三晶体管的第二通路端连接第二电源端；
    所述第三电容的另一端连接至所述第十四晶体管的控制端；所述第十四晶体管的第二通路端连接至所述第十六晶体管的第一通路端；
    所述第四电容的一端连接所述第十三晶体管的第一通路端，所述第四电容的另一端连接所述第十六晶体管的第一通路端；
    所述第十六晶体管的控制端输入第二发光控制信号，所述第十六晶体管的第二通路端连接第二电源端。
  8. 根据权利要求6所述的像素电路，其特征在于，所述第一时间段和所述第二时间段中的一者为奇数帧时间段，另一者为偶数帧时间段。
  9. 一种显示装置，其特征在于，包括如上述权利要求6-8任意一项所述的像素电路。
  10. 一种像素驱动方法，其特征在于，所述像素驱动方法适用于上述权利要求6-8中任一所述像素电路，包括：
    步骤1、第一时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号输出重置信号至电路以及对电路进行补偿动作；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号向所述发光器件输出相应的驱动电流以及向像素单元写入数据信号；
    步骤2、第二时间段，所述第一子电路根据所述扫描线提供的扫描信号和所述第一数据线提供的第一数据信号向所述发光器件输出相应的驱动电流以及向像素单元写入数据信号；第二子电路根据所述扫描线提供的扫描信号和所述第二数据线提供的第二数据信号输出重置信号至电路以及对电路进行补偿动作；
    所述步骤1和所述步骤2交替执行。
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CN110675805A (zh) * 2019-09-30 2020-01-10 南京中电熊猫液晶显示科技有限公司 像素电路、显示装置及像素驱动方法
CN111261113B (zh) * 2020-03-26 2021-08-06 合肥京东方卓印科技有限公司 显示面板、显示装置
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Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080082065A (ko) * 2007-03-07 2008-09-11 엘지디스플레이 주식회사 발광 표시 장치 및 그 구동 방법
CN101727826A (zh) * 2008-10-30 2010-06-09 乐金显示有限公司 有机发光二极管显示器
CN101937647A (zh) * 2010-09-02 2011-01-05 上海交通大学 互补驱动式像素电路
CN103927991A (zh) * 2014-04-29 2014-07-16 何东阳 一种amoled像素电路
CN104050927A (zh) * 2014-07-08 2014-09-17 何东阳 一种amoled像素电路
CN105609047A (zh) * 2016-01-04 2016-05-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN106097959A (zh) * 2016-06-02 2016-11-09 京东方科技集团股份有限公司 像素单元及其驱动方法、像素驱动电路和显示装置
CN107452336A (zh) * 2017-09-25 2017-12-08 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及其驱动方法
CN107886901A (zh) * 2017-12-04 2018-04-06 合肥鑫晟光电科技有限公司 像素驱动电路、显示面板及其驱动方法
CN108010486A (zh) * 2017-12-08 2018-05-08 南京中电熊猫平板显示科技有限公司 一种像素驱动电路及其驱动方法
CN108182908A (zh) * 2018-03-26 2018-06-19 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及其驱动方法
CN110189691A (zh) * 2019-05-14 2019-08-30 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN110675805A (zh) * 2019-09-30 2020-01-10 南京中电熊猫液晶显示科技有限公司 像素电路、显示装置及像素驱动方法
KR20200034477A (ko) * 2018-09-21 2020-03-31 엘지디스플레이 주식회사 전계 발광 표시장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050062866A1 (en) * 2003-09-23 2005-03-24 Ang Lin Ping Multiplexed pixel column architecture for imagers
CN202976779U (zh) * 2012-12-05 2013-06-05 京东方科技集团股份有限公司 一种像素电路、显示面板及显示装置
CN103474024B (zh) * 2013-09-06 2015-09-16 京东方科技集团股份有限公司 一种像素电路及显示器
CN104008726B (zh) * 2014-05-20 2016-05-04 华南理工大学 有源有机电致发光显示器的像素电路及其驱动方法
CN106601169B (zh) * 2016-12-29 2019-08-02 南京华东电子信息科技股份有限公司 双向扫描栅极驱动电路
CN108717841B (zh) * 2018-05-29 2020-07-28 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法、oled显示面板及其驱动电路和驱动方法
CN109410841B (zh) * 2018-11-16 2021-08-06 京东方科技集团股份有限公司 像素电路、显示装置和像素驱动方法

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080082065A (ko) * 2007-03-07 2008-09-11 엘지디스플레이 주식회사 발광 표시 장치 및 그 구동 방법
CN101727826A (zh) * 2008-10-30 2010-06-09 乐金显示有限公司 有机发光二极管显示器
CN101937647A (zh) * 2010-09-02 2011-01-05 上海交通大学 互补驱动式像素电路
CN103927991A (zh) * 2014-04-29 2014-07-16 何东阳 一种amoled像素电路
CN104050927A (zh) * 2014-07-08 2014-09-17 何东阳 一种amoled像素电路
CN105609047A (zh) * 2016-01-04 2016-05-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN106097959A (zh) * 2016-06-02 2016-11-09 京东方科技集团股份有限公司 像素单元及其驱动方法、像素驱动电路和显示装置
CN107452336A (zh) * 2017-09-25 2017-12-08 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及其驱动方法
CN107886901A (zh) * 2017-12-04 2018-04-06 合肥鑫晟光电科技有限公司 像素驱动电路、显示面板及其驱动方法
CN108010486A (zh) * 2017-12-08 2018-05-08 南京中电熊猫平板显示科技有限公司 一种像素驱动电路及其驱动方法
CN108182908A (zh) * 2018-03-26 2018-06-19 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及其驱动方法
KR20200034477A (ko) * 2018-09-21 2020-03-31 엘지디스플레이 주식회사 전계 발광 표시장치
CN110189691A (zh) * 2019-05-14 2019-08-30 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN110675805A (zh) * 2019-09-30 2020-01-10 南京中电熊猫液晶显示科技有限公司 像素电路、显示装置及像素驱动方法

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