WO2021056985A1 - 电接触结构、掩模板组合、接触插塞制作方法及半导体器件 - Google Patents

电接触结构、掩模板组合、接触插塞制作方法及半导体器件 Download PDF

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Publication number
WO2021056985A1
WO2021056985A1 PCT/CN2020/079581 CN2020079581W WO2021056985A1 WO 2021056985 A1 WO2021056985 A1 WO 2021056985A1 CN 2020079581 W CN2020079581 W CN 2020079581W WO 2021056985 A1 WO2021056985 A1 WO 2021056985A1
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WIPO (PCT)
Prior art keywords
area
contact
core
mask
layer
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PCT/CN2020/079581
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English (en)
French (fr)
Inventor
赖惠先
童宇诚
林昭维
朱家仪
吕前宏
Original Assignee
福建省晋华集成电路有限公司
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Priority claimed from CN201910927008.5A external-priority patent/CN111640748A/zh
Priority claimed from CN201910925253.2A external-priority patent/CN111640705A/zh
Application filed by 福建省晋华集成电路有限公司 filed Critical 福建省晋华集成电路有限公司
Priority to US17/612,231 priority Critical patent/US20220254785A1/en
Publication of WO2021056985A1 publication Critical patent/WO2021056985A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Definitions

  • the present invention relates to the technical field of semiconductors, in particular to an electrical contact structure, a mask plate combination and a method for manufacturing a contact plug, a semiconductor device and a manufacturing method thereof.
  • integrated circuits Due to the difference in circuit pattern spacing, integrated circuits are generally divided into device dense area (Dense), device sparse area (ISO) and device isolated area.
  • the device dense area is the area with higher device density (that is, the device is denser), and the device sparse area It is an area where the device density is low (that is, the device is relatively sparse), and the device isolated area is an area where the relatively sparse area and the dense area are separately arranged.
  • the density of circuit patterns and/or device heights also continue to increase, subject to the resolution limit of the optical exposure too1 and the density difference between dense and sparse devices.
  • the influence of the effect ie the density/sparse effect of the circuit pattern
  • the difficulty in performing the photolithography process and/or the etching process will also increase a lot (for example, the process margin is reduced), which in turn leads to the deterioration of the manufactured semiconductor device Performance is affected.
  • each memory cell in the core area of the memory array can be composed of a metal oxide semiconductor (MOS) transistor and a capacitor (capacitor) connected in series.
  • MOS metal oxide semiconductor
  • capacitor capacitor
  • the capacitor is located in the core area of the storage array, the capacitor is stacked above the bit line and is electrically coupled to the storage node contact portion corresponding to the capacitor, and the storage node contact portion is electrically coupled to the active area below it.
  • the contact hole on the outermost edge of the core area of the memory array is prone to abnormalities, which will lead to The formed capacitor has a reduced contact area with the contact plug in the contact hole and an increase in contact resistance, even causing the collapse of the capacitor at the outermost boundary of the array storage area.
  • the purpose of the present invention is to provide an electrical contact structure, a mask combination and a contact plug manufacturing method, a semiconductor device and a manufacturing method thereof, so as to solve the problem of the optical proximity effect and circuit pattern of the existing semiconductor devices such as dynamic random access memory.
  • the dense/sparse effect causes problems such as abnormal electrical structures connected to the contact plugs on the outermost boundary of the core area, and improves device performance.
  • the present invention provides an electrical contact structure of a semiconductor device, the semiconductor device includes a substrate, the substrate includes a core area, a peripheral area, and a boundary area between the core area and the peripheral area, An isolation structure is formed in the junction area, a plurality of core elements are formed in the core area, each of the core elements includes an active area, and the electrical contact structure includes:
  • a plurality of contact plugs formed above the core area and the isolation structure
  • the plurality of contact plugs include the first contact plug closest to the peripheral area, at least the first contact plug is formed above the isolation structure and contacts the isolation structure, and the rest The contact plug is formed above each of the core elements in the core area and the bottom is in contact with the corresponding active area of the core element.
  • the present invention also provides a semiconductor device, including:
  • a substrate the substrate includes a core area, a peripheral area, and a boundary area between the core area and the peripheral area, an isolation structure is formed in the boundary area, and a plurality of core elements are formed in the core area, Each of the core elements includes an active area;
  • the electrical contact structure is formed in the interlayer dielectric layer.
  • the present invention also provides a method for manufacturing an electrical contact structure of a semiconductor device according to the present invention, which is characterized in that it includes:
  • a substrate is provided, the substrate has a core area, a peripheral area, and a boundary area between the core area and the peripheral area, an isolation structure is formed in the boundary area, and a plurality of core elements are formed in the core area , Each of the core elements includes an active area;
  • An interlayer dielectric layer is formed on the substrate, and a plurality of contact holes are formed in the interlayer dielectric layer, wherein the plurality of contact holes includes the first contact hole closest to the peripheral area, at least The first contact hole penetrates the interlayer dielectric layer and exposes a part of the isolation structure, and the remaining contact holes penetrate the interlayer dielectric layer and expose the corresponding active area of the core element;
  • a corresponding contact plug is formed in each of the contact holes.
  • the present invention also provides a method for manufacturing a semiconductor device, including: using the method for manufacturing an electrical contact structure of a semiconductor device according to the present invention, a semiconductor substrate having a core area, a peripheral area, and an isolation structure Corresponding electrical contact structure is formed on it.
  • the first contact plug By forming at least the first contact plug closest to the peripheral area above and in contact with the isolation structure in the junction area of the core area and the peripheral area, the first contact plug can be made to be in contact with the isolation structure as a whole.
  • the isolation structure overlaps.
  • a part of the bottom of the first contact plug may overlap with the isolation structure, and another part of the bottom may overlap with the active area of the core area next to the isolation structure. This may even further make the first contact plug overlap with the isolation structure.
  • the top of the plug is at least connected with the top of the contact plug immediately above the active area of the core area of the isolation structure.
  • the electrical structure originally formed on the outermost edge of the core area boundary can be completely formed on the isolation structure of the junction area as a virtual structure, and the virtual structure can ensure The consistency of the electrical structure on the boundary of the core area and the internal contact plugs.
  • the top of the first contact plug overlaps with the core area
  • the cross-sectional area of the top of the first contact plug is relatively increased.
  • the process margin is conducive to the increase in the size of the electrical structure in the junction area, and avoids the electrical structure in the junction area from being abnormal or collapsed; on the other hand, it can make the electrical structure and the first contact plug formed above the first contact plug.
  • Each contact plug has a larger contact area, thereby reducing the contact resistance, which is beneficial to improve the electrical performance of the device; more importantly, the first contact plug increases the size of the electrical structure connected to it, which can buffer
  • the density difference of the circuit pattern between the core area and the peripheral area can improve the optical proximity effect, reduce the sparse/dense load effect, and ensure the core area in the photolithography process and/or etching process for forming all the electrical structures in the core area.
  • the consistency of the electrical structure above the contact plugs in the area improves the device performance.
  • the first contact plug is at least partially located on the junction area, on the one hand, the first contact plug and the electrical structure connected to it can be minimized (the area of the electrical structure can be reduced).
  • the occupied area of the core area is conducive to improving the effective area utilization of the core area, and thus the device density; on the other hand, the size of the first contact plug and the electrical structure connected to it can be increased as much as possible, thereby It has a better effect in improving the consistency between the electrical structures connected to all the contact plugs inside the core area.
  • the present invention also provides a mask plate assembly for making contact plugs, the mask plate assembly comprising:
  • the first mask plate has a plurality of parallel first light-shielding stripes, and a first light-transmitting area is formed between two adjacent first light-shielding stripes;
  • the second mask plate has a plurality of parallel second light-shielding stripes, and a second light-transmitting area is formed between two adjacent second light-shielding stripes;
  • the third mask plate has a light-shielding block and a third light-transmitting area complementary to the light-shielding block;
  • the plurality of parallel second light-shielding stripes intersect each of the first stripes, so
  • the light-shielding block covers at least one first light-shielding stripe closest to the boundary of the first mask and a part of the first light-transmitting area closest to the covered first light-shielding stripe, and the light-shielding block also covers the most At least two second light-shielding stripes close to the boundary of the second mask and a part of the second light-transmitting area between the two covered second light-shielding stripes, the third light-transmitting area, the The overlapping area of the first light-transmitting area and the second light-transmitting area is an area for forming a contact plug.
  • the present invention also provides a contact plug manufacturing method, which is manufactured by using the mask plate combination of the present invention, and the contact plug manufacturing method includes:
  • the pattern on the first mask plate in the mask plate assembly is transferred to the first mask layer to obtain the transferred first mask layer, and the transferred first mask layer A plurality of first lines are formed in the first mask layer, wherein each of the first lines corresponds to a corresponding first light-shielding stripe on the first mask plate, and the grooves between adjacent first lines Corresponding to the corresponding first light-transmitting area on the first mask plate and exposing the corresponding interlayer dielectric layer;
  • a second mask layer is covered on the interlayer dielectric layer and the first mask layer, and the pattern on the second mask plate in the mask plate combination is transferred to On the second mask layer to obtain a transferred second mask layer, a plurality of second lines are formed in the transferred second mask layer, and each of the plurality of second lines is The first lines intersect, wherein each of the second lines corresponds to a corresponding second light-shielding stripe on the second mask plate, and the grooves between adjacent second lines correspond to corresponding ones on the second mask plate.
  • the third mask layer on the first mask layer, the second mask layer and the interlayer dielectric layer, and adopt a photolithography combined etching process to combine the third mask in the mask combination Is transferred to the third mask layer to obtain a transferred third mask layer, the transferred third mask layer corresponds to the light-shielding block of the third mask plate, and the transferred third mask layer
  • the interlayer dielectric layer jointly exposed by the three mask layers, the transferred first mask layer and the transferred second mask layer serves as a region where contact plugs are to be formed;
  • the exposed interlayer dielectric layer is etched to Forming a plurality of contact holes exposing the corresponding active area
  • a contact plug is formed in each of the contact holes, and the bottom of each of the contact plugs is in contact with the corresponding active region.
  • the present invention also provides a method for manufacturing a semiconductor device, including: using the method for manufacturing contact plugs of the present invention, forming contact plugs on a semiconductor substrate with a core region, each of the The bottom of the contact plug is in contact with the active area of the corresponding core element in the core area.
  • the present invention also provides a semiconductor device manufactured using the semiconductor device manufacturing method of the present invention, including:
  • a semiconductor substrate including a core area, a plurality of core elements are formed in the core area, and each of the core elements includes an active area;
  • a plurality of contact plugs are formed in the interlayer dielectric layer and are in contact with the active area of the corresponding core element;
  • the formation position of the contact plug is defined, so that there is no contact plug above part of the active area at the boundary of the core area, and other active areas at the boundary of the core area and inside the core area There are contact plugs above the active area. Therefore, when the existing process is used to form the corresponding electrical structure inside and at the boundary of the core area, part of the electrical structure at the boundary of the core area is not connected to the lower part of the electrical structure.
  • the contact plug in the active area becomes a virtual structure, which can avoid the problem that the manufactured semiconductor device cannot pass the relevant test due to the electrical structure problem at the boundary of the core area, thereby improving the manufactured semiconductor device The performance and pass rate.
  • FIGS. 1A to 1C are schematic cross-sectional structural diagrams of an electrical contact structure of a semiconductor device according to a specific embodiment of the present invention.
  • FIG. 2A to 2D are schematic diagrams of cross-sectional structures in a manufacturing method of a specific example of the electrical contact structure of the semiconductor device of FIG. 1C;
  • 3A to 3D are schematic cross-sectional structural views of another specific example of the manufacturing method of the electrical contact structure of the semiconductor device of FIG. 1C;
  • FIG. 4 is a schematic diagram of a top view structure in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • 5-13 are schematic diagrams of the cross-sectional structure along the line aa' in FIG. 4 in a method of manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 14 is a schematic diagram of the structure of the first mask plate of the specific embodiment of the present invention.
  • FIG. 15 is a schematic structural diagram of a second mask plate according to a specific embodiment of the present invention.
  • FIG. 16 is a schematic diagram of the structure of a first mask plate of a specific embodiment of the present invention.
  • FIG. 17A is a schematic diagram of the structure after the pattern alignment and overlap of the first mask plate and the active area of the core area according to a specific embodiment of the present invention (some layers that affect the observation pattern alignment and overlap effect are omitted);
  • 17B is a schematic structural diagram of the second mask plate, the first mask plate, and the active area of the core area of the specific embodiment of the present invention after the pattern alignment overlaps (some layers that affect the observation pattern alignment overlap effect are omitted);
  • 17C is a schematic diagram of the structure after the pattern alignment of the third mask plate, the second mask plate, the first mask plate and the active area of the core area according to a specific embodiment of the present invention are overlapped (some of which are omitted to affect the observation pattern alignment overlap Effect layer);
  • FIG. 18 is a schematic diagram of the distribution of contact plugs fabricated on the core area using a mask plate combination in a specific embodiment of the present invention, wherein there are no contact plugs above part of the active area at the boundary of the core area;
  • FIG. 19 is a schematic cross-sectional structure diagram of a specific embodiment of the present invention at the boundary of the core area in FIG. 18 and along the line aa';
  • 20 is a schematic diagram of a cross-sectional structure of a semiconductor device at the boundary of the core region according to a specific embodiment of the present invention.
  • I-core area I-core area; II-peripheral area; III-junction area; H1, H2-depth; AA1, AA2-active area; WL-buried word line; BL-bit line; S/D1, S/D2- Source and drain regions; G1-gate structure; W1-first width; W2-second width;
  • FIG. 1A is a schematic cross-sectional view showing an electrical contact structure of a semiconductor device according to an embodiment of the invention.
  • an electrical contact structure of a semiconductor device provided by an embodiment of the present invention includes: a substrate 100 and a plurality of contact plugs 103a, 103b.
  • the substrate 100 includes a core area I and a peripheral area II, and a boundary area III (also referred to as an interface) between the core area I and the peripheral area II, and an isolation structure is formed in the boundary area III 100a
  • the core area I is the device dense area
  • the surrounding peripheral area II is the device sparse area.
  • a plurality of contact plugs 103a, 103b are formed above the isolation structure 100a of the core area I and the boundary area III, and at least the first contact plug 103b closest to the peripheral area II is formed at the boundary Above the isolation structure 100a of the region III, and the bottom is in contact with the isolation structure 100a of the junction region III, the remaining contact plugs 103a are all formed above the core element (not shown) of the core region I, and the bottom It is in contact with the corresponding active area 101 of the core element.
  • Each contact plug 103a, 103b may include a barrier metal layer (not shown) and a metal layer (not shown), and the barrier metal layer may include, for example, Ti, Ta, Mo, Ti x N y , Ta x N y , TixZry , Ti x Zr y N z , Nb x N y , Zr x N y , W x N y , V x N y , Hf x N y , Mo x N y , Ru x N y and/or Ti x Si y N z .
  • the metal layer may include, for example, tungsten, copper, and/or aluminum.
  • Each contact plug 103a may also include a metal silicide to reduce the contact resistance between it and the active region 101.
  • the bottom of the first contact plug 103b completely overlaps the isolation structure 100a of the junction area III, and the bottom of the first contact plug 103b can extend into the junction area III.
  • the interior of the isolation structure 100a, optionally, the bottom of the first contact plug 103b extends into the interior of the isolation structure 100a of the junction area III.
  • the depth H1 is smaller than that of the remaining contact plugs 103a (ie, the core
  • the bottom of the contact plug 103a) in the region I extends to the depth H2 in the corresponding active region 101.
  • the first contact plug 103b on the isolation structure 100a of the junction area III overlaps the isolation structure 100a as a whole, so that it can be originally located at the outermost boundary of the core area I
  • the electrical structure formed on the above (not shown, refer to the capacitor in FIG. 13) is completely formed above the isolation structure 100a of the junction area III and serves as a virtual structure, and then the virtual structure is used to ensure that the contact plugs 103a in the core area I are on The consistency of the electrical structure of the connection.
  • 1B is a schematic cross-sectional view showing an electrical contact structure of a semiconductor device according to another embodiment of the invention.
  • the electrical contact structure of a semiconductor device provided by another embodiment of the present invention includes: a substrate 100 and a plurality of contact plugs 103a, 103b.
  • the substrate 100 has a core area I, a peripheral area II, and a boundary area III between the core area I and the peripheral area II, an isolation structure 100a is formed in the interface area III, and the core area I is a device In the dense area, the surrounding area II is the device sparse area.
  • a plurality of contact plugs 103a, 103b are formed above the isolation structure 100a of the core area I and the boundary area III, and at least the first contact plug 103b closest to the peripheral area II is formed at the boundary
  • the isolation structure 100a of the region III and the core region I are immediately above the active region 101 of the isolation structure 100a of the junction region III, and a part of the bottom is in contact with and overlaps with the isolation structure 100a of the junction region III. The other part is in contact with and overlaps with the active region 101 of the isolation structure 100a in the core region I next to the boundary region III.
  • the bottom of the first contact plug 103b in this embodiment is The isolation structure 100a of the junction area III extends laterally to the active area 101 of the core area I of the isolation structure 100a of the junction area III, and the bottom of the first contact plug 103b can extend into The isolation structure 100a of the junction area III and the inside of the corresponding active area 101.
  • the depth H1 that the bottom of the first contact plug 103b extends into the interior of the isolation structure 100a of the junction area III is smaller than that of the rest of the contact plugs 103a (that is, the contact plugs in the core area I).
  • the bottom of the plug 103a) extends into the corresponding active region 101 to a depth H2.
  • a gate buried in the substrate 100 (not shown, refer to the buried word line WL in FIG. 5) is formed in the substrate, only one side of the first contact plug 103b is closest to it The adjacent gate contact is buried in the substrate 100.
  • a part of the bottom of the first contact plug 103b above the isolation structure 100a of the junction area III overlaps with the isolation structure 100a of the junction area III, and the other part of the bottom is isolated from the isolation structure immediately adjacent to the junction area III.
  • the active region 101 of the core region I of the structure 100a overlaps, therefore, the cross-sectional area of the first contact plug 103b above the isolation structure 100a of the junction region III is relatively increased.
  • the process of the structure (not shown, refer to the capacitor in FIG. 13) provides sufficient process margin, which is beneficial to increase the size of the electrical structure on the junction area III, and avoids the first contact plug in the junction area III
  • the electrical structure connected to 103b is abnormal or collapsed; on the other hand, the electrical structure connected to the first contact plug 103b of the junction area III and the first contact plug 103b can have a larger contact area, thereby reducing The contact resistance is beneficial to improve the electrical performance of the device; more importantly, the first contact plug 103b in the junction area III increases the size of the electrical structure connected to it, which can buffer the core area I and the peripheral area II.
  • the optical proximity effect can be improved in the photolithography process and/or etching process of forming all the electrical structures in the core area I, and the sparse/dense loading effect can be reduced to ensure that each of the core area I
  • the consistency of the electrical structure above the contact plug 103a improves the performance of the device.
  • FIG. 1C is a schematic cross-sectional view showing an electrical contact structure of a semiconductor device according to another embodiment of the present invention.
  • the electrical contact structure of a semiconductor device provided by another embodiment of the present invention includes: a substrate 100 and a plurality of contact plugs 103a, 103b.
  • the substrate 100 has a core area I and a peripheral area II, and a boundary area III between the core area I and the peripheral area II.
  • An isolation structure 100a is formed in the boundary area III, and the core area I is a device.
  • the surrounding area II is the device sparse area.
  • a plurality of contact plugs 103a, 103b are formed above the isolation structure 100a of the core area I and the boundary area III, and at least the first contact plug 103b closest to the peripheral area II is formed at the boundary Above the isolation structure 100a of the region III, and its bottom completely overlaps the isolation structure 100a of the junction region III, and the top is at least on the active region 101 of the isolation structure 100a in the core region I next to the junction region III.
  • One contact plug 103a is connected together.
  • the difference between the first contact plug 103b in this embodiment and the first contact plug 103b in the embodiment shown in FIG. 1A is that the top of the first contact plug 103b in this embodiment is directly connected to the top of the first contact plug 103b in this embodiment.
  • the tops of at least one contact plug 103a on the active region 101 of the core region I of the isolation structure 100a of the junction region III are connected together.
  • the top cross-sectional area of the combined contact structure formed by connecting the tops of the first contact plug 103b and the other at least one contact plug 103a above the isolation structure 100a of the junction area III The relative increase, on the one hand, provides sufficient process margin for the subsequent process of forming an electrical structure (not shown, refer to the capacitor in FIG. 13) in the junction area III, which is beneficial to the development of the electrical structure on the junction area III.
  • the increase in size prevents the electrical structure connected to the combined contact structure of the junction area III from being abnormal or collapsed; on the other hand, it can make the electrical structure connected to the combined contact structure of the junction area III and the combined contact structure larger
  • the contact area, thereby reducing the contact resistance, is conducive to improving the electrical performance of the device; more importantly, the combined contact structure of the junction area III increases the size of the electrical structure connected to it, which can buffer the core area I and the periphery
  • the density difference of the circuit patterns between the regions II can improve the optical proximity effect, reduce the sparse/dense load effect, and ensure the core region I in the photolithography process and/or etching process for forming all the electrical structures in the core region I
  • the consistency of the electrical structure above the contact plug 103a in each of the contact plugs 103a improves the performance of the device. All the contact plugs 103b and 103a connected together at the top form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure.
  • the first contact plug 103b and the contact hole corresponding to each contact plug 103a in the core region I are formed by the same etching process and the same filling process to simplify Craft. And because the bottom of the contact hole corresponding to the contact plug 103a needs to expose the active region 101, and the bottom of the contact hole corresponding to the first contact plug 103b of the interface region III needs to expose the isolation structure 100a, and the isolation structure 100a The material of the active region 101 is different from that of the active region 101. When the corresponding contact holes are formed by etching at the same time, the isolation structure 100a is etched at a slower speed, and the active region 101 is etched at a faster speed.
  • the depth H1 that the bottom of the first contact plug 103b of the junction area III extends into the interior of the isolation structure 100a of the junction area III is smaller than that of the remaining contact plugs 103a (that is, the contact plugs in the core area I).
  • the bottom of 103a) extends into the corresponding active region 101 to a depth H2.
  • a corresponding isolation structure 100b is also formed between the active regions 101 of adjacent core elements in the core region I, so as to define the active regions 101 of each core element; in the peripheral region II An isolation structure 100b and a corresponding contact plug 103c are also formed, and the isolation structure 100b is used to define the active area 101 of each peripheral element.
  • the semiconductor device is a dynamic random access memory (DRAM)
  • the core area is the storage array area of the DRAM memory
  • the core element is a storage transistor.
  • the electrical contact structure is a storage node contact part, and a capacitor (that is, a storage node) is connected to it. That is, each contact plug 103a in the core area I is connected to a capacitor (as shown in 705a in Figure 12), and the first contact plug closest to the peripheral area II among all the contact plugs in the core area I and the boundary area III A capacitor is connected to the plug 103b (as shown in 705b in FIG.
  • the capacitor in the junction area III has a first width W1
  • the capacitor in the core area I has a second width W2.
  • the first A width W1 is greater than the second width W2.
  • the size of the capacitor in the boundary area III is increased, which can buffer the core area I and the peripheral area II.
  • the difference in the density of the circuit patterns between the circuit patterns can improve the optical proximity effect, reduce the sparse/dense load effect, and ensure the consistency of the capacitors above the contact plugs 103a in the core area I when the photolithography process and/or etching process are performed.
  • the electrical structure connected to it can be used as a virtual structure, and the smaller the area, the better.
  • the contact plug is at least partially located on the isolation structure of the junction area, so the area of the electrical structure connected to it can be reduced to a small size, which reduces the area occupied by the core area and is beneficial to increase the effective area of the core area. Utilization rate, in turn, helps to increase device density.
  • the semiconductor device includes a plurality of word lines WL and a plurality of bit lines BL, each of the word lines WL intersects the plurality of active areas AA1 in the core area I, so
  • the word line WL may be a buried word line
  • the bit line BL is formed above the core element of the core region I and is perpendicular to the word line WL.
  • the isolation structure 100a of the junction region III and the core region I are immediately above the active region 101 of the isolation structure 100a of the junction region III, and a part of the bottom of the first contact plug 103b is connected to the boundary region.
  • the isolation structure 100a of III contacts and overlaps, the other part of the bottom of the first contact plug 103b contacts and overlaps with the active region 101 of the isolation structure 100a in the core region I next to the junction region III, and so
  • the first contact plug 103b only has a side facing the core region I in contact with the nearest word line WL embedded in the substrate 100.
  • the first contact plug 103b closest to the peripheral area II among all the contact plugs in the core area I and the boundary area III adopts the structure shown in FIG. 1C, that is, the first contact plug 103b is formed in the Above the isolation structure 100a of the junction area III, and its top is at least connected with the top of a contact plug 103a in the core area I immediately above the active area 101 of the isolation structure 100a of the junction area III, so All the contact plugs connected together at the top form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, and the inverted U-shaped electrical contact structure or comb-shaped electrical contact structure can be the most boundary of the core area I (ie the core area I).
  • the word line WL that is, the word line closest to the boundary area in the core region I) on the outermost
  • the bit line BL that is, parallel
  • an inverted U-shaped electrical contact structure or comb is formed
  • the side of the electrical contact structure closest to the core area I is in
  • the semiconductor device is a DRAM as an example, the technical solution of the present invention is not limited to this.
  • the semiconductor device can also be any suitable electrical device, such as a memory of other architectures.
  • the capacitor can be replaced with a corresponding electrical structure, such as a resistor.
  • FIG. 1C. 2A to 2D are schematic cross-sectional views of the device in a manufacturing method of the electrical contact structure of the semiconductor device shown in FIG. 1C. 2A to 2D, this embodiment provides a method for manufacturing an electrical contact structure of a semiconductor device, including the following steps:
  • a semiconductor substrate 100 which includes a core area I, a peripheral area II, and a boundary area III between the core area I and the peripheral area II.
  • the semiconductor substrate 100 may be selected from silicon substrates, insulators Silicon-on-substrate (SOI), germanium substrate, germanium-on-insulator (GOI), silicon germanium substrate, etc.
  • a plurality of shallow trench isolation structures 100a, 100b are formed in the semiconductor substrate 100.
  • the shallow trench isolation structures 100a, 100b form trenches by etching the semiconductor substrate 100, and then fill the trenches with insulating materials.
  • the material of the shallow trench isolation structure 100a, 100b may include silicon oxide, silicon nitride, or silicon oxynitride.
  • the shallow trench isolation structure 101a located in the junction area III defines the boundary between the core area I and the peripheral area II on the two-dimensional plane, and the shallow trench isolation structure 100a located in the core area I defines the core on the two-dimensional plane.
  • the active area 101 corresponding to each core element in the area I, and the shallow trench isolation structure (not shown) in the peripheral area II defines the corresponding to each peripheral element in the peripheral area II on a two-dimensional plane. Active area 101.
  • the semiconductor substrate 100 is covered with an interlayer dielectric layer 102, and the interlayer dielectric layer 102 can be configured to have a single-layer structure or a multi-layer structure.
  • the interlayer dielectric layer 102 may include at least one of silicon nitride, silicon oxynitride, and low-k dielectric materials.
  • the dielectric constant k of the low-k dielectric material is smaller than that of silicon oxide, and it can be used as an intermetal dielectric layer (IMD), such as high-density plasma (HDP) oxide, orthosilicate four Ethyl vinegar (TEOS), plasma enhanced TEOS (PE-TEOS), undoped silicate glass (USG), phosphorous silicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), spin-on glass (SOG), etc.
  • IMD intermetal dielectric layer
  • HDP high-density plasma
  • TEOS orthosilicate four Ethyl vinegar
  • PE-TEOS plasma enhanced TEOS
  • USG phosphorous silicate glass
  • BSG borosilicate glass
  • BPSG borophosphosilicate glass
  • FSG fluorinated silicate glass
  • SOG spin-on glass
  • an etch stop layer (not shown) may be formed between the semiconductor substrate 100 and the interlayer dielectric layer 102, and the etch stop layer may include SiN, SiON, SiC, SiCN, BN (nitride barrier) or any combination thereof.
  • the etch stop layer and the interlayer dielectric layer 102 may be formed using plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), atmospheric pressure CVD (APCVD) and/or spin coating process.
  • PECVD plasma enhanced CVD
  • HDP-CVD high density plasma CVD
  • APCVD atmospheric pressure CVD
  • a first mask pattern 104 is formed on the interlayer dielectric layer 102.
  • the first mask pattern 104 defines the position of each contact plug.
  • use The first mask pattern 104 is used as an etching mask to etch the interlayer dielectric layer 102 anisotropically to form contact holes 102a, 102b, and 102c penetrating the interlayer dielectric layer 102 and exposing the corresponding active region 101 below ,
  • the contact holes 102a, 102b, and 102c are independent of each other.
  • Each contact hole 102a is located in the core area I and exposes the active area 101 of the corresponding core element in the core area I.
  • Each contact hole 102b is located in the boundary area III and The isolation structure 100a in the junction area III is exposed, and each contact hole 102c is located in the peripheral area II and exposes the active area 101 of the corresponding peripheral element.
  • an ashing process or a wet cleaning process may be performed to remove the first mask pattern 104 and fill the sacrificial layer 105 in each of the contact holes 102a-102c.
  • the sacrificial layer 105 may be formed by a spin-on hard mask layer (SOH) or an amorphous carbon layer (ACL), which may enable the sacrificial layer 105 to fill the contact holes 102a-102c with a high aspect ratio.
  • a second mask pattern 106 can be formed on the interlayer dielectric layer 102 and the sacrificial layer 105 through a second photolithography process.
  • the contact hole 102b is connected to the trench 102d at the top of at least one contact hole 102a in the core region I next to the boundary region III.
  • the interlayer dielectric layer at the boundary region III is etched to form a contact hole 102b corresponding to the boundary region III with at least one of the core regions I next to the boundary region III.
  • a trench 102d connected to the top of the hole 102a.
  • the trench 102d extends from the boundary region III to the core region I.
  • the trench 102d exposes at least one contact hole 102b of the boundary region III and the outermost of the core region I next to the boundary region III ⁇ contact hole 102a.
  • oxygen, ozone or ultraviolet ashing process or wet cleaning process can be used to remove the sacrificial layer 105 in the contact holes 102a-102c, 102d and the second mask pattern 106 to re-expose each contact hole 102a ⁇ 102c and groove 102d.
  • a barrier metal layer (not shown) may be formed in the contact holes 102a-102c and the trench 102d.
  • the barrier metal layer may cover the inner walls of the contact holes and trenches and the interlayer dielectric with a uniform thickness. The top surface of layer 102.
  • the barrier metal layer can reduce or prevent the metal materials provided in the contact holes and trenches from diffusing into the interlayer dielectric layer 102.
  • the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or any combination thereof, and may use chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) (for example, sputtering) and other processes. Then, each of the contact holes 102a to 102c and the trench 102d is filled with a metal layer to form contact plugs 103a, 103b, and 103c.
  • the metal layer may be formed of refractory metal(s) (for example, cobalt, iron, nickel, tungsten, and/or molybdenum).
  • the metal layer may be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (for example, sputtering).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the deposited metal layer also covers the surface of the interlayer dielectric layer 102 around the contact hole.
  • CMP chemical mechanical polishing
  • the top surface of the dielectric layer 102 forms contact plugs 103a, 103b, and 103c in the interlayer dielectric layer 102.
  • the contact plug 103b is the first contact plug closest to the peripheral area II in the core area I and the boundary area III, and its top is connected to at least one contact plug 103a in the nearest neighboring core area I. Together, an inverted U-shaped contact plug or comb-shaped contact plug is formed.
  • the method shown in FIGS. 2A to 2D can reduce the number of deposition processes under the same number of photolithography, so that all the contact plugs connected together at the top are integrally formed.
  • FIGS. 3A to 3D are schematic cross-sectional views of the device in another manufacturing method of the electrical contact structure of the semiconductor device shown in FIG. 1C.
  • another method for manufacturing an electrical contact structure of a semiconductor device provided by this embodiment includes the following steps:
  • a semiconductor substrate 100 which includes a core area I, a peripheral area II, and a boundary area III between the core area I and the peripheral area II.
  • a plurality of shallow trench isolation structures 100a, 100b are formed in the semiconductor substrate 100.
  • the shallow trench isolation structure 100a defines the boundary between the core region I and the peripheral region II on a two-dimensional plane.
  • the multiple shallow trench isolation structures 100a The active area 101 corresponding to each core element in the core area I is defined.
  • first interlayer dielectric layer 102 on the semiconductor substrate 100.
  • an etching stop layer (not shown) may be formed between the semiconductor substrate 100 and the first interlayer dielectric layer 102; through the first photolithography process, a first mask is formed on the first interlayer dielectric layer 102 The first mask pattern 104 defines the position of each contact plug.
  • the first interlayer dielectric layer 102 is anisotropically etched to form a through hole
  • the first interlayer dielectric layer 102 exposes the contact holes 102a, 102b, and 102c of the corresponding active area 101 below, and each contact hole 102a is located in the core area I and exposes the active area of the corresponding core element of the core area I.
  • the contact holes 102b are located in the junction area III and expose the isolation structure 100a in the junction area III
  • each contact hole 102c is located in the peripheral area II and exposes the active area 101 of the corresponding peripheral element.
  • an ashing process or a wet cleaning process can be performed to remove the first mask pattern 104 and fill with a barrier metal layer (not shown) made of TiN or the like.
  • a metal layer (not shown) made of tungsten and other materials is placed in each contact hole 102a-102c, and a chemical mechanical polishing (CMP) process is further used to chemically mechanically polish the top surface of the deposited metal layer until the first interlayer is exposed.
  • CMP chemical mechanical polishing
  • the top surface of the dielectric layer 102 is formed to form contact plugs 103a, 103b, 103c in the interlayer dielectric layer 102, and the bottom of each of the contact plugs 103a in the core region I and the active region 101 of the corresponding core element Contact, the bottom of the contact plug 103b is in contact with the isolation structure 100a of the junction area III, the bottom of each of the contact plugs 103c in the peripheral area II is in contact with the active area 101 of the corresponding peripheral component, and the bottom of the contact plug 103b is in contact with the isolation structure 100a of the junction area III.
  • the bottom of the first contact plug 103b extends into the interior of the isolation structure 100a of the junction area III with a depth of H1, and the bottom of the contact plug 103a extends into the corresponding active area in the core area I
  • the inside of 101 and the extending depth is H2
  • the bottom of the contact plug 103c extends into the corresponding active area 101 in the peripheral area II and the extending depth is H2, and H1 is smaller than H2.
  • a second interlayer dielectric layer 107 and a second mask pattern 108 can be formed on the first interlayer dielectric layer 102 and the contact plugs 103a, 103b, 103c, and the second mask pattern 108 passes through the first interlayer dielectric layer 102 and the contact plugs 103a, 103b, 103c.
  • the second photolithography process is formed to define an interconnection trench (not shown) for connecting the top of the first contact plug 103b in the junction area III with the top of at least one contact plug 103a in the nearest neighboring core area I Show) and separate grooves located in other contact plugs 103a, 103c.
  • the second interlayer dielectric layer 107 is etched to form trenches 107a, 107b, 107c exposing the tops of the corresponding contact plugs, wherein the corresponding trenches 107a in the junction area III
  • the top of the first contact plug 103b and the top of the nearest neighboring at least one contact plug 103a and the top of the space between the two contact plugs are exposed, and the groove 107b of the core area I exposes the corresponding contact.
  • the top of the plug 103a and the trench 107c in the peripheral area II expose the top of the corresponding contact plug 103c.
  • each contact hole trench 107a-107c is filled with a metal layer to form mutually independent contact pads 109a, 109b, and 109c.
  • Each contact pad 109a is formed on the top of the contact plug 103a of the corresponding core area I, and electrically contacts the top of the corresponding contact plug 103a in a one-to-one correspondence, and the contact pad 109b forms a contact in the interface area III.
  • the top of the plug 103b extends to at least one contact plug 103a in the core area I nearest to the contact plug 103b of the junction area III, and electrically contacts the top of the corresponding contact plug 103a in a one-to-one correspondence , So that all the contact plugs connected at the top in the junction area III form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure.
  • the method shown in Figures 3A to 3D can be produced by dividing each contact plug (including the top-connected contact plug and the independent contact plug) into two equal heights under the same number of photolithography. Therefore, the aspect ratio of the contact hole or trench corresponding to the etching process and the filling process corresponding to each section height can be reduced, and the performance of the formed electrical contact structure can be ensured.
  • the technical solution of the present invention is not limited to the above-mentioned formation method of the electrical contact structure, and the method that can be used to form an independent contact plug and a top-connected contact plug can be applied to the present invention.
  • the technical solution of the invention for example, in another example of the present invention, after the structure of FIG. 2A is formed and the mask pattern 104 is removed, the sacrificial layer is no longer filled, but the material of the contact plug (including the barrier metal layer and the Metal layer) to form independent contact plugs, and then form the second mask pattern 106 in FIG.
  • the interlayer dielectric layer 102 on the interlayer dielectric layer 102 and the independent contact plugs, and further etch the interlayer dielectric layer 102 to form Expose the top sidewall of the first contact plug 103b at the junction area III and at least one trench 102d of the top sidewall of the contact plug 103a in the nearest core area I, and then fill the trench 102d
  • a conductive material is used to form a corresponding contact pad (not shown), which connects the tops of the contact plugs 103b and 103a exposed by the trench 102d together.
  • FIGS. 4 to 13 is a schematic top view of the device structure in the method of manufacturing a semiconductor device according to an embodiment of the present invention
  • FIGS. 5-13 are devices along the line aa' in FIG. 4 in the method of manufacturing a semiconductor device according to an embodiment of the present invention Schematic diagram of structural section.
  • a substrate 300 with multiple core elements ie, memory transistors.
  • the specific process includes:
  • a semiconductor substrate 300a which includes a core area I and a peripheral area II, and a boundary area III between the core area I and the peripheral area II.
  • the core area I is a storage area
  • the core element to be formed on the core area I includes a selection element, and then a data storage element is connected above the core element.
  • the selection element is, for example, a MOS transistor or a diode
  • the data storage element is, for example, a capacitor.
  • Variable resistors, etc., a selection element and the corresponding data storage element form a memory cell.
  • a peripheral circuit TR (for example, NMOS transistor and PMOS transistor, diode, or resistor) may be formed in the peripheral area II to control the memory cell.
  • a plurality of shallow trench isolation structures 301a and 301b are formed in the semiconductor substrate 300.
  • the shallow trench isolation structure 301b defines the boundary between the core region I and the peripheral region II on a two-dimensional plane.
  • the shallow trench isolation structure 301a also The active area AA1 corresponding to each core element in the core area I and the active area AA2 corresponding to the peripheral elements in the peripheral area II are defined.
  • the distribution of the active areas AA1 on the two-dimensional plane is in a stripe shape and all extend along the first direction, and the active areas AA1 may be arranged in a staggered arrangement on the surface of the semiconductor substrate 300a.
  • a buried word line WL is formed in the semiconductor substrate 300a.
  • the buried word line WL is generally buried at a predetermined depth in the semiconductor substrate 300a, extending in the second direction (ie the row direction) and passing through the shallow trench isolation structure. 301a and the active area AA1, the second direction intersects but not perpendicular to the first direction of the active area AA1.
  • the buried word line WL is used as the gate to control the switching of the memory cell. It includes but is not limited to doped semiconductor materials (such as doped silicon), metal materials (such as tungsten, aluminum, titanium, or tantalum), and conductive materials.
  • Metal compounds such as titanium nitride, tantalum nitride, or tungsten nitride), or semiconductor compounds (such as silicon nitride), etc.
  • the sidewalls and bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is buried in the gate cap layer 302. Since the buried word line WL is not the focus of the present invention, the related manufacturing process can refer to the known technical solutions in the art, which will not be described in detail here.
  • the gate dielectric layer may include silicon oxide or other suitable dielectric materials
  • the buried word line WL may include aluminum, tungsten, copper, titanium aluminum alloy, polysilicon or other suitable conductive materials
  • the gate cap layer 302 may Including silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials.
  • the active area AA1 on both sides of the buried word line WL can be doped with a second type of dopants, such as P-type or N-type dopants, to form source and drain regions (defined as S/ D1).
  • a second type of dopants such as P-type or N-type dopants
  • One of the AA1 on both sides of the buried word line WL is located at the center of AA1 corresponding to the predetermined bit line contact structure, and the other is located at the end of the active area AA1 corresponding to the predetermined storage node contact structure.
  • the word lines WL and S/D1 may constitute or define a plurality of MOS memory transistors formed on the core region I of the semiconductor device.
  • the source and drain regions corresponding to the peripheral transistors can also be formed in the peripheral area II at the same time.
  • an etch stop layer 303 can be further formed on the semiconductor substrate 300a.
  • the etch stop layer 303 covers the S/D1 and S/D2.
  • silicon nitride (SiN) and/or silicon oxide (SiO 2 ) are included.
  • bit line contact plugs (not shown) and a bit line BL located above the bit line contact plugs are formed on the S/D1 serving as the drain region of the core region I.
  • the bit line The contact plug can be formed by the following method: firstly etch the S/D1 in one active area AA1 and located between two adjacent WLs to form a groove, and then form a metal silicide in the groove.
  • the bit lines BL are parallel to each other and extend along the third direction (ie, the column direction) perpendicular to the buried word line WL, and cross the active area AA1 and the buried word line WL at the same time.
  • Each bit line BL includes, for example, a semiconductor layer (such as polysilicon, not shown), a barrier layer (such as Ti or TiN, not shown), and a metal layer (such as tungsten, aluminum, or copper, etc.) stacked in sequence. Not shown) and a mask layer (for example, containing silicon oxide, silicon nitride or silicon carbonitride, not shown).
  • At least one gate structure G1 is formed, which includes, for example, a gate dielectric layer (not shown) and a gate layer (not shown) stacked in sequence.
  • the gate layer of the gate structure G1 is formed together with the semiconductor layer or the metal layer of the bit line BL.
  • different processes or the same process can be used to form the sidewall spacers 304 respectively surrounding each bit line BL and the gate structure G1.
  • the manufacturing process of the sidewall spacer of the gate structure G1 may be performed first, so that the sidewall 304 of the gate structure G1 includes silicon oxide or silicon oxynitride (SiON), and then the manufacturing process of the sidewall spacer of the bit line BL is performed.
  • the sidewall spacer of the bit line BL may include silicon nitride.
  • an etching back manufacturing process may be performed again, so that the overall height of the gate structure G1 is lower than the bit line BL.
  • the storage node contact structure can be formed on the basis of the electrical contact structure of the semiconductor device shown in FIGS. 1A to 1C of the present invention, and the method for manufacturing the electrical contact structure of the semiconductor device shown in FIGS. 2A to 2D is used below.
  • the specific process is as follows:
  • an interlayer dielectric layer 400 is formed on the semiconductor substrate 300, the material of which includes, for example, Silicon oxide, silicon nitride or low-K dielectric, etc.
  • the interlayer dielectric layer 400 is completely covered on the semiconductor substrate 300 through a deposition process, and the interlayer dielectric layer 400 is made to fill the space between the bit lines BL and connect the bit lines BL to the gate structure G1 and its The sidewall spacers 304 are buried in, and then the interlayer dielectric layer 400 is planarized by a process such as chemical mechanical polishing to form the interlayer dielectric layer 400 having a flat top surface as a whole.
  • the top surface of the planarized interlayer dielectric layer 400 is at least not lower than the top surface of each bit line BL.
  • a first mask pattern (not shown) is formed on the interlayer dielectric layer 400 through a photolithography process.
  • the first mask pattern defines the position of each storage node contact structure, and then uses The first mask pattern is used as an etching mask to anisotropically etch the interlayer dielectric layer 400 to form contact holes 401a and 401a penetrating the interlayer dielectric layer 400 and exposing the corresponding S/D1 used as the source region below.
  • each contact hole 401a is located in the core region I and exposes the source region of the corresponding core element in the core region I
  • the contact hole 401b is located in the junction area III and exposes the isolation structure in the junction area III
  • the top surface of 301a extends into the isolation structure 301a to a certain depth (H1 in Figure 1B, H1 is smaller than H2)
  • each contact hole 401d, 401e is located in the peripheral area II and exposes the source/drain of the corresponding peripheral element Region S/D2 or gate structure G1.
  • the sacrificial layer 402 may be formed of a spin-on hard mask layer (SOH) or an amorphous carbon layer (ACL), which may enable the sacrificial layer 402 to fill the contact holes 401a, 401b, and 401d with high aspect ratios, 401e.
  • SOH spin-on hard mask layer
  • ACL amorphous carbon layer
  • a second mask pattern (not shown) may be formed on the interlayer dielectric layer 400 and the sacrificial layer 402, and the second mask pattern defines a contact hole 401b corresponding to the boundary region III.
  • a trench 401c that communicates with the top of at least one contact hole 401a in the core region I nearest to it.
  • etch the interlayer dielectric layer 400 in the boundary region III to form at least one of the top of the first contact hole 401b corresponding to the boundary region III and the core region I nearest to it
  • the top of the contact hole 401a is connected to the trench 401c.
  • the trench 401c may be parallel to the bit line BL.
  • the sacrificial layer 402 and the second mask pattern in the contact holes 401a, 401b, 401d, and 401e can be removed using an ashing process of oxygen, ozone, or ultraviolet rays or a wet cleaning process to re-
  • the respective contact holes 401a, 401b, 401d, 401e and the trench 401c are exposed.
  • a barrier metal layer (not shown) may be formed in the contact holes 401a, 401b, 401d, 401e and the trench 401c.
  • the barrier metal layer may cover the contact holes 401a, 401b, and 401a with a uniform thickness.
  • the barrier metal layer can reduce or prevent the metal material provided in the contact holes 401a, 401b, 401d, 401e and the trench 401c from diffusing into the interlayer dielectric layer 400.
  • the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, Ti N, TiSiN, W, WN, or any combination thereof, and may use chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition. It is formed by processes such as deposition (PVD) (for example, sputtering). Then, a metal layer is filled in the respective contact holes 401a, 401b, 401d, 401e and the trench 401c to form contact plugs 501a, 501d, 501e and a combined contact structure 501b.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the metal layer may be formed of refractory metal(s) (for example, cobalt, iron, nickel, tungsten, and/or molybdenum).
  • the metal layer may be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (for example, sputtering).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the formed metal layer also covers the surface of the interlayer dielectric layer 400 around the contact hole and the trench. After that, the top surface of the deposited metal layer can be chemically and mechanically polished by a chemical mechanical polishing (CMP) process until the top surface of the deposited metal layer is exposed.
  • CMP chemical mechanical polishing
  • the top surface of the interlayer dielectric layer 400 is formed to form contact plugs 501a, 501d, 501e and a combined contact structure 501b in the interlayer dielectric layer 400.
  • the contact plug 501a serves as a storage node contact structure in the core area I, and is used to connect to a capacitor formed above the core area I later.
  • the combined contact structure 501b is connected by the top of the first contact plug in the junction area III and its nearest neighboring at least one contact plug 501a (that is, the core area I is closest to the at least one contact plug 501a in the junction area III).
  • the combined contact structure 501b may be aligned with the bit line BL parallel.
  • the combined contact structure 501b is, for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, and the side closest to the core area I can also be connected to one of the word lines WL in the outermost active area AA1 of the core area I. contact.
  • the contact plug 501d is used as the contact structure of the gate structure G1 of the peripheral region II to lead the gate structure G1 outward
  • the contact plug 501e is used as the contact structure of the source region or the drain region S/D2 of the peripheral region II. To lead the source region or drain region S/D2 of the peripheral region II to the outside.
  • an underlying support layer 600 and a second layer can be sequentially formed on the surface of the interlayer dielectric layer 400, the contact plugs 501a, 501d, 501e, and the combined contact structure 501b by chemical vapor deposition, spin coating, etc.
  • the bottom support layer 600 is used to support the bottom electrode layer subsequently formed on the one hand, and also to isolate the semiconductor liner on the other hand.
  • the formation process of the bottom support layer 600 may also be a thermal oxidation process.
  • the material of the bottom support layer 600, the middle support layer 601 and the top support layer 602 includes but is not limited to silicon nitride, and the material of the first sacrificial layer 611 and the second sacrificial layer 612 includes but is not limited to silicon oxide.
  • the thickness of the first sacrificial layer 611 defines the height of the intermediate support layer 601 to be formed later. Therefore, the thickness of the first sacrificial layer 611 can be adjusted according to the height position of the intermediate support layer 601 to be formed. In the case where the thickness of the first sacrificial layer 611 and the intermediate support layer 601 is determined, the thickness of the second sacrificial layer 612 defines the height of the top support layer 602 to be formed subsequently.
  • the second sacrificial layer The thickness of 612 can be adjusted according to the height position of the top support layer 602 to be formed.
  • two or more intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602, and between adjacent intermediate support layers There is a sacrificial layer for isolation.
  • a plurality of capacitor holes 700a and 700b are formed in the sacrificial layer on the core region I and the support layer.
  • Each capacitor hole 700a is formed in the core region I and exposes the The surface of the corresponding contact plug 501a in the core area I is used to form a capacitor in the core area 1.
  • the capacitive hole 700b is formed on the boundary of the core region I and the boundary region III and exposes the surface of the combined contact structure 501b that spans from the boundary region III to the boundary of the core region I, and is used to form a boundary across the boundary of the core region I and the boundary region III. On the capacitor.
  • the capacitor holes 700a and 700b are arranged in an array, and the capacitor hole 700b has a first width W1, and the capacitor hole 700a has a second width W2.
  • a mask layer (not shown) is formed on the top support layer 602, the mask layer is patterned to expose the areas where the capacitor holes 700a and 700b are scheduled to be formed, and then a patterned mask is used.
  • the mold layer is a mask, and the top support layer 602, the second sacrificial layer 612, the middle support layer 601, the first sacrificial layer 611, and the bottom support layer 600 are etched in sequence to remove the peripheral area II and the core area
  • the supporting layer and the sacrificial layer are formed on the edge area of I, and a plurality of capacitor holes 700a and 700b are formed in the core area I and the boundary area III, and then the patterned mask layer is removed.
  • the capacitor holes 700a and 700b sequentially penetrate the top support layer 602, the second sacrificial layer 612, the middle support layer 601, the first sacrificial layer 611, and the bottom support layer 600 to expose the corresponding contacts of the core region I
  • the combination of the plug 501a and the junction area III contacts the surface of the structure 501b.
  • all the capacitor holes are arranged in a hexagonal close-packed arrangement.
  • the capacitor hole may be an inverted trapezoidal hole, a rectangular hole, etc., and the sidewalls thereof may have irregular shapes, such as curved sidewalls, etc., which are not specifically limited herein.
  • the bottom support layer 600 is also reserved on the peripheral region II to protect the device surface of the peripheral region II during the subsequent capacitor formation process.
  • the combined contact structure 501b due to the larger area of the combined contact structure 501b, it can provide sufficient process margin for the production of the capacitor hole 700b located on the boundary of the core area I and the boundary area III, and make the width of the capacitor hole 700b relatively large. Large, avoid abnormal deformation or collapse of the capacitor hole 700b, and at the same time make the capacitor formed in the capacitor hole 700b and the combined contact structure 501b have a larger contact area, thereby reducing the contact impedance, and improving the electrical performance of the device .
  • the width of the capacitor hole 700b in the junction area III is relatively large, the difference in the density of the circuit patterns in the peripheral area II and the core area I can be buffered, so that the optical lithography process and/or etching process of the capacitor hole can be improved.
  • the proximity effect reduces the sparse/dense load effect, ensures the consistency of the capacitor holes in the core area, and prevents the capacitor holes above the contact plugs in some locations in the core area from being abnormal and causing subsequent capacitor failure problems.
  • a bottom electrode layer 701 is formed to cover the sidewalls and bottom walls of the capacitor holes 700a and 700b.
  • the part of the bottom electrode layer 701 located in the capacitor holes 700a, 700b has a shape consistent with the topography of the capacitor holes 700a, 700b, so that the bottom electrode located in the capacitor holes 700a, 700b
  • the layer 701 constitutes a cylindrical structure.
  • the lower electrode layer 701 can be formed on the basis of a deposition process combined with a planarization process. For example, first, a patterned protective layer (not shown) such as photoresist can be used to protect the peripheral region II and expose it.
  • the top surface of the top support layer 602 in the core area I and the surfaces of the capacitor holes 700a, 700b are removed; then, a physical vapor deposition or chemical vapor deposition process is used to form an electrode material layer on the patterned protective layer and the core area I On the exposed surface of the, the electrode material layer covers the bottom and sidewalls of the capacitor holes 700a and 700b, and the top surface of the top support layer 602 covering the core area I and the top surface of the patterned protective layer of the peripheral area II; Perform a planarization process (for example, a chemical mechanical polishing process CMP) to remove the part of the electrode material layer above the top support layer 602, so that the remaining electrode material layer is only formed in the capacitor holes 700a, 700b to A lower electrode layer 701 having a plurality of cylindrical structures is formed, and then the patterned protective layer is removed.
  • a planarization process for example, a chemical mechanical polishing process CMP
  • the contact plugs 501a, 501b are exposed through the capacitor holes 700a, 700b, respectively, so that the bottom of the cylindrical structure of the lower electrode layer 701 formed can contact the contact plugs. 501a and 501b are in electrical contact.
  • the lower electrode layer 701 may be a polysilicon electrode or a metal electrode.
  • a metal electrode a stacked structure of titanium nitride (TiN) and Ti can also be used.
  • the lower electrode layer 701 is a polysilicon electrode, it may be formed of a zero-doped and/or doped polysilicon material.
  • each of the sacrificial layers is removed and each of the supporting layers is retained. All the supporting layers form a lateral supporting layer to connect the multiple cylindrical structures of the lower electrode layer 701 laterally.
  • the outer wall of each cylindrical structure supports the lower electrode layer 701 on the side wall of each cylindrical structure.
  • the top support layer 602 is located at the outer periphery of the top of the plurality of cylindrical structures of the lower electrode layer 701
  • the middle support layer 601 is located at the middle part of the plurality of cylindrical structures of the lower electrode layer 701
  • the support layer 600 is located at the periphery of the bottom of the plurality of cylindrical structures of the lower electrode layer 701.
  • the specific process includes: forming a first opening (not shown) in the top support layer 602 and exposing the second sacrificial layer 612; the second sacrificial layer 612 can be etched and removed by a wet etching process Forming a second opening in the intermediate support layer 601 to expose the first sacrificial layer 611; using a wet etching process to etch and remove the first sacrificial layer 611; wherein, only one of the first openings It overlaps with one of the capacitor holes 700a or 700b, or one of the first openings overlaps with a plurality of the capacitor holes 700a and/or 700b at the same time; and one of the second openings overlaps with only one of the capacitor holes 700a or 700b.
  • 700b overlaps, or one of the second openings overlaps a plurality of the capacitor holes 700a and/or 700b at the same time.
  • the second opening may be completely aligned with the first opening.
  • the capacitor dielectric layer 702 may be a high-K dielectric layer such as metal oxide.
  • the capacitor dielectric layer 702 has a multilayer structure, for example, a two-layer structure of hafnium oxide-zirconia.
  • the upper electrode layer 703 may be a single-layer structure or a multi-layer structure.
  • the upper electrode layer 703 is a single-layer structure, for example, a polysilicon electrode or a metal electrode
  • when the upper electrode layer 703 is a metal electrode In this case, for example, titanium nitride (TiN) can be used.
  • TiN titanium nitride
  • the upper electrode layer 703 can form a capacitor with the capacitive dielectric layer 702 and the lower electrode layer 701 corresponding to the inside of the cylindrical structure and the outside of the cylindrical structure.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 all have uneven sidewall structures corresponding to the middle support layer 601 and the top support layer 602 outside the cylindrical structure of the lower electrode layer 701, As a result, the part of the upper electrode layer 703 on the edge area of the core area I (that is, the boundary area of the capacitor hole array) corresponds to the middle support layer 601 and the top support layer 602 to be far away from the lower electrode layer 701 Protruding in the direction of, making the boundary of the capacitor array in the core area I uneven.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 also extend sequentially to cover the surface of the bottom support layer 600 remaining on the peripheral region II.
  • a chemical vapor deposition process may be used to form an upper electrode filling layer 704 on the surface of the upper electrode layer 703, and the upper electrode filling layer 704 fills the gap between the upper electrode layers 703.
  • the upper electrode filling layer 704 fills up the gap between the adjacent cylindrical structures and covers the structure formed above.
  • the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon.
  • the width of the capacitor hole 700b is greater than the width of the capacitor hole 700a
  • the size of the capacitor hole 700b is large, it is favorable for material filling, thereby improving the performance of the capacitor 705b.
  • the size of the capacitor 705b connected to the contact structure 501b is increased by combining the contact structure 501b, which can buffer the density difference of the circuit pattern between the core region and the peripheral region, thereby forming the core region
  • the photolithography process and/or etching process of all capacitors can improve the optical proximity effect, reduce the sparse/dense load effect, ensure the consistency of the capacitor above the contact plug in the core area, and improve the performance of the device.
  • the capacitor 705b and the combined contact structure 501b have a larger contact area, thereby reducing the contact resistance and improving the electrical performance of the device.
  • the first contact plug 501b formed in the junction area III is completely overlapped with the isolation structure 300a in the junction area III, please refer to FIG. 1A and FIG.
  • the capacitor 705b which originally extends laterally from the junction area III to the outermost side of the core area I, is completely formed above the isolation structure 300a of the junction area III as a virtual structure, and the virtual structure is used to ensure that the contact plug 501a of the core area I is connected to The electrical structure 705a is consistent; when a part of the bottom of the first contact plug 501b formed in the junction area III overlaps with the isolation structure 300a of the junction area III, the other part of the bottom overlaps with the core area I of the isolation structure 300a next to the junction area III
  • the active region 301 overlaps please refer to Figure 1B and Figure 13
  • the cross-sectional area of the top of the first contact plug 501b formed in the junction area III is relatively increased, which is also for the subsequent formation of a capacitor above the
  • An embodiment of the present invention provides a mask assembly for making contact plugs.
  • the mask assembly includes: a first mask 10, a second mask 20, and a third mask.
  • Mask plate 30 is
  • the first mask 10 has a plurality of parallel first light-shielding stripes, and a first light-transmitting area 112 is formed between two adjacent first light-shielding stripes.
  • the first first light-shielding stripe 111a at the boundary of the first mask 10 (that is, the boundary along the arrangement direction of the first light-shielding stripe) has a first width K1
  • the second first light-shielding stripe 111a The width of the stripe 111b is smaller than K1
  • the remaining first light-shielding stripe 111c has a second width K2
  • the first width K1 is greater than the second width K2, for example, K1>1.5*K2
  • the width of is greater than K2, so in the photolithography and etching process of transferring the pattern on the first mask 10 to the corresponding film layer, the first first light-shielding stripe 111a in the first mask 10 can be used The width
  • the width of the second first light-shielding stripe 111b may be equal to the width of the first first light-shielding stripe 111a.
  • the width of the first light-transmitting region 112 between the first first light-shielding stripe 111a and the second first light-shielding stripe 111b is larger than the width of the remaining first light-transmitting regions 112, thereby facilitating Sufficient process margin is provided for the production of contact plugs at the boundary of the core region of the semiconductor device.
  • the second mask 20 has a plurality of second light-shielding stripes 201 that are parallel and perpendicularly intersect each of the first stripes 111a, 111b, 111c, and there is a space between two adjacent second light-shielding stripes 201 The second light-transmitting area 202.
  • At least one second light-shielding stripe (not shown) has a third width (not shown), and the remaining second light-shielding stripe has a fourth width (not shown), and the third width is greater than the The fourth width, for example, the third width is greater than 1.5 times the fourth width, so that in the photolithography and etching process of transferring the pattern on the second mask 20 to the corresponding film layer, the first The width gradient of the second light-shielding stripes in the second mask 20 can improve the pattern density/sparse effect between the core area and the peripheral area of the semiconductor device, and improve the pattern transfer effect of the second mask 20.
  • the first second light-shielding stripes and the second second light-shielding stripes optionally, at the boundary of the second mask 20 (that is, at the boundary along the arrangement direction of the second light-shielding stripes), the first second light-shielding stripes and the second second light-shielding stripes.
  • the width of the second light-transmitting region 202 between the stripes is greater than the width of the remaining second light-transmitting regions 202, which is beneficial to provide sufficient process margin for the production of contact plugs at the boundary of the core region of the semiconductor device.
  • the third mask 30 has a light-shielding block 311 and a third light-transmitting area 312 complementary to the light-shielding block 311.
  • the light-shielding block 311 may have a serrated edge facing the core area, so as to mask a part of the area at the boundary of the core area where the contact hole is to be formed.
  • FIGS. 14 to 16 only show the patterns of one corner area of the first mask 10, the second mask 20, and the third mask 30, respectively. Those skilled in the art should be able to refer to FIGS. 14 to 16 The area shown in 16 is extended accordingly to obtain a substantially rectangular complete mask.
  • the light-shielding block 311 is a closed ring structure or a non-closed ring-shaped structure with at least one opening on the complete third mask plate 30, and the light-shielding block 311 faces the zigzag shape at the center of the third mask plate 30.
  • edges are asymmetrical, that is, the light-shielding blocks 311 on the upper and lower sides of the third mask plate 30 are asymmetrical, and the light-shielding blocks 311 on the left and right sides of the third mask plate 30 are asymmetric.
  • the light-shielding block 311 covers all At least one first light-shielding stripe at the boundary of the first mask 10 and a portion of the first light-transmitting area nearest to the first light-shielding stripe, and at least two light-shielding regions covering the boundary of the second mask 20
  • the overlapping area of the third light-transmitting area 312, the first light-transmitting area 112, the second light-transmitting area 202 and the core area I is the area CT where the contact plug is formed.
  • the shape of the formed contact plug region CT includes at least one of a square, a circle, an ellipse, a triangle, a rectangle, a polygon, and a heart shape.
  • the number of second light-shielding stripes 201 covered by the light-shielding block 311 is 2 to 5 times the number of first light-shielding stripes covered by the light-shielding block 311 .
  • An embodiment of the present invention also provides a method for manufacturing a contact plug.
  • the method for manufacturing a contact plug is implemented by using the mask plate combination of the present invention. , Specifically including the following steps:
  • a semiconductor substrate 410 with multiple active regions AA1 is provided.
  • An interlayer dielectric layer 500 and a first mask layer P1 are sequentially formed on the semiconductor substrate 410, wherein the semiconductor
  • the substrate 410 also has a core area I, a peripheral area II, and a junction area III between the core area I and the peripheral area II.
  • the core area I is formed with a shallow trench isolation structure 411b defining each active area AA1, and the junction area
  • a shallow trench isolation structure 411a defining the core region I and the peripheral region II is formed in III, and the material of the first mask layer P1 may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the pattern on the first mask plate in the mask plate assembly is transferred to the first mask layer P1 by using a photolithography and etching process. That is, the first mask layer P1 is patterned by using the first mask plate 10. Specifically, firstly, a bottom anti-reflective layer (not shown) and a photoresist layer (not shown) are sequentially covered on the first mask layer P1, and the first mask 10 is used to treat the photoresist layer Exposure and development are performed to transfer the pattern on the first mask 10 to the first mask layer P1, and then the bottom anti-reflection layer and the photoresist layer can be removed.
  • a plurality of first lines are formed in the patterned first mask layer P1, where each first line corresponds to a corresponding first light-shielding stripe on the first mask plate 10, and the first line between adjacent first lines
  • the trench corresponds to the corresponding first light-transmitting area 112 on the first mask 10 and exposes the corresponding interlayer dielectric layer 500.
  • the outermost first line P11 at the boundary of the core area I corresponds to the first line P11 at the boundary of the first mask 10
  • the second first line P12 corresponds to the second first shading stripe 111b at the boundary of the first mask 10
  • the remaining first lines P10 correspond to the remaining first shading inside the first mask 10 Stripe 111c.
  • a second mask layer P2 is covered on the first mask layer P1 and the interlayer dielectric layer 500, and a photolithography combined etching process is used to remove the mask
  • the pattern on the second mask plate 20 in the combination is transferred to the second mask layer P2 to form a corresponding plurality of second lines P20, that is, the second mask layer P2 is patterned by the second mask plate 20.
  • the specific process is basically the same as the process of patterning the first mask layer P1 by using the first mask plate, and will not be described in detail here.
  • each second line P20 corresponds to the corresponding second light-shielding stripe 201 on the second mask plate 20, and the grooves (not labeled) between the adjacent second lines P20 correspond to the corresponding second transparent stripes on the second mask plate 20.
  • each second line P20 perpendicularly intersects all the first lines P11, P12, P10 and covers one of these first lines P11, P12, P10 and the adjacent first lines in the line width area.
  • Corresponding parts of the grooves between the adjacent second lines P20, and the grooves between adjacent second lines P20 expose the corresponding first lines P11, P12, P10 in the groove width area and the grooves between adjacent first lines In the interlayer dielectric layer 500.
  • the material of the second mask layer P2 is different from the material of the first mask layer P1, so that the above-mentioned etching process can retain the first line between adjacent second lines.
  • a third mask layer P3 is covered on the second mask layer P2, the first mask layer P1, and the interlayer dielectric layer 500, wherein the third mask layer P3
  • the material of is different from the material of the second mask layer P2 and the material of the first mask layer P1, so that subsequent patterning of the third mask layer P3 can retain the exposed first and second lines, optional Ground, the material of the third mask layer P3 is photoresist; the pattern on the third mask plate 30 in the mask plate assembly is transferred to the third mask layer P3 by using a photolithography process, that is, the third mask layer P3 is used.
  • the three mask plate 30 patterns the third mask layer P3, the remaining third mask layer P3 (that is, the patterned third mask layer P3) corresponds to the light-shielding block 311 of the third mask plate 30, and the remaining third mask layer P3
  • the trench CTa area ie, the exposed interlayer dielectric layer 500 area
  • the remaining third mask layer P3 covers all the trenches defined by the intersection of the first line and the second line on the boundary area III, and covers the outermost first line and second line at the boundary in each direction of the core area I Part of the groove defined by the intersection is covered.
  • the word line WL may overlap the second line P20, and the first lines P10 to P12 may overlap the bit line BL accordingly. Therefore, the first mask 10 may be a bit line mask, and the second mask 20 may be a word line mask.
  • a contact plug CT is formed in each of the contact holes, and the bottom of each contact plug CT is in contact with the corresponding active area AA1. It can be seen from FIG. 19 that there are no contact plugs above part of the active area AA1 at the boundary along the length of the first line or the second line of the core area I, as shown by dCT in FIG. 19.
  • the contact plugs CT at the borders on opposite sides of the core area I are distributed asymmetrically, for example, the contact plugs at the upper and lower borders of the core area I are distributed asymmetrically, and/or , The contact plugs at the left boundary and the right boundary of the core area I are distributed asymmetrically.
  • the contact plug manufacturing method of the present invention by adjusting the shape and size of the light-shielding block of the third mask, the first line and the second line covered by the patterned third mask layer can be adjusted to intersect to define
  • the location of the trenches can achieve the requirement that there are no contact plugs above the active area at some special positions at the boundary of the core area. Therefore, in the actual production process, the problematic areas at the boundary of the core area can be collected based on historical production data, so that no contact plugs are formed in these areas, so that the original contact plug positions in these areas are connected.
  • the electrical structure (such as capacitors or resistors, etc.) becomes a virtual structure, which does not participate in the test in the subsequent yield test and other tests, which can increase the test pass rate and ultimately achieve the goal of improving the product pass rate.
  • the manufacturing method of the semiconductor device of the present invention specifically includes the following processes:
  • a semiconductor substrate 410 with multiple core elements is provided.
  • the specific process includes: First, a semiconductor substrate 410a is provided, which includes the core region I and the peripheral region II and the boundary Zone III.
  • the core area I is a storage area
  • the core element to be formed on the core area I includes a selection element, and then a data storage element is connected above the core element.
  • the selection element is, for example, a MOS transistor or a diode
  • the data storage element is, for example, a capacitor.
  • Variable resistors, etc., a selection element and the corresponding data storage element form a memory cell.
  • Peripheral circuits may be formed in the peripheral area II to control the memory cells.
  • a plurality of shallow trench isolation structures 411b are formed in the semiconductor substrate 410a of the core region I, shallow trench isolation structures 411a are formed in the semiconductor substrate 410a of the junction region III, and the shallow trench isolation structures 411a define a two-dimensional plane At the boundary between the core area I and the peripheral area II, the shallow trench isolation structure 411b defines the active area AA1 corresponding to each core element in the core area I.
  • the distribution of the active area AA1 on the two-dimensional plane is strip-shaped and all extend along the first direction, and the active area AA1 may be arranged in a staggered arrangement on the surface of the semiconductor substrate 410a.
  • a buried word line WL is formed in the semiconductor substrate 410a.
  • the buried word line WL is generally buried at a predetermined depth in the semiconductor substrate 410a, extending in the second direction (ie, the row direction) and passing through the shallow trench isolation structure. 411b and the active area AA1, the second direction intersects but not perpendicular to the first direction of the active area AA1.
  • the buried word line WL is used as a gate to control the switching of the memory cell.
  • the sidewall and bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is covered by the gate.
  • the cap layer 412 is buried inside. Since the buried word line WL is not the focus of the present invention, the related manufacturing process can refer to the known technical solutions in the art, which will not be described in detail here.
  • the gate dielectric layer may include silicon oxide or other suitable dielectric materials
  • the buried word line WL may include aluminum, tungsten, copper, titanium aluminum alloy, polysilicon or other suitable conductive materials
  • the gate cap layer 412 may Including silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials.
  • the active area AA1 on both sides of the buried word line WL can be doped with a second type of dopants, such as P-type or N-type dopants, to form source and drain regions (defined as S/ D)
  • a second type of dopants such as P-type or N-type dopants
  • One of the AA1 on both sides of the buried word line WL is located at the center of AA1 corresponding to the predetermined bit line contact structure, and the other is located at the predetermined storage node contact structure at the end of the active area AA1.
  • the word lines WL and S/D may constitute or define a plurality of MOS memory transistors formed on the core region I of the semiconductor device.
  • the source region and the drain region (not shown) corresponding to the peripheral transistor can also be formed in the peripheral region II at the same time.
  • an etch stop layer 413 may be further formed on the semiconductor substrate 410a, and the etch stop layer 413 covers the S/D and shallow trench isolation structures 411a, 411b.
  • the material includes, for example, silicon nitride (SiN) and/or silicon oxide (SiO 2 ).
  • a plurality of bit line contact plugs (not shown) and a bit line BL located above the bit line contact plugs are formed on the S/D serving as the drain region of the core region I.
  • the bit line The contact plug may be formed by first etching the S/D between two adjacent WLs formed in one active area AA1 to form a groove, and then forming a metal silicide in the groove.
  • the bit lines BL are parallel to each other and extend along the third direction (ie, the column direction) perpendicular to the buried word line WL, and cross the active area AA1 and the buried word line WL at the same time.
  • Each bit line BL includes, for example, a semiconductor layer (such as polysilicon, not shown), a barrier layer (such as Ti or TiN, not shown), and a metal layer (such as tungsten, aluminum, or copper, etc.) stacked in sequence. Not shown) and a mask layer (for example, containing silicon oxide, silicon nitride or silicon carbonitride, not shown).
  • an interlayer dielectric layer 500 is formed on the semiconductor substrate 410, which Materials include silicon oxide, silicon nitride or low-K dielectrics. Specifically, the interlayer dielectric layer 500 is completely covered on the semiconductor substrate 410 through a deposition process, and the interlayer dielectric layer 500 is made to fill the space between the bit lines BL and bury the bit lines BL, and then chemically Processes such as mechanical polishing flatten the interlayer dielectric layer 500 to form the interlayer dielectric layer 500 having a flat top surface as a whole. Wherein, the top surface of the planarized interlayer dielectric layer 500 is at least higher than the top surface of each bit line BL.
  • the interlayer dielectric layer 500 is sequentially formed with the pattern of the first mask 10
  • the second mask layer P2 is formed on the first mask layer P1 and the exposed interlayer dielectric layer 500
  • the third mask layer P3 is formed on the second mask layer P2 and the exposed first mask layer.
  • the first lines in the first mask layer P1 and the second lines in the second mask layer P2 perpendicularly intersect and define some grooves arranged in a checkerboard shape.
  • the three mask layer P3 masks all the trenches in the boundary area III and part of the trenches at the boundary of the core area I to define the positions of each effective storage node contact structure.
  • a contact hole that penetrates the interlayer dielectric layer 500 and exposes the corresponding S/D used as a source region below
  • a contact hole (not shown) that exposes the corresponding area in the peripheral region II can be formed at the same time .
  • the size of the contact hole at the boundary of the core region I may be larger than the size of the contact hole inside the core region 1.
  • a contact hole may also be formed in the region where the boundary region III is close to the boundary of the core region I, and the contact plug in the contact hole in the subsequent boundary region III may be at the boundary of the core region I The tops of the corresponding contact plugs are connected together.
  • an ashing process or wet cleaning or other suitable processes may be performed to remove the third mask layer P3 and the second mask layer above the interlayer dielectric layer 500.
  • the mold layer P2 and the first mask layer P1 are filled with a barrier metal layer (not shown) and a conductive metal layer (not shown) in sequence in each contact hole, and the barrier metal layer may cover the contact hole with a uniform thickness
  • the barrier metal layer can reduce or prevent the metal material provided in the contact hole from diffusing into the interlayer dielectric layer 500.
  • the conductive metal layer can be formed by ( One or more) refractory metals (e.g., cobalt, iron, nickel, tungsten, and/or molybdenum) are formed.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the conductive metal layer can be formed by ( One or more) refractory metals (e.g., cobalt, iron, nickel, tungsten, and/or molybdenum) are formed.
  • the conductive metal layer may be formed using a deposition process with good step coverage properties, for example, formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (for example, sputtering).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the formed conductive metal layer also covers the surface of the interlayer dielectric layer 500 around the contact hole.
  • CMP chemical mechanical polishing
  • the top surface of the interlayer dielectric layer 500 forms a contact plug CT in the interlayer dielectric layer 500.
  • FIG. 20 shows a part of the non-contact plugs above the active area AA1 at the boundary of the core area I (for these positions, contact plugs are formed in the prior art, but not in the present invention, that is, in FIG. 20 Used for dashed frame column dCT for contrast), another part of the active area AA1 above has a contact plug CT.
  • the contact plug CT serves as a storage node contact structure in the core area I, and is used to connect with a capacitor formed above the core area I later.
  • a capacitor 705 is formed above each S/D of the core area I.
  • the capacitor 705 whose bottom is electrically connected to the corresponding S/D through the corresponding contact plug CT is an effective capacitor. Participate in testing and device operation, and the capacitor with no contact plug CT between the bottom and the corresponding S/D is a virtual capacitor, and will no longer participate in device-related testing and device operation in the future, thereby increasing the pass rate of the product.
  • each capacitor 705 includes a lower electrode layer 701, a capacitor dielectric layer 702, and an upper electrode layer 703.
  • the capacitors 705 have a bottom support layer 600, a middle support layer 601, and a top support layer that are laterally supported and stacked in intervals. 602.
  • the bottom support layer 600 is used to support the bottom electrode layer subsequently formed on the one hand, and also to isolate the internal components of the semiconductor substrate 410 from the upper capacitors and other components on the other hand.
  • the formation process of the bottom support layer 600 may also be a thermal oxidation process.
  • the materials of the bottom support layer 600, the middle support layer 601 and the top support layer 602 include but are not limited to silicon nitride.
  • two or more intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602.
  • all the capacitors 705 may be arranged in a hexagonal close-packed arrangement.
  • the lower electrode layer 701 has a cylindrical structure, and may be a polysilicon electrode or a metal electrode.
  • a metal electrode a stacked structure of titanium nitride (TiN) and Ti can also be used.
  • TiN titanium nitride
  • the lower electrode layer 701 is a polysilicon electrode, it may be formed of a zero-doped and/or doped polysilicon material.
  • the capacitor dielectric layer 702 covers the inner surface and the outer surface of the cylindrical structure of the lower electrode layer 701 to make full use of the two opposite surfaces of the lower electrode layer 701 to form a capacitor with a larger electrode surface area.
  • the capacitor dielectric layer 702 may be a high-K dielectric layer such as metal oxide.
  • the capacitor dielectric layer 702 has a multilayer structure, for example, a two-layer structure of hafnium oxide-zirconia.
  • the upper electrode layer 703 may be a single-layer structure or a multilayer structure.
  • the upper electrode layer 703 is a single-layer structure, for example, a polysilicon electrode or a metal electrode, when the upper electrode layer 703 is a metal electrode In this case, for example, titanium nitride (TiN) can be used.
  • TiN titanium nitride
  • the upper electrode layer 703 can form a capacitor with the capacitive dielectric layer 702 and the lower electrode layer 701 corresponding to the inside of the cylindrical structure and the outside of the cylindrical structure.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 all have uneven sidewall structures corresponding to the middle support layer 601 and the top support layer 602 outside the cylindrical structure of the lower electrode layer 701, As a result, the part of the upper electrode layer 703 on the edge area of the core area I (that is, the boundary area of the capacitor hole array) corresponds to the middle support layer 601 and the top support layer 602 to be far away from the lower electrode layer 701 Protruding in the direction of, making the boundary of the capacitor array in the core area I uneven.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 also extend sequentially to cover the surface of the bottom support layer 600 retained on the peripheral region II.
  • the upper electrode layer 703 The surface is also covered with an upper electrode filling layer 704.
  • the upper electrode filling layer 704 fills the gap between the upper electrode layers 703, that is, the upper electrode filling layer 704 fills the adjacent cylindrical structure. And cover the structure formed above.
  • the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon.
  • the present invention also provides a semiconductor device manufactured by the above-mentioned semiconductor device manufacturing method, including: a semiconductor substrate 410, an interlayer dielectric layer 500 and a plurality of contact plugs CT.
  • the semiconductor substrate 410 has a core area I, a peripheral area II, and a boundary area III between the core area I and the peripheral area II, and a shallow trench isolation structure defining each active area AA1 is formed in the core area I 411b, a shallow trench isolation structure 411a defining the core area I and the peripheral area II is formed in the boundary area II.
  • the interlayer dielectric layer 500 is formed on the semiconductor substrate 410, and may be silicon dioxide, silicon nitride, or a low-K dielectric (the dielectric constant K is lower than 3).
  • a plurality of contact plugs CT are formed in the interlayer dielectric layer 500 and are in contact with the active area AA1 of the corresponding core element. Wherein, there are no contact plugs above part of the active area AA1 at the boundary of the core area I.
  • the contact plugs CT at the borders on opposite sides of the core area I are distributed asymmetrically, for example, the contact plugs at the upper and lower borders of the core area I are distributed asymmetrically, and/or , The contact plugs at the left boundary and the right boundary of the core area I are distributed asymmetrically.
  • the semiconductor device may be a memory, which further includes a plurality of word lines WL, source and drain regions S/D, bit line contacts (not shown), and a plurality of bit lines BL (not shown) .
  • each word line WL is a buried word line, which is formed in the semiconductor substrate 410 and crosses the active area AA1.
  • the source and drain regions S/D are formed in the active region AA1 on both sides of the word line.
  • the bit line contact is formed on the drain region, and each bit line is formed on the corresponding bit line contact and crosses each of the word lines.
  • the interlayer dielectric layer 500 bury the semiconductor substrate 410, the word line WL, the source and drain regions S/D, the bit line contact and the bit line.
  • the formation position of the contact plug is defined by the mask combination provided by the present invention, so that there is no contact plug on the part of the active area at the boundary of the core area, and the core There are contact plugs on the other active areas at the boundary of the area and the active area inside the core area. Therefore, when the corresponding electrical structure is formed in the inner and boundary of the core area by subsequent use of the existing process, the core Part of the electrical structure at the boundary of the region becomes a virtual structure because there is no contact plug underneath that is in contact with the active region, which can prevent the manufactured semiconductor device from failing due to the electrical structure at the boundary of the core region.
  • the problem of testing improves the performance and pass rate of the semiconductor devices produced.

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Abstract

本发明提供了一种电接触结构、掩模板组合、接触插塞制作方法及半导体器件，通过将至少最靠近所述周边区的第一个接触插塞形成于核心区和周边区的交界区的隔离结构上方并与该隔离结构接触，且可以使得第一个接触插塞的底部完全重叠在该隔离结构上，或者，一部分底部与该隔离结构重叠，另一部分底部与紧挨该隔离结构的核心区的有源区重叠，甚至使得第一个接触插塞的顶部至少与紧挨该隔离结构的核心区的有源区上方的接触插塞的顶部相联在一起，由此，可以使得原先在核心区边界最外侧上形成的电学结构至少部分形成于交界区的隔离结构上方，进而保证核心区内部中的接触插塞上方的电学结构的一致性以及保证核心区边界上的电学结构的性能。

Description

电接触结构、掩模板组合、接触插塞制作方法及半导体器件 技术领域
本发明涉及半导体技术领域，特别涉及一种电接触结构、掩模板组合及接触插塞制作方法、半导体器件及其制造方法。
背景技术
已使用各种技术，在半导体衬底或晶片的有限面积中集成更多电路图案。由于电路图案间距的不同，集成电路一般分为器件密集区(Dense)、器件稀疏区(ISO)及器件孤立区，器件密集区是器件密度较高(即器件比较密集)的区域，器件稀疏区是器件密度较低(即器件比较稀疏)的区域，器件孤立区是相对稀疏区和密集区单独设置的区域。随着半导体器件的临界尺寸不断减小，电路图案的密度和/或器件高度也不断增加，受到曝光机台(optical exposure too1)的分辨率极限以及器件密集区和器件稀疏区之间的密度差异效应(即电路图案的密集/稀疏效应)的影响，在执行光刻工艺和/或蚀刻工艺时的困难也会增大很多(例如，工艺余量减小)，进而导致制造出来的半导体器件的性能受到影响。
例如，在动态随机存取存储(dynamic random access memory，以下简称为DRAM)装置的情况中，数目庞大的存储单元(memory cell)聚集形成一存储阵列核心区，而核心区的旁边存在有周边区，周边区内包含有其他晶体管元件以及接触结构等，存储阵列核心区作为DRAM的器件密集区，用来存储数据，周边区作为DRAM的器件稀疏区，用于提供存储阵列核心区所需的输入输出信号等。其中，存储阵列核心区中的每一存储单元可由一金属氧化物半导体(metal oxide semiconductor，MOS)晶体管与一电容器(capacitor)串联组成。其中，电容器位于存储阵列核心区内，所述电容器堆叠在位线上方并电耦接至所述电容器对应的存储节点接触部，所述存储节点接触部电耦接至其下的有源区。随着半导体技术的不断发展，器件的临界尺寸不断减小，DRAM装置的存储单元之间的间隙变得更窄，当通过自对准接触(Self Aligned Contact，SAC)工艺形成存储节点接触部时，受到曝光机台(optical  exposure too1)的分辨率极限以及器件密集区和器件稀疏区之间的密度差异效应的影响，存储阵列核心区边界最外侧上的接触孔容易产生异常，进而导致其上方形成的电容器与该接触孔中的接触插塞接触面积减小、接触阻抗的增加，甚至造成阵列存储区边界最外侧的电容器坍塌的问题，这些问题影响和限制了DRAM性能的提高。
发明内容
本发明的目的在于提供一种电接触结构、掩模板组合及接触插塞制作方法、半导体器件及其制造方法，以解决现有的动态随机存取存储器等半导体器件因光学邻近效应以及电路图案的密集/稀疏效应而导致核心区边界最外侧的接触插塞上接的电学结构异常等问题，改善器件性能。
为解决上述技术问题，本发明提供一种半导体器件的电接触结构，所述半导体器件包括一衬底，所述衬底包括核心区、周边区以及位于所述核心区和周边区的交界区，所述交界区中形成有隔离结构，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区，所述电接触结构包括：
多个接触插塞，形成于所述核心区和所述隔离结构的上方；
其中，所述多个接触插塞包括最靠近所述周边区的第一个接触插塞，至少所述第一个接触插塞形成于所述隔离结构上方并与所述隔离结构接触，其余的所述接触插塞形成于所述核心区的各所述核心元件的上方且底部与相应的所述核心元件的有源区接触。
基于同一发明构思，本发明还提供一种半导体器件，包括：
衬底，所述衬底包括核心区、周边区以及位于所述核心区和所述周边区的交界区，所述交界区中形成有隔离结构，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区；
层间介质层，覆盖在所述衬底上；以及，
如上所述的半导体器件的电接触结构，所述电接触结构形成于所述层间介质层中。
基于同一发明构思，本发明还提供一种如本发明所述的半导体器件的电 接触结构的制造方法，其特征在于，包括：
提供衬底，所述衬底具有核心区、周边区以及位于所述核心区和所述周边区的交界区，所述交界区中形成有隔离结构，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区；
在所述衬底上形成层间介质层，并在所述层间介质层中形成多个接触孔，其中，所述多个接触孔包括最靠近所述周边区的第一个接触孔，至少所述第一个接触孔贯穿所述层间介质层并暴露出部分所述隔离结构，其余的所述接触孔贯穿所述层间介质层并暴露出相应的所述核心元件的有源区；
在各个所述接触孔中形成相应的接触插塞。
基于同一发明构思，本发明还提供一种半导体器件的制造方法，包括：采用本发明所述的半导体器件的电接触结构的制造方法，在一具有核心区、周边区和隔离结构的半导体衬底上形成相应的电接触结构。
与现有技术相比，本发明的技术方案具有以下有益效果：
通过将至少最靠近所述周边区的第一个接触插塞形成于核心区和周边区的交界区的隔离结构上方并与该隔离结构接触，且可以使得第一个接触插塞整体上与该隔离结构重叠，或者，可以使得第一个接触插塞的一部分底部与该隔离结构重叠，另一部分底部与紧挨该隔离结构的核心区的有源区重叠，甚至可以进一步使得第一个接触插塞的顶部至少与紧挨该隔离结构的核心区的有源区上方的接触插塞的顶部相联在一起。当第一个接触插塞整体上与该隔离结构重叠时，可以使得原先在核心区边界最外侧上形成的电学结构完全形成于交界区的隔离结构上方并作为虚拟结构，进而通过该虚拟结构保证核心区边界和内部的接触插塞上接的电学结构的一致性。当第一个接触插塞的一部分底部与该隔离结构重叠，另一部分底部与紧挨该隔离结构的核心区的有源区重叠，和/或，第一个接触插塞的顶部与核心区中的至少一个接触插塞的顶部相联在一起时，第一个接触插塞的顶部横截面积相对增大，一方面，为后续在第一个接触插塞上方形成电学结构的工艺提供足够的工艺余量，有利于该交界区的所述电学结构的尺寸增大，避免该交界区的电学结构出现异常或坍塌；另一方面，能够使得第一个接触插塞上方形成电学结构和第一个 接触插塞有较大的接触面积，从而降低接触阻抗，有利于提高器件的电学性能；更重要的是，通过第一个接触插塞使得其上接的电学结构的尺寸增大，能够缓冲核心区和周边区之间的电路图案的密度差异，从而在形成核心区中的所有电学结构的光刻工艺和/或蚀刻工艺中能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区中的接触插塞上方的电学结构的一致性，提高器件性能。此外，由于第一个接触插塞至少部分位于所述交界区上，一方面，可以尽量减小第一个接触插塞及其上接的电学结构(该电学结构的面积可以缩很小)对核心区的占用面积，有利于提高核心区的有效面积利用率，进而有利于提高器件密度；另一方面，可以使得第一个接触插塞及其上接的电学结构的尺寸尽量增大，从而使得在改善核心区内部的所有接触插塞上接的电学结构之间的一致性等方面具有更好的效果。
进一步的，本发明还提供一种掩模板组合，用于制作接触插塞，所述掩模板组合包括：
第一掩模板，具有多条平行的第一遮光条纹，相邻的两条所述第一遮光条纹之间为第一透光区；
第二掩模板，具有多条平行的第二遮光条纹，相邻的两条所述第二遮光条纹之间为第二透光区；
第三掩模板，具有遮光块和与所述遮光块互补的第三透光区；
其中，所述第一掩模板、所述第二掩模板和所述第三掩模板依次叠置在一起时，所述多条平行的第二遮光条纹与每条所述第一条纹相交，所述遮光块覆盖最靠近所述第一掩模板的边界的至少一条第一遮光条纹和被覆盖的该条第一遮光条纹最近邻的部分第一透光区，以及，所述遮光块还覆盖最靠近所述第二掩模板的边界的至少两条第二遮光条纹以及被覆盖的所述两条第二遮光条纹之间的部分所述第二透光区，所述第三透光区、所述第一透光区和所述第二透光区的重叠区域为用于形成接触插塞的区域。
基于同一发明构思，本发明还提供一种接触插塞制作方法，使用本发明所述的掩模板组合来制作，所述接触插塞制作方法包括：
提供形成有多个有源区的半导体衬底，在所述半导体衬底上依次形成层 间介质层和第一掩模层；
采用光刻结合刻蚀的工艺，将所述掩模板组合中的第一掩模板上的图案转移到所述第一掩模层上以得到转移后的第一掩模层，所述转移后的第一掩模层中形成有多条第一线条，其中，每条所述第一线条对应所述第一掩模板上相应的第一遮光条纹，相邻所述第一线条之间的沟槽对应所述第一掩模板上相应的第一透光区并暴露出相应的所述层间介质层；
在所述层间介质层和所述第一掩模层上覆盖第二掩模层，并采用光刻结合刻蚀的工艺，将所述掩模板组合中的第二掩模板上的图案转移到所述第二掩模层上以得到转移后的第二掩模层，所述转移后的第二掩模层中形成有多条第二线条，所述多条第二线条与每条所述第一线条相交，其中，每条所述第二线条对应所述第二掩模板上相应的第二遮光条纹，相邻所述第二线条之间的沟槽对应所述第二掩模板上相应的第二透光区并暴露出相应的所述第一线条以及所述第一透光区中的层间介质层；
在所述第一掩模层、第二掩模层和层间介质层上覆盖第三掩模层，并采用光刻结合刻蚀的工艺，将所述掩模板组合中的第三掩模板上的图案转移到所述第三掩模层上以得到转移后的第三掩模层，所述转移后的第三掩模层对应所述第三掩模板的遮光块，所述转移后的第三掩模层、所述转移后的第一掩模层和所述转移后的第二掩模层共同暴露出的所述层间介质层作为待形成接触插塞的区域；
以所述转移后的第一掩模层、所述转移后的第二掩模层和所述转移后的第三掩模层为掩模，刻蚀暴露出的所述层间介质层，以形成暴露出相应的有源区的多个接触孔；
在每个所述接触孔中形成接触插塞，各个所述接触插塞的底部与相应的所述有源区接触。
基于同一发明构思，本发明还提供一种半导体器件的制造方法，包括：采用本发明所述的制作接触插塞的方法，在一具有核心区的半导体衬底上形成接触插塞，各个所述接触插塞的底部与核心区中相应的核心元件的有源区接触。
基于同一发明构思，本发明还提供一种采用本发明所述的半导体器件的制造方法制造的半导体器件，包括：
半导体衬底，所述半导体衬底包括核心区，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区；
层间介质层，形成在所述半导体衬底上；
多个接触插塞，形成所述层间介质层中，并与相应的核心元件的有源区接触；
其中，所述核心区边界处的部分有源区的上方无接触插塞。
与现有技术相比，本发明的技术方案具有以下有益效果：
通过本发明提供的掩模板组合，来定义接触插塞的形成位置，以使得核心区边界处的部分有源区的上方无接触插塞，而核心区边界处的其他有源区以及核心区内部的有源区的上方均有接触插塞，由此，后续再采用现有工艺在核心区的内部和边界处形成相应的电学结构时，使得核心区边界处的部分电学结构因其下方没有与有源区接触的接触插塞而变为虚拟结构，由此可以避免制造出来的半导体器件因核心区边界处的电学结构的问题而导致不能通过相关测试的问题，继而提高了制得的半导体器件的性能和合格率。
附图说明
图1A～1C是本发明具体实施例的半导体器件的电学接触结构的剖面结构示意图；
图2A～2D是图1C的半导体器件的电学接触结构的一种具体示例的制造方法中的剖面结构示意图；
图3A～3D是图1C的半导体器件的电学接触结构的另一种具体示例的制造方法中的剖面结构示意图；
图4是本发明一实施例的半导体器件的制造方法中的俯视结构示意图；
图5～13是本发明一实施例的半导体器件的制造方法中的沿图4中的aa’线的剖面结构示意图；
图14是本发明具体实施例的第一掩模板的结构示意图；
图15是本发明具体实施例的第二掩模板的结构示意图；
图16是本发明具体实施例的第一掩模板的结构示意图；
图17A是本发明具体实施例的第一掩模板和核心区的有源区的图案对准重叠后的结构示意图(其中省略了一些影响观察图案对准重叠效果的层)；
图17B是本发明具体实施例的第二掩模板、第一掩模板和核心区的有源区的图案对准重叠后的结构示意图(其中省略了一些影响观察图案对准重叠效果的层)；
图17C是本发明具体实施例的第三掩模板、第二掩模板、第一掩模板和核心区的有源区的图案对准重叠后的结构示意图(其中省略了一些影响观察图案对准重叠效果的层)；
图18是本发明具体实施例中利用掩模板组合在核心区上制作的接触插塞的分布示意图，其中在核心区边界处的部分有源区的上方无接触插塞；
图19是本发明具体实施例在图18中核心区边界处且沿aa’线的剖面结构示意图；
图20是本发明具体实施例的半导体器件在核心区边界处的剖面结构示意图。
其中，附图标记说明如下：
I-核心区；II-周边区；III-交界区；H1、H2-深度；AA1、AA2-有源区；WL-埋入式字线；BL-位线；S/D1、S/D2-源区和漏区；G1-栅极结构；W1-第一宽度；W2-第二宽度；
100-衬底；100a、100b-隔离结构；101-有源区；102-层间介质层；102a、102b、102c-接触孔；102d-沟槽；103a、103b、103c-接触插塞；104-第一掩模图案；105-牺牲层；106-第二掩模图案；107-第二层间介质层；107a、107b、107c-沟槽；180-第二掩模图案；109a、109b、109c-接触垫；300-半导体衬底；300a-半导体基底；301a、301b-浅沟槽隔离结构；302-栅极盖层；303-刻蚀停止层；304-侧墙；400-层间介质层；401a、401b、401d、401e-接触孔；401c-沟槽；402-牺牲层；501a、501d、501e-接触插塞；501b-组合接触结构；600-底层支撑层；601-中间支撑层；602-顶层支撑层；611-第一牺牲层；612-第二 牺牲层；700a、700b-电容孔；701-下电极层；702-电容介质层；703-上电极层；704-上电极填充层；705a、705b-电容器；
K1-第一宽度；K2-第二宽度；P1-第一掩模层；P10、P11、P12-第一线条；P2-第二掩模层；P20-第二线条；CTa-沟槽；CT-接触插塞；P3-第三掩模层；
10-第一掩模板；111a、111b、111c-第一遮光条纹；112-第一透光区；20-第二掩模板；201-第二遮光条纹；202-第二透光区；30-第三掩模板；311-遮光块；312-第三透光区；410-半导体衬底；410a-半导体基底；411a、411b-浅沟槽隔离结构；412-栅极盖层；413-刻蚀停止层；500-层间介质层。
具体实施方式
以下结合附图和具体实施例对本发明提出的电接触结构、掩模板组合及接触插塞制作方法、半导体器件及其制造方法作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
图1A是示出本发明一实施例的半导体器件的电接触结构的剖面示意图。请参考图1A，本发明一实施例提供的半导体器件的电接触结构包括:一衬底100和多个接触插塞103a、103b。其中，所述衬底100包括核心区I和周边区II以及位于所述核心区I和周边区II之间的交界区III(又称为界面处)，所述交界区III中形成有隔离结构100a，核心区I为器件密集区，其周围的周边区II为器件稀疏区。多个接触插塞103a、103b形成于所述核心区I和所述交界区III的隔离结构100a的上方，且至少最靠近所述周边区II的第一个接触插塞103b形成于所述交界区III的隔离结构100a的上方，且底部与所述交界区III的隔离结构100a接触，其余的接触插塞103a均形成于所述核心区I的核心元件(未图示)的上方，且底部与相应的所述核心元件的有源区101接触。每个接触插塞103a、103b可以包括阻挡金属层(未图示)和金属层(未图示)，阻挡金属层可以包括例如Ti、Ta、Mo、Ti xN y、Ta xN y、TixZry、Ti xZr yN z、Nb xN y、Zr xN y、W xN y、V xN y、Hf xN y、Mo xN y、Ru xN y和/或Ti xSi yN z。金属层可以包括 例如钨、铜和/或铝。每个接触插塞103a还可以包括金属硅化物，以降低其与有源区101之间的接触电阻。本实施例中，第一个接触插塞103b的底部完全重叠在所述交界区III的隔离结构100a上，且所述第一个接触插塞103b的底部可以伸入到所述交界区III的隔离结构100a的内部，可选地，所述第一个接触插塞103b的底部伸入到所述交界区III的隔离结构100a的内部的深度H1小于其余的所述接触插塞103a(即核心区I内的接触插塞103a)的底部伸入到相应的有源区101内的深度H2。图1A所示的实施例中，所述交界区III的隔离结构100a上的第一个接触插塞103b整体上重叠在该隔离结构100a上，由此，可以使得原先在核心区I边界最外侧上形成的电学结构(未图示，可参考图13的电容器)完全形成于交界区III的隔离结构100a上方并作为虚拟结构，进而通过该虚拟结构保证核心区I内的各个接触插塞103a上接的电学结构的一致性。
图1B是示出本发明另一实施例的半导体器件的电接触结构的剖面示意图。请参考图1B，本发明另一实施例提供的半导体器件的电接触结构包括:一衬底100和多个接触插塞103a、103b。其中，所述衬底100具有核心区I和周边区II以及位于所述核心区I和周边区II之间的交界区III，所述交接区III中形成有隔离结构100a，核心区I为器件密集区，其周围的周边区II为器件稀疏区。多个接触插塞103a、103b形成于所述核心区I和所述交界区III的隔离结构100a的上方，且至少最靠近所述周边区II的第一个接触插塞103b形成于所述交界区III的隔离结构100a和核心区I中紧挨所述交界区III的隔离结构100a的有源区101的上方，且底部的一部分与所述交界区III的隔离结构100a接触和重叠，底部的另一部分与核心区I中紧挨所述交界区III的隔离结构100a的有源区101接触和重叠。本实施例中的第一个接触插塞103b与图1A所示的实施例中的第一个接触插塞103b的区别在于，本实施例中的第一个接触插塞103b的底部从所述交界区III的隔离结构100a上一直横向延伸到紧挨所述交界区III的隔离结构100a的核心区I的有源区101上，且所述第一个接触插塞103b的底部可以伸入到所述交界区III的隔离结构100a和相应的有源区101的内部。可选地，所述第一个接触插塞103b的底部伸入到所 述交界区III的隔离结构100a的内部的深度H1小于其余的所述接触插塞103a(即核心区I内的接触插塞103a)的底部伸入到相应的有源区101内的深度H2。当衬底中形成有埋入在所述衬底100中的栅极(未图示，可参考图5中的埋入式字线WL)时，第一个接触插塞103b仅有一侧与其最近邻的埋入在所述衬底100的栅极接触。图1B所示的实施例中，交界区III的隔离结构100a上方的第一个接触插塞103b的一部分底部与该交界区III的隔离结构100a重叠，另一部分底部与紧挨交界区III的隔离结构100a的核心区I的有源区101重叠，因此，交界区III的隔离结构100a上方的第一个接触插塞103b的横截面积相对增大，一方面，为后续在交界区III形成电学结构(未图示，可参考图13的电容器)的工艺提供足够的工艺余量，有利于该交界区III上的所述电学结构的尺寸增大，避免该交界区III第一个接触插塞103b上接的电学结构出现异常或坍塌；另一方面，能够使得该交界区III第一个接触插塞103b上接的电学结构和第一个接触插塞103b有较大的接触面积，从而降低接触阻抗，有利于提高器件的电学性能；更重要的是，通过该交界区III第一个接触插塞103b使得其上接的电学结构的尺寸增大，能够缓冲核心区I和周边区II之间的电路图案的密度差异，从而在形成核心区I中的所有电学结构的光刻工艺和/或蚀刻工艺中能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区I中的各个接触插塞103a上方的电学结构的一致性，提高器件性能。
图1C是示出本发明又一实施例的半导体器件的电接触结构的剖面示意图。请参考图1C，本发明又一实施例提供的半导体器件的电接触结构包括:一衬底100和多个接触插塞103a、103b。其中，所述衬底100具有核心区I和周边区II以及位于所述核心区I和周边区II之间的交界区III，所述交界区III中形成有隔离结构100a，核心区I为器件密集区，其周围的周边区II为器件稀疏区。多个接触插塞103a、103b形成于所述核心区I和所述交界区III的隔离结构100a的上方，且至少最靠近所述周边区II的第一个接触插塞103b形成于所述交界区III的隔离结构100a上方，且其底部完全重叠在所述交界区III的隔离结构100a上，顶部至少与核心区I中紧挨所述交界区III的隔离结构100a的有源区101上的一个接触插塞103a相联在一起。本实施例中的第 一个接触插塞103b与图1A所示的实施例中的第一个接触插塞103b的区别在于，本实施例中的第一个接触插塞103b的顶部与紧挨所述交界区III的隔离结构100a的核心区I的有源区101上的至少一个接触插塞103a的顶部相联在一起。图1C所示的实施例中，交界区III的隔离结构100a上方的第一个接触插塞103b和其他至少一个接触插塞103a的顶部相联在一起而形成的组合接触结构的顶部横截面积相对增大，一方面，为后续在交界区III形成电学结构(未图示，可参考图13的电容器)的工艺提供足够的工艺余量，有利于该交界区III上的所述电学结构的尺寸增大，避免该交界区III的组合接触结构上接的电学结构出现异常或坍塌；另一方面，能够使得该交界区III的组合接触结构上接的电学结构和该组合接触结构有较大的接触面积，从而降低接触阻抗，有利于提高器件的电学性能；更重要的是，通过该交界区III的组合接触结构使得其上接的电学结构的尺寸增大，能够缓冲核心区I和周边区II之间的电路图案的密度差异，从而在形成核心区I中的所有电学结构的光刻工艺和/或蚀刻工艺中能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区I中的各个接触插塞103a上方的电学结构的一致性，提高器件性能。其中顶部相联在一起的所有接触插塞103b、103a构成倒U形电接触结构或者梳状电接触结构。
需要说明的是，在上述各实施例中，第一个接触插塞103b和核心区I中的各个接触插塞103a所对应的接触孔通过同一道刻蚀工艺和同一道填充工艺形成，以简化工艺。且因为接触插塞103a所对应的接触孔的底部需要暴露出有源区101，而交界区III的第一个接触插塞103b所对应的接触孔的底部需要暴露隔离结构100a，且隔离结构100a的材质和有源区101的材质不同，当同时刻蚀形成相应的接触孔时，隔离结构100a被刻蚀的速度较慢，有源区101被刻蚀的速度较快，由此使得，所述交界区III的第一个接触插塞103b的底部伸入到所述交界区III的隔离结构100a的内部的深度H1小于其余的所述接触插塞103a(即核心区I内的接触插塞103a)的底部伸入到相应的有源区101内的深度H2。
此外，还需要说明的是，核心区I中的相邻核心元件的有源区101之间也 形成相应的隔离结构100b，以用于定义每个核心元件的有源区101；周边区II中也形成有隔离结构100b和相应的接触插塞103c，隔离结构100b用于定义每个***元件的有源区101。
请结合图1A～1C和图13，本实施例中，半导体器件为动态随机存取存储器(dynamic random access memory，DRAM)，核心区为DRAM存储器的存储阵列区，核心元件为存储晶体管，所述电接触结构为存储节点接触部，上接电容器(即存储节点，storage node)。即核心区I中的每个接触插塞103a上接一个电容器(如图12中705a所示)，核心区I和交界区III的所有接触插塞中最靠近周边区II的第一个接触插塞103b上接一个电容器(如图12中705b所示)，且所述交界区III的电容器具有第一宽度W1，所述核心区I的电容器具有第二宽度W2，可选地，所述第一宽度W1大于所述第二宽度W2，一方面，避免该交界区III形成的电容器坍塌；另一方面，使得该交界区III的电容器的尺寸增大，能够缓冲核心区I和周边区II之间的电路图案的密度差异，从而在执行光刻工艺和/或蚀刻工艺时能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区I内的各个接触插塞103a上方的电容器的一致性，防止出现核心区I内一些位置的接触插塞上方的电容器出现异常或核心区I边界最外侧的接触插塞上方的电容器出现坍塌的问题。例如W1＝1.3*W2～2.3*W2，作为一种示例，W1＝1.5*W2。
此外，当第一个接触插塞的顶部不与核心区中的其他的接触插塞连接在一起时，其上接的电学结构可以作为虚拟结构，且其面积越小越好，由于第一个接触插塞至少部分位于所述交界区的隔离结构上，因此可以使其上接的电学结构的面积可以缩很小，减小了其对核心区的占用面积，有利于提高核心区的有效面积利用率，进而有利于提高器件密度。
请结合图4所示，所述半导体器件包括多条字线WL和多条位线BL，每条所述字线WL与所述核心区I中的多个所述有源区AA1相交，所述字线WL可以是埋入式字线，所述位线BL形成在核心区I的核心元件的上方并与所述字线WL垂直。当核心区I和交界区III的所有接触插塞中最靠近周边区II的第一个接触插塞103b采用图1B所示的结构时，即所述第一个接触插塞 103b形成于所述交界区III的隔离结构100a和核心区I中紧挨所述交界区III的隔离结构100a的有源区101的上方，且所述第一个接触插塞103b的底部的一部分与所述交界区III的隔离结构100a接触和重叠，所述第一个接触插塞103b的底部的另一部分与核心区I中紧挨所述交界区III的隔离结构100a的有源区101接触和重叠，且所述第一个接触插塞103b仅有面向所述核心区I的一侧与其最近邻的埋入在所述衬底100的字线WL接触。当核心区I和交界区III的所有接触插塞中最靠近周边区II的第一个接触插塞103b采用图1C所示的结构时，即所述第一个接触插塞103b形成于所述交界区III的隔离结构100a上方，且其顶部至少与核心区I中紧挨所述交界区III的隔离结构100a的有源区101的上方的一个接触插塞103a的顶部相联在一起，所述顶部相联在一起的所有接触插塞构成倒U形电接触结构或者梳状电接触结构，且倒U形电接触结构或者梳状电接触结构可以与核心区I最边界(即核心区I最外侧)上的所述字线WL(即核心区I中最靠近交界区的字线)接触并与所述位线BL对准(即平行)，例如形成的倒U形电接触结构或者梳状电接触结构最靠近核心区I的一侧与核心区I最外侧的一个有源区AA1中的一条字线WL接触。需要说明的是，本实施例中，虽然举例所述半导体器件为DRAM，但是本发明的技术方案并不仅仅限定于此，半导体器件还以是任意合适的电学器件，例如其他架构的存储器，此时，所述电容器可以替代为相应的电学结构，例如电阻器等。
图2A～图2D是示出图1C所示的半导体器件的电接触结构的一种制造方法中的器件剖面示意图。请参考图2A～图2D，本实施例提供一种半导体器件的电接触结构的制造方法，包括以下步骤：
首先，请参照图2A，提供一个半导体衬底100，其包含核心区I、周边区II以及位于核心区I和周边区II之间的交界区III，半导体衬底100可以选自硅基板、绝缘体上硅基板(SOI)、锗基板、绝缘体上锗基板(GOI)、硅锗基板等。半导体衬底100中形成有多个浅沟槽隔离结构100a、100b，该浅沟槽隔离结构100a、100b通过刻蚀半导体衬底100以形成沟槽，然后再向沟槽中填入绝缘材料的方式来形成，该浅沟槽隔离结构100a、100b的材质可包含氧化硅、 氮化硅、或是氮氧化硅等。位于交界区III的浅沟槽隔离结构101a在二维平面上界定出了核心区I和周边区II的交界，位于核心区I中的浅沟槽隔离结构100a在二维平面上界定出了核心区I中的各个核心元件所对应的有源区101，位于周边区II中的浅沟槽隔离结构(未图示)在二维平面上界定出了周边区II中的各个***元件所对应的有源区101。
接着，请继续参照图2A，在半导体衬底100上覆盖层间介质层102，层间介质层102可以被设置成具有单层结构或多层结构。层间介质层102可以包括氮化硅、氮氧化硅和低k介电材料中的至少一种。其中，低k介电材料的介电常数k小于氧化硅的介电常数，并且它可以用作金属间介电层(IMD)，例如为高密度等离子体(HDP)氧化物、原硅酸四乙醋(TEOS)、等离子体增强型TEOS(PE-TEOS)、未掺杂硅酸盐玻璃(USG)、硅酸磷玻璃(PSG)、硅酸硼玻璃(BSG)、硅酸硼磷玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、旋涂式玻璃(SOG)等。另外，可以在半导体衬底100和层间介质层102之间形成蚀刻停止层(未图示)，蚀刻停止层可以包括SiN、SiON、SiC、SiCN、BN(氮化棚)或其任何组合。可以使用等离子体增强型CVD(PECVD)、高密度等离子体CVD(HDP-CVD)、大气压CVD(APCVD)和/或旋涂工艺形成蚀刻停止层和层间介质层102。
然后，请继续参照图2A，通过第一次光刻工艺，在层间介质层102上形成第一掩模图案104，该第一掩模图案104定义出各个接触插塞的位置，然后，使用第一掩模图案104作为蚀刻掩模，各向异性地蚀刻层间介质层102，以形成贯穿所述层间介质层102且暴露出下方相应的有源区101的接触孔102a、102b和102c，接触孔102a、102b和102c均相互独立，每个接触孔102a位于核心区I中并暴露出核心区I中的相应核心元件的有源区101，每个接触孔102b位于交界区III中且暴露出交界区III中的隔离结构100a，每个接触孔102c位于周边区II中并暴露出相应***元件的有源区101。
然后，请参考图2B，在形成接触孔102a～102c之后，可以执行灰化工艺或湿式清洗工艺，以去除第一掩模图案104，并填充牺牲层105于各个接触孔102a～102c中。所述牺牲层105可以由旋涂硬掩模层(SOH)或非晶碳层(ACL) 形成，这样可以使得能够用牺牲层105填充具有高的高宽比的接触孔102a～102c。
接着，请继续参考图2B，可以通过第二次光刻工艺在层间介质层102和牺牲层105上形成第二掩模图案106，第二掩模图案106定义出用于将交界区III相应的接触孔102b和紧挨该交界区III的核心区I中的至少一个接触孔102a的顶部相连的沟槽102d。以第二掩模图案106为掩模，刻蚀交界区III处的层间介质层，以形成将交界区III相应的接触孔102b和紧挨该交界区III的核心区I中的至少一个接触孔102a的顶部相连的沟槽102d，沟槽102d自交界区III延伸到核心区I，沟槽102d至少暴露出交界区III的一个接触孔102b和紧挨交界区III的核心区I的最外侧的一个接触孔102a。
请参考图2D，可以使用氧、臭氧或紫外线的灰化工艺或者通过湿式清洗工艺去除接触孔102a～102c、102d中的牺牲层105以及第二掩模图案106，以重新暴露出各个接触孔102a～102c和沟槽102d。
请继续参考图2D，可以在接触孔102a～102c和沟槽102d中形成阻挡金属层(未图示)，例如，阻挡金属层可以以均匀的厚度覆盖接触孔和沟槽的内壁与层间介质层102的顶表面。阻挡金属层能够减少或防止设置在接触孔和沟槽中的金属材料扩散到层间介质层102中。例如，所述阻挡金属层可以由Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或它们的任何组合形成，可以使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)等工艺形成。然后，在各个接触孔102a～102c和沟槽102d中填充金属层，以形成接触插塞103a、103b、103c。其中，金属层可以由(一种或多种)难熔金属(例如，钴、铁、镍、钨和/或钼)形成。另外，可以使用具有良好阶梯覆盖性质的沉积工艺形成金属层，例如，使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)形成。沉积形成的金属层还覆盖在接触孔周围的层间介质层102的表面上，之后，可以采用化学机械抛光(CMP)工艺对沉积的金属层的顶面进行化学机械抛光，直至暴露出层间介质层102的顶面，以形成位于层间介质层102中的接触插塞103a、103b、103c。此时接触插塞103b即为核心区I和交界区III中最靠近周边区II的第一个接触插 塞，且其顶部与最近邻的核心区I中的至少一个接触插塞103a相联在一起，形成倒U形接触插塞或梳状接触插塞。
图2A～图2D所示的方法，能够在相同的光刻次数下，减少沉积工艺的次数，使得顶部相联在一起的所有接触插塞一体成型。
图3A～图3D是示出图1C所示的半导体器件的电接触结构的另一种制造方法中的器件剖面示意图。请参考图3A～图3D，本实施例提供的另一种半导体器件的电接触结构的制造方法，包括以下步骤：
首先，请参照图3A，提供一半导体衬底100，其包含核心区I、周边区II以及位于核心区I和周边区II之间的交界区III。半导体衬底100中形成有多个浅沟槽隔离结构100a、100b，浅沟槽隔离结构100a在二维平面上界定出了核心区I和周边区II的交界，多个浅沟槽隔离结构100a界定出了核心区I中的各个核心元件所对应的有源区101。
接着，请继续参照图3A，在半导体衬底100上覆盖第一层间介质层102。另外，可以在半导体衬底100和第一层间介质层102之间形成蚀刻停止层(未图示)；通过第一次光刻工艺，在第一层间介质层102上形成第一掩模图案104，该第一掩模图案104定义出各个接触插塞的位置，然后，使用第一掩模图案104作为蚀刻掩模，各向异性地蚀刻第一层间介质层102，以形成贯穿所述第一层间介质层102且暴露出下方相应的有源区101的接触孔102a、102b和102c，每个接触孔102a位于核心区I中并暴露出核心区I的相应核心元件的有源区101，接触孔102b位于交界区III中且暴露出交界区III中的隔离结构100a，每个接触孔102c位于周边区II中并暴露出相应***元件的有源区101。
然后，请参考图3B，在形成接触孔102a～102c之后，可以执行灰化工艺或湿式清洗工艺，以去除第一掩模图案104，并填充TiN等材质的阻挡金属层(未图示)和钨等材质的金属层(未图示)于各个接触孔102a～102c中，并进一步采用化学机械抛光(CMP)工艺对沉积的金属层的顶面进行化学机械抛光，直至暴露出第一层间介质层102的顶面，以形成位于层间介质层102中的接触插塞103a、103b、103c，核心区I中的各个所述接触插塞103a的底部与相应的核心元件的有源区101接触，接触插塞103b的底部与交界区III 的隔离结构100a接触，周边区II中的各个所述接触插塞103c的底部与相应的***元件的有源区101接触，且所交界区III的第一个接触插塞103b的底部伸入到所述交界区III的隔离结构100a的内部且伸入深度为H1，所述接触插塞103a的底部伸入到核心区I中相应的有源区101内部且伸入深度为H2，所述接触插塞103c的底部伸入到周边区II中相应的有源区101内部且伸入深度为H2，H1小于H2。
接着，请参考图3C，可以在第一层间介质层102和接触插塞103a、103b、103c上形成第二层间介质层107和第二掩模图案108，第二掩模图案108通过第二次光刻工艺形成，定义出用于将交界区III的第一个接触插塞103b和最近邻的核心区I中的至少一个接触插塞103a的顶部相联的互连沟槽(未图示)以及位于其他接触插塞103a、103c的独立沟槽。以第二掩模图案108为掩模，刻蚀第二层间介质层107，以形成暴露出相应的接触插塞的顶部的沟槽107a、107b、107c，其中交界区III相应的沟槽107a将第一个接触插塞103b的顶部及其最近邻的至少一个接触插塞103a的顶部以及两个接触插塞之间的间隔的顶部暴露出来，核心区I的沟槽107b暴露出相应的接触插塞103a的顶部，周边区II中的沟槽107c暴露出相应的接触插塞103c的顶部。
请参考图3D，可以使用氧、臭氧或紫外线的灰化工艺或者通过湿式清洗工艺去除第二掩模图案108，并在沟槽107a～107c中依次形成阻挡金属层(未图示)和金属层(未图示)。阻挡金属层能够减少或防止设置在接触孔和沟槽中的金属材料扩散到层间介质层102中。然后，在各个接触孔沟槽107a～107c填充金属层，以形成相互独立的接触垫109a、109b、109c。各个接触垫109a形成在相应的所述核心区I的接触插塞103a的顶部，并一一对应地与相应的接触插塞103a的顶部电接触，接触垫109b形成在所述交界区III的接触插塞103b的顶部，并延伸至与交界区III的接触插塞103b最近邻的核心区I中的至少一个接触插塞103a上，并一一对应地与相应的接触插塞103a的顶部电接触，以使得交界区III中所述顶部相联一起的所有接触插塞构成倒U形电接触结构或者梳状电接触结构。
图3A～图3D所示的方法，能够在相同的光刻次数下，将每个接触插塞(包 括顶部相联在一起的接触插塞和独立的接触插塞)均分两段高度来制作，由此可以降低每段高度对应的刻蚀工艺和填充工艺所对应的接触孔或沟槽的深宽比，保证形成的电接触结构的性能。
需要说明的是，本发明的技术方案并不仅仅限定于上述的电接触结构的形成方法，能够用于形成独立的接触插塞和顶部相联在一起的接触插塞的方法均可以适用于本发明的技术方案，例如在本发明的又一示例中，在形成图2A的结构并去除掩膜图案104之后，不再填充牺牲层，而是直接填充接触插塞的材料(包括阻挡金属层和金属层)，来形成独立的接触插塞，然后在层间介质层102和独立的接触插塞上形成图2B中的第二掩膜图案106，并进一步刻蚀层间介质层102，以形成暴露出交界区III处的第一个接触插塞103b的顶部侧壁及其最近邻的核心区I中的至少一个接触插塞103a的顶部侧壁的沟槽102d，之后在沟槽102d中填充导电材料，以形成相应的接触垫(未图示)，该接触垫将沟槽102d暴露出的接触插塞103b和103a的顶部相联在一起。
在下文中，将参照图4至图13来详细描述本发明一实施例的半导体器件及其制造方法。其中图4是本发明一实施例的半导体器件的制造方法中的器件结构俯视示意图；图5～图13是本发明一实施例的半导体器件的制造方法中沿图4中的aa’线的器件结构剖面示意图。
首先，请参考图4和5，提供具有多个核心元件(即存储晶体管)的衬底300，具体过程包括：
首先，请参考图4和图5，提供一个半导体基底300a，其包含核心区I和周边区II以及位于核心区I和周边区II之间的交界区III。本实施例中，核心区I为存储区，核心区I上待形成的核心元件包括选择元件，后续在核心元件上方接数据存储元件，选择元件例如是MOS晶体管或二极管，数据存储元件例如是电容器、可变电阻器等，一个选择元件和相应的数据存储元件组成存储单元。周边区II中可形成***电路TR(例如，NMOS晶体管和PMOS晶体管、二极管或电阻器)来控制存储单元。半导体衬底300中形成有多个浅沟槽隔离结构301a、301b，该浅沟槽隔离结构301b在二维平面上界定出了核心区I和周边区II的交界，浅沟槽隔离结构301a还界定出了核心区I中的各 个核心元件所对应的有源区AA1以及周边区II中的***元件所对应的有源区AA2。其中有源区AA1在二维平面上的分布呈现条形且均沿第一方向延伸，且有源区AA1在半导体基底300a的面上可呈现错位的排列设置。
然后，在半导体基底300a中形成埋入式字线WL，埋入式字线WL一般埋设在半导体基底300a中一预定深度位置，沿第二方向(即行方向)延伸并穿过浅沟槽隔离结构301a以及有源区AA1，第二方向与有源区AA1的第一方向相交但不垂直。埋入式字线WL作为栅极来控制存储单元的开关，其包含但不限定为掺杂性的半导体材料(如掺杂硅)、金属材(如钨、铝、钛、或钽)、导电性金属化合物(如氮化钛、氮化钽、或氮化钨)、或是半导体化合物(如氮化硅)等。通常埋入式字线WL的侧壁和底部被栅介质层(未图示)包围，埋入式字线WL的顶部被栅极盖层302掩埋在内。由于埋入式字线WL并非本发明的重点，其相关制作工艺可以参考本领域的已知技术方案，在此不再详述。此外，栅介质层可包括氧化硅或其他适合的介电材料，埋入式字线WL可包括铝、钨、铜、钛铝合金、多晶硅或其他适合的导电材料，而栅极盖层302可包括氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。
再者，在埋入式字线WL两旁的有源区AA1中可掺入第二类型的掺质，如P类型或N类型的掺质，来形成源区和漏区(统一定义为S/D1)，埋入式字线WL两旁的AA1中的一者位于AA1中心处对应预定的位线接触结构的位置，另一者位于有源区AA1末端对应预定的存储节点接触结构的位置。字线WL和S/D1可以构成或限定形成在半导体器件的核心区I上的多个MOS存储晶体管。此外，在形成S/D1的同时，也可以一并在周边区II中形成***晶体管对应的源区和漏区(统一定义为S/D2)。在形成所述S/D1和S/D2之后，还可进一步形成刻蚀停止层303在所述半导体基底300a上，所述刻蚀停止层303覆盖所述S/D1和S/D2，其材料例如包括氮化硅(SiN)和/或氧化硅(SiO 2)等。
然后，在核心区I的用作漏区的S/D1上形成多个位线接触插塞(bit line contact，未图示)以及位于所述位线接触插塞上方的位线BL，位线接触插塞可以通过如下方法形成：先刻蚀一个有源区AA1中的且位于相邻两条WL之间 的S/D1来形成凹槽，之后在凹槽中形成金属硅化物。多条位线BL相互平行且沿着垂直于埋入式字线WL的第三方向(即列方向)延伸，并同时横跨该有源区AA1与埋入式字线WL。各位线BL例如包含依序堆叠的一半导体层(例如多晶硅，未图示)、一阻障层(例如包括Ti或TiN等，未图示)、一金属层(例如钨、铝或铜等，未图示)与一掩模层(例如包含氧化硅、氮化硅或碳氮化硅，未图示)。
此外，在半导体基底300a的周边区II上，则形成有至少一栅极结构G1，其例如包含依序堆叠的一栅极介电层(未图示)和一栅极层(未图示)。在一具体示例中，栅极结构G1的栅极层与位线BL的半导体层或金属层一并形成。进一步地，可采用不同工艺或同道工艺形成分别环绕各位线BL与栅极结构G1的侧墙304。举例来说，可先进行栅极结构G1的侧墙的制作工艺，使栅极结构G1的侧墙304包含氧化硅或氮氧化硅(SiON)，再进行位线BL的侧墙的制作工艺，而使位线BL的侧墙可包含氮化硅。此外，在栅极结构G1的侧墙的制作工艺中，可再进行一回蚀刻(etching back)制作工艺，使栅极结构G1的整体高度低于各位线BL。
然后，可以在采用本发明的图1A～图1C所示的半导体器件的电接触结构的基础上形成存储节点接触结构，下面以采用图2A～2D所示的半导体器件的电接触结构的制作方法的基础上形成存储节点接触结构为例，具体过程如下：
首先，请参考图6，在提供具有位线BL、核心元件的源区和漏区S/D1的半导体衬底300之后，在半导体衬底300上形成一层间介质层400，其材质例如包括氧化硅、氮化硅或低K介质等。具体地，先通过沉积工艺全面地在半导体衬底300上覆盖层间介质层400，并使得层间介质层400填满各位线BL之间的空间并将各位线BL与栅极结构G1及其侧墙304掩埋在内，然后通过化学机械研磨等工艺对层间介质层400进行平坦化，形成整体上具有平坦的顶表面的层间介质层400。其中，平坦化后的层间介质层400的顶表面至少不低于各位线BL的顶表面。
接着，请参照图6，通过光刻工艺，在层间介质层400上形成第一掩模图案(未图示)，该第一掩模图案定义出各个存储节点接触结构的位置，然后， 使用第一掩模图案作为蚀刻掩模，各向异性地蚀刻层间介质层400，以形成贯穿所述层间介质层400且暴露出下方相应的用作源区的S/D1的接触孔401a和401e，以及暴露出下方浅沟槽隔离结构301a的401b和暴露出下方栅极结构G1的401d，每个接触孔401a位于核心区I中并暴露出核心区I中相应核心元件的用作源区的S/D1的顶面且伸入到相应的用作源区的S/D1中一定深度(如图1B中的H2)，接触孔401b位于交界区III且暴露出交界区III中的隔离结构301a的顶面并伸入到隔离结构301a中一定深度(如图1B中的H1，H1小于H2)，每个接触孔401d、401e位于周边区II中并暴露出相应***元件的源区/漏区S/D2或栅极结构G1。
然后，请参考图7，在形成接触孔401a、401b和401d、401e之后，可以执行灰化工艺或湿式清洗工艺，以去除第一掩模图案，并填充牺牲层402于各个接触孔401a、401b和401d、401e中。所述牺牲层402可以由旋涂硬掩模层(SOH)或非晶碳层(ACL)形成，这样可以使得能够用牺牲层402填充具有高的高宽比的接触孔401a、401b和401d、401e。
接着，请继续参考图7，可以在层间介质层400和牺牲层402上形成第二掩模图案(未图示)，第二掩模图案定义出用于将交界区III相应的接触孔401b的顶部和与其最近邻的核心区I中的至少一个接触孔401a的顶部相连通的沟槽401c。以第二掩模图案为掩模，刻蚀交界区III的层间介质层400，以形成将交界区III相应的第一个接触孔401b的顶部和与其最近邻的核心区I中的至少一个接触孔401a的顶部相连的沟槽401c。沟槽401c可以与位线BL平行。
然后，请参考图7和图8，可以使用氧、臭氧或紫外线的灰化工艺或者通过湿式清洗工艺去除接触孔401a、401b和401d、401e中的牺牲层402以及第二掩模图案，以重新暴露出各个接触孔401a、401b、401d、401e和沟槽401c。
接着，请参考图9，可以在接触孔401a、401b、401d、401e和沟槽401c中形成阻挡金属层(未图示)，例如，阻挡金属层可以以均匀的厚度覆盖接触孔401a、401b、401d、401e和沟槽401c的内壁与层间介质层400的顶表面。阻挡金属层能够减少或防止设置在接触孔401a、401b、401d、401e和沟槽401c中的金属材料扩散到层间介质层400中。例如，所述阻挡金属层可以 由Ta、TaN、TaSiN、Ti、Ti N、TiSiN、W、WN或它们的任何组合形成，可以使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)等工艺形成。然后，在各个接触孔401a、401b、401d、401e和沟槽401c中填充金属层，以形成接触插塞501a、501d、501e和组合接触结构501b。其中，金属层可以由(一种或多种)难熔金属(例如，钴、铁、镍、钨和/或钼)形成。另外，可以使用具有良好阶梯覆盖性质的沉积工艺形成金属层，例如，使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)形成。形成的金属层还覆盖在接触孔和沟槽周围的层间介质层400的表面上，之后，可以采用化学机械抛光(CMP)工艺对沉积的金属层的顶面进行化学机械抛光，直至暴露出层间介质层400的顶面，以形成位于层间介质层400中的接触插塞501a、501d、501e和组合接触结构501b。接触插塞501a作为核心区I中的存储节点接触结构，用于与后续在核心区I上方形成的电容器连接。组合接触结构501b由交界区III中的第一个接触插塞和其最近邻的至少一个接触插塞501a(即核心区I最靠近交界区III中的至少一个接触插塞501a)的顶部相联在一起形成，作为核心区I边界和交界区III中的存储节点接触结构，用于与后续在核心区I边界和交界区III上方形成的电容器连接，组合接触结构501b可以与位线BL对准平行。组合接触结构501b例如为倒U形电接触结构或者梳状电接触结构，其最靠近核心区I的一侧还可以与核心区I最外侧的一个有源区AA1中的一条所述字线WL接触。接触插塞501d作为周边区II的栅极结构G1的接触结构，用于将栅极结构G1向外引出，接触插塞501e作为周边区II的源区或漏区S/D2的接触结构，用于将周边区II的源区或漏区S/D2向外引出。
之后，可以采用本领域常规的电容器的制作方法来在核心区I和交界区III上制作相应的电容器，请参考图10～13，具体过程如下：
首先，请参考图10，可以通过化学气相沉积、旋涂等工艺在所述层间介质层400和接触插塞501a、501d、501e及组合接触结构501b的表面上依次形成底层支撑层600、第一牺牲层611、中间支撑层601、第二牺牲层612以及顶层支撑层602，其中底层支撑层600一方面用于对后续形成的下电极层进行 底部支撑，另一方面还用于隔离半导体衬底300的内部元件与上方的电容器等元件。底层支撑层600的形成工艺还可以是热氧化工艺。所述底层支撑层600、中间支撑层601和顶层支撑层602的材质包含但不限于氮化硅，第一牺牲层611、第二牺牲层612的材质包含但不限于氧化硅。所述第一牺牲层611的厚度界定出后续所形成的中间支撑层601的高度，因此，所述第一牺牲层611的厚度可根据所需形成的中间支撑层601的高度位置进行调整。在所述第一牺牲层611与中间支撑层601的厚度确定的情况下，所述第二牺牲层612的厚度界定出后续所形成的顶层支撑层602的高度，因此，所述第二牺牲层612的厚度可根据所需形成的顶层支撑层602的高度位置进行调整。在本发明的其他实施例中，为了对下电极层进行更好的支撑，底层支撑层600和顶层支撑层602之间还可以层叠两层以上的中间支撑层601，相邻中间支撑层之间有牺牲层进行隔离。
接着，请参考图11所示，形成多个电容孔700a和700b在所述核心区I上的牺牲层与所述支撑层内，每个电容孔700a形成在核心区I中且暴露出所述核心区I中相应的接触插塞501a的表面，用于形成核心区I中的电容器。电容孔700b形成在核心区I边界和交界区III上且暴露出从所述交界区III跨到核心区I边界的组合接触结构501b的表面，用于形成跨在核心区I边界和交界区III上的电容器。电容孔700a和700b呈阵列排布，且电容孔700b具有第一宽度W1，电容孔700a具有第二宽度W2，可选地，W1>W2，例如W1为1.3*W2～2.3*W2。具体的，在所述顶层支撑层602上形成一掩模层(未图示)，对所述掩模层进行图形化，暴露出预定形成电容孔700a和700b的区域，然后以图形化的掩模层为掩模，依次对所述顶层支撑层602、第二牺牲层612、中间支撑层601、第一牺牲层611以及底层支撑层600进行刻蚀，以去除所述周边区II及核心区I边缘区域上的所述支撑层及牺牲层，并在核心区I和交界区III中形成多个电容孔700a和700b，然后去除所述图形化的掩模层。所述电容孔700a和700b依次贯穿所述顶层支撑层602、第二牺牲层612、中间支撑层601、第一牺牲层611以及底层支撑层600，以暴露出所述核心区I的相应的接触插塞501a和交界区III的组合接触结构501b的表面，可选的， 所有的电容孔呈六方密堆积排布。此外，电容孔可以是倒梯形孔、矩形孔等，其侧壁可以是不规则形貌，如具有曲线侧壁等，在此不做具体限制。此外，本实施例中，周边区II上还保留有所述底层支撑层600，以用于在后续电容器形成工艺中保护周边区II的器件表面。
可以理解的是，由于组合接触结构501b的面积较大，因此可以为位于核心区I的边界和交界区III上的电容孔700b的制作提供足够的工艺余量，且使得电容孔700b的宽度较大，避免电容孔700b发生异常变形或坍塌，同时使得后续在该电容孔700b中形成的电容器和所述组合接触结构501b具有较大的接触面积，进而降低接触阻抗，有利于提高器件的电学性能。此外，因为交界区III的电容孔700b的宽度较大，能够缓冲周边区II和核心区I中的电路图案的密度差异，从而在执行电容孔的光刻工艺和/或蚀刻工艺时能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区的各个电容孔的一致性，防止出现核心区内一些位置的接触插塞上方的电容孔出现异常而引起后续形成的电容器失效的问题。
请参考图12所示，形成一下电极层701覆盖于所述电容孔700a、700b的侧壁和底壁上。所述下电极层701位于所述电容孔700a、700b中的部分，其形貌与所述电容孔700a、700b的形貌一致，从而使得位于所述电容孔700a、700b中的所述下电极层701构成一筒状结构。具体的，所述下电极层701可在沉积工艺的基础上结合平坦化工艺形成，例如，首先，可以采用光刻胶等图形化保护层(未图示)将周边区II保护起来，并暴露出核心区I中的顶层支撑层602的顶表面以及电容孔700a、700b的表面；接着，采用物理气相沉积或化学气相沉积等工艺形成一电极材料层于所述图形化保护层以及核心区I的暴露表面上，所述电极材料层覆盖所述电容孔700a、700b的底部和侧壁，以及覆盖所述核心区I的顶层支撑层602和周边区II的图形化保护层顶表面；接着，执行平坦化工艺(例如，化学机械研磨工艺CMP)，去除电极材料层中位于所述顶层支撑层602上方的部分，从而使剩余的电极材料层仅形成在所述电容孔700a、700b中，以构成具有多个筒状结构的下电极层701，之后去除所述图形化保护层。此外，在本实施例中，所述接触插塞501a、501b分别 通过所述电容孔700a、700b暴露出来，从而使得所形成的下电极层701的筒状结构的底部能够与所述接触插塞501a、501b电性接触。进一步的，所述下电极层701可以是多晶硅电极或金属电极。当下电极层701为金属电极时，还可以采用氮化钛(TiN)和Ti层叠结构。当下电极层701为多晶硅电极时，可以采用零掺杂和/或掺杂的多晶硅材料形成。
请继续参考图12所示，去除各个所述的牺牲层并保留各个所述的支撑层，所有的所述支撑层组成横向支撑层，以横向连接所述下电极层701的多个筒状结构的外壁，以在各个所述筒状结构的侧壁上对下电极层701进行支撑。具体的，所述顶层支撑层602位于所述下电极层701的多个筒状结构的顶部***，所述中间支撑层601位于所述下电极层701的多个筒状结构的中间部位，底层支撑层600位于所述下电极层701的多个筒状结构的底部***。其中，具体过程包括：形成第一开口(未图示)于所述顶层支撑层602并暴露出所述第二牺牲层612；可以采用湿法刻蚀工艺刻蚀去除所述第二牺牲层612；形成第二开口于所述中间支撑层601中以暴露出所述第一牺牲层611；采用湿法刻蚀工艺刻蚀去除所述第一牺牲层611；其中，一个所述第一开口仅与一个所述电容孔700a或700b交叠，或者一个所述第一开口同时与多个所述电容孔700a和/或700b交叠；一个所述第二开口仅与一个所述电容孔700a或700b交叠，或者一个所述第二开口同时与多个所述电容孔700a和/或700b交叠。此外，所述第二开口可以与所述第一开口完全对齐。
请参考图13所示，采用化学气相沉积工艺或原子层沉积工艺等形成一电容介质层702于所述下电极层701的内外表面以及各个所述支撑层暴露出的表面；接着，形成一上电极层703于所述电容介质层702的内表面和外表面。其中，所述电容介质层702覆盖所述下电极层701的筒状结构的内表面和外表面，以充分利用下电极层701的两个相对表面，构成具有较大电极表面积的电容器。优选的，所述电容介质层702可以为金属氧化物等高K介质层。进一步的，所述电容介质层702为多层结构，例如为氧化铪-氧化锆的两层结构。所述上电极层703可以为单层结构也可以为多层结构，当所述上电极层703为单层结构时，例如为多晶硅电极，也可以为金属电极，当上电极层703 为金属电极时，例如可以采用氮化钛(TiN)形成。所述上电极层703在对应所述筒状结构的内部和所述筒状结构的外部均能够与所述电容介质层702以及所述下电极层701构成电容器。此外，在核心区I边缘区域(即电容孔阵列的边界区域)上，由于横向支撑层(即中间支撑层601、顶层支撑层602)的存在，所述电容介质层702和所述上电极层703均具有凹凸不平形貌的侧壁结构，所述凹凸不平形貌的侧壁结构对应于在所述下电极层701的筒状结构筒外部的所述中间支撑层601、顶层支撑层602，由此使得所述上电极层703在所述核心区I边缘区域(即电容孔阵列的边界区域)上的部分，对应所述中间支撑层601、顶层支撑层602以远离所述下电极层701的方向凸出，使核心区I中的电容器阵列边界不平整。此外，本实施例中，所述电容介质层702和所述上电极层703还依次延伸覆盖在所述周边区II上保留的底层支撑层600的表面上。
请参考图13所示，可以先采用化学气相沉积工艺在所述上电极层703表面形成一上电极填充层704，所述上电极填充层704填满所述上电极层703之间的间隙，也就是说，所述上电极填充层704填充满相邻的筒状结构之间的间隙并覆盖上述形成的结构。优选的，所述上电极填充层704的材质包括未掺杂或者硼掺杂的多晶硅。由此完成了电容器阵列的制作，即在核心区I中形成了多个电容器705a，在核心区I边界和交界区III上形成电容器705b。
由于电容孔700b的宽度大于电容孔700a的宽度，因此所述电容器705b的宽度(即W1)大于核心区I中各个电容器705a的宽度(即W2)，例如W1＝1.3*W2～2.3*W2，作为一种示例，W1＝W2*1.5。且由于电容孔700b的尺寸较大，有利于材料填充，进而改善了所述电容器705b的性能。
本实施例的半导体器件的制造方法中，通过组合接触结构501b使得其上接的电容器705b的尺寸增大，能够缓冲核心区和周边区之间的电路图案的密度差异，从而在形成核心区中的所有电容器的光刻工艺和/或蚀刻工艺中能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区中的接触插塞上方的电容器的一致性，提高器件性能。此外，电容器705b和组合接触结构501b有较大的接触面积，从而降低接触阻抗，有利于提高器件的电学性能。
在本发明的其他实施例的半导体器件的制造方法中，当交界区III形成的第一接触插塞501b完全重叠在与交界区III的隔离结构300a上时，请结合图1A和图13，可以使得原先从交界区III横向延伸到核心区I最外侧上的电容器705b完全形成于交界区III的隔离结构300a上方并作为虚拟结构，进而通过该虚拟结构保证核心区I的接触插塞501a上接的电学结构705a的一致性；当交界区III形成的第一接触插塞501b的一部分底部与交界区III的隔离结构300a重叠，另一部分底部与紧挨交界区III的隔离结构300a的核心区I的有源区301重叠时，请结合图1B和图13，交界区III形成的第一接触插塞501b的顶部横截面积相对增大，也为后续在第一个接触插塞501b上方形成电容器705b的工艺提供足够的工艺余量，有利于该交界区III的所述电容器705b的尺寸增大，避免该电容器705b出现异常或坍塌；另一方面，能够使得电容器705b和第一个接触插塞501b有较大的接触面积，从而降低接触阻抗，有利于提高器件的电学性能；更重要的是，通过第一个接触插塞501b使得其上接的电容器705b的尺寸增大，能够缓冲核心区I和周边区II之间的电路图案的密度差异，从而在形成核心区I中的所有电容器705a的光刻工艺和/或蚀刻工艺中能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区I中的接触插塞501a上方的电容器705b的一致性，提高器件性能。
接着，请参考图14～图16，本发明一实施例提供一种掩模板组合，用于制作接触插塞，所述掩模板组合包括：第一掩模板10、第二掩模板20以及第三掩模板30。
请参考图14，所述第一掩模板10具有多条平行的第一遮光条纹，相邻的两条第一遮光条纹之间为第一透光区112。本实施例中，所述第一掩模板10的边界处(即沿第一遮光条纹排布方向的边界处)的第一条第一遮光条纹111a具有第一宽度K1，第二条第一遮光条纹111b的宽度小于K1，其余的第一遮光条纹111c具有第二宽度K2，所述第一宽度K1大于所述第二宽度K2，例如K1>1.5*K2，且第二条第一遮光条纹111b的宽度大于K2，由此在将第一掩模板10上的图案转移到相应的膜层上的光刻、刻蚀工艺中，可以利用第一掩模板10中的第一条第一遮光条纹111a、第二条第一遮光条纹111b以及其 余的第一遮光条纹111c的宽度渐变性，来改善半导体器件的核心区和周边区之间的图案密集/稀疏效应，提高第一掩模板10图案转移效果。在本发明的其他实施例中，第二条第一遮光条纹111b的宽度可以等于第一条第一遮光条纹111a的宽度。此外，可选地，第一条第一遮光条纹111a、第二条第一遮光条纹111b之间的第一透光区112的宽度大于其余的第一透光区112的宽度，由此有利于为半导体器件的核心区边界处的接触插塞的制作提供足够的工艺余量。
请参考图15，所述第二掩模板20具有多条平行且与每条第一条纹111a、111b、111c垂直相交的第二遮光条纹201，相邻的两条第二遮光条纹201之间为第二透光区202。图15中示出的第二遮光条纹201的宽度基本相同，但是在本发明的其他实施例中，可选地，所述第二掩模板20的边界处(即沿第二遮光条纹排布方向的边界处)的至少一条第二遮光条纹(未图示)具有第三宽度(未图示)，其余的第二遮光条纹具有第四宽度(未图示)，所述第三宽度大于所述第四宽度，例如述第三宽度大于1.5倍的所述第四宽度，由此在将第二掩模板20上的图案转移到相应的膜层上的光刻、刻蚀工艺中，可以利用第二掩模板20中第二遮光条纹的宽度渐变性，来改善半导体器件的核心区和周边区之间的图案密集/稀疏效应，提高第二掩模板20的图案转移效果。在本发明的其他实施例中，可选地，第二掩模板20的边界处的(即沿第二遮光条纹排布方向的边界处)第一条第二遮光条纹、第二条第二遮光条纹之间的第二透光区202的宽度大于其余的第二透光区202的宽度，由此有利于为半导体器件的核心区边界处的接触插塞的制作提供足够的工艺余量。
请参考图16，所述第三掩模板30具有遮光块311和与遮光块311互补的第三透光区312。所述遮光块311可以具有面向核心区的锯齿状边缘，以用于掩蔽核心区边界处的部分待形成接触孔的区域。
需要说明的是，图14～图16分别仅仅示出了第一掩模板10、第二掩模板20以及第三掩模板30的一个角落区域的图案，本领域技术人员应当能够根据图14至图16显示的区域进行相应的延展而得到基本上呈矩形的完整掩模板。此外，所述遮光块311在完整的第三掩模板30上呈封闭的环状结构或者具有 至少一个开口的非封闭的环状结构，所述遮光块311面向第三掩模板30中心的锯齿状边缘不对称，即第三掩模板30上侧和下侧的遮光块311不对称，第三掩模板30左侧和右侧的遮光块311不对称。
请参考图17C和图18，当本实施例的掩模板组合用于在一具有核心区I、交界区III和周边区II的半导体衬底上制作接触插塞时，所述遮光块311覆盖所述第一掩模板10的边界处的至少一条第一遮光条纹和该条第一遮光条纹最近邻的部分第一透光区，以及，覆盖所述第二掩模板20的边界处的至少两条第二遮光条纹201以及所述两条第二遮光条纹之间的部分第二透光区202。且，第三透光区312、第一透光区112和第二透光区202与核心区I的重叠区域为形成接触插塞的区域CT。可选地，根据第一遮光条纹的形状、第二遮光条纹的形状，所形成接触插塞的区域CT的形状包括正方形、圆形、椭圆形、三角形、矩形、多边形和心形中的至少一种。
此外，为了尽可能地兼顾器件密度以及性能、合格率等问题，所述遮光块311覆盖的第二遮光条纹201的数量为所述遮光块311覆盖的第一遮光条纹的数量的2～5倍。
请参考图14～16、图17A～17C以及图18～19，本发明一实施例还提供一种接触插塞制作方法，所述接触插塞制作方法使用本发明所述的掩模板组合来实现，具体包括以下步骤：
首先，请参考图17A和图19，提供具有多个有源区AA1的半导体衬底410，在所述半导体衬底410上依次形成层间介质层500和第一掩模层P1，其中，半导体衬底410还具有核心区I、周边区II以及位于核心区I和周边区II之间的交界区III，核心区I中形成有限定各个有源区AA1的浅沟槽隔离结构411b，交界区III中形成有限定核心区I和周边区II的浅沟槽隔离结构411a，第一掩模层P1的材料可以是氧化硅、氮化硅或氮氧化硅等。
接着，请参考图14、图17A和图19，通过采用光刻结合刻蚀的工艺，将所述掩模板组合中的第一掩模板上的图案转移到所述第一掩模层P1上，即利用第一掩模板10图案化第一掩模层P1。具体地，首先在第一掩模层P1上依次覆盖底部抗反射层(未图示)和光刻胶层(未图示)，并采用所述第一掩模 板10对所述光刻胶层进行曝光和显影，以将第一掩模板10上的图案转移到第一掩模层P1上，之后可以去除所述底部抗反射层和光刻胶层。其中，图案化后的第一掩模层P1中形成有多条第一线条，其中，每条第一线条对应第一掩模板10上相应的第一遮光条纹，相邻第一线条之间的沟槽(未标示)对应第一掩模板10上相应的第一透光区112并暴露出相应的层间介质层500。具体地，例如核心区I的边界处(即核心区I沿第一线条排布方向的边界处)的最外侧的第一条第一线条P11对应第一掩模板10的边界处的第一条第一遮光条纹111a，第二条第一线条P12对应第一掩模板10的边界处的第二条第一遮光条纹111b，其余的第一线条P10对应第一掩模板10内部的其余第一遮光条纹111c。
然后，请参考图15、图17B和图19，在第一掩模层P1和层间介质层500上覆盖第二掩模层P2，并采用光刻结合刻蚀的工艺，将所述掩模板组合中的第二掩模板20上的图案转移到第二掩模层P2上，以形成相应的多条第二线条P20，即利用第二掩模板20图案化第二掩模层P2。具体工艺与采用第一掩模板图案化第一掩模层P1的工艺基本相同，在此不再详述。其中，每条第二线条P20对应第二掩模板20上相应的第二遮光条纹201，相邻第二线条P20之间的沟槽(未标示)对应第二掩模板20上相应的第二透光区202，每条第二线条P20均与所有的第一线条P11、P12、P10垂直相交并在其线宽区域中覆盖在这些第一线条P11、P12、P10及相邻的第一线条之间的沟槽的相应部分，且相邻第二线条P20之间的沟槽暴露出该沟槽宽度区域内相应的第一线条P11、P12、P10以及相邻的第一线条之间的沟槽中的层间介质层500。此时所有的第一线条和第二线条交叠，限定出呈棋盘状排布的沟槽CTa(未标示)。其中，第二掩膜层P2的材质不同于第一掩膜层P1的材质，以使得上述的刻蚀工艺能够保留相邻第二线条之间的第一线条。
接着，请参考图16、图17C和图19，在第二掩模层P2、第一掩膜层P1和层间介质层500上覆盖第三掩模层P3，其中，第三掩模层P3的材质不同于第二掩膜层P2的材质和第一掩膜层P1的材质，以使得后续图案化第三掩模层P3后能够保留其暴露出的第一线条和第二线条，可选地，第三掩模层P3 的材料为光刻胶；采用光刻工艺将所述掩模板组合中的第三掩模板30上的图案转移到所述第三掩模层P3上，即利用第三掩模板30图案化第三掩模层P3，剩余的第三掩模层P3(即图案化后的第三掩模层P3)对应第三掩模板30的遮光块311，剩余的第三掩模层P3和剩余的第二掩模层P2、第一掩膜层P1共同暴露出的沟槽CTa区域(即暴露出的层间介质层500区域)为待形成接触插塞的区域。剩余的第三掩模层P3将交界区III上的第一线条和第二线条相交限定出的沟槽均覆盖，将核心区I各个方向上的边界处最外侧的第一线条和第二线条相交限定出的部分沟槽覆盖。此外，需要说明的是，本实施例中，所述字线WL可以与所述第二线条P20重叠，所述第一线条P10～P12可以相应的与所述位线BL重叠。因此，第一掩模板10可以是位线掩模板，第二掩模板20可以是字线掩模板。
接着，请参考图17C、图18和图19，以剩余的第三掩模层P3、第二掩模层P2、第一掩膜层P1为掩模，刻蚀暴露出的层间介质层500，至暴露出半导体衬底410中的有源区AA1，以形成暴露出相应的有源区AA1的接触孔。本实施例中，因为第三掩模层P3的掩蔽作用，使得核心区I沿第一线条的排布方向的边界处的部分有源区AA1上有接触孔(如图18中aa’线上的实线边框的方块CT所示)，另一部分有源区AA1上无接触孔(如图18中aa’线上的虚线边框的方块dCT所示)。
之后，请参考图18和图19，在各个所述接触孔中形成接触插塞CT，各个所述接触插塞CT的底部与相应的有源区AA1接触。从图19中可以看出，在核心区I的沿第一线条或第二线条的长度延伸方向上的边界处的部分有源区AA1上方无接触插塞，如图19中的dCT所示。此外，在一些实施例中，核心区I相对两侧的边界处的接触插塞CT不对称分布，例如核心区I上侧边界处和下侧边界处的接触插塞不对称分布，和/或，核心区I左侧边界处和右侧边界处的接触插塞不对称分布。从本发明的接触插塞制作方法中可以看出，调整第三掩模板的遮光块的形状和大小，可以调整图案化后的第三掩模层覆盖的第一线条和第二线条相交限定出的沟槽的位置，从而达到使核心区的边界处的某些特殊位置的有源区上方无接触插塞的要求。由此，在实际生产过 程中，可以根据历史生产数据来收集核心区边界处易出问题的区域，使得这些区域中不再形成接触插塞，从而使得这些区域中原先的接触插塞位置上接的电学结构(例如电容器或电阻器等)成为虚拟结构，在后续的良率测试等测试中不参与测试，进而可以提高测试通过率，最终达到提高产品合格率的目的。
下面以半导体器件为动态随机存储器为例，并结合图14～16、图17A～17C以及图18和图20，来详细说明如何通过上述的接触插塞的制作方法来制作本发明的半导体器件。即本发明的半导体器件的制作方法，具体包括以下过程：
首先，请参考图17A和图20，提供具有多个核心元件(即存储晶体管)的半导体衬底410，具体过程包括：首先，提供一个半导体基底410a，其包含核心区I和周边区II以及交界区III。本实施例中，核心区I为存储区，核心区I上待形成的核心元件包括选择元件，后续在核心元件上方接数据存储元件，选择元件例如是MOS晶体管或二极管，数据存储元件例如是电容器、可变电阻器等，一个选择元件和相应的数据存储元件组成存储单元。周边区II中可形成***电路(例如，NMOS晶体管和PMOS晶体管、二极管或电阻器)来控制存储单元。核心区I的半导体基底410a中形成有多个浅沟槽隔离结构411b，交界区III的半导体基底410a中形成有浅沟槽隔离结构411a，浅沟槽隔离结构411a在二维平面上界定出了核心区I和周边区II的分界处，浅沟槽隔离结构411b界定出了核心区I中的各个核心元件所对应的有源区AA1。其中有源区AA1在二维平面上的分布呈现条形且均沿第一方向延伸，且有源区AA1在半导体基底410a的面上可呈现错位的排列设置。然后，在半导体基底410a中形成埋入式字线WL，埋入式字线WL一般埋设在半导体基底410a中一预定深度位置，沿第二方向(即行方向)延伸并穿过浅沟槽隔离结构411b以及有源区AA1，第二方向与有源区AA1的第一方向相交但不垂直。埋入式字线WL作为栅极来控制存储单元的开关，通常埋入式字线WL的侧壁和底部被栅介质层(未图示)包围，埋入式字线WL的顶部被栅极盖层412掩埋在内。由于埋入式字线WL并非本发明的重点，其相关制作工艺可以参考本领域的已知技术方案，在此不再详述。此外，栅介质层可包括氧化硅或其他 适合的介电材料，埋入式字线WL可包括铝、钨、铜、钛铝合金、多晶硅或其他适合的导电材料，而栅极盖层412可包括氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。再者，在埋入式字线WL两旁的有源区AA1中可掺入第二类型的掺质，如P类型或N类型的掺质，来形成源区和漏区(统一定义为S/D)，埋入式字线WL两旁的AA1中的一者位于AA1中心处对应预定的位线接触结构的位置，另一者位于有源区AA1末端预定的存储节点接触结构的位置。字线WL和S/D可以构成或限定形成在半导体器件的核心区I上的多个MOS存储晶体管。此外，在形成S/D的同时，也可以一并在周边区II中形成***晶体管对应的源区和漏区(未图示)。在形成所述S/D之后，还可进一步形成刻蚀停止层413在所述半导体基底410a上，所述刻蚀停止层413覆盖所述S/D和浅沟槽隔离结构411a、411b，其材料例如包括氮化硅(SiN)和/或氧化硅(SiO 2)等。然后，在核心区I的用作漏区的S/D上形成多个位线接触插塞(bit line contact，未图示)以及位于所述位线接触插塞上方的位线BL，位线接触插塞可以通过先刻蚀一个有源区AA1中形成的相邻两条WL之间的S/D来形成凹槽，之后在凹槽中形成金属硅化物的方法来形成。多条位线BL相互平行且沿着垂直于埋入式字线WL的第三方向(即列方向)延伸，并同时横跨该有源区AA1与埋入式字线WL。各位线BL例如包含依序堆叠的一半导体层(例如多晶硅，未图示)、一阻障层(例如包括Ti或TiN等，未图示)、一金属层(例如钨、铝或铜等，无图示)与一掩模层(例如包含氧化硅、氮化硅或碳氮化硅，未图示)。
然后，请参考图17A和图20，在提供具有位线BL、核心元件的源区和漏区S/D的半导体衬底410之后，在半导体衬底410上形成一层间介质层500，其材质包括氧化硅、氮化硅或低K介质等。具体地，先通过沉积工艺全面地在半导体衬底410上覆盖层间介质层500，并使得层间介质层500填满各位线BL之间的空间并将各位线BL掩埋在内，然后通过化学机械研磨等工艺对层间介质层500进行平坦化，形成整体上具有平坦的顶表面的层间介质层500。其中，平坦化后的层间介质层500的顶表面至少高于各位线BL的顶表面。
接着，请参照图14～图16、图17A～图17C、图18以及图20，通过上述 的接触插塞的制作方法，在层间介质层500上依次形成具有第一掩模板10的图案的第一掩模层P1、具有第二掩模板10的图案的第二掩模层P2、具有第三掩模板30的图案的第三掩模层P3，具体工艺可以参考上文所述，在此不再详述。其中，第二掩模层P2形成在第一掩模层P1及其暴露出的层间介质层500上，第三掩模层P3形成在第二掩模层P2及其暴露出的第一掩模层P1和层间介质层500上，第一掩模层P1中的第一线条和第二掩模层P2中的第二线条垂直相交并限定出一些呈棋盘状排布的沟槽，第三掩模层P3对交界区III中的所有所述沟槽以及核心区I边界处的部分沟槽进行掩蔽，以定义出各个有效的存储节点接触结构的位置。
然后，请继续参照图17C、图18以及图20，以第三掩模层P3、第二掩模层P2和第一掩模层P1为掩模，各向异性地蚀刻层间介质层500，以形成贯穿所述层间介质层500且暴露出下方相应的用作源区的S/D的接触孔，此时可以同时形成暴露出周边区II中的相应区域的接触孔(未图示)。在核心区I的边界处的接触孔的尺寸可以大于核心区I内部的接触孔的尺寸。在本发明的其他实施例中，可以在交界区III靠近核心区I的边界处的区域中也形成接触孔，在后续交界区III中的接触孔中的接触插塞可以与核心区I的边界处的相应的接触插塞的顶部相联在一起。
接着，请继续参照图18和图20，在形成接触孔之后，可以执行灰化工艺或湿式清洗或其他合适的工艺，以去除层间介质层500上方的第三掩模层P3、第二掩模层P2和第一掩模层P1，并在各个接触孔中依次填充阻挡金属层(未图示)和导电金属层(未图示)，所述阻挡金属层可以以均匀的厚度覆盖接触孔的内壁与层间介质层500的顶表面，阻挡金属层能够减少或防止设置在接触孔中的金属材料扩散到层间介质层500中，其可以由Ta、TaN、TaSiN、Ti、Ti N、TiSiN、W、WN或它们的任何组合形成，可以使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)等工艺形成；导电金属层可以由(一种或多种)难熔金属(例如，钴、铁、镍、钨和/或钼)形成。另外，可以使用具有良好阶梯覆盖性质的沉积工艺形成导电金属层，例如，使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如， 溅射)形成。形成的导电金属层还覆盖在接触孔周围的层间介质层500的表面上，之后，可以采用化学机械抛光(CMP)工艺对沉积的导电金属层的顶面进行化学机械抛光，直至暴露出层间介质层500的顶面，以形成位于层间介质层500中的接触插塞CT。图20中显示出了核心区I边界处的部分有源区AA1上方无接触插塞(对于这些位置，现有技术中会形成接触插塞，而本发明中不会形成，即在图20中用于虚线框柱dCT来形成对比)，另一部分有源区AA1上方有接触插塞CT。接触插塞CT作为核心区I中的存储节点接触结构，用于与后续在核心区I上方形成的电容器连接。
之后，请继续参照图20，可以采用本领域常规的电容器的制作方法来在核心区I上制作相应的电容器，具体过程在此不再详述。核心区I的每个S/D上方均形成有一个电容器705，在核心区I的边界处，底部通过相应的接触插塞CT与相应的S/D电连接的电容器705为有效的电容器，后续参与测试以及器件运作，而底部与相应的S/D之间没有接触插塞CT的电容器为虚拟电容器，后续不再参与器件相关测试以及器件运作，由此，提高了产品的合格率。本实施例中，每个电容器705包括下电极层701、电容介质层702以及上电极层703，电容器705之间具有横向支撑且间隔式层叠的底层支撑层600、中间支撑层601以及顶层支撑层602，其中底层支撑层600一方面用于对后续形成的下电极层进行底部支撑，另一方面还用于隔离半导体衬底410的内部元件与上方的电容器等元件。底层支撑层600的形成工艺还可以是热氧化工艺。所述底层支撑层600、中间支撑层601和顶层支撑层602的材质包含但不限于氮化硅。在本发明的其他实施例中，为了对下电极层进行更好的支撑，底层支撑层600和顶层支撑层602之间还可以层叠两层以上的中间支撑层601。可选的，所有的电容器705可以呈六方密堆积排布。进一步的，所述下电极层701呈筒状结构，可以是多晶硅电极或金属电极。当下电极层701为金属电极时，还可以采用氮化钛(TiN)和Ti层叠结构。当下电极层701为多晶硅电极时，可以采用零掺杂和/或掺杂的多晶硅材料形成。所述电容介质层702覆盖所述下电极层701的筒状结构的内表面和外表面，以充分利用下电极层701的两个相对表面，构成具有较大电极表面积的电容器。优选的，所述电容介质层 702可以为金属氧化物等高K介质层。进一步的，所述电容介质层702为多层结构，例如为氧化铪-氧化锆的两层结构。所述上电极层703可以为单层结构也可以为多层结构，当所述上电极层703为单层结构时，例如为多晶硅电极，也可以为金属电极，当上电极层703为金属电极时，例如可以采用氮化钛(TiN)形成。所述上电极层703在对应所述筒状结构的内部和所述筒状结构的外部均能够与所述电容介质层702以及所述下电极层701构成电容器。此外，在核心区I边缘区域(即电容孔阵列的边界区域)上，由于横向支撑层(即中间支撑层601、顶层支撑层602)的存在，所述电容介质层702和所述上电极层703均具有凹凸不平形貌的侧壁结构，所述凹凸不平形貌的侧壁结构对应于在所述下电极层701的筒状结构筒外部的所述中间支撑层601、顶层支撑层602，由此使得所述上电极层703在所述核心区I边缘区域(即电容孔阵列的边界区域)上的部分，对应所述中间支撑层601、顶层支撑层602以远离所述下电极层701的方向凸出，使核心区I中的电容器阵列边界不平整。此外，本实施例中，所述电容介质层702和所述上电极层703还依次延伸覆盖在所述周边区II上保留的底层支撑层600的表面上，此外，在所述上电极层703表面还覆盖有一上电极填充层704，所述上电极填充层704填满所述上电极层703之间的间隙，也就是说，所述上电极填充层704填充满相邻的筒状结构之间的间隙并覆盖上述形成的结构。优选的，所述上电极填充层704的材质包括未掺杂或者硼掺杂的多晶硅。
请参考图20，本发明还提供一种采用上述的半导体器件的制造方法制造的半导体器件，包括：半导体衬底410、层间介质层500和多个接触插塞CT。其中，所述半导体衬底410具有核心区I、周边区II以及位于核心区I和周边区II之间的交界区III，核心区I中形成有限定各个有源区AA1的浅沟槽隔离结构411b，交界区II中形成有限定核心区I和周边区II的浅沟槽隔离结构411a。层间介质层500形成在所述半导体衬底410上，可以是二氧化硅、氮化硅或低K介质(介电常数K低于3)。多个接触插塞CT形成在所述层间介质层500中，并与相应的核心元件的有源区AA1接触。其中，所述核心区I的边界处的部分有源区AA1的上方无接触插塞。此外，在一些实施例中，核心 区I相对两侧的边界处的接触插塞CT不对称分布，例如核心区I上侧边界处和下侧边界处的接触插塞不对称分布，和/或，核心区I左侧边界处和右侧边界处的接触插塞不对称分布。
可选地，所述半导体器件可以是存储器，其还包括多条字线WL、源区及漏区S/D、位线接触部(未图示)以及多条位线BL(未图示)。其中，各条字线WL为埋入式字线，形成在所述半导体衬底410中，并与所述有源区AA1交叉。源区及漏区S/D形成在所述字线两侧的有源区AA1中。位线接触部形成在漏区上，各条位线形成在相应的所述位线接触部上并与各条所述字线交叉。所述层间介质层500将所述半导体衬底410、字线WL、源区和漏区S/D、位线接触部和位线均掩埋在内。所述核心区I的边界处，至少最外侧的两条位线BL之间的部分有源区的上方无接触插塞，和/或(二选一或二者兼具)，至少两条字线WL之间的部分有源区的上方无接触插塞。
综上所述，本发明的技术方案中，通过本发明提供的掩模版组合，来定义接触插塞的形成位置，以使得核心区边界处的部分有源区的上方无接触插塞，而核心区边界处的其他有源区以及核心区内部的有源区的上方均有接触插塞，由此，后续再采用现有工艺在核心区的内部和边界处形成相应的电学结构时，使得核心区边界处的部分电学结构因其下方没有与有源区接触的接触插塞而变为虚拟结构，由此可以避免制造出来的半导体器件因核心区边界处的电学结构的问题而导致不能通过相关测试的问题，继而提高了制得的半导体器件的性能和合格率。
需要说明的是，本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。以及，上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于本发明技术方案所要求的保护范围。
此外，还需要说明的是，除非特别说明或者指出，否则说明书中的术语“第一”、“第二”和“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺 序关系等。本文中的用语“和/或”表示二选一或二者兼具。

Claims (32)

  1. 一种半导体器件的电接触结构，其特征在于，所述半导体器件包括一衬底，所述衬底包括核心区、周边区以及位于所述核心区和周边区之间的交界区，所述交界区中形成有隔离结构，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区，所述电接触结构包括：
    多个接触插塞，形成于所述核心区和所述隔离结构的上方；
    其中，所述多个接触插塞包括最靠近所述周边区的第一个接触插塞，至少所述第一个接触插塞形成于所述隔离结构上方并与所述隔离结构接触，其余的所述接触插塞形成于所述核心区的各所述核心元件的上方且底部与相应的所述核心元件的有源区接触。
  2. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述第一个接触插塞的底部完全重叠在所述隔离结构上。
  3. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述第一个接触插塞的底部一部分重叠在所述隔离结构上，另一部分重叠在最靠近所述隔离结构的所述核心元件的有源区上。
  4. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述第一个接触插塞的底部伸入到所述隔离结构的内部。
  5. 如权利要求4所述的半导体器件的电接触结构，其特征在于，所述第一个接触插塞的底部伸入到所述隔离结构的内部的深度小于其余的每个所述接触插塞的底部伸入到相应的所述有源区内的深度。
  6. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述衬底中埋入有至少一个栅极，所述第一个接触插塞仅有一侧与其最近邻的埋入在所述衬底的栅极接触。
  7. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述第一个接触插塞与其最近邻的形成在所述核心区上方的至少一个所述接触插塞的顶部相联在一起。
  8. 如权利要求7所述的半导体器件的电接触结构，其特征在于，顶部相 联在一起的所有所述接触插塞构成倒U形电接触结构或者梳状电接触结构。
  9. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述电接触结构还包括相互独立的多个接触垫，形成在其余的各个所述接触插塞的顶部，并一一对应地与相应的所述接触插塞的顶部电接触。
  10. 一种半导体器件，其特征在于，包括：
    衬底，所述衬底包括核心区、周边区以及位于所述核心区和所述周边区之间的交界区，所述交界区中形成有隔离结构，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区；
    层间介质层，覆盖在所述衬底上；以及，
    如权利要求1～9中任一项所述的半导体器件的电接触结构，所述电接触结构形成于所述层间介质层中。
  11. 如权利要求10所述的半导体器件，其特征在于，所述半导体器件为DRAM，所述核心区为存储区，所述核心元件为存储晶体管，所述电接触结构为存储节点接触结构；所述半导体器件还包括多个电容器，各个所述电容器的底部分别与各个所述接触插塞的顶部接触。
  12. 如权利要求11所述的半导体器件，其特征在于，所述第一个接触插塞上接的所述电容器的尺寸是其余的各个所述接触插塞上接的所述电容器的尺寸的1.3倍～2.3倍。
  13. 一种如权利要求1～9中任一项所述的半导体器件的电接触结构的制造方法，其特征在于，包括：
    提供衬底，所述衬底具有核心区、周边区以及位于所述核心区和所述周边区之间的交界区，所述交界区中形成有隔离结构，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区；
    在所述衬底上形成层间介质层，并在所述层间介质层中形成多个接触孔，其中，所述多个接触孔包括最靠近所述周边区的第一个接触孔，至少所述第一个接触孔贯穿所述层间介质层并暴露出部分所述隔离结构，其余的所述接触孔贯穿所述层间介质层并暴露出相应的所述核心元件的有源区；
    在各个所述接触孔中形成相应的接触插塞。
  14. 如权利要求13所述的半导体器件的电接触结构的制造方法，其特征在于，所述第一个接触孔与其最近邻的形成在所述核心区上方的至少一个接触孔的顶部相连通。
  15. 如权利要求14所述的半导体器件的电接触结构的制造方法，其特征在于，通过两次光刻工艺使得所述第一个接触孔与其最近邻的形成在所述核心区上方的至少一个接触孔的顶部相连通。
  16. 一种半导体器件的制造方法，其特征在于，包括如权利要求13～15中任一项所述的半导体器件的电接触结构的制造方法。
  17. 一种掩模板组合，用于制作接触插塞，其特征在于，所述掩模板组合包括：
    第一掩模板，具有多条平行的第一遮光条纹，相邻的两条所述第一遮光条纹之间为第一透光区；
    第二掩模板，具有多条平行的第二遮光条纹，相邻的两条所述第二遮光条纹之间为第二透光区；
    第三掩模板，具有遮光块和与所述遮光块互补的第三透光区；
    其中，所述第一掩模板、所述第二掩模板和所述第三掩模板依次叠置在一起时，所述多条平行的第二遮光条纹与每条所述第一条纹相交，所述遮光块覆盖最靠近所述第一掩模板的边界的至少一条第一遮光条纹和被覆盖的该条第一遮光条纹最近邻的部分第一透光区，以及，所述遮光块还覆盖最靠近所述第二掩模板的边界的至少两条第二遮光条纹以及被覆盖的所述两条第二遮光条纹之间的部分所述第二透光区，所述第三透光区、所述第一透光区和所述第二透光区的重叠区域为用于形成接触插塞的区域。
  18. 如权利要求17所述的掩模板组合，其特征在于，所述用于形成接触插塞的区域的形状包括正方形、圆形、椭圆形、三角形、矩形、多边形和心形中的至少一种。
  19. 如权利要求17所述的掩模板组合，其特征在于，所述遮光块覆盖的第二遮光条纹的数量为所述遮光块覆盖的第一遮光条纹的数量的2～5倍。
  20. 如权利要求17所述的掩模板组合，其特征在于，最靠近所述第一掩 模板的边界的至少一条第一遮光条纹具有第一宽度，其余的所述第一遮光条纹具有第二宽度，所述第一宽度大于所述第二宽度。
  21. 如权利要求20所述的掩模板组合，其特征在于，所述第一宽度大于1.5倍的所述第二宽度。
  22. 如权利要求17所述的掩模板组合，其特征在于，最靠近所述第二掩模板的边界的至少一条第二遮光条纹具有第三宽度，其余的所述第二遮光条纹具有第四宽度，所述第三宽度大于所述第四宽度。
  23. 如权利要求22所述的掩模板组合，其特征在于，所述第三宽度大于1.5倍的所述第四宽度。
  24. 如权利要求17所述的掩模板组合，其特征在于，所述遮光块面向所述第三掩模板中心的边缘是不对称的。
  25. 一种接触插塞制作方法，其特征在于，使用权利要求17～24中任一项所述的掩模板组合来制作，所述接触插塞制作方法包括：
    提供形成有多个有源区的半导体衬底，在所述半导体衬底上依次形成层间介质层和第一掩模层；
    采用光刻结合刻蚀的工艺，将所述掩模板组合中的第一掩模板上的图案转移到所述第一掩模层上以得到转移后的第一掩模层，所述转移后的第一掩模层中形成有多条第一线条，其中，每条所述第一线条对应所述第一掩模板上相应的第一遮光条纹，相邻所述第一线条之间的沟槽对应所述第一掩模板上相应的第一透光区并暴露出相应的所述层间介质层；
    在所述层间介质层和所述第一掩模层上覆盖第二掩模层，并采用光刻结合刻蚀的工艺，将所述掩模板组合中的第二掩模板上的图案转移到所述第二掩模层上以得到转移后的第二掩模层，所述转移后的第二掩模层中形成有多条第二线条，所述多条第二线条与每条所述第一线条相交，其中，每条所述第二线条对应所述第二掩模板上相应的第二遮光条纹，相邻所述第二线条之间的沟槽对应所述第二掩模板上相应的第二透光区并暴露出相应的所述第一线条以及所述第一透光区中的层间介质层；
    在所述第一掩模层、第二掩模层和层间介质层上覆盖第三掩模层，并采 用光刻结合刻蚀的工艺，将所述掩模板组合中的第三掩模板上的图案转移到所述第三掩模层上以得到转移后的第三掩模层，所述转移后的第三掩模层对应所述第三掩模板的遮光块，所述转移后的第三掩模层、所述转移后的第一掩模层和所述转移后的第二掩模层共同暴露出的所述层间介质层作为待形成接触插塞的区域；
    以所述转移后的第一掩模层、所述转移后的第二掩模层和所述转移后的第三掩模层为掩模，刻蚀暴露出的所述层间介质层，以形成暴露出相应的有源区的多个接触孔；
    在每个所述接触孔中形成接触插塞，各个所述接触插塞的底部与相应的所述有源区接触。
  26. 一种半导体器件的制造方法，其特征在于，包括：采用如权利要求25所述的制作接触插塞的方法，在一具有核心区的半导体衬底上形成接触插塞，各个所述接触插塞的底部与所述核心区中相应的核心元件的有源区接触。
  27. 如权利要求26所述的半导体器件的制造方法，其特征在于，所述核心区为存储区，所述核心元件为存储晶体管，所述接触插塞为存储节点接触部，所述半导体器件的制造方法还包括：
    在所述接触插塞上形成电容器的下电极；
    形成覆盖所述下电极的电容介质；以及，
    在所述电容介质上形成所述电容器的上电极。
  28. 如权利要求27所述的半导体器件的制造方法，其特征在于，提供具有核心区的半导体衬底的步骤包括：
    提供一具有核心区的半导体衬底，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区；
    在所述半导体衬底中形成字线，所述字线与所述有源区交叉，所述字线与所述第二线条重叠；
    在所述字线两侧的所述有源区中分别形成源区及漏区；
    在所述漏区上形成位线接触部；以及
    在所述位线接触部上形成位线，所述位线与所述字线交叉，所述第一线 条与所述位线重叠。
  29. 一种采用如权利要求26～28中任一项所述的半导体器件的制造方法制造的半导体器件，其特征在于，包括：
    半导体衬底，所述半导体衬底包括核心区，所述核心区中形成有多个核心元件，每个所述核心元件包括有源区；
    层间介质层，形成在所述半导体衬底上；
    多个接触插塞，形成所述层间介质层中，并与相应的所述核心元件的有源区接触；
    其中，所述核心区边界处的部分所述有源区的上方无接触插塞。
  30. 如权利要求29所述的半导体器件，其特征在于，所述核心区相对两侧的边界处的多个所述接触插塞不对称分布。
  31. 如权利要求29所述的半导体器件，其特征在于，所述半导体器件还包括：
    多条字线，形成在所述半导体衬底中，并与相应的一个或多个所述有源区交叉；
    多个源区及漏区，对应形成在每个所述字线两侧的每个所述有源区中；
    多个位线接触部，对应形成在每个所述漏区上；
    多条位线，对应形成在每个所述位线接触部上，所述多条位线与每条所述字线交叉；
    所述层间介质层将所述半导体衬底、所述多条字线、所述多个源区及漏区、所述多个位线接触部和所述多条位线掩埋在内。
  32. 如权利要求31所述的半导体器件，其特征在于，所述核心区的边界处，至少两条位线之间的部分所述有源区的上方无接触插塞，以及，至少两条字线之间的部分所述有源区的上方无接触插塞。
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