WO2021056881A1 - 射频功率放大器幅度调制对幅度调制的补偿电路 - Google Patents

射频功率放大器幅度调制对幅度调制的补偿电路 Download PDF

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WO2021056881A1
WO2021056881A1 PCT/CN2019/127407 CN2019127407W WO2021056881A1 WO 2021056881 A1 WO2021056881 A1 WO 2021056881A1 CN 2019127407 W CN2019127407 W CN 2019127407W WO 2021056881 A1 WO2021056881 A1 WO 2021056881A1
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Prior art keywords
amplitude modulation
power amplifier
transistor
compensation circuit
circuit
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PCT/CN2019/127407
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English (en)
French (fr)
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奕江涛
苏强
温华东
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广州慧智微电子有限公司
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Priority to US17/120,167 priority Critical patent/US11431306B2/en
Publication of WO2021056881A1 publication Critical patent/WO2021056881A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C1/00—Amplitude modulation
    • H03C1/02—Details
    • H03C1/06—Modifications of modulator to reduce distortion, e.g. by feedback, and clearly applicable to more than one type of modulator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C2200/00—Indexing scheme relating to details of modulators or modulation methods covered by H03C
    • H03C2200/0004—Circuit elements of modulators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • This application relates to the field of electronic circuits, for example, to a compensation circuit for amplitude modulation of a radio frequency power amplifier.
  • the efficiency and linear power of the front-end RF power amplifier directly affect the energy consumption and communication quality of the base station and terminal equipment.
  • Adjacent Channel Leakage Ratio (ACLR) indicators must meet the requirements of various mobile communication protocols.
  • the ACLR performance of the power amplifier can be used with the power amplifier's amplitude modulation (Amplitude Modulation-Amplitude Modulation, AM-AM) distortion and amplitude modulation vs. phase modulation (Amplitude Modulation-Phase Modulation, AM-PM). ) Distortion to characterize.
  • the source of AM-AM distortion is mainly that the transistor voltage input and current output characteristics of the power amplifier exhibit nonlinear characteristics under the condition of large signal input. As the input drive power of the power amplifier increases, the power amplifier will experience gain compression, resulting in frequency spectrum Spread, ACLR deteriorates.
  • This application provides a compensation circuit for the amplitude modulation of the radio frequency power amplifier.
  • a compensation circuit for amplitude modulation of a radio frequency power amplifier for amplitude modulation comprising: a first bias circuit, a power amplifier, and a compensation circuit located between the first bias circuit and the power amplifier;
  • the compensation circuit includes a diode detection circuit and a feedforward amplifier for compensating AM-AM distortion.
  • the diode detection circuit includes: a first transistor and a first resistor connected in parallel with the first transistor; wherein,
  • the gate and drain of the first transistor are short-circuited, and both are connected to the first bias circuit; the source of the first transistor is connected to the first end of the power amplifier, and the power amplifier The first terminal is the gate of the second transistor in the power amplifier.
  • the feedforward amplifier includes: a first capacitor, a third transistor, and a second capacitor; wherein,
  • the first end of the first capacitor is connected to the radio frequency input end, the second end of the first capacitor is connected to the gate of the third transistor; the source of the third transistor is connected to the ground, the The drain of the third transistor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the drain of the first transistor.
  • the feedforward amplifier further includes a second bias circuit for providing a bias current for the third transistor;
  • the second bias circuit is connected to the gate of the third transistor.
  • the feedforward amplifier further includes a voltage source and a second resistor connected in series with the voltage source; wherein,
  • the second resistor is connected to the drain of the third transistor for providing a drain bias voltage for the third transistor.
  • the first resistor in the diode detection circuit is a variable resistor.
  • the magnification of the feedforward amplifier is an adjustable magnification.
  • the parameters of the third transistor in the feedforward amplifier are adjustable; and/or,
  • the parameters of the second bias circuit in the feedforward amplifier are adjustable.
  • the parameters of the second bias circuit are adjustable and include at least:
  • the current parameter of the first current source in the second bias circuit is adjustable.
  • the compensation circuit further includes a circuit switch, and both ends of the circuit switch are connected in parallel with both ends of the first transistor.
  • the power amplifier includes a second transistor; or,
  • the power amplifier includes a plurality of second transistors, and a stacked tube structure is formed between the plurality of second transistors.
  • the compensation circuit for amplitude modulation of the radio frequency power amplifier includes: a first bias circuit, a power amplifier, and a compensation circuit located between the first bias circuit and the power amplifier; Wherein, the compensation circuit includes a diode detection circuit and a feedforward amplifier for compensating AM-AM distortion.
  • a compensation circuit is introduced before the power amplifier, and the diode detection circuit in the compensation circuit can realize that when the input signal amplitude of the power amplifier increases, the bias of the power amplifier can be increased. Current (voltage) compensates for gain compression due to AM-AM distortion.
  • the feedforward amplifier in the compensation circuit can meet the requirements of the mobile communication protocol for the power amplifier setup time.
  • the compensation circuit of the amplitude modulation of the radio frequency power amplifier in the embodiment of the present application is relatively simple to implement, and the design is flexible. AMAM programming can be adjusted by adjusting the parameters in the compensation circuit, the applicability is good, the integration is easy, and the cost is low.
  • Figure 1 is a circuit diagram of an AM-AM compensation circuit based on diode detection
  • Figure 2 is a schematic diagram of the comparison between the original circuit and the AM-AM compensation circuit
  • Fig. 3 is a schematic diagram showing the variation of the DC level of Vin with the input power Pin in the AM-AM compensation circuit shown in Fig. 1;
  • FIG. 4 is a schematic diagram of the gain compression compensation effect based on the AM-AM compensation circuit shown in FIG. 1;
  • FIG. 5 is a schematic diagram of the composition structure of a compensation circuit for amplitude modulation of an RF power amplifier according to an embodiment of the application;
  • FIG. 6 is a circuit diagram 1 of a compensation circuit for amplitude modulation to amplitude modulation of a radio frequency power amplifier according to an embodiment of the application;
  • FIG. 7 is a second schematic circuit diagram of a compensation circuit for amplitude modulation to amplitude modulation of a radio frequency power amplifier according to an embodiment of the present application
  • FIG. 8 is a circuit diagram 3 of a compensation circuit for amplitude modulation to amplitude modulation of a radio frequency power amplifier according to an embodiment of the application;
  • FIG. 9 is a circuit schematic diagram 4 of a compensation circuit for amplitude modulation to amplitude modulation of a radio frequency power amplifier according to an embodiment of the application;
  • FIG. 10 is a schematic circuit diagram 5 of a compensation circuit for amplitude modulation to amplitude modulation of a radio frequency power amplifier according to an embodiment of the application.
  • the amplifier When designing the amplifier, it will be based on the signal peak-to-average ratio (PAR) value of the non-constant envelope modulation signal used by the mobile communication system (the ratio of the peak power with a probability of 0.01% to the total average power) Ratio) to determine the difference between the linear power (no distortion or weak distortion power) of the power amplifier to the saturation power.
  • PAR signal peak-to-average ratio
  • the selection of this difference requires a compromise between the ACLR performance and efficiency of the power amplifier; if the value is too large, it is generally necessary to reduce the amplifier load impedance to achieve this.
  • the ACLR performance of the output signal can far meet the protocol requirements, but the power amplifier’s
  • the working current is large and the efficiency is low; if the value is too small, the load impedance of the power amplifier can be increased, and the current consumed by the power amplifier can be reduced.
  • the premature gain compression will cause some signals with higher than average power to be distorted, and the ACLR performance Cannot meet the requirements of the agreement.
  • a compensation circuit based on diode detection is shown in Figure 1. It is composed of N-Metal-Oxide-Semiconductor (NMOS) tube M1, filter capacitor C1, isolation resistor R1 and current source Ib.
  • NMOS N-Metal-Oxide-Semiconductor
  • D1 is added to the bias circuit, and the gate and drain of D1 are short-circuited. They are used as diodes to separate the node voltages Vg and Vd. When a large signal is input, the detection effect of D1 will raise the Vin voltage. To compensate for the gain compression of amplifier M2 under large signals.
  • the mobile communication protocol requires the rising edge setup time of the power amplifier to be ⁇ 10us. This circuit is far from reaching the protocol requirements. Used directly in the RF power amplifier. To this end, the following technical solutions of the embodiments of the present application are proposed.
  • FIG. 5 is a schematic diagram of the composition structure of a compensation circuit for amplitude modulation to amplitude modulation of a radio frequency power amplifier according to an embodiment of the application.
  • the compensation circuit for amplitude modulation of the radio frequency power amplifier includes: a first bias circuit 51, a power amplifier 52, and a circuit between the first bias circuit 51 and the power amplifier 52 Compensation circuit 53; among them,
  • the compensation circuit 53 includes a diode detection circuit 531 and a feedforward amplifier 532 for compensating AM-AM distortion.
  • a compensation circuit including a diode detection circuit and a feedforward amplifier is arranged between the first bias circuit and the power amplifier, and the diode detection circuit in the compensation circuit can realize the input of the power amplifier.
  • the signal amplitude increases, increase the bias current (voltage) of the power amplifier to compensate for gain compression due to AM-AM distortion.
  • the feedforward amplifier in the compensation circuit can meet the requirements of the mobile communication protocol for the power amplifier setup time.
  • the compensation circuit in the embodiment of the present application can also be referred to as an AM-AM compensation circuit because it can compensate for gain compression due to AM-AM distortion.
  • the following is an example of the compensation circuit for the amplitude modulation of the radio frequency power amplifier in the embodiment of the present application in combination with the specific circuit structure.
  • Fig. 6 is a schematic circuit diagram 1 of the compensation circuit for amplitude modulation of the radio frequency power amplifier according to an embodiment of the application.
  • the compensation circuit for the amplitude modulation of the radio frequency power amplifier includes: a first bias circuit 61 , A power amplifier 62, and a compensation circuit 63 located between the first bias circuit 61 and the power amplifier 62; wherein,
  • the compensation circuit 63 includes a diode detection circuit and a feedforward amplifier for compensating AM-AM distortion.
  • the diode detection circuit in the compensation circuit 63 includes: a first transistor D1, and a first resistor R2 connected in parallel with the first transistor D1; The gate and drain are short-circuited, and both are connected to the first bias circuit 61; the source of the first transistor D1 is connected to the first end of the power amplifier 62, and the first end of the power amplifier 62 The terminal is the gate of the second transistor M2 in the power amplifier 62.
  • the feedforward amplifier in the compensation circuit 63 includes: a first capacitor Cb2, a third transistor M3, and a second capacitor Cb3; wherein, the first end of the first capacitor Cb2 is connected to the radio frequency
  • the input terminal RFin is connected, the second terminal of the first capacitor Cb2 is connected to the gate of the third transistor M3; the source of the third transistor M3 is connected to ground, and the drain of the third transistor M3 It is connected to the first terminal of the second capacitor Cb3, and the second terminal of the second capacitor Cb3 is connected to the drain of the first transistor D1.
  • the feedforward amplifier in the compensation circuit 63 further includes a second bias circuit for providing a bias current for the third transistor M3; wherein, the second bias circuit Connected to the gate of the third transistor M3.
  • the feedforward amplifier 63 further includes a voltage source VCC1 and a second resistor R3 connected in series with the voltage source VCC1 to provide a drain bias voltage for the third transistor M3 ; Wherein, the second resistor R3 is connected to the drain of the third transistor M3.
  • the first bias circuit includes a first current source Ib1, a fourth transistor M1, a third capacitor C1, and a third resistor R1.
  • the second bias circuit includes a second current source Ib2, a fifth transistor M4, a fourth capacitor C2, and a fourth resistor R4.
  • the power amplifier includes a second transistor M2, a fifth capacitor Cb1, and a sixth capacitor Cb2.
  • the compensation circuit is composed of the following two parts:
  • the first part (diode detection circuit):
  • the diode-connected NMOS tube D1 i.e. the first transistor D1
  • the parallel isolation resistor R2 i.e. the first resistor R2
  • R2 can effectively Reducing the equivalent DC resistance of D1 and the total resistance of the bias circuit node can significantly improve the quiescent current settling time.
  • the second part is composed of DC blocking capacitor Cb2 (ie first capacitor Cb2), NMOS amplifying tube M3 (ie third transistor M3) and feed-forward capacitor Cb3 (ie third transistor M3) Feedforward amplifier.
  • DC blocking capacitor Cb2 ie first capacitor Cb2
  • NMOS amplifying tube M3 ie third transistor M3
  • feed-forward capacitor Cb3 ie third transistor M3 Feedforward amplifier.
  • the bias current of the feedforward amplifier consists of the current source Ib2 (ie the second current source Ib2), the NMOS tube M4 (ie the fifth transistor M4), the filter capacitor C2 (ie the fourth capacitor C2) and the radio frequency isolation resistor R4 (ie the fourth
  • the second bias circuit composed of resistor R4) is provided; the drain bias voltage of the feedforward amplifier is provided by the voltage source VCC1 and the bias resistor R3 (that is, the second resistor R3); the feedforward amplifier can effectively enhance the detection effect of D1, Effectively compensate for the influence introduced by the isolation resistance R2.
  • R1 that is, the third resistor R1
  • R1 is generally 20kohm, which isolates the influence of the Vd radio frequency signal on the Vg voltage
  • the value of the isolation resistor R2 is generally about 5kohm, which is much smaller than that of D1. Equivalent resistance, Vin's forward voltage swing will be affected by the charge leakage of the R2 and Cb3 channels, and the upper limit of the swing will be limited.
  • the RF voltage swing of node Vd is positive, while the swing of the gate RF voltage Vin of M2 is still negative, and the gate voltage of the NMOS transistor D1 is higher than the source voltage by Vp , D1 is turned on, and Vin is clamped at (Vp+Vin0)-Vth, which is higher than the Vin0-Vth of the existing circuit, which increases the lower limit of the negative swing; select appropriate circuit parameters to make the feedforward amplifier pass the D1 pair
  • the increase of Vin's negative swing is stronger than the limitation of Vin's positive swing by the charge discharge of R2, R1 and the bias tube M1 path, which achieves the purpose of raising the DC voltage of the amplifier tube M2 grid, which plays a large role in compensation.
  • the settling time of the quiescent current of the circuit depends on the node time constant RC.
  • a compensation circuit including a diode detection circuit and a feedforward amplifier is arranged between the first bias circuit and the power amplifier.
  • the diode detection circuit in the compensation circuit can realize the input of the power amplifier.
  • the feedforward amplifier in the compensation circuit can meet the requirements of the mobile communication protocol for the power amplifier setup time.
  • the compensation circuit of the amplitude modulation of the radio frequency power amplifier in the embodiment of the present application is relatively simple to implement, and the design is flexible. AMAM programming can be adjusted by adjusting the parameters in the compensation circuit, the applicability is good, the integration is easy, and the cost is low.
  • the first resistor R2 in the diode detection circuit is a variable resistor, thereby forming a circuit structure as shown in FIG. 7.
  • the AM-AM compensation switch-on power point is realized.
  • the compensation range is programmable and controllable to achieve the purpose of increasing the applicability and flexibility of the circuit.
  • the amplification factor of the feedforward amplifier in the compensation circuit of the amplitude modulation of the radio frequency power amplifier is an adjustable amplification factor, wherein the third transistor M3 in the feedforward amplifier is The parameter is adjustable; and/or, the current parameter of the first current source Ib2 in the second bias circuit in the feedforward amplifier is adjustable, thereby forming a circuit structure as shown in FIG. 8, by changing the feedforward
  • the amplification method of the amplifier realizes that the power point of AM-AM compensation and the compensation amplitude can be programmed and controlled.
  • the compensation circuit of the RF power amplifier amplitude modulation to amplitude modulation compensation circuit also includes a circuit switch S1, and both ends of the circuit switch S1 are connected in parallel with both ends of the first transistor D1, thereby The circuit structure shown in Figure 9 is formed, and the compensation circuit can be selected through the switch S1. When S1 is disconnected, the compensation circuit works, and when S1 is closed, the compensation circuit does not work.
  • the power amplifier of the compensation circuit for the amplitude modulation of the radio frequency power amplifier includes a second transistor M2; or, the number of the second transistor M2 is expanded, and the power amplifier includes a plurality of second transistors.
  • Two transistors M2 a stacked tube structure is formed between the plurality of second transistors, thereby forming a circuit structure as shown in FIG. 10, wherein the number of the second transistors M2 is n, and n is an integer greater than or equal to 2, as shown in FIG.
  • the given n pieces of M2 include M21, M22, ..., M2n, and the n pieces of M2 form a stacked tube structure.
  • transistors in the embodiments of the present application are not limited to NMOS transistors, but can also be other types of power transistors, such as Heterojunction Bipolar Transistor (HBT) Bipolar Junction Transistor (HBT). Transistor, BJT) and other types.
  • HBT Heterojunction Bipolar Transistor
  • HBT Bipolar Junction Transistor
  • BJT Transistor

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Abstract

本申请提供一种射频功率放大器幅度调制对幅度调制的补偿电路，包括：第一偏置电路、功率放大器、以及位于所述第一偏置电路和所述功率放大器之间的补偿电路；其中，所述补偿电路包括二极管检波电路和前馈放大器，用于对幅度调制对幅度调制AM-AM失真进行补偿。

Description

射频功率放大器幅度调制对幅度调制的补偿电路
本申请要求在2019年09月26日提交中国专利局、申请号为201910915549.6的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请涉及电子电路领域，例如涉及一种射频功率放大器幅度调制对幅度调制的补偿电路。
背景技术
在移动通讯***中，前端射频功率放大器(简称功率放大器)的效率和线性功率直接影响基站和终端设备的能耗和通信质量，终端设备的上行调制信号被前端射频功率放大器放大后的输出功率和相邻频道泄漏比(Adjacent Channel Leakage Ratio，ACLR)指标必须满足各种移动通信协议的要求。在无记忆效应***中，功率放大器的ACLR性能可以用功率放大器的幅度调制对幅度调制(Amplitude Modulation-Amplitude Modulation，AM-AM)失真和幅度调制对相位调制(Amplitude Modulation-Phase Modulation，AM-PM)失真来表征。AM-AM失真和AM-PM失真随输入信号变化的变化率越大，功率放大器的输出信号的ACLR越差。AM-AM失真的来源主要是功率放大器的晶体管电压输入电流输出特性在大幅度信号输入的情况下呈现出非线性特性，随着功率放大器输入驱动功率的增加，功率放大器会出现增益压缩，导致频谱扩散，ACLR恶化。
发明内容
本申请提供了一种射频功率放大器幅度调制对幅度调制的补偿电路。
一种射频功率放大器幅度调制对幅度调制的补偿电路，包括：第一偏置电路、功率放大器、以及位于所述第一偏置电路和所述功率放大器之间的补偿电路；其中，
所述补偿电路包括二极管检波电路和前馈放大器，用于对AM-AM失真进行补偿。
所述二极管检波电路包括：第一晶体管、以及与所述第一晶体管并联的第一电阻；其中，
所述第一晶体管的栅极和漏极短接，并均与所述第一偏置电路连接；所述第一晶体管的源极与所述功率放大器的第一端连接，所述功率放大器的第一端为所述功率放大器中的第二晶体管的栅极。
所述前馈放大器包括：第一电容、第三晶体管以及第二电容；其中，
所述第一电容的第一端与射频输入端连接，所述第一电容的第二端与所述第三晶体管的栅极连接；所述第三晶体管的源极与地端连接，所述第三晶体管的漏极与所述第二电容的第一端连接，所述第二电容的第二端与所述第一晶体管的漏极连接。
所述前馈放大器还包括第二偏置电路，用于为所述第三晶体管提供偏置电流；其中，
所述第二偏置电路与所述第三晶体管的栅极连接。
所述前馈放大器还包括电压源、以及与所述电压源串联的第二电阻；其中，
所述第二电阻连接所述第三晶体管的漏极，用于为所述第三晶体管提供漏极偏置电压。
所述二极管检波电路中的所述第一电阻为可变电阻。
所述前馈放大器的放大倍数为可调放大倍数。
所述前馈放大器中的所述第三晶体管的参数可调；和/或，
所述前馈放大器中的所述第二偏置电路的参数可调。
所述第二偏置电路的参数可调，至少包括：
所述第二偏置电路中的第一电流源的电流参数可调。
所述补偿电路还包括电路开关，所述电路开关的两端与所述第一晶体管的两端并联。
所述功率放大器包括一个第二晶体管；或者，
所述功率放大器包括多个第二晶体管，所述多个第二晶体管之间形成叠管结构。
本申请的技术方案中，射频功率放大器幅度调制对幅度调制的补偿电路，包括：第一偏置电路、功率放大器、以及位于所述第一偏置电路和所述功率放大器之间的补偿电路；其中，所述补偿电路包括二极管检波电路和前馈放大器，用于对AM-AM失真进行补偿。采用本申请实施例的技术方案，在功率放大器之 前引入补偿电路，通过该补偿电路中的二级管检波电路能够实现在功率放大器的输入信号幅度变大的情况下，通过提高功率放大器的偏置电流(电压)来补偿因AM-AM失真出现的增益压缩。另一方面，通过该补偿电路中的前馈放大器能够满足移动通信协议对功率放大器建立时间的要求。本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路实现相对简单，设计灵活，通过调整补偿电路中的参数可以实现AMAM编程可调，适用性好，且易集成，成本低。
附图说明
图1为基于二极管检波的AM-AM补偿电路的电路示意图；
图2为原始电路与AM-AM补偿电路的对比示意图；
图3为基于图1所示的AM-AM补偿电路中Vin直流电平随着输入功率Pin的变化示意图；
图4为基于图1所示的AM-AM补偿电路的增益压缩补偿效果示意图；
图5为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的组成结构示意图；
图6为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的电路示意图一；
图7为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的电路示意图二；
图8为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的电路示意图三；
图9为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的电路示意图四；
图10为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的电路示意图五。
具体实施方式
为便于理解本申请实施例的技术方案，以下对本申请实施例的相关技术进 行说明。
在设计放大器时，会根据移动通讯***所采用的非恒包络调制信号的信号峰均比(Peak-to-Average Ratio，PAR)值(出现概率为0.01％的峰值功率与总的平均功率的比)来决定功率放大器的线性功率(无失真或弱失真功率)到饱和功率的差值。该差值的选取需要在功率放大器的ACLR性能和效率之间做折中；若取值过大，一般需要降低放大器负载阻抗来实现，输出信号的ACLR性能远能满足协议要求，但功率放大器的工作电流大，效率低；若取值过小，可以提高功率放大器的负载阻抗，降低功率放大器消耗的电流，但过早出现的增益压缩，会导致高于平均功率的部分信号会失真，ACLR性能不能满足协议要求。
在兼顾效率的同时降低功率放大器的增益压缩对输出信号的ACLR性能的影响的方法有很多种，如包络跟踪，数字预失真等数字补偿方法，这些方法效果好，但需要外部芯片配合，成本高，控制复杂。另一种方法是，在功率放大器前端加入AM-AM补偿电路，在功率放大器的输入信号幅度变大的情况下，通过提高功率放大器的偏置电流(电压)来补偿因AM-AM失真出现的增益压缩，这种方法电路相对简单，效果较好，容易集成，成本很低。
一种基于二极管检波的补偿电路如图1所示，在N型金属-氧化物-半导体(N-Metal-Oxide-Semiconductor，NMOS)管M1，滤波电容C1，隔离电阻R1和电流源Ib组成的偏置电路中加入NMOS管D1，D1的栅极和漏极短接，作为二极管使用，将节点电压Vg和Vd隔开，在大信号输入时D1的检波效果会对Vin电压起到抬升作用，来补偿大信号下放大器M2的增益压缩。
图1所示的补偿电路的原理如下：静态电流条件下，由于D1存在漏电，时间足够长，最终Vg＝Vd＝Vin＝Vin0；在功率放大器工作时，当射频信号摆幅为负，Vin的反向摆幅超过D1的阈值电压Vth，D1导通，将Vin的电压钳位Vin0-Vth，使Vin不能再往低下摆，而当射频信号摆幅为正，Vin的正向摆幅不受D1的限制。经过几个射频周期稳定后，Vin的正向摆幅要高于负向摆幅，如图2所示。由傅里叶分析可知，该Vin波形DC分量会比初始Vin要高，Vin电压抬升到Vin1。当输入信号功率Pin越大，Vin电压摆幅越大，二极管D1的检波效果越明显，VinDC电平被提升的越高，如图3所示，增益压缩补偿效果如图4所示。
图1所示的补偿电路存在一个严重的问题，即静态电流建立时间过长；由电路分析可知，Vin的建立时间取决与该节点的RC常数(过渡反应的时间过程的常数)，其中，节点电阻Rnet＝(D1的截止等效电阻Requ+隔离电阻R1)，通 常D1截止等效电阻Requ很大，约0.5x10 9ohm，节点电容Cnet1＝(功率管M2栅极电容等效Cgate+滤波电容C1)≈4pF，时间常数约为2ms，按4倍的时间常数估算，建立时间约为8ms，而移动通信协议中要求功率放大器的上升沿建立时间≤10us，该电路远远达不到协议要求，无法直接在射频功率放大器中使用。为此，提出了本申请实施例的以下技术方案。
图5为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的组成结构示意图。如图5所示，该射频功率放大器幅度调制对幅度调制的补偿电路包括：第一偏置电路51、功率放大器52、以及位于所述第一偏置电路51和所述功率放大器52之间的补偿电路53；其中，
所述补偿电路53包括二极管检波电路531和前馈放大器532，用于对AM-AM失真进行补偿。
本实施例的技术方案中，在第一偏置电路和功率放大器之间设置包括二极管检波电路和前馈放大器的补偿电路，通过该补偿电路中的二级管检波电路能够实现在功率放大器的输入信号幅度变大的情况下，通过提高功率放大器的偏置电流(电压)来补偿因AM-AM失真出现的增益压缩。另一方面，通过该补偿电路中的前馈放大器能够满足移动通信协议对功率放大器建立时间的要求。
需要说明的是，本申请实施例中的补偿电路由于可以补偿因AM-AM失真出现的增益压缩，因而也可以称为AM-AM补偿电路。
以下结合具体电路结构对本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路进行举例说明。
图6为本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路的电路示意图一，如图6所示，该射频功率放大器幅度调制对幅度调制的补偿电路包括：第一偏置电路61、功率放大器62、以及位于所述第一偏置电路61和所述功率放大器62之间的补偿电路63；其中，
所述补偿电路63包括二极管检波电路和前馈放大器，用于对AM-AM失真进行补偿。
在一种可选实施方式中，所述补偿电路63中的二极管检波电路包括：第一晶体管D1、以及与所述第一晶体管D1并联的第一电阻R2；其中，所述第一晶体管D1的栅极和漏极短接，并均与所述第一偏置电路61连接；所述第一晶体管D1的源极与所述功率放大器62的第一端连接，所述功率放大器62的第一端为所述功率放大器62中的第二晶体管M2的栅极。
在一种可选实施方式中，所述补偿电路63中的前馈放大器包括：第一电容Cb2、第三晶体管M3以及第二电容Cb3；其中，所述第一电容Cb2的第一端与射频输入端RFin连接，所述第一电容Cb2的第二端与所述第三晶体管M3的栅极连接；所述第三晶体管M3的源极与地端连接，所述第三晶体管M3的漏极与所述第二电容Cb3的第一端连接，所述第二电容Cb3的第二端与所述第一晶体管D1的漏极连接。
在一种可选实施方式中，所述补偿电路63中的前馈放大器还包括第二偏置电路，用于为所述第三晶体管M3提供偏置电流；其中，所述第二偏置电路与所述第三晶体管M3的栅极连接。
在一种可选实施方式中，所述前馈放大器63还包括电压源VCC1、以及与所述电压源VCC1串联的第二电阻R3，用于为所述第三晶体管M3提供漏极偏置电压；其中，所述第二电阻R3连接所述第三晶体管M3的漏极。
在一种可选实施方式中，所述第一偏置电路包括第一电流源Ib1、第四晶体管M1、第三电容C1和第三电阻R1。
在一种可选实施方式中，所述第二偏置电路包括第二电流源Ib2、第五晶体管M4、第四电容C2和第四电阻R4。
在一种可选实施方式中，所述功率放大器包括第二晶体管M2、第五电容Cb1和第六电容Cb2。
基于以上电路结构可知，补偿电路由以下两部分组成：
第一部分(二极管检波电路)：具体实现时，通过二极管接法的NMOS管D1(即第一晶体管D1)和并联隔离电阻R2(即第一电阻R2)组成二极管检波电路，其中，R2可以有效地降低D1的等效直流电阻，降低偏置电路节点总电阻，能显著改善静态电流建立时间。
第二部分(前馈放大器)：具体实现时，通过隔直电容Cb2(即第一电容Cb2)，NMOS放大管M3(即第三晶体管M3)和前馈电容Cb3(即第三晶体管M3)组成前馈放大器。前馈放大器的偏置电流由电流源Ib2(即第二电流源Ib2)，NMOS管M4(即第五晶体管M4)，滤波电容C2(即第四电容C2)和射频隔离电阻R4(即第四电阻R4)组成的第二偏置电路提供；前馈放大器的漏极偏置电压由电压源VCC1和偏置电阻R3(即第二电阻R3)提供；前馈放大器可以有效增强D1的检波效果，有效弥补隔离电阻R2引入的影响。
上述射频功率放大器幅度调制对幅度调制的补偿电路的工作原理如下：
当射频输入端RFin的射频电压摆幅为正，幅度为Vp，一部分射频电压经过隔值电容Cb2馈入到前馈放大器中的M3的栅极，而前馈放大器为共源放大器，M3的漏极的射频电压摆幅会被反向为负，经过前馈电容Cb3后，节点Vd的射频电压摆幅仍为负，而M2的栅极射频电压Vin的摆幅仍为正，NMOS管D1的栅极电压比源极电压低于Vp，R1(即第三电阻R1)取值一般在20kohm，隔离Vd射频信号对Vg电压的影响，而隔离电阻R2取值一般在5kohm左右，远小于D1的等效电阻，Vin正向电压摆幅会受R2和Cb3通路电荷泄放的影响，摆幅上限会受限制。
当射频输入端RFin的射频电压摆幅为负，幅度为Vp，一部分射频电压经过隔值电容Cb2馈入到前馈放大器中的M3的栅极，M3的漏极的射频电压摆幅会被反向为正，经过前馈电容Cb3后，节点Vd的射频电压摆幅为正，而M2的栅极射频电压Vin的摆幅仍为负，NMOS管D1的栅极电压比源极电压高于Vp，D1导通，将Vin钳位在(Vp+Vin0)-Vth，高于现有电路的Vin0-Vth，提高了负向摆幅的下限；选取合适的电路参数，使前馈放大器通过D1对Vin的负向摆幅的提升强于受R2、R1和偏置管M1通路的电荷泄放对Vin正向摆幅的限制，达到对放大管M2栅极直流电压的抬升目的，起到了补偿大信号增益的作用。该电路的静态电流建立时间取决于节点时间常数RC。
其中节点电阻Rnet2＝隔离电阻R1+R2＝25kohm；
节点电容Cnet2＝C1+Cb3+Cb1+Cgate≈2pF+2pF+4pF+2pF＝10pF，时间常数约为250ns，按4倍的时间常数估算，建立时间在1us左右，满足协议对功率放大器建立时间的要求。
本申请实施例的技术方案，在第一偏置电路和功率放大器之间设置包括二极管检波电路和前馈放大器的补偿电路，通过该补偿电路中的二级管检波电路能够实现在功率放大器的输入信号幅度变大的情况下，通过提高功率放大器的偏置电流(电压)来补偿因AM-AM失真出现的增益压缩。另一方面，通过该补偿电路中的前馈放大器能够满足移动通信协议对功率放大器建立时间的要求。本申请实施例的射频功率放大器幅度调制对幅度调制的补偿电路实现相对简单，设计灵活，通过调整补偿电路中的参数可以实现AMAM编程可调，适用性好，且易集成，成本低。
可选地，在图6中，二极管检波电路中的第一电阻R2为可变电阻，从而形成如图7所示的电路结构，通过改变R2的阻值，实现AM-AM补偿开启的功率 点和补偿幅度编程可控，达到增加电路的适用性和灵活性目的。
可选地，在图6中，射频功率放大器幅度调制对幅度调制的补偿电路中的前馈放大器的放大倍数为可调放大倍数，其中，所述前馈放大器中的所述第三晶体管M3的参数可调；和/或，所述前馈放大器中的所述第二偏置电路中的第一电流源Ib2的电流参数可调，从而形成如图8所示的电路结构，通过改变前馈放大器的放大倍数方法，来实现AM-AM补偿开启的功率点和补偿幅度编程可控。
可选地，在图6中，射频功率放大器幅度调制对幅度调制的补偿电路的补偿电路还包电路开关S1，所述电路开关S1的两端与所述第一晶体管D1的两端并联，从而形成如图9所示的电路结构，可以通过开关S1选择是否启用补偿电路，S1断开，补偿电路起作用，S1闭合，补偿电路不起作用。
可选地，在图6中，射频功率放大器幅度调制对幅度调制的补偿电路的功率放大器包括一个第二晶体管M2；或者，对第二晶体管M2的数量进行扩展，所述功率放大器包括多个第二晶体管M2，所述多个第二晶体管之间形成叠管结构，从而形成如图10所示的电路结构，其中，第二晶体管M2的数目为n，n为大于等于2的整数，图10给出的n个M2包括M21、M22、……、M2n，这n个M2之间形成叠管结构。
需要说明的是，本申请实施例中的晶体管的类型不只限于NMOS管，还可以是其他类型的功率晶体管，如异质结双极晶体管(Heterojunction Bipolar Transistor，HBT)双极结型晶体管(Bipolar Junction Transistor，BJT)等种类。

Claims (11)

  1. 一种射频功率放大器幅度调制对幅度调制的补偿电路，包括：第一偏置电路、功率放大器、以及位于所述第一偏置电路和所述功率放大器之间的补偿电路；其中，
    所述补偿电路包括二极管检波电路和前馈放大器，用于对幅度调制对幅度调制AM-AM失真进行补偿。
  2. 根据权利要求1所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，所述二极管检波电路包括：第一晶体管、以及与所述第一晶体管并联的第一电阻；其中，
    所述第一晶体管的栅极和漏极短接，并均与所述第一偏置电路连接；所述第一晶体管的源极与所述功率放大器的第一端连接，所述功率放大器的第一端为所述功率放大器中的第二晶体管的栅极。
  3. 根据权利要求1所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，所述前馈放大器包括：第一电容、第三晶体管以及第二电容；其中，
    所述第一电容的第一端与射频输入端连接，所述第一电容的第二端与所述第三晶体管的栅极连接；所述第三晶体管的源极与地端连接，所述第三晶体管的漏极与所述第二电容的第一端连接，所述第二电容的第二端与所述第一晶体管的漏极连接。
  4. 根据权利要求3所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，所述前馈放大器还包括第二偏置电路，用于为所述第三晶体管提供偏置电流；其中，
    所述第二偏置电路与所述第三晶体管的栅极连接。
  5. 根据权利要求4所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，所述前馈放大器还包括电压源、以及与所述电压源串联的第二电阻，用于为所述第三晶体管提供漏极偏置电压；其中，所述第二电阻连接所述第三晶体管的漏极。
  6. 根据权利要求2所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，所述二极管检波电路中的所述第一电阻为可变电阻。
  7. 根据权利要求4或5所述的射频功率放大器幅度调制对幅度调制的补偿 电路，其中，所述前馈放大器的放大倍数为可调放大倍数。
  8. 根据权利要求7所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，
    所述前馈放大器中的所述第三晶体管的参数可调；和/或，
    所述前馈放大器中的所述第二偏置电路的参数可调。
  9. 根据权利要求8所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，所述第二偏置电路的参数可调，至少包括：
    所述第二偏置电路中的第一电流源的电流参数可调。
  10. 根据权利要求2所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，所述补偿电路还包括电路开关，所述电路开关的两端与所述第一晶体管的两端并联。
  11. 根据权利要求1至10中任一项所述的射频功率放大器幅度调制对幅度调制的补偿电路，其中，
    所述功率放大器包括一个第二晶体管；或者，
    所述功率放大器包括多个第二晶体管，所述多个第二晶体管之间形成叠管结构。
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