WO2021051963A1 - 电压钳位电路和降压转换器 - Google Patents

电压钳位电路和降压转换器 Download PDF

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Publication number
WO2021051963A1
WO2021051963A1 PCT/CN2020/100368 CN2020100368W WO2021051963A1 WO 2021051963 A1 WO2021051963 A1 WO 2021051963A1 CN 2020100368 W CN2020100368 W CN 2020100368W WO 2021051963 A1 WO2021051963 A1 WO 2021051963A1
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Prior art keywords
voltage
mos transistor
output
unit
signal
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PCT/CN2020/100368
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English (en)
French (fr)
Inventor
严之嶽
李念龙
程剑涛
杜黎明
孙洪军
乔永庆
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上海艾为电子技术股份有限公司
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Publication of WO2021051963A1 publication Critical patent/WO2021051963A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the invention relates to the field of electronic circuits, in particular to a voltage clamping circuit and a step-down converter.
  • the buck converter is widely used in various electronic products because it can convert the input high DC voltage into a stable low DC voltage output.
  • an error amplifier is used to increase the loop gain
  • the soft start circuit is used to control the inductor current after the buck converter starts to start. Or the voltage reaches the default value in a progressive manner, and the voltage clamp circuit is used to clamp the output voltage of the error amplifier to a certain voltage value.
  • the soft start circuit and the voltage clamp circuit are both independent circuit structures.
  • the soft start circuit is usually set at the input end of the error amplifier, and the voltage clamp circuit is usually set at the output end of the error amplifier, resulting in a circuit structure More complicated.
  • the present invention proposes a voltage clamping circuit and a step-down converter to solve the problem of relatively complicated circuit structure in the existing solution.
  • the first aspect of the present invention discloses a voltage clamping circuit, including:
  • the timer is connected to the control unit
  • the signal generating unit is used to generate an incremental signal
  • the control unit is configured to receive the first voltage input to the control unit, and when the timing of the timer does not reach the predetermined time, control an input terminal of the control unit and an output terminal of the signal generation unit Connected, receiving the incremental signal generated by the signal generating unit, and controlling the first voltage to follow the incremental signal change;
  • the input terminal of the control unit is controlled to receive a fixed voltage, and if the first voltage is greater than the fixed voltage, the first voltage is controlled to perform voltage drop.
  • control unit includes:
  • the source of the first MOS transistor and the source of the second MOS transistor are respectively connected to a working voltage, and the drain of the first MOS transistor is respectively connected to the drain of the third MOS transistor and the fifth MOS transistor.
  • the drain of the MOS tube is connected, and the gate of the first MOS tube serves as the input terminal of the control unit;
  • the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor, and the gate of the second MOS transistor and the drain of the sixth MOS transistor are respectively connected to the first voltage;
  • the gate of the third MOS transistor is connected to the gate of the fourth MOS transistor, and the source of the third MOS transistor is grounded;
  • the gate of the fourth MOS transistor is connected to its drain, and the source of the fourth MOS transistor is grounded;
  • the gate of the fifth MOS transistor is respectively connected to its drain and the gate of the sixth MOS transistor, the source of the fifth MOS transistor is grounded, and the source of the sixth MOS transistor is grounded.
  • the signal generating unit includes:
  • the first terminal of the first capacitor receives the reference current, the second terminal is grounded, and the first terminal of the first capacitor receives the reference current as the output terminal of the signal generating unit.
  • control unit further includes:
  • the control switch is used to connect the input terminal of the control unit with the output terminal of the signal generating unit, or connect the input terminal of the control unit with a fixed voltage.
  • the incremental signal is equal to the fixed voltage.
  • the second aspect of the present invention discloses a step-down converter, including:
  • the output terminal of the error amplifier is connected to the voltage clamp circuit, and is used to output the first voltage to the control unit of the voltage clamp circuit.
  • step-down converter optionally, it further includes:
  • Compensation unit comparator, trigger, switch tube, diode, filter unit, feedback voltage generation unit and inductor current detection unit;
  • the compensation unit is respectively connected to the error amplifier and the voltage clamping circuit, and is used for compensating the first voltage output by the error amplifier;
  • the comparators are respectively connected to the voltage clamping circuit and the inductor current detection unit, and are used to receive the second voltage and the inductor current signal output by the inductor current detection unit, and are based on the second voltage and the inductor current detection unit.
  • An inductor current signal to output a comparison signal the second voltage is a voltage output after the compensation unit and the voltage clamp circuit process the first voltage;
  • the input terminal of the flip-flop is connected to the comparator, and the output terminal is connected to the gate of the switch tube for receiving a clock signal and the comparison signal output by the comparator, and according to the comparison signal and The clock signal outputs a trigger signal;
  • the gate of the switch tube is used to receive the trigger signal output by the trigger unit, and control the switch tube to be turned on or off according to the trigger signal, the source receives the input voltage, and the drain is connected to the trigger signal.
  • the cathode of the diode is connected to the filter unit, and the anode of the diode is grounded;
  • the inductor current detection unit is connected to the source of the switch tube, and outputs the inductor current signal according to the source voltage of the switch tube;
  • the filtering unit is connected to the feedback voltage generating unit, and is used to filter a third voltage, where the third voltage is the voltage at the common terminal of the switch tube and the diode;
  • the feedback voltage generating unit is connected to the error amplifier, and is configured to output the feedback voltage according to the output voltage output by the filtering unit;
  • the inverting input terminal of the error amplifier is used for receiving the feedback voltage output by the feedback voltage generating unit, and the non-inverting input terminal is used for receiving the reference voltage.
  • the compensation unit includes:
  • the first end of the second capacitor is connected to the output end of the error amplifier, the second end is connected to the first end of the first resistor, and the second end of the first resistor is grounded.
  • the filtering unit includes:
  • the first inductor and the third capacitor are The first inductor and the third capacitor;
  • the first terminal of the first inductor is connected to the drain of the switch tube, and the second terminal of the third capacitor is grounded; the common terminal of the first inductor and the third capacitor serves as the filter unit The output terminal outputs the output voltage.
  • the feedback voltage generating unit includes:
  • the first end of the second resistor is connected to the first end of the third resistor, and the second end is used as the input end of the feedback voltage generating unit to receive the output voltage.
  • the second end of the third resistor is The terminal is grounded, and the common terminal of the second resistor and the third resistor is used as the output terminal of the feedback voltage generating unit to output the feedback voltage.
  • the output terminal of the error amplifier is connected to the gate of the second MOS tube of the voltage clamping circuit.
  • the control unit, the timer, and the signal generation unit are integrated into the same circuit, and when the timing of the timer reaches the predetermined time, the control unit is controlled.
  • the input terminal of the control unit is connected to the output terminal of the signal generation unit, receives the incremental signal generated by the signal generation unit, and controls the first voltage to follow the incremental signal to change; and/or, when the timing of the timer reaches a predetermined time At the moment, the input terminal of the control control unit receives a fixed voltage.
  • the first voltage is controlled to perform a voltage drop, which simplifies the circuit difficulty and solves the complicated circuit structure of the existing step-down converter
  • the problem is that the integration of the control unit, the timer, and the signal generation unit in the same circuit can also save chip area and control the duty cycle of the circuit to 100% within a fixed time.
  • FIG. 1 is a schematic structural diagram of a voltage clamping circuit disclosed in an embodiment of the present invention
  • FIG. 2 is a schematic circuit diagram of a voltage clamping circuit disclosed in an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a voltage change of a reference current disclosed in an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of loop locking and voltage clamping changes disclosed in the embodiment of the present invention.
  • Fig. 5 is a schematic circuit diagram of a buck converter disclosed in an embodiment of the present invention.
  • an embodiment of the present application discloses a voltage clamping circuit, which includes a timer 101, a control unit 102 and a signal generation unit 103.
  • the timer 101 is connected to the control unit 102.
  • the signal generating unit 103 is used to generate an incremental signal
  • the control unit 102 is used to receive the first voltage input to the control unit, and when the timing of the timer 101 does not reach the predetermined time, an input end of the control control unit 102 is connected to the output end of the signal generation unit 103 to receive the signal Generating the incremental signal generated by the unit 103, and controlling the first voltage to follow the incremental signal change; and/or, when the timing of the timer 101 reaches a predetermined time, the input terminal of the control control unit 102 receives a fixed voltage, If the first voltage is greater than the fixed voltage, the first voltage is controlled to perform a voltage drop.
  • the timer 101 is a counter of the soft start time.
  • the predetermined time is the time when the soft start in the circuit starts.
  • the soft start time of the circuit can be adjusted by adjusting the timing of the timer 101.
  • one input terminal of the control unit 102 can be connected to the output terminal of the signal generating unit 103 by a control switch, and the input terminal of the control control unit 102 receives a fixed voltage.
  • the type of the control switch can be a single-pole double-throw switch.
  • the control switch can also be other types of switches.
  • the fixed voltage is the default value of the clamping voltage, which can be set according to the application environment and user selection.
  • the fixed voltage can be less than or equal to the working voltage VDD.
  • the value of the fixed voltage is generally equal to the maximum value of the voltage that needs to be clamped in the voltage clamping circuit, that is, equal to the working voltage VDD.
  • the incremental signal is equal to the fixed voltage.
  • an implementation manner of the signal generating unit 103 includes: a first capacitor C1.
  • the first terminal of the first capacitor C1 receives the reference current, and the second terminal is grounded.
  • the first terminal of the first capacitor C1 receiving the reference current is used as the output terminal of the signal generating unit.
  • the voltage change output by the signal generating unit 103 that is, the voltage change of the incremental signal, can be seen in FIG. 3, which is a voltage gradually increasing from 0 to the working voltage VDD.
  • the magnitude and change mode of the voltage output by the signal generating unit 103 can also be set by itself according to the application environment and user requirements, and this application does not make specific limitations, and all fall within the protection scope of this application.
  • an implementation of the control unit 102 includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, and a fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6.
  • the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are respectively connected to the operating voltage VDD, and the drain of the first MOS transistor M1 is respectively connected to the drain of the third MOS transistor M3 and the drain of the fifth MOS transistor.
  • M5 is connected, and the gate of the first MOS tube M1 serves as the input terminal of the control unit 102.
  • the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4, and the gate of the second MOS transistor M2 and the drain of the sixth MOS transistor M6 are respectively connected to the first voltage.
  • the gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4, and the source of the third MOS transistor M3 is grounded.
  • the gate of the fourth MOS transistor M4 is connected to its drain, and the source of the fourth MOS transistor M4 is grounded.
  • the gate of the fifth MOS transistor M5 is respectively connected to its drain and the gate of the sixth MOS transistor M6, the source of the fifth MOS transistor M5 is grounded, and the source of the sixth MOS transistor M6 is grounded.
  • the input terminal of the control control unit 102 is connected to the output terminal of the signal generating unit 103, that is, the gate of the first MOS transistor M1 is connected to the output terminal of the signal generating unit 103 ,
  • the incremental signal output by the output terminal of the receiving signal generating unit 103 because the incremental signal is a voltage signal that increases from 0 to the working voltage VDD, and the voltage signal received by the source of the first MOS transistor M1 is the working voltage VDD.
  • the gate-source voltage of the first MOS tube M1 When the gate-source voltage of the first MOS tube M1 is greater than the turn-on voltage of the first MOS tube M1, it can also be regarded as when the gate voltage of the first MOS tube M1 is lower than the source voltage of the first MOS tube M1, the first MOS tube M1 The tube M1 is turned on, and current flows through the source to the drain. Since the second MOS tube M2 and the first MOS tube M1 are mirror circuits, the second MOS tube M2 is also turned on, and the same current flows through the source. Drain.
  • the third MOS transistor M3 and the fourth MOS transistor M4 are also mirror circuits, and the fifth MOS transistor M5 and the sixth MOS transistor M6 are also mirror circuits.
  • the state changes of the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6 are the same as the state change of the first MOS tube M1.
  • the first MOS tube M1 is in the on state, the first MOS tube M1 is turned on.
  • the three MOS transistors M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are also in the on state, and the currents flowing through the third MOS transistor M3 and the fourth MOS transistor M4 are the same in magnitude, and flow through the first MOS transistor M3.
  • the currents of the fifth MOS tube M5 and the sixth MOS tube M6 are the same.
  • the state change of the second MOS transistor M2 to the sixth MOS transistor M6 is the same as the state change of the first MOS transistor M1, if the first MOS transistor M1 is turned on, the second M2 to the sixth MOS transistor M6 are also turned on, Therefore, when the gate voltage of the first MOS transistor M1 is less than the operating voltage VDD, the first M1 to the sixth MOS transistor M6 are all in the on state.
  • the control unit 102 forms a clamp for the first voltage. The path makes the first voltage follow the change of the gate voltage of the first MOS tube M1, that is, follow the change of the incremental voltage signal.
  • the input terminal of the control control unit 102 receives a fixed voltage, that is, the gate of the first MOS transistor M1 receives a fixed voltage.
  • the fixed voltage received by the gate of the first MOS transistor M1 is a fixed voltage value, for example, its magnitude is equal to the working voltage VDD. Therefore, the state of each MOS transistor in the control unit 102 is affected by the fixed voltage and the first For the control of a voltage, since the fixed voltage does not change, it can be regarded that the state of each MOS transistor in the control unit 102 is controlled by the first voltage.
  • the first MOS transistor M1 to the sixth MOS transistor M6 are turned on, stepping down the first voltage, and reducing the first voltage to a voltage value less than the fixed voltage, that is, to a value less than the fixed voltage.
  • Working voltage VDD is a voltage value less than the fixed voltage
  • the output signal of the output terminal of the signal generating unit 103 is a gradually increasing signal, that is, the clamp voltage set by the circuit at this time is gradually increasing. Voltage. With the gradual increase of the clamping voltage, the duty cycle of the buck converter where the voltage clamping circuit is located also gradually increases. When the clamping voltage reaches the working voltage VDD, the buck converter where the voltage clamping circuit is located The duty cycle is 100%.
  • the duty cycle when the loop is locked in the buck converter where the voltage clamping circuit is located can be set according to the application environment of the circuit and user requirements. This application does not specifically limit the value of the duty cycle in the buck converter where the voltage clamping circuit is located when the loop is locked, and all fall within the protection scope of this application.
  • the value of the set duty cycle Different, the predetermined time of the timer is also different, that is, it may exist that when the incremental signal generated by the signal generating unit reaches the working voltage VDD, the control unit has been switched to be connected to a fixed voltage.
  • the voltage change of the voltage clamp and the change of the duty cycle and the loop lock in the buck converter where the voltage clamp circuit is located can be shown in Figure 4.
  • the dotted line in the figure represents the voltage change of the voltage clamp, namely The change of the first voltage
  • the straight line represents the change of the first voltage when the loop of the buck converter where the voltage clamping circuit is located is locked
  • the sawtooth waveform represents the inherent waveform of the buck converter where the voltage clamping circuit is located
  • any two of the sawtooth wave The time difference between adjacent troughs is one cycle.
  • the control unit 102 by integrating the control unit 102, the timer 101 and the signal generating unit 103 in the same circuit, and by judging whether the timing of the timer 101 reaches the predetermined time, if the timing of the timer 101 reaches the predetermined time At time, the output terminal of the control control unit 102 is connected to the output terminal of the signal generation unit 103, and when the incremental signal generated by the signal generation unit 103 is received, the first voltage is controlled to follow the incremental signal change; if the timer 101 When the timing moment reaches the predetermined time, the input terminal of the control control unit 102 receives a fixed voltage.
  • the first voltage is controlled to perform a voltage drop, which simplifies the circuit difficulty and solves
  • the soft-start circuit and the voltage clamping circuit in the existing buck converter are independent, which leads to the problem of complicated circuit structure, and the control unit 102, the timer 101 and the signal generation unit 103 are integrated in the same circuit, It can also save chip area and control the duty cycle of the circuit to 100% in a fixed time.
  • the voltage clamp circuit only needs to be set with the output terminal of the error amplifier, and has the functions of a soft start circuit and a voltage clamp circuit, which reduces the complexity of the circuit structure; the voltage clamp circuit can also change the output of the error amplifier The voltage is clamped at an adjustable default value; and during soft start, the clamp circuit is used to gradually increase the output voltage of the error amplifier to achieve a gradual increase in the duty cycle, which can also avoid the occurrence of inrush current.
  • an embodiment of the present application discloses a buck converter, including:
  • the error amplifier 402 and the voltage clamp circuit 401 as described in any one of the above embodiments.
  • the output terminal of the error amplifier 402 is connected to the voltage clamping circuit 401, and is used to output the first voltage to the control unit of the voltage clamping circuit 401.
  • the buck converter provided by the embodiment of the present application may further include:
  • the compensation unit 403 is respectively connected to the error amplifier 402 and the voltage clamping circuit 401, and is used to compensate the first voltage output by the error amplifier 402.
  • the comparator 404 is connected to the voltage clamping circuit 401 and the inductor current detecting unit 408, respectively, for receiving the inductor current signal output by the second voltage and inductor current detecting unit 408, and outputting a comparison based on the second voltage and inductor current signal Signal, the second voltage is the voltage output after the compensation unit 403 and the voltage clamping circuit 401 process the first voltage.
  • the comparator 404 may be a PWM (Pulse Width Modulation, pulse width modulation) comparator.
  • the end of the comparator 404 connected to the inductor current detection unit 408 is the non-inverting input end of the comparator 404, that is, the non-inverting input end of the PWM comparator; the end of the comparator 404 connected to the voltage clamp circuit 401 is the opposite of the comparator 404 Phase input terminal, that is, the inverting input terminal of the PWM comparator.
  • the comparator 404 compares the received inductor current signal with the second voltage, and outputs the magnitude relationship between the inductor current signal and the second voltage, that is, outputs the corresponding high level or low level.
  • the input terminal of the flip-flop 405 is connected to the comparator 404, and the output terminal is connected to the gate of the switch tube P, for receiving the clock signal and the comparison signal output by the comparator 404, and outputting a trigger signal according to the comparison signal and the clock signal.
  • the trigger 405 may be an RS trigger.
  • the RS flip-flop is connected to the comparator 404 as: the reset input terminal R of the RS flip-flop is connected to the output terminal of the comparator 404; the RS flip-flop is connected to the gate of the switch tube P as: the output terminal Q of the RS trigger is connected to the switch tube The gate of P is connected; the set input S of the RS flip-flop is used to receive the clock signal.
  • clock signal can be self-defined according to the application environment and user needs. In practical applications, pulsed clock signals can generally be used.
  • the comparator 404 when the second voltage is greater than the inductor current signal, the comparator 404 outputs a comparison signal to reset the trigger unit 405, so that the switch P is turned off. At this time, the current flows from the ground to the first inductor L through the diode Z until the next clock signal causes the trigger unit 405 to flip again, and the switch tube P is set to turn on again to complete a cycle.
  • the ratio of the conduction time of the switch tube P to the entire cycle time is the duty cycle
  • the output voltage output by the buck converter is equal to the product of the input voltage and the duty cycle.
  • the switch tube P may be a PMOS tube.
  • the gate of the PMOS tube is used to receive the trigger signal output by the RS trigger, and control the PMOS tube to be turned on or off according to the trigger signal.
  • the source receives the input voltage, and the drain is connected to the cathode of the diode Z and the filter unit 406, respectively.
  • the anode of the diode Z is grounded.
  • the filtering unit 406 is connected to the feedback voltage generating unit 407 and is used for filtering the third voltage, which is the voltage of the common terminal of the PMOS transistor and the diode Z.
  • the feedback voltage generating unit 407 is connected to the error amplifier 401, and is used to generate the feedback voltage according to the output voltage output by the filtering unit 406.
  • the output terminal of the feedback voltage generating unit 407 is connected to the inverting input terminal of the error amplifier 401.
  • the inductor current detecting unit 408 is connected to the source of the PMOS tube, and outputs an inductor current signal according to the source voltage of the PMOS tube.
  • the inductor current detecting unit 408 may be an inductor current detector, or other circuits that can detect inductor current, which are not specifically limited in this application, and all belong to the protection scope of this application.
  • the inverting input terminal of the error amplifier 402 is used to receive the feedback voltage output by the feedback voltage generating unit 407, and the non-inverting input terminal is used to receive the reference voltage.
  • the error amplifier is generated according to the feedback voltage and the reference voltage, and outputs the first voltage, which acts as an increase in loop gain in the buck converter.
  • the control unit in the voltage clamping circuit is connected to the signal generating unit to control the first voltage to slowly change with the incremental signal, that is, to control the voltage value of the first voltage to zero.
  • the incremental signal continuously rises, the control first voltage also slowly rises, and the feedback voltage also continues to rise until the feedback voltage is equal to the reference voltage, forming a loop lock.
  • an implementation manner of the compensation unit 403 includes:
  • the first end of the second capacitor C2 is connected to the output end of the error amplifier 402, the second end is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded.
  • the second capacitor C2 is a compensation capacitor
  • the first resistor R1 is a compensation resistor.
  • Compensation capacitors are mainly used to compensate for errors caused by measurement, and compensation resistors are mainly used to compensate for the voltage and current asynchronous phenomenon in the circuit.
  • a specific implementation manner of the filtering unit 406 includes:
  • the first end of the first inductor L is connected to the drain of the PMOS transistor, and the second end of the third capacitor C3 is grounded.
  • the common terminal of the first inductor L and the third capacitor C3 is used as the output terminal of the filter unit 406 to output the output voltage.
  • the third voltage can be filtered by the first inductor L and the third capacitor C3, and the ripple of the output voltage output by the buck converter can be reduced.
  • the values of the first inductance L and the third capacitor C3 can be set by themselves according to the application environment and user requirements. This application does not make specific restrictions, and both fall within the protection scope of this application.
  • a specific implementation of the feedback voltage generating unit 407 includes:
  • the first end of the second resistor R2 is connected to the first end of the third resistor R3, the second end is used as the input end of the feedback voltage generating unit 407 to receive the output voltage, and the second end of the third resistor R3 is grounded.
  • the common terminal of the second resistor R2 and the third resistor R3 is used as the output terminal of the feedback voltage generating unit 407 to output the feedback voltage.
  • the buck converter provided in the embodiment of the present application includes an error amplifier 402 and the voltage clamping circuit 401 described in any one of the above embodiments.
  • the output terminal of the error amplifier 402 is connected to the voltage clamping circuit 401 for outputting the first voltage to the control unit of the voltage clamping circuit 401.
  • the voltage clamping circuit 401 is set to the circuit structure described in any of the above embodiments, which simplifies the circuit difficulty and solves the problem of the relatively complicated circuit structure in the existing step-down converter.
  • the improved voltage clamping circuit has a smaller volume and can be The area of the chip is saved, and at the same time, the voltage clamping circuit 401 can also ensure that the duty cycle in the circuit can reach 100% within a fixed time.
  • the buck converter provided in the embodiment of the present application further includes a compensation unit 403, a comparator 404, a trigger 405, a switch P, a diode Z, a filter unit 406, a feedback voltage generation unit 407, and an inductor.
  • the current detection unit 408 can use the clamp circuit 401 to gradually increase the output voltage of the error amplifier within a fixed period of time to achieve a gradual increase in the duty cycle, which can also avoid the occurrence of inrush current, and at the same time, reduce the voltage in the buck converter
  • the fixed voltage of the clamp circuit 401 is set to the inductor current protection value, which can also prevent the switching tube in the buck converter from burning out due to larger voltage and current, and realize real-time inductance for the switching tube in the buck converter. Current protection.
  • the step-down converter can be a DC-DC step-down converter
  • the voltage clamping circuit shown in this application can be applied to a DC-DC step-down converter whose voltage mode is PWM and a current mode. It is a PWM DC-DC step-down converter.
  • PWM DC-DC step-down converter a DC-DC step-down converter
  • it can also be applied to other types of buck converters, which are not limited in this application, and all fall within the protection scope of this application.

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Abstract

一种电压钳位电路和降压转换器，该电压钳位电路包括：定时器(101)、控制单元(102)和信号产生单元(103)；定时器与控制单元相连接；信号产生单元用于产生渐增式信号；控制单元用于接收输入到该控制单元的第一电压，并当定时器的定时时刻未达到预定时刻时，控制该控制单元的输入端与信号产生单元的输出端相连，接收信号产生单元产生的渐增式信号，并控制第一电压跟随渐增式信号变化；和/或，当定时器的定时时刻达到预定时刻时，控制该控制单元的输入端接收固定电压，若第一电压大于固定电压，则控制第一电压进行压降。通过将控制单元、定时器和信号产生单元集成于同一电路中，简化了电路难度。

Description

电压钳位电路和降压转换器
本申请要求于2019年9月16日提交中国专利局、申请号为201910870726.3、发明名称为“电压钳位电路和降压转换器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子电路领域，尤其涉及一种电压钳位电路和降压转换器。
背景技术
降压转换器因其能够实现将输入的高直流电压转换成稳定的低直流电压输出，而被广泛的应用于各种电子产品中。在降压转换器中，通常会设置有误差放大器、软启动电路和电压钳位电路等，误差放大器用于增加环路增益，软启动电路用于在降压转换器开始启动后，控制电感电流或电压以渐进式方式到达默认值，电压钳位电路用于实现误差放大器的输出电压钳位在某个电压值。
现有技术中，软启动电路和电压钳位电路均为独立的电路结构，软启动电路通常被设置于误差放大器的输入端，电压钳位电路通常被设置于误差放大器的输出端，导致电路结构较为复杂。
发明内容
基于上述现有技术的不足，本发明提出了一种电压钳位电路和降压转换器，以解决现有方案中电路结构较为复杂的问题。
为解决上述问题，现提出的方案如下：
本发明第一方面公开了一种电压钳位电路，包括：
定时器、控制单元和信号产生单元；
所述定时器与所述控制单元相连接；
所述信号产生单元用于产生渐增式信号；
所述控制单元用于接收输入到该控制单元的第一电压，并当所述定时器的定时时刻未达到预定时刻时，控制所述控制单元的一个输入端与所述信号产生单元的输出端相连，接收所述信号产生单元产生的所述渐增式信号，并控制所述第一电压跟随所述渐增式信号变化；
和/或，
当所述定时器的定时时刻达到所述预定时刻时，控制所述控制单元的所述输入端接收固定电压，若所述第一电压大于所述固定电压，则控制所述第一电压进行压降。
在上述电压钳位电路中，可选地，所述控制单元，包括：
第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管和第六MOS管；
所述第一MOS管的源极和所述第二MOS管的源极分别与工作电压相连，所述第一MOS管的漏极分别与所述第三MOS管的漏极和所述第五MOS管的漏极相连，所述第一MOS管的栅极作为所述控制单元的所述输入端；
所述第二MOS管的漏极与所述第四MOS管的漏极相连，所述第二MOS管的栅极和所述第六MOS管的漏极分别与所述第一电压相连；
所述第三MOS管的栅极与所述第四MOS管的栅极相连，所述第三MOS管的源极接地；
所述第四MOS管的栅极与其漏极相连，所述第四MOS管的源极接地；
所述第五MOS管的栅极分别与其漏极和所述第六MOS管的栅极相连，所述第五MOS管的源极接地，所述第六MOS管的源极接地。
在上述电压钳位电路中，可选地，所述信号产生单元，包括：
第一电容；
所述第一电容的第一端接收参考电流，第二端接地，所述第一电容接收所述参考电流的第一端作为所述信号产生单元的输出端。
在上述电压钳位电路中，可选地，所述控制单元，还包括：
控制开关；
所述控制开关用于将所述控制单元的输入端与所述信号产生单元的输出端相连，或者将所述控制单元的输入端与固定电压相连。
在上述电压钳位电路中，可选地，当所述定时器的定时时刻达到所述预定时刻时，所述渐增式信号等于所述固定电压。
本发明第二方面公开了一种降压转换器，包括：
误差放大器和如上所述电压钳位电路；
所述误差放大器的输出端和所述电压钳位电路相连，用于向所述电压钳位电路的控制单元输出第一电压。
在上述的降压转换器中，可选地，还包括：
补偿单元、比较器、触发器、开关管、二极管、滤波单元、回授电压产生单元及电感电流侦测单元；
所述补偿单元分别与所述误差放大器和所述电压钳位电路相连，用于对所述误差放大器输出的第一电压进行补偿；
所述比较器分别与所述电压钳位电路和所述电感电流侦测单元相连，用于接收第二电压和所述电感电流侦测单元输出的电感电流信号，并依据第二电压和所述电感电流信号，输出比较信号；所述第二电压为经所述补偿单元和所述电压钳位电路对所述第一电压处理后输出的电压；
所述触发器的输入端和所述比较器相连，输出端与所述开关管的栅极相连，用于接收时钟信号和所述比较器输出的所述比较信号，并依据所述比较信号和所述时钟信号，输出触发信号；
所述开关管的栅极用于接收所述触发单元输出的所述触发信号，并依据所述触发信号控制所述开关管的导通或者断开，源极接收输入电压，漏极分别与所述二极管的阴极和所述滤波单元相连，所述二极管的阳极接地；
所述电感电流侦测单元与所述开关管的源极相连，依据所述开关管的源极电压输出所述电感电流信号；
所述滤波单元和所述回授电压产生单元相连，用于对第三电压进行滤波，所述第三电压为所述开关管和所述二极管公共端的电压；
所述回授电压产生单元和所述误差放大器相连，用于依据所述滤波单元输出的输出电压，输出所述回授电压；
所述误差放大器的反相输入端用于接收所述回授电压产生单元输出的回授电压，同相输入端用于接收参考电压。
在上述的降压转换器中，可选地，所述补偿单元，包括：
第二电容和第一电阻；
所述第二电容的第一端和所述误差放大器的输出端相连，第二端和所述第一电阻的第一端相连，所述第一电阻的第二端接地。
在上述的降压转换器中，可选地，所述滤波单元，包括：
第一电感和第三电容；
所述第一电感的第一端与所述开关管的漏极相连，所述第三电容的第二端接地；所述第一电感和所述第三电容的公共端作为所述滤波单元的输出端，输出所述输出电压。
在上述的降压转换器中，可选地，所述回授电压产生单元，包括：
第二电阻和第三电阻；
所述第二电阻的第一端与所述第三电阻的第一端相连，第二端作为所述回授电压产生单元的输入端，接收所述输出电压，所述第三电阻的第二端接地，所述第二电阻和第三电阻的公共端作为所述回授电压产生单元的输出端，输出所述回授电压。
在上述的降压转换器中，可选地，所述误差放大器的输出端和所述电压钳位电路的第二MOS管的栅极相连。
从上述技术方案可以看出，本申请提供的电压钳位电路中，通过将控制单元、定时器和信号产生单元的集成于同一电路中，并当定时器的定时时刻到达预定时刻时，控制该控制单元的输入端与信号产生单元的输出端相连，接收到信号产生单元产生的渐增式信号，并控制第一电压跟随渐增式信号变化；和/或，当定时器的定时时刻达到预定时刻时，则控制控制单元的输入端接收固定电压，若第一电压大于固定电压，则控制第一电压进行压降，简化了电路难度，解决了现有降压转换器中电路结构较为复杂的问题，再者，将控制单元、定时器和信号产生单元的集成于同一电路，还可节省芯片面积，以及在固定时间内可控制电路中的占空比达到100％。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例公开的一种电压钳位电路的结构示意图；
图2为本发明实施例公开的一种电压钳位电路的电路示意图；
图3为本发明实施例公开的一种参考电流的电压变化示意图；
图4为本发明实施例公开的一种环路锁定及电压钳位变化示意图；
图5为本发明实施例公开的一种降压转换器的电路示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参阅图1，本申请实施例公开了一种电压钳位电路，包括：定时器101、控制单元102和信号产生单元103。
定时器101与控制单元102相连接。
所述信号产生单元103用于产生渐增式信号；
控制单元102用于接收输入到该控制单元的第一电压，并当定时器101的定时时刻未达到预定时刻时，控制控制单元102的一个输入端与信号产生单元103的输出端相连，接收信号产生单元103产生的渐增式信号，并控制第一电压跟随渐增式信号变化；和/或，当定时器101的定时时刻达到预定时刻时，控制控制单元102的该输入端接收固定电压，若第一电压大于固定电压，则控制第一电压进行压降。
需要说明的是，定时器101为软启动时间的计数器。预定时刻为电路中软启动开始启动的时刻。可通过调整定时器101的定时时刻来调整电路的软启动时间。
需要说明的是，可以采用控制开关控制控制单元102的一个输入端与信号产生单元103的输出端相连，以及控制控制单元102的该输入端接收固定电压。其中，控制开关的类型可为单刀双掷开关。当然，控制开关还可以是其他类型的开关。
需要说明的是，固定电压为钳位电压的默认值，可根据应用环境和用户选择自行设定大小，例如，固定电压可以小于或等于工作电压VDD。但在实际应用中，固定电压的取值一般等于电压钳位电路中需要进行钳位的电压最大 值，也即等于工作电压VDD。
需要说明的是，当定时器的定时时刻达到预定时刻时，渐增式信号等于固定电压。
请参见图2，在本申请的另一具体实施例中，该信号产生单元103的一种实施方式，包括：第一电容C1。
其中，第一电容C1的第一端接收参考电流，第二端端接地。第一电容C1接收参考电流的第一端作为信号产生单元的输出端。
在实际应用中，信号产生单元103输出的电压变化，即渐增式信号的电压变化可参见图3，为由0渐增至工作电压VDD的电压。
当然，信号产生单元103输出的电压的大小和变化方式，还可根据应用环境和用户需求自行设定，本申请不作具体限定，均属于本申请的保护范围。
同样参见图2，在本申请的另一具体实施例中，该控制单元102的一种实施方式，包括：第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4、第五MOS管M5和第六MOS管M6。
第一MOS管M1的源极和第二MOS管M2的源极分别与工作电压VDD相连，第一MOS管M1的漏极分别与第三MOS管M3的漏极和第五MOS管的漏极M5相连，第一MOS管M1的栅极作为控制单元102的输入端。
第二MOS管M2的漏极与第四MOS管M4的漏极相连，第二MOS管M2的栅极和第六MOS管M6的漏极分别与第一电压相连。
第三MOS管M3的栅极与第四MOS管M4的栅极相连，第三MOS管M3的源极接地。
第四MOS管M4的栅极与其漏极相连，第四MOS管M4的源极接地。
第五MOS管M5的栅极分别与其漏极和第六MOS管M6的栅极相连，第五MOS管M5的源极接地，第六MOS管M6的源极接地。
若定时器101判断出定时时刻未到达预定时刻，则控制控制单元102的输入端与信号产生单元103的输出端相连，也即第一MOS管M1的栅极与信号产生单元103的输出端相连，接收信号产生单元103的输出端输出的渐增式信号，由于渐增式信号为从0至工作电压VDD递增的电压信号，而第一MOS管M1的源极所接收的电压信号为工作电压VDD。当第一MOS管M1的栅源 电压大于第一MOS管M1的开启电压时，也可视为当第一MOS管M1的栅极电压小于第一MOS管M1的源极电压时，第一MOS管M1导通，有电流经源极流向漏极，由于第二MOS管M2和第一MOS管M1为镜像电路，所以第二MOS管M2也导通，同样也有大小一致的电流经源极流向漏极。
同理，第三MOS管M3和第四MOS管M4也为镜像电路、第五MOS管M5和第六MOS管M6也为镜像电路。第三MOS管M3、第四MOS管M4、第五MOS管M5以及第六MOS管M6的状态变化与第一MOS管M1的状态变化相同，当第一MOS管M1处于导通状态时，第三MOS管M3、第四MOS管M4、第五MOS管M5以及第六MOS管M6也处于导通状态，且流经第三MOS管M3和第四MOS管M4的电流大小相同，流经第五MOS管M5和第六MOS管M6的电流大小相同。因为第二MOS管M2至第六MOS管M6的状态变化与第一MOS管M1的状态变化相同，若第一MOS管M1导通，则第二M2至第六MOS管M6也均导通，故此，当第一MOS管M1的栅极电压均小于工作电压VDD时，第一M1至第六MOS管M6均处于导通状态，此时，控制单元102中形成对第一电压进行钳位的通路，使得第一电压跟随第一MOS管M1的栅极电压变化而变化，也即跟随渐增式电压信号变化。
若定时器101判断出定时时刻到达预定时刻，则控制控制单元102的输入端接收固定电压，也即第一MOS管M1的栅极接收固定电压。此时，第一MOS管M1的栅极所接收到的固定电压为一个固定的电压值，例如其大小等同于工作电压VDD，因此，控制单元102中各个MOS管的状态，受固定电压和第一电压的控制，由于固定电压不变，所以可视为控制单元102中各个MOS管的状态受第一电压控制。当第一电压大于固定电压时，则第一MOS管M1至第六MOS管M6导通，对第一电压进行降压，将第一电压降至小于固定电压的电压值，也即降至小于工作电压VDD。
需要说明的是，当定时器101判断出定时时刻未到达预定时刻，信号产生单元103的输出端输出信号为渐增式信号，也即此时电路设定的钳位电压为渐增式变化的电压。随着钳位电压的逐渐上升，电压钳位电路所在的降压转换器中的占空比也逐渐上升，当达到钳位电压为工作电压VDD时，电压钳位电路所在的降压转换器中的占空比为100％。
需要说明的是，可根据电路的应用环境和用户需求，设定电压钳位电路所在的降压转换器中环路锁定时的占空比。本申请对环路锁定时电压钳位电路所在的降压转换器中的占空比的取值不作具体限定，均属于本申请的保护范围，可选的，设定的占空比的取值不同，定时器的预定时刻也不同，即可能存在，信号产生单元产生的渐增式信号为到达工作电压VDD时，控制单元已切换至与固定电压相连。
电压钳位电路所在降压转换器中电压钳位的电压变化情况和占空比的变化情况以及环路锁定情况，可如图4所示，图中虚线表示电压钳位的电压变化情况，即第一电压的变化情况，直线表示电压钳位电路所在降压转换器的环路锁定时第一电压变化情况，锯齿波形表示电压钳位电路所在降压转换器中固有波形，锯齿波的任意两个相邻波谷之间的时间差为一个周期。
在本实施例中，通过将控制单元102、定时器101和信号产生单元103的集成于同一电路中，并通过判断定时器101的定时时刻是否到达预定时刻，若定时器101的定时时刻到达预定时刻，则控制控制单元102的输出端与信号产生单元103的输出端相连，在接收到信号产生单元103产生的渐增式信号时，控制第一电压跟随渐增式信号变化；若定时器101的定时时刻达到预定时刻，则控制控制单元102的该输入端接收固定电压，在接收到固定电压时，若第一电压大于固定电压，则控制第一电压进行压降，简化了电路难度，解决了现有降压转换器中的软启动电路和电压钳位电路均为独立，而导致电路结构较为复杂的问题，而将控制单元102、定时器101和信号产生单元103的集成于同一电路，还可节省芯片面积，以及在固定时间内可控制电路中的占空比达到100％。
并且，该电压钳位电路仅需要设置与误差放大器的输出端，同时具有软启动电路和电压钳位电路的功能，降低了电路结构的复杂度；该电压钳位电路还可将误差放大器的输出电压钳位在一个可调节的默认值；而在软启动时利用该钳位电路逐渐提高误差放大器的输出电压来达成将占空比逐渐上升，还可以避免突冲电流发生。
参阅图5，本申请实施例公开了一种降压转换器，包括：
误差放大器402和如上述任意一个实施例所述的电压钳位电路401。
误差放大器402的输出端和电压钳位电路401相连，用于向电压钳位电路401的控制单元输出第一电压。
可选的，参阅图5，本申请实施例提供的降压转换器还可以包括：
补偿单元403、比较器404、触发器405、开关管P、二极管Z、滤波单元406、回授电压产生单元407和电感电流侦测单元408。
补偿单元403分别与误差放大器402和电压钳位电路401相连，用于对误差放大器402输出的第一电压进行补偿。
比较器404分别与电压钳位电路401和电感电流侦测单元408相连，用于接收第二电压和电感电流侦测单元408输出的电感电流信号，并依据第二电压和电感电流信号，输出比较信号，第二电压为经补偿单元403和电压钳位电路401对第一电压处理后输出的电压。
需要说明的是，比较器404可以为PWM(Pulse Width Modulation，脉冲宽度调制)比较器。比较器404与电感电流侦测单元408相连的一端为比较器404的同相输入端，也即PWM比较器的同相输入端；比较器404与电压钳位电路401相连的一端为比较器404的反相输入端，也即PWM比较器的反相输入端。
还需要说明的是，比较器404通过将接收到的电感电流信号和第二电压进行比较，输出电感电流信号与第二电压之间的大小关系，即输出相应的高电平或低电平。
触发器405的输入端和比较器404相连，输出端与开关管P的栅极相连，用于接收时钟信号和比较器404输出的比较信号，并依据比较信号和时钟信号，输出触发信号。
可选地，触发器405可以是RS触发器。
RS触发器与比较器404相连为：RS触发器的复位输入端R与比较器404的输出端相连；RS触发器与开关管P的栅极相连为：RS触发器的输出端Q与开关管P的栅极相连；RS触发器的置位输入端S用于接收时钟信号。
需要说明的是，时钟信号可根据应用环境和用户需求自行定义。在实际应用中，一般可选用脉冲时钟信号。
在实际应用中，当第二电压大于电感电流信号，比较器404输出比较信号 重置触发单元405，使得开关管P断开。此时，电流由地通过二极管Z流向第一电感L，直至，下一个时钟信号，使得触发单元405重新翻转，设置开关管P重新导通，完成一个周期。
其中，在一个周期内，开关管P导通时间占整个周期时间的比值为占空比，而降压转换器所输出的输出电压等于输入电压与占空比的乘积。
可选的，开关管P可以为PMOS管。
PMOS管的栅极用于接收RS触发器输出的触发信号，并依据触发信号控制PMOS管的导通或者断开，源极接收输入电压，漏极分别与二极管Z的阴极和滤波单元406相连，二极管Z的阳极接地。
需要说明的是，当PMOS管导通时，电流方向由PMOS管流经第一电感L，当PMOS管P断开时，电流方向由二极管Z流经第一电感L。
滤波单元406和回授电压产生单元407相连，用于对第三电压进行滤波，第三电压为PMOS管和二极管Z公共端的电压。
回授电压产生单元407和误差放大器401相连，用于依据经过滤波单元406输出的输出电压，产生回授电压。
需要说明的是，回授电压产生单元407的输出端和误差放大器401的反相输入端相连。
电感电流侦测单元408与PMOS管的源极相连，依据PMOS管的源极电压输出电感电流信号。
需要说明的是，电感电流侦测单元408可以是电感电流侦测器，或则其他可以侦测电感电流的电路，本申请不作具体限定，均属于本申请的保护范围。
可选的，误差放大器402的反相输入端用于接收回授电压产生单元407输出的回授电压，同相输入端用于接收参考电压。
需要说明的是，误差放大器依据回授电压和参考电压产生，输出第一电压，在降压转换器中充当增加环路增益的作用。
需要说明的是，降压转换器刚上电时，回授电压的电压值为零，参考电压大于回授电压，误差放大器依据参考电压和回授电压，输出第一电压，该第一电压的电压值较大，此时，电压钳位电路中的控制单元和信号产生单元相连，实现控制第一电压随渐增式信号缓慢变化，即控制第一电压的电压值为零，随 着时间的推移，渐增式信号不断上升，控制第一电压也缓慢上升，同时回授电压也在不断上升，直至回授电压等于参考电压，形成环路锁定。
可选地，同样参见图5，在本申请一具体实施例中，补偿单元403的一种实施方式，包括：
第二电容C2和第一电阻R1。
第二电容C2的第一端和误差放大器402的输出端相连，第二端和第一电阻R1的第一端相连，第一电阻R1的第二端接地。
其中，第二电容C2为补偿电容，第一电阻R1为补偿电阻。补偿电容主要用于补偿测量产生的误差，补偿电阻主要用于补偿电路中电压和电流不同步现象。
可选地，同样参见图5，在本申请一具体实施例中，滤波单元406的一种具体实施方式包括：
第一电感L和第三电容C3。
第一电感L的第一端与PMOS管的漏极相连，第三电容C3的第二端接地。其中，第一电感L和第三电容C3的公共端作为滤波单元406的输出端，输出该输出电压。
需要说明的是，通过第一电感L和第三电容C3可对第三电压进行滤波，可减小降压转换器所输出的输出电压的纹波。
在实际应用中，第一电感L和第三电容C3的取值可根据应用环境和用户需求自行设定，本申请不作具体限制，均属于本申请的保护范围。
可选地，同样参见图5，在本申请一具体实施例中，回授电压产生单元407的一种具体实施方式，包括：
第二电阻R2和第三电阻R3。
第二电阻R2的第一端与第三电阻R3的第一端相连，第二端作为回授电压产生单元407的输入端，接收输出电压，第三电阻R3的第二端接地。第二电阻R2和第三电阻R3的公共端作为回授电压产生单元407的输出端，输出 回授电压。
需要说明的是，上述本发明实施例公开的降压转换器中的电压钳位电路401中具体的原理和执行过程，与上述本发明实施例公开的电压钳位电路相同，可参见上述本发明实施例公开的电压钳位电路的相应的部分，这里不再进行赘述。
在本申请实施例提供的降压转换器中，包括误差放大器402及上述任意一个实施例所述的电压钳位电路401。误差放大器402的输出端与电压钳位电路401相连，用于向电压钳位电路401的控制单元输出第一电压。将电压钳位电路401设置为上述任意实施例所述的电路结构，简化电路难度，解决了现有降压转换器中电路结构较为复杂的问题，改进后的电压钳位电路体积较小，可节省芯片的面积，同时，该电压钳位电路401还可以保证在固定时间内可将电路中的占空比达到100％。
可选的，在本申请实施例提供的降压转换器中，还包括补偿单元403、比较器404、触发器405、开关管P、二极管Z、滤波单元406、回授电压产生单元407及电感电流侦测单元408，实现在固定时间内利用该钳位电路401逐渐提高误差放大器的输出电压来达成将占空比逐渐上升，还可避免突冲电流发生，同时，将降压转化器中电压钳位电路401的固定电压设置为电感电流保护值，还能使降压转换器中开关管避免，因较大的电压电流导致的开关管烧毁，对降压转换器中的开关管实现实时电感电流保护。
最后，还需要说明的是，降压转换器可以为DC-DC降压转换器，本申请所示出的电压钳位电路可应用于电压模为PWM的DC-DC降压转换器和电流模为PWM的DC-DC降压转换器。当然，还可应用于其他类型的降压转换器，本申请不作具有限定，均属于本申请的保护范围。
专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来 将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。

Claims (11)

  1. 一种电压钳位电路，其特征在于，包括：
    定时器、控制单元和信号产生单元；
    所述定时器与所述控制单元相连接；
    所述信号产生单元用于产生渐增式信号；
    所述控制单元用于接收输入到该控制单元的第一电压，并当所述定时器的定时时刻未达到预定时刻时，控制所述控制单元的一个输入端与所述信号产生单元的输出端相连，接收所述信号产生单元产生的所述渐增式信号，并控制所述第一电压跟随所述渐增式信号变化；
    和/或，
    当所述定时器的定时时刻达到所述预定时刻时，控制所述控制单元的所述输入端接收固定电压，若所述第一电压大于所述固定电压，则控制所述第一电压进行压降。
  2. 根据权利要求1所述的电路，其特征在于，所述控制单元，包括：
    第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管和第六MOS管；
    所述第一MOS管的源极和所述第二MOS管的源极分别与工作电压相连，所述第一MOS管的漏极分别与所述第三MOS管的漏极和所述第五MOS管的漏极相连，所述第一MOS管的栅极作为所述控制单元的所述输入端；
    所述第二MOS管的漏极与所述第四MOS管的漏极相连，所述第二MOS管的栅极和所述第六MOS管的漏极分别与所述第一电压相连；
    所述第三MOS管的栅极与所述第四MOS管的栅极相连，所述第三MOS管的源极接地；
    所述第四MOS管的栅极与其漏极相连，所述第四MOS管的源极接地；
    所述第五MOS管的栅极分别与其漏极和所述第六MOS管的栅极相连，所述第五MOS管的源极接地，所述第六MOS管的源极接地。
  3. 根据权利要求1所述的电路，其特征在于，所述信号产生单元，包括：
    第一电容；
    所述第一电容的第一端接收参考电流，第二端接地，所述第一电容接收所 述参考电流的第一端作为所述信号产生单元的输出端。
  4. 根据权利要求1所述的电路，其特征在于，所述控制单元，还包括：
    控制开关；
    所述控制开关用于将所述控制单元的输入端与所述信号产生单元的输出端相连，或者将所述控制单元的输入端与固定电压相连。
  5. 根据权利要求1所述的电路，其特征在于，当所述定时器的定时时刻达到所述预定时刻时，所述渐增式信号等于所述固定电压。
  6. 一种降压转换器，其特征在于，包括：
    误差放大器和如权利要求1-5任一所述电压钳位电路；
    所述误差放大器的输出端和所述电压钳位电路相连，用于向所述电压钳位电路的控制单元输出第一电压。
  7. 根据权利要求6所述的降压转换器，其特征在于，还包括：
    补偿单元、比较器、触发器、开关管、二极管、滤波单元、回授电压产生单元及电感电流侦测单元；
    所述补偿单元分别与所述误差放大器和所述电压钳位电路相连，用于对所述误差放大器输出的第一电压进行补偿；
    所述比较器分别与所述电压钳位电路和所述电感电流侦测单元相连，用于接收第二电压和所述电感电流侦测单元输出的电感电流信号，并依据第二电压和所述电感电流信号，输出比较信号；所述第二电压为经所述补偿单元和所述电压钳位电路对所述第一电压处理后输出的电压；
    所述触发器的输入端和所述比较器相连，输出端与所述开关管的栅极相连，用于接收时钟信号和所述比较器输出的所述比较信号，并依据所述比较信号和所述时钟信号，输出触发信号；
    所述开关管的栅极用于接收所述触发单元输出的所述触发信号，并依据所述触发信号控制所述开关管的导通或者断开，源极接收输入电压，漏极分别与所述二极管的阴极和所述滤波单元相连，所述二极管的阳极接地；
    所述电感电流侦测单元与所述开关管的源极相连，依据所述开关管的源极电压输出所述电感电流信号；
    所述滤波单元和所述回授电压产生单元相连，用于对第三电压进行滤波， 所述第三电压为所述开关管和所述二极管公共端的电压；
    所述回授电压产生单元和所述误差放大器相连，用于依据所述滤波单元输出的输出电压，输出所述回授电压；
    所述误差放大器的反相输入端用于接收所述回授电压产生单元输出的回授电压，同相输入端用于接收参考电压。
  8. 根据权利要求7所述的降压转换器，其特征在于，所述补偿单元，包括：
    第二电容和第一电阻；
    所述第二电容的第一端和所述误差放大器的输出端相连，第二端和所述第一电阻的第一端相连，所述第一电阻的第二端接地。
  9. 根据权利要求7所述的降压转换器，其特征在于，所述滤波单元，包括：
    第一电感和第三电容；
    所述第一电感的第一端与所述开关管的漏极相连，所述第三电容的第二端接地；所述第一电感和所述第三电容的公共端作为所述滤波单元的输出端，输出所述输出电压。
  10. 根据权利要求7所述的降压转换器，其特征在于，所述回授电压产生单元，包括：
    第二电阻和第三电阻；
    所述第二电阻的第一端与所述第三电阻的第一端相连，第二端作为所述回授电压产生单元的输入端，接收所述输出电压，所述第三电阻的第二端接地，所述第二电阻和第三电阻的公共端作为所述回授电压产生单元的输出端，输出所述回授电压。
  11. 根据权利要求6所述的降压转换器，其特征在于，所述误差放大器的输出端和所述电压钳位电路的第二MOS管的栅极相连。
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