WO2021035798A1 - 一种在多核场景中自动切换外送数据的uart主控*** - Google Patents

一种在多核场景中自动切换外送数据的uart主控*** Download PDF

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WO2021035798A1
WO2021035798A1 PCT/CN2019/105012 CN2019105012W WO2021035798A1 WO 2021035798 A1 WO2021035798 A1 WO 2021035798A1 CN 2019105012 W CN2019105012 W CN 2019105012W WO 2021035798 A1 WO2021035798 A1 WO 2021035798A1
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uart
sending
command queue
control system
queue register
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PCT/CN2019/105012
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French (fr)
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林海锋
魏智汎
陈育鸣
洪振洲
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江苏华存电子科技有限公司
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Publication of WO2021035798A1 publication Critical patent/WO2021035798A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories

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  • the invention relates to the technical field of a UART master control system for automatically switching external data sources in a non-sequential manner, in particular to a UART master control system for automatically switching external data sources in a multi-core scenario.
  • the existing UART master control system needs the processor to observe the output state and configure the control register to switch the transmission data source when switching the sending data source, which not only consumes a lot of processor resources, but also greatly reduces the efficiency of data transmission at the sending end. If the sending module with multiple sending sources does not handle output monitoring and switching, it will cause the output data to be interleaved and confused in the same buffer, and it is not convenient to identify the data source. Therefore, an improved technology is urgently needed to solve the problem in the prior art. This problem exists.
  • the purpose of the present invention is to provide a UART master control system that automatically switches outgoing data in a multi-core scenario.
  • the CPU can fill in the command queue register and send characteristic data to the buffer to achieve non-transmission.
  • the processing method of sending the data source is automatically switched in order to solve the above-mentioned problems in the background art.
  • a UART master control system that automatically switches outgoing data in a multi-core scenario, including a UART master control system, an interface unit, a UART sending module, a command queue register, a buffer unit, A control unit and a sending port.
  • the UART master control system is provided with an interface unit and a UART sending module.
  • the UART sending module is provided with a command queue register, a number of buffer units, a control unit and a sending port.
  • the interface The units are respectively connected with a command queue register and a number of buffer units, the command queue register and the buffer unit are both connected with the control unit, and the control unit is connected with the sending port.
  • the command queue register and several buffers are connected to the CPU through an interface unit.
  • the command queue register is used to receive a data request command sent by the CPU.
  • control unit is used to read the commands in the command queue register.
  • the method of use includes the following steps:
  • Step 1 The CPU writes the send data request command to the command queue register
  • Step 2 The control unit that automatically switches the sending data source will read the command in the command queue register when it is idle, and switch to the designated sending buffer unit according to the read command;
  • Step 3 When the control unit reads the characteristic data from the sending buffer unit, it releases the sending buffer unit and returns to the idle state, and waits for the arrival of the next command.
  • the present invention is mainly applied in a system with multiple CPUs, and multiple cache units, a command queue register, and a control unit that automatically switch sending data sources need to be configured for use scenarios of multiple data sources.
  • the data sent by the CPU is confused in a buffer to facilitate the identification of the data source, which can realize accurate and automatic switching of the sending data source, and can make each CPU work independently when using the UART, reducing the communication between the CPU and the CPU, and improving the CPU Efficiency, also improves the efficiency of UART sending data overall.
  • the present invention uses a control unit and a command queue register to switch to the specified sending data source as required, and does not need to switch to the required sending data source one by one in order.
  • the present invention accelerates the speed of switching the sending data source in the UART system with multiple sending data sources.
  • Figure 1 is a schematic diagram of the structure of the present invention.
  • FIG. 2 is a schematic diagram of a situation where the control unit M of the present invention switches from reading data from the cache A to reading data from the cache B and then switching to the cache C to read data.
  • FIG. 3 is a schematic diagram of a situation where the control unit M of the present invention switches from reading data from the cache A to reading data from the cache C and then switching to the cache F to read data.
  • FIG. 4 is a schematic diagram of the situation where the data of the UART print sending buffer unit A is switched to the data of the print buffer C and then to the data of the print buffer F through the UART of the present invention (X represents an idle period).
  • Figure 5 is a schematic diagram of the internal transmission module of the UART master control system with only one transmission source.
  • Fig. 6 is a schematic diagram of the internal transmission module of the UART master control system with multiple transmission sources.
  • UART main control system 1 interface unit 2, UART sending module 3, command queue register 4, buffer unit 5, control unit 6, sending port 7.
  • the present invention provides a technical solution: a UART master control system that automatically switches outgoing data in a multi-core scenario, including a UART master control system 1, an interface unit 2, a UART sending module 3, and a command queue register 4.
  • the UART master control system 1 is equipped with an interface unit 2 and a UART sending module 3, and the UART sending module 3 is equipped with a command queue register 4 and several buffer units 5 ,
  • the control unit 6 and the sending port 7, the interface unit 2 is respectively connected to the command queue register 4 and a number of buffer units 5, the command queue register 4 and the buffer unit 5 are both connected to the control unit 6, the control unit 6 and the sending port 7 Phase connection.
  • command queue register 4 and all the cache units 5 are connected to the CPU through the interface unit 2.
  • the command queue register 4 is used to receive the data request command sent by the CPU.
  • control unit 6 that automatically switches the sending data source is used to read the commands in the command queue register 4.
  • the internal transmission module of the UART master control system with multiple transmission sources of the present invention has multiple buffer units, a control unit that automatically switches the transmission data source, a command queue register unit and a transmission port.
  • the system can switch to the designated sending data source at will, without switching in sequence.
  • a UART master control system that automatically switches outgoing data in a multi-core scenario, and its use method includes the following steps:
  • Step 1 The CPU writes the send data request command to the command queue register 4;
  • Step 2 The control unit 6 that automatically switches the sending data source will read the command in the command queue register 4 when it is idle, and switch to the designated sending buffer unit 5 according to the read command;
  • Step 3 When the control unit 6 reads the characteristic data from the sending buffer unit 5, it releases the sending buffer unit 5 and returns to the idle state, and waits for the next command to arrive.
  • processor C when processor A is printing data, processor C also wants to print data, then processor C must send a command to the command queue register, and when processor A sends the data, it will send it to the buffer A unit
  • processor A sends the data
  • the control unit recognizes the characteristic data, it releases the sending buffer A unit, and continues to read and execute the commands issued by the processor C in the command queue register, and the UART continues to print the data of the buffer unit designated by the processor C.
  • the internal transmission module of the UART master control system with multiple transmission sources has multiple buffer units, a control unit that automatically switches the transmission data source and the transmission port.
  • the system can only switch the data source sequentially.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

一种在多核场景中自动切换外送数据的UART主控***(1)，UART主控***(1)内部设置有接口单元(2)及UART发送模组(3)，UART发送模组(3)内部设置有命令队列寄存器(4)、若干个缓存单元(5)、控制单元(6)及发送端口(7)，接口单元(2)分别与命令队列寄存器(4)及若干个缓存单元(5)相连接，命令队列寄存器(4)及缓存单元(5)均与控制单元(6)相连接，控制单元(6)与发送端口(7)相连接，该***可以实现精准自动切换发送数据源，并且可以使得每个CPU在使用UART时独立工作，减少了CPU与CPU之间的沟通，提高CPU的效能，可以按要求切换到指定的发送数据源，不需要按顺序一个一个地切换到所需发送数据源，加速了切换发送数据源的速度。

Description

一种在多核场景中自动切换外送数据的UART主控*** 技术领域
本发明涉及非顺序自动切换外送数据源的UART主控***技术领域，具体为一种在多核场景中自动切换外送数据的UART主控***。
背景技术
现有UART主控***在切换发送数据源时需要处理器时实观测输出状态并配置控制寄存器来切换发送数据源，这样不仅大量消耗处理器资源且会使发送端传输数据的效率大幅下降。如果多发送源的发送模块不处理输出监控与切换的话,则会造成输出数据交错混乱在同一个缓存中的情况，不方便识别数据来源，因此，亟待一种改进的技术来解决现有技术中所存在的这一问题。
发明内容
本发明的目的在于提供一种在多核场景中自动切换外送数据的UART主控***，UART主控***在有多个发送数据源时CPU通过填写命令队列寄存器和向缓存发送特征数据来实现非顺序自动切换发送数据源的处理方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种在多核场景中自动切换外送数据的UART主控***，包括UART主控***、接口单元、UART发送模组、命令队列寄存器、缓存单元、控制单元及发送端口， 所述UART主控***内部设置有接口单元及UART发送模组，所述UART发送模组内部设置有命令队列寄存器、若干个缓存单元、控制单元及发送端口，所述接口单元分别与命令队列寄存器及若干个缓存单元相连接，所述命令队列寄存器及缓存单元均与控制单元相连接，所述控制单元与发送端口相连接。
优选的，所述命令队列寄存器及若干个缓存通过接口单元与CPU相连通。
优选的，所述命令队列寄存器用于接收CPU发送数据请求命令。
优选的，所述控制单元用于读取命令队列寄存器中的命令。
优选的，其使用方法包括以下步骤：
步骤一：CPU将发送数据请求命令写到命令队列寄存器中；
步骤二：自动切换发送数据源的控制单元会在空闲状态时去读取命令队列寄存器中的命令，并根据读取的命令切换到指定的发送缓存单元；
步骤三：当控制单元从发送缓存单元中读取到特征数据时候就释放该发送缓存单元并回到空闲状态，等待下一个命令的到来。
与现有技术相比，本发明的有益效果是：
(1)本发明主要应用在具有多个CPU的***中，需要多数据源的使用场景配置多个缓存单元，一个命令队列寄存器和一个自动切换 发送数据源的控制单元，这样不会使得多个CPU发送的数据混淆在一个缓存中，方便识别数据来源，可以实现精准自动切换发送数据源，并且可以使得每个CPU在使用UART时独立工作，减少了CPU与CPU之间的沟通，提高CPU的效能，也总体提高UART发送数据的效率。
(2)本发明使用一个控制单元和一个命令队列寄存器，可以按要求切换到指定的发送数据源，不需要按顺序一个一个得切换到所需发送数据源。
(3)本发明在有多个发送数据源的UART***中，加速了切换发送数据源的速度。
附图说明
图1为本发明的结构示意图。
图2为通过本发明控制单元M从缓存A读取数据切换到缓存B读取数据再切换到缓存C读取数据的状况示意图。
图3为通过本发明控制单元M从缓存A读取数据切换到缓存C读取数据再切换到缓存F读取数据的状况示意图。
图4为通过本发明UART打印发送缓存单元A的数据切换到打印缓存C的数据再切换到打印缓存F的数据的状况示意图(X表示空闲周期)。
图5为只有一个发送源的UART主控***的内部发送模块的示意 图。
图6为具有多发送源的UART主控***的内部发送模块的示意图。
图中：UART主控***1、接口单元2、UART发送模组3、命令队列寄存器4、缓存单元5、控制单元6、发送端口7。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明提供一种技术方案：一种在多核场景中自动切换外送数据的UART主控***，包括UART主控***1、接口单元2、UART发送模组3、命令队列寄存器4、缓存单元5、控制单元6及发送端口7，UART主控***1内部设置有接口单元2及UART发送模组3，UART发送模组3内部设置有命令队列寄存器4、若干个缓存单元5、控制单元6及发送端口7，接口单元2分别与命令队列寄存器4及若干个缓存单元5相连接，命令队列寄存器4及缓存单元5均与控制单元6相连接，控制单元6与发送端口7相连接。
其中，命令队列寄存器4及所有的缓存单元5通过接口单元2与CPU相连通。
其中，命令队列寄存器4用于接收CPU发送数据请求命令。
其中，自动切换发送数据源的控制单元6用于读取命令队列寄存器4中的命令。
本发明具有多个发送源的UART主控***的内部发送模块，有多个缓存单元，一个自动切换发送数据源的控制单元，一个命令队列寄存器单元和发送端口。该***可以随意切换到指定的发送数据源，无需按顺序切换。
一种在多核场景中自动切换外送数据的UART主控***，其使用方法包括以下步骤：
步骤一：CPU将发送数据请求命令写到命令队列寄存器4中；
步骤二：自动切换发送数据源的控制单元6会在空闲状态时去读取命令队列寄存器4中的命令，并根据读取的命令切换到指定的发送缓存单元5；
步骤三：当控制单元6从发送缓存单元5中读取到特征数据时候就释放该发送缓存单元5并回到空闲状态，等待下一个命令的到来。
如图2-4例如当处理器A正在打印数据时，处理器C也想打印数据，那么处理器C要发送命令到命令队列寄存器，当处理器A发送完数据后就会向缓存A单元发送特征数据，控制单元识别到特征数据就释放掉发送缓存A单元，继续读取命令队列寄存器中处理器C发的命 令并执行，UART也就继续打印处理器C指定缓存单元的数据，这种方案在多核的UART主控***中，可以减少CPU之间的沟通，提高CPU的效能，并提高UART在多核场景下的打印数据效率。
实施例一：
如图5所示，只有设置一个发送源的UART主控***的内部发送模块，内部只有一个缓存和发送端口，没有控制单元，CPU占用比较高。
实施例二：
如图6所示，设置有多个发送源的UART主控***的内部发送模块，有多个缓存单元，一个自动切换发送数据源的控制单元和发送端口。该***只能按顺序切换发送数据源。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (5)

  1. 一种在多核场景中自动切换外送数据的UART主控***，其特征在于：包括UART主控***(1)、接口单元(2)、UART发送模组(3)、命令队列寄存器(4)、缓存单元(5)、控制单元(6)及发送端口(7)，所述UART主控***(1)内部设置有接口单元(2)及UART发送模组(3)，所述UART发送模组(3)内部设置有命令队列寄存器(4)、若干个缓存单元(5)、控制单元(6)及发送端口(7)，所述接口单元(2)分别与命令队列寄存器(4)及若干个缓存单元(5)相连接，所述命令队列寄存器(4)及缓存单元(5)均与控制单元(6)相连接，所述控制单元(6)与发送端口(7)相连接。
  2. 根据权利要求1所述的一种在多核场景中自动切换外送数据的UART主控***，其特征在于：所述命令队列寄存器(4)及所有的缓存单元(5)通过接口单元(2)与CPU相连通。
  3. 根据权利要求1所述的一种在多核场景中自动切换外送数据的UART主控***，其特征在于：所述命令队列寄存器(4)用于接收CPU发送数据请求命令。
  4. 根据权利要求1所述的一种在多核场景中自动切换外送数据的UART主控***，其特征在于：所述控制单元(6)用于读取命令队列寄存器(4)中的命令。
  5. 根据权利要求1所述的一种在多核场景中自动切换外送数据的UART主控***，其特征在于：其使用方法包括以下步骤：
    步骤一：CPU将发送数据请求命令写到命令队列寄存器(4)中；
    步骤二：自动切换发送数据源的控制单元(6)会在空闲状态时去读取命令队列寄存器(4)中的命令，并根据读取的命令切换到指定的发送缓存单元(5)；
    步骤三：当控制单元(6)从发送缓存单元(5)中读取到特征数据时候就释放该发送缓存单元(5)并回到空闲状态，等待下一个命令的到来。
PCT/CN2019/105012 2019-08-27 2019-09-10 一种在多核场景中自动切换外送数据的uart主控*** WO2021035798A1 (zh)

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US6005674A (en) * 1996-02-27 1999-12-21 Lin; Feng System architecture for multiple input/output devices
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CN103778014A (zh) * 2012-10-25 2014-05-07 中兴通讯股份有限公司 多核终端共享资源的方法及装置
CN105137863A (zh) * 2015-07-31 2015-12-09 上海卫星工程研究所 空间飞行器控制管理SoC芯片

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005674A (en) * 1996-02-27 1999-12-21 Lin; Feng System architecture for multiple input/output devices
CN101763333A (zh) * 2008-12-08 2010-06-30 北京谊安医疗***股份有限公司 总线控制器及实现多主机通信的方法
CN103778014A (zh) * 2012-10-25 2014-05-07 中兴通讯股份有限公司 多核终端共享资源的方法及装置
CN105137863A (zh) * 2015-07-31 2015-12-09 上海卫星工程研究所 空间飞行器控制管理SoC芯片

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