WO2021030927A1 - 显示背板及其制作方法、显示装置 - Google Patents

显示背板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2021030927A1
WO2021030927A1 PCT/CN2019/100920 CN2019100920W WO2021030927A1 WO 2021030927 A1 WO2021030927 A1 WO 2021030927A1 CN 2019100920 W CN2019100920 W CN 2019100920W WO 2021030927 A1 WO2021030927 A1 WO 2021030927A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
target layer
display backplane
connection structure
metal film
Prior art date
Application number
PCT/CN2019/100920
Other languages
English (en)
French (fr)
Inventor
梁志伟
刘英伟
岳晗
玄明花
麦轩伟
曹占锋
王珂
王慧娟
袁广才
吕志军
卢鑫泓
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19932246.2A priority Critical patent/EP4016630A4/en
Priority to JP2020570027A priority patent/JP7464540B2/ja
Priority to CN201980001362.3A priority patent/CN112997314B/zh
Priority to US16/959,097 priority patent/US11600747B2/en
Priority to PCT/CN2019/100920 priority patent/WO2021030927A1/zh
Priority to CN201980003118.0A priority patent/CN113169149A/zh
Priority to US16/982,217 priority patent/US11764343B2/en
Priority to EP19930244.9A priority patent/EP3979317A4/en
Priority to PCT/CN2019/126708 priority patent/WO2020238173A1/zh
Publication of WO2021030927A1 publication Critical patent/WO2021030927A1/zh
Priority to US18/228,281 priority patent/US20230378414A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display backplane, a manufacturing method thereof, and a display device.
  • Micro-Light Emitting Diode (Micro-LED) display devices have self-luminescence, high brightness, high contrast, ultra-high resolution and color saturation, long life, fast response speed, Many advantages such as energy saving and wide adaptation to the environment can be applied to fields such as micro displays such as Augmented Reality (AR) or Virtual Reality (VR), medium-sized displays such as mobile TVs, and large-screen displays in theaters.
  • micro displays such as Augmented Reality (AR) or Virtual Reality (VR)
  • AR Augmented Reality
  • VR Virtual Reality
  • medium-sized displays such as mobile TVs
  • large-screen displays in theaters large-screen displays in theaters.
  • a display backplane in one aspect, includes: a substrate, a plurality of driving electrodes arranged on the substrate, and a connecting structure arranged on at least one of the plurality of driving electrodes, the connecting structure being on the substrate.
  • the orthographic projection on the bottom is located in the orthographic projection of the corresponding drive electrode on the substrate; wherein the connecting structure includes at least one conductive portion, and the at least one conductive portion is in a second shape with the corresponding drive electrode.
  • the value of the first included angle ranges from 85° to 95°.
  • connection structure further includes a bottom connected to the at least one conductive part, and the bottom is in direct contact with the corresponding driving electrode.
  • the at least one conductive part and the bottom in the same connection structure are an integral structure.
  • the at least one conductive part includes a plurality of conductive parts, and the plurality of conductive parts are arranged at intervals around the contour of the bottom.
  • the orthographic projection of the at least one conductive portion on the substrate is a closed pattern.
  • the at least one conductive part is a tubular structure.
  • the at least one conductive portion is a tubular structure with a side wall including at least one crack, and the at least one crack extends to an end wall surface of the tubular structure on a side away from the driving electrode.
  • the hardness of the at least one conductive part is greater than the hardness of the corresponding driving electrode.
  • the material of the at least one conductive part includes tungsten, titanium or molybdenum.
  • the display backplane further includes: a conductive plating layer disposed on the at least one conductive portion in each of the connection structures.
  • the display backplane has a plurality of sub-pixel regions; wherein, at least two driving electrodes of the plurality of driving electrodes are located in one sub-pixel region of the plurality of sub-pixel regions.
  • the display backplane further includes at least one driving transistor located in one sub-pixel region of the plurality of sub-pixel regions and disposed on the substrate.
  • the at least two driving electrodes are located on a side of the at least one driving transistor away from the substrate.
  • One of every two driving electrodes in the same sub-pixel area is electrically connected to a corresponding driving transistor.
  • a method for manufacturing a display backplane includes: providing a substrate; fabricating a plurality of driving electrodes on the substrate; fabricating a connection structure on at least one of the plurality of driving electrodes, the connection structure being The orthographic projection on the substrate is located within the orthographic projection of the corresponding drive electrode on the substrate, and the connection structure includes at least one conductive portion, and the at least one conductive portion is connected to the corresponding drive electrode. Set at the first angle.
  • forming a connection structure on at least one of the plurality of driving electrodes includes: stacking and forming a side of at least one of the plurality of driving electrodes away from the substrate The first target layer and the second target layer, the hardness of the second target layer is greater than the hardness of the first target layer; at least one through hole is formed through the second target layer and the first target layer, so The at least one through hole is located in an area where at least one of the plurality of drive electrodes is located, and the at least one through hole corresponds to the at least one drive electrode one to one; a first metal film is deposited, and the first The portion of the metal film located in each through hole of the at least one through hole is electrically connected to the corresponding driving electrode; the first metal film is patterned to retain the portion of the first metal film located in each through hole Part; removing the second target layer and the first target layer to form the connection structure.
  • the manufacturing method of the display backplane further includes: after the first metal film is located in each through hole The inner part is coated with photoresist. Patterning the first metal thin film further includes: patterning the first metal thin film by means of chemical mechanical polishing. Removing the second target layer and the first target layer to form the connection structure further includes: removing the second target layer, the first target layer and the photoresist to form the connection structure .
  • the manufacturing method of the display backplane further includes: coating photoresist, the photoresist covering at least The first metal film is located on the portion in each through hole; the photoresist is patterned to retain the portion of the photoresist corresponding to the portion in each through hole, wherein the The surface of the substrate is the reference plane, the surface of the patterned photoresist facing away from the substrate is not lower than the surface of the first metal film facing away from the substrate, and the patterned photoresist The size of the orthographic projection of the portion located in each through hole on the substrate is the same or substantially the same as the aperture of the corresponding through hole.
  • Removing the second target layer and the first target layer to form the connection structure further includes: removing the second target layer, the first target layer, and the patterned photoresist to form The connection structure.
  • the material of the first target layer is an organic insulating material
  • the material of the second target layer is an inorganic insulating material or a metal material.
  • a display device in another aspect, includes: the display backplane as described above; and one micro light emitting diode electrically connected to every two connection structures in the display backplane.
  • FIG. 1 is a schematic structural diagram of a display backplane according to some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of another display backplane according to some embodiments of the present disclosure.
  • Fig. 3 is a schematic structural diagram of another display backplane according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another display backplane according to some embodiments of the present disclosure.
  • Figure 5 is a top view of a connection structure according to some embodiments of the present disclosure.
  • Fig. 6 is a cross-sectional view of the connection structure shown in Fig. 5 in the A-A' direction;
  • Figure 7 is a top view of another connection structure according to some embodiments of the present disclosure.
  • Figure 8 is a cross-sectional view of the connection structure shown in Figure 7 in the direction of B-B';
  • Figure 9 is a top view of yet another connection structure in some embodiments of the present disclosure.
  • Figure 10 is a cross-sectional view of the connection structure shown in Figure 9 in the C-C' direction;
  • Figure 11 is a top view of yet another connection structure in some embodiments of the present disclosure.
  • Fig. 12 is a cross-sectional view of the connection structure shown in Fig. 11 along the D-D' direction;
  • Figure 13 is a top view of yet another connection structure in some embodiments of the present disclosure.
  • FIG. 14 is a schematic structural diagram of another display backplane according to some embodiments of the present disclosure.
  • FIG. 15 is a schematic structural diagram of another display backplane according to some embodiments of the present disclosure.
  • FIG. 16 is a flowchart of a manufacturing method of a display backplane according to some embodiments of the present disclosure.
  • FIG. 17 is a production flow chart of a display backplane according to some embodiments of the present disclosure.
  • FIG. 18 is a production flow chart of a conductive plating layer in a display backplane according to some embodiments of the present disclosure
  • FIG. 19 is a schematic structural diagram of a display device in some embodiments of the present disclosure.
  • each Micro-LED In a Micro-LED display device, the size of each Micro-LED is usually less than or equal to 100 ⁇ m, and the measurement accuracy of the distance between two adjacent Micro-LEDs is also on the order of microns.
  • the Micro-LED display device includes a display backplane, and each Micro-LED in the Micro-LED display device is generally transferred to the display backplane through Mass Transfer Technology (Mass Transfer Technology).
  • Mass Transfer Technology Mass Transfer Technology
  • the bonding between each Micro-LED and the corresponding electrode in the display backplane has problems of low efficiency, low yield and low reliability. .
  • the display backplane 100 includes a substrate 1, a plurality of driving electrodes 2 arranged on the substrate 1, and a connecting structure 3 arranged on at least one of the plurality of driving electrodes 2 and the connecting structure 3 is on the substrate 1.
  • the orthographic projection on 1 is within the orthographic projection of the corresponding drive electrode 2 on the substrate 1.
  • each of the at least one driving electrode 2 is correspondingly provided with a connecting structure 3.
  • Each connection structure 3 includes at least one conductive portion 31, and the at least one conductive portion 31 is arranged at a first angle ⁇ with the corresponding driving electrode 2.
  • the substrate 1 is configured to carry a plurality of driving electrodes 2 and a connection structure 3 provided on at least one driving electrode 2 and the like.
  • the substrate 1 may be a blank substrate, such as a glass substrate without any thin film; the multiple driving electrodes 2 are directly arranged on the glass substrate, so that the thickness of the entire display backplane 100 is relatively thin.
  • the substrate 1 includes at least one thin film.
  • the at least one film includes at least one of a polyimide film (PI layer for short), a buffer layer, or a light-shielding layer.
  • PI layer for short
  • a plurality of driving electrodes 2 and a driving circuit for providing signals to the plurality of driving electrodes 2 are provided on the substrate including the at least one thin film.
  • the PI layer or buffer layer can provide support for a plurality of driving electrodes 2 and driving circuits and buffer external forces to protect each driving electrode 2 and driving circuits.
  • Each connection structure 3 is provided on the surface of the driving electrode 2 facing away from the substrate 1, that is, each connection structure 3 is in direct contact with the corresponding driving electrode 2.
  • Each connection structure 3 includes at least one conductive portion 31, and the at least one conductive portion 31 and the corresponding driving electrode 2 are arranged at a first included angle ⁇ , and each conductive portion 31 is configured to be inserted into a pin of a corresponding micro electronic component .
  • each connection structure 3 can not only be electrically connected to the corresponding drive electrode 2, but also be well connected to the pins of the corresponding micro electronic component to transmit the drive signal of the corresponding drive electrode 2 to the corresponding micro electronic component. , So as to control the working status of the corresponding miniature electronic components.
  • the value range of the first included angle ⁇ between the at least one conductive portion 31 and the corresponding driving electrode 2 is in the range of 85° to 95°. That is, each conductive portion 31 of the at least one conductive portion 31 is perpendicular (or close to perpendicular) to the surface of the corresponding driving electrode 2 facing away from the substrate 1.
  • the conductive portions 31 in each connecting structure 3 can not only easily penetrate into the pins of the corresponding micro electronic components .
  • To achieve a good electrical connection by mutual diffusion that is, atoms in each conductive portion 31 migrate and penetrate into the corresponding pin, and atoms in each pin migrate and penetrate into the corresponding conductive portion 31) to achieve good electrical connection, and also ensure The force in the direction parallel to the plane where the substrate 1 is located is small or negligible, so as to avoid the force deformation and the problem of electrical connection failure due to deformation.
  • a plurality of connection structures 3 configured to connect the pins of the corresponding micro electronic components are arranged on the corresponding driving electrodes 2 in the display backplane 100, which is not only convenient for manufacturing, but also has low
  • the production cost of the plurality of connection structures 3 can be mass-produced in a large area; moreover, in the process of transferring a large number of micro electronic components to the display backplane 100, the plurality of connection structures 3 It can also effectively insert the pins of the corresponding micro electronic components, thereby effectively improving the bonding efficiency, bonding yield, and bonding reliability of each micro electronic component and the corresponding driving electrode 2 in the display backplane 100.
  • the orthographic projection of the at least one conductive portion 31 in each connection structure 3 on the substrate 1 is a closed pattern. That is, each connection structure 3 is surrounded by at least one conductive portion 31, so that the boundary pattern of the orthographic projection of each connection structure 3 on the substrate 1 is closed.
  • the boundary graphics of the orthographic projection of each connecting structure 3 on the substrate 1 is a circle, an ellipse, an arbitrary polygon, etc., where the circle, ellipse, or any polygon is a hollow or solid graphic.
  • the connecting structure 3 adopts a tubular structure, such as a round tube or a square tube.
  • the connecting structure 3 adopts a cone-shaped structure with a sharp top, such as a cone or a pyramid.
  • each connection structure 3 includes a plurality of conductive portions 31, wherein each conductive portion 31 is a tubular structure, and the plurality of conductive portions 31 have different tube diameters and are embedded in sequence. set. In this way, the orthographic projection of the connecting structure 3 on the substrate 1 is a plurality of hollow patterns nested one by one, as shown in FIG. 9.
  • the orthographic projection of the at least one conductive portion 31 in each connection structure 3 on the substrate 1 is a non-closed pattern. That is, each connection structure 3 is composed of at least two conductive parts 31 arranged at intervals, so that the boundary pattern of the orthographic projection of each connection structure 3 on the substrate 1 is not closed.
  • the orthographic projection of each connecting structure 3 on the substrate 1 includes a plurality of orthographic projection parts corresponding to each conductive portion 31 one by one, and the plurality of orthographic projection parts are scattered.
  • each connection structure 3 includes two conductive parts 31 that are opposite and spaced apart, and each conductive part 31 is a vertical sheet structure.
  • each connecting structure 3 is a tubular structure with at least one crack in the side wall, and the at least one crack extends to the end wall surfaces on both sides of the tubular structure, that is, the at least A fissure divides the tubular structure into at least two separate parts.
  • each connecting structure 3 is a tubular structure with at least one crack in the side wall, if one end of each of the at least one crack is located in the middle section of the tubular structure, the other end extends to the tubular structure
  • the boundary pattern of the orthographic projection of the tubular structure on the substrate 1 is a closed pattern.
  • connection structure 3 also includes a bottom 32 connected to its respective conductive portions 31.
  • the bottom 32 is in direct contact with the corresponding driving electrode 2, that is, the The bottom 32 is disposed on the surface of the side facing away from the substrate 1 corresponding to the driving electrode 2. This not only ensures that each connection structure 3 has high stability, but also increases the contact area between each connection structure 3 and the corresponding drive electrode 2, and improves the connection reliability between each connection structure 3 and the corresponding drive electrode 2. , And improve the transmission efficiency of the driving signal transmitted by the driving electrode 2.
  • each connecting structure 3 is connected to its conductive parts 31, and the shape of the bottom 32 is related to the surrounding shape of the conductive parts 31.
  • the surrounding shape of each conductive part 31 is tubular, and the bottom 32 is a closed figure, and matches the shape of the tube orifice enclosed by each conductive part 31, that is, each conductive part 31 is on the substrate
  • the inner contour of the upper orthographic projection coincides with the outer contour of the orthographic projection of the bottom 32 on the substrate; or the outer contour of the conductive portions 31 orthographically projected on the substrate and the outer contour of the orthographic projection of the bottom 32 on the substrate
  • each connection structure 3 includes a plurality of conductive parts 31 which are arranged at intervals around the contour of the bottom 32.
  • the orthographic projection of its bottom 32 on the substrate 1 is circular, and its conductive parts 31 are evenly distributed on the outline of the bottom 32, and each conductive part 31 is on the substrate.
  • the orthographic projection of is an arc that matches the circle.
  • the at least one conductive portion 31 and the corresponding bottom portion 32 in the same connecting structure 3 are an integral structure. That is, the at least one conductive portion 31 and the corresponding bottom portion 32 in the same connecting structure 3 are integrally formed with the same conductive material, which is convenient for manufacturing.
  • the hardness of the at least one conductive portion 31 in each connection structure 3 is greater than the hardness of the corresponding driving electrode 2.
  • the at least one conductive portion 31 in each connection structure 3 is made of a material with a Mohs hardness greater than or equal to 5.5, for example, made of tungsten, titanium or molybdenum. In this way, it can be ensured that the at least one conductive portion 31 has a relatively stable shape and a better support strength, and thus each connection structure 3 has a relatively stable shape and a better support strength.
  • each connection structure 3 further includes a bottom 32 connected to the at least one conductive portion 31, and the bottom 32 and each conductive portion 31 are made of the same material.
  • the bottom 32 is also in direct contact with the corresponding driving electrode 2, and the bottom 32 and the corresponding driving electrode 2 are made of the same material, which is also allowed.
  • the display backplane 100 further includes a conductive plating layer 8 disposed on the at least one conductive portion 31 in each connection structure 3.
  • the conductive plating layer 8 can surround the corresponding connection structure 3 on the corresponding drive electrode 2, so that the conductive plating layer 8 is used to electrically connect the corresponding connection structure 3 and the corresponding drive electrode 2, which is beneficial to improve the corresponding connection structure 3.
  • the surface conductivity of each connecting structure 3 and the corresponding driving electrode 2 and the corresponding micro-electronic components are enhanced.
  • the conductive plating layer 8 includes at least one of a copper layer, an aluminum layer, or a silver layer.
  • each connection structure 3 the arrangement of the conductive plating layer 8 on the at least one conductive portion 31 in each connection structure 3 is shown as being provided on the exposed surface of the at least one conductive portion 31, That is, the surface other than the surface in contact with the corresponding driving electrode 2.
  • the conductive plating layer 8 is also provided on the surface of the corresponding bottom 32 facing away from the substrate 1.
  • the arrangement of the conductive plating layer 8 on the at least one conductive portion 31 in each connection structure 3 is also shown as the edge of the conductive plating layer 8 extends to each connection
  • the driving motor 2 corresponding to the structure 3 is on the surface facing away from the substrate 1.
  • the display backplane 100 has a plurality of sub-pixel regions S arranged in an array, and at least two of the plurality of driving electrodes 2 are located in the plurality of sub-pixel regions S. Within one sub-pixel area S in the sub-pixel areas S.
  • the number of driving electrodes 2 provided in each sub-pixel region S is selected and set according to actual requirements, which is not limited in some embodiments of the present disclosure.
  • the miniature electronic component is a Micro-LED, which usually has two pins.
  • the above-mentioned display backplane 100 further includes at least one driving transistor 4 located in one sub-pixel region S of the plurality of sub-pixel regions S and disposed on the substrate 1, and disposed on the substrate A plurality of electrode lines 5 on 1, wherein the extension direction of each electrode line 5 is parallel (or close to parallel) with the extension direction of each row of sub-pixel regions S, or the extension direction of each electrode line 5 is parallel ( Or approaching parallel to the extension direction of the sub-pixel area S in each column.
  • Every two driving electrodes 2 in the same sub-pixel region S corresponds to one driving transistor 4, and the sub-pixel regions S in the same row or column correspond to one electrode line 5.
  • One of every two drive electrodes 2 in the same sub-pixel region S is electrically connected to the corresponding drive transistor 4, and the other is electrically connected to the corresponding electrode line 5.
  • Each of the two driving electrodes 2 is configured to control the corresponding Micro-LED to emit light or not to emit light under the driving of the corresponding driving transistor 4 and the corresponding electrode line 5.
  • each electrode line 5 is configured to provide a common voltage signal.
  • each electrode wire 5 is an integral structure, that is, each electrode wire 5 is made by using the same material in one patterning process.
  • each driving transistor 4 is located on the side of the corresponding driving electrode 2 close to the substrate 1.
  • Each driving transistor 4 adopts a bottom gate structure or a top gate structure.
  • each driving transistor 4 adopts a top gate structure.
  • each driving transistor 4 includes an active layer 41, a gate insulating layer 42, a gate 43 and an interlayer dielectric layer 44 stacked on the substrate 1 in sequence.
  • Each driving transistor 4 further includes a source 45 and a drain 46 disposed on a side of the interlayer dielectric layer 44 away from the gate 43, and the source 45 and the drain 46 are electrically connected to the corresponding active layer 41, respectively.
  • each electrode line 5 and the source 45 and drain 46 of each drive transistor 4 are arranged in the same layer, that is, each electrode line 5 and the source 45 and drain 46 of each drive transistor 4 can be made of the same material at one time. Finished in the composition process.
  • a planarization layer 6 and a passivation layer 7 are sequentially stacked between the drive transistor 4 and the corresponding drive electrode 2.
  • the drive electrode 2 passes through the planarization layer 6 and the passivation layer 7.
  • the via is electrically connected to the corresponding driving transistor 4.
  • Some embodiments of the present disclosure provide a manufacturing method of a display backplane for manufacturing the display backplane 100 provided by some of the above embodiments.
  • the manufacturing method of the display backplane includes S100-S300.
  • an electrode layer is deposited on the substrate 1 by sputtering deposition, and the electrode layer is patterned, that is, a mask is used in a patterning process
  • the electrode layer is etched to obtain the plurality of driving electrodes 2.
  • the thickness of the driving electrode 2 (that is, the size of the driving electrode 2 in a direction perpendicular to the substrate 1) is selected and set according to actual requirements.
  • the thickness of the driving electrode 2 ranges from 0.60 ⁇ m to 0.80 ⁇ m, for example, the thickness of the driving electrode 2 is 0.75 ⁇ m.
  • the driving electrode 2 is made of at least one of conductive metal materials such as titanium, aluminum, copper, or chromium.
  • the driving electrode 2 includes a titanium layer, an aluminum layer, and a titanium layer stacked in sequence, wherein the thickness of the titanium layer is 0.05 ⁇ m, the thickness of the aluminum layer is 0.65 ⁇ m, and the thickness of the titanium layer is 0.05 ⁇ m.
  • connection structure 3 Fabricate a connecting structure 3 on at least one of the driving electrodes 2 of the plurality of driving electrodes 2, and the orthographic projection of the connecting structure 3 on the substrate 1 is in the orthographic projection of the corresponding driving electrode 2 on the substrate 1, and
  • the connection structure 3 includes at least one conductive portion 31, and the at least one conductive portion 31 is arranged at a first angle ⁇ with the corresponding driving electrode 2.
  • connecting structure 3 on at least one driving electrode 2 is represented by fabricating at least one conductive portion 31 on the surface of each driving electrode 2 facing away from the substrate 1 in the at least one driving electrode 2 to realize each Each connection structure 3 has a good electrical connection with the corresponding driving electrode 2.
  • beneficial effects that can be achieved by the manufacturing method of the display backplane provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display backplane provided by some of the above embodiments, and will not be repeated here.
  • each conductive portion 31 in each connecting structure 3 described above is related to its structure, and it can be selected and set according to actual needs. Some embodiments of the present disclosure do not limit this.
  • fabricating the connection structure 3 on at least one of the plurality of driving electrodes 2 in the above S300 includes:
  • a first target layer 101 and a second target layer 102 are laminated to form a first target layer 101 and a second target layer 102 on a side facing away from the substrate 1 of at least one of the plurality of driving electrodes 2 ,
  • the hardness of the second target layer 102 is greater than the hardness of the first target layer 101.
  • the material of the first target layer 101 and the material of the second target layer 102 can be selected and set according to actual requirements.
  • the material of the first target layer 101 is an organic insulating material, and the organic insulating material includes a photosensitive resin material, such as a positive photoresist resin.
  • the material of the second target layer 102 is an inorganic material, such as silicon dioxide, or the material of the second target layer 102 is a metal material, such as aluminum, copper, tungsten, titanium, or molybdenum.
  • the material of the first target layer 101 is an organic insulating material
  • the material of the second target layer 102 is an inorganic material or a metal material.
  • the first target layer 101 is made of organic insulating materials by coating, and the second target layer 102 is made of inorganic materials or metal materials by chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD for short).
  • the thickness of the first target layer 101 (that is, the size of the first target layer 101 in a direction perpendicular to the substrate 1) is generally greater than the thickness of the second target layer 102.
  • the thickness of the first target layer 101 can be determined according to the requirements of the height of each conductive portion 31 in the corresponding connection structure 3 (that is, the size of the conductive portion 31 in a direction perpendicular to the substrate 1 ).
  • the thickness of the first target layer 101 ranges from 3 ⁇ m to 4 ⁇ m
  • the thickness of the second target layer 102 ranges from 0.15 ⁇ m to 0.25 ⁇ m.
  • At least one through hole 103 penetrating through the second target layer 102 and the first target layer 101 is formed, and the at least one through hole 103 is located in at least one of the plurality of driving electrodes 2 In the area where the driving electrode 2 is located, the at least one through hole 103 corresponds to the at least one driving electrode 2 one to one.
  • the thickness of the first target layer 101 is greater than the thickness of the second target layer 102, and the first target layer 101 with a larger thickness can ensure that the at least one through hole 103 formed has a larger height.
  • the hardness of the second target layer 102 is greater than that of the first target layer 101. Using the second target layer 102 with a higher hardness can ensure that the shape of the at least one through hole is stable and the hole wall is steep, thereby ensuring Each of the at least one through hole is accurately shaped.
  • the at least one through hole 103 is located in the area where the at least one drive electrode 2 is located, that is, the orthographic projection of each through hole 103 on the substrate 1 is located in the orthographic projection of the corresponding drive electrode 2 on the substrate 1. .
  • Each through hole 103 penetrates the second target layer 102 and the first target layer 101, that is, the surface of the area where the corresponding through hole 103 of the driving electrode 2 is located is exposed in the hole.
  • each through hole 103 and its formation method are related to the structure of each conductive portion 31 in the corresponding connection structure 3.
  • the connecting structure 3 is a conductive part in a circular tube shape, and the diameter of the corresponding through hole is the same as the tube outer diameter of the conductive part.
  • the connecting structure 3 is a conductive part of a polygonal tube shape, and the aperture of the corresponding through hole is the same as the largest diagonal dimension of the conductive part in a direction parallel to the substrate 1.
  • the diameter of each through hole 103 ranges from 1 ⁇ m to 8 ⁇ m.
  • a first metal film 104 is formed on the surface of the second target layer 102 facing away from the substrate 1 and in the at least one through hole 103, and the first metal film 104 is located in each The part in the through hole 103 covers the exposed surface of the corresponding driving electrode 2 and directly contacts the driving electrode 2.
  • the material of the first metal film 104 can be selected and set according to actual needs, which is not limited in some embodiments of the present disclosure.
  • the first metal thin film 104 is made of a metal material with a Mohs hardness ⁇ 5.5, as shown in Table 1 for example.
  • the second target layer 102 is made of inorganic materials or metal materials, and the second target layer 102 is usually removed by dry etching.
  • the first target layer 101 is made of an organic insulating material, and the first target layer 101 is usually removed by plasma etching, such as oxygen plasma etching.
  • the thickness of the portion of the first metal thin film 104 located on the surface of the second target layer 102 facing away from the substrate 1 is between 0.3 ⁇ m and 4.0 ⁇ m.
  • the thickness of the portion of the first metal film 104 located on the sidewall of each through hole 103 is between 0.1 ⁇ m and 2 ⁇ m.
  • the patterning of the first metal film 104 in S340 is completed by dry etching using a mask.
  • the opening pattern on the mask is determined according to the pattern design of the first metal film 104 to be formed.
  • the second target layer 102 is made of a metal material, and the second target layer 102 and the first metal thin film 104 can be patterned using the same mask.
  • the manufacturing process is simple and easy to implement, and can effectively shorten the process flow of the connection structure 3.
  • the patterning of the first metal thin film 104 in S340 is completed by chemical mechanical polishing (Chemical Mechanical Polish, CMP for short).
  • S340 includes: coating a photoresist on the portion of the first metal film 104 located in each through hole 103, and the photoresist protects the portion of the first metal film 104 located in each through hole 103. Then, the first metal film 104 is patterned by CMP to remove the part of the first metal film 104 that is not protected by the photoresist.
  • S350 also includes removing the aforementioned photoresist.
  • the above-mentioned photoresist is removed by plasma etching.
  • the above-mentioned photoresist and the first target layer 101 may be simultaneously removed by one plasma etching process.
  • the above-mentioned coating of photoresist on the part of the first metal film 104 located in each through hole 103 is to ensure that the photoresist is accurately aligned with the corresponding through hole 103, using light
  • the resist fills up or fills up each through hole 103. In this way, it is beneficial to obtain the connection structure 3 meeting the requirements through the protection of the photoresist.
  • the value range of the aperture of each through hole 103 is 0.1 ⁇ m to 1 m.
  • the step of patterning the first metal film 104 in S340 includes S341-S343.
  • a photoresist 105 is coated, and the photoresist 105 at least covers the part of the first metal film 104 in each through hole 103.
  • the photoresist 105 covers the entire surface of the first metal film 104 facing away from the substrate 1, and the surface of the photoresist 105 facing away from the substrate 1 is a substantially flat surface.
  • S342 Pattern the above-mentioned photoresist 105 to retain the part of the photoresist 105 corresponding to each through hole 103, where the surface of the substrate 1 is used as a reference plane, and the patterned photoresist 106 deviates The surface of the substrate 1 is not lower than the surface of the first metal film 104 facing away from the substrate 1, and the size of the orthographic projection of the patterned photoresist 106 in each through hole 103 on the substrate 1 corresponds to The apertures of the through holes 103 are the same or approximately the same.
  • the patterning of the above-mentioned photoresist 105 can be completed by plasma etching with equal thickness.
  • the etching amount of the photoresist is the same, which can ensure that the surface of the patterned photoresist 106 facing away from the substrate 1 and the first metal film 104 are not located in the through holes 103
  • the surface of the part facing away from the substrate 1 is flat or substantially flat. Therefore, the patterned photoresist 106 only remains in the part of each through hole 103, thereby protecting the part of the first metal film 104 in each through hole 103.
  • the first metal film 104 is patterned by dry etching or CMP, that is, the photoresist of the first metal film 104 that has not been patterned above 106 The protected part is removed.
  • S350 further includes removing the patterned photoresist 106.
  • the patterned photoresist 106 is removed by plasma etching.
  • the patterned photoresist 106 and the first target layer 101 may be simultaneously removed through a plasma etching process.
  • the second target layer 102 is made of a metal material, and the removal of the second target layer 102 and the patterning of the first metal film 104 can be completed in the same dry etching process or the same CMP process. In order to simplify the manufacturing process of each connection structure 3.
  • the photoresist 105 by coating a whole layer of photoresist 105 on the surface of the first metal film 104 facing away from the substrate 1, the photoresist 105 can be filled up naturally.
  • the surface of the patterned photoresist 106 facing away from the substrate 1 is no lower than the surface of the first metal film 104 facing away from the substrate 1, that is, the patterned photolithography
  • the glue 106 is the part of the photoresist 105 left in each through hole 103, which realizes the self-alignment of the patterned photoresist 106 and each through hole 103, and effectively improves its alignment accuracy, and then It is possible to ensure the molding accuracy of each corresponding connection structure 3, and realize mass production of each connection structure 3 in a large area.
  • the manufacturing method of the display backplane described above further includes S400.
  • the structure of the conductive plating layer 8 is shown in FIG. 3.
  • the conductive plating layer 8 is formed on the exposed surface of the corresponding connection structure 3 so that the conductive plating layer 8 surrounds the corresponding connection structure 3 on the corresponding driving electrode 2.
  • the structure of the conductive plating layer 8 is shown in FIG. 4.
  • the manufacturing method of the conductive plating layer 8 is shown in Fig. 18 (a) and (b).
  • a second metal film 105 is deposited by sputtering deposition, and the second metal film 105 at least covers the exposed surfaces of each driving electrode 2 and each connecting structure 3.
  • the second metal film 105 is patterned to obtain a conductive plating layer 8 disposed on each connection structure 3 and the corresponding driving electrode 2.
  • the second metal film 105 is made of at least one of copper, aluminum, or silver.
  • the patterning of the second metal thin film 105 is completed by dry etching using a mask.
  • the conductive plating layer 8 and the corresponding driving electrode 2 are formed by etching with the same pattern in the same mask, which is convenient to manufacture.
  • the conductive plating layer 8 is used to electrically connect the corresponding connection structure 3 and the corresponding drive electrode 2, which is beneficial to improve the surface conductivity of the corresponding connection structure 3, thereby enhancing the connection structure 3 and the corresponding drive.
  • the display device 200 includes a display backplane 100 as provided in some of the above embodiments, and one Micro-LED 9 electrically connected to every two connection structures 3 in the display backplane 100.
  • the number of pixels of a display device is usually on the order of millions.
  • the display has a resolution of 3840x2160 and has 8,294,400 pixels.
  • Each Micro-LED 9 corresponds to a primary color. That is, each pixel corresponds to three Micro-LEDs. This means that the display has 24,883,200 Micro-LEDs, and tens of millions of Micro-LEDs need to be bound in the display device.
  • the Micro-LED 9 usually includes an LED body 91 and two pins 92, the two pins 92 are arranged on the LED body 91 and are electrically connected to the corresponding two connection structures 3, respectively.
  • Each connection structure 3 is respectively arranged on the corresponding driving electrode 2.
  • the location of each drive electrode 2 is usually designed according to the location of the pin 92 in the corresponding Micro-LED 9 to ensure that each drive electrode 2 can be electrically connected to the corresponding pin 92 through the corresponding connection structure 3.
  • the orthographic projection of each pin 92 on the substrate 1 is within the orthographic projection of the corresponding drive electrode 2 on the substrate 1.
  • the overall size of the Micro-LED 9 is usually less than 100 ⁇ m.
  • the size of the pins 92 of the Micro-LED 9 is smaller than that of the Micro-LED 9, so that the pins 92 of the Micro-LED 9 are usually welded with metal. There are dots, and the electrical connection between the pin 92 of the Micro-LED 9 and the corresponding connection structure 3 is realized by plugging.
  • each connecting structure 3 facing away from the substrate 1 adopts a relatively sharp structure, such as sharp corners or thin walls, etc., so that in the process of transferring a large number of Micro-LED 9 to the display backplane 100, Each connecting structure 3 can effectively penetrate into the corresponding pin 92 to ensure that each connecting structure 3 can be electrically connected to the corresponding pin 92.
  • the alignment accuracy of the above-mentioned connecting structures 3 and the corresponding pins 92 is related to the molding accuracy in the related manufacturing process.
  • each connection structure 3 referring to the molding accuracy that can be achieved by its corresponding manufacturing process, that is, the possible alignment accuracy between each connection structure 3 and the corresponding pin 92, it can be reasonably determined that each connection structure 3 is Corresponds to the orthographic projection area on the driving electrode 2.
  • each connecting structure 3 and the corresponding pin 92 the design of the orthographic outline of each connecting structure 3 on the corresponding drive electrode 2 can be located where the corresponding pin 92 is located. In the area where the orthographic projection on the driving electrode 2 is located, a good electrical connection between each connection structure 3 and the corresponding pin 92 is ensured.
  • the orthographic outline of each connecting structure 3 on the corresponding drive electrode 2 may also be located at the corresponding pin 92
  • the orthographic projection on the driving electrode 2 is outside the area, and the orthographic projection of each connection structure 3 on the corresponding driving electrode 2 can cover the orthographic projection of the corresponding pin 92 on the driving electrode 2, so that the connection structure 3
  • the beneficial effects that can be achieved by the display device provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display backplane provided by some of the above embodiments, and will not be repeated here.
  • the material of the pin 92 of the Micro-LED 9 can be selected and set according to actual needs, which is not limited in some embodiments of the present disclosure.
  • the material of the pin 92 of the Micro-LED 9 is shown in Table 2.
  • each connection structure 3 in the display backplane 100 is greater than the hardness of the pin 92 of the corresponding Micro-LED 9. In this way, in the process of massively transferring multiple Micro-LEDs 9 to the display backplane 100 and binding the multiple Micro-LEDs 9 to the corresponding connection structure 3, each connection structure 3 can be inserted into the corresponding Micro-LED almost simultaneously. -In the pin 92 (that is, the metal solder joint) of the LED 9, a good electrical connection is achieved through inter-metal diffusion.
  • the aforementioned display device 200 is a product or component with a display function, such as a mobile phone, a tablet computer, a notebook computer, a monitor, or a television.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示背板（100），包括：衬底（1）、设置于衬底（1）上的多个驱动电极（2）、以及设置于多个驱动电极（2）中至少一个驱动电极（2）上的连接结构（3），连接结构（3）在衬底（1）上的正投影位于对应的驱动电极（2）在衬底（1）上的正投影内；其中，连接结构（3）包括至少一个导电部（31），至少一个导电部（31）与对应的驱动电极（2）呈第一夹角（ɑ）设置。

Description

显示背板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示背板及其制作方法、显示装置。
背景技术
随着显示技术的发展，微型发光二极管(Micro Light Emitting Diode，简称Micro-LED)显示装置因具有自发光、高亮度、高对比度、超高分辨率与色彩饱和度、长寿命、响应速度快、节能、适应环境宽泛等诸多优点，能够被应用至增强现实(Augmented Reality，简称AR)或虚拟现实(Virtual Reality，简称VR)等微显示、手机电视等中等尺寸显示到影院大屏幕显示等领域。
发明内容
一方面，提供一种显示背板。所述显示背板包括：衬底、设置于所述衬底上的多个驱动电极、以及设置于所述多个驱动电极中至少一个驱动电极上的连接结构，所述连接结构在所述衬底上的正投影位于对应的所述驱动电极在所述衬底上的正投影内；其中，所述连接结构包括至少一个导电部，所述至少一个导电部与对应的所述驱动电极呈第一夹角设置。
在一些实施例中，所述第一夹角的取值范围为85°～95°。
在一些实施例中，所述连接结构还包括与所述至少一个导电部相连接的底部，所述底部与对应的所述驱动电极直接接触。
在一些实施例中，同一个所述连接结构中的所述至少一个导电部与所述底部为一体结构。
在一些实施例中，所述至少一个导电部包括多个导电部，所述多个导电部环绕所述底部的轮廓间隔设置。
在一些实施例中，所述至少一个导电部在所述衬底上的正投影为封闭图形。
在一些实施例中，所述至少一个导电部为管状结构。
在一些实施例中，所述至少一个导电部为侧壁包括至少一个裂隙的管状结构，所述至少一个裂隙延伸至所述管状结构的远离所述驱动电极的一侧的端壁表面。
在一些实施例中，所述至少一个导电部的硬度大于对应的所述驱动电极的硬度。
在一些实施例中，所述至少一个导电部的材料包括钨、钛或钼。
在一些实施例中，所述显示背板还包括：设置于每个所述连接结构中的所述至少一个导电部上的导电性镀层。
在一些实施例中，所述显示背板具有多个子像素区域；其中，所述多个驱动电极中的至少两个驱动电极位于所述多个子像素区域中的一个子像素区域内。
在一些实施例中，所述显示背板还包括位于所述多个子像素区域中的一个子像素区域内且设置于所述衬底上的至少一个驱动晶体管。所述至少两个驱动电极位于所述至少一个驱动晶体管的背离所述衬底的一侧。同一个子像素区域内的每两个驱动电极中的一者与对应的一驱动晶体管电连接。
另一方面，提供一种显示背板的制作方法。所述显示背板的制作方法包括：提供一衬底；在所述衬底上制作多个驱动电极；在所述多个驱动电极中的至少一个驱动电极上制作连接结构，所述连接结构在所述衬底上的正投影位于对应的所述驱动电极在所述衬底上的正投影内，且所述连接结构包括至少一个导电部，所述至少一个导电部与对应的所述驱动电极呈第一夹角设置。
在一些实施例中，在所述多个驱动电极中的至少一个驱动电极上制作连接结构，包括：在所述多个驱动电极中的至少一个驱动电极的背离所述 衬底的一侧层叠形成第一目标层和第二目标层，所述第二目标层的硬度大于所述第一目标层的硬度；形成贯穿所述第二目标层和所述第一目标层的至少一个通孔，所述至少一个通孔位于所述多个驱动电极中的至少一个驱动电极所在的区域内，所述至少一个通孔与所述至少一个驱动电极一一对应；沉积第一金属薄膜，所述第一金属薄膜位于所述至少一个通孔中每个通孔内的部分与对应的驱动电极电连接；图案化所述第一金属薄膜以保留所述第一金属薄膜位于所述每个通孔内的部分；去除所述第二目标层和所述第一目标层，形成所述连接结构。
在一些实施例中，在沉积第一金属薄膜之后，以及图案化所述第一金属薄膜之前，所述显示背板的制作方法还包括：在所述第一金属薄膜位于所述每个通孔内的部分上涂覆光刻胶。图案化所述第一金属薄膜，还包括：采用化学机械研磨的方式，将所述第一金属薄膜图案化。去除所述第二目标层和所述第一目标层，形成所述连接结构，还包括：去除所述第二目标层、所述第一目标层和所述光刻胶，形成所述连接结构。
在一些实施例中，在沉积第一金属薄膜之后，以及图案化所述第一金属薄膜之前，所述显示背板的制作方法还包括：涂覆光刻胶，所述光刻胶至少覆盖在所述第一金属薄膜位于所述每个通孔内的部分上；图案化所述光刻胶，以保留所述光刻胶对应位于所述每个通孔内的部分，其中，以所述衬底的表面为基准面，图案化后的光刻胶的背离所述衬底的表面不低于所述第一金属薄膜的背离所述衬底的表面，所述图案化后的光刻胶位于所述每个通孔内的部分在所述衬底上的正投影的尺寸与对应的通孔的孔径相同或大致相同。去除所述第二目标层和所述第一目标层，形成所述连接结构，还包括：去除所述第二目标层、所述第一目标层以及所述图案化后的光刻胶，形成所述连接结构。
在一些实施例中，所述第一目标层的材料为有机绝缘材料，和/或，所述第二目标层的材料为无机绝缘材料或金属材料。
又一方面，提供一种显示装置。所述显示装置包括：如上所述的显示背板；以及，与所述显示背板中的每两个连接结构对应电连接的一个微发光二极管。
附图说明
为了更清楚地说明本公开一些实施例中的技术方案，下面将对一些实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为根据本公开一些实施例中的一种显示背板的结构示意图；
图2为根据本公开一些实施例中的另一种显示背板的结构示意图；
图3为根据本公开一些实施例中的又一种显示背板的结构示意图；
图4为根据本公开一些实施例中的又一种显示背板的结构示意图；
图5为根据本公开一些实施例中的一种连接结构的俯视图；
图6为图5所示的一种连接结构的A-A＇向的截面图；
图7为根据本公开一些实施例中的另一种连接结构的俯视图；
图8为图7所示的一种连接结构的B-B＇向的截面图；
图9为根据本公开一些实施例中的又一种连接结构的俯视图；
图10为图9所示的一种连接结构的C-C＇向的截面图；
图11为根据本公开一些实施例中的又一种连接结构的俯视图；
图12为图11所示的一种连接结构的D-D＇向的截面图；
图13为根据本公开一些实施例中的又一种连接结构的俯视图；
图14为根据本公开一些实施例中的又一种显示背板的结构示意图；
图15为根据本公开一些实施例中的又一种显示背板的结构示意图；
图16为根据本公开一些实施例中的一种显示背板的制作方法的流程图；
图17为根据本公开一些实施例中的一种显示背板的制作流程图；
图18为根据本公开一些实施例中的一种显示背板中导电性镀层的制作流程图；
图19为根据本公开一些实施例中的一种显示装置的结构示意图。
具体实施方式
下面将结合本公开一些实施例中的附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的一些实施例，本领域普通技术人员所能获得的所有其他实施例，都属于本公开保护的范围。
在Micro-LED显示装置中，每个Micro-LED的尺寸通常小于或等于100μm，且相邻两个Micro-LED之间的距离的度量精度也在微米量级。Micro-LED显示装置包括显示背板，Micro-LED显示装置中的各Micro-LED一般通过巨量转移技术(Mass Transfer Technology)转移至所述显示背板上。然而，在将各Micro-LED转移至所述显示背板上的过程中，各Micro-LED与显示背板中对应电极的绑定(Bonding)存在效率低、良率低和可靠性低的问题。
基于此，请参阅图1～图10，本公开的一些实施例提供了一种显示背板100。该显示背板100包括衬底1、设置于衬底1上的多个驱动电极2、以及设置于多个驱动电极2中至少一个驱动电极2上的连接结构3，该连接结构3在衬底1上的正投影位于对应的驱动电极2在衬底1上的正投影内。
此处，所述至少一个驱动电极2中的每个驱动电极2上对应设置一个连接结构3。每个连接结构3包括至少一个导电部31，所述至少一个导电部31与对应的驱动电极2呈第一夹角α设置。
衬底1配置为承载多个驱动电极2以及设置于至少一个驱动电极2上的连接结构3等。在一些示例中，衬底1可以为空白基板，例如未设有任何薄膜的玻璃基板；上述多个驱动电极2直接设置在玻璃基板上，从而整 个显示背板100的厚度较薄。
在另一些示例中，衬底1采用包括有至少一层薄膜的基板。此处，至少一层薄膜包括聚酰亚胺层(Polyimide Film，简称PI层)、缓冲层或遮光层中的至少一层。在包括该至少一层薄膜的基板上设置多个驱动电极2以及用于向多个驱动电极2提供信号的驱动电路。PI层或缓冲层等可以为多个驱动电极2和驱动电路提供支撑并缓冲外力，以保护各驱动电极2以及驱动电路。
每个连接结构3设置驱动电极2的背离衬底1的一侧表面上，也即每个连接结构3与对应的驱动电极2直接接触。每个连接结构3包括至少一个导电部31，且所述至少一个导电部31与对应的驱动电极2呈第一夹角α设置，各导电部31配置为插接对应微型电子元器件的引脚。这样每个连接结构3不仅可以与对应的驱动电极2电连接，还能与对应的微型电子元器件的引脚良好插接，以将对应驱动电极2的驱动信号传输至对应的微型电子元器件，从而控制对应的微型电子元器件的工作状态。
示例性的，请参阅图1、图6和图8，上述至少一个导电部31与对应的驱动电极2之间的第一夹角α的取值范围在85°～95°的范围内，也即所述至少一个导电部31中的每个导电部31垂直(或趋近于垂直)于对应的驱动电极2的背离衬底1的表面。这样在将每个连接结构3与对应微型电子元器件的引脚进行插接的过程中，每个连接结构3中的各导电部31不仅能够容易的刺入对应微型电子元器件的引脚中，以通过相互扩散(也即各导电部31中的原子迁移渗透至对应的引脚中，各引脚中的原子迁移渗透至对应的导电部31)的方式实现良好的电连接，还能够确保其沿平行于衬底1所在平面的方向上的受力较小或忽略不计，以避免其受力变形，以及因变形而导致出现电连接失效的问题。
在本公开的一些实施例中，将配置为连接对应微型电子元器件的引脚的多个连接结构3设置在显示背板100中对应的驱动电极2上，不仅方便 于制作，还具有较低的生产成本，从而能够实现该多个连接结构3在大面积范围的大量制作；而且，在将多个微型电子元器件巨量转移至显示背板100的过程中，利用该多个连接结构3还能够有效插接对应微型电子元器件的引脚，从而有效提高每个微型电子元器件与显示背板100中对应驱动电极2的绑定效率、绑定良率以及绑定可靠性。
在一些实施例中，请参阅图5～图10，每个连接结构3中的所述至少一个导电部31在衬底1上的正投影为封闭图形。也即，每个连接结构3由至少一个导电部31围成，使得每个连接结构3在衬底上1的正投影的边界图形封闭。
示例性的，每个连接结构3在衬底上1的正投影的边界图形为圆形、椭圆形、任意多边形等，其中，圆形、椭圆形或任意多边形为空心图形或实心图形，均可。相应的，若每个连接结构3在衬底上1的正投影为空心图形，则该连接结构3采用管状结构，例如圆管或方管等。若每个连接结构3在衬底上1的正投影为实心图形，则该连接结构3采用顶部呈尖角的锥状结构，例如圆锥或棱锥等。
此外，请参阅图9～图10，在一些示例中，每个连接结构3包括多个导电部31，其中，每个导电部31为管状结构，多个导电部31的管径不同且依次嵌套。如此，该连接结构3在衬底1上的正投影为逐一嵌套的多个空心图形，如图9所示。
在另一些实施例中，请参阅图11～图13，每个连接结构3中的所述至少一个导电部31在衬底1上的正投影为非封闭图形。也即，每个连接结构3由间隔设置的至少两个导电部31构成，使得每个连接结构3在衬底上1的正投影的边界图形不封闭。例如，每个连接结构3在衬底上1的正投影包括与其各导电部31一一对应的多个正投影部分，且该多个正投影部分分散设置。
在一些示例中，如图13所示，每个连接结构3包括两个相对且具有间 隔的导电部31，且每个导电部31为竖立的薄片结构。
在另一些示例中，如图11所示，每个连接结构3为侧壁包括至少一个裂隙的管状结构，所述至少一个裂隙延伸至所述管状结构两侧的端壁表面，也即该至少一个裂隙将所述管状结构分割为至少两个独立的部分。
此外，在每个连接结构3为侧壁包括至少一个裂隙的管状结构的情况下，若所述至少一个裂隙中每个裂隙的一端位于所述管状结构的中段，另一端延伸至所述管状结构的远离所述驱动电极的一侧的端壁表面，则所述管状结构在衬底1上的正投影的边界图形为封闭图形。
在上述一些实施例的基础上，请参阅图11～图12，每个连接结构3还包括与其各导电部31相连接的底部32，该底部32与对应的驱动电极2直接接触，也即该底部32设置于对应驱动电极2的背离衬底1的一侧表面上。这样不仅可以确保各连接结构3具有较高的稳定性，也可以增大每个连接结构3与对应驱动电极2的接触面积，提高每个连接结构3与对应驱动电极2之间的连接可靠性，以及提高驱动电极2所传输驱动信号的传输效率。
此处，每个连接结构3的底部32与其各导电部31相连接，该底部32的形状与所述各导电部31的围成形状相关。例如，所述各导电部31的围成形状为管状，底部32为封闭图形，且与所述各导电部31围成的管状的管口形状相匹配，即所述各导电部31在衬底上正投影的内轮廓与底部32在衬底上正投影的外轮廓的部分重合；或者所述各导电部31在衬底上正投影的外轮廓与底部32在衬底上正投影的外轮廓的部分重合从而底部32将所述各导电部31连接。
在一些示例中，请参阅图11和图12，每个连接结构3包括多个导电部31，该多个导电部31环绕底部32的轮廓间隔设置。例如，在每个连接结构3中，其底部32在衬底上1的正投影为圆形，其各导电部31均匀分布在该底部32的轮廓上，每个导电部31在衬底上1的正投影为与所述圆形相匹配的一段弧形。
此外，在一些示例中，同一个连接结构3中的所述至少一个导电部31与对应的底部32为一体结构。也即，同一个连接结构3中的所述至少一个导电部31与对应的底部32采用相同的导电材料一体成型，方便制作。
在一些实施例中，每个连接结构3中的所述至少一个导电部31的硬度大于对应的驱动电极2的硬度。示例性的，每个连接结构3中的所述至少一个导电部31采用莫氏硬度大于或等于5.5的材料制作形成，例如采用钨、钛或钼等制作形成。这样可以确保所述至少一个导电部31具有较为稳定的形状以及较好的支撑强度，进而确保每个连接结构3具有较为稳定的形状以及较好的支撑强度。
在一些示例中，每个连接结构3还包括与所述至少一个导电部31相连接的底部32，该底部32与各导电部31采用相同的材料制作形成。当然，该底部32还与对应的驱动电极2直接接触，该底部32与对应的驱动电极2采用相同的材料制作形成，也是允许的。
在一些实施例中，请参阅图3和图4，显示背板100还包括设置于每个连接结构3中的所述至少一个导电部31上的导电性镀层8。该导电性镀层8能够将对应的连接结构3围设在对应的驱动电极2上，这样利用导电性镀层8电连接对应的连接结构3以及对应的驱动电极2，有利于提高对应的连接结构3的表面导电性，进而增强各连接结构3与对应的驱动电极2以及对应的微型电子元器件之间的电连接性能。
在一些示例中，导电性镀层8包括铜层、铝层或银层中的至少一种。
上述导电镀层8的设置方式有多种。
在一些示例中，请参阅图3，该导电性镀层8在每个连接结构3中的所述至少一个导电部31上的设置方式，表现为设置在所述至少一个导电部31的裸露表面，也就是其除了与对应的驱动电极2接触的表面以外的表面。在每个连接结构3还包括底部32的情况下，该导电性镀层8还设置在对应的底部32的背离衬底1的一侧表面上。
在另一些示例中，请参阅图4，该导电性镀层8在每个连接结构3中的所述至少一个导电部31上的设置方式，还表现为导电性镀层8的边缘延伸至每个连接结构3所对应的驱动电机2的背离衬底1的表面上。
在一些实施例中，请参阅图14和图15，上述显示背板100具有呈阵列状排布的多个子像素区域S，所述多个驱动电极2中的至少两个驱动电极2位于上述多个子像素区域S中的一个子像素区域S内。
每个子像素区域S内设置的驱动电极2的数量根据实际需求选择设置，本公开的一些实施例对此不作限定。
在一些示例中，微型电子元器件为Micro-LED，Micro-LED通常具有两个引脚。每个子像素区域S内的驱动电极2通常成对设置，也即每个子像区域S内设置有2N(N＝1，2，3…)个驱动电极2。这样每个子像素区域S与N个Micro-LED对应。
基于此，请参阅图1，上述显示背板100还包括位于所述多个子像素区域S中的一个子像素区域S内且设置于衬底1上的至少一个驱动晶体管4，以及设置于衬底1上的多条电极线5，其中，每条电极线5的延伸方向平行(或趋近于平行)于每行子像素区域S的延伸方向，或者，每条电极线5的延伸方向平行(或趋近于平行)于每列子像素区域S的延伸方向。
同一个子像素区域S内的每两个驱动电极2与一个驱动晶体管4对应，同一行或同一列的子像素区域S与一条电极线5相对应。同一个子像素区域S内的每两个驱动电极2中的一者与对应的驱动晶体管4电连接，另一者与对应的电极线5电连接。所述每两个驱动电极2配置为在对应的驱动晶体管4和对应的电极线5的驱动下，控制对应的Micro-LED发光或不发光。
此处，每条电极线5配置为提供公共电压信号。可选的，各电极线5为一体结构，也即各电极线5采用相同的材料在一次构图工艺中制作形成。
上述每个驱动晶体管4的结构可以根据实际需求选择设置。每个驱动 晶体管4位于对应的驱动电极2的靠近衬底1的一侧。每个驱动晶体管4采用底栅结构或顶栅结构。示例性的，每个驱动晶体管4采用顶栅结构。请参阅图1，每个驱动晶体管4包括依次层叠设置在衬底1上的有源层41、栅绝缘层42、栅极43以及层间介质层44。每个驱动晶体管4还包括设置在层间介质层44的背离栅极43的一侧的源极45和漏极46，源极45和漏极46分别与对应的有源层41电连接。
上述各电极线5与各驱动晶体管4中的源极45以及漏极46同层设置，也即各电极线5与各驱动晶体管4中的源极45以及漏极46可以采用相同的材料在一次构图工艺中制作完成。
在一些示例中，请参阅图1，驱动晶体管4与对应的驱动电极2之间依次层叠设置有平坦层6和钝化层7，该驱动电极2穿过贯穿平坦层6和钝化层7的过孔与对应的驱动晶体管4电连接。利用平坦层6和钝化层7，可以将各驱动晶体管4的背离衬底1的一侧平坦化，以确保对应的各驱动电极2具有较好的平整度，避免各驱动电极2发生断裂的情况。
本公开的一些实施例提供了一种显示背板的制作方法，用于制作上述一些实施例提供的显示背板100。请参阅图16和图17，所述显示背板的制作方法包括S100～S300。
S100：提供一衬底1。
衬底1的结构根据实际需要选择设置，本公开的一些实施例对此不做限定。
S200：在衬底1上制作多个驱动电极2。
示例的，如图17中(a)所示，采用溅射沉积的方式在衬底1上沉积一电极层，并对该电极层进行图案化处理，也即利用掩膜在一次构图工艺中在对该电极层进行刻蚀，以得到所述多个驱动电极2。
此处，驱动电极2的厚度(也即驱动电极2沿垂直于衬底1的方向上的尺寸)根据实际需求选择设置。示例的，驱动电极2的厚度范围位于 0.60μm～0.80μm，例如驱动电极2的厚度为0.75μm。
此外，驱动电极2采用钛、铝、铜或铬等可导电金属材料中的至少一种制作形成。示例的，驱动电极2包括依次层叠设置的钛层、铝层和钛层，其中，钛层的厚度为0.05μm，铝层的厚度为0.65μm，钛层的厚度为0.05μm。
S300：在多个驱动电极2中的至少一个驱动电极2上制作连接结构3，该连接结构3在衬底1上的正投影位于对应的驱动电极2在衬底1上的正投影内，且连接结构3包括至少一个导电部31，所述至少一个导电部31与对应的驱动电极2呈第一夹角α设置。
上述在至少一个驱动电极2上制作连接结构3，表现为在所述至少一个驱动电极2中的每个驱动电极2的背离衬底1的一侧表面上制作至少一个导电部31，以实现每个连接结构3与对应驱动电极2的良好电连接。
本公开一些实施例提供的显示背板的制作方法所能实现的有益效果，与上述一些实施例提供的显示背板所能达到的有益效果相同，在此不做赘述。
上述每个连接结构3中的各导电部31的制作方法与其结构相关，根据实际需求选择设置即可。本公开的一些实施例对此不作限定。
示例性的，上述S300中在多个驱动电极2中的至少一个驱动电极2上制作连接结构3，包括：
S310：如图17中(b)所示，在所述多个驱动电2中的至少一个驱动电极2的背离衬底1的一侧层叠形成第一目标层101和第二目标层102，其中，第二目标层102的硬度大于第一目标层101的硬度。
在一些示例中，第一目标层101的材料和第二目标层102的材料，可以根据实际需求选择设置。可选的，第一目标层101的材料为有机绝缘材料，该有机绝缘材料包括感光树脂材料，例如正性光刻胶树脂。可选的，第二目标层102的材料为无机材料，例如二氧化硅，或者，第二目标层102的材料为金属材料，例如铝、铜、钨、钛或钼等。可选的，第一目标层101 的材料为有机绝缘材料，且第二目标层102的材料为无机材料或金属材料。
第一目标层101采用有机绝缘材料通过涂覆的方式制作形成，第二目标层102采用无机材料或金属材料通过化学气相沉积的方式(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)制作形成。第一目标层101的厚度(也即第一目标层101沿垂直于衬底1的方向上的尺寸)通常大于第二目标层102的厚度。
此处，第一目标层101的厚度，可以根据对应连接结构3中各导电部31的高度(也即导电部31沿垂直于衬底1的方向上的尺寸)的需求确定。示例性的，第一目标层101的厚度的取值范围为3μm～4μm，第二目标层102的厚度的取值范围为0.15μm～0.25μm。
S320：如图17中(c)所示，形成贯穿第二目标层102和第一目标层101的至少一个通孔103，所述至少一个通孔103位于上述多个驱动电极2中的至少一个驱动电极2所在的区域内，所述至少一个通孔103与所述至少一个驱动电极2一一对应。
此处，第一目标层101的厚度大于第二目标层102的厚度，利用厚度较大的第一目标层101能够确保所形成的所述至少一个通孔103具有较大的高度。第二目标层102的硬度大于第一目标层101的硬度，利用硬度较大的第二目标层102能够确保所形成的所述至少一个通孔的孔口形状稳定且孔壁陡直，从而确保所述至少一个通孔中的每个通孔准确成型。
所述至少一个通孔103位于所述至少一个驱动电极2所在的区域内，也即每个通孔103在衬底1上的正投影位于对应的驱动电极2在衬底1上的正投影内。各通孔103贯穿第二目标层102和第一目标层101，也即驱动电极2的对应通孔103所在区域的表面裸露于其孔内。
各通孔103的形状及其形成方式，与对应连接结构3中各导电部31的结构相关。例如，连接结构3为圆管状的一个导电部，该对应通孔的孔径与该导电部的管外径相同。或者，还例如，连接结构3为多边形管状的 一个导电部，该对应通孔的孔径与该导电部沿平行于衬底1方向上的最大的对角线尺寸相同。可选的，每个通孔103的孔径的取值范围为1μm～8μm。
S330：如图17中(d)所示，沉积第一金属薄膜104，第一金属薄膜104位于所述至少一个通孔103中每个通孔103内的部分与对应的驱动电极2电连接。
示例的，采用溅射沉积的方式，在第二目标层102的背离衬底1的一侧表面上以及所述至少一个通孔103内形成第一金属薄膜104，第一金属薄膜104位于每个通孔103内的部分覆盖对应驱动电极2的裸露表面，与驱动电极2直接接触。
第一金属薄膜104的材料可以根据实际需要选择设置，本公开的一些实施例对此不作限定。示例性的，第一金属薄膜104采用莫氏硬度≥5.5的金属材料制作形成，例如表1中所示。
Figure PCTCN2019100920-appb-000001
表1
S340：图案化第一金属薄膜104以保留第一金属薄膜104位于每个通孔103内的部分。
S350：去除第二目标层102和第一目标层101，形成连接结构3。
此处，第二目标层102采用无机材料或金属材料制作形成，第二目标层102通常采用干法刻蚀的方式去除。第一目标层101采用有机绝缘材料制作形成，第一目标层101通常采用等离子体刻蚀的方式去除，例如氧等离子体刻蚀。
此外，可选的，第一金属薄膜104中位于第二目标层102的背离衬底 1的一侧表面上的部分的厚度取值位于0.3μm～4.0μm。第一金属薄膜104中位于每个通孔103的侧壁上的部分的厚度取值位于0.1μm～2μm。这样在将第一金属薄膜104图案化并保留第一金属薄膜104位于每个通孔103内的部分后，能够确保所形成的连接结构3在具有所需机械强度的基础上还能实现良好的电性连接。
上述S340中，图案化第一金属薄膜104的方式可以有多种，根据实际需求选择设置即可。本公开的一些实施例对此不作限定。
在一些示例中，S340中第一金属薄膜104的图案化，利用掩膜进行干法刻蚀完成。掩膜上的开口图案根据第一金属薄膜104的待成形图案设计确定。此外，可选的，第二目标层102采用金属材料制作形成，第二目标层102与第一金属薄膜104能够利用同一掩膜进行图案化。该制作工艺简单易实现，可以有效缩短连接结构3的工艺流程。
在另一些示例中，S340中第一金属薄膜104的图案化采用化学机械研磨(Chemical Mechanical Polish，简称CMP)的方式完成。
例如，S340包括：在第一金属薄膜104位于每个通孔103内的部分上涂覆光刻胶，该光刻胶对第一金属薄膜104位于每个通孔103内的部分形成保护。然后采用CMP的方式将第一金属薄膜104图案化，以将第一金属薄膜104未被该光刻胶保护的部分去除。
对应的，S350中还包括去除上述光刻胶。例如，采用等离子体刻蚀的方式去除上述光刻胶。在一些示例中，上述光刻胶和第一目标层101可以通过一次等离子体刻蚀工序同时去除。
需要补充的是，上述在第一金属薄膜104位于每个通孔103内的部分上涂覆光刻胶，也就是在确保该光刻胶与对应通孔103精准对位的基础上，利用光刻胶填平或填满每个通孔103。如此，有利于通过光刻胶的保护来获得符合需求的连接结构3。
在又一些示例中，每个通孔103的孔径的取值范围为每个通孔103的 孔径的取值范围为0.1μm～1μm。S340中图案化第一金属薄膜104的步骤包括S341～S343。
S341：如图17中(e)所示，涂覆光刻胶105，该光刻胶105至少覆盖在第一金属薄膜104位于每个通孔103内的部分上。
示例性的，光刻胶105覆盖在第一金属薄膜104的背离衬底1的整个表面上，且该光刻胶105的背离衬底1的一侧表面为基本平整的表面。
S342：图案化上述光刻胶105，以保留该光刻胶105对应位于每个通孔103内的部分，其中，以衬底1的表面为基准面，图案化后的光刻胶106的背离衬底1的表面不低于第一金属薄膜104的背离衬底1的表面，图案化后的光刻胶106位于每个通孔103内的部分在衬底1上的正投影的尺寸与对应的通孔103的孔径相同或大致相同。
此处，对上述光刻胶105的图案化，可以采用等离子体等厚刻蚀的方式完成。这样在垂直于衬底1的方向上，光刻胶的刻蚀量相同，可以确保图案化后的光刻胶106的背离衬底1的表面与第一金属薄膜104未位于各通孔103内的部分的背离衬底1的表面持平或大致持平。由此，图案化后的光刻胶106只保留在每个通孔103内的部分，从而对第一金属薄膜104位于每个通孔103内的部分进行保护。
S343：如图17中(f)所示，采用干法刻蚀的方式或CMP的方式将第一金属薄膜104图案化，也即将第一金属薄膜104的未被上述图案化后的光刻胶106保护的部分去除。
对应的，如图17中(g)和(h)所示，S350还包括去除所述图案化后的光刻胶106。例如，采用等离子体刻蚀的方式去除上述图案化后的光刻胶106。在一些示例中，上述图案化后的光刻胶106和第一目标层101可以通过一次等离子体刻蚀工序同时去除。
此外，可选的，第二目标层102采用金属材料制作形成，第二目标层102的去除与第一金属薄膜104的图案化能够在同一次干法刻蚀工序或同 一次CMP工序中完成，以简化各连接结构3的制作工艺。
在本公开一些实施例中，通过在第一金属薄膜104的背离衬底1的一侧表面上涂覆整层的光刻胶105，可以使该光刻胶105的部分自然而然地填满每个通孔103。在将光刻胶图案化后，该图案化后的光刻胶106的背离衬底1的表面不低于第一金属薄膜104的背离衬底1的表面，也即该图案化后的光刻胶106为光刻胶105遗留在每个通孔103内的部分，这样实现了该图案化后的光刻胶106与各通孔103的自对准，并有效提高了其对位精度，进而能够确保对应的各连接结构3的成型精度，实现各连接结构3在大面积范围的大量制作。
在一些实施例中，请参阅图3、图4以及图18，上述显示背板的制作方法还包括S400。
S400，在每个连接结构3上制作导电性镀层8。
在一些示例中，导电性镀层8的结构如图3所示。导电性镀层8制作在对应连接结构3的裸露表面上，以使得该导电性镀层8将对应的连接结构3围设在对应的驱动电极2上。
在另一些示例中，导电性镀层8的结构如图4所示。导电性镀层8的制作方法如图18中(a)和(b)中所示。首先，采用溅射沉积的方式沉积第二金属薄膜105，该第二金属薄膜105至少覆盖于各驱动电极2以及各连接结构3的裸露表面。然后，将第二金属薄膜105图案化，以获得设置于每个连接结构3以及对应驱动电极2上的导电性镀层8。
此处，可选的，第二金属薄膜105采用铜、铝或银中的至少一种材料制作形成。
此外，第二金属薄膜105的图案化，利用掩膜进行干法刻蚀完成。
可选的，导电性镀层8和对应的驱动电极2利用同一掩膜中的同一图案刻蚀形成，制作方便。
在本公开一些实施例中，利用导电性镀层8电连接对应的连接结构3 以及对应的驱动电极2，有利于提高对应的连接结构3的表面导电性，进而增强各连接结构3与对应的驱动电极2以及对应的微型电子元器件之间的电连接性能。
本公开的一些实施例提供了一种显示装置200。请参阅图19，所述显示装置200包括如上述一些实施例提供的显示背板100，以及与所述显示背板100中的每两个连接结构3对应电连接的一个Micro-LED 9。
示例的，显示装置的像素数量通常为百万级。以显示装置为4K超高清(Ultra-High Definition，简称UHD)Micro-LED显示屏为例，该显示屏的分辨率为3840x2160，具有8,294,400个像素，其中，每个Micro-LED 9对应一原色，也即每个像素对应三个Micro-LED。这也就意味着，该显示屏具有24,883,200个Micro-LED，需要在显示装置中绑定千万级的Micro-LED。
Micro-LED 9通常包括一LED本体91以及两个引脚92，该两个引脚92设置在LED本体91上，并与对应的两个连接结构3分别电连接。各连接结构3分别设置在对应的驱动电极2上。各驱动电极2的设置位置通常根据对应Micro-LED 9中引脚92的设置位置来设计，以确保各驱动电极2能够通过对应的连接结构3与对应的引脚92电连接。例如，每一引脚92在衬底1上的正投影位于对应的驱动电极2在衬底1上的正投影内。
此外，Micro-LED 9的整体尺寸通常小于100μm，该Micro-LED 9的引脚92的尺寸相比于Micro-LED 9的整体尺寸更小，使得Micro-LED 9的引脚92通常以金属焊点的形式存在，Micro-LED 9的引脚92与对应连接结构3之间的电连接采用插接的方式实现。
示例性的，每个连接结构3的背离衬底1的一端采用较为尖锐的结构，例如尖角或薄壁等，这样在巨量转移多个Micro-LED 9至显示背板100的过程中，每个连接结构3能够有效刺入对应的引脚92内，以确保每个连接结构3能够与对应的引脚92良好电连接。
上述各连接结构3与对应引脚92的对位精度，与相关制作工艺中的成型精度有关。在设计各连接结构3的过程中，参考其对应制作工艺所能达到的成型精度，也即各连接结构3与对应引脚92之间可能具有的对位精度，能够合理确定各连接结构3在对应驱动电极2上的正投影面积。
示例性的，在各连接结构3与对应引脚92之间具有较高对位精度的情况下，设计各连接结构3在对应驱动电极2上的正投影外轮廓可以位于对应引脚92在所述驱动电极2上的正投影所在区域内，从而确保各连接结构3与对应的引脚92之间具有良好的电连接。
示例性的，在各连接结构3与对应引脚92之间具有较低对位精度的情况下，设计各连接结构3在对应驱动电极2上的正投影外轮廓也可以位于对应引脚92在所述驱动电极2上的正投影所在区域外，且各连接结构3在对应驱动电极2上的正投影能够覆盖对应引脚92在所述驱动电极2上的正投影，这样在各连接结构3与对应引脚92之间出现对位偏差的情况下，依然可以保证各引脚92在对应驱动电极2上的正投影位于对应连接结构3在所述驱动电极2上的外轮廓内，也即确保各连接结构3与对应的引脚92之间能够具有有效的电连接。
本公开一些实施例提供的显示装置所能实现的有益效果，与上述一些实施例提供的显示背板所能达到的有益效果相同，在此不做赘述。
如图19所示，Micro-LED 9的引脚92的材料可以根据实际需要选择设置，本公开的一些实施例对此不作限定。示例性的，Micro-LED 9的引脚92的材料如表2中所示。
Figure PCTCN2019100920-appb-000002
Figure PCTCN2019100920-appb-000003
表2
由此，显示背板100中各连接结构3的硬度大于对应Micro-LED 9的引脚92的硬度。这样在巨量转移多个Micro-LED 9至显示背板100，并将多个Micro-LED 9与对应的连接结构3进行绑定的过程中，各连接结构3能够几乎同时同时***至对应Micro-LED 9的引脚92(也即金属焊点)内，以通过金属间相互扩散实现良好的电连接。
如此，无需针对多个Micro-LED 9进行逐个绑定，可以有效提高各Micro-LED 9与显示背板100中对应的驱动电极2的绑定效率、绑定良率以及绑定可靠性，同时有效降低制作显示装置200的成本。此外，上述巨量转移多个Micro-LED 9至显示背板100的过程能够在室温下进行，方便制作。
在一些示例中，上述显示装置200为手机、平板电脑、笔记本电脑、显示器或电视机等具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示背板，包括：
    衬底；
    设置于所述衬底上的多个驱动电极；以及，
    设置于所述多个驱动电极中至少一个驱动电极上的连接结构，所述连接结构在所述衬底上的正投影位于对应的所述驱动电极在所述衬底上的正投影内；
    其中，所述连接结构包括至少一个导电部，所述至少一个导电部与对应的所述驱动电极呈第一夹角设置。
  2. 根据权利要求1所述的显示背板，其中，
    所述第一夹角的取值范围为85°～95°。
  3. 根据权利要求1所述的显示背板，其中，所述连接结构还包括与所述至少一个导电部相连接的底部，所述底部与对应的所述驱动电极直接接触。
  4. 根据权利要求3所述的显示背板，其中，同一个所述连接结构中的所述至少一个导电部与所述底部为一体结构。
  5. 根据权利要求3所述的显示背板，其中，所述至少一个导电部包括多个导电部，所述多个导电部环绕所述底部的轮廓间隔设置。
  6. 根据权利要求1～4任一项所述的显示背板，其中，所述至少一个导电部在所述衬底上的正投影为封闭图形。
  7. 根据权利要求6所述的显示背板，其中，所述至少一个导电部为管状结构。
  8. 根据权利要求1～5任一项所述的显示背板，其中，所述至少一个导电部为侧壁包括至少一个裂隙的管状结构，所述至少一个裂隙延伸至所述管状结构的远离所述驱动电极的一侧的端壁表面。
  9. 根据权利要求1～8任一项所述的显示背板，其中，所述至少一个 导电部的硬度大于对应的所述驱动电极的硬度。
  10. 根据权利要求9所述的显示背板，其中，所述至少一个导电部的材料包括钨、钛或钼。
  11. 根据权利要求1～10任一项所述的显示背板，还包括：设置于每个所述连接结构中的所述至少一个导电部上的导电性镀层。
  12. 根据权利要求1～11任一项所述的显示背板，具有多个子像素区域；其中，所述多个驱动电极中的至少两个驱动电极位于所述多个子像素区域中的一个子像素区域内。
  13. 根据权利要求12所述的显示背板，还包括位于所述多个子像素区域中的一个子像素区域内且设置于所述衬底上的至少一个驱动晶体管；
    所述至少两个驱动电极位于对应的所述驱动晶体管的背离所述衬底的一侧；
    同一个子像素区域内的每两个驱动电极中的一者与对应的一驱动晶体管电连接。
  14. 一种显示背板的制作方法，包括：
    提供一衬底；
    在所述衬底上制作多个驱动电极；
    在所述多个驱动电极中的至少一个驱动电极上制作连接结构，所述连接结构在所述衬底上的正投影位于对应的所述驱动电极在所述衬底上的正投影内，且所述连接结构包括至少一个导电部，所述至少一个导电部与对应的所述驱动电极呈第一夹角设置。
  15. 根据权利要求14所述的显示背板的制作方法，其中，在所述多个驱动电极中的至少一个驱动电极上制作连接结构，包括：
    在所述多个驱动电极中的至少一个驱动电极的背离所述衬底的一侧层叠形成第一目标层和第二目标层，所述第二目标层的硬度大于所述第一目标层的硬度；
    形成贯穿所述第二目标层和所述第一目标层的至少一个通孔，所述至少一个通孔位于所述多个驱动电极中的至少一个驱动电极所在的区域内，所述至少一个通孔与所述至少一个驱动电极一一对应；
    沉积第一金属薄膜，所述第一金属薄膜位于所述至少一个通孔中每个通孔内的部分与对应的驱动电极电连接；
    图案化所述第一金属薄膜以保留所述第一金属薄膜位于所述每个通孔内的部分；
    去除所述第二目标层和所述第一目标层，形成所述连接结构。
  16. 根据权利要求15所述的显示背板的制作方法，其中，在沉积第一金属薄膜之后，以及图案化所述第一金属薄膜之前，所述显示背板的制作方法还包括：
    在所述第一金属薄膜位于所述每个通孔内的部分上涂覆光刻胶；
    图案化所述第一金属薄膜，还包括：采用化学机械研磨的方式，将所述第一金属薄膜图案化；
    去除所述第二目标层和所述第一目标层，形成所述连接结构，还包括：
    去除所述第二目标层、所述第一目标层和所述光刻胶，形成所述连接结构。
  17. 根据权利要求15所述的显示背板的制作方法，其中，在沉积第一金属薄膜之后，以及图案化所述第一金属薄膜之前，所述显示背板的制作方法还包括：
    涂覆光刻胶，所述光刻胶至少覆盖在所述第一金属薄膜位于所述每个通孔内的部分上；
    图案化所述光刻胶，以保留所述光刻胶对应位于所述每个通孔内的部分；其中，以所述衬底的表面为基准面，图案化后的光刻胶的背离所述衬底的表面不低于所述第一金属薄膜的背离所述衬底的表面，所述图案化后的光刻胶位于所述每个通孔内的部分在所述衬底上的正投影的尺寸与对应 的通孔的孔径相同或大致相同；
    去除所述第二目标层和所述第一目标层，形成所述连接结构，还包括：
    去除所述第二目标层、所述第一目标层以及所述图案化后的光刻胶，形成所述连接结构。
  18. 根据权利要求15所述的显示背板的制作方法，其中，所述第一目标层的材料为有机绝缘材料，和/或，所述第二目标层的材料为无机绝缘材料或金属材料。
  19. 一种显示装置，包括：
    如权利要求1-13任一项所述的显示背板；以及，
    与所述显示背板中的每两个连接结构对应电连接的一个微发光二极管。
PCT/CN2019/100920 2019-05-31 2019-08-16 显示背板及其制作方法、显示装置 WO2021030927A1 (zh)

Priority Applications (10)

Application Number Priority Date Filing Date Title
EP19932246.2A EP4016630A4 (en) 2019-08-16 2019-08-16 DISPLAY BACKPLATE AND METHOD FOR MAKING IT, AND DISPLAY DEVICE
JP2020570027A JP7464540B2 (ja) 2019-08-16 2019-08-16 表示バックプレーン及びその製造方法、表示装置
CN201980001362.3A CN112997314B (zh) 2019-08-16 2019-08-16 显示背板及其制作方法、显示装置
US16/959,097 US11600747B2 (en) 2019-08-16 2019-08-16 Display backplane and method of manufacturing the same, display device
PCT/CN2019/100920 WO2021030927A1 (zh) 2019-08-16 2019-08-16 显示背板及其制作方法、显示装置
CN201980003118.0A CN113169149A (zh) 2019-05-31 2019-12-19 显示背板及其制备方法和显示装置
US16/982,217 US11764343B2 (en) 2019-05-31 2019-12-19 Display backboard and manufacturing method thereof and display device
EP19930244.9A EP3979317A4 (en) 2019-05-31 2019-12-19 Display backplane and manufacturing method therefor, and display device
PCT/CN2019/126708 WO2020238173A1 (zh) 2019-05-31 2019-12-19 显示背板及其制备方法和显示装置
US18/228,281 US20230378414A1 (en) 2019-05-31 2023-07-31 Display backboard and manufacturing method thereof and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/100920 WO2021030927A1 (zh) 2019-08-16 2019-08-16 显示背板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2021030927A1 true WO2021030927A1 (zh) 2021-02-25

Family

ID=74660151

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/100920 WO2021030927A1 (zh) 2019-05-31 2019-08-16 显示背板及其制作方法、显示装置

Country Status (5)

Country Link
US (1) US11600747B2 (zh)
EP (1) EP4016630A4 (zh)
JP (1) JP7464540B2 (zh)
CN (1) CN112997314B (zh)
WO (1) WO2021030927A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024108432A1 (zh) * 2022-11-23 2024-05-30 厦门市芯颖显示科技有限公司 微型绑定器件、绑定背板和显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114755852B (zh) * 2022-04-21 2024-03-29 南京京东方显示技术有限公司 背板、背板加工方法、背光模组及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106486493A (zh) * 2015-08-31 2017-03-08 三星显示有限公司 显示设备
CN106876552A (zh) * 2017-02-27 2017-06-20 深圳市华星光电技术有限公司 微发光二极管阵列基板及显示面板
WO2018111752A1 (en) * 2016-12-13 2018-06-21 Hong Kong Beida Jade Bird Display Limited Mass transfer of micro structures using adhesives
CN108493154A (zh) * 2018-04-28 2018-09-04 深圳市华星光电技术有限公司 Micro LED显示面板的制作方法及Micro LED显示面板
CN108933153A (zh) * 2018-07-27 2018-12-04 上海天马微电子有限公司 显示面板及其制作方法、显示装置
CN110100309A (zh) * 2016-12-23 2019-08-06 株式会社流明斯 微型led模块及其制造方法

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000183507A (ja) * 1998-12-17 2000-06-30 Shinko Electric Ind Co Ltd 半導体チップ若しくは半導体装置の実装基板への実装構造
JP2002289770A (ja) * 2001-03-27 2002-10-04 Nec Kansai Ltd 半導体装置
JP4920330B2 (ja) * 2006-07-18 2012-04-18 ソニー株式会社 実装構造体の実装方法、発光ダイオードディスプレイの実装方法、発光ダイオードバックライトの実装方法および電子機器の実装方法
JP4949279B2 (ja) * 2008-01-21 2012-06-06 新光電気工業株式会社 配線基板及びその製造方法
US20100044416A1 (en) 2008-08-21 2010-02-25 Nec Corporation Method of manufacturing electronic components having bump
JP5407269B2 (ja) * 2008-10-21 2014-02-05 富士通セミコンダクター株式会社 半導体装置
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
JP5692772B2 (ja) 2009-11-26 2015-04-01 国立大学法人東北大学 表面保護膜、接ガス部材、ガス処理装置及びメカニカルポンプ
US8766439B2 (en) 2009-12-10 2014-07-01 International Business Machines Corporation Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip
CN103117246B (zh) 2011-11-17 2015-09-02 中芯国际集成电路制造(上海)有限公司 金属互连结构的制作方法
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
JP6413412B2 (ja) * 2014-07-11 2018-10-31 日亜化学工業株式会社 半導体発光装置及びその製造方法
WO2017149521A1 (en) 2016-03-04 2017-09-08 Vuereal Inc. Micro device integration into system substrate
KR20160119942A (ko) * 2015-04-06 2016-10-17 에스케이하이닉스 주식회사 소켓 플러그 접속 구조를 포함하는 반도체 패키지
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
KR102455088B1 (ko) 2016-01-11 2022-10-14 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 박막 트랜지스터 기판, 이를 포함하는 표시패널 및 표시장치
US10103069B2 (en) 2016-04-01 2018-10-16 X-Celeprint Limited Pressure-activated electrical interconnection by micro-transfer printing
CN105759522B (zh) * 2016-05-11 2019-01-22 深圳市华星光电技术有限公司 Tft基板的断线修复方法
JP6729046B2 (ja) * 2016-06-20 2020-07-22 大日本印刷株式会社 配線基板およびその製造方法、ならびに半導体装置の製造方法
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
TWI607559B (zh) 2017-01-10 2017-12-01 錼創科技股份有限公司 顯示面板
US20180247584A1 (en) 2017-02-27 2018-08-30 Shenzhen China Star Optoelectronics Technology Co., Ltd. Micro light emitting diode array substrates and display panels
CN108183156A (zh) * 2017-12-26 2018-06-19 深圳市华星光电技术有限公司 微型发光二极管显示面板及其制作方法
KR102433873B1 (ko) 2018-01-29 2022-08-19 삼성전자주식회사 Led 패널 및 led 패널의 제조 방법
US10325894B1 (en) 2018-04-17 2019-06-18 Shaoher Pan Integrated multi-color light-emitting pixel arrays based devices by bonding
US10665573B2 (en) 2018-04-28 2020-05-26 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacturing method of micro light-emitting diode display panel having elastic conductive layer filled between pixel electrode and micro light-emitting diode and micro light-emitting diode display panel manufactured with the same
CN109494292B (zh) 2018-10-30 2020-07-31 海信视像科技股份有限公司 一种微型发光二极管灯板、其制作方法及显示装置
CN109285856B (zh) * 2018-11-22 2020-07-03 京东方科技集团股份有限公司 Led发光基板及其制作方法、显示装置
CN109755376A (zh) 2019-03-20 2019-05-14 中芯长电半导体（江阴）有限公司 扇出型led的封装结构及封装方法
CN109950270B (zh) 2019-03-27 2021-01-08 京东方科技集团股份有限公司 发光二极管芯片的驱动背板及其制作方法、显示面板
CN109887950A (zh) * 2019-04-19 2019-06-14 京东方科技集团股份有限公司 显示基板、led器件、显示面板、显示装置及制作方法
CN110061106B (zh) 2019-04-24 2020-04-17 京东方科技集团股份有限公司 芯片、目标基板、芯片转移方法及显示装置
CN110047866B (zh) 2019-04-30 2021-04-02 京东方科技集团股份有限公司 阵列基板、显示面板及微型led的转移方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106486493A (zh) * 2015-08-31 2017-03-08 三星显示有限公司 显示设备
WO2018111752A1 (en) * 2016-12-13 2018-06-21 Hong Kong Beida Jade Bird Display Limited Mass transfer of micro structures using adhesives
CN110100309A (zh) * 2016-12-23 2019-08-06 株式会社流明斯 微型led模块及其制造方法
CN106876552A (zh) * 2017-02-27 2017-06-20 深圳市华星光电技术有限公司 微发光二极管阵列基板及显示面板
CN108493154A (zh) * 2018-04-28 2018-09-04 深圳市华星光电技术有限公司 Micro LED显示面板的制作方法及Micro LED显示面板
CN108933153A (zh) * 2018-07-27 2018-12-04 上海天马微电子有限公司 显示面板及其制作方法、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4016630A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024108432A1 (zh) * 2022-11-23 2024-05-30 厦门市芯颖显示科技有限公司 微型绑定器件、绑定背板和显示装置

Also Published As

Publication number Publication date
US11600747B2 (en) 2023-03-07
EP4016630A4 (en) 2022-08-24
JP2022551676A (ja) 2022-12-13
CN112997314B (zh) 2022-12-09
EP4016630A1 (en) 2022-06-22
JP7464540B2 (ja) 2024-04-09
US20210408331A1 (en) 2021-12-30
CN112997314A (zh) 2021-06-18

Similar Documents

Publication Publication Date Title
US11641772B2 (en) Display device
CN110767646B (zh) 显示基板及其制造方法、显示装置
US10236279B2 (en) Emissive display with light management system
JP2022550490A (ja) 表示基板及び表示装置
WO2021088037A1 (zh) 阵列基板及其制造方法、显示面板、显示装置
WO2021030927A1 (zh) 显示背板及其制作方法、显示装置
WO2021093681A1 (zh) 显示背板及其制作方法和显示装置
CN110050512A (zh) 使用半导体发光元件的显示装置
TW201508601A (zh) 觸控面板與觸控顯示面板
CN111162162A (zh) 转移基板及其制备方法、微发光二极管的转移方法
WO2015151401A1 (ja) 半導体ユニット、半導体素子、発光装置、表示装置、半導体素子の製造方法
CN115101534A (zh) 显示基板及其制备方法、显示装置
JP2008288544A (ja) 駆動ｉｃ用の窪みのない金バンプ
WO2020143582A1 (zh) 显示面板、阵列基板及其制备方法
WO2019206023A1 (zh) 一种显示面板、其制作方法及显示装置
WO2021031381A1 (zh) 阵列基板及其制备方法
WO2022198650A1 (zh) 显示基板及其制备方法、显示装置
CN116031342A (zh) 发光器件、包括其的显示装置以及制造其的方法
TW200906209A (en) System for displaying image and fabrication method thereof
GB2610947A (en) Display substrate and manufacturing method therefor, and display device
WO2020238173A1 (zh) 显示背板及其制备方法和显示装置
WO2021035529A1 (zh) 电子装置基板及其制作方法、电子装置
WO2022001425A1 (zh) 发光基板及其制备方法、显示装置
CN219352274U (zh) 阵列基板及显示面板
TWI797915B (zh) 鏡面顯示器

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2020570027

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19932246

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019932246

Country of ref document: EP

Effective date: 20220316