WO2021027514A1 - 像素电路及其驱动方法以及显示面板 - Google Patents

像素电路及其驱动方法以及显示面板 Download PDF

Info

Publication number
WO2021027514A1
WO2021027514A1 PCT/CN2020/103554 CN2020103554W WO2021027514A1 WO 2021027514 A1 WO2021027514 A1 WO 2021027514A1 CN 2020103554 W CN2020103554 W CN 2020103554W WO 2021027514 A1 WO2021027514 A1 WO 2021027514A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
electrically connected
electrode
transistor
emitting
Prior art date
Application number
PCT/CN2020/103554
Other languages
English (en)
French (fr)
Inventor
刘伟星
王铁石
徐智强
李胜男
滕万鹏
张春芳
李小龙
秦纬
郭凯
彭宽军
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/271,776 priority Critical patent/US11238803B2/en
Publication of WO2021027514A1 publication Critical patent/WO2021027514A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/125—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light
    • H10K50/13—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light comprising stacked EL layers within one EL unit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/32—Stacked devices having two or more layers, each emitting at different wavelengths
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display panel.
  • OLED organic light-emitting diode
  • a pixel circuit including: a driving sub-circuit, electrically connected to a first node, a first power signal terminal, and a second node, and configured to be a voltage at the first node
  • the first power supply voltage from the first power signal terminal is transferred to the second node, the light-emitting control sub-circuit, and the second node, the second power signal terminal, the first light-emitting control terminal, and the second node under the control of Light emitting control terminal, third light emitting control terminal, first pole of first light emitting element, second pole of first light emitting element, first pole of second light emitting element, second pole of second light emitting element, third light emitting element
  • the first pole of the light-emitting element and the second pole of the third light-emitting element are electrically connected, and are configured to control the light emission from the first light-emitting control terminal, the second light-emitting control terminal, and the third light-emitting control terminal.
  • the first pole of the element and the second pole of the first light-emitting element are respectively transferred to the first pole of the second light-emitting element and the second pole of the second light-emitting element in a second period of time.
  • the second pole is respectively transferred to the first pole of the third light-emitting element and the second pole of the third light-emitting element in the third period.
  • the light emission control sub-circuit includes a first transistor, the control electrode of the first transistor is electrically connected to the second light emission control terminal, and the first electrode of the first transistor is electrically connected to the second light emission control terminal.
  • Two nodes are electrically connected, the second electrode of the first transistor is electrically connected to the fourth node, the second transistor, the control electrode of the second transistor is electrically connected to the first light-emitting control terminal, and the The first electrode is electrically connected to the second node, the second electrode of the second transistor is electrically connected to the first electrode of the first light-emitting element, and the third transistor is electrically connected to the control electrode of the third transistor.
  • the third light-emitting control terminal is electrically connected, the first electrode of the third transistor is electrically connected to the second node, the second electrode of the third transistor is electrically connected to the fifth node, the fourth transistor, the The control electrode of the fourth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the second power supply.
  • the signal terminal is electrically connected, a fifth transistor, the control electrode of the fifth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the fifth node, and the fifth transistor is electrically connected to the
  • the second electrode of the transistor is electrically connected to the second power signal terminal, and the second electrode of the first light-emitting element is electrically connected to the first electrode of the second light-emitting element via the fourth node,
  • the second pole of the second light emitting element and the first pole of the third light emitting element are electrically connected via the fifth node, and the second pole of the third light emitting element is electrically connected to the first pole of the third light emitting element.
  • the power signal terminal is electrically connected.
  • the light emission control sub-circuit includes a first transistor, the control electrode of the first transistor is electrically connected to the second light emission control terminal, and the first electrode of the first transistor is electrically connected to the second light emission control terminal.
  • Two nodes are electrically connected, the second electrode of the first transistor is electrically connected to the fourth node, the second transistor, the control electrode of the second transistor is electrically connected to the third light-emitting control terminal, and the second transistor
  • the first electrode is electrically connected to the second electrode of the third light-emitting element, the second electrode of the second transistor is electrically connected to the second power signal terminal, and the third transistor is controlled by the third transistor
  • the electrode is electrically connected to the third light-emitting control terminal, the first electrode of the third transistor is electrically connected to the second node, the second electrode of the third transistor is electrically connected to the fifth node, the fourth transistor,
  • the control electrode of the fourth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the fourth transistor is electrically connected to
  • the two power signal terminals are electrically connected, a fifth transistor, the control electrode of the fifth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the fifth node, and the The second electrode of the fifth transistor is electrically connected to the second power signal terminal, the first electrode of the first light emitting element is electrically connected to the second node, and the second electrode of the first light emitting element is electrically connected to the second node.
  • the electrode is electrically connected to the first electrode of the second light-emitting element via the fourth node, and the second electrode of the second light-emitting element and the first electrode of the third light-emitting element are electrically connected via the fourth node.
  • the fifth node is electrically connected.
  • the driving sub-circuit includes a sixth transistor, wherein the control electrode of the sixth transistor is electrically connected to the first node, and the first electrode of the sixth transistor is electrically connected to the first power supply.
  • the signal terminal is electrically connected, and the second electrode of the sixth transistor is electrically connected to the second node.
  • the pixel circuit further includes: a storage sub-circuit, electrically connected between the first node and the third node, a charge control sub-circuit, and a scan signal terminal, a data signal terminal, and the first node.
  • the node, the second node and the third node are electrically connected, and are configured to generate a voltage difference between the first node and the third node under the control of the first scan voltage from the scan signal terminal,
  • the reset sub-circuit is electrically connected to the first reset control terminal, the second reset control terminal, the third node and the reset voltage signal terminal, and is configured to respond to the first reset control signal from the first reset control terminal or from the second reset Under the control of the second reset control signal from the control terminal, the third node is reset using the reset voltage signal from the reset voltage signal terminal.
  • the storage sub-circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the first node. connection.
  • the charge control sub-circuit includes a seventh transistor, a control electrode of the seventh transistor is electrically connected to the scan signal terminal, and a first electrode of the seventh transistor is electrically connected to the data signal terminal. Electrically connected, the second electrode of the seventh transistor is electrically connected to the third node, the eighth transistor, the control electrode of the eighth transistor is electrically connected to the scan signal terminal, and the first electrode of the eighth transistor The electrode is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node.
  • the reset sub-circuit includes: a ninth transistor, a control electrode of the ninth transistor is electrically connected to the first reset control terminal, and a first electrode of the ninth transistor is connected to the reset voltage
  • the signal terminal is electrically connected
  • the second electrode of the ninth transistor is electrically connected to the third node
  • the tenth transistor the control electrode of the tenth transistor is electrically connected to the second reset control terminal
  • the tenth transistor is electrically connected to the second reset control terminal.
  • the first pole of the transistor is electrically connected to the reset voltage signal terminal
  • the second pole of the tenth transistor is electrically connected to the third node.
  • the scan signal terminal is configured to receive a scan signal for the current row of pixels
  • the first reset control terminal is configured to receive a scan signal for the previous row of pixels
  • the second reset control terminal is configured to It is configured to receive the scanning signal for the next row of pixels.
  • a display panel including a plurality of pixel units, and at least one pixel unit of the plurality of pixel units includes the pixel circuit described above.
  • each pixel unit of the at least one pixel unit includes: a substrate; a control circuit layer, which is provided on the substrate, and includes the driver subcircuit and the light emission control subcircuit; an intermediate layer, Is arranged on the side of the control circuit layer away from the substrate and is configured to cover the control circuit layer; sequentially stack a first electrode layer, a first light-emitting layer, and a second electrode layer on the intermediate layer , A second light-emitting layer, a third electrode layer, a third light-emitting layer, and a fourth electrode layer, wherein the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer are used as first light-emitting elements, respectively , The second light-emitting element and the third light-emitting element.
  • the substrate includes a first area and a second area that do not overlap with each other, wherein at least a part of the driving sub-circuit and at least a part of the light-emission control sub-circuit are projected on the substrate.
  • the first region At least a part of the first electrode layer, at least a part of the first light-emitting layer, at least a part of the second electrode layer, at least a part of the second light-emitting layer, and the third electrode layer
  • a projection of at least a part of the third light-emitting layer and the fourth electrode layer on the substrate is located in the second region.
  • the first electrode layer, the second electrode layer, and the third electrode layer are electrically connected to the light emission control sub-circuit through through holes penetrating the intermediate layer, respectively.
  • the material of the first electrode layer includes an opaque material
  • the material of the second electrode layer, the third electrode layer, and the fourth electrode layer includes a transparent material
  • each of the first period, the second period, and the third period includes an initialization phase, a charging phase, and a light-emitting phase
  • the method includes: providing a first lighting control signal having a second level in the lighting phase of the first period, providing a second lighting control signal and a third lighting control signal having a first level, and In the light-emitting stage of the second period, a second light-emitting control signal with a second level is provided, and a first light-emitting control signal and a third light-emitting control signal with a first level are provided.
  • a third light-emitting control signal with a second level In the light-emitting stage of the third period, Provide a third light-emitting control signal with a second level, provide a first light-emitting control signal and a second light-emitting control signal with a first level, and provide a first-level light-emitting control signal during the initialization phase and charging phase of each period The first lighting control signal, the second lighting control signal, and the third lighting control signal.
  • a display panel including a plurality of pixel units, each pixel unit including: a substrate; a control circuit layer provided on the substrate; an intermediate layer provided on the control circuit layer The side away from the substrate; the first electrode layer, the first light-emitting layer, the second electrode layer, the second light-emitting layer, the third electrode layer, the third light-emitting layer, and the fourth layer are sequentially stacked on the intermediate layer An electrode layer, wherein the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer are used as a first light-emitting element, a second light-emitting element, and a third light-emitting element, respectively.
  • the substrate includes a first region and a second region that do not overlap with each other, wherein at least a part of the first electrode layer, at least a part of the first light-emitting layer, and the second electrode layer A projection of at least a part of the second light-emitting layer, at least a part of the third electrode layer, at least a part of the third light-emitting layer and the fourth electrode layer on the substrate is located in the second region.
  • the first electrode layer, the second electrode layer, and the third electrode layer are electrically connected to the control circuit layer through through holes penetrating the intermediate layer.
  • the first electrode layer includes an opaque material
  • the second electrode layer, the third electrode layer, and the fourth electrode layer include transparent materials.
  • FIG. 1 shows a schematic cross-sectional view of a pixel unit of a display panel according to the related art.
  • FIG. 2A shows a schematic cross-sectional view of a pixel unit of a display panel according to an embodiment of the present disclosure.
  • FIG. 2B shows a schematic cross-sectional view of another pixel unit of the display panel according to an embodiment of the present disclosure.
  • FIG. 3 shows a more detailed layer structure diagram of a pixel unit according to an embodiment of the present disclosure.
  • FIG. 4 shows a circuit structure diagram of a pixel circuit in a pixel unit according to an embodiment of the present disclosure.
  • FIG. 5 shows a further circuit structure diagram of the pixel circuit in FIG. 4.
  • FIG. 6 shows a detailed circuit diagram of the pixel circuit shown in FIG. 5.
  • FIG. 7A shows a signal timing diagram of the pixel circuit of FIG. 6.
  • FIG. 7B-7F show schematic diagrams of the principle of each stage of the pixel circuit of FIG. 6.
  • FIG. 8 shows another detailed circuit diagram of the pixel circuit shown in FIG. 5.
  • FIG. 9 shows a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 shows a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • the term "electrically connected” may mean that two components are directly electrically connected, or may mean that two components are electrically connected via one or more other components. In addition, these two components can be electrically connected or coupled in a wired or wireless manner.
  • the specific type of display is not limited, but those skilled in the art should understand that any display that emits light by providing a light-emitting layer and applying a voltage across the light-emitting layer (for example, OLED display, Quantum dot light emitting diode (QLED) displays) are all covered by this disclosure.
  • any display that emits light by providing a light-emitting layer and applying a voltage across the light-emitting layer for example, OLED display, Quantum dot light emitting diode (QLED) displays
  • QLED Quantum dot light emitting diode
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors (TFT) or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged. In the embodiments of the present disclosure, one of the source electrode and the drain electrode is called the first electrode, and the other of the source electrode and the drain electrode is called the second electrode.
  • the driving transistor is described as a P-type thin film transistor, and other transistors are of the same or different type from the driving transistor according to the circuit design.
  • the driving transistor may also be shown as an N-type thin film transistor.
  • the driving transistor may also be shown as an N-type thin film transistor.
  • first level and second level are only used to distinguish the two levels from being different in amplitude.
  • the "first level” may be an inactive level that turns off the relevant transistor
  • the “second level” may be an effective level that turns on the relevant transistor.
  • the driving transistor is exemplified as a P-type thin film transistor
  • the "first level” is exemplified as a high level
  • the “second level” is exemplified as a low level.
  • FIG. 1 shows a schematic cross-sectional view of a pixel unit 100 of a display panel according to the related art.
  • the display panel includes a plurality of pixel units 100.
  • the pixel unit 100 includes a substrate 110, a control circuit layer 120, a first electrode layer 130, a light emitting layer 140, and a second electrode layer 150.
  • the substrate 110 may be, for example, a glass substrate.
  • Pixel circuits are formed in the control circuit layer 120.
  • the control circuit layer 120 may include a plurality of pixel circuits configured to control different light-emitting elements (sub-pixels).
  • the first electrode layer 130 is disposed on a side of the control circuit layer 120 away from the substrate 110.
  • the first electrode layer 130 may include a plurality of driving electrodes, which are respectively connected to different pixel circuits in the control circuit layer 120 to receive driving voltages for driving different light emitting elements in the light emitting layer 140 from the corresponding pixel circuits.
  • a portion of the first electrode layer 130 is disposed in the light emitting region in the pixel unit 100, and the first electrode layer 130 may include an opaque material (for example, Al and Ag).
  • one or more intermediate layers may also be provided, and the intermediate layer is located between the control circuit layer 120 and the first electrode layer 130 or surrounds the first electrode layer 130 outside the light-emitting area.
  • the first electrode layer 130 is electrically connected to the pixel circuit in the control circuit layer 120 through through holes penetrating the one or more intermediate layers.
  • the intermediate layer may include an interlayer dielectric layer (ILD) and various flat layers, insulating layers or organic layers.
  • the light-emitting layer 140 includes three parts arranged side by side, corresponding to the red light-emitting element (R), the green light-emitting element (G), and the blue light-emitting element (B) in the pixel unit 100 to emit red, green, and blue. Color of light.
  • each light-emitting element corresponds to one pixel circuit in the control circuit layer 120 and one electrode in the first electrode layer 130 to receive the driving voltage from the corresponding pixel circuit through the corresponding electrode.
  • the light emitting layer 140 serves as a light emitting element in the pixel circuit.
  • the second electrode layer 150 may include a common electrode, each light-emitting element of each pixel unit on the panel may share the same electrode, and the common electrode may be a transparent electrode (for example, made of indium tin oxide (ITO)).
  • ITO indium tin oxide
  • FIG. 2A shows a schematic cross-sectional view of a pixel unit 200 of a display panel according to an embodiment of the present disclosure.
  • the pixel unit 200 includes a substrate 210, a control circuit layer 220, a first electrode layer 230, a first light-emitting layer 240, a second electrode layer 250, a second light-emitting layer 260, a third electrode layer 270, and a third electrode layer.
  • the light emitting layer 280 and the fourth electrode layer 290 are also included in the pixel unit 200.
  • the substrate 210 may be, for example, a glass substrate.
  • Pixel circuits are formed in the control circuit layer 220.
  • a single pixel circuit may be formed in the control circuit layer 220, and the single pixel circuit is configured to control each light-emitting layer in the pixel unit 200 to emit light in different periods.
  • the first electrode layer 230 is disposed on a side of the control circuit layer 220 away from the substrate 210.
  • the first electrode layer 230 may include a single driving electrode, which is electrically connected to the pixel circuit in the control circuit layer 220, to receive a driving voltage for driving the first light emitting layer 240 from the pixel circuit in the first period of one frame.
  • a part of the first electrode layer 230 is disposed in the light emitting area of the pixel unit 200, wherein the driving electrode may include an opaque material (for example, Al and Ag).
  • one or more intermediate layers 225 are also provided.
  • the intermediate layers 225 may be arranged between the control circuit layer 220 and the first electrode layer 230 or surround the first electrode layer outside the light-emitting area.
  • the first electrode layer 230 is electrically connected to the pixel circuit in the control circuit layer 220 through a through hole penetrating the intermediate layer.
  • the intermediate layer may include an interlayer dielectric layer (ILD) and various flat layers, insulating layers or organic layers.
  • ILD interlayer dielectric layer
  • the first light emitting layer 240 includes a single part corresponding to the red light emitting element (R) in the pixel unit 200 for emitting red light.
  • the first light-emitting layer 240 receives a driving voltage from the pixel circuit in the controlled circuit layer 220 through the driving electrode in the first electrode layer 230.
  • the second electrode layer 250 is disposed on the side of the first light-emitting layer 240 away from the substrate 210.
  • the second electrode layer 250 may include a single electrode, which is electrically connected to the pixel circuit in the control circuit layer 220, to receive the common voltage in the first period of a frame, and to receive the common voltage from the pixel circuit in the second period of the frame.
  • the driving electrode in the second electrode layer 250 may be a transparent electrode. In order to achieve electrical connection between the second electrode layer 250 and the pixel circuit in the control circuit layer 220, a through hole needs to be provided in the intermediate layer.
  • the second light emitting layer 260 includes a single part corresponding to the green light emitting element (G) in the pixel unit 200 for emitting green light.
  • the second light emitting layer 260 receives driving voltages from the pixel circuits in the controlled circuit layer 220 through the driving electrodes in the second electrode layer 250.
  • the third electrode layer 270 is disposed on the side of the second light-emitting layer 260 away from the substrate 210.
  • the third electrode layer 270 may include a single electrode, which is electrically connected to the pixel circuit in the control circuit layer 220 to receive the common voltage in the second period of a frame, and receive the common voltage from the pixel circuit in the third period of the frame.
  • the driving electrode in the third electrode layer 270 may be a transparent electrode. In order to realize the electrical connection between the third electrode layer 270 and the pixel circuit in the control circuit layer 220, a through hole needs to be provided in the intermediate layer.
  • the third light emitting layer 280 includes a single part, corresponding to the blue light emitting element (B) in the pixel unit 200, for emitting blue light.
  • the third light-emitting layer 280 receives a driving voltage from the pixel circuit in the controlled circuit layer 220 through the driving electrode in the third electrode layer 270.
  • the fourth electrode layer 290 is disposed on the side of the third light-emitting layer 280 away from the substrate 210.
  • the fourth electrode layer 290 may include a single electrode therein, which is electrically connected to the pixel circuit in the control circuit layer 220 to receive the common voltage in the third period in one frame.
  • the driving electrode in the fourth electrode layer 290 may be a transparent electrode. In order to achieve electrical connection between the fourth electrode layer 290 and the pixel circuit in the control circuit layer 220, a through hole needs to be provided in the intermediate layer.
  • FIG. 3 shows a more detailed layer structure diagram of a pixel unit according to an embodiment of the present disclosure.
  • the structure of the pixel unit 300 includes a substrate 310, a buffer layer 320, a control circuit layer 330, a first intermediate layer 340, a second intermediate layer 350, a third intermediate layer 360, and a first electrode layer 370 which are sequentially stacked.
  • the first light-emitting layer 371, the second light-emitting layer 373, and the third light-emitting layer 375 are located in the light-emitting area of the pixel unit.
  • Part of the first electrode layer 370, the second electrode layer 372, the third electrode layer 374, and the fourth electrode layer 376 are located in the light-emitting area.
  • the first electrode layer 370, the second electrode layer 372, the third electrode layer 374 and the fourth electrode layer The other part of the electrode layer 376 is located in the TFT area so as to be electrically connected to the pixel circuit or the common power line.
  • some layers for example, the buffer layer 320 in the structure shown in FIG. 3 can be removed or new layers can be added, and the structure of some layers can also be changed. There is no restriction on this.
  • the substrate 310 in FIG. 3 includes a TFT area (first area) and a light emitting area (second area), and the first area and the second area do not overlap.
  • the first intermediate layer 340 and the second intermediate layer 350 in FIG. 3 are disposed between the control circuit layer 330 and the first electrode layer 370, and the third intermediate layer 360 surrounds the first intermediate layer outside the light-emitting area.
  • the control circuit layer 330 in FIG. 3 shows two transistors M1 and M2 in the pixel circuit.
  • One of the source and drain of the transistor M1 is electrically connected to the first electrode layer 370 through the through hole V1, wherein a part of the first electrode layer 370 is formed in the through hole V1.
  • the transistor M2 is electrically connected to the second electrode layer 372 through the through hole V2, wherein the second electrode layer 372 is electrically connected to the electrical connection layer 3721 provided in the through hole V2, and the electrical connection layer 3721 is connected to the first electrode layer.
  • 370 is arranged in the same layer, and the electrical connection layer 3721 and the second electrode layer 372 are made of different materials.
  • the third electrode layer 374 is also electrically connected to the transistors in the pixel circuit, but a part of a specific cross-sectional view of the pixel unit is taken in FIG. 3, and the transistors connected to the third electrode layer 374 are not shown.
  • FIG. 4 shows a circuit structure diagram of a pixel circuit 400 in a pixel unit according to an embodiment of the present disclosure.
  • the pixel circuit 400 includes a driving sub-circuit 410, a light-emission control sub-circuit 420, a first light-emitting element R, a second light-emitting element G, and a third light-emitting element B.
  • the driving sub-circuit 410 is electrically connected to the first node N1, the first power signal terminal VDD, and the second node N2.
  • the driving sub-circuit 410 is configured to transfer the first power supply voltage from the first power supply signal terminal VDD to the second node N2 under the control of the voltage of the first node N1.
  • the light emission control sub-circuit 420 is connected to the second node N2, the second power signal terminal VSS, the first light emission control terminal EM1, the second light emission control terminal EM2, the third light emission control terminal EM3, the first pole and the first pole of the first light emitting element R
  • the two poles, the first pole and the second pole of the second light-emitting element G, and the first pole and the second pole of the third light-emitting element B are electrically connected, and the light emission control sub-circuit 420 is configured to Under the control of the first light emission control signal, the second light emission control signal and the third light emission control signal of the terminal EM1, the second light emission control terminal EM2 and the third light emission control terminal EM3, the voltage of the second node N2 is caused to be the same as the voltage from the second power supply
  • the second power supply voltage of the signal terminal VSS is respectively transferred to the first pole and the second pole of the first light-emitting element R in the first period, and is transferred to the first pole and the second pole of
  • the circuit structure in FIG. 4 can realize the time-sharing driving of three different light-emitting elements R, G, and B in an unused period in one frame, so that the pixel units in FIGS. 2A, 2B, and 3 can realize display.
  • FIG. 5 shows a further circuit structure diagram of the pixel circuit in FIG. 4.
  • the pixel circuit 500 in FIG. 5 further includes a storage sub-circuit 430, a charge control sub-circuit 440, and a reset sub-circuit 450.
  • the storage sub-circuit 430 is electrically connected between the first node N1 and the third node N3.
  • the charge control sub-circuit 440 is electrically connected to the scan signal terminal Scan, the data signal terminal Data, the first node N1, the second node N2, and the third node N3, and is configured to control the first scan voltage from the scan signal terminal Scan Next, a voltage difference is generated between the first node N1 and the third node N3.
  • the reset sub-circuit 450 is electrically connected to the first reset control terminal Reset1, the second reset control terminal Reset2, the third node N3 and the reset voltage signal terminal Vini, and is configured to respond to the first reset control signal from the first reset control terminal Reset1 Or under the control of the second reset control signal from the second reset control terminal Reset2, the third node N3 is reset using the reset voltage signal from the reset voltage signal terminal Vini.
  • FIG. 6 shows a detailed circuit diagram of the pixel circuit shown in FIG. 5.
  • the light emission control sub-circuit 420 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the control electrode of the first transistor T1 is electrically connected to the second light emitting control terminal EM2, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4.
  • the control electrode of the second transistor T2 is electrically connected to the first light emitting control terminal EM1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the first light emitting element R. Extremely electrical connection.
  • the control electrode of the third transistor T3 is electrically connected to the third light emitting control terminal EM3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the fifth node N5.
  • the control electrode of the fourth transistor T4 is electrically connected to the first light emission control terminal EM1, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the second power signal terminal VSS .
  • the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting control terminal EM2, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the second power signal terminal VSS .
  • the second pole of the first light-emitting element R and the first pole of the second light-emitting element G are electrically connected through the fourth node N4, and the second pole of the second light-emitting element G and the first pole of the third light-emitting element B are electrically connected through the fifth node N5 is electrically connected, and the second pole of the third light-emitting element B is electrically connected to the second power signal terminal VSS.
  • the driver sub-circuit 410 includes a sixth transistor T6.
  • the control electrode of the sixth transistor T6 is electrically connected to the first node N1
  • the first electrode of the sixth transistor T6 is electrically connected to the first power signal terminal VDD
  • the second electrode of the sixth transistor T6 is electrically connected to the second node N2.
  • the storage sub-circuit 430 includes a first capacitor C1.
  • the first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the first node N1.
  • the charge control sub-circuit 440 includes a seventh transistor T7 and an eighth transistor T8.
  • the control electrode of the seventh transistor T7 is electrically connected to the scan signal terminal Scan, the first electrode of the seventh transistor T7 is electrically connected to the data signal terminal Data, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3.
  • the control electrode of the eighth transistor T8 is electrically connected to the scan signal terminal Scan, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2.
  • the reset sub-circuit 450 includes a ninth transistor T9 and a tenth transistor T10.
  • the control electrode of the ninth transistor T9 is electrically connected to the first reset control terminal Reset1, the first electrode of the ninth transistor T9 is electrically connected to the reset voltage signal terminal Vini, and the second electrode of the ninth transistor T9 is electrically connected to the third node N3.
  • the control electrode of the tenth transistor T10 is electrically connected to the second reset control terminal Reset2, the first electrode of the tenth transistor T10 is electrically connected to the reset voltage signal terminal Vini, and the second electrode of the tenth transistor T10 is electrically connected to the third node N3.
  • the scan signal terminal Scan is configured to receive scan signals for pixels in the current row
  • the first reset control terminal Reset1 is configured to receive scan signals for pixels in the previous row
  • the second reset control terminal Reset2 is configured to receive Scan signal for the next row of pixels.
  • FIG. 7A shows a signal timing diagram of the pixel circuit of FIG. 6.
  • 7B-7F show schematic diagrams of the principle of each stage of the pixel circuit of FIG. 6.
  • each frame is divided into three periods tp1, tp2, and tp3, and each period is used to drive one light-emitting element (ie, one sub-pixel) to emit light.
  • the tp1 period is used to drive the first light-emitting element R
  • the tp2 period is used to drive the second light-emitting element G
  • the tp3 period is used to drive the third light-emitting element B.
  • Each time period is divided into three stages, namely the initialization stage, the charging stage and the light-emitting stage.
  • the first period tp1 is described first, during which the first light-emitting element R is driven to emit light.
  • the first light-emitting control terminal EM1 the second light-emitting control terminal EM2, and the third light-emitting control terminal EM3 all provide high-level signals, so that all T1-T5 are turned off.
  • the first reset control terminal Reset1 provides a low level signal
  • the second reset control terminal Reset2 and the scan signal terminal Scan provide a high level signal.
  • T7, T8, and T10 are turned off, and T9 is turned on.
  • the voltage of the third node N3 changes the voltage of the floating first node N1 to VGL, so that T6 is turned on, and the voltage Vdd of the first power terminal VDD is transmitted to the second node N2.
  • FIG. 7B the schematic diagram of the principle of the pixel circuit is shown in FIG. 7B. It should be noted that in FIG. 7B, the transistors that are turned off at this stage are marked with an oblique cross " ⁇ ".
  • the first light-emitting control terminal EM1, the second light-emitting control terminal EM2, and the third light-emitting control terminal EM3 keep providing high-level signals, so that T1-T5 are kept off.
  • the scan signal terminal Scan provides a low level signal
  • the first reset control terminal Reset1 and the second reset control terminal Reset2 provide a high level signal.
  • T7 and T8 are turned on, and T9 and T10 are turned off.
  • the high-level data voltage Vdata is input to the third node N3 through the data signal terminal Data, which changes the level of the first terminal of the first capacitor C1 to Vdata.
  • the first node N1 and the second node N2 are electrically connected, and the first power signal terminal VDD starts to charge the first node until the level at point N1 becomes Vdd+Vth, where Vth is the sixth transistor.
  • the threshold voltage of T6 is the threshold voltage of T6.
  • FIG. 7C the schematic diagram of the principle of the pixel circuit is shown in FIG. 7C. It should be noted that in FIG. 7C, the transistors that are turned off at this stage are marked with an oblique cross " ⁇ ".
  • the second light-emitting control terminal EM2 and the third light-emitting control terminal EM3 keep providing high-level signals, and the first light-emitting control terminal EM1 provides low-level signals, so that T1, T3, and T5 are kept off, and T2 and T4 Turning on makes the two ends of the first light emitting element R connected to the second node N2 and the second power supply terminal VSS, respectively.
  • the scan signal terminal Scan and the first reset control terminal Reset1 provide a high-level signal, and the second reset control terminal Reset2 provides a low-level signal.
  • T10 is turned on, and T7 to T9 are turned off.
  • the reset signal terminal Vini changes the voltage of the third node N3 to VGL. Since the first node N1 becomes floating again, the first capacitor C1 maintains the previously generated pressure difference. Thus, the voltage of the first node N1 becomes Vdd+Vth-Vdata+VGL.
  • the sixth transistor T6 is in a saturated state.
  • its source-gate voltage Vsg is:
  • K is the current constant associated with the sixth transistor T6, and is related to the process parameters and geometric dimensions of the sixth transistor T6. It can be seen from the above formula that the driving current Id used to drive the first light-emitting element R to emit light has nothing to do with the threshold voltage Vth of the sixth transistor T6, so that the brightness of the light-emitting element caused by the difference in the threshold voltage Vth of the sixth transistor T6 can be eliminated. Uneven phenomenon.
  • FIG. 7D the schematic diagram of the principle of the pixel circuit is shown in FIG. 7D. It should be noted that in FIG. 7D, the transistors that are turned off at this stage are marked with an oblique cross " ⁇ ".
  • the first light-emitting control terminal EM1 and the third light-emitting control terminal EM3 keep providing high-level signals, and the second light-emitting control terminal EM2 provides low power.
  • the signal is flat, so that T2, T3, and T4 are turned off, and T1 and T5 are turned on, so that both ends of the second light emitting element G are connected to the second node N2 and the second power supply terminal VSS, respectively.
  • the scan signal terminal Scan and the first reset control terminal Reset1 provide a high-level signal, and the second reset control terminal Reset2 provides a low-level signal.
  • T10 is turned on, and T7 to T9 are turned off.
  • the reset signal terminal Vini changes the voltage of the third node N3 to VGL. Since the first node N1 becomes floating again, the first capacitor C1 maintains the previously generated pressure difference. Thus, the voltage of the first node N1 becomes Vdd+Vth-Vdata+VGL.
  • the sixth transistor T6 is in a saturated state.
  • its source-gate voltage Vsg is:
  • K is the current constant associated with the sixth transistor T6, and is related to the process parameters and geometric dimensions of the sixth transistor T6. It can be seen from the above formula that the driving current Id used to drive the second light-emitting element G to emit light has nothing to do with the threshold voltage Vth of the sixth transistor T6, so that the brightness of the light-emitting element caused by the difference in the threshold voltage Vth of the sixth transistor T6 can be eliminated. Uneven phenomenon.
  • FIG. 7E the schematic diagram of the principle of the pixel circuit is shown in FIG. 7E. It should be noted that in FIG. 7E, the transistors that are turned off at this stage are marked with an oblique cross " ⁇ ".
  • the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2 keep providing high-level signals, and the third light-emitting control terminal EM3 provides low power.
  • the signal is flat, so that T1, T2, T4, and T5 are turned off, and T3 is turned on, so that both ends of the third light-emitting element B are connected to the second node N2 and the second power supply terminal VSS, respectively.
  • the scan signal terminal Scan and the first reset control terminal Reset1 provide a high-level signal, and the second reset control terminal Reset2 provides a low-level signal.
  • T10 is turned on, and T7 to T9 are turned off.
  • the reset signal terminal Vini changes the voltage of the third node N3 to VGL. Since the first node N1 becomes floating again, the first capacitor C1 maintains the previously generated pressure difference. Thus, the voltage of the first node N1 becomes Vdd+Vth-Vdata+VGL.
  • the sixth transistor T6 is in a saturated state.
  • its source-gate voltage Vsg is:
  • K is the current constant associated with the sixth transistor T6, and is related to the process parameters and geometric dimensions of the sixth transistor T6. It can be seen from the above formula that the driving current Id used to drive the third light-emitting element B to emit light has nothing to do with the threshold voltage Vth of the sixth transistor T6, so that the brightness of the light-emitting element caused by the difference in the threshold voltage Vth of the sixth transistor T6 can be eliminated. Uneven phenomenon.
  • FIG. 7F the schematic diagram of the principle of the pixel circuit is shown in FIG. 7F. It should be noted that in FIG. 7F, the transistors that are turned off at this stage are marked by an oblique cross " ⁇ ".
  • FIG. 8 shows another detailed circuit diagram of the pixel circuit shown in FIG. 5.
  • the difference between the pixel circuit 800 in FIG. 8 and the pixel circuit 600 in FIG. 6 lies in the circuit structure of the light emission control sub-circuit 420.
  • the circuit structure of other sub-circuits will not be repeated.
  • the light emission control sub-circuit 420 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the control electrode of the first transistor T1 is electrically connected to the second light emitting control terminal EM2, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4.
  • the control electrode of the second transistor T2 is electrically connected to the third light emitting control terminal EM3, the first electrode of the second transistor T2 is electrically connected to the second electrode of the third light emitting element B, and the second electrode of the second transistor T2 is electrically connected to the second power supply.
  • the signal terminal VSS is electrically connected.
  • the control electrode of the third transistor T3 is electrically connected to the third light emitting control terminal EM3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the fifth node N5.
  • the control electrode of the fourth transistor T4 is electrically connected to the first light emission control terminal EM1, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the second power signal terminal VSS .
  • the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting control terminal EM2, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the second power signal terminal VSS .
  • the first pole of the first light emitting element R is electrically connected to the second node N2
  • the second pole of the first light emitting element R and the first pole of the second light emitting element G are electrically connected through the fourth node N4, and the second pole of the second light emitting element G
  • the second pole and the first pole of the third light-emitting element B are electrically connected via the fifth node N5.
  • FIG. 9 shows a schematic block diagram of a display panel 900 according to an embodiment of the present disclosure.
  • the display panel 900 may include a plurality of scan lines SL; a plurality of data lines DL, which are arranged to cross the plurality of scan lines SL; and a plurality of pixel units 910, which are arranged in a matrix in each The intersection of the scan line and each data line is electrically connected to the corresponding data line DL and scan line SL.
  • Each of the plurality of pixel units 910 is provided with a pixel circuit according to an embodiment of the present disclosure, for example, according to the pixel circuit shown in FIG. 2A 2B, FIG. 3, FIG. 4, FIG. 5, FIG. 6 or FIG.
  • the data signal terminal Data in the pixel circuit receives the data signal from the corresponding data line DL, and the scan signal in the pixel circuit
  • the terminal Scan receives the scan signal from the corresponding scan line SL.
  • the display panel 900 may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • FIG. 10 shows a flowchart of a driving method 1000 of a pixel circuit according to an embodiment of the present disclosure.
  • the driving of the pixel circuit is divided into a first period, a second period, and a third period, and each period includes an initialization phase, a charging phase, and a light-emitting phase.
  • the method 1000 includes step S1010-step S1030,
  • step S1010 in the light-emitting stage of the first period, a first light-emitting control signal having a second level is provided, and a second light-emitting control signal and a third light-emitting control signal having the first level are provided.
  • a first light-emitting control signal, a second light-emitting control signal, and a third light-emitting control signal having a first level are provided.
  • the transistor is a P-type transistor, the first level is a high level, and the second level is a low level.
  • Step S1020 in the light-emitting stage of the second time period, a second light-emitting control signal having a second level is provided, and a first light-emitting control signal and a third light-emitting control signal having the first level are provided.
  • a first light-emission control signal, a second light-emission control signal, and a third light-emission control signal having a first level are provided.
  • step S1030 in the light-emitting stage of the third period, a third light-emitting control signal having a second level is provided, and a first light-emitting control signal and a second light-emitting control signal having the first level are provided.
  • the first light-emitting control signal, the second light-emitting control signal, and the third light-emitting control signal having the first level are provided.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本公开提供了一种像素电路及其驱动方法以及显示面板。像素电路包括驱动子电路、发光控制子电路、第一发光元件、第二发光元件和第三发光元件。驱动子电路被配置为在第一节点的电压的控制下将来自第一电源信号端的第一电源电压传递到第二节点。发光控制子电路被配置为在来自第一、第二和第三发光控制端的第一、第二和第三发光控制信号的控制下，将第二节点的电压和来自第二电源信号端的第二电源电压在第一时段分别传递到第一发光元件的第一极和第二极，在第二时段分别传递到第二发光元件的第一极和第二极，在第三时段分别传递到第三发光元件的第一极和第二极。

Description

像素电路及其驱动方法以及显示面板
本公开要求于2019年8月14日提交的、申请号为201910752533.8的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别地涉及一种像素电路及其驱动方法以及显示面板。
背景技术
常规的有机发光二极管(OLED)显示器中，每个像素单元中不同颜色的子像素在面板上横向排列，占用面板空间较大。
发明内容
根据本公开的第一方面，提出了一种像素电路，包括：驱动子电路，与第一节点、第一电源信号端和第二节点电连接，并被配置为在所述第一节点的电压的控制下将来自所述第一电源信号端的第一电源电压传递到所述第二节点，发光控制子电路，与所述第二节点、第二电源信号端、第一发光控制端、第二发光控制端、第三发光控制端、第一发光元件的第一极、第一发光元件的第二极、第二发光元件的第一极、第二发光元件的第二极、第三发光元件的第一极、以及第三发光元件的第二极电连接，并被配置为在来自所述第一发光控制端、所述第二发光控制端和所述第三发光控制端的第一发光控制信号、第二发光控制信号和第三发光控制信号的控制下，将所述第二节点的电压和来自所述第二电源信号端的第二电源电压在第一时段分别传递到所述第一发光元件的所述第一极和所述第一发光元件的所述第二极，在第二时段分别传递到所述第二发光元件的所述第一极和所述第二发光元件的所述第二极，在第三时段分别传递到所述第三发光元件的所述第一极和所述第三发光元件的所述第二极。
在一些实施例中，所述发光控制子电路包括：第一晶体管，所述第一晶体管的控制极与所述第二发光控制端电连接，所述第一晶体管的第一极与所述第二节点电连接，所述第一晶体管的第二极与第四节点电连接，第二晶体管，所述第二晶体管的控制极与所述第一发光控制端电连接，所述第二晶体管的第一极与所述第二节点电连接，所述第二 晶体管的第二极与所述第一发光元件的所述第一极电连接，第三晶体管，所述第三晶体管的控制极与所述第三发光控制端电连接，所述第三晶体管的第一极与所述第二节点电连接，所述第三晶体管的第二极与第五节点电连接，第四晶体管，所述第四晶体管的控制极与所述第一发光控制端电连接，所述第四晶体管的第一极与所述第四节点电连接，所述第四晶体管的第二极与所述第二电源信号端电连接，第五晶体管，所述第五晶体管的控制极与所述第二发光控制端电连接，所述第五晶体管的第一极与所述第五节点电连接，所述第五晶体管的第二极与所述第二电源信号端电连接，所述第一发光元件的所述第二极与所述第二发光元件的所述第一极经由所述第四节点电连接，所述第二发光元件的所述第二极与所述第三发光元件的所述第一极经由所述第五节点电连接，所述第三发光元件的所述第二极与所述第二电源信号端电连接。
在一些实施例中，所述发光控制子电路包括：第一晶体管，所述第一晶体管的控制极与所述第二发光控制端电连接，所述第一晶体管的第一极与所述第二节点电连接，所述第一晶体管的第二极与第四节点电连接，第二晶体管，所述第二晶体管的控制极与所述第三发光控制端电连接，所述第二晶体管的第一极与所述第三发光元件的所述第二极电连接，所述第二晶体管的第二极与所述第二电源信号端电连接，第三晶体管，所述第三晶体管的控制极与所述第三发光控制端电连接，所述第三晶体管的第一极与所述第二节点电连接，所述第三晶体管的第二极与第五节点电连接，第四晶体管，所述第四晶体管的控制极与所述第一发光控制端电连接，所述第四晶体管的第一极与所述第四节点电连接，所述第四晶体管的第二极与所述第二电源信号端电连接，第五晶体管，所述第五晶体管的控制极与所述第二发光控制端电连接，所述第五晶体管的第一极与所述第五节点电连接，所述第五晶体管的第二极与所述第二电源信号端电连接，所述第一发光元件的所述第一极与所述第二节点电连接，所述第一发光元件的所述第二极与所述第二发光元件的所述第一极经由所述第四节点电连接，所述第二发光元件的所述第二极与所述第三发光元件的所述第一极经由所述第五节点电连接。
在一些实施例中，所述驱动子电路包括第六晶体管，其中，所述第六晶体管的控制极与所述第一节点电连接，所述第六晶体管的第一极与所述第一电源信号端电连接，所述第六晶体管的第二极与所述第二节点电连接。
在一些实施例中，所述像素电路还包括：存储子电路，电连接在所述第一节点与第三节点之间，充电控制子电路，与扫描信号端、数据信号端、所述第一节点、所述第二 节点和所述第三节点电连接，被配置为在来自扫描信号端的第一扫描电压的控制下，使所述第一节点和所述第三节点之间产生电压差，复位子电路，与第一复位控制端、第二复位控制端、所述第三节点和复位电压信号端电连接，被配置为在来自第一复位控制端的第一复位控制信号或来自第二复位控制端的第二复位控制信号的控制下，使用来自所述复位电压信号端的复位电压信号对所述第三节点进行复位。
在一些实施例中，所述存储子电路包括第一电容，所述第一电容的第一端与所述第三节点电连接，所述第一电容的第二端与所述第一节点电连接。
在一些实施例中，所述充电控制子电路包括：第七晶体管，所述第七晶体管的控制极与所述扫描信号端电连接，所述第七晶体管的第一极与所述数据信号端电连接，所述第七晶体管的第二极与所述第三节点电连接，第八晶体管，所述第八晶体管的控制极与所述扫描信号端电连接，所述第八晶体管的第一极与所述第一节点电连接，所述第八晶体管的第二极与所述第二节点电连接。
在一些实施例中，所述复位子电路包括：第九晶体管，所述第九晶体管的控制极与所述第一复位控制端电连接，所述第九晶体管的第一极与所述复位电压信号端电连接，所述第九晶体管的第二极与所述第三节点电连接，第十晶体管，所述第十晶体管的控制极与所述第二复位控制端电连接，所述第十晶体管的第一极与所述复位电压信号端电连接，所述第十晶体管的第二极与所述第三节点电连接。
在一些实施例中，所述扫描信号端被配置为接收针对本行像素的扫描信号，所述第一复位控制端被配置为接收针对上一行像素的扫描信号，所述第二复位控制端被配置为接收针对下一行像素的扫描信号。
根据本公开的第二方面，提供一种显示面板，包括多个像素单元，所述多个像素单元中的至少一个像素单元包括如上所述的像素电路。
在一些实施例中，所述至少一个像素单元中的每一个像素单元包括：基板；控制电路层，设置在所述基板上，包括所述驱动子电路和所述发光控制子电路；中间层，设置在所述控制电路层的远离所述基板的一侧，并被构造成覆盖所述控制电路层；在所述中间层上顺序地堆叠第一电极层、第一发光层、第二电极层、第二发光层、第三电极层、第三发光层和第四电极层，其中，所述第一发光层、所述第二发光层和所述第三发光层分别用作第一发光元件、第二发光元件和第三发光元件。
在一些实施例中，所述基板包括彼此不重叠的第一区域和第二区域，其中，所述驱 动子电路的至少一部分和所述发光控制子电路的至少一部分在所述基板上的投影位于所述第一区域内；所述第一电极层的至少一部分、所述第一发光层、所述第二电极层的至少一部分、所述第二发光层、所述第三电极层的至少一部分、所述第三发光层和所述第四电极层的至少一部分在所述基板上的投影位于所述第二区域内。
在一些实施例中，所述第一电极层、所述第二电极层和所述第三电极层分别通过贯穿所述中间层的通孔与所述发光控制子电路电连接。
在一些实施例中，所述第一电极层的材料包括不透明材料，所述第二电极层、所述第三电极层和所述第四电极层的材料包括透明材料。
根据本公开的第三方面，提供一种对如上所述的像素电路进行驱动的方法，其中，第一时段、第二时段和第三时段中的每一个都包括初始化阶段、充电阶段和发光阶段，所述方法包括：在所述第一时段的发光阶段，提供具有第二电平的第一发光控制信号，提供具有第一电平的第二发光控制信号和第三发光控制信号，在所述第二时段的发光阶段，提供具有第二电平的第二发光控制信号，提供具有第一电平的第一发光控制信号和第三发光控制信号，在所述第三时段的发光阶段，提供具有第二电平的第三发光控制信号，提供具有第一电平的第一发光控制信号和第二发光控制信号，在每一个时段的初始化阶段和充电阶段，提供具有第一电平的第一发光控制信号、第二发光控制信号和第三发光控制信号。
根据本公开的第四方面，提供一种显示面板，包括多个像素单元，每个像素单元包括：基板；控制电路层，设置在所述基板上；中间层，设置在所述控制电路层的远离所述基板的一侧；在所述中间层上顺序地堆叠的第一电极层、第一发光层、第二电极层、第二发光层、第三电极层、第三发光层和第四电极层，其中，所述第一发光层、所述第二发光层和所述第三发光层分别用作第一发光元件、第二发光元件和第三发光元件。
在一些实施例中，所述基板包括彼此不重叠的第一区域和第二区域，其中，所述第一电极层的至少一部分、所述第一发光层、所述第二电极层的至少一部分、所述第二发光层、所述第三电极层的至少一部分、所述第三发光层和所述第四电极层的至少一部分在所述基板上的投影位于所述第二区域内。
在一些实施例中，所述第一电极层、第二电极层和第三电极层分别通过贯穿所述中间层的通孔与控制电路层电连接。
在一些实施例中，所述第一电极层包括不透明材料，所述第二电极层、所述第三电 极层和所述第四电极层包括透明材料。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，图中：
图1示出了根据相关技术的显示面板的像素单元的示意截面图。
图2A示出了根据本公开实施例的显示面板的像素单元的示意截面图。
图2B示出了根据本公开实施例的显示面板的另一像素单元的示意截面图。
图3示出了根据本公开实施例的像素单元的更为详细的层结构图。
图4示出了根据本公开实施例的像素单元中的像素电路的电路结构图。
图5示出了图4中的像素电路的进一步的电路结构图。
图6示出了图5所示的像素电路的详细电路图。
图7A示出了图6的像素电路的信号时序图。
图7B-图7F示出了图6的像素电路的各阶段原理示意图。
图8示出了图5所示的像素电路的另一详细电路图。
图9示出了根据本公开实施例的显示面板的示意方框图。
图10示出了根据本公开实施例的像素电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内 容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“电连接”可以是指两个组件直接电连接，也可以是指两个组件之间经由一个或多个其他组件电连接。此外，这两个组件可以通过有线或无线方式电连接或耦接。
在以下实施例中，并没有对显示器的具体类型进行限定，但本领域技术人员应该理解的是，任何通过设置发光层并在发光层两端施加电压的方式发光的显示器(例如，OLED显示器、量子点发光二极管(QLED)显示器)都被本公开涵盖在内。
本公开实施例中采用的晶体管均可以为薄膜晶体管(TFT)或场效应管或其他特性相同的器件。根据在电路中的作用，本公开实施例使用的晶体管主要为开关晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。在以下示例中以驱动晶体管为P型薄膜晶体管的情况进行描述，其他晶体管根据电路设计与驱动晶体管具有相同或不同的类型。类似地，在其他实施例中，驱动晶体管也可以被示为N型薄膜晶体管。本领域技术人员能够理解的是，通过将其他晶体管的类型相应地改变并将各驱动信号和电平信号进行反相(和/或进行其他附加的适应性修改)，同样能够实现本公开的技术方案。
此外，在本公开实施例的描述中，术语“第一电平”和“第二电平”仅用于区别两个电平的幅度不同。在一些实施例中，“第一电平”可以是使相关晶体管截止的无效电平，“第二电平”可以是使相关晶体管导通的有效电平。下文中，由于驱动晶体管被示例为P型薄膜晶体管，因此“第一电平”被示例为高电平，“第二电平”被示例为低电平。
以下参考附图对本公开进行具体描述。
图1示出了根据相关技术的显示面板的像素单元100的示意截面图。
显示面板包括多个像素单元100。如图1所示，像素单元100包括基板110、控制 电路层120、第一电极层130、发光层140和第二电极层150。
基板110可以是例如玻璃基板。
控制电路层120中形成有像素电路。例如，控制电路层120中可以包括被配置为控制不同发光元件(子像素)的多个像素电路。
第一电极层130设置在所述控制电路层120的远离所述基板110的一侧。第一电极层130中可以包括多个驱动电极，分别连接到控制电路层120中的不同像素电路，以从相应像素电路接收用于驱动发光层140中的不同发光元件的驱动电压。第一电极层130的一部分设置在像素单元100中的发光区中，所述第一电极层130可以包括不透明材料(例如，Al和Ag)。
在一些实施例中，还可设置有一个或多个中间层，所述中间层位于控制电路层120和第一电极层130之间或在发光区之外包围第一电极层130。第一电极层130通过贯穿所述一个或多个中间层的通孔与控制电路层120中的像素电路电连接。所述中间层可以包括层间介质层(ILD)和各种平坦层、绝缘层或有机层。
发光层140包括并排布置的三个部分，分别对应于像素单元100中的红色发光元件(R)、绿色发光元件(G)和蓝色发光元件(B)，以发射红、绿和蓝三种颜色的光。如上文所述，每个发光元件对应于控制电路层120中的一个像素电路和第一电极层130中的一个电极，以通过所对应的电极从所对应的像素电路接收驱动电压。发光层140充当像素电路中的发光元件。
第二电极层150可以包括公共电极，面板上各像素单元的各发光元件可以共用同一电极，所述公共电极可以是透明电极(例如，由氧化铟锡(ITO)制成)。
在图1的像素结构中，不同颜色的发光元件在面板上横向排列，占用面板空间较大，不利于高PPI的实现。
图2A示出了根据本公开实施例的显示面板的像素单元200的示意截面图。
如图2A所示，像素单元200包括基板210、控制电路层220、第一电极层230、第一发光层240、第二电极层250、第二发光层260、第三电极层270、第三发光层280和第四电极层290。
基板210可以是例如玻璃基板。
控制电路层220中形成有像素电路。例如，控制电路层220中可以形成单个像素电路，该单个像素电路被配置为在不同的时段分别控制像素单元200中的各个发光层发光。
第一电极层230设置在所述控制电路层220的远离所述基板210的一侧。第一电极层230中可以包括单个驱动电极，其与控制电路层220中的像素电路电连接，以在一帧中的第一时段从像素电路接收用于驱动第一发光层240的驱动电压。第一电极层230的一部分设置在像素单元200的发光区内，其中，驱动电极可以包括不透明材料(例如，A1和Ag)。
在一些实施例中，如图2B所示，还设置有一个或多个中间层225，中间层225可以设置在控制电路层220和第一电极层230之间或者在发光区之外包围第一电极层230以及之上的层结构。第一电极层230通过贯穿中间层的通孔与控制电路层220中的像素电路电连接。所述中间层可以包括层间介质层(ILD)和各种平坦层、绝缘层或有机层。
第一发光层240包括单个部分，对应于像素单元200中的红色发光元件(R)，用来发射红光。第一发光层240通过所述第一电极层230中的驱动电极从所控制电路层220中的像素电路接收驱动电压。
第二电极层250设置在所述第一发光层240远离所述基板210的一侧。第二电极层250中可以包括单个电极，其与控制电路层220中的像素电路电连接，以在一帧中的第一时段接收公共电压，在一帧中的第二时段从像素电路接收用于驱动第二发光层260发光的驱动电压。第二电极层250中的驱动电极可以是透明电极。为了实现第二电极层250与控制电路层220中的像素电路的电连接，需要在中间层中设置通孔。
第二发光层260包括单个部分，对应于像素单元200中的绿色发光元件(G)，用来发射绿光。第二发光层260通过所述第二电极层250中的驱动电极从所控制电路层220中的像素电路接收驱动电压。
第三电极层270设置在所述第二发光层260的远离所述基板210的一侧。第三电极层270中可以包括单个电极，其与控制电路层220中的像素电路电连接，以在一帧中的第二时段接收公共电压，在一帧中的第三时段从像素电路接收用于驱动第三发光层280发光的驱动电压。第三电极层270中的驱动电极可以是透明电极。为了实现第三电极层 270与控制电路层220中的像素电路的电连接，需要在中间层中设置通孔。
第三发光层280包括单个部分，对应于像素单元200中的蓝色发光元件(B)，用来发射蓝光。第三发光层280通过所述第三电极层270中的驱动电极从所控制电路层220中的像素电路接收驱动电压。
第四电极层290设置在第三发光层280的远离所述基板210的一侧。第四电极层290中可以包括单个电极，其与控制电路层220中的像素电路电连接，以在一帧中的第三时段接收公共电压。第四电极层290中的驱动电极可以是透明电极。为了实现第四电极层290与控制电路层220中的像素电路的电连接，需要在中间层中设置通孔。
图3示出了根据本公开实施例的像素单元的更为详细的层结构图。
如图3所示，像素单元300的结构包括依次堆叠的基板310、缓冲层320、控制电路层330、第一中间层340、第二中间层350、第三中间层360、第一电极层370、第一发光层371、第二电极层372、第二发光层373、第三电极层374、第三发光层375和第四电极层376。其中，第一发光层371、第二发光层373和第三发光层375位于像素单元的发光区。第一电极层370、第二电极层372、第三电极层374和第四电极层376的一部分位于发光区内，第一电极层370、第二电极层372、第三电极层374和第四电极层376的另一部分位于TFT区内，以便与像素电路或公共电源线电连接。应该理解的是，在其他实施例中，可以去除图3中所示结构中的某些层(例如，缓冲层320)或增加新的层，也可以对某些层的结构进行改变，本公开对此不加以限制。
示例性地，图3中的基板310包括TFT区(第一区域)和发光区(第二区域)，所述第一区域与所述第二区域不重叠。
示例性地，图3中的第一中间层340和第二中间层350设置在所述控制电路层330和第一电极层370之间，所述第三中间层360在发光区之外包围第一电极层370。
示例性地，图3中的控制电路层330示出了像素电路中的两个晶体管M1和M2。晶体管M1的源极和漏极之一通过通孔V1与第一电极层370电连接，其中，第一电极层370的一部分形成在通孔V1中。晶体管M2通过通孔V2与第二电极层372电连接，其中，第二电极层372与设置在通孔V2中的电连接层3721电连接，所述电连接层3721与所述第一电极层370同层设置，并且所述电连接层3721与所述第二电极层372采用不 同的材料制成。第三电极层374同样与像素电路中的晶体管电连接，但图3中截取了像素单元的特定截面图的一部分，并未示出与第三电极层374连接的晶体管。
从图2A-2B的示意图和图3的示例层结构图可见，通过在原本设置单个发光元件的区域在竖向方向顺序地堆叠三个发光元件，并通过原本用于对单个发光元件进行驱动的像素电路对三个发光元件分别进行驱动，能够节省每个像素单元所占用的面板空间，更有利于高PPI的实现。
为了实现显示面板的正常显示，需要对像素电路和信号时序进行设计，使得三个发光元件在不同的时段发光，每一个发光元件都不会受到其他发光元件的驱动影响。
图4示出了根据本公开实施例的像素单元中的像素电路400的电路结构图。
如图4所示，像素电路400包括驱动子电路410、发光控制子电路420、第一发光元件R、第二发光元件G和第三发光元件B。
驱动子电路410与第一节点N1、第一电源信号端VDD和第二节点N2电连接。驱动子电路410被配置为在第一节点N1的电压的控制下将来自第一电源信号端VDD的第一电源电压传递到第二节点N2。
发光控制子电路420与第二节点N2、第二电源信号端VSS、第一发光控制端EM1、第二发光控制端EM2、第三发光控制端EM3、第一发光元件R的第一极和第二极、第二发光元件G的第一极和第二极、以及第三发光元件B的第一极和第二极电连接，所述发光控制子电路420被配置为在来自第一发光控制端EM1、第二发光控制端EM2和第三发光控制端EM3的第一发光控制信号、第二发光控制信号和第三发光控制信号的控制下，使第二节点N2的电压和来自第二电源信号端VSS的第二电源电压在第一时段分别传递到第一发光元件R的第一极和第二极，在第二时段分别传递到第二发光元件G的第一极和第二极，在第三时段分别传递到第三发光元件B的第一极和第二极。
如此，图4中的电路结构能够实现三个不同的发光元件R、G和B在一帧中的不用时段的分时驱动，使得图2A、图2B和图3中的像素单元能够实现显示。
图5示出了图4中的像素电路的进一步的电路结构图。
在图4的基础上，图5中的像素电路500还包括存储子电路430、充电控制子电路440和复位子电路450。
存储子电路430电连接在第一节点N1与第三节点N3之间。
充电控制子电路440与扫描信号端Scan、数据信号端Data、第一节点N1、第二节点N2、第三节点N3电连接，并被配置为在来自扫描信号端Scan的第一扫描电压的控制下，使第一节点N1和第三节点N3之间产生电压差。
复位子电路450与第一复位控制端Reset1、第二复位控制端Reset2、第三节点N3和复位电压信号端Vini电连接，并被配置为在来自第一复位控制端Reset1的第一复位控制信号或来自第二复位控制端Reset2的第二复位控制信号的控制下，使用来自复位电压信号端Vini的复位电压信号对第三节点N3进行复位。
图6示出了图5所示的像素电路的详细电路图。
如图6所示，发光控制子电路420可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5。
第一晶体管T1的控制极与第二发光控制端EM2电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的第二极与第四节点N4电连接。
第二晶体管T2的控制极与第一发光控制端EM1电连接，第二晶体管T2的第一极与第二节点N2电连接，第二晶体管T2的第二极与第一发光元件R的第一极电连接。
第三晶体管T3的控制极与第三发光控制端EM3电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第五节点N5电连接。
第四晶体管T4的控制极与第一发光控制端EM1电连接，第四晶体管T4的第一极与第四节点N4电连接，第四晶体管T4的第二极与第二电源信号端VSS电连接。
第五晶体管T5的控制极与第二发光控制端EM2电连接，第五晶体管T5的第一极与第五节点N5电连接，第五晶体管T5的第二极与第二电源信号端VSS电连接。
第一发光元件R的第二极与第二发光元件G的第一极经由第四节点N4电连接，第二发光元件G的第二极与第三发光元件B的第一极经由第五节点N5电连接，第三发光元件B的第二极与第二电源信号端VSS电连接。
驱动子电路410包括第六晶体管T6。
第六晶体管T6的控制极与第一节点N1电连接，第六晶体管T6的第一极与第一电源信号端VDD电连接，第六晶体管T6的第二极与第二节点N2电连接。
存储子电路430包括第一电容C1。
第一电容C1的第一端与第三节点N3电连接，第一电容C1的第二端与第一节点N1电连接。
充电控制子电路440包括第七晶体管T7和第八晶体管T8。
第七晶体管T7的控制极与扫描信号端Scan电连接，第七晶体管T7的第一极与数据信号端Data电连接，第七晶体管T7的第二极与第三节点N3电连接。
第八晶体管T8的控制极与扫描信号端Scan电连接，第八晶体管T8的第一极与第一节点N1电连接，第八晶体管T8的第二极与第二节点N2电连接。
复位子电路450包括第九晶体管T9和第十晶体管T10。
第九晶体管T9的控制极与第一复位控制端Reset1电连接，第九晶体管T9的第一极与复位电压信号端Vini电连接，第九晶体管T9的第二极与第三节点N3电连接。
第十晶体管T10的控制极与第二复位控制端Reset2电连接，第十晶体管T10的第一极与复位电压信号端Vini电连接，第十晶体管T10的第二极与第三节点N3电连接。
在一些实施例中，扫描信号端Scan被配置为接收针对本行像素的扫描信号，第一复位控制端Reset1被配置为接收针对上一行像素的扫描信号，第二复位控制端Reset2被配置为接收针对下一行像素的扫描信号。在以下描述中，以这一情形作为示例进行描述。
图7A示出了图6的像素电路的信号时序图。图7B-图7F示出了图6的像素电路的各阶段原理示意图。
例如，参见图7A，每一帧中分三个时段tp1、tp2和tp3，每个时段分别用于驱动一个发光元件(即一个子像素)发光。例如，tp1时段用于驱动第一发光元件R，tp2时段用于驱动第二发光元件G，tp3时段用于驱动第三发光元件B。每个时段又分为三个阶段，即初始化阶段、充电阶段以及发光阶段。
先描述第一时段tp1，在此时段将驱动第一发光元件R发光。
在初始化阶段P1期间，第一发光控制端EM1、第二发光控制端EM2和第三发光控制端EM3均提供高电平信号，从而T1-T5全部截止。
第一复位控制端Reset1提供低电平信号，第二复位控制端Reset2和扫描信号端 Scan提供高电平信号。从而，T7、T8和T10截止，T9导通。通过Vini将第三节点N3复位。假定Vini的电压为VGL，则此时第三节点N3被复位为VGL。并且，通过电容C1的作用，第三节点N3的电压将浮置的第一节点N1的电压变为VGL，使得T6导通，将第一电源端VDD的电压Vdd传送到第二节点N2。
在P1阶段，像素电路的原理示意图如图7B所示，应该指出的是，图7B中将本阶段截止的晶体管通过斜十字“×”标记。
在充电阶段P2期间，第一发光控制端EM1、第二发光控制端EM2和第三发光控制端EM3保持提供高电平信号，从而T1-T5保持截止。
扫描信号端Scan提供提供低电平信号，第一复位控制端Reset1与第二复位控制端Reset2提供高电平信号。从而，T7、T8导通，T9和T10截止。此时，高电平数据电压Vdata通过数据信号端Data输入到第三节点N3，将第一电容C1的第一端的电平变为Vdata。另一方面，第一节点N1和第二节点N2电连接，第一电源信号端VDD开始对第一节点充电，直到N1点的电平变为Vdd+Vth时达到平衡，其中Vth是第六晶体管T6的阈值电压。
在这一阶段，通过数据电压端Data和第一电源端VDD的充电，在第一电容C1的两端施加了不同的电压，产生了电压差Vdd+Vth-Vdata。
在P2阶段，像素电路的原理示意图如图7C所示，应该指出的是，图7C中将本阶段截止的晶体管通过斜十字“×”标记。
在发光阶段P3期间，第二发光控制端EM2和第三发光控制端EM3保持提供高电平信号，第一发光控制端EM1提供低电平信号，从而T1、T3和T5保持截止，T2和T4导通，使得第一发光元件R的两端分别与第二节点N2和第二电源端VSS接通。
扫描信号端Scan和第一复位控制端Reset1提供高电平信号，第二复位控制端Reset2提供低电平信号。从而，T10导通，T7至T9截止。此时，复位信号端Vini将第三节点N3的电压变为VGL。由于第一节点N1再次变为浮置，第一电容C1保持此前产生的压差。从而，第一节点N1的电压变为Vdd+Vth-Vdata+VGL。此时，第六晶体管T6处于饱和状态。对于P型晶体管T6来讲，其源栅电压Vsg为：
Vsg＝Vdd-(Vdd+Vth-Vdata+VGL)＝Vdata-VGL-Vth。
从而，驱动电流Id的表达式为：
Id＝K·(Vgs-Vth) 2
＝K·(-Vdata+VGL+Vth-Vth) 2
＝K·(Vdata-VGL) 2
其中，K为关联于第六晶体管T6的电流常数，与第六晶体管T6的工艺参数和几何尺寸有关。由以上公式可知，用于驱动第一发光元件R进行发光的驱动电流Id与第六晶体管T6的阈值电压Vth无关，从而可以消除由于第六晶体管T6的阈值电压Vth存在差异而导致的发光元件亮度不均的现象。
在P3阶段，像素电路的原理示意图如图7D所示，应该指出的是，图7D中将本阶段截止的晶体管通过斜十字“×”标记。
接下来描述第二时段tp2，在此时段将驱动第二发光元件G发光。
从时序图图7A可以看出，第二时段tp2的初始化阶段P4和充电阶段P5与第一时段tp1的初始化阶段P1和充电阶段P2的操作完全相同，在此不再进行赘述。
第二时段tp2与第一时段tp1的区别在于发光阶段，在发光阶段P6期间，第一发光控制端EM1和第三发光控制端EM3保持提供高电平信号，第二发光控制端EM2提供低电平信号，从而T2、T3和T4截止，T1和T5导通，使得第二发光元件G的两端分别与第二节点N2和第二电源端VSS接通。
扫描信号端Scan和第一复位控制端Reset1提供高电平信号，第二复位控制端Reset2提供低电平信号。从而，T10导通，T7至T9截止。此时，复位信号端Vini将第三节点N3的电压变为VGL。由于第一节点N1再次变为浮置，第一电容C1保持此前产生的压差。从而，第一节点N1的电压变为Vdd+Vth-Vdata+VGL。此时，第六晶体管T6处于饱和状态。对于P型晶体管T6来讲，其源栅电压Vsg为：
Vsg＝Vdd-(Vdd+Vth-Vdata+VGL)＝Vdata-VGL-Vth。
从而，驱动电流Id的表达式为：
Id＝K·(Vgs-Vth) 2
＝K·(-Vdata+VGL+Vth-Vth) 2
＝K·(Vdata-VGL) 2
其中，K为关联于第六晶体管T6的电流常数，与第六晶体管T6的工艺参数和几何尺寸有关。由以上公式可知，用于驱动第二发光元件G进行发光的驱动电流Id与第六晶体管T6的阈值电压Vth无关，从而可以消除由于第六晶体管T6的阈值电压Vth存在差异而导致的发光元件亮度不均的现象。
在P6阶段，像素电路的原理示意图如图7E所示，应该指出的是，图7E中将本阶段截止的晶体管通过斜十字“×”标记。
最后，描述第三时段tp3，在此时段将驱动第三发光元件B发光。
从时序图图7A可以看出，第三时段tp3的初始化阶段P7和充电阶段P8与第一时段tp1的初始化阶段P1和充电阶段P2的操作完全相同，在此不再进行赘述。
第三时段tp3与第一时段tp1的区别在于发光阶段，在发光阶段P9期间，第一发光控制端EM1和第二发光控制端EM2保持提供高电平信号，第三发光控制端EM3提供低电平信号，从而T1、T2、T4和T5截止，T3导通，使得第三发光元件B的两端分别与第二节点N2和第二电源端VSS接通。
扫描信号端Scan和第一复位控制端Reset1提供高电平信号，第二复位控制端Reset2提供低电平信号。从而，T10导通，T7至T9截止。此时，复位信号端Vini将第三节点N3的电压变为VGL。由于第一节点N1再次变为浮置，第一电容C1保持此前产生的压差。从而，第一节点N1的电压变为Vdd+Vth-Vdata+VGL。此时，第六晶体管T6处于饱和状态。对于P型晶体管T6来讲，其源栅电压Vsg为：
Vsg＝Vdd-(Vdd+Vth-Vdata+VGL)＝Vdata-VGL-Vth。
从而，驱动电流Id的表达式为：
Id＝K·(Vgs-Vth) 2
＝K·(-Vdata+VGL+Vth-Vth) 2
＝K·(Vdata-VGL) 2
其中，K为关联于第六晶体管T6的电流常数，与第六晶体管T6的工艺参数和几何尺寸有关。由以上公式可知，用于驱动第三发光元件B进行发光的驱动电流Id与第六晶体管T6的阈值电压Vth无关，从而可以消除由于第六晶体管T6的阈值电压Vth存在差异而导致的发光元件亮度不均的现象。
在P9阶段，像素电路的原理示意图如图7F所示，应该指出的是，图7F中将本阶段截止的晶体管通过斜十字“×”标记。
图8示出了图5所示的像素电路的另一详细电路图。图8中的像素电路800与图6中的像素电路600的区别在于发光控制子电路420的电路结构不同。在此，对其他子电路的电路结构不再赘述。
如图8所示，发光控制子电路420可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5。
第一晶体管T1的控制极与第二发光控制端EM2电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的第二极与第四节点N4电连接。
第二晶体管T2的控制极与第三发光控制端EM3电连接，第二晶体管T2的第一极与第三发光元件B的第二极电连接，第二晶体管T2的第二极与第二电源信号端VSS电连接。
第三晶体管T3的控制极与第三发光控制端EM3电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第五节点N5电连接。
第四晶体管T4的控制极与第一发光控制端EM1电连接，第四晶体管T4的第一极与第四节点N4电连接，第四晶体管T4的第二极与第二电源信号端VSS电连接。
第五晶体管T5的控制极与第二发光控制端EM2电连接，第五晶体管T5的第一极与第五节点N5电连接，第五晶体管T5的第二极与第二电源信号端VSS电连接。
第一发光元件R的第一极与第二节点N2电连接，第一发光元件R的第二极与第二发光元件G的第一极经由第四节点N4电连接，第二发光元件G的第二极与第三发光元件B的第一极经由第五节点N5电连接。
图9示出了根据本公开实施例的显示面板900的示意方框图。
如图9所示，显示面板900可以包括多条扫描线SL；多条数据线DL，与所述多条扫描线SL纵横交叉设置；以及多个像素单元910，以矩阵的形式设置在每个扫描线和每个数据线的交叉处，并且与对应的数据线DL和扫描线SL电连接。所述多个像素单元910中的每一个中均设置有根据本公开实施例的像素电路，例如根据图2A 2B、图3、图4、图5、图6或图8所示的像素电路。
当通过图4、图5、图6或图8中的像素电路来实现图9的显示面板900时，像素电路中的数据信号端Data从对应数据线DL接收数据信号，像素电路中的扫描信号端Scan从对应扫描线SL接收扫描信号。
显示面板900可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图10示出了根据本公开实施例的像素电路的驱动方法1000的流程图。如上文所述，对像素电路的驱动分第一时段、第二时段和第三时段进行，每一个时段都包括初始化阶段、充电阶段和发光阶段。
所述方法1000包括步骤S1010-步骤S1030，
步骤S1010，在第一时段的发光阶段，提供具有第二电平的第一发光控制信号，提供具有第一电平的第二发光控制信号和第三发光控制信号。
此外，在第一时段的初始化阶段和充电阶段，提供具有第一电平的第一发光控制信号、第二发光控制信号和第三发光控制信号。
在如图6或图8所述的实施例中，晶体管是P型晶体管，第一电平为高电平，第二电平为低电平。
步骤S1020，在第二时段的发光阶段，提供具有第二电平的第二发光控制信号，提供具有第一电平的第一发光控制信号和第三发光控制信号。
此外，在第二时段的初始化阶段和充电阶段，提供具有第一电平的第一发光控制信号、第二发光控制信号和第三发光控制信号。
步骤S1030，在第三时段的发光阶段，提供具有第二电平的第三发光控制信号，提供具有第一电平的第一发光控制信号和第二发光控制信号。
此外，在第三时段的初始化阶段和充电阶段，提供具有第一电平的第一发光控制信号、第二发光控制信号和第三发光控制信号。以上的详细描述通过使用示意图、流程图和/或示例，已经阐述了众多实施例。在这种示意图、流程图和/或示例包含一个或多个功能和/或操作的情况下，本领域技术人员应理解，这种示意图、流程图或示例中的每一功能和/或操作可以通过各种结构、硬件、软件、固件或实质上它们的任意组合来单独和/或共同实现。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (19)

  1. 一种像素电路，包括：
    驱动子电路，与第一节点、第一电源信号端和第二节点电连接，并被配置为在所述第一节点的电压的控制下将来自所述第一电源信号端的第一电源电压传递到所述第二节点，
    发光控制子电路，与所述第二节点、第二电源信号端、第一发光控制端、第二发光控制端、第三发光控制端、第一发光元件的第一极、第一发光元件的第二极、第二发光元件的第一极、第二发光元件的第二极、第三发光元件的第一极、以及第三发光元件的第二极电连接，并被配置为在来自所述第一发光控制端、所述第二发光控制端和所述第三发光控制端的第一发光控制信号、第二发光控制信号和第三发光控制信号的控制下，将所述第二节点的电压和来自所述第二电源信号端的第二电源电压在第一时段分别传递到所述第一发光元件的所述第一极和所述第一发光元件的所述第二极，在第二时段分别传递到所述第二发光元件的所述第一极和所述第二发光元件的所述第二极，在第三时段分别传递到所述第三发光元件的所述第一极和所述第三发光元件的所述第二极。
  2. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括：
    第一晶体管，所述第一晶体管的控制极与所述第二发光控制端电连接，所述第一晶体管的第一极与所述第二节点电连接，所述第一晶体管的第二极与第四节点电连接，
    第二晶体管，所述第二晶体管的控制极与所述第一发光控制端电连接，所述第二晶体管的第一极与所述第二节点电连接，所述第二晶体管的第二极与所述第一发光元件的所述第一极电连接，
    第三晶体管，所述第三晶体管的控制极与所述第三发光控制端电连接，所述第三晶体管的第一极与所述第二节点电连接，所述第三晶体管的第二极与第五节点电连接，
    第四晶体管，所述第四晶体管的控制极与所述第一发光控制端电连接，所述第四晶体管的第一极与所述第四节点电连接，所述第四晶体管的第二极与所述第二电源信号端电连接，
    第五晶体管，所述第五晶体管的控制极与所述第二发光控制端电连接，所述第五晶体管的第一极与所述第五节点电连接，所述第五晶体管的第二极与所述第二电源信号端电连接，
    所述第一发光元件的所述第二极与所述第二发光元件的所述第一极经由所述第四节点电连接，所述第二发光元件的所述第二极与所述第三发光元件的所述第一极经由所述第五节点电连接，所述第三发光元件的所述第二极与所述第二电源信号端电连接。
  3. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括：
    第一晶体管，所述第一晶体管的控制极与所述第二发光控制端电连接，所述第一晶体管的第一极与所述第二节点电连接，所述第一晶体管的第二极与第四节点电连接，
    第二晶体管，所述第二晶体管的控制极与所述第三发光控制端电连接，所述第二晶体管的第一极与所述第三发光元件的所述第二极电连接，所述第二晶体管的第二极与所述第二电源信号端电连接，
    第三晶体管，所述第三晶体管的控制极与所述第三发光控制端电连接，所述第三晶体管的第一极与所述第二节点电连接，所述第三晶体管的第二极与第五节点电连接，
    第四晶体管，所述第四晶体管的控制极与所述第一发光控制端电连接，所述第四晶体管的第一极与所述第四节点电连接，所述第四晶体管的第二极与所述第二电源信号端电连接，
    第五晶体管，所述第五晶体管的控制极与所述第二发光控制端电连接，所述第五晶体管的第一极与所述第五节点电连接，所述第五晶体管的第二极与所述第二电源信号端电连接，
    所述第一发光元件的所述第一极与所述第二节点电连接，所述第一发光元件的所述第二极与所述第二发光元件的所述第一极经由所述第四节点电连接，所述第二发光元件的所述第二极与所述第三发光元件的所述第一极经由所述第五节点电连接。
  4. 根据权利要求1所述的像素电路，其中，所述驱动子电路包括第六晶体管，其中，
    所述第六晶体管的控制极与所述第一节点电连接，所述第六晶体管的第一极与所述第一电源信号端电连接，所述第六晶体管的第二极与所述第二节点电连接。
  5. 根据权利要求1-4中的任一项所述的像素电路，还包括：
    存储子电路，电连接在所述第一节点与第三节点之间，
    充电控制子电路，与扫描信号端、数据信号端、所述第一节点、所述第二节点和所述第三节点电连接，被配置为在来自扫描信号端的第一扫描电压的控制下，使所述第一节点和所述第三节点之间产生电压差，
    复位子电路，与第一复位控制端、第二复位控制端、所述第三节点和复位电压信号端电连接，被配置为在来自第一复位控制端的第一复位控制信号或来自第二复位控制端的第二复位控制信号的控制下，使用来自所述复位电压信号端的复位电压信号对所述第三节点进行复位。
  6. 根据权利要求5所述的像素电路，其中，所述存储子电路包括第一电容，
    所述第一电容的第一端与所述第三节点电连接，所述第一电容的第二端与所述第一节点电连接。
  7. 根据权利要求5所述的像素电路，其中，所述充电控制子电路包括：
    第七晶体管，所述第七晶体管的控制极与所述扫描信号端电连接，所述第七晶体管的第一极与所述数据信号端电连接，所述第七晶体管的第二极与所述第三节点电连接，
    第八晶体管，所述第八晶体管的控制极与所述扫描信号端电连接，所述第八晶体管的第一极与所述第一节点电连接，所述第八晶体管的第二极与所述第二节点电连接。
  8. 根据权利要求5所述的像素电路，其中，所述复位子电路包括：
    第九晶体管，所述第九晶体管的控制极与所述第一复位控制端电连接，所述第九晶体管的第一极与所述复位电压信号端电连接，所述第九晶体管的第二极与所述第三节点电连接，
    第十晶体管，所述第十晶体管的控制极与所述第二复位控制端电连接，所述第十晶体管的第一极与所述复位电压信号端电连接，所述第十晶体管的第二极与所述 第三节点电连接。
  9. 根据权利要求5所述的像素电路，其中，所述扫描信号端被配置为接收针对本行像素的扫描信号，所述第一复位控制端被配置为接收针对上一行像素的扫描信号，所述第二复位控制端被配置为接收针对下一行像素的扫描信号。
  10. 一种显示面板，包括多个像素单元，所述多个像素单元中的至少一个像素单元包括根据权利要求1-9中的任一项所述的像素电路。
  11. 根据权利要求10所述的显示面板，其中，所述至少一个像素单元中的每一个像素单元包括：
    基板；
    控制电路层，设置在所述基板上，包括所述驱动子电路和所述发光控制子电路；
    中间层，设置在所述控制电路层的远离所述基板的一侧，并被构造成覆盖所述控制电路层；
    在所述中间层上顺序地堆叠第一电极层、第一发光层、第二电极层、第二发光层、第三电极层、第三发光层和第四电极层，其中，所述第一发光层、所述第二发光层和所述第三发光层分别用作第一发光元件、第二发光元件和第三发光元件。
  12. 根据权利要求11所述的显示面板，其中，所述基板包括彼此不重叠的第一区域和第二区域，其中，
    所述驱动子电路的至少一部分和所述发光控制子电路的至少一部分在所述基板上的投影位于所述第一区域内；
    所述第一电极层的至少一部分、所述第一发光层、所述第二电极层的至少一部分、所述第二发光层、所述第三电极层的至少一部分、所述第三发光层和所述第四电极层的至少一部分在所述基板上的投影位于所述第二区域内。
  13. 根据权利要求11所述的显示面板，其中，所述第一电极层、所述第二电极层和所述第三电极层分别通过贯穿所述中间层的通孔与所述发光控制子电路电连接。
  14. 根据权利要求11所述的显示面板，其中，所述第一电极层的材料包括不透明材料，所述第二电极层、所述第三电极层和所述第四电极层的材料包括透明材料。
  15. 一种对根据权利要求1-9所述的像素电路进行驱动的方法，其中，第一时段、第二时段和第三时段中的每一个都包括初始化阶段、充电阶段和发光阶段，所述方法包括：
    在所述第一时段的发光阶段，提供具有第二电平的第一发光控制信号，提供具有第一电平的第二发光控制信号和第三发光控制信号，
    在所述第二时段的发光阶段，提供具有第二电平的第二发光控制信号，提供具有第一电平的第一发光控制信号和第三发光控制信号，
    在所述第三时段的发光阶段，提供具有第二电平的第三发光控制信号，提供具有第一电平的第一发光控制信号和第二发光控制信号，
    在每一个时段的初始化阶段和充电阶段，提供具有第一电平的第一发光控制信号、第二发光控制信号和第三发光控制信号。
  16. 一种显示面板，包括多个像素单元，每个像素单元包括：
    基板；
    控制电路层，设置在所述基板上；
    中间层，设置在所述控制电路层的远离所述基板的一侧；
    在所述中间层上顺序地堆叠的第一电极层、第一发光层、第二电极层、第二发光层、第三电极层、第三发光层和第四电极层，其中，所述第一发光层、所述第二发光层和所述第三发光层分别用作第一发光元件、第二发光元件和第三发光元件。
  17. 根据权利要求16所述的显示面板，其中，所述基板包括彼此不重叠的第一区域和第二区域，其中，
    所述第一电极层的至少一部分、所述第一发光层、所述第二电极层的至少一部分、所述第二发光层、所述第三电极层的至少一部分、所述第三发光层和所述第四电极层的至少一部分在所述基板上的投影位于所述第二区域内。
  18. 根据权利要求16所述的显示面板，其中，所述第一电极层、第二电极层和第三电极层分别通过贯穿所述中间层的通孔与控制电路层电连接。
  19. 根据权利要求16所述的显示面板，其中，所述第一电极层包括不透明材料，所述第二电极层、所述第三电极层和所述第四电极层包括透明材料。
PCT/CN2020/103554 2019-08-14 2020-07-22 像素电路及其驱动方法以及显示面板 WO2021027514A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/271,776 US11238803B2 (en) 2019-08-14 2020-07-22 Pixel circuit and method for driving the same, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910752533.8 2019-08-14
CN201910752533.8A CN110428778B (zh) 2019-08-14 2019-08-14 像素电路及其驱动方法以及显示面板

Publications (1)

Publication Number Publication Date
WO2021027514A1 true WO2021027514A1 (zh) 2021-02-18

Family

ID=68416376

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/103554 WO2021027514A1 (zh) 2019-08-14 2020-07-22 像素电路及其驱动方法以及显示面板

Country Status (3)

Country Link
US (1) US11238803B2 (zh)
CN (1) CN110428778B (zh)
WO (1) WO2021027514A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110428778B (zh) 2019-08-14 2021-08-17 京东方科技集团股份有限公司 像素电路及其驱动方法以及显示面板
CN111668383B (zh) * 2020-06-22 2022-08-09 京东方科技集团股份有限公司 显示面板、显示装置
CN115831047A (zh) * 2020-11-27 2023-03-21 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示基板及显示装置
CN112863436B (zh) * 2021-01-11 2022-06-10 京东方科技集团股份有限公司 一种像素电路、驱动方法、电致发光显示面板及显示装置
CN112909053A (zh) * 2021-01-26 2021-06-04 京东方科技集团股份有限公司 显示装置、显示面板及其制造方法
CN113539170B (zh) * 2021-07-12 2022-12-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示基板、显示装置
CN117337629A (zh) * 2022-04-26 2024-01-02 京东方科技集团股份有限公司 显示基板及其制备方法和驱动方法、显示面板、显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917280A (en) * 1997-02-03 1999-06-29 The Trustees Of Princeton University Stacked organic light emitting devices
CN101127194A (zh) * 2007-09-26 2008-02-20 友达光电股份有限公司 主动式有机发光二极管显示器
CN105514287A (zh) * 2014-10-13 2016-04-20 乐金显示有限公司 有机发光二极管装置
CN106449659A (zh) * 2016-11-11 2017-02-22 京东方科技集团股份有限公司 阵列基板及其制造方法、显示器
CN107068057A (zh) * 2017-02-14 2017-08-18 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及显示面板
CN208225917U (zh) * 2018-05-28 2018-12-11 昆山国显光电有限公司 有机发光器件和显示装置
CN109564931A (zh) * 2017-04-12 2019-04-02 京东方科技集团股份有限公司 堆叠式有机发光装置、有机发光二极管显示装置和制造堆叠式有机发光装置的方法
CN110060637A (zh) * 2019-05-28 2019-07-26 京东方科技集团股份有限公司 像素驱动电路、驱动方法、显示面板及显示装置
CN110428778A (zh) * 2019-08-14 2019-11-08 京东方科技集团股份有限公司 像素电路及其驱动方法以及显示面板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100686334B1 (ko) * 2003-11-14 2007-02-22 삼성에스디아이 주식회사 표시장치 및 그의 구동방법
US7528810B2 (en) * 2004-05-25 2009-05-05 Victor Company Of Japan, Limited Display with multiple emission layers
KR101214205B1 (ko) 2005-12-02 2012-12-21 재단법인서울대학교산학협력재단 표시 장치 및 그 구동 방법
KR102113650B1 (ko) * 2013-12-27 2020-06-03 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN104269429B (zh) * 2014-09-19 2017-05-31 京东方科技集团股份有限公司 一种有机电致发光显示器件、其驱动方法及显示装置
KR102277411B1 (ko) * 2014-10-10 2021-07-16 삼성디스플레이 주식회사 유기전계발광 표시장치
CN104599641A (zh) * 2015-03-02 2015-05-06 京东方科技集团股份有限公司 Oled像素单元及其驱动方法、oled显示装置
CN107342047B (zh) 2017-01-03 2020-06-23 京东方科技集团股份有限公司 像素电路及其驱动方法、以及显示面板
US10783830B1 (en) * 2019-05-14 2020-09-22 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with short programming time

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917280A (en) * 1997-02-03 1999-06-29 The Trustees Of Princeton University Stacked organic light emitting devices
CN101127194A (zh) * 2007-09-26 2008-02-20 友达光电股份有限公司 主动式有机发光二极管显示器
CN105514287A (zh) * 2014-10-13 2016-04-20 乐金显示有限公司 有机发光二极管装置
CN106449659A (zh) * 2016-11-11 2017-02-22 京东方科技集团股份有限公司 阵列基板及其制造方法、显示器
US20190267436A1 (en) * 2016-11-11 2019-08-29 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof and display device
CN107068057A (zh) * 2017-02-14 2017-08-18 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及显示面板
CN109564931A (zh) * 2017-04-12 2019-04-02 京东方科技集团股份有限公司 堆叠式有机发光装置、有机发光二极管显示装置和制造堆叠式有机发光装置的方法
CN208225917U (zh) * 2018-05-28 2018-12-11 昆山国显光电有限公司 有机发光器件和显示装置
CN110060637A (zh) * 2019-05-28 2019-07-26 京东方科技集团股份有限公司 像素驱动电路、驱动方法、显示面板及显示装置
CN110428778A (zh) * 2019-08-14 2019-11-08 京东方科技集团股份有限公司 像素电路及其驱动方法以及显示面板

Also Published As

Publication number Publication date
CN110428778A (zh) 2019-11-08
US20210327357A1 (en) 2021-10-21
US11238803B2 (en) 2022-02-01
CN110428778B (zh) 2021-08-17

Similar Documents

Publication Publication Date Title
WO2021027514A1 (zh) 像素电路及其驱动方法以及显示面板
JP7495031B2 (ja) 画素回路、画素回路の駆動方法及び表示装置
CN109523956B (zh) 像素电路及其驱动方法、显示装置
WO2020186933A1 (zh) 像素电路、其驱动方法、电致发光显示面板及显示装置
KR20210093833A (ko) 주사 구동 회로 및 주사 구동 회로를 구비한 표시장치
WO2020146978A1 (zh) 像素电路、显示面板及像素电路的驱动方法
JP7159182B2 (ja) 画素回路及びその駆動方法、表示パネル
KR102475504B1 (ko) 투명표시패널 및 이를 포함하는 투명표시장치
WO2019205547A1 (en) Double-sided display panel and manufacturing method, driving circuit and driving method
WO2018219066A1 (zh) 像素电路、驱动方法、显示面板及显示装置
CN109728068B (zh) 一种阵列基板、其驱动方法及显示装置
CN109346009B (zh) 有机发光显示面板和显示装置
WO2016041306A1 (zh) 有机电致发光显示器件、其驱动方法及显示装置
US20230309341A1 (en) Display substrate and display device
CN111986621B (zh) Oled显示面板
US11276743B2 (en) Display apparatus
WO2020151414A1 (zh) 显示面板及其驱动方法、显示装置
CN113327543A (zh) 显示基板及其驱动方法、显示装置
KR102220553B1 (ko) 표시 패널 및 그것을 포함하는 표시 장치
KR20240004210A (ko) 디스플레이 패널 및 디스플레이 장치
US12027086B2 (en) Driving circuit and driving method of display panel, display panel, and display apparatus
JP2022534548A (ja) ピクセル補償回路、ディスプレイパネル、駆動方法、およびディスプレイ装置
CN111354315B (zh) 显示面板及显示装置、像素驱动方法
JP2021507274A (ja) 画素回路、表示パネル及び表示装置
CN106782271B (zh) 一种像素电路、显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20853349

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20853349

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20853349

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 08.02.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20853349

Country of ref document: EP

Kind code of ref document: A1