WO2021022461A1 - 一种倒装发光二极管 - Google Patents
一种倒装发光二极管 Download PDFInfo
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- WO2021022461A1 WO2021022461A1 PCT/CN2019/099322 CN2019099322W WO2021022461A1 WO 2021022461 A1 WO2021022461 A1 WO 2021022461A1 CN 2019099322 W CN2019099322 W CN 2019099322W WO 2021022461 A1 WO2021022461 A1 WO 2021022461A1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
Definitions
- the invention relates to the field of semiconductor technology, in particular to designing a patterned substrate structure for flip-chip light emitting diodes.
- Light-emitting diodes are semiconductor devices that convert electrical energy into light energy and become LED (Light Emitting Diode) chips. According to different packaging forms, light-emitting diodes can be simply divided into front-mounted light-emitting diodes, flip-chip light-emitting diodes and vertical light-emitting diodes. Among them, flip-chip light-emitting diodes have the advantages of no wire bonding process, high current drive, and high reliability. Therefore, flip-chip light-emitting diodes must have very good applications in general lighting, backlight, flash, display, and car lights. .
- patterned substrates are widely used in the production of flip-chip light-emitting diodes.
- the substrate pattern will facilitate epitaxial growth and blue light emission , To reduce light reflection at the interface of GaN and sapphire.
- the packaging process of flip-chip light-emitting diodes uses solder paste for packaging and bonding.
- an insulating protective layer Passivation Layer, referred to as: PV layer
- the insulating protective layer is located between the core particles and the core particles.
- an isolation layer etching process is used in the chip process to remove part of the epitaxial light-emitting layer, and at least expose the edge of the substrate, and then on the top of the epitaxial light-emitting layer, sidewalls and exposed
- the substrate is covered with an insulating protective layer.
- the exposed substrate surface has pattern protrusions, such as patterned conical protrusions, the areas between the individual patterns and the top of the conical PSS pattern become stress concentration areas.
- the bumps when covering the insulating protective layer, the bumps will cause the insulating protective layer to be unevenly covered or the insulating protective layer to crack, causing the solder paste to drill into the insulating protective layer from the gap (refer to the dark line in the wire frame area in the picture), causing a short circuit Risk, in the long-term aging process, there is a risk that the solder paste passes through the gap and is connected to u-GaN (the undoped gallium nitride at the bottom layer in the epitaxial layer) to cause a short circuit.
- u-GaN the undoped gallium nitride at the bottom layer in the epitaxial layer
- the surface of the substrate has patterned protrusions, which are easy to absorb metal debris, dirt, etc. in the subsequent chip manufacturing process or package die-attach process, resulting in die-bonding solder paste remaining on the chip edge and causing abnormalities such as IR (high leakage current).
- the PSS pattern at the edge of the light-emitting diode is reduced or secondary patterned to reduce the passivation film layer at the edge of the light-emitting diode
- the stress concentration phenomenon, from the top view, the isolation groove is located at the edge of each LED core particle.
- the present invention provides a flip-chip light-emitting diode, which includes a substrate with a series of protrusions on the surface and an epitaxial light-emitting layer on the substrate.
- the protrusions are the surface pattern of the substrate. It is made by pattern imprinting, wet etching or dry etching.
- the material of the substrate includes sapphire, silicon, silicon carbide or gallium arsenide.
- the convex shapes on the substrate include cone, triangular pyramid, hexagonal cone, cone-like, and Triangular cone or similar hexagonal cone.
- the epitaxial light-emitting layer can be made of gallium nitride-based materials, including a first semiconductor layer, a second semiconductor layer and an active layer located between the two covering the substrate, a first electrode connected to the first semiconductor layer, and The second semiconductor layer is connected to the second electrode, and a part of the substrate is exposed from the first semiconductor layer.
- the first semiconductor layer may include an N-side layer and a buffer layer.
- the buffer layer is used to reduce the crystal lattice between the substrate and the N-side layer. Mismatch, thereby promoting the crystal growth of the N-side layer.
- the buffer layer basically has no direct influence on the function of the semiconductor.
- the second semiconductor layer includes the P-side layer. In some cases, the order can be reversed.
- the active layer includes multiple quantum wells.
- the exposed area of the substrate at least partly serves to reserve space for the insulating protective layer covering the sidewall of the light-emitting diode.
- the protrusions in the exposed bottom area are at least partially covered by the insulating protective layer.
- the insulating protective layer on the protrusions has high and low fluctuations.
- the peak height of the fluctuations is 0 to 0.5 microns, of which 0 micron is the ideal state, that is, the insulating protective layer on the protrusions is basically free. ups and downs.
- a certain height of bumps, such as 0.5 micron bumps, can improve the light extraction efficiency of the side surface of the LED.
- the height of the protrusions in the area covered by the insulating protective layer of the substrate is at least partly lower than the height of the protrusions in the area covered by the first semiconductor layer of the substrate.
- the shape of the light-emitting area is similar or the same but the same proportion is reduced.
- the equal proportion here means that the proportion is close, and it does not limit the proportion to be completely consistent.
- the edge of the light-emitting diode substrate is at least partially wrapped by the insulating protective layer, or the entire periphery is covered by the insulating protective layer.
- the protrusion height of the area covered by the first semiconductor layer of the substrate is 1 to 2 microns, or 2 to 2.5 microns.
- maintaining a certain height of the substrate protrusion is beneficial to reduce epitaxial mismatch and reduce epitaxial dislocation defects.
- a certain height of the substrate protrusion covers the semiconductor layer, and the growth direction of linear lattice defects also deviates from the semiconductor layer.
- a certain height of the substrate protrusion realizes that the semiconductor layer has a region in which the lattice defect density is reduced. This region containing reduced (i.e., fewer) defects can be used to form the active layer region of the semiconductor device, resulting in improved light emitting diode performance characteristics.
- the ratio of the height of the protrusion of the area covered by the first semiconductor layer of the substrate to the height of the peak height of the insulating protection layer on the protrusion of the exposed area of the substrate is greater than 3.
- the protrusion height of the area covered by the insulating protective layer of the substrate is at least partly 0 to 1 ⁇ m, or 1 to 2.5 ⁇ m.
- the protrusions in the exposed area of the substrate can be removed or partially removed by chemical etching or ICP etching (ion beam assisted radical etching), which includes the area to be covered by the insulating protective layer, and the removal also includes the fully exposed protrusions Area to reduce the height of the protrusions in the exposed area of the substrate, and then make a covering insulating protective layer. Since the patterned substrate itself is a roughened surface, the higher the surface roughness of the substrate covered by the insulating protective layer, the easier it is to adsorb dirt. Lowering the pattern height is beneficial to reduce the adsorption and eliminate the risk of chip short circuit.
- the convex pattern of the area covered by the insulating protective layer is reduced and the etching process is optimized. It is made into a partial arc-shaped or platform-shaped pattern.
- the insulating protective layer covers the protrusions, it will facilitate the smooth transition of the top of the protrusions and reduce the phenomenon of stress concentration on the top of the pattern, that is, the top of the protrusions in the area covered by the insulating protective layer It is arc-shaped or platform-shaped.
- the gap between the PSS pattern protrusions and the pattern protrusions will have greater stress after covering the insulating protective layer due to surface fluctuations.
- the protrusion density of the area covered by the insulating protective layer is designed to be the substrate
- the first semiconductor layer covers 1/10 to 1/2 of the protrusion density of the region.
- the insulating protective layer covering at least part of the substrate protrusions is made of a flexible insulating material, and the ductility of the flexible insulating material is used to eliminate or reduce film layer stress and reduce the fluctuation of the insulating protective layer. Cover it with a conventional insulating protective layer.
- the material of the insulating protection layer can be relatively rigid silicon dioxide, silicon nitride, titanium oxide, tantalum oxide or niobium oxide, or it can be a Bragg reflector DBR, or a flexible insulating material, such as Insulating plastic material.
- the thickness of the insulating protection layer at least partially covering the protrusions of the substrate is 0.5 to 2 microns, or 2 to 5 microns.
- the design of the insulating protection layer in Mini products requires comprehensive consideration of multiple factors, for example, With the characteristics of small size and concentrated current, the design hopes to reduce the thickness of the insulating protective layer as much as possible to improve the heat dissipation capacity and reliability of the product.
- the present invention takes the insulating protective layer as an example with a thickness of 2 microns to ensure that the insulating protective layer will not be short-circuited by the eutectic electrode and the P-type region due to cracking (except for steep cracks, including too thin, easy to break when grabbing the thimble, etc.) , Caused by core particle failure.
- the conventional Mini product has a smaller chip size than a conventional size product, which leads to an increase in the difficulty of the splitting process.
- the epitaxial light-emitting layer between the core particle and the core particle is removed to expose the substrate.
- the ratio of the protrusion height of at least part of the substrate covered by the insulating protective layer to the thickness of the insulating protective layer covering the substrate protrusion is greater than 0.5. Under the condition that the thickness of the insulating protective layer is limited, the The technical solution can keep the protrusion height as much as possible.
- the chip size of the flip-chip light emitting diode is not greater than 250 micrometers*250 micrometers.
- the flip-chip light emitting diode is a micro light emitting diode (Micro LED), for example, having a length from 2 to 100 microns, or 100 to 500 microns.
- the flip-chip light emitting diode has a width from 2 to 100 microns, or 100 to 500 microns.
- Flip-chip LEDs have a height from 2 to 100 microns, or 100 to 200 microns.
- the peak height of the undulations of the insulating protection layer is greater than 0 to less than or equal to 0.5 microns.
- the area covered by the insulating protective layer of the substrate is at least partially located at the edge of the light emitting diode, or the area covered by the insulating protective layer of the substrate is located on the entire periphery of the light emitting diode.
- the protrusion of the area covered by the first semiconductor layer of the substrate includes a first part and a second part.
- the second part can be stacked on the first part, wherein the second part is a removable part.
- the second part is easily separated from the first part.
- the protrusions in the area covered by the insulating protective layer of the substrate only include the first part.
- the convex surface of the first part is a smooth surface, which facilitates smooth coverage of the insulating protective layer and reduces the problem of cracking caused by high and low fluctuations.
- the beneficial effects of the present invention include the complete structure of the insulating protection layer at the edge of the chip, which can further improve the long-term reliability of the chip, the manufacturing process is simple, the effect on the brightness is small, and the technical application range is wide.
- FIG. 1 is a schematic diagram of a cross-sectional structure of a flip-chip light emitting diode in the background art
- FIG. 2 is a photograph of an insulating protective layer covering a flip-chip light-emitting diode substrate in the background art
- FIG. 3 is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode of Embodiment 1;
- FIG. 5 to 11 are schematic diagrams of cross-sectional structures of flip-chip light emitting diodes according to Embodiment 2 to Embodiment 6;
- Figures 12 and 13 are schematic diagrams of protrusion structures in two embodiments of Embodiment 6;
- FIG. 14 and 15 are schematic diagrams of the cross-sectional structure of the flip-chip light emitting diode according to the seventh embodiment.
- 100 substrate, 110, 111, 112: bumps, 110': first part, 110": second part, 110"': third part, 200: epitaxial light-emitting layer, 211: N-side layer , 212: buffer layer, 221: P side layer, 230: active layer, 310: first electrode, 320: second electrode, 400: insulating protective layer, 500: current spreading layer.
- FIG 3 are respectively schematic cross-sectional views schematically showing light emitting diodes according to example embodiments of the inventive concept.
- the light emitting diode is a flip-chip light-emitting diode, especially a small-size or micro-size flip-chip light-emitting diode, for example, the size is not greater than 250 microns * 250 Micron Mini LEDs have lengths and widths of 100 microns to 500 microns, and heights of 100 microns to 200 microns.
- they can include a substrate 100 with a series of protrusions (110) on the surface and a substrate 100 on the substrate.
- Epitaxial light emitting layer 200 Epitaxial light emitting layer 200.
- the flip-chip light-emitting diode is a micro-LED, for example, has a length from 2 to 100 microns, a width from 2 to 100 microns, and a height from 2 to 100 microns.
- Nitride compound semiconductors which are the constituent materials of blue light-emitting diodes and green light-emitting diodes, are prone to cause a lot of displacement due to lattice mismatch, because compared with lattice-matched compound semiconductors (such as GaAs compound semiconductors), there is no suitable A substrate and a compound semiconductor, which can form a grown crystal layer having the same lattice constant as the substrate. As a result, the active layer (light-emitting layer) is easily affected by defects due to displacement, and becomes electrically and mechanically fragile.
- a patterned wafer is used as the growth substrate 100 to reduce the influence of epitaxial growth caused by the above-mentioned substrate mismatch.
- a series of bumps 110 patterns on the surface of the substrate 100 can be embossed, dry etched or wet. Method etching production.
- the shape of the protrusion 110 on the substrate 100 includes a cone, a triangular pyramid, a hexagonal pyramid, a similar cone, a triangular pyramid or a hexagonal pyramid.
- the light-emitting efficiency of the overall light-emitting diode can be improved by adjusting the shape or size of the substrate pattern.
- the epitaxial light-emitting layer 200 includes a first semiconductor layer (N-type), a second semiconductor layer (P-type) covering a substrate, and an active layer 230 between them.
- the electrodes of the light emitting diode include a first electrode 310 and a second electrode 320, which are in ohmic contact with the N-side layer and the P-side layer respectively.
- the current flows from the second electrode 320 through the epitaxial light-emitting layer 200 to the first electrode 310, and is distributed laterally in the epitaxial structure of the epitaxial light-emitting layer 200, making it The photoelectric effect occurs to produce photons.
- the active layer 230 may have different wavelengths of excitation light according to different materials and process conditions.
- the above-mentioned epitaxial light-emitting layer 200 may be adhered to the heat-dissipating substrate by using metal organic compound chemical vapor deposition (MOCVD) on the growth substrate 100 or by flip-chip technology.
- MOCVD metal organic compound chemical vapor deposition
- the above-mentioned light emitting diode is a blue light emitting diode
- the material of the epitaxial light emitting layer 200 is a GaN-based compound.
- the first electrode 310 and/or the second electrode 320 can generally be directly formed on the epitaxial light-emitting layer 200 to connect to an external power source and stimulate the quantum well layer (active layer) to emit light.
- the substrate material provided by the manufacturing process of this embodiment can be selected from sapphire, silicon, silicon carbide or gallium arsenide.
- This embodiment preferably takes a gallium nitride-based device as an example.
- a sapphire substrate 100 is used.
- the first semiconductor layer may include an N-side layer 211 and a buffer layer 212.
- the buffer layer 212 is located between the N-side layer 211 and the substrate 100.
- the layer 212 is in contact with the substrate 100, and the buffer layer 212 is used to reduce the lattice mismatch between the substrate 100 and the N-side layer 211, thereby promoting the crystal growth of the N-side layer 211.
- the buffer layer 212 basically has no direct influence on the function of the semiconductor.
- the N-side layer 211 will generate free electrons, and the P-side layer 221 will have a certain concentration of holes.
- the electrons and holes are combined in the active layer multi-quantum well under the action of an electric field, causing the energy level to be lowered and releasing energy in the form of photons And emit light to produce a light-emitting state on the entire surface.
- the active layer 230 may be a multiple quantum well (MQW) used to restrict the movement of electrons and holes. By increasing the collision probability of electrons and holes, the electron-hole binding rate and luminous efficiency are increased.
- MQW multiple quantum well
- the flip-chip light emitting diode of the type emitting light from the substrate 100 side by partially removing the N-side layer 211, an N-side groove or terrace is formed, exposing the opening of the N-side layer 211 for making the first electrode 310.
- the first electrode 310 N-side electrode
- the key point is to increase the area of the light-emitting layer. In a light emitting diode having a certain external size, the area of the active layer can be increased by reducing the area of the first electrode 310 (N-side electrode).
- the pad portion in view of the requirements of the step of assembling the flip-chip light-emitting diode (assembled on the circuit board or package base), it is necessary for the pad portion to have a size guaranteed in the wire bonding step and the die bonding step (without reducing the mechanical strength) Or reduce installation performance). This requirement is contrary to the requirement of reducing the area of the first electrode 310 (N-side electrode).
- the first electrode 310 (N-side electrode) is generally reduced in size as much as possible, while ensuring the smallest pad area that has no effect on mounting, and is set to minimize the interval between the first electrode 310 and the second electrode 320 (N-side electrode and P-side electrode).
- a high electric field such as static electricity is applied to the light emitting diode
- the high electric field is directly applied to the space between the compound semiconductor layer and the first/second electrode. Therefore, the withstand voltage characteristic of the insulating protective layer 400 between the electrodes is an important factor that determines the electrostatic breakdown strength of the light emitting diode.
- the light from the active layer 230 is directly emitted to the outside through the substrate 100 or reflected by the second electrode 320 and then emitted to the outside through the second electrode 320.
- a material for forming the second electrode 320 for example, silver (Ag) having high reflectance is used.
- the second electrode 320 is usually covered with an insulating protective layer 400 by a CVD method such as plasma CVD or a PVD method such as vacuum deposition or sputtering.
- the insulating protection layer 400 is respectively disposed on the first electrode 310 and the second electrode 320 and the openings above them, and a current spreading layer is disposed between the second electrode 320, the insulating protection layer 400 and the second semiconductor layer (P side layer 221) 500, such as ITO (Indium Tin Oxide), which is a frequently used material, functions to guide current from the second electrode 320 to be more uniformly injected into the second semiconductor layer.
- the current spreading layer 500 is located under the second electrode 320 and above the second semiconductor layer.
- the insulating protection layer 400 may be an electrically insulating material.
- the insulating protection layer 400 may be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof.
- the combination may be a Bragg reflector (DBR), for example.
- the insulating protection layer 400 has different functions according to the designed position. For example, covering the sidewall of the epitaxial light-emitting layer is used to prevent leakage of conductive material and electrically connect the first semiconductor layer and the second semiconductor layer, and reduce the short-circuit abnormality of the light-emitting diode.
- the thickness of the insulating protective layer 400 is 2-5 microns, and the insulating protection layer may also be a Bragg reflector DBR.
- pinholes or cracks are prone to occur in insulating films formed based on CVD or PVD methods, and when there are steep portions due to electrode structures or device structures (such as substrate pattern protrusions), it may be difficult to use insulation
- the protective layer 400 firmly covers the steep part.
- pinholes or cracks may occur in the insulating protective layer 400.
- the steep part may become a discontinuous growth point of the insulating protective layer 400.
- the flip-chip light-emitting diode chip structure reserves a part of the uncovered epitaxial light-emitting layer 200 area on the substrate 100, partially wraps the insulating protective layer 400 around the epitaxial light-emitting layer 200, and the insulating protective layer 400 also It is partially covered on the patterned substrate 100.
- the area covered by the insulating protection layer 400 of the substrate 100 is at least partly located at the edge of the light emitting diode, or the area covered by the insulating protection layer 400 is located on the entire periphery of the light emitting diode.
- the sidewall protection effect significantly affects the performance of the device. This problem is due to the larger size of the conventional-sized light-emitting diodes, and the edge current of the substrate 100 is released. It can be ignored. On the contrary, due to the increased edge current density of the epitaxial light-emitting layer 200 for small-sized chips, the problem of preventing leakage of the edge insulating protective layer 400 should be paid attention to.
- the patterned growth substrate 100 is exposed from the epitaxial light-emitting layer 200 by shrinking
- the protrusion 110 reduces the steepness of the surface of the substrate 100 and reduces the influence of the pattern of the substrate 100 on the insulating protection layer 400, especially the influence on the insulating protection layer 400 located at the edge of the epitaxial light-emitting layer.
- the substrate 100 is exposed from the epitaxial light-emitting layer 200 (specifically, the first semiconductor layer), the protrusions in the exposed area of the substrate 100 are at least partially covered by the insulating protective layer 400, and the insulating protective layer 400 on the protrusions in the exposed area of the substrate 100 has
- the height of the bump 111 is reduced after being reduced.
- the height h1 of the bump 111 is 0 to 1 micron.
- the undulations of the insulating protective layer 400 on it are alleviated.
- the peak height of the insulating protective layer 400 in this area (marked as h in the figure) It is 0 to 0.5 microns.
- Methods for reducing the height of the protrusions on the surface of the substrate 100 include wet etching or dry etching.
- the height h2 of the substrate protrusion 112 covered by the epitaxial light-emitting layer 200 is 2 to 2.5 microns.
- the ratio of the height h2 of the protrusion 112 in the area covered by the first semiconductor layer of the substrate 100 to the height h of the peak height h of the insulating protective layer 400 on the protrusion 111 in the exposed area of the substrate is greater than 3, and the pattern change is not
- the quality of the epitaxial growth of the substrate is affected, and the insulation protection layer 400 can be smoothed.
- the height of the protrusion 111 in the area covered by the insulating protective layer 400 of the substrate 100 is at least partially 1/10 to 1/2 of the height h2 of the protrusion 112 in the area covered by the first semiconductor layer of the substrate 100.
- the height of the bump 111 has a certain relationship with the thickness of the insulating protective layer 400.
- the bump 111 is then covered with an insulating protective layer 400.
- the insulating protective layer 400 smoothly transitions between the two bumps 111 to eliminate pinholes or cracks. . This embodiment focuses on the design of the substrate 100 and the insulating protection layer 400, and the other components and processes of the chip are briefly described.
- the insulating protective layer 400 is continuous and complete, preferably covering the surface of the substrate 100 and the epitaxial light-emitting layer 200, Finally, the light-emitting diode wafers that have completed the chip process are cut into core pellets and further subjected to resin molding and packaging to complete various light-emitting diodes such as shell-type and surface-mounting types.
- the second to seventh embodiments provided by the present invention are similar to the technical problems to be solved in the first embodiment. They are all for preventing the insulating protective layer 400 from cracking due to the steep shape of the substrate 100.
- the main design difference is the change of the protrusion of the substrate 100, because the overall structure such as the epitaxial light-emitting layer 200 and the first electrode 310, the second electrode 320, the insulating protective layer 400, the transparent conductive layer 500, etc. are substantially the same. The description is not repeated in the embodiment.
- the process method of the embodiment includes the processing flow of the substrate 100 In the production of the substrate pattern, the substrate pattern of the peripheral part of the chip is not produced, and only the corresponding pattern protrusion 112 under the epitaxial light-emitting layer 200 in the chip process is produced.
- the substrate pattern is made by mask etching.
- the requirements for the precision of the equipment for making the isolation groove pattern are higher, especially at this stage, the flat edge of the wafer is usually aligned, and the substrate 100 area without protrusions is reserved. It is relatively difficult to completely match the area where the epitaxial light-emitting layer 200 is removed from the edge of the subsequent chip process.
- a method that can be adopted is to appropriately expand the area of the substrate without pattern protrusions to reduce the difficulty of alignment.
- a full-patterned substrate 100 can also be used.
- the epitaxial chip process is first fabricated on the substrate 100. A part of the epitaxial light-emitting layer 200 is removed in the isolation trench fabrication process to expose the peripheral substrate, and then a mask etching technique is used.
- the pattern of the peripheral substrate is removed, and then an insulating protective layer 400 is covered on the epitaxial light-emitting layer 200 and the flat surface of the peripheral substrate.
- the undulation of the insulating protective layer 400 is significantly reduced.
- the process needs to precisely control the etching amount to take into account the pattern removal And device protection.
- the light-emitting diode according to the third embodiment of the present invention uses a process of reducing the size of the protrusions and expanding the distribution density of the protrusions on the substrate.
- the manufacturing process of this embodiment is The operability is relatively high.
- One of the methods for making the substrate is to change the mask pattern and adjust the etching time when making the pattern substrate to produce a convex pattern of a predetermined size and a suitable density. The mature technology of the bottom industry will not be repeated here.
- the height of the protrusions 111 in the area covered by the first semiconductor layer of the substrate 100 is 1 to 2 microns.
- the height of the protrusions of the entire substrate 100 is 1 to 2 microns, and The substrate 100 is covered by the insulating protective layer 400.
- the insulating protective layer 400 has high and low undulations.
- the peak height h of the undulations is 0 to 0.5 microns.
- the distance between the protrusions 112 in the area covered by the epitaxial light-emitting layer 400 and the The distance between the protrusions 111 in the area covered by the insulating protection layer is not less than 2 microns.
- the insulating protective layer 400 covering the protrusions has a longer distance transition, reducing the slope of the insulating protective layer 400, and making the insulating protective layer 400 cover the substrate 100 more smoothly. Thereby reducing steepness and stress concentration.
- the advantage of this embodiment is that it can have a certain height of the substrate pattern height, which can take into account the quality of epitaxial growth and reduce the leakage phenomenon.
- the substrate pattern of the necessary height can reduce the defects of the epitaxial light-emitting layer 400 growing on the substrate 100, which is beneficial to Improve the internal quantum effect.
- the protrusions 112 in the area covered by the first semiconductor layer of the substrate 100 are densely distributed, and the protrusions in the area covered by the first semiconductor layer of the substrate 100 are densely distributed.
- the pitch of 112 is not greater than 3 microns, and the bumps 112 in the area covered by the insulating protective layer 400 are sparsely distributed, and the pitches of the bumps 111 in the area covered by the insulating protective layer 400 are not less than 2 microns.
- the insulating protection layer 400 is taken as an example.
- the distance between the protrusions 112 in the area covered by the first semiconductor layer of the substrate 100 is 2 microns, and the distance between the protrusions 112 in the area covered by the insulating protection layer 400 is 8 microns.
- the density of protrusions 112 in the area covered by the insulating protective layer 400 of the substrate 100 is 1/10 to 1/2 of the density of the protrusions 112 in the area covered by the first semiconductor layer of the substrate 100, where the density refers to the protrusions per unit area. The number of distributions.
- the main advantage of this embodiment is to adapt to different epitaxial growth processes.
- a growth substrate 100 with a conventional protrusion height can be used, for example, the protrusion height is 2 to 2.5 microns, while taking into account the quality of epitaxial growth, the insulating protective layer 400 covers the substrate On the bumps 111, due to the large distance between the bumps 111, the insulating protection layer 400 can still ensure the integrity and provide good insulation protection.
- a growth substrate 100 with a low protrusion height may be used for crystal growth and further chip production process, for example, the protrusion height is 1 to 2 microns, and then the removed part is insulated and protected when the chip isolation groove is made
- the layer 400 covers the bumps 111 in the area and reduces the distribution density of the bumps 111 in the area.
- the removal time of the pattern on the chip side will be less than the bump elimination time in the first embodiment.
- the height of the protrusion 112 in the area covered by the first semiconductor layer of the substrate 100 may be 2 to 2.5 microns, and the height of the protrusion 111 in the area covered by the insulating protection layer 400 may be 1 to 2 microns, and the height of the protrusion 112 may be 1 to 2 ⁇ m.
- the protrusion 112 of the coverage area is designed to be sparse and short.
- the light-emitting diode according to the fifth embodiment adopts a method of changing the shape of the top of the substrate protrusion 110, and uses a smooth or round surface to form a buffer area, especially for the insulated
- the convex design of the substrate covered by the protective layer 400 is, for example, a hemispherical or platform-shaped convex shape.
- the hemispherical protrusion 110 is taken as an example.
- the insulating protection layer covers the surface of the hemispherical protrusion 110.
- the height of the protrusion 110 is 2 to 2.5 microns, and at least part of the substrate is covered by the insulating protection layer 400.
- the ratio of the thickness of the insulating protective layer 400 covering the protrusions of the substrate is greater than 0.5, while taking into account the quality of epitaxial growth, the insulating protective layer 400 covers the substrate protrusions 110. Since the surface of the protrusions 110 is smooth, the insulating protective layer 400 can still ensure integrity It provides good insulation protection.
- the substrate protrusion 110 includes a first portion 110' and a first portion 110' Two parts 110", the first part 110' is closer to the substrate 100, the second part 110" is located on the first part 110', the second part 110" is a sacrificial part, the second part 110" can be moved more easily than the first part 110'
- the semiconductor epitaxial light-emitting layer 200 is first fabricated on the substrate 100.
- the chip structure is fabricated as in the process flow of embodiment 1, and the second part 110" located in the isolation trench is removed after the substrate 100 is exposed.
- the shape of the first part 110' can be hemisphere, platform, cone, triangular cone, hexagonal cone, cone-like, triangular cone or hexagonal cone, and the convex substrate formed by the combination of the first part 110' and the second part 110"
- the starting shape can be a hemisphere, a platform, a cone, a triangular cone, a hexagonal cone, a similar cone, a triangular pyramid or a hexagonal cone.
- the second part 110" is wrapped around the outside of the first part 110', and the figure of the first part 110' is retained by removing the second part 110" located in the isolation groove.
- the first part 110' can be Same as the substrate 100, for example, sapphire is used, and the second part 110" is made of silicon dioxide that is easy to be etched and removed or aluminum nitride.
- Aluminum nitride is more difficult to remove than silicon dioxide, but it is suitable as a semiconductor
- the long crystal plane of gallium nitride has smaller lattice matching problems.
- the substrate protrusion can include three parts, the first part 110' is sapphire, the second part 110" is silicon dioxide, the third part 110"' is aluminum nitride, the second part 110" is a sacrificial layer, the third part 110"' is a growth layer, and the second part 110 "Located between the first part 110' and the third part 110"'.
- the third part 110"' can be roughly expanded to be more suitable as a crystal growth interface than the second part 110", and the second part 110" is easier to remove than the first part 110' and/or the third part 110"'.
- the chip is made, it is easier to remove the second part 110” by selective removal, and at the same time remove the third part 110” on the second part 110”, in the exposed area of the substrate
- the first part 110 ′ is reserved for covering the insulating protective layer 400.
- the isolation groove is filled with a high-temperature resistant flexible insulating layer.
- the material of the insulating protective layer is modified. Specifically, the material of the flexible insulating protective layer 400 is used at least partially, and the insulating glue material is used to cover the substrate protrusion 110. The ductility of the glue material can overcome the protrusion pattern caused Stress concentration problem.
- the insulating protection layer 400 of the light emitting diode includes a first insulating layer 410 and a second insulating layer 420.
- the insulating layer 410 is made of silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or any combination thereof.
- the second insulating layer 420 is located on the bump 110.
- the material used is epoxy resin or photoresist.
- an insulating material with good thermosetting property is used to avoid failure of the insulating protection layer during subsequent chip or packaging processes.
- the first insulating layer 410 mainly covers the main body of the light-emitting diode on.
- the first insulating layer 410 is located above the second insulating layer 420 and is connected to the second insulating layer 420. It is only necessary to fill the isolation grooves with a flexible insulating material after removing the epitaxial light-emitting layer 200 and exposing the substrate. , The production process is relatively simple.
- Example 3 and Example 4 are combined with the first insulating layer 410/second insulating layer 420 (flexible) of Example 7 to further reduce the protrusion 110 in the exposed area of the substrate.
- the second insulating layer 420 is filled simultaneously to reduce the stress of the flexible insulating layer between the bumps 110.
- embodiment 5 and embodiment 7 are combined, in order to further reduce the phenomenon of stress concentration on the top of the pattern, the pattern of the substrate is reduced (or only the pattern of the exposed area of the substrate is reduced) At the same time, by optimizing the etching process, a partial arc-shaped protrusion 110 pattern is fabricated, and then the second insulating layer 420 is filled.
- Example 7 Several implementations are listed in Example 7, which can also be obviously combined with the features of Example 6 or multiple examples to form a new technical solution.
- the technical effects of each feature are similar, for example, the use of sacrificial layer technology to make better For the light emitting diode of epitaxial quality, in Embodiment 7, the insulating protective layer 400 between the exposed area of the substrate 100 and the epitaxial light emitting layer 200 has a complete structure, which can further improve the long-term reliability of the chip.
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Abstract
一种倒装发光二极管,包括图形化衬底(100)和位于衬底上的外延发光层(200),衬底部分区域从外延发光层露出,衬底露出区域的凸起(111)至少部分被绝缘保护层覆盖,衬底露出区域的凸起上绝缘保护层具有高低起伏,起伏的顶峰高度(h)为0至0.5微米,通过降低靠近外延发光层的绝缘保护层起伏波动,从而避免绝缘保护层因应力变化导致的绝缘保护层破裂,绝缘保护层结构完整,可进一步提升芯片的可靠性。
Description
本发明涉及半导体技术领域,特别是设计一种倒装发光二极管的图形化衬底结构。
发光二极管为把电能转换成光能的半导体器件,又成为LED(Light Emitting Diode)芯片,发光二极管根据封装形式的不同,又可以简单分为正装发光二极管、倒装发光二极管和垂直发光二极管。其中倒装发光二极管具有不需要焊线工艺、可以大电流驱动,可靠性较高等优势,因此倒装发光二极管在普通照明,背光、闪光灯、显屏以及车灯等领域都得有非常好的应用。
为了提高发光二极管出光效率,在倒装发光二极管制作中广泛采用了图形化衬底,以采用蓝宝石衬底的氮化镓基蓝光发光二极管为例,衬底图形将有利于外延生长和蓝光的出光,减少光在GaN和蓝宝石界面的反射。
参考图1,倒装发光二极管的封装工艺采用锡膏进行封装键合,为防止锡膏泄露造成的电流,会在半导体层外侧覆盖绝缘保护层(Passivation Layer,简称:PV层)作为隔离层,在晶片未劈裂成单独芯粒前,绝缘保护层位于芯粒与芯粒之间。为了绝缘保护层将半导体的侧壁完整包覆,在芯片工艺中会采用隔离层蚀刻工艺,移除部分外延发光层、至少露出边缘的衬底,再在外延发光层顶部、侧壁以及露出的衬底上覆盖绝缘保护层。一方面,由于露出的衬底表面具有图形凸起,例如图形化圆锥形凸起,其单个图型与图型之间以及圆锥形PSS图型顶端,均成为应力集中区域。
参考图2在覆盖绝缘保护层时,凸起会造成绝缘保护层覆盖不平整或者绝缘保护层破裂,导致锡膏从缝隙(参考图中线框区域的深色线)钻入绝缘保护层,造成短路风险,在长期老化过程中,有锡膏通过其中的缝隙与u-GaN(外延层中位于底层的未掺杂氮化镓)连接导致短路的风险。常规尺寸芯片相比小尺寸或者微尺寸芯片,芯片体积较大,这种现象随着芯片尺寸的不断缩小,会变得越 来越严重,尤其是Mini LED或Micro LED;另一方面,由于露出的衬底表面具有图形凸起,容易在后续芯片制程或封装固晶过程,吸附金属碎屑、脏污等,导致固晶锡膏残留在芯片边缘导致IR(漏电电流高)等异常。
发明概述
问题的解决方案
为解决上述问题,在倒装发光二极管制作工艺中,为防止晶圆上芯粒与芯粒之间的隔离槽处图形化衬底(PSS衬底)上绝缘保护层的应力集中区域开裂,本发明提供了多种解决方案。
本发明的晶圆在芯片工艺中制作完芯粒与芯粒之间的隔离槽后,对发光二极管边缘的PSS图形进行缩小化或二次图形化处理,减小发光二极管边缘的钝化膜层应力集中现象,从俯视来看,隔离槽位于每个发光二极管芯粒的边缘。
具体来说,本发明提供了一种倒装发光二极管,包括表面具有一系列凸起的衬底和位于衬底上的外延发光层,凸起为衬底的表面图形,在衬底制程中可以通过图形压印、湿法蚀刻或者干法蚀刻制作,衬底的材料包括蓝宝石、硅、碳化硅或者砷化镓,衬底上凸起的形状包括圆锥、三角锥、六角锥、类圆锥、类三角锥或者类六角锥。
外延发光层可以采用氮化镓基材料,包括覆盖在衬底上的第一半导体层、第二半导体层和位于两者之间的有源层,与第一半导体层连接有第一电极,与第二半导体层连接有第二电极,衬底部分区域从第一半导体层露出,第一半导体层可以包括N侧层和缓冲层,缓冲层用于减轻衬底和N侧层之间的晶格失配,从而促进N侧层的晶体生长。缓冲层对半导体的功能基本上没有直接影响。第二半导体层包括P侧层,部分情况下也可以对换顺序,有源层包括多量子阱,衬底露出区域至少部分作用是为制作覆盖发光二极管侧壁的绝缘保护层预留空间,衬底露出区域的凸起至少部分被绝缘保护层覆盖,凸起上绝缘保护层具有高低起伏,起伏峰值高度为0至0.5微米,其中0微米为理想状态,即实现凸起上绝缘保护层基本无起伏。一定高度的凸起,例如0.5微米的凸起,可提高发光二极管的侧 面取光效率。
根据本发明,优选的,衬底被绝缘保护层覆盖区域的凸起至少部分高度低于衬底被第一半导体层覆盖区域的凸起高度,例如发光二极管衬底边缘或整个周边露出区域采用与发光区域形状相近或一致但等比例缩小的图形,这里的等比例是指比例接近,并非限定比例完全一致。发光二极管衬底边缘至少部分被绝缘保护层包裹,或整个周边被绝缘保护层覆盖。
根据本发明,优选的,衬底被第一半导体层覆盖区域的凸起高度1至2微米,或者为2至2.5微米。例如采用蓝宝石衬底,衬底凸起保持一定高度有利于减小外延失配,减少外延位错缺陷,一定高度衬底凸起之上覆盖半导体层,线性晶格缺陷的生长方向也偏离半导体层的主表面的法线方向,一定高度衬底凸起实现半导体层具有其中晶格缺陷密度降低的区域。包含减少(即,更少)缺陷的该区域可用于形成半导体器件的有源层区,从而导致改善的发光二极管性能特性。
衬底被第一半导体层覆盖区域的凸起高度与衬底露出区域的凸起上绝缘保护层起伏的顶峰高度的比值大于3。
根据本发明,优选的,衬底被绝缘保护层覆盖区域的凸起高度至少部分为0至1微米,或者为1至2.5微米。可以对衬底露出区域的凸起采用化学蚀刻或者ICP蚀刻(离子束辅助自由基刻蚀)移除或者部分移除,即包括将被绝缘保护层覆盖区域,移除也包括凸起完全露出的区域,以降低衬底露出区域的凸起高度,再制作覆盖绝缘保护层。由于图形化衬底本身是粗化表面,被绝缘保护层覆盖的衬底表面粗糙度越高越容易吸附脏污,降低图形高度有利于减少吸附、消除芯片短路风险。
根据本发明,优选的,为了进一步减小衬底被绝缘保护层覆盖区域绝缘膜层的应力集中现象,将衬底被绝缘保护层覆盖区域的凸起图形缩小的同时,通过蚀刻工艺的优化,制作成偏圆弧状或者平台状的图形,当绝缘保护层覆盖在凸起上时,利于凸起顶部平缓过渡,减小图形顶部应力集中的现象,即被绝缘保护层覆盖区域的凸起顶部为圆弧状或者平台状。
根据本发明,优选的,PSS图形凸起与图形凸起之间的间隙由于表面起伏,在覆盖绝缘保护层后也有较大的应力,被绝缘保护层覆盖区域的凸起密度设计为 衬底被第一半导体层覆盖区域的凸起密度的1/10~1/2。通过减小芯粒边缘处的图型密度,达到平缓过渡绝缘保护层,降低绝缘膜层应力的目的。具体来说,例如将衬底被绝缘保护层覆盖区域的凸起的间隔拉大到2微米及以上,从而尽可能拉平绝缘保护层。
根据本发明,优选的,至少部分覆盖衬底凸起的绝缘保护层采用柔性绝缘材料,利用柔性绝缘材料的延展性消除或减少膜层应力,降低绝缘保护层的起伏,也可在柔性绝缘材料上再覆盖一层常规绝缘保护层。
根据本发明,优选的,绝缘保护层的材料可以采用相对刚性的二氧化硅、氮化硅、氧化钛、氧化钽或者氧化铌,也可以为布拉格反射镜DBR,也可以采用柔性绝缘材料,例如绝缘胶材。
根据本发明,优选的,至少部分覆盖衬底凸起的绝缘保护层厚度为0.5至2微米,或者2至5微米,在Mini产品中绝缘保护层的设计需综合考虑多项因素,例如,由于尺寸小、电流集中的特点,设计中希望尽可能降低绝缘保护层的厚度,提高产品散热能力和可靠性。本发明以绝缘保护层厚度为2微米为例,确保绝缘保护层不会因破裂(除了陡峭破裂还包括过薄情况下,抓取顶针容易顶破等)而导致共晶电极与P型区短路,引起的芯粒失效。
习知的Mini产品相对常规尺寸产品,其芯片尺寸小,导致劈裂工艺难度上升,作为通常应对策略,移除芯粒与芯粒之间的外延发光层至露出衬底。
根据本发明,优选的,至少部分衬底被绝缘保护层覆盖区域的凸起高度与覆盖衬底凸起的绝缘保护层厚度的比值大于0.5,在限制绝缘保护层厚度的条件下,本发明的技术方案可尽可能保留凸起高度。
根据本发明,优选的,倒装发光二极管的芯片尺寸不大于250微米*250微米。根据本发明,优选的,倒装发光二极管为微型发光二极管(Micro LED),例如具有从2至100微米,或者100至500微米的长度。倒装发光二极管具有从2至100微米,或者100至500微米的宽度。倒装发光二极管具有从2至100微米,或者100至200微米的高度。
根据本发明,优选的,绝缘保护层的起伏的顶峰高度为大于0至小于等于0.5微米,因衬底在去除凸起后,需防止过度蚀刻造成破坏,绝缘保护层的非绝对平 坦表面。
根据本发明,优选的,衬底被绝缘保护层覆盖区域至少部分位于发光二极管边缘,或者衬底被绝缘保护层覆盖区域位于发光二极管整个周边。
根据本发明,优选的,衬底被第一半导体层覆盖区域的凸起包括第一部分和第二部分,第二部分可以堆叠在第一部分上,其中第二部分为可移除部分,在一些移除工艺下,第二部分容易与第一部分分离,这里容易指的是工艺简单,且可靠性高,衬底被绝缘保护层覆盖区域的凸起仅包括第一部分。
根据本发明,优选的,第一部分凸起表面为平滑表面,有利于绝缘保护层平整覆盖,减少由于高低起伏造成的破裂问题。
发明的有益效果
本发明的有益效果包括:芯片边缘处绝缘保护层结构完整,可进一步提升芯片的长期使用可靠性,制作工艺简单,对亮度的影响较小,技术应用范围广。
对附图的简要说明
附图用来提供对本发明的进一步理解,并且构成说明书的一部分,与本发明的实施例一起用于解释本发明,并不构成对本发明的限制。此外,附图数据是描述概要,不是按比例绘制。
图1为背景技术的倒装发光二极管剖面结构示意图;
图2为背景技术的倒装发光二极管衬底上覆盖绝缘保护层的照片;
图3为实施例1的倒装发光二极管剖面结构示意图;
图4为实施例1的倒装发光二极管衬底上覆盖绝缘保护层的照片;
图5至图11为实施例2至实施例6的倒装发光二极管剖面结构示意图;
图12和图13为实施例6中两种实施例中凸起结构示意图;
图14和图15为实施例7的倒装发光二极管剖面结构示意图。
图中标示:100:衬底,110、111、112:凸起,110’:第一部分,110”:第二部分,110”’:第三部分,200:外延发光层,211:N侧层,212:缓冲层,221:P侧层,230:有源层,310:第一电极,320:第二电极,400:绝缘保护层, 500:电流扩展层。
发明实施例
下面便结合附图对本发明若干具体实施例作进一步的详细说明。但以下关于实施例的描述及说明对本发明保护范围不构成任何限制。
应当理解,本发明所使用的术语仅出于描述具体实施方式的目的,而不是旨在限制本发明。进一步理解,当在本发明中使用术语“包含”、″包括″时,用于表明陈述的特征、整体、步骤、组件、和/或封装件的存在,而不排除一个或多个其他特征、整体、步骤、组件、封装件、和/或它们的组合的存在或增加。
除另有定义之外,本发明所使用的所有术语(包括技术术语和科学术语)具有与本发明所属领域的普通技术人员通常所理解的含义相同的含义。应进一步理解,本发明所使用的术语应被理解为具有与这些术语在本说明书的上下文和相关领域中的含义一致的含义,并且不应以理想化或过于正式的意义来理解,除本发明中明确如此定义之外。
图3分别是示意性地示出了根据本发明构思的示例实施例的发光二极管的剖面示意图。
参考图3,根据本发明列举的第一个实施例的发光二极管(LED),发光二极管为倒装发光二极管,特别是小尺寸或者微尺寸的倒装发光二极管,例如尺寸不大于250微米*250微米的Mini LED,长宽分别为100微米至500微米,高为100微米至200微米,作为一个单元,可以包括:表面具有一系列凸起(110)的衬底100和位于衬底100上的外延发光层200。如果发光二极管为微米级则倒装发光二极管为微型发光二极管(Micro LED),例如具有从2微米至100微米长度,具有从2微米至100微米的宽度,具有从2微米至100微米的高度。
称为蓝色发光二极管和绿色发光二极管的构成材料的氮化物化合物半导体由于晶格失配而容易引起许多位移,因为与晶格匹配型化合物半导体(例如GaAs化合物半导体)相比,没有适配的衬底和化合物半导体,其可以形成具有与衬底相同的晶格常数的生长晶体层。结果,有源层(发光层)容易受到由于位移引 起的缺陷的影响,并且在电学和机械上变得脆弱。
因此,本实施例采用图形化的晶片作为生长衬底100,降低上述衬底失配造成的外延生长影响,衬底100表面的一系列凸起110图形可采用图形压印、干法蚀刻或者湿法蚀刻制作。衬底上100凸起110的形状包括圆锥、三角锥、六角锥、类圆锥、类三角锥或者类六角锥。可通过调控衬底图形形状或者尺寸提升整体发光二极管的出光效率。外延发光层200包括覆盖在衬底上的第一半导体层(N型)、第二半导体层(P型)和位于两者之间的有源层230。发光二极管的电极包括第一电极310与第二电极320,依次分别与N侧层/P侧层欧姆接触。当分别提供电压于第一电极310与第二电极320,电流从第二电极320,通过外延发光层200,流向第一电极310,并且横向分布于外延发光层200的磊晶结构中,使其发生光电效应而产生光子。有源层230根据材料和工艺条件的不同可以具有不同波长的激发出光。上述外延发光层200可以通过采用金属有机化合物化学气相沉淀(英文缩写为MOCVD)在生长衬底100上或通过覆晶技术粘结在散热性基板上。上述发光二极管为蓝光系发光二极管,外延发光层200材料为GaN基化合物。第一电极310和/或第二电极320一般可直接形成于外延发光层200上,用于连通外部电源,激发量子阱层(有源层)发光。
本实施例的制作工艺提供的衬底材料可以从蓝宝石、硅、碳化硅或者砷化镓中选择。该实施例优选以氮化镓基器件为例,采用蓝宝石衬底100,第一半导体层可以包括N侧层211和缓冲层212,缓冲层212位于N侧层211和衬底100之间,缓冲层212与衬底100接触,缓冲层212用于减轻衬底100和N侧层211之间的晶格失配,从而促进N侧层211的晶体生长。缓冲层212对半导体的功能基本上没有直接影响。为建立第一电极310和N侧层211的电连接,需露出部分N侧层211台面。N侧层211会产生自由电子,而P侧层221会一定浓度的空穴,电子空穴在电场作用下在有源层多量子阱中结合,造成能阶被降低,并以光子形式释放能量而发光,以在整个表面上产生发光状态。有源层230可以是用于限制电子空穴移动的多重量子阱(Multiple Quantum Well,MQW),借由增加电子空穴碰撞机率,因而增加电子空穴结合率与发光效率。
在从衬底100侧发射光的类型的倒装发光二极管中,通过部分移除N侧层211, 形成N侧凹槽或者平台,露出N侧层211开口用于制作第一电极310,为了有效地发光,重要的是设计第一电极310(N侧电极)以使其面积(宽度)最小化并防止电气劣化,考虑电流和扩散之间的关系以及接触电阻的特性。而且,为了实现具有更高亮度的发光二极管,关键点是增加发光层的面积。在具有确定的外部尺寸的发光二极管中,可以通过减小第一电极310(N侧电极)的面积来增加有源层的面积。
另一方面,鉴于组装倒装发光二极管的步骤(组装在电路板或封装基座上)的要求,需要焊盘部分具有在引线键合步骤和管芯键合步骤中保证尺寸(不降低机械强度或降低安装性能)。该要求与减小第一电极310(N侧电极)的面积的要求相反。
因此,第一电极310(N侧电极)通常尽可能地减小尺寸,同时确保对安装没有影响的最小焊盘区域,并且设置为使第一电极310和第二电极320之间的间隔最小化(N侧电极和P侧电极)。当诸如静电的高电场施加到发光二极管时,高电场直接施加到化合物半导体层和第一/第二电极之间的空间。因此,电极之间绝缘保护层400的耐电压特性是决定发光二极管的静电击穿强度的重要因素。
来自有源层230的光通过衬底100直接发射到外部或者被第二电极320反射,然后通过第二电极320发射到外部。作为用于形成第二电极320的材料,例如,使用具有高反射率的银(Ag)。为了提高第二电极320的可靠性,第二电极320通常通过诸如等离子体CVD的CVD方法或诸如真空沉积或溅射的PVD方法用绝缘保护层400覆盖。绝缘保护层400分别设置在第一电极310和第二电极320和两者上方的开口,第二电极320、绝缘保护层400和第二半导体层(P侧层221)之间设置有电流扩展层500,例如经常采用的材料ITO(氧化铟锡),作用在于引导电流从第二电极320更均匀地注入到第二半导体层,电流扩展层500位于第二电极320下方和第二半导体层上方。绝缘保护层400可以是电绝缘材料。例如,绝缘保护层400可以是二氧化硅、氮化硅、氧化钛、氧化钽、氧化铌、钛酸钡或者其组合,组合例如可以是布拉格反射镜(DBR)。绝缘保护层400根据设计的位置具有不同的功效,例如覆盖外延发光层侧壁用于防止导电材料泄露电连通第一半导体层和第二半导体层,减少发光二极管的短路异常。
取决于发光二极管的尺寸,需要减小绝缘保护层400的厚度,增加第二电极320和设置在绝缘保护层400上的第一电极310延伸部分之间的重叠面积,并形成绝缘保护层400使用具有较高介电常数的材料,本实施例中绝缘保护层400的厚度为2~5微米,绝缘保护层也可以为布拉格反射镜DBR。
在通常的技术中,在基于CVD或PVD方法形成的绝缘膜中容易出现针孔或裂缝,并且当由于电极结构或器件结构(例如衬底图形凸起)而存在陡峭部分时,可能难以用绝缘保护层400牢固地覆盖陡峭部分。此外,由于污染物或异物的存在,在绝缘保护层400中可能出现针孔或裂缝。并且,陡峭部分可能成为绝缘保护层400的不连续生长点。
倒装发光二极管芯片结构为了形成对器件的有效保护,在衬底100上预留露出一部分未覆盖外延发光层200区域,将绝缘保护层400部分包裹住外延发光层200,同时绝缘保护层400也会部分覆盖在图形化衬底100上,衬底100被绝缘保护层400覆盖区域至少部分位于发光二极管边缘,或者衬底100被绝缘保护层400覆盖区域位于发光二极管整个周边,在小尺寸芯片中,例如Mini LED,由于外延发光层200面积尽可能被压缩,因此侧壁保护的效果显著影响器件的性能,而该问题在常规尺寸的发光二极管中由于尺寸较大吧,衬底100边缘电流发布可以忽略,反之小尺寸芯片由于外延发光层200边缘电流密度增大,边缘绝缘保护层400防止漏电的问题则应该被重视,本实施例通过缩小图形化生长衬底100从外延发光层200露出的凸起110,减小衬底100表面的陡峭程度,降低衬底100图形对绝缘保护层400的影响,特别是对位于外延发光层边缘的绝缘保护层400的影响。
衬底100从外延发光层200露出(具体是指第一半导体层),衬底100露出区域的凸起至少部分被绝缘保护层400覆盖,衬底100露出区域的凸起上绝缘保护层400具有高低起伏,经过减小后的凸起111,凸起111高度h1为0至1微米,其上绝缘保护层400起伏波动被缓和,该区域绝缘保护层400的顶峰高度(图中标识为h)为0至0.5微米。衬底100表面降低凸起高度的方法包括湿法蚀刻或者干法蚀刻。而被外延发光层200覆盖的衬底凸起112高度h2为2至2.5微米。在本实施例中,衬底100被第一半导体层覆盖区域的凸起112高度h2与衬底露出区域的凸起111上绝缘保护层400起伏的顶峰高度h的比值大于3,图形改变即不影响衬底对外延生 长质量,且能实现绝缘保护层400的平缓化。
衬底100被绝缘保护层400覆盖区域的凸起111高度至少部分为衬底100被第一半导体层覆盖区域的凸起112高度h2的1/10至1/2。凸起111的高度和绝缘保护层400的厚度有一定关系,凸起111上再覆盖绝缘保护层400,绝缘保护层400平缓地在两个凸起111之间过渡,可消除针孔或裂缝现象。本实施例重点记载了衬底100和绝缘保护层400设计,而对芯片其他组成及工艺均采用简单描述。
参考图4,和聚焦在覆盖在衬底凸起111上方的绝缘保护层400的俯视照片,如照片中显示绝缘保护层400连续完整,较佳地覆盖在衬底100和外延发光层200表面,最后,制作完芯片工艺的发光二极管晶圆切割成芯粒并进一步进行树脂模塑和封装,以完成例如壳型和表面安装型的各种发光二极管。
本发明提供的第二至第七个实施例跟第一个实施例待解决的技术问题是类似的,都是为了避免绝缘保护层400因为衬底100图形起伏带来的陡峭形状而造成破裂,主要设计区别几种在衬底100凸起的改变上,因为整体结构例如外延发光层200和其上的第一电极310、第二电极320、绝缘保护层400、透明导电层500等大体一致,不在实施例中重复说明。
参考图5,根据发明列举的第二个实施例的发光二极管,该实施例中芯片***无外延发光层200覆盖区域中未设置衬底图形,实施例的工艺方法包括,衬底100处理流程中在制作衬底图形,不制作芯片***部分的衬底图形,仅制作芯片工艺中外延发光层200下方对应的图形凸起112,例如采用掩膜蚀刻的方式制作衬底图形。在该实施例中,相比实施例1,对制作隔离槽图形的设备精度要求较高,特别是现阶段通常采用晶圆平边对位的方式,预留无凸起的衬底100区域,比较难完全与后续芯片工艺边缘移除外延发光层200的区域吻合,可以采用的做法是适当扩大不做图形凸起的衬底区域,以降低对位的难度。本实施例也可以采用全图形的衬底100,先于衬底100上制作外延芯片工艺,在隔离槽制作流程中移除部分外延发光层200至裸露出***衬底,再利用掩膜蚀刻技术移除***衬底的图形,而后在外延发光层200及平整的***衬底表面覆盖绝缘保护层400,该绝缘保护层400起伏显著下降,而该工艺需精准控制蚀刻量,以兼顾图形移除和器件保护。
参考图6,根据本发明列举的第三个实施例的发光二极管,采用缩小凸起尺寸,且扩大凸起在衬底分布密度的工艺,相对本发明的实施例2,本实施例的制作工艺可操作性较高,其中一种制作该衬底的方法为,在制作图形衬底时,通过改变掩膜图形,调整蚀刻时间,制作得预定尺寸、合适密度的凸起图形,该工艺为衬底行业已成熟的技术,此处不再赘述。在本实施例的芯片结构中,衬底100被第一半导体层覆盖区域的凸起111高度为1至2微米,也可以说整片衬底100的凸起高度为1微米至2微米,而衬底100被绝缘保护层400覆盖区域,绝缘保护层400具有高低起伏,起伏的顶峰高度h为0至0.5微米,衬底100被外延发光层400覆盖区域的凸起112之间的间距和被绝缘保护层覆盖区域的凸起111之间的间距均不小于2微米。通过扩大衬底凸起图形的间距,盖在凸起间的绝缘保护层400有更长的距离过渡,减小绝缘保护层400坡度,使绝缘保护层400更加平缓的覆盖在衬底100上,从而减少陡峭和应力集中现象。该实施例的优势在于可以拥有一定高度的衬底图形高度而能兼顾外延生长质量和减小漏电现象,必要高度的衬底图形能减小外延发光层400在衬底100上生长的缺陷,利于提高内量子效应。
参考图7,根据本发明列举的第四个实施例的发光二极管,在衬底100被第一半导体层覆盖区域的凸起112采用密集分布,衬底100被第一半导体层覆盖区域的凸起112的间距为不大于3微米,而在被绝缘保护层400覆盖区域的凸起112采用稀疏分布,被绝缘保护层400覆盖区域的凸起111的间距均不小于2微米,以2微米厚的绝缘保护层400为例,衬底100被第一半导体层覆盖区域的凸起112的间距为2微米,而在被绝缘保护层400覆盖区域的凸起112的间距为8微米,可以参考的,衬底100被绝缘保护层400覆盖区域的凸起112密度为衬底100被第一半导体层覆盖区域的凸起112密度的1/10~1/2,这里密度指的是单位面积下凸起的分布数量。
本实施例主要优势在于适应不同的外延长晶工艺,可采用常规凸起高度的生长衬底100,例如凸起高度为2至2.5微米,同时兼顾外延生长质量,绝缘保护层400覆盖在衬底凸起111上,由于凸起111间距较大,绝缘保护层400仍可保证完整性,提供良好绝缘保障。
参考图8,进一步地,可采用低凸起高度的生长衬底100进行长晶并进一步制作芯片工艺,例如凸起高度为1至2微米,而后在制作芯片隔离槽时移除部分被绝缘保护层400覆盖区域的凸起111,降低该区域凸起111分布密度,在芯片端图形的移除时间会小于实施例1中凸起消除的时间。
进一步地,也可以衬底100被第一半导体层覆盖区域的凸起112的高度为2至2.5微米,而被绝缘保护层400覆盖区域的凸起111为1至2微米,被绝缘保护层400覆盖区域的凸起112设计为稀疏且矮小。
参考图9,根据本发明列举的第五个实施例的发光二极管,在本实施例中,采用改变衬底凸起110顶端形状的方法,利用平滑或者圆滑表面形成缓冲区域,特别是针对被绝缘保护层400覆盖的衬底凸起设计,例如采用半球或者平台状凸起形状。本实施例以半球状凸起110为例,绝缘保护层覆盖在半球凸起110表面,例如凸起110高度为2至2.5微米,至少部分衬底被绝缘保护层400覆盖区域的凸起高度与覆盖衬底凸起的绝缘保护层400厚度的比值大于0.5,同时兼顾外延生长质量,绝缘保护层400覆盖在衬底凸起110上,由于凸起110表面平滑,绝缘保护层400仍可保证完整性,提供良好绝缘保障。
参考图10和图11,根据本发明列举的第六个实施例的发光二极管,在本实施例中提供了实施例五的其中一种制作方法,衬底凸起110包括第一部分110’和第二部分110”,其中第一部分110’更靠近衬底100,第二部分110”位于第一部分110’上,第二部分110”为牺牲部,第二部分110”可以比第一部分110’易于移除,在外延/芯片工艺中,先在衬底100上制作半导体外延发光层200,如实施例1的工艺流程制作芯片结构,露出衬底100后移除位于隔离槽的第二部分110”。其中,第一部分110’形状可以为半球、平台、圆锥、三角锥、六角锥、类圆锥、类三角锥或者类六角锥,由第一部分110’和第二部分110”组合而成的衬底凸起形状可以为半球、平台、圆锥、三角锥、六角锥、类圆锥、类三角锥或者类六角锥。移除第二部分110”后,一方面可降低衬底凸起高度,另一方面兼顾外延生长质量的同时,可二次设计适合覆盖绝缘保护层400的衬底图形。在一些实施例中,如图11所示,第二部分110”包裹在第一部分110’外侧,通过移除位于隔离槽的第二部分110”从而保留第一部分110’图形。在该实施例中,第一部分110’可以与 衬底100同质,例如采用蓝宝石,第二部分110”采用易于蚀刻移除的二氧化硅或者也可以是氮化铝,氮化铝的移除难度大于二氧化硅,但却适合作为半导体氮化镓的长晶面,具有较小的晶格适配问题。
进一步地,相比蓝宝石或者氮化铝,二氧化硅与氮化镓的晶格匹配度差,但移除容易,为了兼顾工艺难度和长晶质量,衬底凸起可包括三部分,第一部分110’为蓝宝石,第二部分110”为二氧化硅,第三部分110”’为氮化铝,第二部分110”为牺牲层,第三部分110”’为长晶层,第二部分110”位于第一部分110’和第三部分110”’之间。即可以概扩为第三部分110”’比第二部分110”适合作为长晶界面,第二部分110”比第一部分110’和/或第三部分110”’易于移除,在第三部分110”’上进行外延长晶工艺,制作芯片工艺时,通过选择性移除较容易去除第二部分110”,同时去除第二部分110”上的第三部分110”’,在衬底露出区域保留第一部分110’用于覆盖绝缘保护层400。
参考图12,根据本发明列举的第七个实施例的发光二极管,为了防止芯粒的衬底露出区域PSS图型应力集中区域绝缘膜层400的开裂,我们在制作完外延发光层200去除露出衬底凸起110后,对隔离槽进行耐高温柔性绝缘层填充。在本实施例中对绝缘保护层的材料进行修改,具体来说至少部分采用柔性绝缘保护层400的材料,采用绝缘胶材覆盖衬底凸起110,胶材的延展性可克服凸起图形造成的应力集中问题。考虑到柔性绝缘保护层自身的一些特性,可能不适合作为发光二极管绝缘保护层的唯一材料,进一步的,发光二极管的绝缘保护层400包括第一绝缘层410和第二绝缘层420,其中第一绝缘层410采用二氧化硅、氮化硅、氧化钛、氧化钽、氧化铌、钛酸钡或者其中任意组合。第二绝缘层420位于凸起110上,采用的材料例如环氧树脂或者光刻胶,优选的,采用热固性好的绝缘材料,避免后续芯片或者封装工艺中,绝缘保护层失效,第二绝缘层420也可以是热固性聚酰亚胺、派瑞林(Parylene N/C/D/HT)、聚苯并恶唑(PBO)等其中一种或组合,第一绝缘层410主要覆盖在发光二极管主体上。
在一些实施方式中,第一绝缘层410位于第二绝缘层420上方,且与第二绝缘层420相接,只需在移除外延发光层200和露出衬底后用柔性绝缘材料填充隔离槽,制作工艺相对简单。
参考图13,在一些实施方式中,将实施例1~3和实施例7的技术方案相结合,我们先将至少部分衬底露出区域或者整片衬底的PSS图型采用蚀刻的方式缩小或者移除,再填充第二绝缘层420,这样可以用较薄的柔性绝缘材料就可以实现覆盖衬底露出区域的平坦化处理。
在一些实施方式中,采用实施例3和实施例4的手段,与实施例7的第一绝缘层410/第二绝缘层420(柔性)相结合,进一步减小衬底露出区域的凸起110密度,同步填充第二绝缘层420,减小凸起110之间柔性绝缘层的应力。
在一些实施方式中,将实施例5和实施例7的技术方案相结合,为了进一步减小图型顶部应力集中的现象,将衬底的图型缩小(或者仅衬底露出区域的图形缩小)的同时,通过蚀刻工艺的优化,制作成偏圆弧状的凸起110图型,再填充上第二绝缘层420。
在实施例7中列举几种实施方式,还可以显而易见地与实施例6或者多个实施例的特点相结合构成新的技术方案,各个特点的技术效果相近,例如利用牺牲层技术制作得到更好外延质量的发光二极管,实施例7中,在衬底100露出区域和外延发光层200之间的绝缘保护层400结构完整,可进一步提升芯片的长期使用可靠性。
本领域技术人员应该理解,取决于设计要求和其他因素,可以进行各种修改,组合,子组合和变更,只要它们在所附权利要求或其等同物的范围内即可。
Claims (26)
- 一种倒装发光二极管,包括表面具有一系列凸起的衬底和位于衬底上的外延发光层,外延发光层包括覆盖在衬底上的第一半导体层、第二半导体层和位于两者之间的有源层,与第一半导体层连接有第一电极,与第二半导体层连接有第二电极,其特征在于,衬底部分区域从第一半导体层露出,衬底露出区域的凸起至少部分被绝缘保护层覆盖,衬底露出区域的凸起上绝缘保护层具有高低起伏,起伏的顶峰高度为0至0.5微米。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被绝缘保护层覆盖区域的凸起至少部分高度低于衬底被第一半导体层覆盖区域的凸起高度。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被第一半导体层覆盖区域的凸起高度为1至2微米,或者为2至2.5微米。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被绝缘保护层覆盖区域的凸起高度至少部分为0至1微米,或者为1至2.5微米。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被第一半导体层覆盖区域的凸起高度与衬底露出区域的凸起上绝缘保护层起伏的顶峰高度的比值大于3。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被绝缘保护层覆盖区域的凸起高度至少部分为衬底被第一半导体层覆盖区域的凸起高度的1/10~1/2。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底上凸起的形状包括半球、平台、圆锥、三角锥、六角锥、类圆锥、类三角锥或者类六角锥。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被绝缘保护层覆盖区域的凸起中至少部分顶部为圆弧状或者平台状。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被绝缘 保护层覆盖区域的凸起密度为衬底被第一半导体层覆盖区域的凸起密度的1/10~1/2。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被绝缘保护层覆盖区域的凸起的间距不小于2微米。
- 根据权利要求1所述的倒装发光二极管,其特征在于,至少部分覆盖衬底凸起的绝缘保护层采用柔性绝缘材料。
- 根据权利要求1所述的倒装发光二极管,其特征在于,绝缘保护层材料包括的二氧化硅、氮化硅、氧化钛、氧化钽、氧化铌、布拉格反射镜DBR或者绝缘胶材。
- 根据权利要求1所述的倒装发光二极管,其特征在于,至少部分覆盖衬底凸起的绝缘保护层厚度为0.5微米~5微米。
- 根据权利要求1所述的倒装发光二极管,其特征在于,至少部分衬底被绝缘保护层覆盖区域的凸起高度与覆盖衬底凸起的绝缘保护层厚度的比值大于0.5。
- 根据权利要求1所述的倒装发光二极管,其特征在于,倒装发光二极管的芯片尺寸不大于250微米*250微米。
- 根据权利要求1所述的倒装发光二极管,其特征在于,倒装发光二极管具有从2微米到100微米或从100微米到500微米的长度。
- 根据权利要求1所述的倒装发光二极管,其特征在于,倒装发光二极管具有从2微米到100微米或从100微米到500微米的宽度。
- 根据权利要求1所述的倒装发光二极管,其特征在于,倒装发光二极管具有从2微米到100微米或从100微米到200微米的高度。
- 根据权利要求1所述的倒装发光二极管,其特征在于,绝缘保护层的起伏的顶峰高度为大于0至小于等于0.5微米。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底的材料包括蓝宝石、硅、碳化硅或者砷化镓。
- 根据权利要求1所述的倒装发光二极管,其特征在于,外延发光层的材料为氮化镓基。
- 根据权利要求1所述的倒装发光二极管,其特征在于,第一半导体层包括N侧层和缓冲层,其中缓冲层与衬底接触。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被绝缘保护层覆盖区域至少部分位于发光二极管边缘,或者衬底被绝缘保护层覆盖区域位于发光二极管整个周边。
- 根据权利要求1所述的倒装发光二极管,其特征在于,衬底被第一半导体层覆盖区域的凸起包括第一部分和第二部分,其中第二部分为可移除部分,衬底被绝缘保护层覆盖区域的凸起仅包括第一部分。
- 根据权利要求24所述的倒装发光二极管,其特征在于,第一部分凸起表面为平滑表面。
- 一种显示屏,其特征在于,具有权利要求1至权利要求25中任意一项所述的倒装发光二极管。
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