WO2020258958A1 - 一种时间同步的方法和服务器 - Google Patents
一种时间同步的方法和服务器 Download PDFInfo
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- WO2020258958A1 WO2020258958A1 PCT/CN2020/081834 CN2020081834W WO2020258958A1 WO 2020258958 A1 WO2020258958 A1 WO 2020258958A1 CN 2020081834 W CN2020081834 W CN 2020081834W WO 2020258958 A1 WO2020258958 A1 WO 2020258958A1
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- time
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- cpld
- register
- bmc
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Definitions
- This application relates to the field of server technology, and in particular to a time synchronization method and server.
- RTC circuits can be provided on the printed circuit board (PCB) in each server.
- the RTC circuit is connected to each component in the server through a programmable logic device (PLD), obtains time information from the RTC through the PLD, and then the PLD shares the time information to each component to provide time information to each component.
- PLD programmable logic device
- components such as baseboard management controller (baseboard management controller, BMC), central processing unit (central processing unit, CPU), etc.
- BMC baseboard management controller
- CPU central processing unit
- the RTC circuit can provide real-time time to each component of the server to ensure that each component of the server can be based on the real-time time obtained Realize functions such as business docking and log recording.
- the RTC circuit in the traditional server will occupy a large area of the PCB, which affects the layout of the components in the PCB. It is impossible to increase the number of other important components in the limited space provided by the same PCB, resulting in the limited processing capacity of the server.
- the only way to meet their requirements is to increase the number of servers, which increases the cost of server hardware.
- This application provides a time synchronization method and server to reduce the occupied area of the RTC circuit on the PCB in the server and reduce the cost of the server.
- this application provides a method of time synchronization.
- the method can be applied to a server.
- the RTC circuit may not be set in the server.
- the server includes BMC and CPLD.
- the BMC is connected to the CPLD.
- the method includes: BMC can be obtained first The first time, after that, store the acquired first time in the CPLD time register; the time stored in the time register can be updated in real time to store the real-time time; the first time is the time when the BMC obtains the first time operation; CPLD can Based on the first time, start timing and record the timing result.
- the CPLD determines the second time according to the first time and the timing result; and updates the time register according to the second time.
- the BMC in the server obtains the first time and saves the obtained first time in the CPLD, and because the CPLD has a timing function, the time register in the CPLD can record the real-time time so that the time register in the CPLD can record Real-time time can be provided to other components of the server to ensure the normal operation of each component in the server.
- RTC circuits are not required to be deployed in the server, and more important components can be deployed on the PCB in the server, which can improve server performance and effectively reduce Server hardware cost.
- the BMC and the CPLD may communicate through the first interface.
- the BMC stores the acquired first time in the time register of the CPLD
- the first time may be stored in the time register of the CPLD through the first interface.
- the CPLD is provided with the first interface connected with the BMC, so that the BMC can update the first time to the time register more quickly and conveniently.
- the processor and the CPLD can communicate through the second interface, and the processor can read the second time from the time register through the second interface; the processor starts timing and records the real time based on the second time.
- the processor can obtain the second time from the CPLD and start timing to perform some operations that require real-time time as a reference, such as business docking, log recording, etc., so that the processor can operate normally.
- the CPLD timing method is different, and the timing result is also different; for example, the CPLD can be timed by recording the time value.
- the CPLD timing result can be the time value, correspondingly, preset
- the threshold indicates the time interval for CPLD to update the time register; in this way, the CPLD updates the time stored in the time register after each time interval, so that the time recorded by the time register is guaranteed to be consistent with the time of the NTP server.
- the CPLD can record the number of counts and count the number of times.
- the timing result of the CPLD is the number of counts.
- the preset threshold indicates the maximum number of counts of the CPLD.
- the CPLD updates the time stored in the time register whenever the number of counts reaches the maximum number of counts, which can also ensure that the time recorded by the time register is consistent with the time of the NTP server.
- the second time can be determined by an accumulation method; for example, the CPLD can determine the second time according to the accumulation result of the first time and the timing result, Determine the second time.
- the CPLD determines the second time by using an accumulation method, and the second time can be more accurately reflected as the time at the current moment.
- the BMC when the BMC obtains the first time, it can obtain the first time from an NTP server, or it can obtain the first time from a time-calibrated server.
- the first time obtained by the BMC is relatively accurate, which ensures that the second time that can be determined by the subsequent CPLD through timing can be consistent with the real-time time of the NTP server.
- the processor may also obtain user configuration data from the storage medium in the server, and start based on the user configuration data.
- the storage medium may be a non-volatile storage medium, or may be powered by a power supply, The storage medium that does not lose data when the server is powered off.
- the processor can still obtain user configuration data under the condition that the server does not deploy the RTC circuit, so that the processor can operate normally.
- this application provides a time synchronization device, which has the functions implemented by the BMC, the processor, and the CPLD in any one of the possible designs of the first aspect and the first aspect.
- the function can be realized by hardware, or by hardware executing corresponding software.
- the hardware or software includes one or more modules corresponding to the above-mentioned functions.
- the structure of the device includes a management unit, a timing unit, and a processing unit.
- the timing unit also includes a storage unit. These units can perform the corresponding functions of the BMC, the processor, and the CPLD in the example of the first aspect. The detailed description in the example of the first aspect will not be repeated here.
- the present application also provides a server.
- the structure of the server includes a baseboard management controller, a complex programmable logic device, a processor, and a memory.
- the processor is configured to support the processor to execute any one of the aforementioned first aspect and any one of the possible designs of the first aspect.
- the function of the memory is coupled with the processor, which stores the necessary program instructions and data.
- the baseboard management controller is configured to support the baseboard management controller to execute the corresponding function in the baseboard management controller of any possible design of the first aspect and the first aspect;
- the complex programmable logic device is configured to support complex programmable logic The device executes the corresponding function in the complex programmable logic device of the first aspect and any one of the possible designs of the first aspect;
- the communication interface is used to communicate with other devices.
- this application also provides a computer-readable storage medium that stores instructions in the computer-readable storage medium, which when run on a computer, causes the computer to execute the BMC, processor, and CPLD execution methods of the above aspects .
- this application also provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the BMC, processor, and CPLD execution methods of the foregoing aspects.
- the present application also provides a computer chip, which is connected to the memory, and the chip is used to read and execute the software program stored in the memory, and execute the BMC, processor and CPLD execution methods of the above aspects.
- FIG. 1 is a schematic diagram of a server provided by this application.
- Figure 2 is a schematic diagram of the architecture of a system provided by this application.
- FIG. 3 is a schematic diagram of three stages of server startup provided by this application.
- FIG. 4 is a schematic diagram of a time synchronization method provided by this application.
- FIG. 5 is a schematic structural diagram of a time synchronization device provided by this application.
- Fig. 6 is a schematic structural diagram of a server provided by this application.
- RTC circuits are no longer deployed in the server, but the BMC in the server obtains the time from an external server (such as T0 in the embodiment of this application), and stores the obtained time in complex programmable logic In a complex programmable logic device (CPLD), it is convenient for subsequent processors to obtain time from the CPLD so that the processor can perform a series of startup operations after power-on based on the obtained time.
- CPLD complex programmable logic device
- FIG. 1 is a schematic diagram of a time synchronization system provided by an embodiment of the application.
- the system includes a server 100 and a network time protocol (NTP) server 200.
- NTP network time protocol
- the system also includes a server 300.
- the NTP server 200 and the server 300 can be used to provide time synchronization information for the server 100, such as real-time time.
- the server 100 includes a BMC 110, a processor 120, and a complex programmable logic device (CPLD) 130.
- CPLD complex programmable logic device
- the BMC110 and the processor 120 are connected through the CPLD130.
- the CPLD 130 may include a time register 1301, and the time register 1301 may be used to store the current real-time time; such as the time T0 and the updated T1 in the embodiment of the present application.
- CPLD130 also has a timing function, which can time based on the time T0 sent by BMC110, obtain the current real-time time, and update the time stored in the time register 1301.
- the BMC 110 is used to monitor and manage various components in the server.
- the BMC 110 can monitor the temperature and voltage of components in the server 100 (such as the processor 120, the storage medium in the server 100, etc.); it can also control the speed of the fan in the server 110.
- the BMC110 may also have a timing function.
- the BMC110 may include a clock circuit, which can be used for timing.
- the BMC 110 can be connected to each processor 120 through a CPLD 130.
- the BMC 110 A CPLD130 is set between each processor 120; the BMC110 can update the acquired time to the time register 1301 in each CPLD130, and the processor 120 obtains real-time time from the time register 1301 of the connected CPLD130.
- BMC110 can also be connected to some processors 120 of multiple processors 120 through one CPLD130, that is, multiple processors 120 can be connected to one CPLD130; BMC110 can obtain time Update to the time register 1301 in each CPLD 130 connected to it, and the processor 120 obtains the real-time time from the time register 1301 of the connected CPLD 130.
- the BMC 110 may be connected to one of the processors 120 (for convenience of description, the processor may be called the first processor) through the CPLD 130, and the multiple processors 120
- the remaining processors except the first processor may be referred to as second processors
- the second processor can be used as a coprocessor of the first processor to perform some operations in cooperation with the first processor; the second processor can also be a processor with the same functions as the first processor, and the embodiment of the present application does not Define the type and function of the second processor.
- the BMC 110 may update the acquired time to the time register 1301 in the CPLD 130, and the first processor obtains the real-time time from the time register 1301 of the CPLD 130 connected to it.
- the second processor can obtain the real-time time from the connected first processor; in the above description, a first processor is taken as an example for description.
- the embodiment of the present application does not limit the number of first processors.
- the BMC110 can be The multiple first processors are connected through the CPLD130, and the remaining processors can be connected to any one of the multiple first processors to obtain real-time time.
- the CPLD 130 in addition to the time register 1301, the CPLD 130 also includes a counter 1302, a BMC interface 1303 and a processor interface 1304.
- the BMC110 can store the acquired time T0 in the time register 1301 through the BMC interface 1303; the counter 1302 can acquire the time T0 from the time register 1301 and start timing, and can also update the time register 1301. As time progresses, the time register The time stored in 1301 is continuously updated, and the real-time time at the current moment can always be recorded; the processor 120 can read the real-time time at the current moment (such as time T1) from the time register 1301 through the processor interface 1304.
- the embodiment of the present application does not limit the timing of the counter 1302.
- the counter 1302 may include a clock circuit, and the counter 1302 may use the clock circuit to perform timing based on T0.
- the counter 1302 can also be based on a clock circuit to generate a pulse signal S1 of a fixed period (for example, the fixed period is 1 second); then, the counter 1302 uses the pulse signal S1 to time the clock, the starting value of the time is T0, and the counter 1302 generates A pulse signal S1 accumulates 1 to T0 for timing.
- a clock circuit to generate a pulse signal S1 of a fixed period (for example, the fixed period is 1 second); then, the counter 1302 uses the pulse signal S1 to time the clock, the starting value of the time is T0, and the counter 1302 generates A pulse signal S1 accumulates 1 to T0 for timing.
- the embodiment of the present application also does not limit the manner in which the counter 1302 updates the time register 1301. For example, it may be updated at a preset time interval or may be updated at a preset maximum count. For details, please refer to the following description.
- the CPLD in the system architecture can also be used for other calculation or storage functions in the server, which is not limited in this application.
- FIG. 2 is a schematic diagram of another system architecture provided by an embodiment of the application. As shown in FIG. 2, the system includes a manager 400 and multiple servers 100. The structure of each server 100 is similar to that shown in FIG. The server 100 is similar and will not be repeated here.
- the manager 400 can be connected to multiple servers 100 to manage and control multiple servers 100.
- the manager 400 can count the number of servers 100 connected to the manager 400 and each server.
- the type and location of 100 can also be obtained from the BMC 110 in the server 100 to obtain information about some components in the server 100.
- the embodiment of the present application does not limit the connection manner of the manager 400 and each server 100.
- the manager 400 may be connected to the server 100 in a wired manner, or may be connected via a network (such as a wireless network such as Ethernet).
- the embodiment of the present application does not limit the specific form of the manager 400, and it may be a server, a chip, or other types of modules.
- the manager 400 can communicate with a server outside the system.
- the server can be an NTP server 200 or a server 300 whose time has been calibrated; for example, the manager 400 can communicate directly with the system.
- the manager 400 may obtain the time T0 from a server outside the system, and notify the server 100 connected to the manager 400 of the time T0.
- the manager 400 may send the time T0 to the BMC 110 in the server 100.
- the embodiment of the present application does not limit the specific form of the system shown in FIG. 2.
- the system shown in FIG. 2 may be a blade server, the manager 400 is a manager in the blade server, and the service 100 may be a blade server.
- the server; the system shown in FIG. 2 may also be a rack server cluster, the manager 400 is a management board in the rack server cluster, and the server 100 is any server in the rack server cluster.
- FIG. 3 is a description of the startup process of the server 100 provided by an embodiment of the application.
- the startup process of the server 100 can be divided into three stages.
- the power supply mode in the server 100 can be divided into two domains: main power ( main) and standby (standby). After the server 100 is powered on, the components in the server 100 are powered on in a preset order.
- the backup power supplies power to the BMC 110 in the server 100 (the first stage); then, the BMC 110 can send a control command, which is used to control the main power to supply power to the processor 120; after the processor 120 is powered on, the processor 120 To start booting, first boot the basic input output system (BIOS), which corresponds to the second stage; finally, boot the operating system (OS), which corresponds to the third stage.
- BIOS basic input output system
- OS operating system
- BMC110 starts.
- the functions of the BMC110 are initialized.
- the BMC110 can complete the initialization with the BMC interface 1303.
- the initialization operation includes loading the driver of the interface and connecting to the CPLD130.
- the server 100 can be controlled to enter the second stage; the BMC 110 can control the main power to supply power to the processor 120 by sending a control command to enter the second stage.
- the processor 120 After the processor 120 is powered on, it can load the BIOS, read the system configuration information of the server 100, configure the underlying hardware of the processor 120 based on the system configuration information, and execute the boot program (Boot) in the boot record (Boot Record), Complete the boot action initiated by the OS, and then enter the next stage.
- the OS starts.
- the processor 120 loads the OS kernel, performs initialization, and opens up the connection between the OS and the underlying hardware of the processor 120.
- the processor 120 can communicate with an external server. For example, a more accurate real-time time can be obtained from the NTP server. After the processor 120 obtains the real-time time from the NTP server, it performs timing based on the real-time time.
- the time synchronization method includes:
- Step 401 In the first stage of the server 100 startup, after the BMC 110 is powered on, it synchronizes time with other servers to obtain the time T0.
- the other server may be an NTP server 200 or a server 300 whose time has been calibrated in other times.
- BMC110 After BMC110 is powered on, it can synchronize time with NTP server 200. If the connection between BMC110 and NTP server 200 is interrupted or the NTP server fails, BMC110 cannot obtain the current time from NTP server 200. BMC110 can synchronize with the time shown in Figure 1. Communication with other servers in the system to obtain the current time T0.
- the time T0 refers to the moment when the BMC 110 performs the operation of acquiring the time T0, and the time T0 can specifically indicate information such as year, month, date, hour, minute, or second.
- the above-mentioned other servers may be servers 300 whose time has been calibrated.
- Step 402 BMC110 writes time T0 into time register 1301 of CPLD130.
- the BMC110 can write the time T0 into the time register 1301 of the CPLD130 through the BMC interface 1303.
- Step 403 The counter 1302 in the CPLD 130 can start timing based on the time T0, record the timing result, and update the time register 1301 according to the time T0 and the timing result.
- the counter 1302 will keep timing and continue to update the time register 1301 (that is, the counter 1302 will continue to update the time stored in the time register 1301), so that the time stored in the register is the current time, so that the server 100 and the NTP server 200 record The time remains consistent.
- a preset threshold can be set.
- the timing result reaches the preset threshold
- the counter 1302 updates the time stored in the time register 1301; for the counter 1302, the timing method is different, the recorded timing
- the counter 1302 can count by accumulating the time value, or it can record the number of counts, and count by accumulating the product of the number of counts and the counting interval. Other methods can also be used.
- the embodiment of the application is not limited For different timing modes, the time stored in the update register of the counter 1302 is different. Two of them are listed below:
- the counter 1302 can update the time register 1301 at a preset time interval.
- the timing result of the counter 1302 is a time value
- the timing result may be the time length elapsed after the counter 1302 obtains the time T0.
- the time T0 can be added to the time value generated by the time length as The time T1 is updated to the time register 1301.
- the counter 1302 starts timing after obtaining T0 from the time register 1301, and when the time recorded by the clock circuit or pulse signal of the counter 1302 reaches 5 seconds, you can change Accumulate 5 seconds at 9:00 to get 9:05, and update 9:05 to time register 1301; then use a similar method to update time register 1301, for example, counter 1302 starts after 9:05 is obtained from time register 1301
- 9:05 can be accumulated for 5 seconds to obtain 9:10, and 9:10 can be updated to the time register 1301.
- the counter 1302 can update the time stored in the time register 1301, and the time stored in the time register 1301 can be the real time at the current moment.
- the counter 1302 can update the time register 1301 according to the preset maximum count times.
- the timing result of the counter 1302 is the number of counts
- the timing result can be the number of counts after the counter 1302 obtains the time T0.
- the count result can be 5 times, which means that the counter 1302 counted after obtaining the time T0 Five times, indicating that the time elapsed after the counter 1302 acquires the time T0 is 5*1 seconds.
- the time T0 can be accumulated to the time value generated by the duration, as the time T1 is updated to Time register 1301.
- T0 is 9:00, the maximum number of counts is 5, the counting frequency of counter 1302 is once per second; counter 1302 starts timing after obtaining T0 from time register 1301, for example, according to the clock circuit of counter 1302 or The pulse signal is counted.
- the number of counts reaches 5
- the counter 1302 starts timing after obtaining the time 9:05 from the time register 1301.
- it can count according to the clock circuit of the counter 1302 or the pulse signal S1.
- 9:05 can be accumulated by 5*1 Second, get 9:10, and update 9:10 in the time register 1301.
- the counter 1302 can update the time stored in the time register 1301, so that the time stored in the time register 1301 is the real time at the current moment.
- the manner in which the counter 1302 determines that the timing result reaches the preset maximum number of counts is not limited in the embodiment of the present application.
- the counter 1302 can record the number of counts, and each time it counts, it will increase by one by comparing the recorded count number with The maximum number of counts determines whether the count result reaches the preset maximum number of counts; for example, the counter 1302 can maintain the count value, and the initial set value of the count value is the maximum number of counts.
- the counter 1302 can decrement the count value every time it counts. 1. When the count value is reduced to zero, it is determined that the count result reaches the preset maximum count times.
- the process of obtaining the time T0 by the BMC110 and writing the time T0 into the time register 1301 takes a period of time. That is, the current time when the BMC110 writes the time T0 into the time register 1301 is not the time T0, and It is a moment after time T0; in order to ensure that the time register 1301 can more accurately record the real-time time of the current moment, the counter 1302 can increase the time length ⁇ T1 on the basis of the time T0 after acquiring the time T0, that is to say When the counter 1302 gets the time T0 and updates the time register 1301 for the first time, it can increase the duration ⁇ T1 on the basis of the accumulated result of the time T0 and the timing result, generate the time T1, and write it into the time register 1301.
- the duration ⁇ T1 can be estimated
- the BMC110 obtains the time T0 and writes the time T0 into the duration of the time register 1301, which can also be an empirical value.
- each subsequent time the time register 1301 is updated, it can also increase the duration ⁇ T2 on the basis of the accumulated result of the time obtained from the time register 1301 and the timing result.
- the accumulated result of the time length ⁇ T2 is updated to the time register 1301.
- the time length ⁇ T2 can be the estimated time length obtained by the counter 1302 from the time register 1301, or an empirical value.
- the BMC110 after the BMC110 obtains the time T0, it can also use the clock circuit in the BMC110 to perform timing and record the timing result.
- the timing result is the real-time time recorded by the BMC110.
- BMC110 can use the timing results recorded by BMC110 to update the time stored in the time register 1301 in CPLD130.
- the counter 1302 in CPLD130 then counts based on the updated time of BMC110. . This ensures that the time stored in the CPLD130 can be consistent with the time recorded by the BMC110, and the accuracy of the time stored in the CPLD130 is improved.
- the BMC110 uses the timing results recorded by the BMC110 to update the time stored in the time register 1301 in the CPLD130 at regular intervals; in order to ensure that the time register 1301 can more accurately record the real-time time at the current moment, the counter 1302 can be After BMC110 updates the time stored in the time register 1301, obtain the time T2 stored in the time register 1301, and increase the duration ⁇ T3 on the basis of the obtained time T2, which means that the counter 1302 updates the time for the first time after the time stored in the BMC110 update time register 1301 When register 1301, you can increase the duration ⁇ T3 on the basis of the accumulated result of the acquired time T2 and the timing result, generate the current real-time time T3, and write it into the time register 1301.
- the duration ⁇ T3 can be the estimated time written by BMC110
- the time required to enter the time register 1301 may also be an empirical value.
- the embodiment of the present application does not limit the specific numerical values of the duration ⁇ T1, the duration ⁇ T2, and the duration ⁇ T3.
- the duration ⁇ T1, the duration ⁇ T2, and the duration ⁇ T3 can be the same or different.
- Step 404 In the second stage of the server 100 startup, the processor 120 is powered on, and the processor 120 can read the time from the CPLD130 (such as the time register 1301 in the CPLD130) through the processor interface 1304, and the time is the current time stored by the CPLD130 time.
- the processor 120 In the second stage of the server 100 startup, the processor 120 is powered on, and the processor 120 can read the time from the CPLD130 (such as the time register 1301 in the CPLD130) through the processor interface 1304, and the time is the current time stored by the CPLD130 time.
- the processor 120 when the processor 120 reads the time from the CPLD130, the current time stored in the time register 1301 in the CPLD130 is T1 as an example.
- T1 indicates that the processor 120 can read the time from the CPLD130, and the CPLD130 is updated recently time.
- the time T1 can be read from the CPLD 130, and the subsequent BMC 110 may not update the time stored in the CPLD 130.
- the BMC 110 may not update the time stored in the CPLD 130 after sending a control instruction to control the main power to supply power to the processor 120.
- the CPLD 130 may also stop timing after the processor 120 obtains the time T1 and stop updating the time register 1301.
- Step 405 After obtaining the time T1, the processor 120 performs timing based on the time T1, records the real-time time, and performs operations such as data synchronization and log recording based on the recorded real-time time.
- the processor 120 may communicate with the NTP server 200 or the time-calibrated server 300 to obtain the real-time time and update the timing result saved by the current processor 120.
- the embodiment shown in FIG. 4 can also be applied to the system architecture shown in FIG. 2.
- the BMC 110 needs to obtain the time T0 from the manager 400, and the manager 400 can obtain the time T0 from a server outside the system (such as the NTP server 200 or the time-calibrated server 300).
- a server outside the system such as the NTP server 200 or the time-calibrated server 300.
- the RTC circuit includes an RTC chip and a power supply.
- the power supply in the RTC circuit can supply power to the RTC chip.
- the RTC power supply connected to the processor is also used to control the platform controller in the processor. hub, PCH) power supply, used to ensure that the data saved in the PCH is not lost when the server is powered off.
- PCH is used to store user configuration data, such as the user configuration data for the processor 120 to start (such as the second stage, the third stage) Required information.
- these user configuration data include, but are not limited to, the processor's high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) port bandwidth setting, OS boot area setting (such as hard disk boot, CD drive boot).
- these user configuration data may be stored in a storage medium in the server 100.
- the storage medium may be a non-volatile storage medium.
- the storage medium may be a BIOS flash memory (Flash), or may have other power supplies.
- the storage medium maintained by the power supply and the data will not be lost when the server 100 is powered off.
- the processor 120 can read the user configuration data from the storage medium when entering the second stage of the server 100 startup. It is ensured that when the server 100 is not provided with a PTC circuit, the processor 120 in the server 100 can still obtain the user configuration data and can start normally, which ensures the normal performance of the server.
- the invention of this application can also be used in other system architectures.
- the extended system architecture can use other than CPLD
- the other components or logic circuits of the following methods implement the CPLD function.
- the server which can communicate with the BMC and the processor, and confirm and record the current time T1 based on the acquired time T0
- the processor can obtain the time T1 through the logic circuit, and calculate the time at the current moment based on the time T1, so as to implement the configuration of the log and other information during the OS startup process.
- the device includes a management unit 510, a timing unit 520, and a processing unit 530.
- the timing unit 520 includes a storage unit 521, and the storage unit 521 is used for storing Current time
- the management unit 510 is configured to store the obtained first time in the storage unit 521, and the first time is used to indicate the moment of the operation of obtaining the first time; the management unit 510 may be used to perform the steps in the embodiment shown in FIG. 4 401.
- the timing unit 520 is used to start timing and record the timing result; when the timing result reaches a preset threshold, the second time is determined according to the first time and the timing result; the storage unit 521 is updated according to the second time.
- the management unit 510 may be used to execute steps 402 to 403 in the embodiment shown in FIG. 4.
- the management unit 510 and the timing unit 520 may communicate through a first interface; when the management unit 510 stores the acquired first time in the storage unit 521, the first time may be stored in the storage unit 521 through the first interface.
- the device further includes a processing unit 530, and the processing unit 530 and the timing unit 520 can communicate through a second interface:
- the processing unit 530 may read the second time from the storage unit 521 through the second interface, and based on the second time, start timing and record the real-time time.
- the processing unit 530 may be used to execute steps 404 to 405 in the embodiment shown in FIG. 4.
- the timing mode of the timing unit 520 is different, and the timing result is also different. Two of them are listed below:
- the timing unit 520 performs timing by accumulating time values. In this manner, the timing result is a time value, and the preset threshold indicates the time interval for updating the storage unit 521 of the timing unit 520.
- the timing unit 520 records the count times and performs timing by accumulating the product of the count times and the counting interval. In this manner, the timing result is the count times, and the preset threshold indicates the maximum count times of the timing unit 520.
- the timing unit 520 determines the second time according to the first time and the timing result
- the second time may be determined according to the accumulation result of the first time and the timing result.
- the management unit 510 may obtain the first time from an NTP server, or obtain the first time from a server whose time has been calibrated.
- the time synchronization device in the embodiment of the present application can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD).
- ASIC application-specific integrated circuit
- PLD programmable logic device
- the above PLD can be a complex program logic.
- Device complex programmable logical device, CPLD
- field-programmable gate array field-programmable gate array
- FPGA field-programmable gate array
- GAL general array logic
- the time synchronization device and its various modules can also be software modules.
- the time synchronization device can correspond to the method described in the embodiment of the present invention, and the above and other operations and/or functions of each unit in the time synchronization device are to implement the corresponding methods in FIG. 4 For the sake of brevity, the process will not be repeated here.
- FIG. 6 is a schematic diagram of a server structure provided by an embodiment of the application.
- the server 600 includes a BMC 610, a processor 620, and a CPLD 630.
- the server 600 may further include a memory 640, a communication interface 650, and a storage medium 660.
- the BMC610, the processor 620, the CPLD630, the communication interface 650, and the storage medium 660 are connected by a bus 670.
- the processor 620 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or artificial intelligence (AI). ) Chip, system on chip (system on chip, SoC) or complex programmable logic device (CPLD), graphics processing unit (GPU), this application does not limit the type and number of processors .
- CPU central processing unit
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- AI artificial intelligence
- SoC system on chip
- CPLD complex programmable logic device
- GPU graphics processing unit
- the memory 640 is used to store computer program instructions. It can be a volatile memory, such as a random access memory; it can also be a non-volatile memory, such as a read-only memory, flash memory, hard disk drive (HDD) or solid state drive ( solid-state drive, SSD), etc.
- volatile memory such as a random access memory
- non-volatile memory such as a read-only memory, flash memory, hard disk drive (HDD) or solid state drive ( solid-state drive, SSD), etc.
- the storage medium 660 also called external storage, may be used to store data required for the operation of the server.
- the storage medium may be a non-volatile memory, such as a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape) , Optical media (such as optical discs), or semiconductor media (such as solid state drives), etc.
- the bus 670 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are marked as the bus 670 in the figure.
- CPLD630 can also realize the connection between BMC610 and processor 620 through other types of internal buses.
- the internal bus includes link control protocol (LCP), local bus, and I2C bus. (inter-integrated circuit) or serial peripheral interface (serial peripheral interface, SPI) bus connection.
- an independent data transceiving module such as a communication interface 650, can also be provided for sending and receiving data; when the BMC 610 or processor 620 communicates with other devices, data can be performed through the communication interface 650.
- the BMC 610 can obtain the first time from the NTP server 200 or the time-calibrated server 300 through the communication interface 650.
- the processor 620 in FIG. 6 can call the computer program instructions in the memory 640 to execute the method executed by the processor 120 in FIG. 4; the BMC 610 executes the method executed by the BMC 110 in FIG. method.
- the CPLD630 can perform the method performed by the CPLD130 in Figure 4.
- the memory 640 stores computer-executable instructions for implementing the functions of the processing unit in FIG. 5, and the functions/implementation processes of the processing unit in FIG. 5 can all be called by the processor 620 in FIG. 6 stored in the memory 640.
- the computer executes instructions to achieve.
- the server according to the embodiment of the present application may correspond to the time synchronization device in the embodiment of the present application, and may correspond to the corresponding main body that executes the method shown in FIG. 4 according to the embodiment of the present application, and each module in the server
- the above-mentioned and other operations and/or functions are used to implement the corresponding procedures of each method in FIG. 4, and are not repeated here for brevity.
- the foregoing embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination.
- the above-mentioned embodiments may be implemented in the form of a computer program product in whole or in part.
- the computer program product includes one or more computer instructions.
- the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
- the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium.
- the computer instructions may be transmitted from a website, computer, server, or data center.
- the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more sets of available media.
- the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium.
- the semiconductor medium may be a solid state drive (SSD).
- the disclosed system, device, and method may be implemented in other ways.
- the device embodiments described above are only illustrative.
- the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
- the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
- the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
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Abstract
一种时间同步的方法和服务器,BMC可以先获取第一时间,然后,将获取的第一时间存储至CPLD的时间寄存器;CPLD可以基于第一时间,启动计时并记录计时结果,当计时结果达到预设阈值时,CPLD根据第一时间和计时结果确定第二时间;并根据第二时间更新时间寄存器。CPLD中的时间寄存器记录的实时时间可以提供给服务器的其他组件,保证服务器中各个组件的正常运转,能够在服务器中的PCB上部署更多重要的组件,可以提高服务器性能,有效减少服务器硬件成本。
Description
本申请涉及服务器技术领域,尤其涉及一种时间同步的方法和服务器。
每个服务器中的印制电路板(print circuit board,PCB)可设置一个或多个实时时钟(real-time clock,RTC)电路。RTC电路通过可编程逻辑器件(programmable logic device,PLD)与服务器中各个组件相连,通过PLD从RTC获取时间信息,再由PLD将时间信息共享给各个组件,以对各个组件提供时间信息。其中,组件如基板管理控制器(baseboard management controller,BMC)、中央处理器(central processing unit,CPU)等。在服务器长时间未上电的情况下,RTC电路仍可以提供实时时间,若服务器重新上电,RTC电路可以将实时时间提供给服务器的各个组件,以保证服务器的各个组件可以基于获取的实时时间实现业务对接、日志记录等功能。但传统服务器中RTC电路均会占用PCB较大的面积,影响了PCB中组件的布局,无法在同一PCB所提供的有限空间中增加其他重要组件的数量,导致服务器的处理能力受限,当需要满足较高业务需求时,只能通过增加服务器的数量满足其要求,增大了服务器硬件成本。
发明内容
本申请提供一种时间同步的方法和服务器,用以减少服务器中PCB上的RTC电路的占用面积,降低服务器成本。
第一方面,本申请提供了一种时间同步的方法,该方法可以应用于服务器,该服务器中可以不设置RTC电路,服务器包括BMC和CPLD,BMC与CPLD相连,该方法包括:BMC可以先获取第一时间,之后,将获取的第一时间存储至CPLD的时间寄存器中;时间寄存器中存储的时间可以实时更新,以存储实时时间;第一时间为BMC获取第一时间操作的时刻;CPLD可以基于第一时间,启动计时并记录计时结果,当计时结果达到预设阈值时,CPLD根据第一时间和计时结果确定第二时间;并根据第二时间更新时间寄存器。
通过上述方法,服务器中的BMC获取第一时间,并将获取的第一时间保存在CPLD中,且由于CPLD具有计时功能,CPLD中的时间寄存器可以记录实时时间,以便CPLD中的时间寄存器记录的实时时间可以提供给服务器的其他组件,保证服务器中各个组件的正常运转,这样,服务器中不需要部署RTC电路,能够在服务器中的PCB上部署更多重要的组件,可以提高服务器性能,有效减少服务器硬件成本。
在一种可能的设计中,BMC与CPLD可以通过第一接口通信,BMC将获取的第一时间存储至CPLD的时间寄存器时,可以通过第一接口将第一时间存储至CPLD的时间寄存器。
通过上述方法,CPLD中设置有与BMC连接的第一接口,使得BMC可以较快速、便捷的将第一时间更新至时间寄存器。
在一种可能的设计中,处理器与CPLD可以通过第二接口通信,处理器可以通过第二接口从时间寄存器读取第二时间;处理器基于第二时间,启动计时并记录实时时间。
通过上述方法,处理器可以从CPLD获取第二时间,并启动计时,以执行一些需要实时时间做参考的操作,如业务对接、日志记录等,能够使得处理器可以在正常运转。
在一种可能的设计中,CPLD计时的方式不同,计时结果也不同;例如,CPLD可以通过记录时间值的方式计时,这种方式下,CPLD的计时结果可以是时间值,相应的,预设阈值指示CPLD的更新时间寄存器的时间间隔;这样CPLD在每个时间间隔后,对时间寄存器中存储的时间进行更新,使得时间寄存器记录的时间与NTP服务器的时间保证一致。
又例如,CPLD可以记录计数次数,通过计数次数计时,这种方式下,CPLD的计时结果为计数次数,相应的,预设阈值指示CPLD的最大计数次数。这样CPLD在每当计数次数达到最大计数次数时,对时间寄存器中存储的时间进行更新,同样可以使得时间寄存器记录的时间与NTP服务器的时间保证一致。
在一种可能的设计中,CPLD在根据第一时间和计时结果确定第二时间,可以采用累加的方式,确定第二时间;示例性的,CPLD可以根据第一时间和计时结果的累加结果,确定第二时间。
通过上述方法,CPLD通过采用累加的方式确定第二时间,第二时间可以较为精确的反映为当前时刻的时间。
在一种可能的设计中,BMC在获取第一时间时,可以从NTP服务器获取第一时间,也可以从已时间校准的服务器获取第一时间。
通过上述方法,BMC获取的第一时间较为精确,保证后续CPLD可以通过计时确定的第二时间能够与NTP服务器的实时时间保持一致。
在一种可能的设计中,处理器还可以从服务器中的存储介质中获取用户配置数据,基于用户配置数据进行启动,该存储介质可以是非易失性存储介质,也可以是有供电电源供电、服务器掉电情况下数据不丢失的存储介质。
通过上述方法,在服务器不部署RTC电路的情况下,处理器仍可以获取用户配置数据,使得处理器可以正常运行。
第二方面,本申请提供了一种时间同步的装置,该装置具有实现第一方面及第一方面任意一种可能的设计中BMC、处理器以及CPLD所实现的功能。功能可以通过硬件实现,也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块。在一个可能的设计中,装置的结构中包括管理单元、计时单元以及处理单元,计时单元还包括存储单元,这些单元可以执行上述第一方面示例中的BMC、处理器以及CPLD相应功能,具体参见第一方面示例中的详细描述,此处不做赘述。
第三方面,本申请还提供了一种服务器,有益效果可以参见第一方面及第一方面任意一种可能的设计的描述此处不再赘述。服务器的结构中包括基板管理控制器、复 杂可编程逻辑器件、处理器、以及内存,处理器被配置为支持处理器执行上述第一方面及第一方面任意一种可能的设计的处理器中相应的功能,内存与处理器耦合,其保存必要的程序指令和数据。基板管理控制器被配置为支持基板管理控制器执行上述第一方面及第一方面任意一种可能的设计的基板管理控制器中相应的功能;复杂可编程逻辑器件被配置为支持复杂可编程逻辑器件执行上述第一方面及第一方面任意一种可能的设计的复杂可编程逻辑器件中相应的功能;通信接口用于与其他设备进行通信。
第四方面,本申请还提供一种计算机可读存储介质,计算机可读存储介质中存储有指令,当其在计算机上运行时,使得计算机执行上述各方面的BMC、处理器以及CPLD执行的方法。
第五方面,本申请还提供一种包含指令的计算机程序产品,当其在计算机上运行时,使得计算机执行上述各方面的BMC、处理器以及CPLD执行的方法。
第六方面,本申请还提供一种计算机芯片,芯片与存储器相连,芯片用于读取并执行存储器中存储的软件程序,执行上述各方面的BMC、处理器以及CPLD执行的方法。
图1为本申请提供的一种服务器的示意图;
图2为本申请提供的一种***的架构示意图;
图3为本申请提供的一种服务器启动的三阶段的示意图;
图4为本申请提供的一种时间同步的方法示意图;
图5为本申请提供的一种时间同步的装置结构示意图;
图6为本申请提供的一种服务器的结构示意图。
本申请为了降低服务器成本,在服务器中不再部署RTC电路,而是由服务器中的BMC从外部的服务器获取时间(如本申请实施例中的T0),将获取的时间存储在复杂可编程逻辑器件(complex programmable logic device,CPLD)中,便于后续处理器从CPLD中获取时间使得处理器可以基于获取的时间进行一系列上电之后的启动操作。
下面结合附图介绍对本申请实施例所适用的服务器以及***的架构进行说明。
图1为本申请实施例提供的时间同步***的示意图,如图1所示,该***包括服务器100和网络时间协议(network time protocol,NTP)服务器200。可选地,该***中还包括服务器300。NTP服务器200和服务器300可以用于为服务器100提供时间同步信息,如提供实时时间。
如图1所示为,服务器100中包括BMC110、处理器120和复杂可编程逻辑器件(complex programmable logic device,CPLD)130。
BMC110与处理器120之间通过CPLD130相连。在本申请实施例中,CPLD130中可以包括时间寄存器1301,该时间寄存器1301可以用于存储当前的实时时间;如本申请实施例中的时间T0以及更新的T1等。CPLD130还具备计时功能,可以基于BMC110发送的时间T0计时,获得当前的实时时间,并对时间寄存器1301中存储的 时间进行更新。
BMC110用于实现服务器中各个组件进行监控和管理。例如,BMC110可以监控服务器100中组件的(如处理器120、服务器100中存储介质等)温度、电压;还可以控制服务器110中风扇的转速。
BMC110也可以具备计时功能,例如BMC110中可以包括时钟电路,该时钟电路可以用于计时。
需要说明的是,图1中仅示例性的绘制出了服务器100中的一个处理器120。本申请实施例并不限定服务器100中包括的处理器120的数量,当服务器100中存在多个处理器120时,BMC110可以与每个处理器120之间通过一个CPLD130相连,换句话说,BMC110与每个处理器120之间设置一个CPLD130;BMC110可以将获取的时间更新至每个CPLD130中的时间寄存器1301,处理器120从相连的CPLD130的时间寄存器1301中获取实时时间。作为一种可能的实施方式,BMC110也可以通过一个CPLD130与多个处理器120中的部分处理器120相连,也就是说,多个的处理器120可以与一个CPLD130连接;BMC110可以将获取的时间更新至与其相连的各个CPLD130中的时间寄存器1301,处理器120从相连的CPLD130的时间寄存器1301中获取实时时间。
可选的,当服务器100中存在多个处理器120时,BMC110可以与其中一个处理器120(为方便说明该处理器可以称为第一处理器)之间通过CPLD130相连,多个处理器120中除第一处理器外的其余处理器(为方便说明该其余处理器可以称为第二处理器)可以与第一处理器连接。第二处理器可以作为第一处理器的协处理器,与第一处理器配合执行一些操作;第二处理器也可以是与第一处理器具备相同功能的处理器,本申请实施例并不限定第二处理器的类型以及功能。
BMC110可以将获取的时间更新至CPLD130中的时间寄存器1301,第一处理器从相连的CPLD130的时间寄存器1301中获取实时时间。第二处理器可以从相连的第一处理器中获取实时时间;在上述说明中,以一个第一处理器为例进行说明,本申请实施例并不限定第一处理器的数量,BMC110可以与多个第一处理器之间通过CPLD130相连,其余处理器可以连接在多个第一处理器中的任一第一处理器,以获取实时时间。
如图1所示,所述CPLD130中除包括时间寄存器1301,还包括计数器1302以及BMC接口1303以及处理器接口1304。
BMC110可以将获取的时间T0通过BMC接口1303存储在时间寄存器1301中;计数器1302可以从时间寄存器1301中获取时间T0并启动计时,还可以对时间寄存器1301进行更新,随着时间的推进,时间寄存器1301中存储的时间不断的更新,可以始终记录当前时刻的实时时间;处理器120可以通过处理器接口1304从时间寄存器1301中读取当前时刻的实时时间(如时间T1)。
本申请实施例并不限定计数器1302计时的方式,例如,计数器1302中可以包括时钟电路,计数器1302可以基于T0,利用时钟电路进行计时。
可选地,计数器1302也可以基于时钟电路,产生固定周期的脉冲信号S1(如固定周期为1秒);然后,计数器1302利用脉冲信号S1计时,计时的起始值为T0,计 数器1302每产生一个脉冲信号S1,对T0累加1,进行计时。
本申请实施例中也不限定计数器1302更新时间寄存器1301的方式,例如可以按照预设的时间间隔进行更新,也可以按照预设的最大计数次数进行更新,具体可以参见下文中的说明。
值得说明的是,***架构中CPLD除了实现计时器1302和时间寄存器1301的功能外,还可以用于服务器中其他计算或存储功能,本申请对此并不做限制。
图2为本申请实施例提供的另一种***架构示意图,如图2所示,该***中包括一个管理器400、多个服务器100,每个服务器100中的结构与如图2所示的服务器100类似,此处不再赘述。
在如图3所示的***中,管理器400可以连接多个服务器100,对多个服务器100进行管理控制,例如,管理器400可以统计与管理器400连接的服务器100的数量以及每个服务器100的类型、位置等,还可以从服务器100中的BMC110中获取服务器100中一些组件的信息等。本申请实施例并不限定管理器400与每个服务器100的连接方式,例如管理器400可以与服务器100通过有线方式连接,也可以通过网络(如以太网等无线网络)方式连接。
本申请实施例不限定管理器400的具体形态,可以是服务器,也可以是芯片,也可以是其他类型的模块等。
在本申请实施例中,管理器400可以与***之外的服务器通信,该服务器可以是NTP服务器200,也可以是其他时间已校准的服务器300;示例性的,管理器400可以直接与***之外的服务器进行通信,也可以通过交换机与***之外的服务器进行通信。例如,管理器400可以从***之外的服务器获取时间T0,并将时间T0通知给与管理器400连接的服务器100,如可以将时间T0发送给服务器100中的BMC110。
本申请实施例并不限定图2所示的***的具体形态,如图2所示的***可以是刀片式服务器,管理器400为刀片式服务器中的管理器,服务100可以为刀片式服务器中的服务器;如图2所示的***也可以是机柜式服务器集群,管理器400为机柜式服务器集群中的管理板,服务器100为机柜式服务器集群中的任一服务器。
首先,对服务器100启动的各个阶段进行说明。图3为本申请实施例提供的服务器100启动过程的描述,如图3所示,服务器100的启动过程可以分为三个阶段,服务器100内电源供电方式可以划分为两个域:主电(main)和备电(standby)。服务器100接入电源后,服务器100中的各个组件按照预置顺序上电。首先,备电先对服务器100中的BMC110供电(第一阶段);然后,BMC110可以发送控制命令,该控制命令用于控制主电给处理器120供电;处理器120上电后,处理器120开始启动,首先启动基本输入输出***(basic input output system,BIOS),该过程对应第二阶段;最后,启动操作***(operating system,OS),该过程对应第三阶段。
接下来,进一步介绍各个阶段的上电过程:
第一阶段,BMC110启动。
BMC110上电之后,对BMC110的功能进行初始化,例如BMC110可以完成与BMC接口1303初始化,初始化操作包括加载接口的驱动程序,连接CPLD130。当BMC110初始化完成,可以控制服务器100进入第二阶段;BMC110可以通过发送控 制指令的方式控制主电给处理器120供电,进入第二阶段。
第二阶段,BIOS启动。
处理器120上电之后,可以加载BIOS,读取服务器100的***配置信息,基于***配置信息对处理器120的底层硬件的进行配置,执行引导记录(Boot Record)中的引导程序(Boot),完成OS启动的引导动作,之后进入下一个阶段。
第三阶段,OS启动。
进入第三阶段,处理器120加载OS内核,进行初始化,打通OS与处理器120底层硬件之间的连接。
在第三阶段中,处理器120可以与外部服务器进行通信,如可以从NTP服务器获取较为精准的实时时间,处理器120从NTP服务器获取实时时间后,以该实时时间为基础,进行计时。
下面以图1所示的时间同步***为例,结合图4对本申请实施例提供的时间同步的方法进行说明,如图4所示,该方法包括:
步骤401:在服务器100启动的第一阶段,BMC110上电之后,与其他服务器进行时间同步,获取时间T0。
其他服务器可以是NTP服务器200,也可以是其他时间已校准的服务器300。
BMC110上电之后,可以与NTP服务器200进行时间同步,若BMC110与NTP服务器200连接中断或NTP服务器故障,导致BMC110无法从NTP服务器200获取当前时刻的时间,BMC110可以与图1所示的时间同步***中其他服务器通信,以获取当前时刻的时间T0。时间T0是指BMC110在执行获取时间T0的操作时的时刻,时间T0可以具体指示年份、月份、日期、时、分、或秒等信息。其中,上述其他服务器可以是时间已校准的服务器300。
步骤402:BMC110将时间T0写入CPLD130的时间寄存器1301。
BMC110可以通过BMC接口1303将时间T0写入CPLD130的时间寄存器1301。
步骤403:CPLD130中计数器1302可以基于时间T0开始计时,并记录计时结果,并根据时间T0和计时结果更新时间寄存器1301。
计数器1302会一直计时,并持续更新时间寄存器1301(也就是说计数器1302会持续更新时间寄存器1301中存储的时间),使寄存器中存储的时间为当前时刻的时间,使得服务器100与NTP服务器200记录的时间保持一致。
计数器1302在更新时间寄存器1301中存储的时间时,可以设置预设阈值,当计时结果达到预设阈值时,计数器1302更新时间寄存器1301中存储的时间;对于计数器1302计时的方式不同,记录的计时结果也不同,例如计数器1302可以采用累加时间值的方式进行计时,也可以记录计数次数,通过累加计数次数和计数间隔的乘积的方式进行计时,也可以采用其他方式,本申请实施例并不限定,对于不同的计时方式,计数器1302在更新寄存器中存储的时间有所不同,下面列举其中两种:
方式一、计数器1302可以按照预设的时间间隔对时间寄存器1301进行更新。
当计数器1302的计时结果为时间值,例如计时结果可以是计数器1302获取时间T0后所经过的时长,当该时长达到预设的时间间隔时,可以将时间T0累加该时长产生的时间值,作为时间T1更新至时间寄存器1301。
示例性的,若T0为9:00,时间间隔为5秒;计数器1302在从时间寄存器1301获取T0后开始计时,当根据计数器1302的时钟电路或脉冲信号记录的时长达到5秒时,可以将9:00累加5秒,获得9:05,将9:05更新至时间寄存器1301;后续采用相似的方式对时间寄存器1301进行更新,例如,计数器1302在从时间寄存器1301获取时间9:05后开始计时,如可以根据计数器1302的时钟电路或脉冲信号S1记录的时长达到5秒时,可以当将9:05累加5秒,获得的9:10,将9:10更新至时间寄存器1301。采用上述方式计数器1302可以对时间寄存器1301中存储的时间进行更新,时间寄存器1301中存储的时间可以为当前时刻的实时时间。
方式二、计数器1302可以按照预设的最大计数次数对时间寄存器1301进行更新。
当计数器1302的计时结果为计数次数,例如计时结果可以是计数器1302获取时间T0后的计数次数,如以每秒计时一次为例,计数结果可以为5次,表征计数器1302获取时间T0后计数了五次,指示计数器1302获取时间T0后所经过的时长为5*1秒,当该计数次数达到预设的最大计数次数时,可以将时间T0累加该时长产生的时间值,作为时间T1更新至时间寄存器1301。
示例性的,若T0为9:00,最大计数次数为5次,计数器1302的计数频率为每秒一次;计数器1302在从时间寄存器1301获取T0后开始计时,如可以根据计数器1302的时钟电路或脉冲信号进行计数,计数次数达到5次时,可以将9:00累加5*1秒,获得的9:05,将9:05更新至时间寄存器1301;后续采用相似的方式对时间寄存器1301进行更新,例如,计数器1302在从时间寄存器1301获取时间9:05后开始计时,如可以根据计数器1302的时钟电路或脉冲信号S1进行计数,计数次数达到5次时,可以将9:05累加5*1秒,获得9:10,将9:10更新在时间寄存器1301。采用上述方式计数器1302可以对时间寄存器1301中存储的时间进行更新,这样,时间寄存器1301中存储的时间为当前时刻的实时时间。
方式二中,计数器1302确定计时结果达到预设的最大计数次数的方式本申请实施例并不限定,例如,计数器1302可以记录计数次数,每计数一次,则增加一次,通过比较记录的计数次数与最大计数次数确定计数结果是否达到预设的最大计数次数;又例如,计数器1302可以维持计数值,该计数值初始设定的值为最大计数次数,计数器1302每计数一次,可以对该计数值减一,当该计数值减为零,则确定计数结果达到预设的最大计数次数。
需要说明的是,BMC110获取时间T0,并将时间T0写入时间寄存器1301的过程中,需要消耗一段时长,也就是说,BMC110将时间T0写入时间寄存器1301的当前时刻并不是时间T0,而是时间T0之后的一个时刻;为了保证时间寄存器1301能够更加精确的记录当前时刻的实时时间,计数器1302可以在从获取时间T0后,可以在时间T0的基础上增加设时长△T1,也就是说计数器1302在获取时间T0首次更新时间寄存器1301时,可以在时间T0与计时结果的累加结果的基础上,增加时长△T1,生成时间T1,写入时间寄存器1301,时长△T1可以是预估的BMC110获取时间T0,并将时间T0写入时间寄存器1301的时长,也可以为一个经验数值。可选的,计数器1302在首次更新时间寄存器1301后,在后续每次更新时间寄存器1301时,也可以在从时间寄存器1301获取的时间与计时结果的累加结果的基础上增加时长△T2,将增加了时 长△T2的累加结果更新至时间寄存器1301,时长△T2可以是预估的计数器1302从时间寄存器1301中获取时间的时长,也可以为一个经验数值。
在一种可能的实施方式中,BMC110获取时间T0后,也可以利用BMC110中的时钟电路进行计时,记录计时结果,该计时结果为BMC110记录的实时时间,BMC110基于T0计时的方式可以参见计数器1301的计时方式,此处不再赘述,BMC110可以每隔一段时间,利用BMC110记录的计时结果对CPLD130中的时间寄存器1301中存储的时间进行更新,CPLD130中计数器1302再基于BMC110更新后的时间进行计时。以此保证CPLD130中存储的时间可以与BMC110的记录的时间保持一致,提高CPLD130中存储的时间的精确程度。
需要说明的是,BMC110每隔一段时间,利用BMC110记录的计时结果对CPLD130中的时间寄存器1301存储的时间进行更新;为了保证时间寄存器1301能够更加精确的记录当前时刻的实时时间,计数器1302可以在BMC110更新时间寄存器1301存储的时间后,获取时间寄存器1301存储的时间T2,在获取的时间T2的基础上增加时长△T3,也就是说计数器1302在BMC110更新时间寄存器1301存储的时间后首次更新时间寄存器1301时,可以在获取的时间T2与计时结果的累加结果的基础上,增加时长△T3,生成当前的实时时间T3,写入时间寄存器1301,时长△T3可以是预估的BMC110将时间写入到时间寄存器1301的所需时长,也可以为一个经验数值。
本申请实施例并不限定时长△T1、时长△T2以及时长△T3的具体数值,时长△T1、时长△T2以及时长△T3可以相同,也可以不同。
步骤404:在服务器100启动的第二阶段,处理器120上电,处理器120可以通过处理器接口1304从CPLD130(如CPLD130中的时间寄存器1301)中读取时间,该时间为当前时刻CPLD130存储的时间。
在本申请实施例中以处理器120从CPLD130读取时间时,当前CPLD130中的时间寄存器1301存储的时间为T1为例进行说明,T1指示处理器120可以从CPLD130读取时间时,CPLD130最近更新的时间。
由于处理器120上电之后,可以从CPLD130读取时间T1,后续BMC110可以不再更新CPLD130存储的时间。示例性的,BMC110可以在发送控制指令,控制主电给处理器120供电后,不再更新CPLD130中存储的时间。
CPLD130也可以在处理器120获取时间T1后,不再计时,停止更新时间寄存器1301。
步骤405:处理器120获取时间T1后,基于时间T1进行计时,记录实时时间,并基于记录的实时时间,进行数据同步、日志记录等操作。
在服务器100启动的第三阶段,处理器120可以与NTP服务器200或时间已校准的服务器300进行通信,获取实时时间,对当前处理器120保存的计时结果进行更新。
作为一个可能的实施例,如图4所示的实施例也可应用于如图2所示的***架构,区别在于,在步骤401中,BMC110需要从管理器400中获取时间T0,而管理器400可以从***外的服务器(如NTP服务器200或时间已校准的服务器300)获取时间T0。这样,可以使得在多服务器场景下,每个服务器中也不需要设置RTC电路,也可以保证能够进行时间同步,获取实时时间,可以有效减小服务器中RTC电路占用的PCB 的面积,降低服务器硬件成本,服务器的PCB上可以设置更多组件,有益于提高服务器性能。
另外,传统时间同步***中,RTC电路包括RTC芯片以及供电电源,RTC电路中的供电电源可以为RTC芯片供电,与处理器相连的RTC供电电源还用于对处理器中平台控制单元(platform controller hub,PCH)供电,用于保证服务器断电时,PCH中保存的数据不丢失,PCH用于存储用户配置数据,如用户配置数据为处理器120启动(如第二阶段、第三阶段)所需的信息。示例性的,这些用户配置数据包括但不限于处理器的高速串行计算机扩展总线标准(peripheral component interconnect express,PCIe)端口带宽设置、OS启动区设置(如硬盘启动、光驱启动)。当利用本申请的技术方案取消RTC电路时,需要考虑如何保存原PCH中存储的用户配置数据在服务器断电的情况下,用户配置数据不丢失。作为一个可能的实施例,可以将这些用户配置数据保存在服务器100中的存储介质中,该存储介质可以是非易失性存储介质,例如存储介质可以是BIOS闪存(Flash),也可以其他有供电电源维持的、服务器100掉电数据不丢失的存储介质,当进入服务器100启动的第二阶段处理器120可以从该存储介质读取这些用户配置数据。保证在服务器100不设置PTC电路的情况下,服务器100中的处理器120仍可以获取用户配置数据,能够正常启动,保证了服务器的正常性能。
作为一种可能的实施例,除了本申请实施例提供的图1和图2所示的***架构外,本申请的发明还可以利用在其他***架构中,该扩展的***架构可以利用除CPLD以外的其他组件或逻辑电路实现下述方法中CPLD的功能,例如,服务器中存在一个逻辑电路,该逻辑电路可以与BMC和处理器进行通信,并基于获取的时间T0确认并记录当前时刻的时间T1,相应地,处理器可以通过该逻辑电路获取时间T1,并基于该时间T1计算当前时刻的时间,以实现OS启动过程中日志等信息的配置。
上文中结合图1至图4,详细描述了根据本申请实施例所提供的时间同步的方法,下面将结合图5和图6,进一步描述本申请实施例所提供的时间同步的装置和服务器。
图5为本申请实施例提供的一种时间同步装置,如图所示,该装置包括管理单元510、计时单元520以及处理单元530,计时单元520中包括存储单元521,存储单元521用于存储当前时刻的时间;
管理单元510,用于将获取的第一时间存储至存储单元521,第一时间用于指示获取第一时间操作的时刻;管理单元510可以用于执行如图4所示的实施例中的步骤401。
计时单元520,用于启动计时并记录计时结果;当计时结果达到预设阈值时,根据第一时间和计时结果确定第二时间;根据第二时间更新存储单元521。管理单元510可以用于执行如图4所示的实施例中的步骤402~403。
可选的,管理单元510与计时单元520可以通过第一接口通信;管理单元510在将获取的第一时间存储至存储单元521时可以通过第一接口将第一时间存储至存储单元521。
可选的,装置还包括处理单元530,处理单元530与计时单元520可以通过第二接口通信:
处理单元530可以通过第二接口从存储单元521读取第二时间,基于第二时间,启动计时并记录实时时间。处理单元530可以用于执行如图4所示的实施例中的步骤404~405。
可选的,计时单元520的计时方式不同,计时结果也不同,下面列举其中两种:
方式一、计时单元520采用累加时间值的方式进行计时,这种方式下,计时结果为时间值,预设阈值指示计时单元520的更新存储单元521的时间间隔。
方式二、计时单元520记录计数次数,通过累加计数次数与计数间隔的乘积的方式进行计时,这种方式下,计时结果为计数次数,预设阈值指示计时单元520的最大计数次数。
可选的,计时单元520在根据第一时间和计时结果确定第二时间时,可根据第一时间和计时结果的累加结果,确定第二时间。
可选的,管理单元510在获取第一时间时,可以从NTP服务器获取第一时间,也可以从时间已校准的服务器获取第一时间。
应理解的是,本申请实施例的时间同步装置可以通过专用集成电路(application-specific integrated circuit,ASIC)实现,或可编程逻辑器件(programmable logic device,PLD)实现,上述PLD可以是复杂程序逻辑器件(complex programmable logical device,CPLD),现场可编程门阵列(field-programmable gate array,FPGA),通用阵列逻辑(generic array logic,GAL)或其任意组合。也可以通过软件实现图4所示的时间同步方法时,时间同步装置及其各个模块也可以为软件模块。
根据本申请实施例的时间同步装置可对应于执行本发明实施例中描述的方法,并且时间同步装置中的各个单元的上述和其它操作和/或功能分别为了实现图4中的各个方法的相应流程,为了简洁,在此不再赘述。
图6为本申请实施例提供的一种服务器结构示意图,如图所示,服务器600包括BMC610、处理器620,以及CPLD630。
可选的,服务器600还可以包括内存640、通信接口650、存储介质660。
BMC610、处理器620、CPLD630、通信接口650、存储介质660通过总线670连接。
处理器620可以是中央处埋器(central processing unit,CPU)、专用集成电路(application specific integrated circuit,ASIC)、现场可编程门阵列(field programmable gate array,FPGA)、人工智能(artificial intelligence,AI)芯片、片上***(system on chip,SoC)或复杂可编程逻辑器件(complex programmable logic device,CPLD),图形处理器(graphics processing unit,GPU),本申请对于处理器的类型和数量并不限定。
内存640,用于存储计算机程序指令,可以是易失性存储器,例如随机存取存储器;也可以是非易失性存储器,例如只读存储器,闪存,硬盘(hard disk drive,HDD)或固态硬盘(solid-state drive,SSD)等。
在本申请实施例中,存储介质660,也称为外存,可以用于存储服务器运行所需要的数据,该存储介质可以是非易失性存储器,例如磁性介质(例如,软盘、硬盘、磁带)、光介质(例如光盘)、或者半导体介质(例如固态硬盘)等。
总线670除包括数据总线之外,还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见,在图中将各种总线都标为总线670。
作为一种可能的实施例,CPLD630也可以通过其他类型的内部总线实现BMC610和处理器620的连接,其中,内部总线包括链路控制协议(link control protocol,LCP)、局部总线local Bus、I2C总线(inter-integrated circuit)或串行外设接口(serial peripheral interface,SPI)总线连接。
在如图6所示的服务器600中,也可以设置独立的数据收发模块,例如通信接口650,用于收发数据;BMC610或处理器620在与其他设备进行通信时,可以通过通信接口650进行数据传输,如在本申请实施例中,BMC610可以通过通信接口650从NTP服务器200或时间已校准的服务器300获取第一时间。
当所述服务器采用图6所示的形式时,图6中的处理器620可以调用内存640中的计算机程序指令执行如图4中处理器120执行的方法;BMC610执行如图4中BMC110执行的方法。CPLD630可以执行如图4中CPLD130执行的方法。
具体的,内存640中存储有用于实现图5中的处理单元的功能的计算机执行指令,图5中的处理单元的功能/实现过程均可以通过图6中的处理器620调用内存640中存储的计算机执行指令来实现。
应理解,根据本申请实施例的服务器可对应于本申请实施例中的时间同步装置,并可以对应于执行根据本申请实施例图4所示的方法中的相应主体,并且服务器中的各个模块的上述和其它操作和/或功能分别为了实现图4中的各个方法的相应流程,为了简洁,在此不再赘述。
上述实施例,可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时,上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时,全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中,或者从一个计算机可读存储介质向另一个计算机可读存储介质传输,例如,所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如,软盘、硬盘、磁带)、光介质(例如,DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state drive,SSD)。
在本申请所提供的几个实施例中,应该理解到,所揭露的***、装置和方法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个***,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
以上所述,仅为本发明的具体实施方式。熟悉本技术领域的技术人员根据本发明提供的具体实施方式,可想到变化或替换,都应涵盖在本发明的保护范围之内。
Claims (12)
- 一种时间同步的方法,其特征在于,所述方法包括:基板管理控制器BMC将获取的第一时间存储至复杂可编程逻辑电路CPLD的时间寄存器;所述时间寄存器用于存储当前时刻的时间;所述第一时间用于指示获取所述第一时间操作的时刻;所述BMC与所述CPLD相连;所述CPLD启动计时并记录计时结果,当所述计时结果达到预设阈值时,所述CPLD根据所述第一时间和所述计时结果确定第二时间;所述CPLD根据所述第二时间更新所述时间寄存器。
- 如权利要求1所述的方法,其特征在于,所述BMC与所述CPLD相连,包括:所述BMC与所述CPLD通过第一接口通信;则所述BMC将获取的第一时间存储至CPLD的时间寄存器,包括:所述BMC通过所述第一接口将所述第一时间存储至所述CPLD的时间寄存器。
- 如权利要求1所述的方法,其特征在于,处理器与所述CPLD通过第二接口通信,所述方法还包括:所述处理器通过所述第二接口从所述时间寄存器读取所述第二时间;所述处理器基于所述第二时间,启动计时并记录实时时间。
- 如权利要求1所述的方法,其特征在于,所述计时结果为时间值,所述预设阈值指示所述CPLD的更新所述时间寄存器的时间间隔;或所述计时结果为计数次数,所述预设阈值指示所述CPLD的最大计数次数。
- 如权利要求4所述的方法,其特征在于,所述CPLD根据所述第一时间和计时结果确定第二时间,包括:所述CPLD根据所述第一时间和计时结果的累加结果,确定所述第二时间。
- 如权利要求1所述的方法,其特征在于,所述BMC获取第一时间,包括:所述BMC从网络时间协议NTP服务器或已完成时间校准的其他服务器获取所述第一时间。
- 一种服务器,其特征在于,所述服务器包括基板管理控制器BMC和复杂可编程逻辑电路CPLD,所述BMC与所述CPLD相连,所述CPLD包括时间寄存器,所述时间寄存器用于存储当前时刻的时间;所述BMC,用于将获取的第一时间存储至所述时间寄存器,所述第一时间用于指示获取所述第一时间操作的时刻;所述CPLD,用于启动计时并记录计时结果;当所述计时结果达到预设阈值时,根据所述第一时间和所述计时结果确定第二时间;根据所述第二时间更新所述时间寄存器。
- 如权利要求7所述的服务器,其特征在于,所述BMC与所述CPLD通过第一接口通信;所述BMC,还用于通过所述第一接口将所述第一时间存储至所述时间寄存器。
- 如权利要求7所述的服务器,其特征在于,所述服务器还包括处理器,所述处理器与所述CPLD通过第二接口通信;所述处理器,用于通过第二接口从所述时间寄存器读取所述第二时间,基于所述 第二时间,启动计时并记录实时时间。
- 如权利要求7所述的服务器,其特征在于,所述计时结果为时间值,所述预设阈值指示所述CPLD的更新所述时间寄存器的时间间隔;或所述计时结果为计数次数,所述预设阈值指示所述CPLD的最大计数次数。
- 如权利要求10所述的服务器,其特征在于,所述CPLD,还用于根据所述第一时间和计时结果的累加结果,确定所述第二时间。
- 如权利要求7所述的服务器,其特征在于,所述BMC,还用于从网络时间协议NTP服务器或已时间校准的服务器获取所述第一时间。
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