WO2020243883A1 - 像素电路、像素电路的驱动方法、显示装置及其驱动方法 - Google Patents
像素电路、像素电路的驱动方法、显示装置及其驱动方法 Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Definitions
- the present disclosure relates to the field of display technology, and more specifically to a pixel circuit, a driving method of the pixel circuit, a display device, and a driving method of the display device.
- the pixel circuits of current Organic Light-Emitting Diode (OLED) display devices usually consist of multiple low-temperature Polysilicon thin film transistor (LTPS TFT), which receives reset control signal Reset, data control signal Gate_N, Gate_P, light emission control signal EM and other control signals to control the working state of the pixel circuit, so as to realize the display device Features.
- LTPS TFT Low-temperature Polysilicon thin film transistor
- the circuit is controlled by multiple control signals and has a relatively complicated control sequence.
- Multiple groups generally at least three groups or more
- array substrate row driver circuits Gate Driver on Array, GOA
- GOA Gate Driver on Array
- the present disclosure provides a pixel circuit, a driving method of the pixel circuit, a display device, and a driving method of the display device.
- the pixel circuit provided by the present disclosure can effectively reduce the number of control signals, simplify the structure of the pixel circuit, reduce the volume of the pixel circuit, and save power consumption on the basis of realizing the basic functions of the display device.
- a pixel circuit which receives three control signals: a reset control signal, a scan control signal, and a light emission control signal.
- the pixel circuit includes: a reset unit, a voltage writing unit, and a light emission control unit , Wherein the reset unit is connected to the reset control signal terminal and is configured to receive the reset control signal from the reset control signal terminal, and reset the pixel circuit under the control of the reset control signal; the voltage writing unit is connected to the data line,
- the scanning control signal line is configured to receive a scanning control signal from the scanning control signal line, and under the control of the scanning control signal, the data signal of the data line and the threshold voltage of the driving transistor are stored in the pixel circuit;
- a light emission control unit It is connected to the light emission control signal terminal and includes the drive transistor, and is configured to receive a light emission control signal from the light emission control signal terminal, and under the control of the light emission control signal, utilize the data signal stored in the pixel circuit and the drive transistor The threshold voltage of, generates a current
- the reset unit includes: a first reset transistor, the gate of which is connected to the reset control signal terminal, the first terminal is connected to the first reference voltage terminal, and the second terminal is connected to the second node; A transistor whose gate is connected to the reset control signal terminal, the first terminal is connected to the first node, and the second terminal is connected to the second reference voltage terminal; the third reset transistor has its gate connected to the reset control signal terminal, and the first terminal Is connected to the second reference voltage terminal, and the second terminal is connected to at least one light-emitting device; wherein the reset unit is configured to reset the first node and the second node under the control of the reset control signal .
- the first reference voltage terminal is a reference voltage terminal, a power supply voltage terminal, or a data line.
- the voltage writing unit includes: an input transistor, the gate of which is connected to the scan control signal line, the first end is connected to the second node, and the second end is connected to the data line; and the first compensation transistor The gate is connected to the scan control signal line, the first end is connected to the first node, and the second end is connected to the second end of the driving transistor in the light emission control unit; the compensation capacitor, the first end of which is connected to the second node, and the second Terminal is connected to the first node; wherein, the voltage writing unit is configured to write the data signal of the data line into the second node under the control of the scan control signal, and the voltage is between the first node and the second node The data signal and the threshold voltage of the driving transistor are stored in between.
- the light emission control unit includes: a driving transistor whose gate is connected to the first node and the first terminal is connected to the power supply voltage terminal; the first light-emitting transistor whose gate is connected to the light emission control signal terminal; One end is connected to the reference voltage terminal, the second end is connected to the second node; the light emission control transistor, the gate of which is connected to the light emission control signal terminal, the first end is connected to the second end of the driving transistor, and the second end is connected to at least one light emitting Device; wherein the light-emitting control unit is configured to generate a current for driving the light-emitting device to emit light by using the data signal stored between the first node and the second node and the threshold voltage of the driving transistor under the control of the light-emitting control signal.
- the first reset transistor, the second reset transistor, the third reset transistor, the input transistor and the first compensation transistor are all N-type oxide thin film transistors
- the driving transistor, the first light-emitting transistor and the light-emitting control transistor are all P-type low temperature polysilicon thin film transistor.
- a display device which includes a pixel circuit array, a first array substrate row driving circuit, and a second array substrate row driving circuit.
- the pixel circuit array includes a plurality of pixels as described above.
- the first array substrate row drive circuit and the second array substrate row drive circuit provide three control signals to each pixel circuit in the pixel circuit array: reset control signal, scan control signal, and light emission control signal.
- the array substrate row drive circuit is used to provide reset control signals and scan control signals to the pixel circuit; the second array substrate row drive circuit is used to provide light emission control signals to the pixel circuit.
- the start time of the reset control signal and the scan control signal are different, and the duration is the same; the start time of the reset control signal and the light-emitting control signal are the same, and the duration of the light-emitting control signal is longer than the duration of the reset control signal .
- the first array substrate row drive circuit and the second array substrate row drive circuit are the same array substrate row drive circuit, and the first array substrate row drive circuit and the second array substrate row drive circuit both receive: A power signal, a second power signal, and a clock signal.
- each of the first array substrate row drive circuit and the second array substrate row drive circuit includes a plurality of array substrate row drive units cascaded, wherein the first power supply of all the array substrate row drive units The second power terminal of all array substrate row driving units receives the second power signal; the signal output terminal of each level of array substrate row driving unit is connected to the next level of array substrate row driver adjacent to it.
- the first input terminal of the unit; the second input terminal of each level of array substrate row drive unit is connected to the pull-up input node of its adjacent next level of array substrate row drive unit; the first input of each level of array substrate row drive unit
- the first clock signal of a clock terminal is the same as the second clock signal of the second clock terminal of the row drive unit of the next stage array substrate;
- the first clock signals of the first clock terminals of the row driving units of the adjacent next-level array substrates are the same.
- each of the plurality of array substrate row driving units includes: an input module, a pull-up control module, a pull-up module, a pull-down control module, and a pull-down module, wherein the input module is connected to the second The power supply terminal, the second clock terminal, and the first input terminal are configured to generate and output a first control signal according to the first input signal of the first input terminal when the second clock signal of the second clock terminal is at an effective level, and according to the The second power signal of the two power terminals generates and outputs the second control signal; the pull-up control module is connected to the input module, the first power terminal and the first clock terminal, and has a first control input node and a second control input node, Is configured to write the first control signal and the second control signal received from the input module into the first control input node and the second control input node, respectively, and the first control input node is at an invalid level and the second control input node When the first clock signal of the first clock terminal and the first clock terminal are both at an
- the pull-down module includes: a pull-down transistor, the gate of which is connected to the pull-down input node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the second power terminal; the tenth transistor has its gate Connected to the second input terminal, the first terminal is connected to the signal output terminal; the fourth capacitor, the first terminal of which is connected to the second terminal of the tenth transistor, and the second terminal is connected to the pull-down input node.
- a method of driving the display device as described above wherein for each array substrate row driving unit: an invalid level is applied to a first input terminal, and an invalid level is applied to a first clock terminal.
- Level apply an effective level to the second clock terminal to generate a first control signal at an invalid level and a second control signal at an effective level; apply an effective level to the first clock terminal, according to the first control Signal and the second control signal to generate a pull-up control signal, and based on the pull-up control signal, write the first power signal of the first power terminal into the signal output terminal; to the first input terminal, the second input terminal, and the second input terminal.
- the clock terminal applies an effective level to generate a first control signal at the effective level, generates a pull-down control signal according to the first control signal, and based on the pull-down control signal, writes the second power signal of the second power terminal into the signal output end.
- a method for driving the aforementioned pixel circuit includes: applying an effective level to a reset control signal terminal to reset the pixel circuit; applying an effective level to a scan control signal line,
- the pixel circuit stores the data signal and the threshold voltage of the drive transistor; and applies an effective level to the light emission control signal terminal, and drives the light emitting device to emit light by using the data signal and the threshold voltage of the drive transistor stored in the pixel circuit.
- FIG. 1A shows a schematic diagram of a pixel circuit 100 according to an embodiment of the present disclosure
- FIG. 1B shows a circuit structure diagram of a pixel circuit 100 according to an embodiment of the present disclosure
- FIG. 1C shows a circuit structure diagram of a variation of the pixel circuit 100 according to an embodiment of the present disclosure
- FIG. 1D shows a circuit structure diagram of another variation of the pixel circuit 100 according to an embodiment of the present disclosure
- FIG. 2A shows a flowchart of a driving method 200 of a pixel circuit according to an embodiment of the present disclosure
- FIG. 2B shows a working timing diagram of a pixel circuit according to an embodiment of the present disclosure
- FIG. 3A shows a circuit diagram of a row driving unit of an array substrate according to an embodiment of the present disclosure
- FIG. 3B shows a timing diagram of the row driving unit of the array substrate according to an embodiment of the present disclosure
- 3C shows a waveform diagram of the output signal OUT in the pull-down stage when the row driving unit of the array substrate according to an embodiment of the present disclosure is not provided with the capacitor C 4 and the transistor M 10 ;
- FIG. 4A shows a schematic diagram of a display device 300 according to an embodiment of the present disclosure
- FIG. 4B shows a circuit structure diagram of a display device 300 according to an embodiment of the present disclosure
- FIG. 5A shows a flowchart of a method 500 for driving row driving units of an array substrate according to an embodiment of the present disclosure
- Fig. 5B shows a working sequence diagram of the first-stage GOA unit, the second-stage GOA unit, and the first-stage GOA unit of the second array substrate row driving circuit in the first array substrate row driving circuit according to an embodiment of the present disclosure.
- any number of different modules may be used and run on the user terminal and/or server.
- the modules are merely illustrative, and different modules may be used for different aspects of the system and method.
- a flowchart is used in this application to illustrate the operations performed by the system according to the embodiments of the application. It should be understood that the preceding or following operations are not necessarily performed exactly in order. On the contrary, the various steps can be processed in reverse order or simultaneously as required. At the same time, you can also add other operations to these processes, or remove a step or several operations from these processes.
- FIG. 1A shows a schematic diagram of a pixel circuit 100 according to an embodiment of the present disclosure.
- the pixel circuit 100 receives three control signals: a reset control signal Reset, a scan control signal Gate, and an emission control signal EM.
- the pixel circuit 100 includes a reset unit 110, a voltage writing unit 120, and an emission control unit 130.
- the reset unit 110 is connected to the reset control signal terminal, and is configured to receive the reset control signal Reset from the reset control signal terminal, and reset the pixel circuit under the control of the reset control signal Reset.
- the voltage writing unit 120 is connected to the data line and the scan control signal line, and is configured to receive the scan control signal Gate from the scan control signal line, and store the data in the pixel circuit under the control of the scan control signal Gate.
- the signal Vdata and the threshold voltage Vth of the driving transistor are connected to the data line and the scan control signal line, and is configured to receive the scan control signal Gate from the scan control signal line, and store the data in the pixel circuit under the control of the scan control signal Gate.
- the signal Vdata and the threshold voltage Vth of the driving transistor are configured to receive the scan control signal Gate from the scan control signal line, and store the data in the pixel circuit under the control of the scan control signal Gate.
- the light emission control unit 130 is connected to the light emission control signal terminal and includes the drive transistor, and the light emission control unit is configured to receive the light emission control signal EM from the light emission control signal terminal, and under the control of the light emission control signal EM, use the The data signal Vdata stored in the pixel circuit and the threshold voltage Vth of the driving transistor generate a current that drives the light-emitting device to emit light.
- the data signal Vdata may be, for example, a high-level signal, or it may also be a low-level signal, and the embodiments of the present disclosure are not limited by the specific level of the data signal set.
- the light emission control unit includes a first type transistor
- the reset unit and voltage writing unit include a second type transistor different from the first type transistor
- the different types of the transistors are intended to characterize the different driving modes of the transistors.
- the first type transistor is an N type transistor and the second type transistor is a P type transistor; or the first type transistor is a P type transistor and the second type transistor is an N type transistor.
- the embodiments of the present disclosure are not limited by the specific types of selected first type transistors and second type transistors.
- first type transistor and the second type transistor described in this application are only used to distinguish different types of transistors, and are not intended to limit the types of transistors.
- the transistors included in the light-emitting control unit in the pixel circuit and the transistors included in the reset unit and the voltage writing unit are of different types, so that the pixel circuit is controlled only by fewer control signals. It can realize its basic functions. Accordingly, on the basis of realizing the basic functions of the pixel circuit (reset, voltage writing, driving the light emitting device to emit light), it is helpful to reduce the volume of the pixel circuit.
- FIG. 1B shows a circuit structure diagram of a pixel circuit 100 according to an embodiment of the present disclosure. 1B, each component unit of the above-mentioned pixel circuit can be described in more detail.
- the reset unit 110 includes a first reset transistor T 2 , a second reset transistor T 4 , and a third reset transistor T 6 .
- the gate of the first reset transistor T 2 is connected to the reset control signal terminal, the first terminal is connected to the first reference voltage terminal, and the second terminal is connected to the second node N 2 for the reset control signal at the reset control signal terminal Under the control of Reset, the first reference voltage of the first reference voltage terminal is written into the second node N 2 .
- the gate of the second reset transistor T 4 is connected to the reset control signal terminal, the first terminal is connected to the first node N 1 , and the second terminal is connected to the second reference voltage terminal for the reset control signal at the reset control signal terminal Under the control of Reset, the second reference voltage of the second reference voltage terminal is written into the first node N 1 .
- the third reset gate of the transistor T 6 is connected to the reset control signal terminal, the first terminal is connected to a second reference voltage terminal, a second terminal connected to the at least one light emitting device, the reset control signal for the reset control signal Reset terminal Under control, the second reference voltage of the second reference voltage terminal is written into the anode of the light emitting device.
- the reset unit 110 is configured to reset the first node N 1 , the second node N 2 and the anode of the light emitting device under the control of the reset control signal Reset.
- the first reference voltage of the first reference voltage terminal and the second reference voltage of the second reference voltage terminal may be set to the same voltage signal according to circuit logic requirements; or may also be different voltage signals, such as the first reference voltage.
- the reference voltage is a high-level voltage signal
- the second reference voltage is a low-level voltage signal.
- the embodiments of the present disclosure are not affected by the specific voltage values of the first reference voltage and the second reference voltage and their relationship. .
- FIG. 1C shows a circuit structure diagram of a variation of the pixel circuit 100 according to an embodiment of the present disclosure
- FIG. 1D shows a circuit structure diagram of another variation of the pixel circuit 100 according to an embodiment of the present disclosure.
- the first reference voltage terminal may be, for example, a reference voltage terminal, a power supply voltage terminal, or a data line.
- the power supply voltage Vdd or the data signal Vdata is output as the first reference voltage, or it can also be connected to a preset voltage terminal outside the pixel circuit for transmitting the preset voltage signal.
- the embodiment of the present disclosure is not limited by the specific type of the first reference voltage terminal.
- the second reference voltage terminal may also be a preset voltage terminal outside the pixel circuit for outputting a preset voltage signal.
- the embodiment of the present disclosure is not limited by the specific type of the second reference voltage terminal.
- the pixel circuit By setting the first reset transistor T 2 , the second reset transistor T 4 , and the third reset transistor T 6 , when the reset control signal is received at the reset control signal terminal, the pixel circuit connects the second node N 2 , the first node N 1 , The anodes of the light emitting device are respectively reset to: the first reference voltage, the second reference voltage, and the second reference voltage.
- the voltage writing unit 120 includes an input transistor T 3 , a first compensation transistor T 5 and a compensation capacitor C 1 .
- the input gate of the transistor T 3 is connected to the scan control signal line, a first terminal connected to the second node N 2, a second terminal connected to a data line, a scan control signal under the control of the data line Gate
- the data signal Vdata is written into the second node N 2 .
- the gate of the first compensation transistor T 5 is connected to the scan control signal line, a first terminal connected to the first node N 1, a second terminal connected to a second terminal of the light emitting control driving unit D of the transistor T, which was to the scan control signal under the control of the driving transistor Gate T D and a second end connected to the first node N 1, so as to reflect the driving transistor T D is a threshold voltage of the first node is written N 1.
- the first end of the compensation capacitor C 1 is connected to the second node N 2 , and the second end is connected to the first node N 1 .
- the voltage writing unit 120 is configured to write the data signal Vdata of the data line to the second node N 2 under the control of the scan control signal Gate, and to write the data signal Vdata of the data line in the first node N 1 and the second node N 2 stores the data signal Vdata and the threshold voltage Vth of the driving transistor.
- the voltage writing unit 120 can write the data signal Vdata of the data line to the second node N 2 in response to the scan control signal Gate, the first node and the second node N 1 - N threshold voltage Vth storing the data signal Vdata and the driving transistor 2 between.
- the light emission control unit 130 includes a driving transistor T D , a first light emission transistor T 1 and a light emission control transistor T 7 .
- the gate of the driving transistor T D is connected to the first node N 1 , and the first terminal is connected to the power supply voltage terminal, which is controlled by the voltage at the first node N 1 to be in an on or off state.
- the gate of the first light-emitting transistor T 1 is connected to the light-emitting control signal terminal, the first terminal is connected to the reference voltage terminal, and the second terminal is connected to the second node N 2 , which is used for the light-emitting control signal EM at the light-emitting control signal terminal.
- the reference voltage Vref at the reference voltage terminal is written into the second node N 2 .
- the emission control signal is connected to a terminal of the light emission control gate of the transistor T 7, the first end of the driving transistor T D is connected to a second end connected to the at least one light emitting device, a light emission control signal terminal of the control signal EM under the control of the light emission current of the driving transistor T D is generated based on the driving device emits light.
- the light emission control unit 130 is configured to use the data signal Vdata stored between the first node N 1 and the second node N 2 and the threshold voltage Vth of the driving transistor to generate driving under the control of the light emission control signal EM.
- the current that a light-emitting device emits light is configured to use the data signal Vdata stored between the first node N 1 and the second node N 2 and the threshold voltage Vth of the driving transistor to generate driving under the control of the light emission control signal EM.
- the reference voltage Vref of the reference voltage terminal may be, for example, a high level or a low level.
- the embodiments of the present disclosure are not limited by the specific value of the reference voltage Vref.
- the light emitting control unit can respond to the control of the light emitting control signal EM and utilize the storage between the first node N 1 and the second node N 2
- the data signal and the threshold voltage of the driving transistor generate a current that drives the light-emitting device to emit light.
- the first reset transistor T 2 , the second reset transistor T 4 , the third reset transistor T 6 , the input transistor T 3 and the first compensation transistor T 5 are all N-type oxide thin film transistors.
- the transistor T D , the first light emitting transistor T 1 and the light emitting control transistor T 7 are all P-type low temperature polysilicon thin film transistors.
- the effective levels of the scan control signal Gate and the reset control signal Reset of the pixel circuit are both high-level signals Therefore, it is possible to reduce the number of array substrate row driving circuits for generating the above-mentioned control signals. At the same time, there are fewer low-temperature polysilicon thin film transistors in the circuit, which is beneficial to reduce its power consumption.
- a method 200 for driving a pixel circuit as described above is provided.
- FIG. 2A shows a flowchart of a driving method 200 of a pixel circuit according to an embodiment of the present disclosure
- FIG. 2B shows a working timing diagram of a pixel circuit according to an embodiment of the present disclosure. 2A and 2B, the pixel driving method 200 can be described in more detail.
- an effective level is applied to the reset control signal terminal to reset the pixel circuit.
- the applied effective level may be, for example, a high-level signal, or it may also be a low-level signal, and the embodiments of the present disclosure are not limited by the specific level set.
- the reference voltage Vref is at a high level
- the second reference voltage Vinit is at a low level.
- the transistors T 2 , T 4 , and T 6 in the pixel circuit are turned on, and other transistors are turned off. This process resets the level of the first node N 1 to the potential of the second reference voltage Vinit, which is a low level.
- the potential of the second node N 2 is reset to the potential of the reference voltage Vref, the anode of the light emitting device OLED is reset to the potential of the second reference voltage Vinit.
- the pixel circuit is initialized.
- step S202 an effective level is applied to the scan control signal line, and the data signal Vdata of the data line and the threshold voltage Vth of the driving transistor are stored in the pixel circuit.
- the pixel circuit described in FIG. 1B Take the pixel circuit described in FIG. 1B as an example.
- the signal applied by the reset signal terminal changes to a low level signal
- the scanning signal line changes to apply a high level signal
- the light emission control signal terminal Continue to apply a high level signal.
- the pixel circuit of the transistor T 2, T 4 is turned off, the transistors T 3 and T 5 is turned on, the gate of the driving transistor T D is set in the previous stage due to the low level and turned on, the driving transistor T D Vdd by N 1 starts charging the first node, the first node N 1 until the capacitor is charged to Vdd-Vth, where Vth represents the threshold voltage of the driving transistor T D.
- the potential of the second end of the compensation capacitor C 1 is Vdd-Vth.
- the first terminal of the compensation capacitor C 1 is connected to the second node N 2. Since the second node N 2 is connected to the data line through the input transistor M 5 , the potential of the first terminal of the compensation capacitor C 1 is the second node N 2 potential, which is the data signal Vdata, the compensation capacitor C 1 to the voltage difference across Vdd-Vth-Vdata, the phase of the charging phase of the pixel circuit, a data signal is written to the pixel circuit stage.
- step S203 an effective level is applied to the light emitting control signal terminal, and the data signal Vdata stored in the pixel circuit and the threshold voltage Vth of the driving transistor are used to drive the light emitting device to emit light.
- the driving current I OLED generated by the driving transistor T D can be expressed by the following formula:
- V GS is the voltage between the gate and drain of the transistor.
- the driving current I OLED has not driven the threshold voltage Vth of the transistor T D, the only relevant data signal Vdata to the data line access.
- the influence of the driving transistor T D since the operation process recipe and prolonged resulting threshold voltage Vth shift driving current I OLED of the driving transistor T D output can ensure the uniformity of the light emitting display, improve the display quality.
- the driving control of the pixel circuit By setting the pixel circuit driving method, it is possible to realize the driving control of the pixel circuit with fewer control signals (for example, only the reset control signal Reset, the scanning control signal Gate, and the light emission control signal EM) can be used to achieve the corresponding driving control.
- the function of the control signal is small and the logic is simple, which is conducive to the realization of fast and efficient control process.
- FIG. 3A shows a circuit diagram of a row driving unit of an array substrate according to an embodiment of the present disclosure.
- the array substrate row driving unit includes: an input module, a pull-up control module, a pull-up module, a pull-down control module, and a pull-down module.
- the input module is connected to the second power terminal, the second clock terminal, and the first input terminal, and is configured to generate the signal according to the first input signal STV1 of the first input terminal when the second clock signal K2 of the second clock terminal is at an effective level And output the first control signal S C1 , and generate and output the second control signal S C2 according to the second power signal of the second power terminal.
- the pull-up control module is connected to the input module, the first power terminal, and the first clock terminal, and has a first control input node P 1 and a second control input node P 2 , which is configured to receive the first control input from the input module.
- a control signal S C1 and a second control signal S C2 are written into the first control input node P 1 and the second control input node P 2 respectively , and the first control input node P 1 is at an inactive level and the second control input node a case where P 2 and the first clock terminal K1 of the first clock signal are at active level, generates and outputs a control signal pull-on Ip.
- the pull-up module is connected to the pull-up control module, the first power terminal, and the signal output terminal, and has a pull-up input node P 3 , and the pull-up module is configured to pull up under the control of the pull-up control signal Ip input node P 3 at the active level to the first power supply terminal a first signal output terminal of the write signal.
- the pull-down control module is connected to the input module, the first clock terminal and has a pull-down control input node P 4 , and is configured to make the pull-down control input node P 4 at an effective level and output under the control of the first control signal S C1 Pull down the control signal Id.
- the pull-down module is connected to the pull-down control module, the second power terminal, the second input terminal, and the signal output terminal, and has a pull-down input node P 5 , and the pull-down module is configured to be under the control of the pull-down control signal Id,
- the pull-down input node P 5 is made to be at an effective level to write the second power signal of the second power terminal into the signal output terminal.
- the pull-down module includes a pull-down transistor M 9 , a tenth transistor M 10 , and a fourth capacitor C 4 .
- the gate of the pull-down transistor M 9 is connected to the pull-down input node P 5 , the first end is connected to the signal output end, and the second end is connected to the second power supply end, for when the pull-down input node P 5 is at a valid level, The second power signal of the second power terminal is written into the signal output terminal.
- the gate of the tenth transistor M 10 is connected to the second input terminal, a first terminal connected to the signal output terminal, a second input terminal which is controlled by the second input signal STV2 in the ON state or OFF state.
- the first terminal of the fourth capacitor C 4 is connected to the second terminal of the tenth transistor M 10 , and the second terminal is connected to the pull-down input node P 5 .
- the above valid level and invalid level are only used to distinguish the different level states of the signal, for example, the valid level is a high level and the invalid level is a low level; or the valid level can also be a low level.
- Level, the invalid level is a high level, and the embodiments of the present disclosure are not limited by the specific level signals of the valid level and the invalid level.
- the input module includes: a first transistor M 1 , a second transistor M 2 and a third transistor M 3 .
- the gate of the first transistor M 1 is connected to the second clock terminal, the first terminal is connected to the first control input node P 1 , and the second terminal is connected to the first input terminal for the second clock terminal.
- the first control signal S C1 is generated based on the first input signal STV1 of the first input terminal.
- the gate of the second transistor M 2 is connected to the first control input node P 1 , the first terminal is connected to the second control input node P 2 , and the second terminal is connected to the second clock terminal.
- the gate of the third transistor M 3 is connected to the second clock terminal, the first terminal is connected to the second control input node P 2 , and the second terminal is connected to the second power terminal for the second clock at the second clock terminal Under the control of the signal K2, the second control signal S C2 is generated based on the second power signal of the second power terminal.
- the pull-up control module includes a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 and a third capacitor C 3 .
- M gate of the fourth transistor 4 is connected to the control input of the second node P 2, a first end connected to the fifth transistor. 5 M second end, a second end connected to the first clock terminal.
- the gate of the fifth transistor M 5 is connected to the first clock terminal, a first terminal connected to the pull-input node P 3.
- the gate of the sixth transistor M 6 is connected to the first control input node P 1 , the first terminal is connected to the first power terminal, and the second terminal is connected to the pull-up input node P 3 .
- the first terminal of the third capacitor C 3 is connected to the first terminal of the fourth transistor M 4 , and the second terminal is connected to the second control input node P 2 .
- the pull-up module includes a first capacitor C 1 and an eighth transistor M 8 .
- the first terminal of the first capacitor C 1 is connected to the first power terminal, and the second terminal is connected to the pull-up input node P 3 .
- a gate of the eighth transistor M 8 is connected to an input node of the pull-up P 3, a first terminal connected to the first power supply terminal, a second terminal connected to the signal output terminal.
- the pull-down control module includes a seventh transistor M 7 and a second capacitor C 2 .
- the gate of the seventh transistor M 7 is connected to the pull-down control input node P 4 , and the second terminal is connected to the first clock terminal.
- the first terminal of the second capacitor C 2 is connected to the pull-down control input node P 4 , and the second terminal is connected to the first terminal of the seventh transistor M 7 .
- FIG. 3B further shows a timing diagram of the row driving unit of the array substrate according to an embodiment of the present disclosure.
- the first power signal of the first power terminal is, for example, a high-level signal VGH
- the second power signal of the second power terminal is a low-level signal VGL
- the second clock signal, the first input signal, and the second input signal all take the low level as the effective level, and assume that the threshold voltage of each transistor here is all Vth.
- the first working stage s 1 when the first clock signal K1 at the first clock terminal is high, the first input signal STV1 at the first input terminal jumps to high level, and the second clock at the second clock terminal K2 signals go low, then transistor M 1 is turned on, the first control signal S C1 according to the first high-level input signal STV1, and writes the first control signal S C1 of the first control input node P 1 turns off the transistors M 2 , M 6 , and M 7 .
- Level of the second clock signal K2 of the transistor M 3 is turned on, a low level of the second control signal S C2, the potential of the second control input node P 2 is pulled down to VGL + Vth, the transistor M 4 is turned on, the high-level first clock signal K1 is transmitted to the first terminal of the fourth transistor M 4, both ends of the capacitor C 3 is the potential difference VGH-VGL-Vth.
- the output signal OUT is at a low level
- the pull-up input node P 3 is at a high level.
- the first clock signal K1 at the first clock terminal jumps to low level
- the second clock signal K2 at the second clock terminal jumps to high level
- the The first input signal STV1 maintains a high level. Since a potential has been stored in the capacitor C 3 in the first stage, when the first clock signal K1 jumps to the low level VGL, the stored potential of the capacitor C 3 cannot change suddenly, and the level of the second control input node P 2 will be changed. For the capacitance to 2VGL-VGH + 2Vth, so that the transistor M 4 open well, a first clock signal K1 low transmission loss without the threshold to a first terminal of the fourth transistor M 4.
- a first clock signal K1 transistor M 5 is turned on, the pull-up control signal Ip is generated, the potential of the node P 3 pull VGL input pulled low, transistor M 8 is turned on, the output signal OUT is pulled to the first power supply terminal High level signal VGH.
- the first clock signal K1 at the first clock terminal jumps to high level
- the second clock signal K2 at the second clock terminal jumps to low level
- the first the input signal is still high STV1, STV2 second input signal is low
- the transistor M 10 is turned on
- the capacitor C is 4 into the circuit
- a first terminal of the capacitor C 4 at this time a high level VGH
- the capacitor C 4 is connected to the second end of the pull-down an input node P 5
- a high level VGH through the pull-down transistor M9 charge the input node P 5
- the pull-down an input node P 5 is charged to a VGH-Vth, at both ends of the capacitor C 4
- the voltage difference is Vth.
- the first clock signal K1 at the first clock terminal is high
- the second clock signal K2 at the second clock terminal is low
- the first input signal STV1 is low level VGL.
- the transistor M 1 is turned on, the first control signal is at a low level S C1, so that the pull-down control input node P 4 is low, and thus the output pull-down control signal Id so that the pull-down to a low level input node P 5,
- the transistor M 9 is turned on, the output signal OUT of the signal output terminal will be pulled low, and the pull-up input node P 3 will jump to a high level.
- FIG. 3C shows a waveform diagram of the output signal OUT in the pull-down stage when the row driving unit of the array substrate according to an embodiment of the present disclosure is not provided with the capacitor C4 and the transistor M10.
- the second end of the first clock signal is set to a high level VGH, then this When the capacitor C 2 has a negative potential VGL+Vth-VGH at both ends. Subsequently, when the first clock signal of a low level VGL jump K1, a second capacitor C 2 becomes a terminal voltage VGL + Vth. Since the voltage of the capacitor C 2 cannot change suddenly, the potential of the pull-down input node P 5 then jumps to a lower potential 2VGL+2Vth-VGH. At this time, the transistor M 9 is fully turned on and the output signal OUT at the signal output terminal is Pull down to VGL, therefore, the waveform of the output signal OUT will show a stepped falling edge.
- the transistor M 9 is turned on more fully, and finally the potential of the pull-down input node P 5 will be VGL-Vth, so that the low-level signal VGL of the second power supply terminal can be transmitted to the signal output terminal without threshold loss, So that the waveform of the output signal appears as a falling edge without steps.
- the first input signal STV1 is always low level
- the second input signal STV2 is high level
- the capacitor C 4 is no longer connected to the circuit, so that the signal output terminal The output signal OUT can be well maintained at a low level.
- the array substrate row driving unit described in the present application is not limited to the above-mentioned work flow.
- it may not include a high-level sustaining stage, or it may not include a low-level sustaining stage, as long as it can realize the preset signal output function.
- the array substrate row driving unit By providing the array substrate row driving unit described above, and further, by providing the fourth capacitor C 4 and the tenth transistor M 10 in the pull-down module, the array substrate row driving unit can generate the control signals described in this application, and The array substrate row driving unit can form a stepless falling edge from high level to low level in the pull-down stage, which is beneficial to the output of effective control signals and avoids control logic errors caused by the stepped falling edge of the output.
- a display device 300 is provided, and FIG. 4A shows a schematic diagram of the display device 300.
- the display device 300 includes a pixel circuit array 330, a first array substrate row driving circuit 310, and a second array substrate row driving circuit 320.
- the pixel circuit array 330 includes a plurality of pixel circuits 100 as described above, and the first array substrate row drive circuit 310 and the second array substrate row drive circuit 320 provide three pixel circuits 100 in the pixel circuit array 330.
- Two control signals reset control signal Reset, scan control signal Gate and light emission control signal EM.
- the first array substrate row drive circuit 310 that is, a gate drive circuit, is used to provide a reset control signal Reset and a scan control signal Gate to the pixel circuit;
- the second array substrate row drive circuit 320 that is, a light emission control drive The circuit is used to provide the emission control signal EM to the pixel circuit.
- the second array substrate row driving circuit 320 is used to provide a reset control signal Reset and a scan control signal Gate to the pixel circuit; the first array substrate row The driving circuit 310 is used to provide a light emission control signal EM to the pixel circuit.
- the first array substrate row driving circuit 310 and the second array substrate row driving circuit 320 can provide a reset control signal Reset, a scan control signal Gate, and light emission for each pixel circuit in the pixel circuit array 330.
- the control signal EM realizes good sequential logic control of the pixel circuit and completes the corresponding display device function.
- the structure of the display device is simpler and has a smaller volume, it is beneficial to realize a narrow frame design.
- the first array substrate row driving circuit 310 and the second array substrate row driving circuit 320 generate a reset control signal Reset, a scan control signal Gate, and a light emission control signal EM as shown in FIG. 2B.
- the reset control signal Reset and the scan control signal Gate have a different start time and the same duration.
- the reset control signal Reset has the same start time as the light emission control signal EM, and the duration of the light emission control signal EM is longer than the duration of the reset control signal Reset.
- the duration of the light emission control signal EM is twice or more than the duration of the reset control signal Reset.
- the relationship and its duration are conducive to achieving good control of the pixel circuit and avoiding incorrect display of the display device due to the chaotic logic of the control signal sequence.
- the first array substrate row drive circuit and the second array substrate row drive circuit are the same array substrate row drive circuit, and the first array substrate row drive circuit and the second array substrate row
- the driving circuits all receive: a first power signal, a second power signal, and a clock signal.
- the first array substrate row drive circuit and the second array substrate row drive circuit are the same array substrate row drive circuit, which means that the first array substrate row drive circuit and the second array substrate row drive circuit have the same circuit structure.
- the first power signal and the second power signal may be the same signal, for example, they are both high-level signals, or they may be different signals, for example, the first power signal is a high-level signal, and the second power signal
- the signal is a low-level signal, and the embodiments of the present disclosure are not limited by the specific signal content and relationship of the first power signal and the second power signal.
- the clock signal may further include a first clock signal and a second clock signal, for example.
- the embodiments of the present disclosure are not limited by the specific composition and signal content of the clock signal.
- the first array substrate row drive circuit and the second array substrate row drive circuit helps to simplify the design process of the array substrate row drive circuit;
- An array substrate row drive circuit and a second array substrate row drive circuit share the same signals (the first power signal, the second power signal, and the clock signal), which helps to realize the comparison between the first array substrate row drive circuit and the second array substrate
- the sequential logic control of the row driving circuit enables it to provide the pixel circuit with the reset control signal Reset, the scan control signal Gate, and the light emission control signal EM as described above.
- FIG. 4B shows a circuit structure diagram of a display device 300 according to an embodiment of the present disclosure.
- each of the first array substrate row driving circuit 310 and the second array substrate row driving circuit 320 includes a plurality of array substrate row driving units as described above in cascade, and Each array substrate row driving unit includes a first power terminal, a second power terminal, a first input terminal, a second input terminal, a signal output terminal Cout, and a pull-up input node P 3 .
- the signal output terminal Cout of each level of array substrate row driving unit is connected to the first input terminal of the next level array substrate row driving unit adjacent to it.
- the second input terminal of each level of array substrate row driving unit is connected to the pull-up input node P 3 of its adjacent next level array substrate row driving unit.
- the signal output terminal of the array substrate row driving unit of each level is connected to the reset control signal terminal of the corresponding pixel circuit of the same level, so as to transmit the signal to the pixel circuit.
- the pull-up input node P 3 of each level array substrate row drive unit is connected to it
- the second input terminal of the upper-level array substrate row driving unit provides a second input signal to the upper-level substrate row driving unit; in addition to the first-level array substrate row driving unit, the array substrate row driving unit of each level
- the signal output terminal is also connected to the scan signal control terminal of the pixel circuit of the same level corresponding to the row driving unit of the
- the signal output terminal of each level of the array substrate row driving unit is connected to the light emission control signal terminal of the corresponding pixel circuit of the same level to provide the light emission control signal to the pixel circuit EM;
- the signal output end of each level array substrate row drive unit is also connected to the first signal input end of the next level array substrate row drive unit adjacent to it to provide its an array substrate in a desired row driving unit operates a first input signal;
- an input node of the pull P 3 which is connected to an array of the array substrate on each of a row driving unit
- the second input terminal of the substrate row driving unit provides a second input signal to the upper substrate row driving unit.
- the first power terminal E 1 of all the array substrate row driving units receives the first power signal
- the second power terminal E 2 of all the array substrate row driving units receives the second power signal
- the first clock signal of the first clock terminal of the row drive unit of each level of array substrate is the same as the second clock signal of the second clock terminal of the next level array substrate row drive unit adjacent to it;
- the second clock signal of the second clock terminal is the same as the first clock signal of the first clock terminal of the row driving unit of the next stage array substrate adjacent to the second clock terminal.
- the first clock signal STVG1_K1 received by the first clock terminal I K1 of the first-level GOA unit STVG 1 is The clock signal CK1
- the second clock signal STVG1_K2 received by the second clock terminal I K2 is the clock signal CK2
- the first clock signal STVG2_K1 received by the first clock terminal I K1 is the clock signal CK2
- the second clock signal STVG2_K2 received by the second clock terminal I K2 is the clock signal CK1.
- the first-stage array substrate row drive unit STVG 1 and the second-stage array substrate row drive unit STVG 1 of the first array substrate row drive circuit in the display device are provided.
- the output signals of the first-stage array substrate row driving unit STVE 1 of the array substrate row driving circuit have a timing relationship as described below.
- the first-stage array substrate row driving unit STVG 1 of the first array substrate row driving circuit is in a valid working state
- the first-stage array substrate row driving unit STVE 1 of the second array substrate row driving circuit is in an invalid state.
- the signal output terminal of the first-stage array substrate row driving unit STVG 1 outputs an output signal Gout 1 with an effective level
- the signal output terminal of the first-stage array substrate row driving unit STVE 1 outputs an output with an invalid level Signal Eout 1 .
- the start time of the effective level of the output signal Gout 1 of the first-level array substrate row driving unit STVG 1 and the first-level array substrate row driving unit STVE of the second array substrate row driving circuit are set Eout an output signal of an inactive level is the same as a start time and duration of the output signal Gout active level 1 is smaller than the second row of the array substrate of the first substrate stage array row driving circuit of the driving unit STVE 1
- the duration of the inactive level of the output signal Eout 1 is greater than or equal to twice the duration of the active level of the output signal Gout 1 .
- the array substrate row drive unit at each level and the array substrate row drive unit at the next level sequentially
- the output signals of the corresponding level array substrate row driving units of the second-level array substrate row driving circuit are all at the invalid level.
- connection relationship and the timing relationship of the plurality of array substrate row driving units in each of the first array substrate row driving circuit 310 and the second array substrate row driving circuit 320 it is beneficial to achieve good output of control signals, thereby Ensure effective control of the pixel circuit.
- a method 500 for driving the display device as described above is also proposed.
- FIG. 5A shows a flowchart of a method 500 for driving array substrate row driving units according to an embodiment of the present disclosure.
- step S501 for each array substrate row driving unit of the first array substrate driving circuit and the second array substrate driving circuit in the display device, first, in step S501, an invalid level is applied to the first input terminal , Applying an invalid level to the first clock terminal, and applying an active level to the second clock terminal, to generate a first control signal S C1 at an invalid level and a second control signal S C2 at an active level.
- step S502 an effective level is applied to the first clock terminal, and a pull-up control signal Ip is generated according to the first control signal S C1 and the second control signal S C2 , based on the pull-up control signal Ip , Write the first power signal of the first power terminal into the signal output terminal.
- step S503 an effective level is applied to the first input terminal, the second input terminal, and the second clock terminal to generate the first control signal S C1 at the effective level, and generate the first control signal S C1 according to the first control signal S C1
- the pull-down control signal Id based on the pull-down control signal Id, writes the second power signal of the second power terminal into the signal output terminal.
- the first substrate row driving unit and the second substrate row driving unit can be driven to generate reset control signals, scan control signals, and light emission control signals for pixel circuits, so as to realize the corresponding functions of the display device.
- FIG. 5B shows the first-stage GOA unit STVG 1 of the first array substrate row driving circuit 310, the second-stage GOA unit STVG 2 and the first-stage GOA unit of the second array substrate row driving circuit 320 according to an embodiment of the present disclosure STVE 1 working sequence diagram.
- the first power signal is a high-level signal VGH
- the second power signal is a low-level signal VGL
- the clock signal CK1 and the clock signal CK2 have the same clock period Tm
- the clock signal CK1 lags the clock signal CK2 by half a clock period Tm .
- the first stage GOA cell array substrate STVG first row driving circuit 310 to the first input terminal 1 is connected to a first initial signal STVG_Original, a first clock signal terminal for receiving a clock signal CK1, a second clock signal terminal for receiving a clock signal CK2,
- the invalid levels of the first initial signal STVG_Original, the clock signal CK1, and the clock signal CK2 are all high, and the duration of the invalid level of the first initial signal STVG_Original is half of the clock period Tm of the clock signal CK1.
- the first control signal, the second control signal, the pull-up control signal, and the pull-down control signal all adopt the low level as their effective level.
- the inactive level of the second initial signal STVE_Original is high, the start time of its inactive level is the same as the first initial signal STVG_Original, and the duration of its inactive level is equal to three times the duration of the inactive level of the first initial signal. Times, that is, 1.5 times the clock period Tm of the clock signal CK1.
- the specific working timing relationships of the first-stage GOA unit STVG 1 of the first array substrate row driving circuit 310, the second-stage GOA unit STVG 2 and the first-stage GOA unit STVE 1 of the second array substrate row driving circuit 320 are as follows :
- the first-stage GOA unit STVG 1 will be in an operating state, and the second-stage GOA unit STVG 2 and the first-stage GOA unit STVE 1 of the second array substrate row driving circuit 320 will be in an inoperative state. At this time, only the first-stage GOA unit STVG 1 generates an output signal at an effective level, that is, generates a reset control signal Reset, to reset the pixel circuit of the first row.
- step S501 the first input signal STVG1_STV1 of the first input terminal is set to high level, and the second clock signal STVG1_K2 received by the second clock terminal thereof is low level.
- the first clock signal STVG1_K1 received by the first clock terminal is high, then the first stage GOA unit STVG 1 enters the first working stage s 1 to generate the first control signal S C1 at high level and at low level a second level control signal S C2, the input node of the pull-up P 3 is the output signal of the signal output terminal Gout 1 high, STVG 1 is low.
- step S502 when the first clock signal STVG1_K1 received by its first clock terminal jumps to a low level, the first-stage GOA unit STVG 1 enters the second working stage s 2 , based on the high-level first clock signal A control signal S C1 and a second control signal S C2 at a low level generate a pull-up control signal Ip, which pulls the potential of the pull-up input node P3 to a low level and pulls the output signal Gout 1 high to the first power terminal. High level signal VGH.
- step S503 when the first stage unit STVG GOA first input signal 1 STVG_STV1, the second input signal STVG_STV2, a second clock terminal receiving a second clock signal of STVG1_K2 are low, then the second The first level GOA unit STVG 1 enters the fourth working stage s 4 , generates a low-level first control signal S C1 , and generates a pull-down control signal Id based on the first control signal S C1 , so that its signal output terminal will output no threshold VGL low signal losses, and the input node of the pull-up P 3 clock low.
- the first-stage GOA unit STVG 1 enters the fifth working stage s 5 .
- the output signal Gout 1 at the signal output terminal will always remain low.
- the output signal Gout 1 of the first-stage GOA unit STVG 1 signal output has the same pulse width as the first input signal STVG1_STV1 and its phase lags the first input signal STVG1_STV1 by half.
- the output signal Gout 1 is the reset control signal Reset of the pixel circuit of the first row.
- the second-stage GOA unit STVG 2 is in an operating state, and the first-stage GOA unit STVG 1 and the first-stage GOA unit STVE 1 of the second array substrate row driving circuit 320 are both in an inoperative state.
- the second-stage GOA unit STVG 2 generates an output signal at an effective level, that is, generates a scan control signal Gate to write the data signal Vdata of the data line and the threshold voltage of the driving transistor into the pixel circuit of the first row.
- the second stage unit GOA GOA STVG 2 will be the first stage output signal Gout of STVG unit 1 as a first input signal, and since the second stage GOA The first clock signal and the second clock signal of the unit STVG 2 and the first-level GOA unit STVG 1 are interchanged.
- the second-level GOA unit STVG 2 similarly, the second-level GOA unit STVG 2 will be in the first working stage s 2 , the second working stage s 2 , The fourth working stage s 4 and the fifth working stage s 5 , and due to the period setting of each signal shown in FIG.
- the output signal Gout 2 of the second signal output terminal is the same as the output signal of the first stage GOA unit STVG 1 Gout 1 has the same pulse width, and the output signal Gout 2 lags the output signal Gout 1 by half a clock period Tm.
- the first-stage GOA unit STVE 1 of the second array substrate row driving circuit 320 is in a working state, and the first-stage GOA unit STVG 1 and the second-stage GOA unit STVG 2 are both in an inoperative state.
- the first-stage GOA unit STVE 1 of the second array substrate row driving circuit 320 generates an output signal at an effective level, that is, generates a light-emission control signal EM to drive the pixel circuit of the first row using the storage in the pixel circuit.
- the data signal and the threshold voltage of the driving transistor generate a current that drives the light-emitting device to emit light.
- the first-stage GOA unit STVE 1 in FIG. 4B first, when the first clock signal STVE1_K1 received by it is at a high level and the second clock signal STVE1_K2 is at a low level, its first input terminal receives When the first input signal STVE1_STV1 is at a high level, it enters the first working stage s 1 , and the output signal Eout 1 of the signal output terminal of the first-stage GOA unit STVE 1 is at a low level.
- the first-stage GOA unit STVE 1 enters the second working stage s 2 , and its output signal Eout 1 will jump to high level, and then when the first clock signal STVE1_K1 When it jumps to a high level again, the output signal Eout 1 still maintains a high level.
- the first-stage GOA unit STVE 1 enters the third working stage s 3 , and its output signal Eout 1 remains at a high level. Thereafter, when its first clock signal STVE1_K1 jumps to a low level and When the second clock signal STVE1_K2 jumps to a high level, its output signal Eout 1 remains at a high level.
- the first-stage GOA unit STVE 1 enters the fourth working stage s 4 , and the output signal Eout 1 of its signal output terminal jumps to a low level.
- the first stage GOA unit STVE 1 enters the fifth working stage s 5 , No matter how the levels of the first clock signal STVE1_K1 and the second clock signal STVE1_K1 change, the output signal Eout 1 at the signal output terminal will always remain low.
- the output signal Eout 1 of the STVE 1 signal output terminal of the first-stage GOA unit will present the waveform as shown in FIG. 5B, and the output signal Eout 1 and the first input signal STVE1_STV1 of the first input terminal have the same pulse width.
- the first input signal STVE1_STV1 by half a clock period Tm, that is, it is the same as the start time of the output signal Gout 1 of the first stage GOA unit STVG 1 of the first array substrate row driving circuit 310, and the pulse width is Gout 1. Three times the pulse width.
- the first-stage GOA unit STVG 1 , the second-stage GOA unit STVG 2 and the first-stage GOA unit STVE 1 of the second array substrate row driving circuit 320 will be in the working state sequentially, thereby generating The reset control signal Reset, the scan control signal Gate, and the light emission control signal EM at the effective level realize effective control of the pixel circuits of the first row.
- the output signal of the previous-stage GOA unit signal output terminal can be used as the corresponding The reset signal of the pixel circuit, where the output signal of the signal output terminal of the GOA unit of the subsequent stage is used as the Gate signal of the same pixel circuit.
- the output signal of its signal output terminal is used as the corresponding pixel circuit of the same level.
- the EM signal and the first array substrate row driving unit of the same level cooperate to realize the aforementioned working process.
- first/second embodiment means a certain feature, structure, or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that “an embodiment” or “an embodiment” or “an alternative embodiment” mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. . In addition, some features, structures, or characteristics in one or more embodiments of the present application can be appropriately combined.
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Abstract
Description
Claims (14)
- 一种像素电路,其接收三个控制信号:复位控制信号、扫描控制信号及发光控制信号,所述像素电路包括:复位单元、电压写入单元和发光控制单元,其中,复位单元连接至复位控制信号端,被配置为从复位控制信号端接收复位控制信号,在复位控制信号的控制下,对所述像素电路进行复位;电压写入单元连接至数据线、扫描控制信号线,被配置为从扫描控制信号线接收扫描控制信号,在扫描控制信号的控制下,在所述像素电路中存储所述数据线的数据信号及驱动晶体管的阈值电压;发光控制单元连接至发光控制信号端并且包括所述驱动晶体管,被配置为从发光控制信号端接收发光控制信号,在发光控制信号的控制下,利用在所述像素电路中存储的数据信号及所述驱动晶体管的阈值电压,产生驱动发光器件发光的电流;其中,所述发光控制单元包括第一类型晶体管,所述复位单元及电压写入单元包括与该第一类型晶体管不同的第二类型晶体管。
- 如权利要求1所述的像素电路,所述复位单元包括:第一复位晶体管(T2),其栅极连接至复位控制信号端,第一端连接至第一参考电压端,第二端连接至第二节点;第二复位晶体管(T4),其栅极连接至复位控制信号端,第一端连接至第一节点,第二端连接至第二参考电压端;第三复位晶体管(T6),其栅极连接至复位控制信号端,第一端连接至第二参考电压端,第二端连接至少一个发光器件;其中,所述复位单元被配置为在所述复位控制信号的控制下,对所述第一节点和所述第二节点进行复位。
- 如权利要求2所述的像素电路,其中,第一参考电压端为基准电压端或电源电压端或数据线。
- 如权利要求2所述的像素电路,所述电压写入单元包括:输入晶体管(T3),其栅极连接至扫描控制信号线,第一端连接至第二节点,第二端连接至数据线;第一补偿晶体管(T5),其栅极连接至扫描控制信号线,第一端连接至 第一节点,第二端连接至发光控制单元中的驱动晶体管(TD)的第二端;补偿电容(C1),其第一端连接至第二节点,第二端连接至第一节点;其中,所述电压写入单元被配置为在所述扫描控制信号的控制下,将数据线的数据信号写入第二节点,并在第一节点和第二节点之间存储所述数据信号及驱动晶体管的阈值电压。
- 如权利要求4所述的像素电路,所述发光控制单元包括:驱动晶体管(TD),其栅极连接至第一节点,第一端连接至电源电压端;第一发光晶体管(T1),其栅极连接至发光控制信号端,第一端连接至基准电压端,第二端连接至第二节点;发光控制晶体管(T7),其栅极连接至发光控制信号端,第一端连接至驱动晶体管(TD)的第二端,第二端连接至少一个发光器件;其中,所述发光控制单元被配置为在发光控制信号的控制下,利用在第一节点和第二节点之间存储的数据信号及驱动晶体管的阈值电压,产生驱动发光器件发光的电流。
- 如权利要求5所述的像素电路,其中,第一复位晶体管(T2)、第二复位晶体管(T4)、第三复位晶体管(T6)、输入晶体管(T3)和第一补偿晶体管(T5)均为N型氧化物薄膜晶体管,驱动晶体管(TD)、第一发光晶体管(T1)和发光控制晶体管(T7)皆为P型低温多晶硅薄膜晶体管。
- 一种显示装置,其包括像素电路阵列、第一阵列基板行驱动电路和第二阵列基板行驱动电路,所述像素电路阵列包括多个如权利要求1所述的像素电路,且第一阵列基板行驱动电路和第二阵列基板行驱动电路向像素电路阵列中的每个像素电路提供三个控制信号:复位控制信号、扫描控制信号及发光控制信号,其中,第一阵列基板行驱动电路用于向像素电路提供复位控制信号及扫描控制信号;第二阵列基板行驱动电路用于向像素电路提供发光控制信号。
- 如权利要求7所述的显示装置,其中,复位控制信号与扫描控制信号的起始时间不同,持续时间相同;复位控制信号与发光控制信号的起始时间相同,发光控制信号的持续时间比复位控制信号的持续时间长。
- 如权利要求8所述的显示装置,其中,所述第一阵列基板行驱动电路 和所述第二阵列基板行驱动电路为相同的阵列基板行驱动电路,且所述第一阵列基板行驱动电路和所述第二阵列基板行驱动电路均接收:第一电源信号、第二电源信号、时钟信号。
- 如权利要求9所述的显示装置,其中,所述第一阵列基板行驱动电路及所述第二阵列基板行驱动电路中的每一个包括级联的多个阵列基板行驱动单元,其中,所有的阵列基板行驱动单元的第一电源端接收第一电源信号,所有的阵列基板行驱动单元的第二电源端接收第二电源信号;每一级阵列基板行驱动单元的信号输出端连接至与其相邻的下一级阵列基板行驱动单元的第一输入端;每一级阵列基板行驱动单元的第二输入端连接至其相邻的下一级阵列基板行驱动单元的上拉输入节点;每一级阵列基板行驱动单元的第一时钟端的第一时钟信号和与其相邻的下一级阵列基板行驱动单元的第二时钟端的第二时钟信号相同;每一级阵列基板行驱动单元的第二时钟端的第二时钟信号和与其相邻的下一级阵列基板行驱动单元的第一时钟端的第一时钟信号相同。
- 如权利要求10所述的显示装置,所述多个阵列基板行驱动单元中的每一个包括:输入模块、上拉控制模块、上拉模块、下拉控制模块、下拉模块,其中,输入模块,其连接至第二电源端、第二时钟端、第一输入端,被配置为当第二时钟端的第二时钟信号处于有效电平时,根据第一输入端的第一输入信号(STV1)产生并输出第一控制信号,并根据第二电源端的第二电源信号产生并输出第二控制信号;上拉控制模块,其连接至输入模块、第一电源端及第一时钟端,且具有第一控制输入节点(P1)及第二控制输入节点(P2),被配置为将从输入模块接收的第一控制信号和第二控制信号分别写入第一控制输入节点(P1)和第二控制输入节点(P2),且在第一控制输入节点(P1)处于无效电平且第二控制输入节点(P2)及第一时钟端的第一时钟信号均处于有效电平的情况下,产生并输出上拉控制信号;上拉模块,其连接至上拉控制模块、第一电源端及信号输出端,且具有 上拉输入节点(P3),所述上拉模块被配置为在所述上拉控制信号的控制下,使得上拉输入节点(P3)处于有效电平,以将第一电源端的第一电源信号写入信号输出端;下拉控制模块,其连接至输入模块、第一时钟端且具有下拉控制输入节点(P4),被配置为在所述第一控制信号的控制下,使得下拉控制输入节点(P4)处于有效电平且输出下拉控制信号;下拉模块,其连接至下拉控制模块、第二电源端、第二输入端及信号输出端,且具有下拉输入节点(P5),所述下拉模块被配置为在所述下拉控制信号的控制下,使得下拉输入节点(P5)处于有效电平,以将第二电源端的第二电源信号写入信号输出端。
- 如权利要求11所述的显示装置,其中,所述下拉模块包括:下拉晶体管(M9),其栅极连接至下拉输入节点(P5),第一端连接至信号输出端,第二端连接至第二电源端;第十晶体管(M10),其栅极连接至第二输入端,第一端连接至信号输出端;第四电容(C4),其第一端连接至第十晶体管(M10)的第二端,第二端连接至下拉输入节点(P5)。
- 一种驱动权利要求11所述的显示装置的方法,其中,对于每个阵列基板行驱动单元:向第一输入端施加无效电平,向第一时钟端施加无效电平,向第二时钟端施加有效电平,产生处于无效电平的第一控制信号及处于有效电平的第二控制信号;向第一时钟端施加有效电平,根据所述第一控制信号及所述第二控制信号产生上拉控制信号,基于所述上拉控制信号,将第一电源端的第一电源信号写入信号输出端;向第一输入端、第二输入端、第二时钟端施加有效电平,产生处于有效电平的第一控制信号,根据所述第一控制信号产生下拉控制信号,基于所述下拉控制信号,将第二电源端的第二电源信号写入信号输出端。
- 一种驱动权利要求1所述的像素电路的方法,包括:向复位控制信号端施加有效电平,对所述像素电路进行复位;向扫描控制信号线施加有效电平,在所述像素电路中存储所述数据信号及驱动晶体管的阈值电压;以及向发光控制信号端施加有效电平,利用在所述像素电路中存储所述数据信号及驱动晶体管的阈值电压驱动发光器件发光。
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US11727868B2 (en) | 2023-08-15 |
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US20230306911A1 (en) | 2023-09-28 |
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