WO2020228070A1 - Tft阵列基板及其制造方法 - Google Patents

Tft阵列基板及其制造方法 Download PDF

Info

Publication number
WO2020228070A1
WO2020228070A1 PCT/CN2019/089831 CN2019089831W WO2020228070A1 WO 2020228070 A1 WO2020228070 A1 WO 2020228070A1 CN 2019089831 W CN2019089831 W CN 2019089831W WO 2020228070 A1 WO2020228070 A1 WO 2020228070A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
metal layer
layer
orthographic projection
tft array
Prior art date
Application number
PCT/CN2019/089831
Other languages
English (en)
French (fr)
Inventor
夏慧
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2020228070A1 publication Critical patent/WO2020228070A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present invention relates to the field of display technology, in particular to a TFT array substrate and a manufacturing method thereof.
  • the patterning differences of the film layers in the thin film transistor (Thin Film Transistor, TFT) array substrate result in some areas containing two layers of metal, and some areas containing a layer of metal, transition between the two terrain areas The zone forms a step with a large height difference, resulting in poor coverage of the film.
  • TFT Thi Film Transistor
  • some areas contain two layers of metal, and some areas contain one layer of metal.
  • the transition area between the two terrain areas forms a step with a large height difference, resulting in poor film coverage.
  • a TFT array substrate includes a substrate and a film structure arranged on the substrate, the film structure including:
  • the orthographic projection of the first part of the first metal layer on the substrate coincides with the orthographic projection of the second part of the second metal layer on the substrate, and the substrate and the first part and A groove is provided at a position corresponding to the second part, and the depth of the groove is equal to half of the sum of the thickness of the first part and the thickness of the second part;
  • the first metal layer includes gate metal Layer and scan traces
  • the second metal layer includes a source-drain metal layer and data traces
  • the orthographic projection of the source-drain metal layer on the substrate and the orthographic projection of the gate metal layer on the substrate The projection part overlaps.
  • orthographic projection of the data trace on the substrate is partially overlapped with the orthographic projection of the scanning trace on the substrate.
  • the film layer structure further includes:
  • a gate insulating layer disposed on the substrate and covering the first metal layer
  • the first metal layer is disposed on the substrate; the second metal layer is disposed on the gate insulating layer and the source and drain metal layers are in contact with the active layer; the passivation The layer covers the second metal layer.
  • a TFT array substrate includes a substrate and a film structure arranged on the substrate, the film structure including:
  • the orthographic projection of the first part of the first metal layer on the substrate coincides with the orthographic projection of the second part of the second metal layer on the substrate, and the substrate and the first part and A groove is provided at a position corresponding to the second part.
  • the depth of the groove is equal to half of the sum of the thickness of the first part and the thickness of the second part.
  • the first metal layer includes a gate metal layer and scan traces
  • the second metal layer includes a source-drain metal layer and data traces
  • the orthographic projection of the source-drain metal layer on the substrate is The orthographic projections of the gate metal layer on the substrate partially overlap.
  • orthographic projection of the data trace on the substrate is partially overlapped with the orthographic projection of the scanning trace on the substrate.
  • the film layer structure further includes:
  • a gate insulating layer disposed on the substrate and covering the first metal layer
  • the first metal layer is disposed on the substrate; the second metal layer is disposed on the gate insulating layer and the source and drain metal layers are in contact with the active layer; the passivation The layer covers the second metal layer.
  • the present invention also provides a method for manufacturing a TFT array substrate, including the following steps:
  • a patterned second metal layer is formed on the gate insulating layer, and the orthographic projection of the first part of the first metal layer on the substrate and the second part of the second metal layer are in the The orthographic projections on the substrate coincide;
  • step S20 includes:
  • the depth of the groove is equal to half of the sum of the thickness of the first metal layer and the thickness of the second metal layer.
  • the first metal layer includes a gate metal layer and scan traces
  • the second metal layer includes a source-drain metal layer and data traces
  • the orthographic projection of the source-drain metal layer on the substrate is The orthographic projections of the gate metal layer on the substrate partially overlap.
  • orthographic projection of the data trace on the substrate is partially overlapped with the orthographic projection of the scanning trace on the substrate.
  • the substrate is pre-patterned to form grooves at preset positions, thereby reducing the height difference between the double-layer metal area and the single-layer metal area in the TFT array substrate, improving flatness, and improving the coverage of each film layer. Reduce the terrain complexity caused by the height difference between the double-layer metal area and the single-layer metal area.
  • FIG. 1 is a schematic diagram of the structure of a TFT array substrate in a specific embodiment of the present invention
  • FIG. 2 is a schematic diagram of a manufacturing process of a TFT array substrate in a specific embodiment of the present invention
  • 3 to 8 are schematic diagrams of manufacturing steps of a TFT array substrate in a specific embodiment of the present invention.
  • the present invention aims at the existing TFT array substrate, where some areas contain two layers of metal, and some areas contain one layer of metal.
  • the transition area between the two terrain areas forms a step with a large height difference, resulting in film coverage. Poor technical problem.
  • the present invention can solve the above-mentioned problems.
  • the TFT array substrate includes a substrate 10 and a film structure provided on the substrate 10.
  • the film structure includes a first metal layer, a gate insulating layer 30, The active layer 40, the second metal layer, the passivation layer 60 and the pixel electrode 70.
  • the second metal layer is located above the first metal layer, the first metal layer includes the first portion 24, the second metal layer includes the second portion 53, and the first portion of the first metal layer
  • the orthographic projection of 24 on the substrate 10 coincides with the orthographic projection of the second portion 53 of the second metal layer on the substrate 10, which overlaps the first portion 24 and the second portion on the substrate 10
  • a groove 11 is provided at the position corresponding to 53.
  • the substrate 10 is pre-patterned to form the groove 11 at the preset position, thereby reducing the height difference between the double-layer metal area and the single-layer metal area in the TFT array substrate 10, improving the flatness, and improving the film layers.
  • the coverage reducing the terrain complexity caused by the height difference between the double-layer metal area and the single-layer metal area.
  • the depth of the groove 11 is equal to half of the sum of the thickness of the first portion 24 and the thickness of the second portion 53.
  • the thickness of the first portion 24 of the first metal layer is A
  • the thickness of the second portion 53 of the second metal layer is B
  • the depth of the groove 11 is C
  • the first metal layer is disposed on the substrate 10, and the first metal layer includes a gate metal layer 21, a scan line 22, and is connected to the gate metal layer 21 and the scan line 22. Capacitor plates 23 isolated from each other.
  • the gate insulating layer 30 is disposed on the substrate 10 and covers the first metal layer.
  • the active layer 40 is disposed on the gate insulating layer 30, the active layer 40 includes an active island, and the active island has an ion-doped region.
  • the second metal layer is disposed on the gate insulating layer 30, the second metal layer includes a source-drain metal layer 51 and a data trace 52, and the source-drain metal layer 51 is connected to the active
  • the layer 40 is connected in contact.
  • the source-drain metal layer 51 is in contact with the ion-doped region of the active island.
  • the orthographic projection of the source-drain metal layer 51 on the substrate 10 overlaps with the orthographic projection of the gate metal layer 21 on the substrate 10, and the data wiring 52 is on the substrate 10.
  • the orthographic projection of is overlapped with the orthographic projection of the scan line 22 on the substrate 10.
  • the passivation layer 60 is disposed on the gate insulating layer 30 and covers the second metal layer.
  • the pixel electrode 70 is disposed on the passivation layer 60 and is in contact with the source and drain metal layer 51, and the pixel electrode 70 and the capacitor plate 23 form a storage capacitor.
  • the present invention also provides a method for manufacturing a TFT array substrate, as shown in FIG. 2, including the following steps:
  • a patterned second metal layer is formed on the gate insulating layer 30, and the orthographic projection of the first part 24 of the first metal layer on the substrate 10 and the second part of the second metal layer The orthographic projections of 53 on the substrate 10 coincide;
  • step S20 includes:
  • the preset position is determined according to the area defined by the projection of the first part 24 of the first metal layer and the second part 53 of the second metal layer on the substrate 10,
  • the projections of the first part 24 and the second part 53 on the substrate 10 are encompassed by an area defined by a preset position.
  • the depth of the groove 11 is equal to half of the sum of the thickness of the first portion 24 and the thickness of the second portion 53.
  • the first metal layer includes a gate metal layer 21 and a scan line 22, and the second metal layer includes a source and drain metal layer 51 and a data line 52.
  • the orthographic projection of the source-drain metal layer 51 on the substrate 10 overlaps with the orthographic projection of the gate metal layer 21 on the substrate 10, and the data wiring 52 is on the substrate 10.
  • the orthographic projection of is overlapped with the orthographic projection of the scan line 22 on the substrate 10.
  • FIGS. 3 to 8 are schematic diagrams of manufacturing steps of the TFT array substrate.
  • a photoresist layer 80 is formed on the substrate 10, and the photoresist layer 80 is exposed and developed to peel off the part of the photoresist layer 80 at a predetermined position on the substrate 10. So that the surface of the substrate 10 at the preset position is exposed.
  • the substrate 10 at the preset position is etched with an etching solution to form the groove 11.
  • the substrate 10 is a glass substrate
  • the etching solution is a glass etching solution.
  • a first metal layer is formed on the substrate 10, and the first metal layer is patterned to form a gate metal layer 21, a scan line 22, and a gate metal layer.
  • the layer 21 and the capacitive plate 23 of the scan trace 22 are isolated from each other, and at the same time, the first portion 24 of the first metal layer is located in the groove 11.
  • an active layer 40 is formed on the gate insulating layer 30.
  • a second metal layer is formed on the gate insulating layer 30, and the second metal layer is patterned to form a source-drain metal layer 51 and data wiring 52;
  • the source-drain metal layer 51 is in contact with the active layer 40, the orthographic projection of the second part 53 of the second metal layer on the substrate 10 and the first part 24 of the first metal layer are in the The orthographic projections on the substrate 10 coincide.
  • a contact connection with the source and drain metal layer 51 is formed on the passivation layer 60
  • the pixel electrode 70, the pixel electrode 70 and the capacitor plate 23 form a storage capacitor, and the passivation layer 60 and the gate insulating layer 30 between the pixel electrode 70 and the capacitor plate 23 are the dielectric materials of the capacitor .
  • the substrate 10 is pre-patterned to form a groove 11 at a preset position, thereby reducing the height difference between the double-layer metal area and the single-layer metal area in the TFT array substrate 10, and improving the flatness Therefore, the coverage of each film layer is improved, and the terrain complexity caused by the height difference between the double-layer metal area and the single-layer metal area is reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种TFT阵列基板及其制造方法，TFT阵列基板包括基板（10）和设置于基板（10）上的膜层结构；其中，膜层结构包括第一金属层和位于第一金属层上方的第二金属层，第一金属层的第一部分（24）在基板（10）上的正投影与第二金属层的第二部分（53）在所述基板（10）上的正投影重合，基板（10）上与第一部分（24）和第二部分（53）对应的位置处设置有凹槽（11）。

Description

TFT阵列基板及其制造方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制造方法。
 背景技术
目前液晶显示器制造中，薄膜晶体管（Thin Film Transistor，TFT）阵列基板中各膜层的图形化差异导致部分区域含有两层金属，还有部分区域含有一层金属，两种地形区域之间的过渡区形成高度差较大的台阶，从而导致膜层的覆盖性较差。
 技术问题
现有的TFT阵列基板中，部分区域含有两层金属，还有部分区域含有一层金属，两种地形区域之间的过渡区形成高度差较大的台阶，导致膜层的覆盖性较差。
 技术解决方案
一种TFT阵列基板，包括基板和设置于所述基板上的膜层结构，所述膜层结构包括：
第一金属层；
位于所述第一金属层上方的第二金属层；
其中，所述第一金属层的第一部分在所述基板上的正投影与所述第二金属层的第二部分在所述基板上的正投影重合，所述基板上与所述第一部分和所述第二部分对应的位置处设置有凹槽，所述凹槽的深度等于所述第一部分的厚度与所述第二部分的厚度之和的一半；所述第一金属层包括栅极金属层和扫描走线，所述第二金属层包括源漏金属层和数据走线，所述源漏金属层在所述基板上的正投影与所述栅极金属层在所述基板上的正投影部分重合。
进一步的，所述数据走线在所述基板上的正投影与所述扫描走线在所述基板上的正投影部分重合。
进一步的，所述膜层结构还包括：
设置于所述基板上且覆盖所述第一金属层的栅极绝缘层；
设置于所述栅极绝缘层上的有源层和钝化层；
设置于所述钝化层上的像素电极；
其中，所述第一金属层设置于所述基板上；所述第二金属层设置于所述栅极绝缘层上且所述源漏金属层与所述有源层接触连接；所述钝化层覆盖所述第二金属层。
一种TFT阵列基板，包括基板和设置于所述基板上的膜层结构，所述膜层结构包括：
第一金属层；
位于所述第一金属层上方的第二金属层；
其中，所述第一金属层的第一部分在所述基板上的正投影与所述第二金属层的第二部分在所述基板上的正投影重合，所述基板上与所述第一部分和所述第二部分对应的位置处设置有凹槽。
进一步的，所述凹槽的深度等于所述第一部分的厚度与所述第二部分的厚度之和的一半。
进一步的，所述第一金属层包括栅极金属层和扫描走线，所述第二金属层包括源漏金属层和数据走线，所述源漏金属层在所述基板上的正投影与所述栅极金属层在所述基板上的正投影部分重合。
进一步的，所述数据走线在所述基板上的正投影与所述扫描走线在所述基板上的正投影部分重合。
进一步的，所述膜层结构还包括：
设置于所述基板上且覆盖所述第一金属层的栅极绝缘层；
设置于所述栅极绝缘层上的有源层和钝化层；
设置于所述钝化层上的像素电极；
其中，所述第一金属层设置于所述基板上；所述第二金属层设置于所述栅极绝缘层上且所述源漏金属层与所述有源层接触连接；所述钝化层覆盖所述第二金属层。
本发明还提供一种TFT阵列基板的制造方法，包括以下步骤：
S10、提供一基板；
S20、在所述基板上的预设位置处形成凹槽；
S30、在所述基板上形成图案化的第一金属层，所述第一金属层的第一部分位于所述凹槽中；
S40、在所述基板上形成覆盖所述第一金属层的栅极绝缘层；
S50、在所述栅极绝缘层上形成有源层；
S60、在所述栅极绝缘层上形成图案化的第二金属层，所述第一金属层的第一部分在所述基板上的正投影与所述第二金属层的第二部分在所述基板上的正投影重合；
S70、在所述栅极绝缘层上形成覆盖所述第二金属层的钝化层；
S80、在所述钝化层上形成像素电极。
进一步的，所述步骤S20包括：
S21、在所述基板上形成光阻层；
S22、对所述光阻层进行曝光和显影，将光阻层位于所述基板上预设位置处的部分剥离；
S23、使用蚀刻液对预设位置处的基板进行蚀刻处理，以形成凹槽。
进一步的，所述凹槽的深度等于所述第一金属层的厚度与所述第二金属层的厚度之和的一半。
进一步的，所述第一金属层包括栅极金属层和扫描走线，所述第二金属层包括源漏金属层和数据走线，所述源漏金属层在所述基板上的正投影与所述栅极金属层在所述基板上的正投影部分重合。
进一步的，所述数据走线在所述基板上的正投影与所述扫描走线在所述基板上的正投影部分重合。
 有益效果
对基板进行预图形化处理在预设位置处形成凹槽，从而降低TFT阵列基板中双层金属区域与单层金属区域之间的高度差异，提高平坦度，从而提高各膜层的覆盖性，减小双层金属区域与单层金属区域的高度差异带来的地形复杂化问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明具体实施方式中TFT阵列基板的结构示意图；
图2为本发明具体实施方式中TFT阵列基板的制造流程示意图；
图3至图8为本发明具体实施方式中TFT阵列基板的制造步骤示意图。
附图标记：
10、基板；11、凹槽；21、栅极金属层；22、扫描走线；23、电容极板；24、第一部分；30、栅极绝缘层；40、有源层；51、源漏金属层；52、数据走线；53、第二部分；60、钝化层；70、像素电极；80、光阻层。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的TFT阵列基板中，部分区域含有两层金属，还有部分区域含有一层金属，两种地形区域之间的过渡区形成高度差较大的台阶，导致膜层的覆盖性较差的技术问题。本发明可以解决上述问题。
一种TFT阵列基板，如图1所示，所述TFT阵列基板包括基板10和设置于所述基板10上的膜层结构，所述膜层结构包括第一金属层、栅极绝缘层30、有源层40、第二金属层、钝化层60以及像素电极70。
其中，所述第二金属层位于所述第一金属层的上方，所述第一金属层包括第一部分24，所述第二金属层包括第二部分53，所述第一金属层的第一部分24在所述基板10上的正投影与所述第二金属层的第二部分53在所述基板10上的正投影重合，所述基板10上与所述第一部分24和所述第二部分53对应的位置处设置有凹槽11。
对基板10进行预图形化处理以在预设位置处形成凹槽11，从而降低TFT阵列基板10中双层金属区域与单层金属区域之间的高度差异，提高平坦度，从而提高各膜层的覆盖性，减小双层金属区域与单层金属区域的高度差异带来的地形复杂化问题。
进一步的，所述凹槽11的深度等于所述第一部分24的厚度与所述第二部分53的厚度之和的一半。
需要说明的是，所述第一金属层的第一部分24的厚度为A，所述第二金属层的第二部分53的厚度为B，所述凹槽11的深度为C，则C=（A+B）÷2。
具体的，所述第一金属层设置于所述基板10上，所述第一金属层包括栅极金属层21、扫描走线22以及与所述栅极金属层21和所述扫描走线22相互隔离的电容极板23。
具体的，所述栅极绝缘层30设置于所述基板10上且覆盖所述第一金属层。
具体的，所述有源层40设置于所述栅极绝缘层30上，所述有源层40包括有源岛，所述有源岛具有离子掺杂区。
具体的，所述第二金属层设置于所述栅极绝缘层30上，所述第二金属层包括源漏金属层51和数据走线52，所述源漏金属层51与所述有源层40接触连接。
进一步的，所述源漏金属层51与所述有源岛的离子掺杂区接触连接。
其中，所述源漏金属层51在所述基板10上的正投影与所述栅极金属层21在所述基板10上的正投影部分重合，所述数据走线52在所述基板10上的正投影与所述扫描走线22在所述基板10上的正投影部分重合。
具体的，所述钝化层60设置于所述栅极绝缘层30上且覆盖所述第二金属层。
具体的，所述像素电极70设置于所述钝化层60上且与所述源漏金属层51接触连接，所述像素电极70与所述电容极板23形成存储电容。
基于上述TFT阵列基板，本发明还提供一种TFT阵列基板的制造方法，如图2所示，包括以下步骤：
S10、提供一基板10；
S20、在所述基板10上的预设位置处形成凹槽11；
S30、在所述基板10上形成图案化的第一金属层，所述第一金属层的第一部分24位于所述凹槽11中；
S40、在所述基板10上形成覆盖所述第一金属层的栅极绝缘层30；
S50、在所述栅极绝缘层30上形成有源层40；
S60、在所述栅极绝缘层30上形成图案化的第二金属层，所述第一金属层的第一部分24在所述基板10上的正投影与所述第二金属层的第二部分53在所述基板10上的正投影重合；
S70、在所述栅极绝缘层30上形成覆盖所述第二金属层的钝化层60；
S80、在所述钝化层60上形成像素电极70。
进一步的，所述步骤S20包括：
S21、在所述基板10上形成光阻层80；
S22、对所述光阻层80进行曝光和显影，将光阻层80位于所述基板10上预设位置处的部分剥离；
S23、使用蚀刻液对预设位置处的基板10进行蚀刻处理，以形成凹槽11。
需要说明的是，实际实施中，根据所述第一金属层的第一部分24和所述第二金属层的第二部分53在基板10上的投影所限定的区域来确定预设位置，所述第一部分24和所述第二部分53在基板10上的投影被预设位置所限定的区域包纳。
具体的，所述凹槽11的深度等于所述第一部分24的厚度与所述第二部分53的厚度之和的一半。
具体的，所述第一金属层包括栅极金属层21和扫描走线22，所述第二金属层包括源漏金属层51和数据走线52。
其中，所述源漏金属层51在所述基板10上的正投影与所述栅极金属层21在所述基板10上的正投影部分重合，所述数据走线52在所述基板10上的正投影与所述扫描走线22在所述基板10上的正投影部分重合。
参见图3至图8，图3至图8为所述TFT阵列基板的制造步骤示意图。
如图3所示，在所述基板10上形成光阻层80，并对所述光阻层80进行曝光和显影，将光阻层80位于所述基板10上预设位置处的部分剥离，以使位于预设位置处的基板10表面露出。
如图4所示，使用蚀刻液对预设位置处的基板10进行蚀刻处理，以形成凹槽11。
在一实施方式中，所述基板10为玻璃基板，所述蚀刻液为玻璃蚀刻液。
如图5所示，在所述基板10上形成第一金属层，并对所述第一金属层进行图案化处理，以形成栅极金属层21、扫描走线22以及与所述栅极金属层21和所述扫描走线22相互隔离的电容极板23，同时，所述第一金属层的第一部分24位于所述凹槽11中。
如图6所示，在所述基板10上形成覆盖所述第一金属层的栅极绝缘层30后，在所述栅极绝缘层30上形成有源层40。
如图7所示，在所述栅极绝缘层30上形成第二金属层，并对所述第二金属层进行图案化处理，以形成源漏金属层51和数据走线52；其中，所述源漏金属层51与所述有源层40接触连接，所述第二金属层的第二部分53在所述基板10上的正投影与所述第一金属层的第一部分24在所述基板10上的正投影重合。
如图8所示，在所述栅极绝缘层30上形成覆盖所述第二金属层的钝化层60后，在所述钝化层60上形成与所述源漏金属层51接触连接的像素电极70，所述像素电极70与所述电容极板23形成存储电容，所述像素电极70与所述电容极板23之间的钝化层60和栅极绝缘层30为电容的介质材料。
本发明的有益效果为：对基板10进行预图形化处理在预设位置处形成凹槽11，从而降低TFT阵列基板10中双层金属区域与单层金属区域之间的高度差异，提高平坦度，从而提高各膜层的覆盖性，减小双层金属区域与单层金属区域的高度差异带来的地形复杂化问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种TFT阵列基板，其中，所述TFT阵列基板包括基板和设置于所述基板上的膜层结构，所述膜层结构包括：
    第一金属层；
    位于所述第一金属层上方的第二金属层；
    其中，所述第一金属层的第一部分在所述基板上的正投影与所述第二金属层的第二部分在所述基板上的正投影重合，所述基板上与所述第一部分和所述第二部分对应的位置处设置有凹槽，所述凹槽的深度等于所述第一部分的厚度与所述第二部分的厚度之和的一半；所述第一金属层包括栅极金属层和扫描走线，所述第二金属层包括源漏金属层和数据走线，所述源漏金属层在所述基板上的正投影与所述栅极金属层在所述基板上的正投影部分重合。
  2. 根据权利要求1所述的TFT阵列基板，其中，所述数据走线在所述基板上的正投影与所述扫描走线在所述基板上的正投影部分重合。
  3. 根据权利要求1所述的TFT阵列基板，其中，所述膜层结构还包括：
    设置于所述基板上且覆盖所述第一金属层的栅极绝缘层；
    设置于所述栅极绝缘层上的有源层和钝化层；
    设置于所述钝化层上的像素电极；
    其中，所述第一金属层设置于所述基板上；所述第二金属层设置于所述栅极绝缘层上且所述源漏金属层与所述有源层接触连接；所述钝化层覆盖所述第二金属层。
  4. 一种TFT阵列基板，其中，所述TFT阵列基板包括基板和设置于所述基板上的膜层结构，所述膜层结构包括：
    第一金属层；
    位于所述第一金属层上方的第二金属层；
    其中，所述第一金属层的第一部分在所述基板上的正投影与所述第二金属层的第二部分在所述基板上的正投影重合，所述基板上与所述第一部分和所述第二部分对应的位置处设置有凹槽。
  5. 根据权利要求4所述的TFT阵列基板，其中，所述凹槽的深度等于所述第一部分的厚度与所述第二部分的厚度之和的一半。
  6. 根据权利要求4所述的TFT阵列基板，其中，所述第一金属层包括栅极金属层和扫描走线，所述第二金属层包括源漏金属层和数据走线，所述源漏金属层在所述基板上的正投影与所述栅极金属层在所述基板上的正投影部分重合。
  7. 根据权利要求6所述的TFT阵列基板，其中，所述数据走线在所述基板上的正投影与所述扫描走线在所述基板上的正投影部分重合。
  8. 根据权利要求6所述的TFT阵列基板，其中，所述膜层结构还包括：
    设置于所述基板上且覆盖所述第一金属层的栅极绝缘层；
    设置于所述栅极绝缘层上的有源层和钝化层；
    设置于所述钝化层上的像素电极；
    其中，所述第一金属层设置于所述基板上；所述第二金属层设置于所述栅极绝缘层上且所述源漏金属层与所述有源层接触连接；所述钝化层覆盖所述第二金属层。
  9. 一种TFT阵列基板的制造方法，其中，包括以下步骤：
    S10、提供一基板；
    S20、在所述基板上的预设位置处形成凹槽；
    S30、在所述基板上形成图案化的第一金属层，所述第一金属层的第一部分位于所述凹槽中；
    S40、在所述基板上形成覆盖所述第一金属层的栅极绝缘层；
    S50、在所述栅极绝缘层上形成有源层；
    S60、在所述栅极绝缘层上形成图案化的第二金属层，所述第一金属层的第一部分在所述基板上的正投影与所述第二金属层的第二部分在所述基板上的正投影重合；
    S70、在所述栅极绝缘层上形成覆盖所述第二金属层的钝化层；
    S80、在所述钝化层上形成像素电极。
  10. 根据权利要求9所述的TFT阵列基板的制造方法，其中，所述步骤S20包括：
    S21、在所述基板上形成光阻层；
    S22、对所述光阻层进行曝光和显影，将光阻层位于所述基板上预设位置处的部分剥离；
    S23、使用蚀刻液对预设位置处的基板进行蚀刻处理，以形成凹槽。
  11. 根据权利要求9所述的TFT阵列基板的制造方法，其中，所述凹槽的深度等于所述第一金属层的厚度与所述第二金属层的厚度之和的一半。
  12. 根据权利要求9所述的TFT阵列基板的制造方法，其中，所述第一金属层包括栅极金属层和扫描走线，所述第二金属层包括源漏金属层和数据走线，所述源漏金属层在所述基板上的正投影与所述栅极金属层在所述基板上的正投影部分重合。
  13. 根据权利要求12所述的TFT阵列基板的制造方法，其中，所述数据走线在所述基板上的正投影与所述扫描走线在所述基板上的正投影部分重合。
PCT/CN2019/089831 2019-05-15 2019-06-03 Tft阵列基板及其制造方法 WO2020228070A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910400628.3 2019-05-15
CN201910400628.3A CN110164871A (zh) 2019-05-15 2019-05-15 Tft阵列基板及其制造方法

Publications (1)

Publication Number Publication Date
WO2020228070A1 true WO2020228070A1 (zh) 2020-11-19

Family

ID=67634624

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/089831 WO2020228070A1 (zh) 2019-05-15 2019-06-03 Tft阵列基板及其制造方法

Country Status (2)

Country Link
CN (1) CN110164871A (zh)
WO (1) WO2020228070A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740607A (zh) * 2008-11-10 2010-06-16 三星移动显示器株式会社 有机发光显示器件及其制造方法
CN104795400A (zh) * 2015-02-12 2015-07-22 合肥鑫晟光电科技有限公司 阵列基板制造方法、阵列基板和显示装置
US20180102379A1 (en) * 2016-03-01 2018-04-12 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacture method of array substrate and array substrate manufactured by the method
CN109742121A (zh) * 2019-01-10 2019-05-10 京东方科技集团股份有限公司 一种柔性基板及其制备方法、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09139508A (ja) * 1995-11-10 1997-05-27 Toyota Motor Corp 薄膜トランジスタの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740607A (zh) * 2008-11-10 2010-06-16 三星移动显示器株式会社 有机发光显示器件及其制造方法
CN104795400A (zh) * 2015-02-12 2015-07-22 合肥鑫晟光电科技有限公司 阵列基板制造方法、阵列基板和显示装置
US20180102379A1 (en) * 2016-03-01 2018-04-12 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacture method of array substrate and array substrate manufactured by the method
CN109742121A (zh) * 2019-01-10 2019-05-10 京东方科技集团股份有限公司 一种柔性基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN110164871A (zh) 2019-08-23

Similar Documents

Publication Publication Date Title
US8633066B2 (en) Thin film transistor with reduced edge slope angle, array substrate and having the thin film transistor and manufacturing method thereof
US9971220B2 (en) COA substrate and manufacturing method thereof
WO2016119344A1 (zh) 阵列基板及其制造方法和显示面板
WO2017049842A1 (zh) 阵列基板及其制作方法、显示装置
JP2006330470A (ja) 液晶表示装置及びその製造方法
JP6521534B2 (ja) 薄膜トランジスタとその作製方法、アレイ基板及び表示装置
US9773817B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
WO2015000255A1 (zh) 阵列基板、显示装置及阵列基板的制造方法
US9450103B2 (en) Thin film transistor, method for manufacturing the same, display device and electronic product
JP2009133954A (ja) 液晶表示装置及びその製造方法
US9219088B2 (en) Array substrate, manufacturing method thereof, and display device
WO2016074413A1 (zh) 显示基板及其制作方法、显示面板及显示装置
WO2020133651A1 (zh) 像素电极结构及其制作方法
US20210303093A1 (en) Array substrate and method for manufacturing same, and display device
WO2017140058A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
WO2020253031A1 (zh) 一种阵列基板及其制备方法
WO2020082623A1 (zh) 薄膜晶体管及其制造方法
WO2021168904A1 (zh) 一种显示面板、其制备方法及显示装置
CN103681514B (zh) 阵列基板及其制作方法、显示装置
WO2020077861A1 (zh) 一种阵列基板及其制备方法
WO2015180302A1 (zh) 阵列基板及其制备方法、显示装置
US9799683B2 (en) Array substrate, preparation method thereof and display device
WO2020124713A1 (zh) 一种阵列基板及其制备方法
US20120119210A1 (en) Pixel structure and dual gate pixel structure
WO2018108069A1 (zh) 显示装置及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19928931

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19928931

Country of ref document: EP

Kind code of ref document: A1