WO2020186989A1 - 基板及其制作方法、触控显示装置 - Google Patents

基板及其制作方法、触控显示装置 Download PDF

Info

Publication number
WO2020186989A1
WO2020186989A1 PCT/CN2020/076942 CN2020076942W WO2020186989A1 WO 2020186989 A1 WO2020186989 A1 WO 2020186989A1 CN 2020076942 W CN2020076942 W CN 2020076942W WO 2020186989 A1 WO2020186989 A1 WO 2020186989A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive pattern
photoresist
substrate
layer
conductive
Prior art date
Application number
PCT/CN2020/076942
Other languages
English (en)
French (fr)
Inventor
孙雪峰
刘国梁
吴国特
陈志龙
李香
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020186989A1 publication Critical patent/WO2020186989A1/zh

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412Digitisers structurally integrated in a display
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/045Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40OLEDs integrated with touch screens
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present disclosure relates to the field of touch technology, in particular to a substrate, a manufacturing method thereof, and a touch display device.
  • the contact method between the touch electrode and the touch signal line in the touch display product in the related technology is that the touch electrode contacts the surface of the touch electrode line through the through hole penetrating the flat layer.
  • the resolution of the touch display product the The higher the pixel density, the larger the pixel density, and the smaller the contact area between the touch electrode and the touch signal line, which makes the contact resistance between the touch electrode and the touch signal line too large, which is likely to cause poor sensing.
  • the embodiments of the present disclosure provide a substrate, including a base substrate and a first conductive pattern, an insulating layer, and a second conductive pattern sequentially located on the base substrate, the second conductive pattern passing through the insulating layer
  • the via hole is connected to the first conductive pattern, a groove is formed on the surface of the first conductive pattern away from the base substrate, and the second conductive pattern is connected to the bottom and sidewalls of the groove To contact.
  • the substrate is a touch substrate
  • the first conductive pattern is a touch signal line
  • the second conductive pattern is a touch electrode
  • first conductive pattern and the source and drain of the thin film transistor of the substrate are provided in the same layer and the same material.
  • the first conductive pattern adopts a three-layer structure of Ti/Al/Ti, and the bottom of the groove exposes Ti at the bottom of the first conductive pattern.
  • the embodiment of the present disclosure also provides a touch display device, including the substrate as described above.
  • the embodiment of the present disclosure also provides a method for manufacturing a substrate, including:
  • a second conductive pattern is formed on the insulating layer, and the second conductive pattern is in contact with the bottom and sidewalls of the groove through the via hole.
  • the substrate is a touch substrate
  • the first conductive pattern is a touch signal line
  • the second conductive pattern is a touch electrode
  • the forming the first conductive pattern on the base substrate includes:
  • the same mask is used to form the first conductive pattern and the source and drain of the thin film transistor of the substrate through a patterning process.
  • the formation of the first conductive pattern and the source and drain of the thin film transistor of the substrate by a patterning process using the same mask includes:
  • the photoresist fully reserved area corresponds to the source electrode and the drain electrode, and the first thickness of the photoresist partially reserved area is smaller than the second thickness of the photoresist fully reserved area.
  • the first conductive pattern adopts a Ti/Al/Ti three-layer structure
  • the etching the conductive layer in the partially reserved area of the photoresist includes:
  • the first thickness of the partially reserved photoresist area is adjusted so that when the conductive layer in the partially reserved photoresist area is etched, only Ti at the bottom of the first conductive pattern is etched.
  • the forming an insulating layer covering the first conductive pattern includes:
  • the forming a second conductive pattern on the insulating layer includes:
  • the transparent conductive layer is patterned to form the second conductive pattern, and the second conductive pattern is in contact with the bottom and sidewalls of the groove through the via hole penetrating the insulating layer.
  • FIG. 1 is a schematic diagram of the structure of a substrate in the related art
  • FIG. 2 is a schematic diagram of the structure of a substrate according to an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of an embodiment of the disclosure after a conductive layer is formed
  • FIG. 4 is a schematic diagram after exposing the photoresist according to the embodiment of the disclosure.
  • FIG. 5 is a schematic diagram after etching the conductive layer according to an embodiment of the disclosure.
  • FIG. 1 is a schematic diagram of the structure of a substrate in the related art.
  • the touch display substrate in the related art includes: a base substrate 1, a light shielding layer 6 on the base substrate 1, and a buffer covering the light shielding layer 6 Layer 2, the active layer 7 located on the buffer layer 2, the interlayer insulating layer 3 covering the active layer 7, the gate electrode 8 located on the interlayer insulating layer 3, the gate insulating layer 4 covering the gate electrode 8, located on the gate
  • touch The control electrode 12 is connected to the touch signal line 11 through a via hole penetrating the planar layer 5.
  • the touch electrode 12 and the touch signal line 11 are only in surface contact. As the resolution of touch display products becomes higher and higher, the pixel density becomes larger and larger, the touch electrode 12 and the touch signal The contact area of the wire 11 is also getting smaller and smaller, so that the contact resistance between the touch electrode 12 and the touch signal wire 11 is too large, which is likely to cause poor sensing.
  • the embodiments of the present disclosure provide a substrate, a manufacturing method thereof, and a touch display device, which can optimize the electrical performance of the substrate and avoid poor sensing.
  • the embodiment of the present disclosure provides a substrate, including a base substrate and a first conductive pattern, an insulating layer, and a second conductive pattern sequentially located on the base substrate, and the second conductive pattern passes through the insulating layer.
  • the hole is connected to the first conductive pattern, a groove is formed on the surface of the first conductive pattern away from the base substrate, and the second conductive pattern is in contact with the bottom and sidewalls of the groove .
  • a groove is formed on the surface of the first conductive pattern away from the base substrate, and the second conductive pattern is in contact with the bottom and sidewalls of the groove, so that the first conductive pattern and the second conductive pattern can be increased.
  • the contact area is reduced, the contact resistance between the first conductive pattern and the second conductive pattern is reduced, the connection between the first conductive pattern and the second conductive pattern in different layers is optimized, the electrical performance of the substrate is ensured, and poor sensing is avoided.
  • the aforementioned substrate may be a touch substrate, a display substrate, or a touch display substrate.
  • the first conductive pattern and the second conductive pattern may be any two conductive patterns arranged in different layers on the display substrate.
  • the first conductive pattern may be the drain of a thin film transistor
  • the second conductive pattern may It is the anode of the OLED display substrate, which can optimize the connection between the drain of the thin film transistor and the anode of the OLED display substrate to avoid display failure.
  • the first conductive pattern may be a touch signal line
  • the second conductive pattern may be a touch electrode, which can optimize the connection between the touch signal line and the touch electrode , To avoid poor sensing.
  • the first conductive pattern is a touch signal line
  • the first conductive pattern and the source and drain of the thin film transistor of the substrate are arranged in the same layer and the same material, so that the first patterning process can be formed at the same time.
  • the conductive pattern and the source and drain of the thin film transistor of the substrate can save the number of patterning processes of the substrate and reduce the production cost of the substrate.
  • the first conductive pattern may adopt a three-layer structure of Ti/Al/Ti, wherein the upper and lower layers of Ti can prevent the Al in the middle from being oxidized.
  • the grooves The bottom part can expose the Ti at the bottom of the first conductive pattern, so that the second conductive pattern is in contact with the upper layer Ti and the Al in the middle, which can increase the contact area between the first conductive pattern and the second conductive pattern, and reduce the first conductive pattern and
  • the contact resistance of the second conductive pattern optimizes the connection condition between the first conductive pattern and the second conductive pattern in different layers.
  • the embodiment of the present disclosure also provides a touch display device, including the substrate as described above.
  • the touch display device may be any product or component with a display function, such as an LCD TV, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane .
  • the embodiment of the present disclosure also provides a method for manufacturing a substrate, including:
  • a second conductive pattern is formed on the insulating layer, and the second conductive pattern is in contact with the bottom and sidewalls of the groove through the via hole.
  • a groove is formed on the surface of the first conductive pattern away from the base substrate, and the second conductive pattern is in contact with the bottom and sidewalls of the groove, so that the first conductive pattern and the second conductive pattern can be increased.
  • the contact area is reduced, the contact resistance between the first conductive pattern and the second conductive pattern is reduced, the connection between the first conductive pattern and the second conductive pattern in different layers is optimized, the electrical performance of the substrate is ensured, and poor sensing is avoided.
  • the aforementioned substrate may be a touch substrate, a display substrate, or a touch display substrate.
  • the first conductive pattern and the second conductive pattern may be any two conductive patterns arranged in different layers on the display substrate.
  • the first conductive pattern may be the drain of a thin film transistor
  • the second conductive pattern may It is the anode of the OLED display substrate, which can optimize the connection between the drain of the thin film transistor and the anode of the OLED display substrate to avoid display failure.
  • the first conductive pattern may be a touch signal line
  • the second conductive pattern may be a touch electrode, which can optimize the connection between the touch signal line and the touch electrode , To avoid poor sensing.
  • the first conductive pattern is a touch signal line
  • the first conductive pattern and the source and drain of the thin film transistor of the substrate are provided in the same layer and the same material, and the first conductive pattern is formed on the base substrate.
  • Conductive patterns include:
  • the first conductive pattern, the source electrode and the drain electrode of the thin film transistor of the substrate are formed by one patterning process using the same mask. In this way, the first conductive pattern, the source electrode and the drain electrode of the thin film transistor of the substrate can be simultaneously formed through one patterning process, which can save the number of patterning processes of the substrate and reduce the production cost of the substrate.
  • the formation of the first conductive pattern and the source and drain of the thin film transistor of the substrate by a patterning process using the same mask includes:
  • the photoresist fully reserved area corresponds to the source electrode and the drain electrode, and the first thickness of the photoresist partially reserved area is smaller than the second thickness of the photoresist fully reserved area.
  • the first conductive pattern adopts a Ti/Al/Ti three-layer structure
  • the etching of the conductive layer in the partially reserved area of the photoresist includes:
  • the first thickness of the partially reserved photoresist area is adjusted so that when the conductive layer in the partially reserved photoresist area is etched, only Ti at the bottom of the first conductive pattern is etched.
  • the forming the insulating layer covering the first conductive pattern includes:
  • the forming a second conductive pattern on the insulating layer includes:
  • the transparent conductive layer is patterned to form the second conductive pattern, and the second conductive pattern is in contact with the bottom and sidewalls of the groove through the via hole penetrating the insulating layer.
  • FIG. 2 is a schematic diagram of the structure of the substrate of the embodiment of the disclosure.
  • the touch display substrate of this embodiment includes: a base substrate 1.
  • the gate insulating layer 4 covering the gate 8, the touch signal line 11, the source 9 and the drain 10 on the gate insulating layer 4, the flat layer 5 covering the touch signal line 11, the source 9 and the drain 10 ,
  • the sidewalls and bottom of the groove on the surface of the wire 11 are in contact with each other to realize the connection with the touch signal wire 11, which
  • the touch signal line 11 of this embodiment may adopt a three-layer structure of Ti/Al/Ti. As shown in FIG. 3, when the touch signal line 11 is manufactured, a light shielding layer 6, a buffer layer 2, and an active layer are formed. 7. The first titanium layer 21, the aluminum layer 22, and the second titanium layer 23 are formed on the base substrate 1 of the interlayer insulating layer 3, the gate electrode 8, and the gate insulating layer 4. The first titanium layer 21, the aluminum layer 22 and The second titanium layer 23 constitutes a conductive layer; as shown in FIG. 4, a photoresist 24 is formed on the first titanium layer 21, and the photoresist 24 is exposed using a gray tone mask or a halftone mask.
  • a photoresist completely reserved area, a photoresist partially reserved area, and a photoresist removal area are formed, and the photoresist removal area corresponds to the removal of the touch signal line 11, the source electrode 9 and the drain electrode 10.
  • the photoresist partially reserved area corresponds to the groove
  • the photoresist fully reserved area corresponds to the source 9 and the drain 10; as shown in FIG.
  • the photoresist The conductive layer in the glue removal area is etched to form the transition pattern of the touch signal line 11, the source electrode 9 and the drain electrode 10; the photoresist in the partially reserved area of the photoresist is removed; The conductive layer in the partially reserved area of the resist is etched to form the touch signal line 11; the photoresist in the completely reserved area of the photoresist is removed.
  • the conductive layer in the photoresist removal area and the conductive layer in the photoresist partly reserved area may be etched once, for example, dry etching is used to form the source 9 and the conductive layer.
  • the drain 10 and the touch signal line 11 are described.
  • the position of the gray tone mask or halftone mask corresponding to the groove is in a half-exposure form, and the gray tone mask or halftone mask can be formed at the groove
  • the first thickness of the photoresist partly reserved area can be adjusted (for example, by adjusting the exposure energy, etc.) so that when the conductive layer of the photoresist partly reserved area is etched, only up to
  • the second titanium layer 23 is shown in FIG. 5.
  • the second thickness of the photoresist completely reserved area formed at the source 9 and the drain 10 through the gray tone mask or halftone mask, the first thickness is less than the second thickness, as shown in FIG. 4 Show.
  • an acrylic material layer is coated on the base substrate 1 on which the touch signal line 11 is formed, and the acrylic material layer is patterned to form a via hole exposing the groove, and then the via hole is formed.
  • the acrylic material layer is cured to form a flat layer 5;
  • a transparent conductive layer such as an indium tin oxide (ITO) layer
  • ITO indium tin oxide
  • a transparent conductive layer is formed on the flat layer 5 by ion sputtering, and the transparent conductive layer is patterned to form a touch
  • the electrodes 12 and the touch electrodes 12 are in contact with the grooves of the touch signal lines 11 through the via holes penetrating the planar layer 5 to realize the connection between the touch signal lines 11 and the touch electrodes 12.
  • the touch display substrate shown in FIG. 2 can be obtained.
  • the technical solution of the present disclosure can increase the contact area of the touch signal 11 and the touch electrode 12, and reduce the contact resistance between the touch signal 11 and the touch electrode 12 Optimize the connection between the touch signal 11 and the touch electrode 12 to avoid poor sensing.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种基板及其制作方法、触控显示装置,属于触控技术领域。其中,基板,包括衬底基板(1)和依次位于所述衬底基板(1)上的第一导电图形、绝缘层和第二导电图形,所述第二导电图形通过贯穿所述绝缘层的过孔与所述第一导电图形连接,所述第一导电图形远离所述衬底基板(1)的一侧表面上形成有凹槽,所述第二导电图形与所述凹槽的底部和侧壁相接触。

Description

基板及其制作方法、触控显示装置
相关申请的交叉引用
本申请主张在2019年3月19日在中国提交的中国专利申请号No.201910207431.8的优先权,其全部内容通过引用包含于此。
技术领域
本公开涉及触控技术领域,特别是指一种基板及其制作方法、触控显示装置。
背景技术
相关技术中的触控显示产品中触控电极与触控信号线的接触方式是触控电极通过贯穿平坦层的过孔与触控电极线表面接触,随着触控显示产品的分辨率越来越高,像素密度越来越大,触控电极与触控信号线的接触面积也越来越小,使得触控电极与触控信号线之间的接触电阻过大,易产生传感不良。
发明内容
本公开实施例提供了提供一种基板,包括衬底基板和依次位于所述衬底基板上的第一导电图形、绝缘层和第二导电图形,所述第二导电图形通过贯穿所述绝缘层的过孔与所述第一导电图形连接,所述第一导电图形远离所述衬底基板的一侧表面上形成有凹槽,所述第二导电图形与所述凹槽的底部和侧壁相接触。
进一步地,所述基板为触控基板,所述第一导电图形为触控信号线,所述第二导电图形为触控电极。
进一步地,所述第一导电图形与所述基板的薄膜晶体管的源极和漏极同层同材料设置。
进一步地,所述第一导电图形采用Ti/Al/Ti的三层结构,所述凹槽的底部暴露出所述第一导电图形底部的Ti。
本公开实施例还提供了一种触控显示装置,包括如上所述的基板。
本公开实施例还提供了一种基板的制作方法,包括:
在衬底基板上形成第一导电图形,所述第一导电图形远离所述衬底基板的一侧表面上形成有凹槽;
形成覆盖所述第一导电图形的绝缘层,所述绝缘层具有暴露出所述凹槽的过孔;
在所述绝缘层上形成第二导电图形,所述第二导电图形通过所述过孔与所述凹槽的底部和侧壁相接触。
进一步地,所述基板为触控基板,所述第一导电图形为触控信号线,所述第二导电图形为触控电极。
进一步地,所述在衬底基板上形成第一导电图形包括:
采用同一掩膜板通过一次构图工艺形成所述第一导电图形、所述基板的薄膜晶体管的源极和漏极。
进一步地,所述采用同一掩膜板通过一次构图工艺形成所述第一导电图形、所述基板的薄膜晶体管的源极和漏极包括:
形成导电层;
在所述导电层上涂覆光刻胶,利用灰色调掩膜板或半色调掩膜板对光刻胶进行曝光,显影后形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶去除区域,所述光刻胶去除区域对应除所述第一导电图形、所述源极和所述漏极之外的部分,所述光刻胶部分保留区域对应所述凹槽;
对所述光刻胶去除区域的导电层进行刻蚀,形成第一导电图形的过渡图形、所述源极和所述漏极;
去除所述光刻胶部分保留区域的光刻胶;
对所述光刻胶部分保留区域的导电层进行刻蚀,形成所述第一导电图形;
去除所述光刻胶完全保留区域的光刻胶。
进一步地,所述光刻胶完全保留区域对应所述源极和所述漏极,所述光刻胶部分保留区域的第一厚度小于所述光刻胶完全保留区域的第二厚度。
进一步地,所述第一导电图形采用Ti/Al/Ti的三层结构,所述对所述光刻胶部分保留区域的导电层进行刻蚀,包括:
调整所述光刻胶部分保留区域的第一厚度,以使得对所述光刻胶部分保留区域的导电层进行刻蚀时,仅刻蚀到所述第一导电图形底部的Ti。
进一步地,所述形成覆盖所述第一导电图形的绝缘层包括:
在形成有所述第一导电图形的衬底基板上涂覆亚克力材料层;
对所述亚克力材料层进行构图,形成暴露出所述凹槽的过孔;
对形成有所述过孔的亚克力材料层进行固化,形成所述绝缘层。
进一步地,所述在所述绝缘层上形成第二导电图形包括:
在所述绝缘层上形成透明导电层;
对透明导电层进行构图形成所述第二导电图形,所述第二导电图形通过贯穿所述绝缘层的所述过孔与所述凹槽的底部和侧壁相接触。
附图说明
图1为相关技术中的基板的结构示意图;
图2为本公开实施例基板的结构示意图;
图3为本公开实施例形成导电层后的示意图;
图4为本公开实施例对光刻胶进行曝光后的示意图;
图5为本公开实施例对导电层进行刻蚀后的示意图。
附图标记
1  衬底基板
2  缓冲层
3  层间绝缘层
4  栅绝缘层
5  平坦层
6  遮光层
7  有源层
8  栅极
9  源极
10 漏极
11 触控信号线
12 触控电极
21 第一钛层
22 铝层
23 第二钛层
24 光刻胶
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
图1为相关技术中的基板的结构示意图,如图1所示,相关技术中的触控显示基板包括:衬底基板1、位于衬底基板1上的遮光层6,覆盖遮光层6的缓冲层2,位于缓冲层2上的有源层7,覆盖有源层7的层间绝缘层3,位于层间绝缘层3上的栅极8,覆盖栅极8的栅绝缘层4,位于栅绝缘层4上的触控信号线11、源极9和漏极10,覆盖触控信号线11、源极9和漏极10的平坦层5,位于平坦层5上的触控电极12,触控电极12通过贯穿平坦层5的过孔与触控信号线11连接。
如图1所示,触控电极12与触控信号线11仅是表面接触,随着触控显示产品的分辨率越来越高,像素密度越来越大,触控电极12与触控信号线11的接触面积也越来越小,使得触控电极12与触控信号线11之间的接触电阻过大,易产生传感不良。
本公开的实施例针对上述问题,提供一种基板及其制作方法、触控显示装置,能够优化基板的电学性能,避免出现传感不良。
本公开实施例提供一种基板,包括衬底基板和依次位于所述衬底基板上的第一导电图形、绝缘层和第二导电图形,所述第二导电图形通过贯穿所述绝缘层的过孔与所述第一导电图形连接,所述第一导电图形远离所述衬底基板的一侧表面上形成有凹槽,所述第二导电图形与所述凹槽的底部和侧壁相接触。
本实施例中,第一导电图形远离衬底基板的一侧表面上形成有凹槽,第二导电图形与凹槽的底部和侧壁相接触,这样能够增加第一导电图形与第二 导电图形的接触面积,降低第一导电图形与第二导电图形的接触电阻,优化异层的第一导电图形与第二导电图形之间的连接状况,保证基板的电学性能,避免出现传感不良。
其中,上述基板可以是触控基板,也可以是显示基板,还可以是触控显示基板。在上述基板为显示基板时,第一导电图形和第二导电图形可以为显示基板上任两个异层设置的导电图形,比如,第一导电图形可以为薄膜晶体管的漏极,第二导电图形可以为OLED显示基板的阳极,这样能够优化薄膜晶体管的漏极与OLED显示基板的阳极之间的连接情况,避免出现显示不良。在上述基板为触控基板时,所述第一导电图形可以为触控信号线,所述第二导电图形可以为触控电极,这样能够优化触控信号线与触控电极之间的连接情况,避免出现传感不良。
进一步地,在第一导电图形为触控信号线时,所述第一导电图形与所述基板的薄膜晶体管的源极和漏极同层同材料设置,这样可以通过一次构图工艺同时形成第一导电图形、基板的薄膜晶体管的源极和漏极,能够节省基板的构图工艺的次数,降低基板的生产成本。
为了保证第一导电图形的性能,所述第一导电图形可以采用Ti/Al/Ti的三层结构,其中,上下两层的Ti可以防止中间的Al出现氧化,具体地,所述凹槽的底部可以暴露出所述第一导电图形底部的Ti,这样第二导电图形与上层的Ti以及中间的Al接触,能够增加第一导电图形与第二导电图形的接触面积,降低第一导电图形与第二导电图形的接触电阻,优化异层的第一导电图形与第二导电图形之间的连接状况。
本公开实施例还提供了一种触控显示装置,包括如上所述的基板。所述触控显示装置可以为:液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件,其中,所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开实施例还提供了一种基板的制作方法,包括:
在衬底基板上形成第一导电图形,所述第一导电图形远离所述衬底基板的一侧表面上形成有凹槽;
形成覆盖所述第一导电图形的绝缘层,所述绝缘层具有暴露出所述凹槽 的过孔;
在所述绝缘层上形成第二导电图形,所述第二导电图形通过所述过孔与所述凹槽的底部和侧壁相接触。
本实施例中,第一导电图形远离衬底基板的一侧表面上形成有凹槽,第二导电图形与凹槽的底部和侧壁相接触,这样能够增加第一导电图形与第二导电图形的接触面积,降低第一导电图形与第二导电图形的接触电阻,优化异层的第一导电图形与第二导电图形之间的连接状况,保证基板的电学性能,避免出现传感不良。
其中,上述基板可以是触控基板,也可以是显示基板,还可以是触控显示基板。在上述基板为显示基板时,第一导电图形和第二导电图形可以为显示基板上任两个异层设置的导电图形,比如,第一导电图形可以为薄膜晶体管的漏极,第二导电图形可以为OLED显示基板的阳极,这样能够优化薄膜晶体管的漏极与OLED显示基板的阳极之间的连接情况,避免出现显示不良。在上述基板为触控基板时,所述第一导电图形可以为触控信号线,所述第二导电图形可以为触控电极,这样能够优化触控信号线与触控电极之间的连接情况,避免出现传感不良。
进一步地,在第一导电图形为触控信号线时,所述第一导电图形与所述基板的薄膜晶体管的源极和漏极同层同材料设置,所述在衬底基板上形成第一导电图形包括:
利用同一掩膜板通过一次构图工艺形成所述第一导电图形、所述基板的薄膜晶体管的源极和漏极。这样可以通过一次构图工艺同时形成第一导电图形、基板的薄膜晶体管的源极和漏极,能够节省基板的构图工艺的次数,降低基板的生产成本。
一具体示例中,所述利用同一掩膜板通过一次构图工艺形成所述第一导电图形、所述基板的薄膜晶体管的源极和漏极包括:
形成导电层;
在所述导电层上涂覆光刻胶,利用灰色调掩膜板或半色调掩膜板对光刻胶进行曝光,显影后形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶去除区域,所述光刻胶去除区域对应除所述第一导电图形、所述源极和所 述漏极之外的部分,所述光刻胶部分保留区域对应所述凹槽;
对所述光刻胶去除区域的导电层进行刻蚀,形成第一导电图形的过渡图形、所述源极和所述漏极;
去除所述光刻胶部分保留区域的光刻胶;
对所述光刻胶部分保留区域的导电层进行刻蚀,形成所述第一导电图形;
去除所述光刻胶完全保留区域的光刻胶。
一具体示例中,所述光刻胶完全保留区域对应所述源极和所述漏极,所述光刻胶部分保留区域的第一厚度小于所述光刻胶完全保留区域的第二厚度。
一具体示例中,所述第一导电图形采用Ti/Al/Ti的三层结构,所述对所述光刻胶部分保留区域的导电层进行刻蚀,包括:
调整所述光刻胶部分保留区域的第一厚度,以使得对所述光刻胶部分保留区域的导电层进行刻蚀时,仅刻蚀到所述第一导电图形底部的Ti。
一具体示例中,所述形成覆盖所述第一导电图形的绝缘层包括:
在形成有所述第一导电图形的衬底基板上涂覆亚克力材料层;
对所述亚克力材料层进行构图,形成暴露出所述凹槽的过孔;
对形成有所述过孔的亚克力材料层进行固化,形成所述绝缘层。
一具体示例中,所述在所述绝缘层上形成第二导电图形包括:
在所述绝缘层上形成透明导电层;
对透明导电层进行构图形成所述第二导电图形,所述第二导电图形通过贯穿所述绝缘层的所述过孔与所述凹槽的底部和侧壁相接触。
下面结合附图以及具体的实施例对本公开的技术方案进行进一步介绍:
以本实施例的基板为触控基板为例,图2为本公开实施例基板的结构示意图,如图2所示,本实施例的触控显示基板包括:衬底基板1、位于衬底基板1上的遮光层6,覆盖遮光层6的缓冲层2,位于缓冲层2上的有源层7,覆盖有源层7的层间绝缘层3,位于层间绝缘层3上的栅极8,覆盖栅极8的栅绝缘层4,位于栅绝缘层4上的触控信号线11、源极9和漏极10,覆盖触控信号线11、源极9和漏极10的平坦层5,位于平坦层5上的触控电极12,其中,触控信号线11远离衬底基板1的一侧表面上设置有凹槽,触控电极12通过贯穿平坦层5的过孔与触控信号线11表面的凹槽的侧壁和底部均接触, 实现与触控信号线11的连接,这样可以增加触控信号11与触控电极12的接触面积,降低触控信号11与触控电极12的接触电阻,优化触控信号11与触控电极12的之间的连接状况,避免出现传感不良。
本实施例的触控信号线11可以采用Ti/Al/Ti的三层结构,如图3所示,在制作触控信号线11时,在形成有遮光层6,缓冲层2,有源层7,层间绝缘层3,栅极8,栅绝缘层4的衬底基板1上形成第一钛层21、铝层22和第二钛层23,由第一钛层21、铝层22和第二钛层23组成导电层;如图4所示,在第一钛层21上形成光刻胶24,利用灰色调掩膜板或半色调掩膜板对光刻胶24进行曝光,显影后形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶去除区域,所述光刻胶去除区域对应除所述触控信号线11、所述源极9和所述漏极10之外的部分,所述光刻胶部分保留区域对应所述凹槽,所述光刻胶完全保留区域对应所述源极9和所述漏极10;如图5所示,对所述光刻胶去除区域的导电层进行刻蚀,形成触控信号线11的过渡图形、所述源极9和所述漏极10;去除所述光刻胶部分保留区域的光刻胶;对所述光刻胶部分保留区域的导电层进行刻蚀,形成触控信号线11;去除所述光刻胶完全保留区域的光刻胶。在一些实施例中,可以对所述光刻胶去除区域的导电层和所述光刻胶部分保留区域的导电层进行一次刻蚀,例如,采用干法蚀刻,形成所述源极9、所述漏极10和触控信号线11。
其中,所述灰色调掩膜板或半色调掩膜板对应于所述凹槽的位置为半曝光形式,通过该灰色调掩膜板或半色调掩膜板,在所述凹槽处可以形成第一厚度的所述光刻胶部分保留区域,可以调整该第一厚度(例如通过调整曝光能量等)以使得对所述光刻胶部分保留区域的导电层进行刻蚀时,仅刻蚀到第二钛层23,如图5所示。同时,通过灰色调掩膜板或半色调掩膜板在源极9、漏极10处形成的第二厚度的光刻胶完全保留区域,所述第一厚度小于第二厚度,如图4所示。
之后在形成有触控信号线11的衬底基板1上涂覆亚克力材料层,对所述亚克力材料层进行构图,形成暴露出所述凹槽的过孔,再对形成有所述过孔的亚克力材料层进行固化,形成平坦层5;
之后在平坦层5上形成透明导电层(如氧化铟锡(indium tin oxide,ITO) 层),例如,通过离子溅射在平坦层5上形成透明导电层,对透明导电层进行构图形成触控电极12,触控电极12通过贯穿平坦层5的过孔与触控信号线11的凹槽相接触,实现触控信号线11与触控电极12的连接。
经过上述步骤即可得到如图2所示的触控显示基板,本公开的技术方案可以增加触控信号11与触控电极12的接触面积,降低触控信号11与触控电极12的接触电阻,优化触控信号11与触控电极12的之间的连接状况,避免出现传感不良。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
可以理解,当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”,或者可以存在中间元件。
以上所述的是本公开的可选实施方式,应当指出对于本技术领域的普通人员来说,在不脱离本公开所述的原理前提下还可以作出若干改进和润饰,这些改进和润饰也在本公开的保护范围内。
术人员来说,在不脱离本公开所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本公开的保护范围。

Claims (13)

  1. 一种基板,包括衬底基板和依次位于所述衬底基板上的第一导电图形、绝缘层和第二导电图形,所述第二导电图形通过贯穿所述绝缘层的过孔与所述第一导电图形连接,所述第一导电图形远离所述衬底基板的一侧表面上形成有凹槽,所述第二导电图形与所述凹槽的底部和侧壁相接触。
  2. 根据权利要求1所述的基板,其中,所述基板为触控基板,所述第一导电图形为触控信号线,所述第二导电图形为触控电极。
  3. 根据权利要求2所述的基板,其中,所述第一导电图形与所述基板的薄膜晶体管的源极和漏极同层同材料设置。
  4. 根据权利要求1所述的基板,其中,所述第一导电图形采用Ti/Al/Ti的三层结构,所述凹槽的底部暴露出所述第一导电图形底部的Ti。
  5. 一种触控显示装置,包括如权利要求1-4中任一项所述的基板。
  6. 一种基板的制作方法,包括:
    在衬底基板上形成第一导电图形,所述第一导电图形远离所述衬底基板的一侧表面上形成有凹槽;
    形成覆盖所述第一导电图形的绝缘层,所述绝缘层具有暴露出所述凹槽的过孔;
    在所述绝缘层上形成第二导电图形,所述第二导电图形通过所述过孔与所述凹槽的底部和侧壁相接触。
  7. 根据权利要求6所述的基板的制作方法,其中,所述基板为触控基板,所述第一导电图形为触控信号线,所述第二导电图形为触控电极。
  8. 根据权利要求7所述的基板的制作方法,其中,所述在衬底基板上形成第一导电图形包括:
    采用同一掩膜板通过一次构图工艺形成所述第一导电图形、所述基板的薄膜晶体管的源极和漏极。
  9. 根据权利要求8所述的基板的制作方法,其中,所述采用同一掩膜板通过一次构图工艺形成所述第一导电图形、所述基板的薄膜晶体管的源极和漏极包括:
    形成导电层;
    在所述导电层上涂覆光刻胶,利用灰色调掩膜板或半色调掩膜板对光刻胶进行曝光,显影后形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶去除区域,所述光刻胶去除区域对应除所述第一导电图形、所述源极和所述漏极之外的部分,所述光刻胶部分保留区域对应所述凹槽;
    对所述光刻胶去除区域的导电层进行刻蚀,形成第一导电图形的过渡图形、所述源极和所述漏极;
    去除所述光刻胶部分保留区域的光刻胶;
    对所述光刻胶部分保留区域的导电层进行刻蚀,形成所述第一导电图形;
    去除所述光刻胶完全保留区域的光刻胶。
  10. 根据权利要求9所述的基板的制作方法,其中,所述光刻胶完全保留区域对应所述源极和所述漏极,所述光刻胶部分保留区域的第一厚度小于所述光刻胶完全保留区域的第二厚度。
  11. 根据权利要求9所述的基板的制作方法,其中,所述第一导电图形采用Ti/Al/Ti的三层结构,所述对所述光刻胶部分保留区域的导电层进行刻蚀,包括:
    调整所述光刻胶部分保留区域的第一厚度,以使得对所述光刻胶部分保留区域的导电层进行刻蚀时,仅刻蚀到所述第一导电图形底部的Ti。
  12. 根据权利要求6所述的基板的制作方法,其中,所述形成覆盖所述第一导电图形的绝缘层包括:
    在形成有所述第一导电图形的衬底基板上涂覆亚克力材料层;
    对所述亚克力材料层进行构图,形成暴露出所述凹槽的过孔;
    对形成有所述过孔的亚克力材料层进行固化,形成所述绝缘层。
  13. 根据权利要求6所述的基板的制作方法,其中,所述在所述绝缘层上形成第二导电图形包括:
    在所述绝缘层上形成透明导电层;
    对透明导电层进行构图形成所述第二导电图形,所述第二导电图形通过贯穿所述绝缘层的所述过孔与所述凹槽的底部和侧壁相接触。
PCT/CN2020/076942 2019-03-19 2020-02-27 基板及其制作方法、触控显示装置 WO2020186989A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910207431.8A CN109960438B (zh) 2019-03-19 2019-03-19 基板及其制作方法、触控显示装置
CN201910207431.8 2019-03-19

Publications (1)

Publication Number Publication Date
WO2020186989A1 true WO2020186989A1 (zh) 2020-09-24

Family

ID=67024509

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/076942 WO2020186989A1 (zh) 2019-03-19 2020-02-27 基板及其制作方法、触控显示装置

Country Status (2)

Country Link
CN (1) CN109960438B (zh)
WO (1) WO2020186989A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109960438B (zh) * 2019-03-19 2021-04-23 京东方科技集团股份有限公司 基板及其制作方法、触控显示装置
CN111129032A (zh) * 2019-12-19 2020-05-08 武汉华星光电技术有限公司 一种阵列基板及其制作方法
CN114093241B (zh) * 2020-08-25 2023-08-15 合肥鑫晟光电科技有限公司 驱动背板及其制作方法、显示装置
CN112987369A (zh) * 2021-02-08 2021-06-18 武汉华星光电技术有限公司 显示面板、显示面板的制备方法及显示装置
CN113193032A (zh) * 2021-04-29 2021-07-30 合肥维信诺科技有限公司 显示面板、显示装置及显示面板的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074502A (zh) * 2009-11-20 2011-05-25 乐金显示有限公司 制造阵列基板的方法
CN102983135A (zh) * 2012-12-13 2013-03-20 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN103681488A (zh) * 2013-12-16 2014-03-26 合肥京东方光电科技有限公司 阵列基板及其制作方法,显示装置
US20180248011A1 (en) * 2015-09-25 2018-08-30 Intel Corporation Semiconductor device contacts with increased contact area
CN109960438A (zh) * 2019-03-19 2019-07-02 京东方科技集团股份有限公司 基板及其制作方法、触控显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100626378B1 (ko) * 2004-06-25 2006-09-20 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
KR100764386B1 (ko) * 2006-03-20 2007-10-08 삼성전기주식회사 고온공정에 적합한 절연구조체 및 그 제조방법
CN101459181A (zh) * 2007-12-14 2009-06-17 群康科技(深圳)有限公司 薄膜晶体管基板与液晶显示装置
KR101797651B1 (ko) * 2011-06-15 2017-11-15 미래나노텍(주) 터치스크린 패널용 배선 전극 및 이를 구비하는 터치스크린 패널
KR102109166B1 (ko) * 2013-01-15 2020-05-12 삼성디스플레이 주식회사 박막 트랜지스터 및 이를 구비하는 표시 기판
CN104658973B (zh) * 2015-02-28 2017-10-24 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN105097845A (zh) * 2015-08-24 2015-11-25 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN105448935B (zh) * 2016-01-04 2018-11-30 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN105468202B (zh) * 2016-01-29 2018-09-14 上海中航光电子有限公司 阵列基板、触控显示面板及触控显示装置
CN107946342B (zh) * 2017-11-14 2020-06-16 京东方科技集团股份有限公司 柔性显示基板及其制作方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074502A (zh) * 2009-11-20 2011-05-25 乐金显示有限公司 制造阵列基板的方法
CN102983135A (zh) * 2012-12-13 2013-03-20 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN103681488A (zh) * 2013-12-16 2014-03-26 合肥京东方光电科技有限公司 阵列基板及其制作方法,显示装置
US20180248011A1 (en) * 2015-09-25 2018-08-30 Intel Corporation Semiconductor device contacts with increased contact area
CN109960438A (zh) * 2019-03-19 2019-07-02 京东方科技集团股份有限公司 基板及其制作方法、触控显示装置

Also Published As

Publication number Publication date
CN109960438A (zh) 2019-07-02
CN109960438B (zh) 2021-04-23

Similar Documents

Publication Publication Date Title
WO2020186989A1 (zh) 基板及其制作方法、触控显示装置
US11056543B2 (en) Display panel and manufacturing method thereof
WO2018209977A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
WO2020216208A1 (zh) 一种显示基板及其制作方法、显示装置
US11335870B2 (en) Display substrate and preparation method thereof, and display device
WO2015090000A1 (zh) 阵列基板及其制作方法,显示装置
US10418391B2 (en) Display substrate, manufacture method thereof, and display device
WO2019007228A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
US20190103419A1 (en) Method for manufacturing array substrate, array substrate and display apparatus
WO2014205998A1 (zh) Coa基板及其制造方法、显示装置
WO2018157814A1 (zh) 触控屏的制作方法、触控屏和显示装置
CN104020902B (zh) 一种触摸屏及显示装置
JP6049111B2 (ja) 有機薄膜トランジスタアレイ基板及びその製造方法、並びに表示装置
WO2014190657A1 (zh) 像素单元及其制备方法、阵列基板、显示装置
WO2014166150A1 (zh) 触摸面板及其制作方法、显示装置
US20210405478A1 (en) Array substrate and manufacturing method thereof, and display panel
US10651244B2 (en) Touch display panel, method for fabricating the same, and display device
WO2019218837A1 (zh) 触控面板及其制作方法、触控装置
WO2018166022A1 (zh) Tft基板的制作方法及tft基板
CN105742299A (zh) 一种像素单元及其制作方法、阵列基板及显示装置
WO2015043023A1 (zh) Tft-lcd阵列基板的制造方法、液晶面板及液晶显示器
WO2019237498A1 (zh) 一种有源矩阵有机发光二极管显示器及其制作方法
WO2016206203A1 (zh) 导电结构及其制作方法、阵列基板、显示装置
WO2015021712A1 (zh) 阵列基板及其制造方法和显示装置
US9799683B2 (en) Array substrate, preparation method thereof and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20773772

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20773772

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17/02/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20773772

Country of ref document: EP

Kind code of ref document: A1